1 /* 2 * intel TCO Watchdog Driver (Used in i82801 and i6300ESB chipsets) 3 * 4 * (c) Copyright 2006-2007 Wim Van Sebroeck <wim@iguana.be>. 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 9 * 2 of the License, or (at your option) any later version. 10 * 11 * Neither Wim Van Sebroeck nor Iguana vzw. admit liability nor 12 * provide warranty for any of this software. This material is 13 * provided "AS-IS" and at no charge. 14 * 15 * The TCO watchdog is implemented in the following I/O controller hubs: 16 * (See the intel documentation on http://developer.intel.com.) 17 * 82801AA (ICH) : document number 290655-003, 290677-014, 18 * 82801AB (ICHO) : document number 290655-003, 290677-014, 19 * 82801BA (ICH2) : document number 290687-002, 298242-027, 20 * 82801BAM (ICH2-M) : document number 290687-002, 298242-027, 21 * 82801CA (ICH3-S) : document number 290733-003, 290739-013, 22 * 82801CAM (ICH3-M) : document number 290716-001, 290718-007, 23 * 82801DB (ICH4) : document number 290744-001, 290745-020, 24 * 82801DBM (ICH4-M) : document number 252337-001, 252663-005, 25 * 82801E (C-ICH) : document number 273599-001, 273645-002, 26 * 82801EB (ICH5) : document number 252516-001, 252517-003, 27 * 82801ER (ICH5R) : document number 252516-001, 252517-003, 28 * 82801FB (ICH6) : document number 301473-002, 301474-007, 29 * 82801FR (ICH6R) : document number 301473-002, 301474-007, 30 * 82801FBM (ICH6-M) : document number 301473-002, 301474-007, 31 * 82801FW (ICH6W) : document number 301473-001, 301474-007, 32 * 82801FRW (ICH6RW) : document number 301473-001, 301474-007, 33 * 82801GB (ICH7) : document number 307013-002, 307014-009, 34 * 82801GR (ICH7R) : document number 307013-002, 307014-009, 35 * 82801GDH (ICH7DH) : document number 307013-002, 307014-009, 36 * 82801GBM (ICH7-M) : document number 307013-002, 307014-009, 37 * 82801GHM (ICH7-M DH) : document number 307013-002, 307014-009, 38 * 82801HB (ICH8) : document number 313056-003, 313057-009, 39 * 82801HR (ICH8R) : document number 313056-003, 313057-009, 40 * 82801HBM (ICH8M) : document number 313056-003, 313057-009, 41 * 82801HH (ICH8DH) : document number 313056-003, 313057-009, 42 * 82801HO (ICH8DO) : document number 313056-003, 313057-009, 43 * 82801HEM (ICH8M-E) : document number 313056-003, 313057-009, 44 * 82801IB (ICH9) : document number 316972-001, 316973-006, 45 * 82801IR (ICH9R) : document number 316972-001, 316973-006, 46 * 82801IH (ICH9DH) : document number 316972-001, 316973-006, 47 * 82801IO (ICH9DO) : document number 316972-001, 316973-006, 48 * 6300ESB (6300ESB) : document number 300641-003, 300884-010, 49 * 631xESB (631xESB) : document number 313082-001, 313075-005, 50 * 632xESB (632xESB) : document number 313082-001, 313075-005 51 */ 52 53 /* 54 * Includes, defines, variables, module parameters, ... 55 */ 56 57 /* Module and version information */ 58 #define DRV_NAME "iTCO_wdt" 59 #define DRV_VERSION "1.03" 60 #define DRV_RELDATE "30-Apr-2008" 61 #define PFX DRV_NAME ": " 62 63 /* Includes */ 64 #include <linux/module.h> /* For module specific items */ 65 #include <linux/moduleparam.h> /* For new moduleparam's */ 66 #include <linux/types.h> /* For standard types (like size_t) */ 67 #include <linux/errno.h> /* For the -ENODEV/... values */ 68 #include <linux/kernel.h> /* For printk/panic/... */ 69 #include <linux/miscdevice.h> /* For MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR) */ 70 #include <linux/watchdog.h> /* For the watchdog specific items */ 71 #include <linux/init.h> /* For __init/__exit/... */ 72 #include <linux/fs.h> /* For file operations */ 73 #include <linux/platform_device.h> /* For platform_driver framework */ 74 #include <linux/pci.h> /* For pci functions */ 75 #include <linux/ioport.h> /* For io-port access */ 76 #include <linux/spinlock.h> /* For spin_lock/spin_unlock/... */ 77 78 #include <asm/uaccess.h> /* For copy_to_user/put_user/... */ 79 #include <asm/io.h> /* For inb/outb/... */ 80 81 /* TCO related info */ 82 enum iTCO_chipsets { 83 TCO_ICH = 0, /* ICH */ 84 TCO_ICH0, /* ICH0 */ 85 TCO_ICH2, /* ICH2 */ 86 TCO_ICH2M, /* ICH2-M */ 87 TCO_ICH3, /* ICH3-S */ 88 TCO_ICH3M, /* ICH3-M */ 89 TCO_ICH4, /* ICH4 */ 90 TCO_ICH4M, /* ICH4-M */ 91 TCO_CICH, /* C-ICH */ 92 TCO_ICH5, /* ICH5 & ICH5R */ 93 TCO_6300ESB, /* 6300ESB */ 94 TCO_ICH6, /* ICH6 & ICH6R */ 95 TCO_ICH6M, /* ICH6-M */ 96 TCO_ICH6W, /* ICH6W & ICH6RW */ 97 TCO_ICH7, /* ICH7 & ICH7R */ 98 TCO_ICH7M, /* ICH7-M */ 99 TCO_ICH7MDH, /* ICH7-M DH */ 100 TCO_ICH8, /* ICH8 & ICH8R */ 101 TCO_ICH8ME, /* ICH8M-E */ 102 TCO_ICH8DH, /* ICH8DH */ 103 TCO_ICH8DO, /* ICH8DO */ 104 TCO_ICH8M, /* ICH8M */ 105 TCO_ICH9, /* ICH9 */ 106 TCO_ICH9R, /* ICH9R */ 107 TCO_ICH9DH, /* ICH9DH */ 108 TCO_ICH9DO, /* ICH9DO */ 109 TCO_631XESB, /* 631xESB/632xESB */ 110 }; 111 112 static struct { 113 char *name; 114 unsigned int iTCO_version; 115 } iTCO_chipset_info[] __devinitdata = { 116 {"ICH", 1}, 117 {"ICH0", 1}, 118 {"ICH2", 1}, 119 {"ICH2-M", 1}, 120 {"ICH3-S", 1}, 121 {"ICH3-M", 1}, 122 {"ICH4", 1}, 123 {"ICH4-M", 1}, 124 {"C-ICH", 1}, 125 {"ICH5 or ICH5R", 1}, 126 {"6300ESB", 1}, 127 {"ICH6 or ICH6R", 2}, 128 {"ICH6-M", 2}, 129 {"ICH6W or ICH6RW", 2}, 130 {"ICH7 or ICH7R", 2}, 131 {"ICH7-M", 2}, 132 {"ICH7-M DH", 2}, 133 {"ICH8 or ICH8R", 2}, 134 {"ICH8M-E", 2}, 135 {"ICH8DH", 2}, 136 {"ICH8DO", 2}, 137 {"ICH8M", 2}, 138 {"ICH9", 2}, 139 {"ICH9R", 2}, 140 {"ICH9DH", 2}, 141 {"ICH9DO", 2}, 142 {"631xESB/632xESB", 2}, 143 {NULL,0} 144 }; 145 146 #define ITCO_PCI_DEVICE(dev, data) \ 147 .vendor = PCI_VENDOR_ID_INTEL, \ 148 .device = dev, \ 149 .subvendor = PCI_ANY_ID, \ 150 .subdevice = PCI_ANY_ID, \ 151 .class = 0, \ 152 .class_mask = 0, \ 153 .driver_data = data 154 155 /* 156 * This data only exists for exporting the supported PCI ids 157 * via MODULE_DEVICE_TABLE. We do not actually register a 158 * pci_driver, because the I/O Controller Hub has also other 159 * functions that probably will be registered by other drivers. 160 */ 161 static struct pci_device_id iTCO_wdt_pci_tbl[] = { 162 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801AA_0, TCO_ICH )}, 163 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801AB_0, TCO_ICH0 )}, 164 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801BA_0, TCO_ICH2 )}, 165 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801BA_10, TCO_ICH2M )}, 166 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801CA_0, TCO_ICH3 )}, 167 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801CA_12, TCO_ICH3M )}, 168 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801DB_0, TCO_ICH4 )}, 169 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801DB_12, TCO_ICH4M )}, 170 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801E_0, TCO_CICH )}, 171 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801EB_0, TCO_ICH5 )}, 172 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ESB_1, TCO_6300ESB)}, 173 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH6_0, TCO_ICH6 )}, 174 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH6_1, TCO_ICH6M )}, 175 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH6_2, TCO_ICH6W )}, 176 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH7_0, TCO_ICH7 )}, 177 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH7_1, TCO_ICH7M )}, 178 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH7_31, TCO_ICH7MDH)}, 179 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH8_0, TCO_ICH8 )}, 180 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH8_1, TCO_ICH8ME )}, 181 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH8_2, TCO_ICH8DH )}, 182 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH8_3, TCO_ICH8DO )}, 183 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH8_4, TCO_ICH8M )}, 184 { ITCO_PCI_DEVICE(0x2918, TCO_ICH9 )}, 185 { ITCO_PCI_DEVICE(0x2916, TCO_ICH9R )}, 186 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH9_2, TCO_ICH9DH )}, 187 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH9_4, TCO_ICH9DO )}, 188 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ESB2_0, TCO_631XESB)}, 189 { ITCO_PCI_DEVICE(0x2671, TCO_631XESB)}, 190 { ITCO_PCI_DEVICE(0x2672, TCO_631XESB)}, 191 { ITCO_PCI_DEVICE(0x2673, TCO_631XESB)}, 192 { ITCO_PCI_DEVICE(0x2674, TCO_631XESB)}, 193 { ITCO_PCI_DEVICE(0x2675, TCO_631XESB)}, 194 { ITCO_PCI_DEVICE(0x2676, TCO_631XESB)}, 195 { ITCO_PCI_DEVICE(0x2677, TCO_631XESB)}, 196 { ITCO_PCI_DEVICE(0x2678, TCO_631XESB)}, 197 { ITCO_PCI_DEVICE(0x2679, TCO_631XESB)}, 198 { ITCO_PCI_DEVICE(0x267a, TCO_631XESB)}, 199 { ITCO_PCI_DEVICE(0x267b, TCO_631XESB)}, 200 { ITCO_PCI_DEVICE(0x267c, TCO_631XESB)}, 201 { ITCO_PCI_DEVICE(0x267d, TCO_631XESB)}, 202 { ITCO_PCI_DEVICE(0x267e, TCO_631XESB)}, 203 { ITCO_PCI_DEVICE(0x267f, TCO_631XESB)}, 204 { 0, }, /* End of list */ 205 }; 206 MODULE_DEVICE_TABLE (pci, iTCO_wdt_pci_tbl); 207 208 /* Address definitions for the TCO */ 209 #define TCOBASE iTCO_wdt_private.ACPIBASE + 0x60 /* TCO base address */ 210 #define SMI_EN iTCO_wdt_private.ACPIBASE + 0x30 /* SMI Control and Enable Register */ 211 212 #define TCO_RLD TCOBASE + 0x00 /* TCO Timer Reload and Current Value */ 213 #define TCOv1_TMR TCOBASE + 0x01 /* TCOv1 Timer Initial Value */ 214 #define TCO_DAT_IN TCOBASE + 0x02 /* TCO Data In Register */ 215 #define TCO_DAT_OUT TCOBASE + 0x03 /* TCO Data Out Register */ 216 #define TCO1_STS TCOBASE + 0x04 /* TCO1 Status Register */ 217 #define TCO2_STS TCOBASE + 0x06 /* TCO2 Status Register */ 218 #define TCO1_CNT TCOBASE + 0x08 /* TCO1 Control Register */ 219 #define TCO2_CNT TCOBASE + 0x0a /* TCO2 Control Register */ 220 #define TCOv2_TMR TCOBASE + 0x12 /* TCOv2 Timer Initial Value */ 221 222 /* internal variables */ 223 static unsigned long is_active; 224 static char expect_release; 225 static struct { /* this is private data for the iTCO_wdt device */ 226 unsigned int iTCO_version; /* TCO version/generation */ 227 unsigned long ACPIBASE; /* The cards ACPIBASE address (TCOBASE = ACPIBASE+0x60) */ 228 unsigned long __iomem *gcs; /* NO_REBOOT flag is Memory-Mapped GCS register bit 5 (TCO version 2) */ 229 spinlock_t io_lock; /* the lock for io operations */ 230 struct pci_dev *pdev; /* the PCI-device */ 231 } iTCO_wdt_private; 232 233 static struct platform_device *iTCO_wdt_platform_device; /* the watchdog platform device */ 234 235 /* module parameters */ 236 #define WATCHDOG_HEARTBEAT 30 /* 30 sec default heartbeat */ 237 static int heartbeat = WATCHDOG_HEARTBEAT; /* in seconds */ 238 module_param(heartbeat, int, 0); 239 MODULE_PARM_DESC(heartbeat, "Watchdog heartbeat in seconds. (2<heartbeat<39 (TCO v1) or 613 (TCO v2), default=" __MODULE_STRING(WATCHDOG_HEARTBEAT) ")"); 240 241 static int nowayout = WATCHDOG_NOWAYOUT; 242 module_param(nowayout, int, 0); 243 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); 244 245 /* iTCO Vendor Specific Support hooks */ 246 #ifdef CONFIG_ITCO_VENDOR_SUPPORT 247 extern void iTCO_vendor_pre_start(unsigned long, unsigned int); 248 extern void iTCO_vendor_pre_stop(unsigned long); 249 extern void iTCO_vendor_pre_keepalive(unsigned long, unsigned int); 250 extern void iTCO_vendor_pre_set_heartbeat(unsigned int); 251 extern int iTCO_vendor_check_noreboot_on(void); 252 #else 253 #define iTCO_vendor_pre_start(acpibase, heartbeat) {} 254 #define iTCO_vendor_pre_stop(acpibase) {} 255 #define iTCO_vendor_pre_keepalive(acpibase,heartbeat) {} 256 #define iTCO_vendor_pre_set_heartbeat(heartbeat) {} 257 #define iTCO_vendor_check_noreboot_on() 1 /* 1=check noreboot; 0=don't check */ 258 #endif 259 260 /* 261 * Some TCO specific functions 262 */ 263 264 static inline unsigned int seconds_to_ticks(int seconds) 265 { 266 /* the internal timer is stored as ticks which decrement 267 * every 0.6 seconds */ 268 return (seconds * 10) / 6; 269 } 270 271 static void iTCO_wdt_set_NO_REBOOT_bit(void) 272 { 273 u32 val32; 274 275 /* Set the NO_REBOOT bit: this disables reboots */ 276 if (iTCO_wdt_private.iTCO_version == 2) { 277 val32 = readl(iTCO_wdt_private.gcs); 278 val32 |= 0x00000020; 279 writel(val32, iTCO_wdt_private.gcs); 280 } else if (iTCO_wdt_private.iTCO_version == 1) { 281 pci_read_config_dword(iTCO_wdt_private.pdev, 0xd4, &val32); 282 val32 |= 0x00000002; 283 pci_write_config_dword(iTCO_wdt_private.pdev, 0xd4, val32); 284 } 285 } 286 287 static int iTCO_wdt_unset_NO_REBOOT_bit(void) 288 { 289 int ret = 0; 290 u32 val32; 291 292 /* Unset the NO_REBOOT bit: this enables reboots */ 293 if (iTCO_wdt_private.iTCO_version == 2) { 294 val32 = readl(iTCO_wdt_private.gcs); 295 val32 &= 0xffffffdf; 296 writel(val32, iTCO_wdt_private.gcs); 297 298 val32 = readl(iTCO_wdt_private.gcs); 299 if (val32 & 0x00000020) 300 ret = -EIO; 301 } else if (iTCO_wdt_private.iTCO_version == 1) { 302 pci_read_config_dword(iTCO_wdt_private.pdev, 0xd4, &val32); 303 val32 &= 0xfffffffd; 304 pci_write_config_dword(iTCO_wdt_private.pdev, 0xd4, val32); 305 306 pci_read_config_dword(iTCO_wdt_private.pdev, 0xd4, &val32); 307 if (val32 & 0x00000002) 308 ret = -EIO; 309 } 310 311 return ret; /* returns: 0 = OK, -EIO = Error */ 312 } 313 314 static int iTCO_wdt_start(void) 315 { 316 unsigned int val; 317 318 spin_lock(&iTCO_wdt_private.io_lock); 319 320 iTCO_vendor_pre_start(iTCO_wdt_private.ACPIBASE, heartbeat); 321 322 /* disable chipset's NO_REBOOT bit */ 323 if (iTCO_wdt_unset_NO_REBOOT_bit()) { 324 spin_unlock(&iTCO_wdt_private.io_lock); 325 printk(KERN_ERR PFX "failed to reset NO_REBOOT flag, reboot disabled by hardware\n"); 326 return -EIO; 327 } 328 329 /* Bit 11: TCO Timer Halt -> 0 = The TCO timer is enabled to count */ 330 val = inw(TCO1_CNT); 331 val &= 0xf7ff; 332 outw(val, TCO1_CNT); 333 val = inw(TCO1_CNT); 334 spin_unlock(&iTCO_wdt_private.io_lock); 335 336 if (val & 0x0800) 337 return -1; 338 return 0; 339 } 340 341 static int iTCO_wdt_stop(void) 342 { 343 unsigned int val; 344 345 spin_lock(&iTCO_wdt_private.io_lock); 346 347 iTCO_vendor_pre_stop(iTCO_wdt_private.ACPIBASE); 348 349 /* Bit 11: TCO Timer Halt -> 1 = The TCO timer is disabled */ 350 val = inw(TCO1_CNT); 351 val |= 0x0800; 352 outw(val, TCO1_CNT); 353 val = inw(TCO1_CNT); 354 355 /* Set the NO_REBOOT bit to prevent later reboots, just for sure */ 356 iTCO_wdt_set_NO_REBOOT_bit(); 357 358 spin_unlock(&iTCO_wdt_private.io_lock); 359 360 if ((val & 0x0800) == 0) 361 return -1; 362 return 0; 363 } 364 365 static int iTCO_wdt_keepalive(void) 366 { 367 spin_lock(&iTCO_wdt_private.io_lock); 368 369 iTCO_vendor_pre_keepalive(iTCO_wdt_private.ACPIBASE, heartbeat); 370 371 /* Reload the timer by writing to the TCO Timer Counter register */ 372 if (iTCO_wdt_private.iTCO_version == 2) { 373 outw(0x01, TCO_RLD); 374 } else if (iTCO_wdt_private.iTCO_version == 1) { 375 outb(0x01, TCO_RLD); 376 } 377 378 spin_unlock(&iTCO_wdt_private.io_lock); 379 return 0; 380 } 381 382 static int iTCO_wdt_set_heartbeat(int t) 383 { 384 unsigned int val16; 385 unsigned char val8; 386 unsigned int tmrval; 387 388 tmrval = seconds_to_ticks(t); 389 /* from the specs: */ 390 /* "Values of 0h-3h are ignored and should not be attempted" */ 391 if (tmrval < 0x04) 392 return -EINVAL; 393 if (((iTCO_wdt_private.iTCO_version == 2) && (tmrval > 0x3ff)) || 394 ((iTCO_wdt_private.iTCO_version == 1) && (tmrval > 0x03f))) 395 return -EINVAL; 396 397 iTCO_vendor_pre_set_heartbeat(tmrval); 398 399 /* Write new heartbeat to watchdog */ 400 if (iTCO_wdt_private.iTCO_version == 2) { 401 spin_lock(&iTCO_wdt_private.io_lock); 402 val16 = inw(TCOv2_TMR); 403 val16 &= 0xfc00; 404 val16 |= tmrval; 405 outw(val16, TCOv2_TMR); 406 val16 = inw(TCOv2_TMR); 407 spin_unlock(&iTCO_wdt_private.io_lock); 408 409 if ((val16 & 0x3ff) != tmrval) 410 return -EINVAL; 411 } else if (iTCO_wdt_private.iTCO_version == 1) { 412 spin_lock(&iTCO_wdt_private.io_lock); 413 val8 = inb(TCOv1_TMR); 414 val8 &= 0xc0; 415 val8 |= (tmrval & 0xff); 416 outb(val8, TCOv1_TMR); 417 val8 = inb(TCOv1_TMR); 418 spin_unlock(&iTCO_wdt_private.io_lock); 419 420 if ((val8 & 0x3f) != tmrval) 421 return -EINVAL; 422 } 423 424 heartbeat = t; 425 return 0; 426 } 427 428 static int iTCO_wdt_get_timeleft (int *time_left) 429 { 430 unsigned int val16; 431 unsigned char val8; 432 433 /* read the TCO Timer */ 434 if (iTCO_wdt_private.iTCO_version == 2) { 435 spin_lock(&iTCO_wdt_private.io_lock); 436 val16 = inw(TCO_RLD); 437 val16 &= 0x3ff; 438 spin_unlock(&iTCO_wdt_private.io_lock); 439 440 *time_left = (val16 * 6) / 10; 441 } else if (iTCO_wdt_private.iTCO_version == 1) { 442 spin_lock(&iTCO_wdt_private.io_lock); 443 val8 = inb(TCO_RLD); 444 val8 &= 0x3f; 445 spin_unlock(&iTCO_wdt_private.io_lock); 446 447 *time_left = (val8 * 6) / 10; 448 } else 449 return -EINVAL; 450 return 0; 451 } 452 453 /* 454 * /dev/watchdog handling 455 */ 456 457 static int iTCO_wdt_open (struct inode *inode, struct file *file) 458 { 459 /* /dev/watchdog can only be opened once */ 460 if (test_and_set_bit(0, &is_active)) 461 return -EBUSY; 462 463 /* 464 * Reload and activate timer 465 */ 466 iTCO_wdt_keepalive(); 467 iTCO_wdt_start(); 468 return nonseekable_open(inode, file); 469 } 470 471 static int iTCO_wdt_release (struct inode *inode, struct file *file) 472 { 473 /* 474 * Shut off the timer. 475 */ 476 if (expect_release == 42) { 477 iTCO_wdt_stop(); 478 } else { 479 printk(KERN_CRIT PFX "Unexpected close, not stopping watchdog!\n"); 480 iTCO_wdt_keepalive(); 481 } 482 clear_bit(0, &is_active); 483 expect_release = 0; 484 return 0; 485 } 486 487 static ssize_t iTCO_wdt_write (struct file *file, const char __user *data, 488 size_t len, loff_t * ppos) 489 { 490 /* See if we got the magic character 'V' and reload the timer */ 491 if (len) { 492 if (!nowayout) { 493 size_t i; 494 495 /* note: just in case someone wrote the magic character 496 * five months ago... */ 497 expect_release = 0; 498 499 /* scan to see whether or not we got the magic character */ 500 for (i = 0; i != len; i++) { 501 char c; 502 if (get_user(c, data+i)) 503 return -EFAULT; 504 if (c == 'V') 505 expect_release = 42; 506 } 507 } 508 509 /* someone wrote to us, we should reload the timer */ 510 iTCO_wdt_keepalive(); 511 } 512 return len; 513 } 514 515 static int iTCO_wdt_ioctl (struct inode *inode, struct file *file, 516 unsigned int cmd, unsigned long arg) 517 { 518 int new_options, retval = -EINVAL; 519 int new_heartbeat; 520 void __user *argp = (void __user *)arg; 521 int __user *p = argp; 522 static struct watchdog_info ident = { 523 .options = WDIOF_SETTIMEOUT | 524 WDIOF_KEEPALIVEPING | 525 WDIOF_MAGICCLOSE, 526 .firmware_version = 0, 527 .identity = DRV_NAME, 528 }; 529 530 switch (cmd) { 531 case WDIOC_GETSUPPORT: 532 return copy_to_user(argp, &ident, 533 sizeof (ident)) ? -EFAULT : 0; 534 535 case WDIOC_GETSTATUS: 536 case WDIOC_GETBOOTSTATUS: 537 return put_user(0, p); 538 539 case WDIOC_KEEPALIVE: 540 iTCO_wdt_keepalive(); 541 return 0; 542 543 case WDIOC_SETOPTIONS: 544 { 545 if (get_user(new_options, p)) 546 return -EFAULT; 547 548 if (new_options & WDIOS_DISABLECARD) { 549 iTCO_wdt_stop(); 550 retval = 0; 551 } 552 553 if (new_options & WDIOS_ENABLECARD) { 554 iTCO_wdt_keepalive(); 555 iTCO_wdt_start(); 556 retval = 0; 557 } 558 559 return retval; 560 } 561 562 case WDIOC_SETTIMEOUT: 563 { 564 if (get_user(new_heartbeat, p)) 565 return -EFAULT; 566 567 if (iTCO_wdt_set_heartbeat(new_heartbeat)) 568 return -EINVAL; 569 570 iTCO_wdt_keepalive(); 571 /* Fall */ 572 } 573 574 case WDIOC_GETTIMEOUT: 575 return put_user(heartbeat, p); 576 577 case WDIOC_GETTIMELEFT: 578 { 579 int time_left; 580 581 if (iTCO_wdt_get_timeleft(&time_left)) 582 return -EINVAL; 583 584 return put_user(time_left, p); 585 } 586 587 default: 588 return -ENOTTY; 589 } 590 } 591 592 /* 593 * Kernel Interfaces 594 */ 595 596 static const struct file_operations iTCO_wdt_fops = { 597 .owner = THIS_MODULE, 598 .llseek = no_llseek, 599 .write = iTCO_wdt_write, 600 .ioctl = iTCO_wdt_ioctl, 601 .open = iTCO_wdt_open, 602 .release = iTCO_wdt_release, 603 }; 604 605 static struct miscdevice iTCO_wdt_miscdev = { 606 .minor = WATCHDOG_MINOR, 607 .name = "watchdog", 608 .fops = &iTCO_wdt_fops, 609 }; 610 611 /* 612 * Init & exit routines 613 */ 614 615 static int __devinit iTCO_wdt_init(struct pci_dev *pdev, const struct pci_device_id *ent, struct platform_device *dev) 616 { 617 int ret; 618 u32 base_address; 619 unsigned long RCBA; 620 unsigned long val32; 621 622 /* 623 * Find the ACPI/PM base I/O address which is the base 624 * for the TCO registers (TCOBASE=ACPIBASE + 0x60) 625 * ACPIBASE is bits [15:7] from 0x40-0x43 626 */ 627 pci_read_config_dword(pdev, 0x40, &base_address); 628 base_address &= 0x0000ff80; 629 if (base_address == 0x00000000) { 630 /* Something's wrong here, ACPIBASE has to be set */ 631 printk(KERN_ERR PFX "failed to get TCOBASE address\n"); 632 pci_dev_put(pdev); 633 return -ENODEV; 634 } 635 iTCO_wdt_private.iTCO_version = iTCO_chipset_info[ent->driver_data].iTCO_version; 636 iTCO_wdt_private.ACPIBASE = base_address; 637 iTCO_wdt_private.pdev = pdev; 638 639 /* Get the Memory-Mapped GCS register, we need it for the NO_REBOOT flag (TCO v2) */ 640 /* To get access to it you have to read RCBA from PCI Config space 0xf0 641 and use it as base. GCS = RCBA + ICH6_GCS(0x3410). */ 642 if (iTCO_wdt_private.iTCO_version == 2) { 643 pci_read_config_dword(pdev, 0xf0, &base_address); 644 RCBA = base_address & 0xffffc000; 645 iTCO_wdt_private.gcs = ioremap((RCBA + 0x3410),4); 646 } 647 648 /* Check chipset's NO_REBOOT bit */ 649 if (iTCO_wdt_unset_NO_REBOOT_bit() && iTCO_vendor_check_noreboot_on()) { 650 printk(KERN_ERR PFX "failed to reset NO_REBOOT flag, reboot disabled by hardware\n"); 651 ret = -ENODEV; /* Cannot reset NO_REBOOT bit */ 652 goto out; 653 } 654 655 /* Set the NO_REBOOT bit to prevent later reboots, just for sure */ 656 iTCO_wdt_set_NO_REBOOT_bit(); 657 658 /* Set the TCO_EN bit in SMI_EN register */ 659 if (!request_region(SMI_EN, 4, "iTCO_wdt")) { 660 printk(KERN_ERR PFX "I/O address 0x%04lx already in use\n", 661 SMI_EN ); 662 ret = -EIO; 663 goto out; 664 } 665 val32 = inl(SMI_EN); 666 val32 &= 0xffffdfff; /* Turn off SMI clearing watchdog */ 667 outl(val32, SMI_EN); 668 release_region(SMI_EN, 4); 669 670 /* The TCO I/O registers reside in a 32-byte range pointed to by the TCOBASE value */ 671 if (!request_region (TCOBASE, 0x20, "iTCO_wdt")) { 672 printk (KERN_ERR PFX "I/O address 0x%04lx already in use\n", 673 TCOBASE); 674 ret = -EIO; 675 goto out; 676 } 677 678 printk(KERN_INFO PFX "Found a %s TCO device (Version=%d, TCOBASE=0x%04lx)\n", 679 iTCO_chipset_info[ent->driver_data].name, 680 iTCO_chipset_info[ent->driver_data].iTCO_version, 681 TCOBASE); 682 683 /* Clear out the (probably old) status */ 684 outb(0, TCO1_STS); 685 outb(3, TCO2_STS); 686 687 /* Make sure the watchdog is not running */ 688 iTCO_wdt_stop(); 689 690 /* Check that the heartbeat value is within it's range ; if not reset to the default */ 691 if (iTCO_wdt_set_heartbeat(heartbeat)) { 692 iTCO_wdt_set_heartbeat(WATCHDOG_HEARTBEAT); 693 printk(KERN_INFO PFX "heartbeat value must be 2<heartbeat<39 (TCO v1) or 613 (TCO v2), using %d\n", 694 heartbeat); 695 } 696 697 ret = misc_register(&iTCO_wdt_miscdev); 698 if (ret != 0) { 699 printk(KERN_ERR PFX "cannot register miscdev on minor=%d (err=%d)\n", 700 WATCHDOG_MINOR, ret); 701 goto unreg_region; 702 } 703 704 printk (KERN_INFO PFX "initialized. heartbeat=%d sec (nowayout=%d)\n", 705 heartbeat, nowayout); 706 707 return 0; 708 709 unreg_region: 710 release_region (TCOBASE, 0x20); 711 out: 712 if (iTCO_wdt_private.iTCO_version == 2) 713 iounmap(iTCO_wdt_private.gcs); 714 pci_dev_put(iTCO_wdt_private.pdev); 715 iTCO_wdt_private.ACPIBASE = 0; 716 return ret; 717 } 718 719 static void __devexit iTCO_wdt_cleanup(void) 720 { 721 /* Stop the timer before we leave */ 722 if (!nowayout) 723 iTCO_wdt_stop(); 724 725 /* Deregister */ 726 misc_deregister(&iTCO_wdt_miscdev); 727 release_region(TCOBASE, 0x20); 728 if (iTCO_wdt_private.iTCO_version == 2) 729 iounmap(iTCO_wdt_private.gcs); 730 pci_dev_put(iTCO_wdt_private.pdev); 731 iTCO_wdt_private.ACPIBASE = 0; 732 } 733 734 static int __devinit iTCO_wdt_probe(struct platform_device *dev) 735 { 736 int found = 0; 737 struct pci_dev *pdev = NULL; 738 const struct pci_device_id *ent; 739 740 spin_lock_init(&iTCO_wdt_private.io_lock); 741 742 for_each_pci_dev(pdev) { 743 ent = pci_match_id(iTCO_wdt_pci_tbl, pdev); 744 if (ent) { 745 if (!(iTCO_wdt_init(pdev, ent, dev))) { 746 found++; 747 break; 748 } 749 } 750 } 751 752 if (!found) { 753 printk(KERN_INFO PFX "No card detected\n"); 754 return -ENODEV; 755 } 756 757 return 0; 758 } 759 760 static int __devexit iTCO_wdt_remove(struct platform_device *dev) 761 { 762 if (iTCO_wdt_private.ACPIBASE) 763 iTCO_wdt_cleanup(); 764 765 return 0; 766 } 767 768 static void iTCO_wdt_shutdown(struct platform_device *dev) 769 { 770 iTCO_wdt_stop(); 771 } 772 773 #define iTCO_wdt_suspend NULL 774 #define iTCO_wdt_resume NULL 775 776 static struct platform_driver iTCO_wdt_driver = { 777 .probe = iTCO_wdt_probe, 778 .remove = __devexit_p(iTCO_wdt_remove), 779 .shutdown = iTCO_wdt_shutdown, 780 .suspend = iTCO_wdt_suspend, 781 .resume = iTCO_wdt_resume, 782 .driver = { 783 .owner = THIS_MODULE, 784 .name = DRV_NAME, 785 }, 786 }; 787 788 static int __init iTCO_wdt_init_module(void) 789 { 790 int err; 791 792 printk(KERN_INFO PFX "Intel TCO WatchDog Timer Driver v%s (%s)\n", 793 DRV_VERSION, DRV_RELDATE); 794 795 err = platform_driver_register(&iTCO_wdt_driver); 796 if (err) 797 return err; 798 799 iTCO_wdt_platform_device = platform_device_register_simple(DRV_NAME, -1, NULL, 0); 800 if (IS_ERR(iTCO_wdt_platform_device)) { 801 err = PTR_ERR(iTCO_wdt_platform_device); 802 goto unreg_platform_driver; 803 } 804 805 return 0; 806 807 unreg_platform_driver: 808 platform_driver_unregister(&iTCO_wdt_driver); 809 return err; 810 } 811 812 static void __exit iTCO_wdt_cleanup_module(void) 813 { 814 platform_device_unregister(iTCO_wdt_platform_device); 815 platform_driver_unregister(&iTCO_wdt_driver); 816 printk(KERN_INFO PFX "Watchdog Module Unloaded.\n"); 817 } 818 819 module_init(iTCO_wdt_init_module); 820 module_exit(iTCO_wdt_cleanup_module); 821 822 MODULE_AUTHOR("Wim Van Sebroeck <wim@iguana.be>"); 823 MODULE_DESCRIPTION("Intel TCO WatchDog Timer Driver"); 824 MODULE_VERSION(DRV_VERSION); 825 MODULE_LICENSE("GPL"); 826 MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR); 827