1 /* 2 * intel TCO vendor specific watchdog driver support 3 * 4 * (c) Copyright 2006 Wim Van Sebroeck <wim@iguana.be>. 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 9 * 2 of the License, or (at your option) any later version. 10 * 11 * Neither Wim Van Sebroeck nor Iguana vzw. admit liability nor 12 * provide warranty for any of this software. This material is 13 * provided "AS-IS" and at no charge. 14 */ 15 16 /* 17 * Includes, defines, variables, module parameters, ... 18 */ 19 20 /* Module and version information */ 21 #define DRV_NAME "iTCO_vendor_support" 22 #define DRV_VERSION "1.01" 23 #define DRV_RELDATE "11-Nov-2006" 24 #define PFX DRV_NAME ": " 25 26 /* Includes */ 27 #include <linux/module.h> /* For module specific items */ 28 #include <linux/moduleparam.h> /* For new moduleparam's */ 29 #include <linux/types.h> /* For standard types (like size_t) */ 30 #include <linux/errno.h> /* For the -ENODEV/... values */ 31 #include <linux/kernel.h> /* For printk/panic/... */ 32 #include <linux/init.h> /* For __init/__exit/... */ 33 #include <linux/ioport.h> /* For io-port access */ 34 35 #include <asm/io.h> /* For inb/outb/... */ 36 37 /* iTCO defines */ 38 #define SMI_EN acpibase + 0x30 /* SMI Control and Enable Register */ 39 #define TCOBASE acpibase + 0x60 /* TCO base address */ 40 #define TCO1_STS TCOBASE + 0x04 /* TCO1 Status Register */ 41 42 /* List of vendor support modes */ 43 #define SUPERMICRO_OLD_BOARD 1 /* SuperMicro Pentium 3 Era 370SSE+-OEM1/P3TSSE */ 44 #define SUPERMICRO_NEW_BOARD 2 /* SuperMicro Pentium 4 / Xeon 4 / EMT64T Era Systems */ 45 46 static int vendorsupport = 0; 47 module_param(vendorsupport, int, 0); 48 MODULE_PARM_DESC(vendorsupport, "iTCO vendor specific support mode, default=0 (none), 1=SuperMicro Pent3, 2=SuperMicro Pent4+"); 49 50 /* 51 * Vendor Specific Support 52 */ 53 54 /* 55 * Vendor Support: 1 56 * Board: Super Micro Computer Inc. 370SSE+-OEM1/P3TSSE 57 * iTCO chipset: ICH2 58 * 59 * Code contributed by: R. Seretny <lkpatches@paypc.com> 60 * Documentation obtained by R. Seretny from SuperMicro Technical Support 61 * 62 * To enable Watchdog function: 63 * BIOS setup -> Power -> TCO Logic SMI Enable -> Within5Minutes 64 * This setting enables SMI to clear the watchdog expired flag. 65 * If BIOS or CPU fail which may cause SMI hang, then system will 66 * reboot. When application starts to use watchdog function, 67 * application has to take over the control from SMI. 68 * 69 * For P3TSSE, J36 jumper needs to be removed to enable the Watchdog 70 * function. 71 * 72 * Note: The system will reboot when Expire Flag is set TWICE. 73 * So, if the watchdog timer is 20 seconds, then the maximum hang 74 * time is about 40 seconds, and the minimum hang time is about 75 * 20.6 seconds. 76 */ 77 78 static void supermicro_old_pre_start(unsigned long acpibase) 79 { 80 unsigned long val32; 81 82 val32 = inl(SMI_EN); 83 val32 &= 0xffffdfff; /* Turn off SMI clearing watchdog */ 84 outl(val32, SMI_EN); /* Needed to activate watchdog */ 85 } 86 87 static void supermicro_old_pre_stop(unsigned long acpibase) 88 { 89 unsigned long val32; 90 91 val32 = inl(SMI_EN); 92 val32 &= 0x00002000; /* Turn on SMI clearing watchdog */ 93 outl(val32, SMI_EN); /* Needed to deactivate watchdog */ 94 } 95 96 static void supermicro_old_pre_keepalive(unsigned long acpibase) 97 { 98 /* Reload TCO Timer (done in iTCO_wdt_keepalive) + */ 99 /* Clear "Expire Flag" (Bit 3 of TC01_STS register) */ 100 outb(0x08, TCO1_STS); 101 } 102 103 /* 104 * Vendor Support: 2 105 * Board: Super Micro Computer Inc. P4SBx, P4DPx 106 * iTCO chipset: ICH4 107 * 108 * Code contributed by: R. Seretny <lkpatches@paypc.com> 109 * Documentation obtained by R. Seretny from SuperMicro Technical Support 110 * 111 * To enable Watchdog function: 112 * 1. BIOS 113 * For P4SBx: 114 * BIOS setup -> Advanced -> Integrated Peripherals -> Watch Dog Feature 115 * For P4DPx: 116 * BIOS setup -> Advanced -> I/O Device Configuration -> Watch Dog 117 * This setting enables or disables Watchdog function. When enabled, the 118 * default watchdog timer is set to be 5 minutes (about 4m35s). It is 119 * enough to load and run the OS. The application (service or driver) has 120 * to take over the control once OS is running up and before watchdog 121 * expires. 122 * 123 * 2. JUMPER 124 * For P4SBx: JP39 125 * For P4DPx: JP37 126 * This jumper is used for safety. Closed is enabled. This jumper 127 * prevents user enables watchdog in BIOS by accident. 128 * 129 * To enable Watch Dog function, both BIOS and JUMPER must be enabled. 130 * 131 * The documentation lists motherboards P4SBx and P4DPx series as of 132 * 20-March-2002. However, this code works flawlessly with much newer 133 * motherboards, such as my X6DHR-8G2 (SuperServer 6014H-82). 134 * 135 * The original iTCO driver as written does not actually reset the 136 * watchdog timer on these machines, as a result they reboot after five 137 * minutes. 138 * 139 * NOTE: You may leave the Watchdog function disabled in the SuperMicro 140 * BIOS to avoid a "boot-race"... This driver will enable watchdog 141 * functionality even if it's disabled in the BIOS once the /dev/watchdog 142 * file is opened. 143 */ 144 145 /* I/O Port's */ 146 #define SM_REGINDEX 0x2e /* SuperMicro ICH4+ Register Index */ 147 #define SM_DATAIO 0x2f /* SuperMicro ICH4+ Register Data I/O */ 148 149 /* Control Register's */ 150 #define SM_CTLPAGESW 0x07 /* SuperMicro ICH4+ Control Page Switch */ 151 #define SM_CTLPAGE 0x08 /* SuperMicro ICH4+ Control Page Num */ 152 153 #define SM_WATCHENABLE 0x30 /* Watchdog enable: Bit 0: 0=off, 1=on */ 154 155 #define SM_WATCHPAGE 0x87 /* Watchdog unlock control page */ 156 157 #define SM_ENDWATCH 0xAA /* Watchdog lock control page */ 158 159 #define SM_COUNTMODE 0xf5 /* Watchdog count mode select */ 160 /* (Bit 3: 0 = seconds, 1 = minutes */ 161 162 #define SM_WATCHTIMER 0xf6 /* 8-bits, Watchdog timer counter (RW) */ 163 164 #define SM_RESETCONTROL 0xf7 /* Watchdog reset control */ 165 /* Bit 6: timer is reset by kbd interrupt */ 166 /* Bit 7: timer is reset by mouse interrupt */ 167 168 static void supermicro_new_unlock_watchdog(void) 169 { 170 outb(SM_WATCHPAGE, SM_REGINDEX); /* Write 0x87 to port 0x2e twice */ 171 outb(SM_WATCHPAGE, SM_REGINDEX); 172 173 outb(SM_CTLPAGESW, SM_REGINDEX); /* Switch to watchdog control page */ 174 outb(SM_CTLPAGE, SM_DATAIO); 175 } 176 177 static void supermicro_new_lock_watchdog(void) 178 { 179 outb(SM_ENDWATCH, SM_REGINDEX); 180 } 181 182 static void supermicro_new_pre_start(unsigned int heartbeat) 183 { 184 unsigned int val; 185 186 supermicro_new_unlock_watchdog(); 187 188 /* Watchdog timer setting needs to be in seconds*/ 189 outb(SM_COUNTMODE, SM_REGINDEX); 190 val = inb(SM_DATAIO); 191 val &= 0xF7; 192 outb(val, SM_DATAIO); 193 194 /* Write heartbeat interval to WDOG */ 195 outb (SM_WATCHTIMER, SM_REGINDEX); 196 outb((heartbeat & 255), SM_DATAIO); 197 198 /* Make sure keyboard/mouse interrupts don't interfere */ 199 outb(SM_RESETCONTROL, SM_REGINDEX); 200 val = inb(SM_DATAIO); 201 val &= 0x3f; 202 outb(val, SM_DATAIO); 203 204 /* enable watchdog by setting bit 0 of Watchdog Enable to 1 */ 205 outb(SM_WATCHENABLE, SM_REGINDEX); 206 val = inb(SM_DATAIO); 207 val |= 0x01; 208 outb(val, SM_DATAIO); 209 210 supermicro_new_lock_watchdog(); 211 } 212 213 static void supermicro_new_pre_stop(void) 214 { 215 unsigned int val; 216 217 supermicro_new_unlock_watchdog(); 218 219 /* disable watchdog by setting bit 0 of Watchdog Enable to 0 */ 220 outb(SM_WATCHENABLE, SM_REGINDEX); 221 val = inb(SM_DATAIO); 222 val &= 0xFE; 223 outb(val, SM_DATAIO); 224 225 supermicro_new_lock_watchdog(); 226 } 227 228 static void supermicro_new_pre_set_heartbeat(unsigned int heartbeat) 229 { 230 supermicro_new_unlock_watchdog(); 231 232 /* reset watchdog timeout to heartveat value */ 233 outb(SM_WATCHTIMER, SM_REGINDEX); 234 outb((heartbeat & 255), SM_DATAIO); 235 236 supermicro_new_lock_watchdog(); 237 } 238 239 /* 240 * Generic Support Functions 241 */ 242 243 void iTCO_vendor_pre_start(unsigned long acpibase, 244 unsigned int heartbeat) 245 { 246 if (vendorsupport == SUPERMICRO_OLD_BOARD) 247 supermicro_old_pre_start(acpibase); 248 else if (vendorsupport == SUPERMICRO_NEW_BOARD) 249 supermicro_new_pre_start(heartbeat); 250 } 251 EXPORT_SYMBOL(iTCO_vendor_pre_start); 252 253 void iTCO_vendor_pre_stop(unsigned long acpibase) 254 { 255 if (vendorsupport == SUPERMICRO_OLD_BOARD) 256 supermicro_old_pre_stop(acpibase); 257 else if (vendorsupport == SUPERMICRO_NEW_BOARD) 258 supermicro_new_pre_stop(); 259 } 260 EXPORT_SYMBOL(iTCO_vendor_pre_stop); 261 262 void iTCO_vendor_pre_keepalive(unsigned long acpibase, unsigned int heartbeat) 263 { 264 if (vendorsupport == SUPERMICRO_OLD_BOARD) 265 supermicro_old_pre_keepalive(acpibase); 266 else if (vendorsupport == SUPERMICRO_NEW_BOARD) 267 supermicro_new_pre_set_heartbeat(heartbeat); 268 } 269 EXPORT_SYMBOL(iTCO_vendor_pre_keepalive); 270 271 void iTCO_vendor_pre_set_heartbeat(unsigned int heartbeat) 272 { 273 if (vendorsupport == SUPERMICRO_NEW_BOARD) 274 supermicro_new_pre_set_heartbeat(heartbeat); 275 } 276 EXPORT_SYMBOL(iTCO_vendor_pre_set_heartbeat); 277 278 int iTCO_vendor_check_noreboot_on(void) 279 { 280 switch(vendorsupport) { 281 case SUPERMICRO_OLD_BOARD: 282 return 0; 283 default: 284 return 1; 285 } 286 } 287 EXPORT_SYMBOL(iTCO_vendor_check_noreboot_on); 288 289 static int __init iTCO_vendor_init_module(void) 290 { 291 printk (KERN_INFO PFX "vendor-support=%d\n", vendorsupport); 292 return 0; 293 } 294 295 static void __exit iTCO_vendor_exit_module(void) 296 { 297 printk (KERN_INFO PFX "Module Unloaded\n"); 298 } 299 300 module_init(iTCO_vendor_init_module); 301 module_exit(iTCO_vendor_exit_module); 302 303 MODULE_AUTHOR("Wim Van Sebroeck <wim@iguana.be>, R. Seretny <lkpatches@paypc.com>"); 304 MODULE_DESCRIPTION("Intel TCO Vendor Specific WatchDog Timer Driver Support"); 305 MODULE_VERSION(DRV_VERSION); 306 MODULE_LICENSE("GPL"); 307 308