1 /* 2 * intel TCO vendor specific watchdog driver support 3 * 4 * (c) Copyright 2006-2009 Wim Van Sebroeck <wim@iguana.be>. 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 9 * 2 of the License, or (at your option) any later version. 10 * 11 * Neither Wim Van Sebroeck nor Iguana vzw. admit liability nor 12 * provide warranty for any of this software. This material is 13 * provided "AS-IS" and at no charge. 14 */ 15 16 /* 17 * Includes, defines, variables, module parameters, ... 18 */ 19 20 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 21 22 /* Module and version information */ 23 #define DRV_NAME "iTCO_vendor_support" 24 #define DRV_VERSION "1.04" 25 26 /* Includes */ 27 #include <linux/module.h> /* For module specific items */ 28 #include <linux/moduleparam.h> /* For new moduleparam's */ 29 #include <linux/types.h> /* For standard types (like size_t) */ 30 #include <linux/errno.h> /* For the -ENODEV/... values */ 31 #include <linux/kernel.h> /* For printk/panic/... */ 32 #include <linux/init.h> /* For __init/__exit/... */ 33 #include <linux/ioport.h> /* For io-port access */ 34 #include <linux/io.h> /* For inb/outb/... */ 35 36 #include "iTCO_vendor.h" 37 38 /* iTCO defines */ 39 #define SMI_EN (acpibase + 0x30) /* SMI Control and Enable Register */ 40 #define TCOBASE (acpibase + 0x60) /* TCO base address */ 41 #define TCO1_STS (TCOBASE + 0x04) /* TCO1 Status Register */ 42 43 /* List of vendor support modes */ 44 /* SuperMicro Pentium 3 Era 370SSE+-OEM1/P3TSSE */ 45 #define SUPERMICRO_OLD_BOARD 1 46 /* SuperMicro Pentium 4 / Xeon 4 / EMT64T Era Systems */ 47 #define SUPERMICRO_NEW_BOARD 2 48 /* Broken BIOS */ 49 #define BROKEN_BIOS 911 50 51 static int vendorsupport; 52 module_param(vendorsupport, int, 0); 53 MODULE_PARM_DESC(vendorsupport, "iTCO vendor specific support mode, default=" 54 "0 (none), 1=SuperMicro Pent3, 2=SuperMicro Pent4+, " 55 "911=Broken SMI BIOS"); 56 57 /* 58 * Vendor Specific Support 59 */ 60 61 /* 62 * Vendor Support: 1 63 * Board: Super Micro Computer Inc. 370SSE+-OEM1/P3TSSE 64 * iTCO chipset: ICH2 65 * 66 * Code contributed by: R. Seretny <lkpatches@paypc.com> 67 * Documentation obtained by R. Seretny from SuperMicro Technical Support 68 * 69 * To enable Watchdog function: 70 * BIOS setup -> Power -> TCO Logic SMI Enable -> Within5Minutes 71 * This setting enables SMI to clear the watchdog expired flag. 72 * If BIOS or CPU fail which may cause SMI hang, then system will 73 * reboot. When application starts to use watchdog function, 74 * application has to take over the control from SMI. 75 * 76 * For P3TSSE, J36 jumper needs to be removed to enable the Watchdog 77 * function. 78 * 79 * Note: The system will reboot when Expire Flag is set TWICE. 80 * So, if the watchdog timer is 20 seconds, then the maximum hang 81 * time is about 40 seconds, and the minimum hang time is about 82 * 20.6 seconds. 83 */ 84 85 static void supermicro_old_pre_start(unsigned long acpibase) 86 { 87 unsigned long val32; 88 89 /* Bit 13: TCO_EN -> 0 = Disables TCO logic generating an SMI# */ 90 val32 = inl(SMI_EN); 91 val32 &= 0xffffdfff; /* Turn off SMI clearing watchdog */ 92 outl(val32, SMI_EN); /* Needed to activate watchdog */ 93 } 94 95 static void supermicro_old_pre_stop(unsigned long acpibase) 96 { 97 unsigned long val32; 98 99 /* Bit 13: TCO_EN -> 1 = Enables the TCO logic to generate SMI# */ 100 val32 = inl(SMI_EN); 101 val32 |= 0x00002000; /* Turn on SMI clearing watchdog */ 102 outl(val32, SMI_EN); /* Needed to deactivate watchdog */ 103 } 104 105 /* 106 * Vendor Support: 2 107 * Board: Super Micro Computer Inc. P4SBx, P4DPx 108 * iTCO chipset: ICH4 109 * 110 * Code contributed by: R. Seretny <lkpatches@paypc.com> 111 * Documentation obtained by R. Seretny from SuperMicro Technical Support 112 * 113 * To enable Watchdog function: 114 * 1. BIOS 115 * For P4SBx: 116 * BIOS setup -> Advanced -> Integrated Peripherals -> Watch Dog Feature 117 * For P4DPx: 118 * BIOS setup -> Advanced -> I/O Device Configuration -> Watch Dog 119 * This setting enables or disables Watchdog function. When enabled, the 120 * default watchdog timer is set to be 5 minutes (about 4m35s). It is 121 * enough to load and run the OS. The application (service or driver) has 122 * to take over the control once OS is running up and before watchdog 123 * expires. 124 * 125 * 2. JUMPER 126 * For P4SBx: JP39 127 * For P4DPx: JP37 128 * This jumper is used for safety. Closed is enabled. This jumper 129 * prevents user enables watchdog in BIOS by accident. 130 * 131 * To enable Watch Dog function, both BIOS and JUMPER must be enabled. 132 * 133 * The documentation lists motherboards P4SBx and P4DPx series as of 134 * 20-March-2002. However, this code works flawlessly with much newer 135 * motherboards, such as my X6DHR-8G2 (SuperServer 6014H-82). 136 * 137 * The original iTCO driver as written does not actually reset the 138 * watchdog timer on these machines, as a result they reboot after five 139 * minutes. 140 * 141 * NOTE: You may leave the Watchdog function disabled in the SuperMicro 142 * BIOS to avoid a "boot-race"... This driver will enable watchdog 143 * functionality even if it's disabled in the BIOS once the /dev/watchdog 144 * file is opened. 145 */ 146 147 /* I/O Port's */ 148 #define SM_REGINDEX 0x2e /* SuperMicro ICH4+ Register Index */ 149 #define SM_DATAIO 0x2f /* SuperMicro ICH4+ Register Data I/O */ 150 151 /* Control Register's */ 152 #define SM_CTLPAGESW 0x07 /* SuperMicro ICH4+ Control Page Switch */ 153 #define SM_CTLPAGE 0x08 /* SuperMicro ICH4+ Control Page Num */ 154 155 #define SM_WATCHENABLE 0x30 /* Watchdog enable: Bit 0: 0=off, 1=on */ 156 157 #define SM_WATCHPAGE 0x87 /* Watchdog unlock control page */ 158 159 #define SM_ENDWATCH 0xAA /* Watchdog lock control page */ 160 161 #define SM_COUNTMODE 0xf5 /* Watchdog count mode select */ 162 /* (Bit 3: 0 = seconds, 1 = minutes */ 163 164 #define SM_WATCHTIMER 0xf6 /* 8-bits, Watchdog timer counter (RW) */ 165 166 #define SM_RESETCONTROL 0xf7 /* Watchdog reset control */ 167 /* Bit 6: timer is reset by kbd interrupt */ 168 /* Bit 7: timer is reset by mouse interrupt */ 169 170 static void supermicro_new_unlock_watchdog(void) 171 { 172 /* Write 0x87 to port 0x2e twice */ 173 outb(SM_WATCHPAGE, SM_REGINDEX); 174 outb(SM_WATCHPAGE, SM_REGINDEX); 175 /* Switch to watchdog control page */ 176 outb(SM_CTLPAGESW, SM_REGINDEX); 177 outb(SM_CTLPAGE, SM_DATAIO); 178 } 179 180 static void supermicro_new_lock_watchdog(void) 181 { 182 outb(SM_ENDWATCH, SM_REGINDEX); 183 } 184 185 static void supermicro_new_pre_start(unsigned int heartbeat) 186 { 187 unsigned int val; 188 189 supermicro_new_unlock_watchdog(); 190 191 /* Watchdog timer setting needs to be in seconds*/ 192 outb(SM_COUNTMODE, SM_REGINDEX); 193 val = inb(SM_DATAIO); 194 val &= 0xF7; 195 outb(val, SM_DATAIO); 196 197 /* Write heartbeat interval to WDOG */ 198 outb(SM_WATCHTIMER, SM_REGINDEX); 199 outb((heartbeat & 255), SM_DATAIO); 200 201 /* Make sure keyboard/mouse interrupts don't interfere */ 202 outb(SM_RESETCONTROL, SM_REGINDEX); 203 val = inb(SM_DATAIO); 204 val &= 0x3f; 205 outb(val, SM_DATAIO); 206 207 /* enable watchdog by setting bit 0 of Watchdog Enable to 1 */ 208 outb(SM_WATCHENABLE, SM_REGINDEX); 209 val = inb(SM_DATAIO); 210 val |= 0x01; 211 outb(val, SM_DATAIO); 212 213 supermicro_new_lock_watchdog(); 214 } 215 216 static void supermicro_new_pre_stop(void) 217 { 218 unsigned int val; 219 220 supermicro_new_unlock_watchdog(); 221 222 /* disable watchdog by setting bit 0 of Watchdog Enable to 0 */ 223 outb(SM_WATCHENABLE, SM_REGINDEX); 224 val = inb(SM_DATAIO); 225 val &= 0xFE; 226 outb(val, SM_DATAIO); 227 228 supermicro_new_lock_watchdog(); 229 } 230 231 static void supermicro_new_pre_set_heartbeat(unsigned int heartbeat) 232 { 233 supermicro_new_unlock_watchdog(); 234 235 /* reset watchdog timeout to heartveat value */ 236 outb(SM_WATCHTIMER, SM_REGINDEX); 237 outb((heartbeat & 255), SM_DATAIO); 238 239 supermicro_new_lock_watchdog(); 240 } 241 242 /* 243 * Vendor Support: 911 244 * Board: Some Intel ICHx based motherboards 245 * iTCO chipset: ICH7+ 246 * 247 * Some Intel motherboards have a broken BIOS implementation: i.e. 248 * the SMI handler clear's the TIMEOUT bit in the TC01_STS register 249 * and does not reload the time. Thus the TCO watchdog does not reboot 250 * the system. 251 * 252 * These are the conclusions of Andriy Gapon <avg@icyb.net.ua> after 253 * debugging: the SMI handler is quite simple - it tests value in 254 * TCO1_CNT against 0x800, i.e. checks TCO_TMR_HLT. If the bit is set 255 * the handler goes into an infinite loop, apparently to allow the 256 * second timeout and reboot. Otherwise it simply clears TIMEOUT bit 257 * in TCO1_STS and that's it. 258 * So the logic seems to be reversed, because it is hard to see how 259 * TIMEOUT can get set to 1 and SMI generated when TCO_TMR_HLT is set 260 * (other than a transitional effect). 261 * 262 * The only fix found to get the motherboard(s) to reboot is to put 263 * the glb_smi_en bit to 0. This is a dirty hack that bypasses the 264 * broken code by disabling Global SMI. 265 * 266 * WARNING: globally disabling SMI could possibly lead to dramatic 267 * problems, especially on laptops! I.e. various ACPI things where 268 * SMI is used for communication between OS and firmware. 269 * 270 * Don't use this fix if you don't need to!!! 271 */ 272 273 static void broken_bios_start(unsigned long acpibase) 274 { 275 unsigned long val32; 276 277 val32 = inl(SMI_EN); 278 /* Bit 13: TCO_EN -> 0 = Disables TCO logic generating an SMI# 279 Bit 0: GBL_SMI_EN -> 0 = No SMI# will be generated by ICH. */ 280 val32 &= 0xffffdffe; 281 outl(val32, SMI_EN); 282 } 283 284 static void broken_bios_stop(unsigned long acpibase) 285 { 286 unsigned long val32; 287 288 val32 = inl(SMI_EN); 289 /* Bit 13: TCO_EN -> 1 = Enables TCO logic generating an SMI# 290 Bit 0: GBL_SMI_EN -> 1 = Turn global SMI on again. */ 291 val32 |= 0x00002001; 292 outl(val32, SMI_EN); 293 } 294 295 /* 296 * Generic Support Functions 297 */ 298 299 void iTCO_vendor_pre_start(unsigned long acpibase, 300 unsigned int heartbeat) 301 { 302 switch (vendorsupport) { 303 case SUPERMICRO_OLD_BOARD: 304 supermicro_old_pre_start(acpibase); 305 break; 306 case SUPERMICRO_NEW_BOARD: 307 supermicro_new_pre_start(heartbeat); 308 break; 309 case BROKEN_BIOS: 310 broken_bios_start(acpibase); 311 break; 312 } 313 } 314 EXPORT_SYMBOL(iTCO_vendor_pre_start); 315 316 void iTCO_vendor_pre_stop(unsigned long acpibase) 317 { 318 switch (vendorsupport) { 319 case SUPERMICRO_OLD_BOARD: 320 supermicro_old_pre_stop(acpibase); 321 break; 322 case SUPERMICRO_NEW_BOARD: 323 supermicro_new_pre_stop(); 324 break; 325 case BROKEN_BIOS: 326 broken_bios_stop(acpibase); 327 break; 328 } 329 } 330 EXPORT_SYMBOL(iTCO_vendor_pre_stop); 331 332 void iTCO_vendor_pre_keepalive(unsigned long acpibase, unsigned int heartbeat) 333 { 334 if (vendorsupport == SUPERMICRO_NEW_BOARD) 335 supermicro_new_pre_set_heartbeat(heartbeat); 336 } 337 EXPORT_SYMBOL(iTCO_vendor_pre_keepalive); 338 339 void iTCO_vendor_pre_set_heartbeat(unsigned int heartbeat) 340 { 341 if (vendorsupport == SUPERMICRO_NEW_BOARD) 342 supermicro_new_pre_set_heartbeat(heartbeat); 343 } 344 EXPORT_SYMBOL(iTCO_vendor_pre_set_heartbeat); 345 346 int iTCO_vendor_check_noreboot_on(void) 347 { 348 switch (vendorsupport) { 349 case SUPERMICRO_OLD_BOARD: 350 return 0; 351 default: 352 return 1; 353 } 354 } 355 EXPORT_SYMBOL(iTCO_vendor_check_noreboot_on); 356 357 static int __init iTCO_vendor_init_module(void) 358 { 359 pr_info("vendor-support=%d\n", vendorsupport); 360 return 0; 361 } 362 363 static void __exit iTCO_vendor_exit_module(void) 364 { 365 pr_info("Module Unloaded\n"); 366 } 367 368 module_init(iTCO_vendor_init_module); 369 module_exit(iTCO_vendor_exit_module); 370 371 MODULE_AUTHOR("Wim Van Sebroeck <wim@iguana.be>, " 372 "R. Seretny <lkpatches@paypc.com>"); 373 MODULE_DESCRIPTION("Intel TCO Vendor Specific WatchDog Timer Driver Support"); 374 MODULE_VERSION(DRV_VERSION); 375 MODULE_LICENSE("GPL"); 376 377