1 /* 2 * Copyright 2010-2011 Picochip Ltd., Jamie Iles 3 * http://www.picochip.com 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License 7 * as published by the Free Software Foundation; either version 8 * 2 of the License, or (at your option) any later version. 9 * 10 * This file implements a driver for the Synopsys DesignWare watchdog device 11 * in the many subsystems. The watchdog has 16 different timeout periods 12 * and these are a function of the input clock frequency. 13 * 14 * The DesignWare watchdog cannot be stopped once it has been started so we 15 * do not implement a stop function. The watchdog core will continue to send 16 * heartbeat requests after the watchdog device has been closed. 17 */ 18 19 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 20 21 #include <linux/bitops.h> 22 #include <linux/clk.h> 23 #include <linux/delay.h> 24 #include <linux/err.h> 25 #include <linux/io.h> 26 #include <linux/kernel.h> 27 #include <linux/module.h> 28 #include <linux/moduleparam.h> 29 #include <linux/of.h> 30 #include <linux/pm.h> 31 #include <linux/platform_device.h> 32 #include <linux/reset.h> 33 #include <linux/watchdog.h> 34 35 #define WDOG_CONTROL_REG_OFFSET 0x00 36 #define WDOG_CONTROL_REG_WDT_EN_MASK 0x01 37 #define WDOG_TIMEOUT_RANGE_REG_OFFSET 0x04 38 #define WDOG_TIMEOUT_RANGE_TOPINIT_SHIFT 4 39 #define WDOG_CURRENT_COUNT_REG_OFFSET 0x08 40 #define WDOG_COUNTER_RESTART_REG_OFFSET 0x0c 41 #define WDOG_COUNTER_RESTART_KICK_VALUE 0x76 42 43 /* The maximum TOP (timeout period) value that can be set in the watchdog. */ 44 #define DW_WDT_MAX_TOP 15 45 46 #define DW_WDT_DEFAULT_SECONDS 30 47 48 static bool nowayout = WATCHDOG_NOWAYOUT; 49 module_param(nowayout, bool, 0); 50 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started " 51 "(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); 52 53 struct dw_wdt { 54 void __iomem *regs; 55 struct clk *clk; 56 unsigned long rate; 57 struct watchdog_device wdd; 58 struct reset_control *rst; 59 }; 60 61 #define to_dw_wdt(wdd) container_of(wdd, struct dw_wdt, wdd) 62 63 static inline int dw_wdt_is_enabled(struct dw_wdt *dw_wdt) 64 { 65 return readl(dw_wdt->regs + WDOG_CONTROL_REG_OFFSET) & 66 WDOG_CONTROL_REG_WDT_EN_MASK; 67 } 68 69 static inline int dw_wdt_top_in_seconds(struct dw_wdt *dw_wdt, unsigned top) 70 { 71 /* 72 * There are 16 possible timeout values in 0..15 where the number of 73 * cycles is 2 ^ (16 + i) and the watchdog counts down. 74 */ 75 return (1U << (16 + top)) / dw_wdt->rate; 76 } 77 78 static int dw_wdt_get_top(struct dw_wdt *dw_wdt) 79 { 80 int top = readl(dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET) & 0xF; 81 82 return dw_wdt_top_in_seconds(dw_wdt, top); 83 } 84 85 static int dw_wdt_ping(struct watchdog_device *wdd) 86 { 87 struct dw_wdt *dw_wdt = to_dw_wdt(wdd); 88 89 writel(WDOG_COUNTER_RESTART_KICK_VALUE, dw_wdt->regs + 90 WDOG_COUNTER_RESTART_REG_OFFSET); 91 92 return 0; 93 } 94 95 static int dw_wdt_set_timeout(struct watchdog_device *wdd, unsigned int top_s) 96 { 97 struct dw_wdt *dw_wdt = to_dw_wdt(wdd); 98 int i, top_val = DW_WDT_MAX_TOP; 99 100 /* 101 * Iterate over the timeout values until we find the closest match. We 102 * always look for >=. 103 */ 104 for (i = 0; i <= DW_WDT_MAX_TOP; ++i) 105 if (dw_wdt_top_in_seconds(dw_wdt, i) >= top_s) { 106 top_val = i; 107 break; 108 } 109 110 /* 111 * Set the new value in the watchdog. Some versions of dw_wdt 112 * have have TOPINIT in the TIMEOUT_RANGE register (as per 113 * CP_WDT_DUAL_TOP in WDT_COMP_PARAMS_1). On those we 114 * effectively get a pat of the watchdog right here. 115 */ 116 writel(top_val | top_val << WDOG_TIMEOUT_RANGE_TOPINIT_SHIFT, 117 dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET); 118 119 wdd->timeout = dw_wdt_top_in_seconds(dw_wdt, top_val); 120 121 return 0; 122 } 123 124 static int dw_wdt_start(struct watchdog_device *wdd) 125 { 126 struct dw_wdt *dw_wdt = to_dw_wdt(wdd); 127 128 dw_wdt_set_timeout(wdd, wdd->timeout); 129 130 set_bit(WDOG_HW_RUNNING, &wdd->status); 131 132 writel(WDOG_CONTROL_REG_WDT_EN_MASK, 133 dw_wdt->regs + WDOG_CONTROL_REG_OFFSET); 134 135 return 0; 136 } 137 138 static int dw_wdt_restart(struct watchdog_device *wdd, 139 unsigned long action, void *data) 140 { 141 struct dw_wdt *dw_wdt = to_dw_wdt(wdd); 142 u32 val; 143 144 writel(0, dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET); 145 val = readl(dw_wdt->regs + WDOG_CONTROL_REG_OFFSET); 146 if (val & WDOG_CONTROL_REG_WDT_EN_MASK) 147 writel(WDOG_COUNTER_RESTART_KICK_VALUE, 148 dw_wdt->regs + WDOG_COUNTER_RESTART_REG_OFFSET); 149 else 150 writel(WDOG_CONTROL_REG_WDT_EN_MASK, 151 dw_wdt->regs + WDOG_CONTROL_REG_OFFSET); 152 153 /* wait for reset to assert... */ 154 mdelay(500); 155 156 return 0; 157 } 158 159 static unsigned int dw_wdt_get_timeleft(struct watchdog_device *wdd) 160 { 161 struct dw_wdt *dw_wdt = to_dw_wdt(wdd); 162 163 return readl(dw_wdt->regs + WDOG_CURRENT_COUNT_REG_OFFSET) / 164 dw_wdt->rate; 165 } 166 167 static const struct watchdog_info dw_wdt_ident = { 168 .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | 169 WDIOF_MAGICCLOSE, 170 .identity = "Synopsys DesignWare Watchdog", 171 }; 172 173 static const struct watchdog_ops dw_wdt_ops = { 174 .owner = THIS_MODULE, 175 .start = dw_wdt_start, 176 .ping = dw_wdt_ping, 177 .set_timeout = dw_wdt_set_timeout, 178 .get_timeleft = dw_wdt_get_timeleft, 179 .restart = dw_wdt_restart, 180 }; 181 182 #ifdef CONFIG_PM_SLEEP 183 static int dw_wdt_suspend(struct device *dev) 184 { 185 struct dw_wdt *dw_wdt = dev_get_drvdata(dev); 186 187 clk_disable_unprepare(dw_wdt->clk); 188 189 return 0; 190 } 191 192 static int dw_wdt_resume(struct device *dev) 193 { 194 struct dw_wdt *dw_wdt = dev_get_drvdata(dev); 195 int err = clk_prepare_enable(dw_wdt->clk); 196 197 if (err) 198 return err; 199 200 dw_wdt_ping(&dw_wdt->wdd); 201 202 return 0; 203 } 204 #endif /* CONFIG_PM_SLEEP */ 205 206 static SIMPLE_DEV_PM_OPS(dw_wdt_pm_ops, dw_wdt_suspend, dw_wdt_resume); 207 208 static int dw_wdt_drv_probe(struct platform_device *pdev) 209 { 210 struct device *dev = &pdev->dev; 211 struct watchdog_device *wdd; 212 struct dw_wdt *dw_wdt; 213 struct resource *mem; 214 int ret; 215 216 dw_wdt = devm_kzalloc(dev, sizeof(*dw_wdt), GFP_KERNEL); 217 if (!dw_wdt) 218 return -ENOMEM; 219 220 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 221 dw_wdt->regs = devm_ioremap_resource(dev, mem); 222 if (IS_ERR(dw_wdt->regs)) 223 return PTR_ERR(dw_wdt->regs); 224 225 dw_wdt->clk = devm_clk_get(dev, NULL); 226 if (IS_ERR(dw_wdt->clk)) 227 return PTR_ERR(dw_wdt->clk); 228 229 ret = clk_prepare_enable(dw_wdt->clk); 230 if (ret) 231 return ret; 232 233 dw_wdt->rate = clk_get_rate(dw_wdt->clk); 234 if (dw_wdt->rate == 0) { 235 ret = -EINVAL; 236 goto out_disable_clk; 237 } 238 239 dw_wdt->rst = devm_reset_control_get_optional_shared(&pdev->dev, NULL); 240 if (IS_ERR(dw_wdt->rst)) { 241 ret = PTR_ERR(dw_wdt->rst); 242 goto out_disable_clk; 243 } 244 245 reset_control_deassert(dw_wdt->rst); 246 247 wdd = &dw_wdt->wdd; 248 wdd->info = &dw_wdt_ident; 249 wdd->ops = &dw_wdt_ops; 250 wdd->min_timeout = 1; 251 wdd->max_hw_heartbeat_ms = 252 dw_wdt_top_in_seconds(dw_wdt, DW_WDT_MAX_TOP) * 1000; 253 wdd->parent = dev; 254 255 watchdog_set_drvdata(wdd, dw_wdt); 256 watchdog_set_nowayout(wdd, nowayout); 257 watchdog_init_timeout(wdd, 0, dev); 258 259 /* 260 * If the watchdog is already running, use its already configured 261 * timeout. Otherwise use the default or the value provided through 262 * devicetree. 263 */ 264 if (dw_wdt_is_enabled(dw_wdt)) { 265 wdd->timeout = dw_wdt_get_top(dw_wdt); 266 set_bit(WDOG_HW_RUNNING, &wdd->status); 267 } else { 268 wdd->timeout = DW_WDT_DEFAULT_SECONDS; 269 watchdog_init_timeout(wdd, 0, dev); 270 } 271 272 platform_set_drvdata(pdev, dw_wdt); 273 274 watchdog_set_restart_priority(wdd, 128); 275 276 ret = watchdog_register_device(wdd); 277 if (ret) 278 goto out_disable_clk; 279 280 return 0; 281 282 out_disable_clk: 283 clk_disable_unprepare(dw_wdt->clk); 284 return ret; 285 } 286 287 static int dw_wdt_drv_remove(struct platform_device *pdev) 288 { 289 struct dw_wdt *dw_wdt = platform_get_drvdata(pdev); 290 291 watchdog_unregister_device(&dw_wdt->wdd); 292 reset_control_assert(dw_wdt->rst); 293 clk_disable_unprepare(dw_wdt->clk); 294 295 return 0; 296 } 297 298 #ifdef CONFIG_OF 299 static const struct of_device_id dw_wdt_of_match[] = { 300 { .compatible = "snps,dw-wdt", }, 301 { /* sentinel */ } 302 }; 303 MODULE_DEVICE_TABLE(of, dw_wdt_of_match); 304 #endif 305 306 static struct platform_driver dw_wdt_driver = { 307 .probe = dw_wdt_drv_probe, 308 .remove = dw_wdt_drv_remove, 309 .driver = { 310 .name = "dw_wdt", 311 .of_match_table = of_match_ptr(dw_wdt_of_match), 312 .pm = &dw_wdt_pm_ops, 313 }, 314 }; 315 316 module_platform_driver(dw_wdt_driver); 317 318 MODULE_AUTHOR("Jamie Iles"); 319 MODULE_DESCRIPTION("Synopsys DesignWare Watchdog Driver"); 320 MODULE_LICENSE("GPL"); 321