1 /* 2 * Copyright 2016 IBM Corporation 3 * 4 * Joel Stanley <joel@jms.id.au> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 9 * 2 of the License, or (at your option) any later version. 10 */ 11 12 #include <linux/delay.h> 13 #include <linux/io.h> 14 #include <linux/kernel.h> 15 #include <linux/module.h> 16 #include <linux/of.h> 17 #include <linux/platform_device.h> 18 #include <linux/watchdog.h> 19 20 struct aspeed_wdt { 21 struct watchdog_device wdd; 22 void __iomem *base; 23 u32 ctrl; 24 }; 25 26 struct aspeed_wdt_config { 27 u32 ext_pulse_width_mask; 28 }; 29 30 static const struct aspeed_wdt_config ast2400_config = { 31 .ext_pulse_width_mask = 0xff, 32 }; 33 34 static const struct aspeed_wdt_config ast2500_config = { 35 .ext_pulse_width_mask = 0xfffff, 36 }; 37 38 static const struct of_device_id aspeed_wdt_of_table[] = { 39 { .compatible = "aspeed,ast2400-wdt", .data = &ast2400_config }, 40 { .compatible = "aspeed,ast2500-wdt", .data = &ast2500_config }, 41 { }, 42 }; 43 MODULE_DEVICE_TABLE(of, aspeed_wdt_of_table); 44 45 #define WDT_STATUS 0x00 46 #define WDT_RELOAD_VALUE 0x04 47 #define WDT_RESTART 0x08 48 #define WDT_CTRL 0x0C 49 #define WDT_CTRL_RESET_MODE_SOC (0x00 << 5) 50 #define WDT_CTRL_RESET_MODE_FULL_CHIP (0x01 << 5) 51 #define WDT_CTRL_RESET_MODE_ARM_CPU (0x10 << 5) 52 #define WDT_CTRL_1MHZ_CLK BIT(4) 53 #define WDT_CTRL_WDT_EXT BIT(3) 54 #define WDT_CTRL_WDT_INTR BIT(2) 55 #define WDT_CTRL_RESET_SYSTEM BIT(1) 56 #define WDT_CTRL_ENABLE BIT(0) 57 58 /* 59 * WDT_RESET_WIDTH controls the characteristics of the external pulse (if 60 * enabled), specifically: 61 * 62 * * Pulse duration 63 * * Drive mode: push-pull vs open-drain 64 * * Polarity: Active high or active low 65 * 66 * Pulse duration configuration is available on both the AST2400 and AST2500, 67 * though the field changes between SoCs: 68 * 69 * AST2400: Bits 7:0 70 * AST2500: Bits 19:0 71 * 72 * This difference is captured in struct aspeed_wdt_config. 73 * 74 * The AST2500 exposes the drive mode and polarity options, but not in a 75 * regular fashion. For read purposes, bit 31 represents active high or low, 76 * and bit 30 represents push-pull or open-drain. With respect to write, magic 77 * values need to be written to the top byte to change the state of the drive 78 * mode and polarity bits. Any other value written to the top byte has no 79 * effect on the state of the drive mode or polarity bits. However, the pulse 80 * width value must be preserved (as desired) if written. 81 */ 82 #define WDT_RESET_WIDTH 0x18 83 #define WDT_RESET_WIDTH_ACTIVE_HIGH BIT(31) 84 #define WDT_ACTIVE_HIGH_MAGIC (0xA5 << 24) 85 #define WDT_ACTIVE_LOW_MAGIC (0x5A << 24) 86 #define WDT_RESET_WIDTH_PUSH_PULL BIT(30) 87 #define WDT_PUSH_PULL_MAGIC (0xA8 << 24) 88 #define WDT_OPEN_DRAIN_MAGIC (0x8A << 24) 89 90 #define WDT_RESTART_MAGIC 0x4755 91 92 /* 32 bits at 1MHz, in milliseconds */ 93 #define WDT_MAX_TIMEOUT_MS 4294967 94 #define WDT_DEFAULT_TIMEOUT 30 95 #define WDT_RATE_1MHZ 1000000 96 97 static struct aspeed_wdt *to_aspeed_wdt(struct watchdog_device *wdd) 98 { 99 return container_of(wdd, struct aspeed_wdt, wdd); 100 } 101 102 static void aspeed_wdt_enable(struct aspeed_wdt *wdt, int count) 103 { 104 wdt->ctrl |= WDT_CTRL_ENABLE; 105 106 writel(0, wdt->base + WDT_CTRL); 107 writel(count, wdt->base + WDT_RELOAD_VALUE); 108 writel(WDT_RESTART_MAGIC, wdt->base + WDT_RESTART); 109 writel(wdt->ctrl, wdt->base + WDT_CTRL); 110 } 111 112 static int aspeed_wdt_start(struct watchdog_device *wdd) 113 { 114 struct aspeed_wdt *wdt = to_aspeed_wdt(wdd); 115 116 aspeed_wdt_enable(wdt, wdd->timeout * WDT_RATE_1MHZ); 117 118 return 0; 119 } 120 121 static int aspeed_wdt_stop(struct watchdog_device *wdd) 122 { 123 struct aspeed_wdt *wdt = to_aspeed_wdt(wdd); 124 125 wdt->ctrl &= ~WDT_CTRL_ENABLE; 126 writel(wdt->ctrl, wdt->base + WDT_CTRL); 127 128 return 0; 129 } 130 131 static int aspeed_wdt_ping(struct watchdog_device *wdd) 132 { 133 struct aspeed_wdt *wdt = to_aspeed_wdt(wdd); 134 135 writel(WDT_RESTART_MAGIC, wdt->base + WDT_RESTART); 136 137 return 0; 138 } 139 140 static int aspeed_wdt_set_timeout(struct watchdog_device *wdd, 141 unsigned int timeout) 142 { 143 struct aspeed_wdt *wdt = to_aspeed_wdt(wdd); 144 u32 actual; 145 146 wdd->timeout = timeout; 147 148 actual = min(timeout, wdd->max_hw_heartbeat_ms * 1000); 149 150 writel(actual * WDT_RATE_1MHZ, wdt->base + WDT_RELOAD_VALUE); 151 writel(WDT_RESTART_MAGIC, wdt->base + WDT_RESTART); 152 153 return 0; 154 } 155 156 static int aspeed_wdt_restart(struct watchdog_device *wdd, 157 unsigned long action, void *data) 158 { 159 struct aspeed_wdt *wdt = to_aspeed_wdt(wdd); 160 161 aspeed_wdt_enable(wdt, 128 * WDT_RATE_1MHZ / 1000); 162 163 mdelay(1000); 164 165 return 0; 166 } 167 168 static const struct watchdog_ops aspeed_wdt_ops = { 169 .start = aspeed_wdt_start, 170 .stop = aspeed_wdt_stop, 171 .ping = aspeed_wdt_ping, 172 .set_timeout = aspeed_wdt_set_timeout, 173 .restart = aspeed_wdt_restart, 174 .owner = THIS_MODULE, 175 }; 176 177 static const struct watchdog_info aspeed_wdt_info = { 178 .options = WDIOF_KEEPALIVEPING 179 | WDIOF_MAGICCLOSE 180 | WDIOF_SETTIMEOUT, 181 .identity = KBUILD_MODNAME, 182 }; 183 184 static int aspeed_wdt_probe(struct platform_device *pdev) 185 { 186 const struct aspeed_wdt_config *config; 187 const struct of_device_id *ofdid; 188 struct aspeed_wdt *wdt; 189 struct resource *res; 190 struct device_node *np; 191 const char *reset_type; 192 u32 duration; 193 int ret; 194 195 wdt = devm_kzalloc(&pdev->dev, sizeof(*wdt), GFP_KERNEL); 196 if (!wdt) 197 return -ENOMEM; 198 199 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 200 wdt->base = devm_ioremap_resource(&pdev->dev, res); 201 if (IS_ERR(wdt->base)) 202 return PTR_ERR(wdt->base); 203 204 /* 205 * The ast2400 wdt can run at PCLK, or 1MHz. The ast2500 only 206 * runs at 1MHz. We chose to always run at 1MHz, as there's no 207 * good reason to have a faster watchdog counter. 208 */ 209 wdt->wdd.info = &aspeed_wdt_info; 210 wdt->wdd.ops = &aspeed_wdt_ops; 211 wdt->wdd.max_hw_heartbeat_ms = WDT_MAX_TIMEOUT_MS; 212 wdt->wdd.parent = &pdev->dev; 213 214 wdt->wdd.timeout = WDT_DEFAULT_TIMEOUT; 215 watchdog_init_timeout(&wdt->wdd, 0, &pdev->dev); 216 217 np = pdev->dev.of_node; 218 219 ofdid = of_match_node(aspeed_wdt_of_table, np); 220 if (!ofdid) 221 return -EINVAL; 222 config = ofdid->data; 223 224 wdt->ctrl = WDT_CTRL_1MHZ_CLK; 225 226 /* 227 * Control reset on a per-device basis to ensure the 228 * host is not affected by a BMC reboot 229 */ 230 ret = of_property_read_string(np, "aspeed,reset-type", &reset_type); 231 if (ret) { 232 wdt->ctrl |= WDT_CTRL_RESET_MODE_SOC | WDT_CTRL_RESET_SYSTEM; 233 } else { 234 if (!strcmp(reset_type, "cpu")) 235 wdt->ctrl |= WDT_CTRL_RESET_MODE_ARM_CPU; 236 else if (!strcmp(reset_type, "soc")) 237 wdt->ctrl |= WDT_CTRL_RESET_MODE_SOC; 238 else if (!strcmp(reset_type, "system")) 239 wdt->ctrl |= WDT_CTRL_RESET_SYSTEM; 240 else if (strcmp(reset_type, "none")) 241 return -EINVAL; 242 } 243 if (of_property_read_bool(np, "aspeed,external-signal")) 244 wdt->ctrl |= WDT_CTRL_WDT_EXT; 245 246 if (readl(wdt->base + WDT_CTRL) & WDT_CTRL_ENABLE) { 247 /* 248 * The watchdog is running, but invoke aspeed_wdt_start() to 249 * write wdt->ctrl to WDT_CTRL to ensure the watchdog's 250 * configuration conforms to the driver's expectations. 251 * Primarily, ensure we're using the 1MHz clock source. 252 */ 253 aspeed_wdt_start(&wdt->wdd); 254 set_bit(WDOG_HW_RUNNING, &wdt->wdd.status); 255 } 256 257 if (of_device_is_compatible(np, "aspeed,ast2500-wdt")) { 258 u32 reg = readl(wdt->base + WDT_RESET_WIDTH); 259 260 reg &= config->ext_pulse_width_mask; 261 if (of_property_read_bool(np, "aspeed,ext-push-pull")) 262 reg |= WDT_PUSH_PULL_MAGIC; 263 else 264 reg |= WDT_OPEN_DRAIN_MAGIC; 265 266 writel(reg, wdt->base + WDT_RESET_WIDTH); 267 268 reg &= config->ext_pulse_width_mask; 269 if (of_property_read_bool(np, "aspeed,ext-active-high")) 270 reg |= WDT_ACTIVE_HIGH_MAGIC; 271 else 272 reg |= WDT_ACTIVE_LOW_MAGIC; 273 274 writel(reg, wdt->base + WDT_RESET_WIDTH); 275 } 276 277 if (!of_property_read_u32(np, "aspeed,ext-pulse-duration", &duration)) { 278 u32 max_duration = config->ext_pulse_width_mask + 1; 279 280 if (duration == 0 || duration > max_duration) { 281 dev_err(&pdev->dev, "Invalid pulse duration: %uus\n", 282 duration); 283 duration = max(1U, min(max_duration, duration)); 284 dev_info(&pdev->dev, "Pulse duration set to %uus\n", 285 duration); 286 } 287 288 /* 289 * The watchdog is always configured with a 1MHz source, so 290 * there is no need to scale the microsecond value. However we 291 * need to offset it - from the datasheet: 292 * 293 * "This register decides the asserting duration of wdt_ext and 294 * wdt_rstarm signal. The default value is 0xFF. It means the 295 * default asserting duration of wdt_ext and wdt_rstarm is 296 * 256us." 297 * 298 * This implies a value of 0 gives a 1us pulse. 299 */ 300 writel(duration - 1, wdt->base + WDT_RESET_WIDTH); 301 } 302 303 ret = devm_watchdog_register_device(&pdev->dev, &wdt->wdd); 304 if (ret) { 305 dev_err(&pdev->dev, "failed to register\n"); 306 return ret; 307 } 308 309 return 0; 310 } 311 312 static struct platform_driver aspeed_watchdog_driver = { 313 .probe = aspeed_wdt_probe, 314 .driver = { 315 .name = KBUILD_MODNAME, 316 .of_match_table = of_match_ptr(aspeed_wdt_of_table), 317 }, 318 }; 319 320 static int __init aspeed_wdt_init(void) 321 { 322 return platform_driver_register(&aspeed_watchdog_driver); 323 } 324 arch_initcall(aspeed_wdt_init); 325 326 static void __exit aspeed_wdt_exit(void) 327 { 328 platform_driver_unregister(&aspeed_watchdog_driver); 329 } 330 module_exit(aspeed_wdt_exit); 331 332 MODULE_DESCRIPTION("Aspeed Watchdog Driver"); 333 MODULE_LICENSE("GPL"); 334