1 /* 2 * Copyright 2005-2008 Freescale Semiconductor, Inc. All Rights Reserved. 3 * Copyright 2008 Luotao Fu, kernel@pengutronix.de 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License 7 * as published by the Free Software Foundation; either version 2 8 * of the License, or (at your option) any later version. 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. 17 * 18 */ 19 20 #include <linux/module.h> 21 #include <linux/interrupt.h> 22 #include <linux/platform_device.h> 23 #include <linux/clk.h> 24 #include <linux/slab.h> 25 #include <linux/delay.h> 26 #include <linux/io.h> 27 28 #include "../w1.h" 29 #include "../w1_int.h" 30 #include "../w1_log.h" 31 32 /* According to the mx27 Datasheet the reset procedure should take up to about 33 * 1350us. We set the timeout to 500*100us = 50ms for sure */ 34 #define MXC_W1_RESET_TIMEOUT 500 35 36 /* 37 * MXC W1 Register offsets 38 */ 39 #define MXC_W1_CONTROL 0x00 40 #define MXC_W1_TIME_DIVIDER 0x02 41 #define MXC_W1_RESET 0x04 42 #define MXC_W1_COMMAND 0x06 43 #define MXC_W1_TXRX 0x08 44 #define MXC_W1_INTERRUPT 0x0A 45 #define MXC_W1_INTERRUPT_EN 0x0C 46 47 struct mxc_w1_device { 48 void __iomem *regs; 49 struct clk *clk; 50 struct w1_bus_master bus_master; 51 }; 52 53 /* 54 * this is the low level routine to 55 * reset the device on the One Wire interface 56 * on the hardware 57 */ 58 static u8 mxc_w1_ds2_reset_bus(void *data) 59 { 60 u8 reg_val; 61 unsigned int timeout_cnt = 0; 62 struct mxc_w1_device *dev = data; 63 64 __raw_writeb(0x80, (dev->regs + MXC_W1_CONTROL)); 65 66 while (1) { 67 reg_val = __raw_readb(dev->regs + MXC_W1_CONTROL); 68 69 if (((reg_val >> 7) & 0x1) == 0 || 70 timeout_cnt > MXC_W1_RESET_TIMEOUT) 71 break; 72 else 73 timeout_cnt++; 74 75 udelay(100); 76 } 77 return (reg_val >> 7) & 0x1; 78 } 79 80 /* 81 * this is the low level routine to read/write a bit on the One Wire 82 * interface on the hardware. It does write 0 if parameter bit is set 83 * to 0, otherwise a write 1/read. 84 */ 85 static u8 mxc_w1_ds2_touch_bit(void *data, u8 bit) 86 { 87 struct mxc_w1_device *mdev = data; 88 void __iomem *ctrl_addr = mdev->regs + MXC_W1_CONTROL; 89 unsigned int timeout_cnt = 400; /* Takes max. 120us according to 90 * datasheet. 91 */ 92 93 __raw_writeb((1 << (5 - bit)), ctrl_addr); 94 95 while (timeout_cnt--) { 96 if (!((__raw_readb(ctrl_addr) >> (5 - bit)) & 0x1)) 97 break; 98 99 udelay(1); 100 } 101 102 return ((__raw_readb(ctrl_addr)) >> 3) & 0x1; 103 } 104 105 static int mxc_w1_probe(struct platform_device *pdev) 106 { 107 struct mxc_w1_device *mdev; 108 unsigned long clkrate; 109 struct resource *res; 110 unsigned int clkdiv; 111 int err; 112 113 mdev = devm_kzalloc(&pdev->dev, sizeof(struct mxc_w1_device), 114 GFP_KERNEL); 115 if (!mdev) 116 return -ENOMEM; 117 118 mdev->clk = devm_clk_get(&pdev->dev, NULL); 119 if (IS_ERR(mdev->clk)) 120 return PTR_ERR(mdev->clk); 121 122 clkrate = clk_get_rate(mdev->clk); 123 if (clkrate < 10000000) 124 dev_warn(&pdev->dev, 125 "Low clock frequency causes improper function\n"); 126 127 clkdiv = DIV_ROUND_CLOSEST(clkrate, 1000000); 128 clkrate /= clkdiv; 129 if ((clkrate < 980000) || (clkrate > 1020000)) 130 dev_warn(&pdev->dev, 131 "Incorrect time base frequency %lu Hz\n", clkrate); 132 133 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 134 mdev->regs = devm_ioremap_resource(&pdev->dev, res); 135 if (IS_ERR(mdev->regs)) 136 return PTR_ERR(mdev->regs); 137 138 err = clk_prepare_enable(mdev->clk); 139 if (err) 140 return err; 141 142 __raw_writeb(clkdiv - 1, mdev->regs + MXC_W1_TIME_DIVIDER); 143 144 mdev->bus_master.data = mdev; 145 mdev->bus_master.reset_bus = mxc_w1_ds2_reset_bus; 146 mdev->bus_master.touch_bit = mxc_w1_ds2_touch_bit; 147 148 platform_set_drvdata(pdev, mdev); 149 150 err = w1_add_master_device(&mdev->bus_master); 151 if (err) 152 clk_disable_unprepare(mdev->clk); 153 154 return err; 155 } 156 157 /* 158 * disassociate the w1 device from the driver 159 */ 160 static int mxc_w1_remove(struct platform_device *pdev) 161 { 162 struct mxc_w1_device *mdev = platform_get_drvdata(pdev); 163 164 w1_remove_master_device(&mdev->bus_master); 165 166 clk_disable_unprepare(mdev->clk); 167 168 return 0; 169 } 170 171 static struct of_device_id mxc_w1_dt_ids[] = { 172 { .compatible = "fsl,imx21-owire" }, 173 { /* sentinel */ } 174 }; 175 MODULE_DEVICE_TABLE(of, mxc_w1_dt_ids); 176 177 static struct platform_driver mxc_w1_driver = { 178 .driver = { 179 .name = "mxc_w1", 180 .of_match_table = mxc_w1_dt_ids, 181 }, 182 .probe = mxc_w1_probe, 183 .remove = mxc_w1_remove, 184 }; 185 module_platform_driver(mxc_w1_driver); 186 187 MODULE_LICENSE("GPL"); 188 MODULE_AUTHOR("Freescale Semiconductors Inc"); 189 MODULE_DESCRIPTION("Driver for One-Wire on MXC"); 190