1 /* 2 * Xilinx TFT frame buffer driver 3 * 4 * Author: MontaVista Software, Inc. 5 * source@mvista.com 6 * 7 * 2002-2007 (c) MontaVista Software, Inc. 8 * 2007 (c) Secret Lab Technologies, Ltd. 9 * 2009 (c) Xilinx Inc. 10 * 11 * This file is licensed under the terms of the GNU General Public License 12 * version 2. This program is licensed "as is" without any warranty of any 13 * kind, whether express or implied. 14 */ 15 16 /* 17 * This driver was based on au1100fb.c by MontaVista rewritten for 2.6 18 * by Embedded Alley Solutions <source@embeddedalley.com>, which in turn 19 * was based on skeletonfb.c, Skeleton for a frame buffer device by 20 * Geert Uytterhoeven. 21 */ 22 23 #include <linux/device.h> 24 #include <linux/module.h> 25 #include <linux/kernel.h> 26 #include <linux/errno.h> 27 #include <linux/string.h> 28 #include <linux/mm.h> 29 #include <linux/fb.h> 30 #include <linux/init.h> 31 #include <linux/dma-mapping.h> 32 #include <linux/of_device.h> 33 #include <linux/of_platform.h> 34 #include <linux/of_address.h> 35 #include <linux/io.h> 36 #include <linux/slab.h> 37 38 #ifdef CONFIG_PPC_DCR 39 #include <asm/dcr.h> 40 #endif 41 42 #define DRIVER_NAME "xilinxfb" 43 44 /* 45 * Xilinx calls it "TFT LCD Controller" though it can also be used for 46 * the VGA port on the Xilinx ML40x board. This is a hardware display 47 * controller for a 640x480 resolution TFT or VGA screen. 48 * 49 * The interface to the framebuffer is nice and simple. There are two 50 * control registers. The first tells the LCD interface where in memory 51 * the frame buffer is (only the 11 most significant bits are used, so 52 * don't start thinking about scrolling). The second allows the LCD to 53 * be turned on or off as well as rotated 180 degrees. 54 * 55 * In case of direct BUS access the second control register will be at 56 * an offset of 4 as compared to the DCR access where the offset is 1 57 * i.e. REG_CTRL. So this is taken care in the function 58 * xilinx_fb_out32 where it left shifts the offset 2 times in case of 59 * direct BUS access. 60 */ 61 #define NUM_REGS 2 62 #define REG_FB_ADDR 0 63 #define REG_CTRL 1 64 #define REG_CTRL_ENABLE 0x0001 65 #define REG_CTRL_ROTATE 0x0002 66 67 /* 68 * The hardware only handles a single mode: 640x480 24 bit true 69 * color. Each pixel gets a word (32 bits) of memory. Within each word, 70 * the 8 most significant bits are ignored, the next 8 bits are the red 71 * level, the next 8 bits are the green level and the 8 least 72 * significant bits are the blue level. Each row of the LCD uses 1024 73 * words, but only the first 640 pixels are displayed with the other 384 74 * words being ignored. There are 480 rows. 75 */ 76 #define BYTES_PER_PIXEL 4 77 #define BITS_PER_PIXEL (BYTES_PER_PIXEL * 8) 78 79 #define RED_SHIFT 16 80 #define GREEN_SHIFT 8 81 #define BLUE_SHIFT 0 82 83 #define PALETTE_ENTRIES_NO 16 /* passed to fb_alloc_cmap() */ 84 85 /* ML300/403 reference design framebuffer driver platform data struct */ 86 struct xilinxfb_platform_data { 87 u32 rotate_screen; /* Flag to rotate display 180 degrees */ 88 u32 screen_height_mm; /* Physical dimensions of screen in mm */ 89 u32 screen_width_mm; 90 u32 xres, yres; /* resolution of screen in pixels */ 91 u32 xvirt, yvirt; /* resolution of memory buffer */ 92 93 /* Physical address of framebuffer memory; If non-zero, driver 94 * will use provided memory address instead of allocating one from 95 * the consistent pool. 96 */ 97 u32 fb_phys; 98 }; 99 100 /* 101 * Default xilinxfb configuration 102 */ 103 static const struct xilinxfb_platform_data xilinx_fb_default_pdata = { 104 .xres = 640, 105 .yres = 480, 106 .xvirt = 1024, 107 .yvirt = 480, 108 }; 109 110 /* 111 * Here are the default fb_fix_screeninfo and fb_var_screeninfo structures 112 */ 113 static const struct fb_fix_screeninfo xilinx_fb_fix = { 114 .id = "Xilinx", 115 .type = FB_TYPE_PACKED_PIXELS, 116 .visual = FB_VISUAL_TRUECOLOR, 117 .accel = FB_ACCEL_NONE 118 }; 119 120 static const struct fb_var_screeninfo xilinx_fb_var = { 121 .bits_per_pixel = BITS_PER_PIXEL, 122 123 .red = { RED_SHIFT, 8, 0 }, 124 .green = { GREEN_SHIFT, 8, 0 }, 125 .blue = { BLUE_SHIFT, 8, 0 }, 126 .transp = { 0, 0, 0 }, 127 128 .activate = FB_ACTIVATE_NOW 129 }; 130 131 #define BUS_ACCESS_FLAG 0x1 /* 1 = BUS, 0 = DCR */ 132 #define LITTLE_ENDIAN_ACCESS 0x2 /* LITTLE ENDIAN IO functions */ 133 134 struct xilinxfb_drvdata { 135 struct fb_info info; /* FB driver info record */ 136 137 phys_addr_t regs_phys; /* phys. address of the control 138 * registers 139 */ 140 void __iomem *regs; /* virt. address of the control 141 * registers 142 */ 143 #ifdef CONFIG_PPC_DCR 144 dcr_host_t dcr_host; 145 unsigned int dcr_len; 146 #endif 147 void *fb_virt; /* virt. address of the frame buffer */ 148 dma_addr_t fb_phys; /* phys. address of the frame buffer */ 149 int fb_alloced; /* Flag, was the fb memory alloced? */ 150 151 u8 flags; /* features of the driver */ 152 153 u32 reg_ctrl_default; 154 155 u32 pseudo_palette[PALETTE_ENTRIES_NO]; 156 /* Fake palette of 16 colors */ 157 }; 158 159 #define to_xilinxfb_drvdata(_info) \ 160 container_of(_info, struct xilinxfb_drvdata, info) 161 162 /* 163 * The XPS TFT Controller can be accessed through BUS or DCR interface. 164 * To perform the read/write on the registers we need to check on 165 * which bus its connected and call the appropriate write API. 166 */ 167 static void xilinx_fb_out32(struct xilinxfb_drvdata *drvdata, u32 offset, 168 u32 val) 169 { 170 if (drvdata->flags & BUS_ACCESS_FLAG) { 171 if (drvdata->flags & LITTLE_ENDIAN_ACCESS) 172 iowrite32(val, drvdata->regs + (offset << 2)); 173 else 174 iowrite32be(val, drvdata->regs + (offset << 2)); 175 } 176 #ifdef CONFIG_PPC_DCR 177 else 178 dcr_write(drvdata->dcr_host, offset, val); 179 #endif 180 } 181 182 static u32 xilinx_fb_in32(struct xilinxfb_drvdata *drvdata, u32 offset) 183 { 184 if (drvdata->flags & BUS_ACCESS_FLAG) { 185 if (drvdata->flags & LITTLE_ENDIAN_ACCESS) 186 return ioread32(drvdata->regs + (offset << 2)); 187 else 188 return ioread32be(drvdata->regs + (offset << 2)); 189 } 190 #ifdef CONFIG_PPC_DCR 191 else 192 return dcr_read(drvdata->dcr_host, offset); 193 #endif 194 return 0; 195 } 196 197 static int 198 xilinx_fb_setcolreg(unsigned int regno, unsigned int red, unsigned int green, 199 unsigned int blue, unsigned int transp, struct fb_info *fbi) 200 { 201 u32 *palette = fbi->pseudo_palette; 202 203 if (regno >= PALETTE_ENTRIES_NO) 204 return -EINVAL; 205 206 if (fbi->var.grayscale) { 207 /* Convert color to grayscale. 208 * grayscale = 0.30*R + 0.59*G + 0.11*B 209 */ 210 blue = (red * 77 + green * 151 + blue * 28 + 127) >> 8; 211 green = blue; 212 red = green; 213 } 214 215 /* fbi->fix.visual is always FB_VISUAL_TRUECOLOR */ 216 217 /* We only handle 8 bits of each color. */ 218 red >>= 8; 219 green >>= 8; 220 blue >>= 8; 221 palette[regno] = (red << RED_SHIFT) | (green << GREEN_SHIFT) | 222 (blue << BLUE_SHIFT); 223 224 return 0; 225 } 226 227 static int 228 xilinx_fb_blank(int blank_mode, struct fb_info *fbi) 229 { 230 struct xilinxfb_drvdata *drvdata = to_xilinxfb_drvdata(fbi); 231 232 switch (blank_mode) { 233 case FB_BLANK_UNBLANK: 234 /* turn on panel */ 235 xilinx_fb_out32(drvdata, REG_CTRL, drvdata->reg_ctrl_default); 236 break; 237 238 case FB_BLANK_NORMAL: 239 case FB_BLANK_VSYNC_SUSPEND: 240 case FB_BLANK_HSYNC_SUSPEND: 241 case FB_BLANK_POWERDOWN: 242 /* turn off panel */ 243 xilinx_fb_out32(drvdata, REG_CTRL, 0); 244 break; 245 246 default: 247 break; 248 } 249 return 0; /* success */ 250 } 251 252 static const struct fb_ops xilinxfb_ops = { 253 .owner = THIS_MODULE, 254 .fb_setcolreg = xilinx_fb_setcolreg, 255 .fb_blank = xilinx_fb_blank, 256 .fb_fillrect = cfb_fillrect, 257 .fb_copyarea = cfb_copyarea, 258 .fb_imageblit = cfb_imageblit, 259 }; 260 261 /* --------------------------------------------------------------------- 262 * Bus independent setup/teardown 263 */ 264 265 static int xilinxfb_assign(struct platform_device *pdev, 266 struct xilinxfb_drvdata *drvdata, 267 struct xilinxfb_platform_data *pdata) 268 { 269 int rc; 270 struct device *dev = &pdev->dev; 271 int fbsize = pdata->xvirt * pdata->yvirt * BYTES_PER_PIXEL; 272 273 if (drvdata->flags & BUS_ACCESS_FLAG) { 274 struct resource *res; 275 276 drvdata->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 277 if (IS_ERR(drvdata->regs)) 278 return PTR_ERR(drvdata->regs); 279 280 drvdata->regs_phys = res->start; 281 } 282 283 /* Allocate the framebuffer memory */ 284 if (pdata->fb_phys) { 285 drvdata->fb_phys = pdata->fb_phys; 286 drvdata->fb_virt = ioremap(pdata->fb_phys, fbsize); 287 } else { 288 drvdata->fb_alloced = 1; 289 drvdata->fb_virt = dma_alloc_coherent(dev, PAGE_ALIGN(fbsize), 290 &drvdata->fb_phys, 291 GFP_KERNEL); 292 } 293 294 if (!drvdata->fb_virt) { 295 dev_err(dev, "Could not allocate frame buffer memory\n"); 296 return -ENOMEM; 297 } 298 299 /* Clear (turn to black) the framebuffer */ 300 memset_io((void __iomem *)drvdata->fb_virt, 0, fbsize); 301 302 /* Tell the hardware where the frame buffer is */ 303 xilinx_fb_out32(drvdata, REG_FB_ADDR, drvdata->fb_phys); 304 rc = xilinx_fb_in32(drvdata, REG_FB_ADDR); 305 /* Endianness detection */ 306 if (rc != drvdata->fb_phys) { 307 drvdata->flags |= LITTLE_ENDIAN_ACCESS; 308 xilinx_fb_out32(drvdata, REG_FB_ADDR, drvdata->fb_phys); 309 } 310 311 /* Turn on the display */ 312 drvdata->reg_ctrl_default = REG_CTRL_ENABLE; 313 if (pdata->rotate_screen) 314 drvdata->reg_ctrl_default |= REG_CTRL_ROTATE; 315 xilinx_fb_out32(drvdata, REG_CTRL, drvdata->reg_ctrl_default); 316 317 /* Fill struct fb_info */ 318 drvdata->info.device = dev; 319 drvdata->info.screen_base = (void __iomem *)drvdata->fb_virt; 320 drvdata->info.fbops = &xilinxfb_ops; 321 drvdata->info.fix = xilinx_fb_fix; 322 drvdata->info.fix.smem_start = drvdata->fb_phys; 323 drvdata->info.fix.smem_len = fbsize; 324 drvdata->info.fix.line_length = pdata->xvirt * BYTES_PER_PIXEL; 325 326 drvdata->info.pseudo_palette = drvdata->pseudo_palette; 327 drvdata->info.flags = FBINFO_DEFAULT; 328 drvdata->info.var = xilinx_fb_var; 329 drvdata->info.var.height = pdata->screen_height_mm; 330 drvdata->info.var.width = pdata->screen_width_mm; 331 drvdata->info.var.xres = pdata->xres; 332 drvdata->info.var.yres = pdata->yres; 333 drvdata->info.var.xres_virtual = pdata->xvirt; 334 drvdata->info.var.yres_virtual = pdata->yvirt; 335 336 /* Allocate a colour map */ 337 rc = fb_alloc_cmap(&drvdata->info.cmap, PALETTE_ENTRIES_NO, 0); 338 if (rc) { 339 dev_err(dev, "Fail to allocate colormap (%d entries)\n", 340 PALETTE_ENTRIES_NO); 341 goto err_cmap; 342 } 343 344 /* Register new frame buffer */ 345 rc = register_framebuffer(&drvdata->info); 346 if (rc) { 347 dev_err(dev, "Could not register frame buffer\n"); 348 goto err_regfb; 349 } 350 351 if (drvdata->flags & BUS_ACCESS_FLAG) { 352 /* Put a banner in the log (for DEBUG) */ 353 dev_dbg(dev, "regs: phys=%pa, virt=%p\n", 354 &drvdata->regs_phys, drvdata->regs); 355 } 356 /* Put a banner in the log (for DEBUG) */ 357 dev_dbg(dev, "fb: phys=%llx, virt=%p, size=%x\n", 358 (unsigned long long)drvdata->fb_phys, drvdata->fb_virt, fbsize); 359 360 return 0; /* success */ 361 362 err_regfb: 363 fb_dealloc_cmap(&drvdata->info.cmap); 364 365 err_cmap: 366 if (drvdata->fb_alloced) 367 dma_free_coherent(dev, PAGE_ALIGN(fbsize), drvdata->fb_virt, 368 drvdata->fb_phys); 369 else 370 iounmap(drvdata->fb_virt); 371 372 /* Turn off the display */ 373 xilinx_fb_out32(drvdata, REG_CTRL, 0); 374 375 return rc; 376 } 377 378 static void xilinxfb_release(struct device *dev) 379 { 380 struct xilinxfb_drvdata *drvdata = dev_get_drvdata(dev); 381 382 #if !defined(CONFIG_FRAMEBUFFER_CONSOLE) && defined(CONFIG_LOGO) 383 xilinx_fb_blank(VESA_POWERDOWN, &drvdata->info); 384 #endif 385 386 unregister_framebuffer(&drvdata->info); 387 388 fb_dealloc_cmap(&drvdata->info.cmap); 389 390 if (drvdata->fb_alloced) 391 dma_free_coherent(dev, PAGE_ALIGN(drvdata->info.fix.smem_len), 392 drvdata->fb_virt, drvdata->fb_phys); 393 else 394 iounmap(drvdata->fb_virt); 395 396 /* Turn off the display */ 397 xilinx_fb_out32(drvdata, REG_CTRL, 0); 398 399 #ifdef CONFIG_PPC_DCR 400 /* Release the resources, as allocated based on interface */ 401 if (!(drvdata->flags & BUS_ACCESS_FLAG)) 402 dcr_unmap(drvdata->dcr_host, drvdata->dcr_len); 403 #endif 404 } 405 406 /* --------------------------------------------------------------------- 407 * OF bus binding 408 */ 409 410 static int xilinxfb_of_probe(struct platform_device *pdev) 411 { 412 const u32 *prop; 413 u32 tft_access = 0; 414 struct xilinxfb_platform_data pdata; 415 int size; 416 struct xilinxfb_drvdata *drvdata; 417 418 /* Copy with the default pdata (not a ptr reference!) */ 419 pdata = xilinx_fb_default_pdata; 420 421 /* Allocate the driver data region */ 422 drvdata = devm_kzalloc(&pdev->dev, sizeof(*drvdata), GFP_KERNEL); 423 if (!drvdata) 424 return -ENOMEM; 425 426 /* 427 * To check whether the core is connected directly to DCR or BUS 428 * interface and initialize the tft_access accordingly. 429 */ 430 of_property_read_u32(pdev->dev.of_node, "xlnx,dcr-splb-slave-if", 431 &tft_access); 432 433 /* 434 * Fill the resource structure if its direct BUS interface 435 * otherwise fill the dcr_host structure. 436 */ 437 if (tft_access) 438 drvdata->flags |= BUS_ACCESS_FLAG; 439 #ifdef CONFIG_PPC_DCR 440 else { 441 int start; 442 443 start = dcr_resource_start(pdev->dev.of_node, 0); 444 drvdata->dcr_len = dcr_resource_len(pdev->dev.of_node, 0); 445 drvdata->dcr_host = dcr_map(pdev->dev.of_node, start, drvdata->dcr_len); 446 if (!DCR_MAP_OK(drvdata->dcr_host)) { 447 dev_err(&pdev->dev, "invalid DCR address\n"); 448 return -ENODEV; 449 } 450 } 451 #endif 452 453 prop = of_get_property(pdev->dev.of_node, "phys-size", &size); 454 if ((prop) && (size >= sizeof(u32) * 2)) { 455 pdata.screen_width_mm = prop[0]; 456 pdata.screen_height_mm = prop[1]; 457 } 458 459 prop = of_get_property(pdev->dev.of_node, "resolution", &size); 460 if ((prop) && (size >= sizeof(u32) * 2)) { 461 pdata.xres = prop[0]; 462 pdata.yres = prop[1]; 463 } 464 465 prop = of_get_property(pdev->dev.of_node, "virtual-resolution", &size); 466 if ((prop) && (size >= sizeof(u32) * 2)) { 467 pdata.xvirt = prop[0]; 468 pdata.yvirt = prop[1]; 469 } 470 471 pdata.rotate_screen = of_property_read_bool(pdev->dev.of_node, "rotate-display"); 472 473 platform_set_drvdata(pdev, drvdata); 474 return xilinxfb_assign(pdev, drvdata, &pdata); 475 } 476 477 static int xilinxfb_of_remove(struct platform_device *op) 478 { 479 xilinxfb_release(&op->dev); 480 481 return 0; 482 } 483 484 /* Match table for of_platform binding */ 485 static const struct of_device_id xilinxfb_of_match[] = { 486 { .compatible = "xlnx,xps-tft-1.00.a", }, 487 { .compatible = "xlnx,xps-tft-2.00.a", }, 488 { .compatible = "xlnx,xps-tft-2.01.a", }, 489 { .compatible = "xlnx,plb-tft-cntlr-ref-1.00.a", }, 490 { .compatible = "xlnx,plb-dvi-cntlr-ref-1.00.c", }, 491 {}, 492 }; 493 MODULE_DEVICE_TABLE(of, xilinxfb_of_match); 494 495 static struct platform_driver xilinxfb_of_driver = { 496 .probe = xilinxfb_of_probe, 497 .remove = xilinxfb_of_remove, 498 .driver = { 499 .name = DRIVER_NAME, 500 .of_match_table = xilinxfb_of_match, 501 }, 502 }; 503 504 module_platform_driver(xilinxfb_of_driver); 505 506 MODULE_AUTHOR("MontaVista Software, Inc. <source@mvista.com>"); 507 MODULE_DESCRIPTION("Xilinx TFT frame buffer driver"); 508 MODULE_LICENSE("GPL"); 509