1 /*
2 * linux/drivers/video/vt8623fb.c - fbdev driver for
3 * integrated graphic core in VIA VT8623 [CLE266] chipset
4 *
5 * Copyright (c) 2006-2007 Ondrej Zajicek <santiago@crfreenet.org>
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file COPYING in the main directory of this archive for
9 * more details.
10 *
11 * Code is based on s3fb, some parts are from David Boucher's viafb
12 * (http://davesdomain.org.uk/viafb/)
13 */
14
15 #include <linux/aperture.h>
16 #include <linux/module.h>
17 #include <linux/kernel.h>
18 #include <linux/errno.h>
19 #include <linux/string.h>
20 #include <linux/mm.h>
21 #include <linux/tty.h>
22 #include <linux/delay.h>
23 #include <linux/fb.h>
24 #include <linux/svga.h>
25 #include <linux/init.h>
26 #include <linux/pci.h>
27 #include <linux/console.h> /* Why should fb driver call console functions? because console_lock() */
28 #include <video/vga.h>
29
30 struct vt8623fb_info {
31 char __iomem *mmio_base;
32 int wc_cookie;
33 struct vgastate state;
34 struct mutex open_lock;
35 unsigned int ref_count;
36 u32 pseudo_palette[16];
37 };
38
39
40
41 /* ------------------------------------------------------------------------- */
42
43 static const struct svga_fb_format vt8623fb_formats[] = {
44 { 0, {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0}, 0,
45 FB_TYPE_TEXT, FB_AUX_TEXT_SVGA_STEP8, FB_VISUAL_PSEUDOCOLOR, 16, 16},
46 { 4, {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0}, 0,
47 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_PSEUDOCOLOR, 16, 16},
48 { 4, {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0}, 1,
49 FB_TYPE_INTERLEAVED_PLANES, 1, FB_VISUAL_PSEUDOCOLOR, 16, 16},
50 { 8, {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0}, 0,
51 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_PSEUDOCOLOR, 8, 8},
52 /* {16, {10, 5, 0}, {5, 5, 0}, {0, 5, 0}, {0, 0, 0}, 0,
53 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 4, 4}, */
54 {16, {11, 5, 0}, {5, 6, 0}, {0, 5, 0}, {0, 0, 0}, 0,
55 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 4, 4},
56 {32, {16, 8, 0}, {8, 8, 0}, {0, 8, 0}, {0, 0, 0}, 0,
57 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 2, 2},
58 SVGA_FORMAT_END
59 };
60
61 static const struct svga_pll vt8623_pll = {2, 127, 2, 7, 0, 3,
62 60000, 300000, 14318};
63
64 /* CRT timing register sets */
65
66 static const struct vga_regset vt8623_h_total_regs[] = {{0x00, 0, 7}, {0x36, 3, 3}, VGA_REGSET_END};
67 static const struct vga_regset vt8623_h_display_regs[] = {{0x01, 0, 7}, VGA_REGSET_END};
68 static const struct vga_regset vt8623_h_blank_start_regs[] = {{0x02, 0, 7}, VGA_REGSET_END};
69 static const struct vga_regset vt8623_h_blank_end_regs[] = {{0x03, 0, 4}, {0x05, 7, 7}, {0x33, 5, 5}, VGA_REGSET_END};
70 static const struct vga_regset vt8623_h_sync_start_regs[] = {{0x04, 0, 7}, {0x33, 4, 4}, VGA_REGSET_END};
71 static const struct vga_regset vt8623_h_sync_end_regs[] = {{0x05, 0, 4}, VGA_REGSET_END};
72
73 static const struct vga_regset vt8623_v_total_regs[] = {{0x06, 0, 7}, {0x07, 0, 0}, {0x07, 5, 5}, {0x35, 0, 0}, VGA_REGSET_END};
74 static const struct vga_regset vt8623_v_display_regs[] = {{0x12, 0, 7}, {0x07, 1, 1}, {0x07, 6, 6}, {0x35, 2, 2}, VGA_REGSET_END};
75 static const struct vga_regset vt8623_v_blank_start_regs[] = {{0x15, 0, 7}, {0x07, 3, 3}, {0x09, 5, 5}, {0x35, 3, 3}, VGA_REGSET_END};
76 static const struct vga_regset vt8623_v_blank_end_regs[] = {{0x16, 0, 7}, VGA_REGSET_END};
77 static const struct vga_regset vt8623_v_sync_start_regs[] = {{0x10, 0, 7}, {0x07, 2, 2}, {0x07, 7, 7}, {0x35, 1, 1}, VGA_REGSET_END};
78 static const struct vga_regset vt8623_v_sync_end_regs[] = {{0x11, 0, 3}, VGA_REGSET_END};
79
80 static const struct vga_regset vt8623_offset_regs[] = {{0x13, 0, 7}, {0x35, 5, 7}, VGA_REGSET_END};
81 static const struct vga_regset vt8623_line_compare_regs[] = {{0x18, 0, 7}, {0x07, 4, 4}, {0x09, 6, 6}, {0x33, 0, 2}, {0x35, 4, 4}, VGA_REGSET_END};
82 static const struct vga_regset vt8623_fetch_count_regs[] = {{0x1C, 0, 7}, {0x1D, 0, 1}, VGA_REGSET_END};
83 static const struct vga_regset vt8623_start_address_regs[] = {{0x0d, 0, 7}, {0x0c, 0, 7}, {0x34, 0, 7}, {0x48, 0, 1}, VGA_REGSET_END};
84
85 static const struct svga_timing_regs vt8623_timing_regs = {
86 vt8623_h_total_regs, vt8623_h_display_regs, vt8623_h_blank_start_regs,
87 vt8623_h_blank_end_regs, vt8623_h_sync_start_regs, vt8623_h_sync_end_regs,
88 vt8623_v_total_regs, vt8623_v_display_regs, vt8623_v_blank_start_regs,
89 vt8623_v_blank_end_regs, vt8623_v_sync_start_regs, vt8623_v_sync_end_regs,
90 };
91
92
93 /* ------------------------------------------------------------------------- */
94
95
96 /* Module parameters */
97
98 static char *mode_option = "640x480-8@60";
99 static int mtrr = 1;
100
101 MODULE_AUTHOR("(c) 2006 Ondrej Zajicek <santiago@crfreenet.org>");
102 MODULE_LICENSE("GPL");
103 MODULE_DESCRIPTION("fbdev driver for integrated graphics core in VIA VT8623 [CLE266]");
104
105 module_param(mode_option, charp, 0644);
106 MODULE_PARM_DESC(mode_option, "Default video mode ('640x480-8@60', etc)");
107 module_param_named(mode, mode_option, charp, 0);
108 MODULE_PARM_DESC(mode, "Default video mode e.g. '648x480-8@60' (deprecated)");
109 module_param(mtrr, int, 0444);
110 MODULE_PARM_DESC(mtrr, "Enable write-combining with MTRR (1=enable, 0=disable, default=1)");
111
112
113 /* ------------------------------------------------------------------------- */
114
vt8623fb_tilecursor(struct fb_info * info,struct fb_tilecursor * cursor)115 static void vt8623fb_tilecursor(struct fb_info *info, struct fb_tilecursor *cursor)
116 {
117 struct vt8623fb_info *par = info->par;
118
119 svga_tilecursor(par->state.vgabase, info, cursor);
120 }
121
122 static struct fb_tile_ops vt8623fb_tile_ops = {
123 .fb_settile = svga_settile,
124 .fb_tilecopy = svga_tilecopy,
125 .fb_tilefill = svga_tilefill,
126 .fb_tileblit = svga_tileblit,
127 .fb_tilecursor = vt8623fb_tilecursor,
128 .fb_get_tilemax = svga_get_tilemax,
129 };
130
131
132 /* ------------------------------------------------------------------------- */
133
134
135 /* image data is MSB-first, fb structure is MSB-first too */
expand_color(u32 c)136 static inline u32 expand_color(u32 c)
137 {
138 return ((c & 1) | ((c & 2) << 7) | ((c & 4) << 14) | ((c & 8) << 21)) * 0xFF;
139 }
140
141 /* vt8623fb_iplan_imageblit silently assumes that almost everything is 8-pixel aligned */
vt8623fb_iplan_imageblit(struct fb_info * info,const struct fb_image * image)142 static void vt8623fb_iplan_imageblit(struct fb_info *info, const struct fb_image *image)
143 {
144 u32 fg = expand_color(image->fg_color);
145 u32 bg = expand_color(image->bg_color);
146 const u8 *src1, *src;
147 u8 __iomem *dst1;
148 u32 __iomem *dst;
149 u32 val;
150 int x, y;
151
152 src1 = image->data;
153 dst1 = info->screen_base + (image->dy * info->fix.line_length)
154 + ((image->dx / 8) * 4);
155
156 for (y = 0; y < image->height; y++) {
157 src = src1;
158 dst = (u32 __iomem *) dst1;
159 for (x = 0; x < image->width; x += 8) {
160 val = *(src++) * 0x01010101;
161 val = (val & fg) | (~val & bg);
162 fb_writel(val, dst++);
163 }
164 src1 += image->width / 8;
165 dst1 += info->fix.line_length;
166 }
167 }
168
169 /* vt8623fb_iplan_fillrect silently assumes that almost everything is 8-pixel aligned */
vt8623fb_iplan_fillrect(struct fb_info * info,const struct fb_fillrect * rect)170 static void vt8623fb_iplan_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
171 {
172 u32 fg = expand_color(rect->color);
173 u8 __iomem *dst1;
174 u32 __iomem *dst;
175 int x, y;
176
177 dst1 = info->screen_base + (rect->dy * info->fix.line_length)
178 + ((rect->dx / 8) * 4);
179
180 for (y = 0; y < rect->height; y++) {
181 dst = (u32 __iomem *) dst1;
182 for (x = 0; x < rect->width; x += 8) {
183 fb_writel(fg, dst++);
184 }
185 dst1 += info->fix.line_length;
186 }
187 }
188
189
190 /* image data is MSB-first, fb structure is high-nibble-in-low-byte-first */
expand_pixel(u32 c)191 static inline u32 expand_pixel(u32 c)
192 {
193 return (((c & 1) << 24) | ((c & 2) << 27) | ((c & 4) << 14) | ((c & 8) << 17) |
194 ((c & 16) << 4) | ((c & 32) << 7) | ((c & 64) >> 6) | ((c & 128) >> 3)) * 0xF;
195 }
196
197 /* vt8623fb_cfb4_imageblit silently assumes that almost everything is 8-pixel aligned */
vt8623fb_cfb4_imageblit(struct fb_info * info,const struct fb_image * image)198 static void vt8623fb_cfb4_imageblit(struct fb_info *info, const struct fb_image *image)
199 {
200 u32 fg = image->fg_color * 0x11111111;
201 u32 bg = image->bg_color * 0x11111111;
202 const u8 *src1, *src;
203 u8 __iomem *dst1;
204 u32 __iomem *dst;
205 u32 val;
206 int x, y;
207
208 src1 = image->data;
209 dst1 = info->screen_base + (image->dy * info->fix.line_length)
210 + ((image->dx / 8) * 4);
211
212 for (y = 0; y < image->height; y++) {
213 src = src1;
214 dst = (u32 __iomem *) dst1;
215 for (x = 0; x < image->width; x += 8) {
216 val = expand_pixel(*(src++));
217 val = (val & fg) | (~val & bg);
218 fb_writel(val, dst++);
219 }
220 src1 += image->width / 8;
221 dst1 += info->fix.line_length;
222 }
223 }
224
vt8623fb_imageblit(struct fb_info * info,const struct fb_image * image)225 static void vt8623fb_imageblit(struct fb_info *info, const struct fb_image *image)
226 {
227 if ((info->var.bits_per_pixel == 4) && (image->depth == 1)
228 && ((image->width % 8) == 0) && ((image->dx % 8) == 0)) {
229 if (info->fix.type == FB_TYPE_INTERLEAVED_PLANES)
230 vt8623fb_iplan_imageblit(info, image);
231 else
232 vt8623fb_cfb4_imageblit(info, image);
233 } else
234 cfb_imageblit(info, image);
235 }
236
vt8623fb_fillrect(struct fb_info * info,const struct fb_fillrect * rect)237 static void vt8623fb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
238 {
239 if ((info->var.bits_per_pixel == 4)
240 && ((rect->width % 8) == 0) && ((rect->dx % 8) == 0)
241 && (info->fix.type == FB_TYPE_INTERLEAVED_PLANES))
242 vt8623fb_iplan_fillrect(info, rect);
243 else
244 cfb_fillrect(info, rect);
245 }
246
247
248 /* ------------------------------------------------------------------------- */
249
250
vt8623_set_pixclock(struct fb_info * info,u32 pixclock)251 static void vt8623_set_pixclock(struct fb_info *info, u32 pixclock)
252 {
253 struct vt8623fb_info *par = info->par;
254 u16 m, n, r;
255 u8 regval;
256 int rv;
257
258 rv = svga_compute_pll(&vt8623_pll, 1000000000 / pixclock, &m, &n, &r, info->node);
259 if (rv < 0) {
260 fb_err(info, "cannot set requested pixclock, keeping old value\n");
261 return;
262 }
263
264 /* Set VGA misc register */
265 regval = vga_r(par->state.vgabase, VGA_MIS_R);
266 vga_w(par->state.vgabase, VGA_MIS_W, regval | VGA_MIS_ENB_PLL_LOAD);
267
268 /* Set clock registers */
269 vga_wseq(par->state.vgabase, 0x46, (n | (r << 6)));
270 vga_wseq(par->state.vgabase, 0x47, m);
271
272 udelay(1000);
273
274 /* PLL reset */
275 svga_wseq_mask(par->state.vgabase, 0x40, 0x02, 0x02);
276 svga_wseq_mask(par->state.vgabase, 0x40, 0x00, 0x02);
277 }
278
279
vt8623fb_open(struct fb_info * info,int user)280 static int vt8623fb_open(struct fb_info *info, int user)
281 {
282 struct vt8623fb_info *par = info->par;
283
284 mutex_lock(&(par->open_lock));
285 if (par->ref_count == 0) {
286 void __iomem *vgabase = par->state.vgabase;
287
288 memset(&(par->state), 0, sizeof(struct vgastate));
289 par->state.vgabase = vgabase;
290 par->state.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS | VGA_SAVE_CMAP;
291 par->state.num_crtc = 0xA2;
292 par->state.num_seq = 0x50;
293 save_vga(&(par->state));
294 }
295
296 par->ref_count++;
297 mutex_unlock(&(par->open_lock));
298
299 return 0;
300 }
301
vt8623fb_release(struct fb_info * info,int user)302 static int vt8623fb_release(struct fb_info *info, int user)
303 {
304 struct vt8623fb_info *par = info->par;
305
306 mutex_lock(&(par->open_lock));
307 if (par->ref_count == 0) {
308 mutex_unlock(&(par->open_lock));
309 return -EINVAL;
310 }
311
312 if (par->ref_count == 1)
313 restore_vga(&(par->state));
314
315 par->ref_count--;
316 mutex_unlock(&(par->open_lock));
317
318 return 0;
319 }
320
vt8623fb_check_var(struct fb_var_screeninfo * var,struct fb_info * info)321 static int vt8623fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
322 {
323 int rv, mem, step;
324
325 if (!var->pixclock)
326 return -EINVAL;
327
328 /* Find appropriate format */
329 rv = svga_match_format (vt8623fb_formats, var, NULL);
330 if (rv < 0)
331 {
332 fb_err(info, "unsupported mode requested\n");
333 return rv;
334 }
335
336 /* Do not allow to have real resoulution larger than virtual */
337 if (var->xres > var->xres_virtual)
338 var->xres_virtual = var->xres;
339
340 if (var->yres > var->yres_virtual)
341 var->yres_virtual = var->yres;
342
343 /* Round up xres_virtual to have proper alignment of lines */
344 step = vt8623fb_formats[rv].xresstep - 1;
345 var->xres_virtual = (var->xres_virtual+step) & ~step;
346
347 /* Check whether have enough memory */
348 mem = ((var->bits_per_pixel * var->xres_virtual) >> 3) * var->yres_virtual;
349 if (mem > info->screen_size)
350 {
351 fb_err(info, "not enough framebuffer memory (%d kB requested, %d kB available)\n",
352 mem >> 10, (unsigned int) (info->screen_size >> 10));
353 return -EINVAL;
354 }
355
356 /* Text mode is limited to 256 kB of memory */
357 if ((var->bits_per_pixel == 0) && (mem > (256*1024)))
358 {
359 fb_err(info, "text framebuffer size too large (%d kB requested, 256 kB possible)\n",
360 mem >> 10);
361 return -EINVAL;
362 }
363
364 rv = svga_check_timings (&vt8623_timing_regs, var, info->node);
365 if (rv < 0)
366 {
367 fb_err(info, "invalid timings requested\n");
368 return rv;
369 }
370
371 /* Interlaced mode not supported */
372 if (var->vmode & FB_VMODE_INTERLACED)
373 return -EINVAL;
374
375 return 0;
376 }
377
378
vt8623fb_set_par(struct fb_info * info)379 static int vt8623fb_set_par(struct fb_info *info)
380 {
381 u32 mode, offset_value, fetch_value, screen_size;
382 struct vt8623fb_info *par = info->par;
383 u32 bpp = info->var.bits_per_pixel;
384
385 if (bpp != 0) {
386 info->fix.ypanstep = 1;
387 info->fix.line_length = (info->var.xres_virtual * bpp) / 8;
388
389 info->flags &= ~FBINFO_MISC_TILEBLITTING;
390 info->tileops = NULL;
391
392 /* in 4bpp supports 8p wide tiles only, any tiles otherwise */
393 info->pixmap.blit_x = (bpp == 4) ? (1 << (8 - 1)) : (~(u32)0);
394 info->pixmap.blit_y = ~(u32)0;
395
396 offset_value = (info->var.xres_virtual * bpp) / 64;
397 fetch_value = ((info->var.xres * bpp) / 128) + 4;
398
399 if (bpp == 4)
400 fetch_value = (info->var.xres / 8) + 8; /* + 0 is OK */
401
402 screen_size = info->var.yres_virtual * info->fix.line_length;
403 } else {
404 info->fix.ypanstep = 16;
405 info->fix.line_length = 0;
406
407 info->flags |= FBINFO_MISC_TILEBLITTING;
408 info->tileops = &vt8623fb_tile_ops;
409
410 /* supports 8x16 tiles only */
411 info->pixmap.blit_x = 1 << (8 - 1);
412 info->pixmap.blit_y = 1 << (16 - 1);
413
414 offset_value = info->var.xres_virtual / 16;
415 fetch_value = (info->var.xres / 8) + 8;
416 screen_size = (info->var.xres_virtual * info->var.yres_virtual) / 64;
417 }
418
419 info->var.xoffset = 0;
420 info->var.yoffset = 0;
421 info->var.activate = FB_ACTIVATE_NOW;
422
423 /* Unlock registers */
424 svga_wseq_mask(par->state.vgabase, 0x10, 0x01, 0x01);
425 svga_wcrt_mask(par->state.vgabase, 0x11, 0x00, 0x80);
426 svga_wcrt_mask(par->state.vgabase, 0x47, 0x00, 0x01);
427
428 /* Device, screen and sync off */
429 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
430 svga_wcrt_mask(par->state.vgabase, 0x36, 0x30, 0x30);
431 svga_wcrt_mask(par->state.vgabase, 0x17, 0x00, 0x80);
432
433 /* Set default values */
434 svga_set_default_gfx_regs(par->state.vgabase);
435 svga_set_default_atc_regs(par->state.vgabase);
436 svga_set_default_seq_regs(par->state.vgabase);
437 svga_set_default_crt_regs(par->state.vgabase);
438 svga_wcrt_multi(par->state.vgabase, vt8623_line_compare_regs, 0xFFFFFFFF);
439 svga_wcrt_multi(par->state.vgabase, vt8623_start_address_regs, 0);
440
441 svga_wcrt_multi(par->state.vgabase, vt8623_offset_regs, offset_value);
442 svga_wseq_multi(par->state.vgabase, vt8623_fetch_count_regs, fetch_value);
443
444 /* Clear H/V Skew */
445 svga_wcrt_mask(par->state.vgabase, 0x03, 0x00, 0x60);
446 svga_wcrt_mask(par->state.vgabase, 0x05, 0x00, 0x60);
447
448 if (info->var.vmode & FB_VMODE_DOUBLE)
449 svga_wcrt_mask(par->state.vgabase, 0x09, 0x80, 0x80);
450 else
451 svga_wcrt_mask(par->state.vgabase, 0x09, 0x00, 0x80);
452
453 svga_wseq_mask(par->state.vgabase, 0x1E, 0xF0, 0xF0); // DI/DVP bus
454 svga_wseq_mask(par->state.vgabase, 0x2A, 0x0F, 0x0F); // DI/DVP bus
455 svga_wseq_mask(par->state.vgabase, 0x16, 0x08, 0xBF); // FIFO read threshold
456 vga_wseq(par->state.vgabase, 0x17, 0x1F); // FIFO depth
457 vga_wseq(par->state.vgabase, 0x18, 0x4E);
458 svga_wseq_mask(par->state.vgabase, 0x1A, 0x08, 0x08); // enable MMIO ?
459
460 vga_wcrt(par->state.vgabase, 0x32, 0x00);
461 vga_wcrt(par->state.vgabase, 0x34, 0x00);
462 vga_wcrt(par->state.vgabase, 0x6A, 0x80);
463 vga_wcrt(par->state.vgabase, 0x6A, 0xC0);
464
465 vga_wgfx(par->state.vgabase, 0x20, 0x00);
466 vga_wgfx(par->state.vgabase, 0x21, 0x00);
467 vga_wgfx(par->state.vgabase, 0x22, 0x00);
468
469 /* Set SR15 according to number of bits per pixel */
470 mode = svga_match_format(vt8623fb_formats, &(info->var), &(info->fix));
471 switch (mode) {
472 case 0:
473 fb_dbg(info, "text mode\n");
474 svga_set_textmode_vga_regs(par->state.vgabase);
475 svga_wseq_mask(par->state.vgabase, 0x15, 0x00, 0xFE);
476 svga_wcrt_mask(par->state.vgabase, 0x11, 0x60, 0x70);
477 break;
478 case 1:
479 fb_dbg(info, "4 bit pseudocolor\n");
480 vga_wgfx(par->state.vgabase, VGA_GFX_MODE, 0x40);
481 svga_wseq_mask(par->state.vgabase, 0x15, 0x20, 0xFE);
482 svga_wcrt_mask(par->state.vgabase, 0x11, 0x00, 0x70);
483 break;
484 case 2:
485 fb_dbg(info, "4 bit pseudocolor, planar\n");
486 svga_wseq_mask(par->state.vgabase, 0x15, 0x00, 0xFE);
487 svga_wcrt_mask(par->state.vgabase, 0x11, 0x00, 0x70);
488 break;
489 case 3:
490 fb_dbg(info, "8 bit pseudocolor\n");
491 svga_wseq_mask(par->state.vgabase, 0x15, 0x22, 0xFE);
492 break;
493 case 4:
494 fb_dbg(info, "5/6/5 truecolor\n");
495 svga_wseq_mask(par->state.vgabase, 0x15, 0xB6, 0xFE);
496 break;
497 case 5:
498 fb_dbg(info, "8/8/8 truecolor\n");
499 svga_wseq_mask(par->state.vgabase, 0x15, 0xAE, 0xFE);
500 break;
501 default:
502 printk(KERN_ERR "vt8623fb: unsupported mode - bug\n");
503 return (-EINVAL);
504 }
505
506 vt8623_set_pixclock(info, info->var.pixclock);
507 svga_set_timings(par->state.vgabase, &vt8623_timing_regs, &(info->var), 1, 1,
508 (info->var.vmode & FB_VMODE_DOUBLE) ? 2 : 1, 1,
509 1, info->node);
510
511 if (screen_size > info->screen_size)
512 screen_size = info->screen_size;
513 memset_io(info->screen_base, 0x00, screen_size);
514
515 /* Device and screen back on */
516 svga_wcrt_mask(par->state.vgabase, 0x17, 0x80, 0x80);
517 svga_wcrt_mask(par->state.vgabase, 0x36, 0x00, 0x30);
518 svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20);
519
520 return 0;
521 }
522
523
vt8623fb_setcolreg(u_int regno,u_int red,u_int green,u_int blue,u_int transp,struct fb_info * fb)524 static int vt8623fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
525 u_int transp, struct fb_info *fb)
526 {
527 switch (fb->var.bits_per_pixel) {
528 case 0:
529 case 4:
530 if (regno >= 16)
531 return -EINVAL;
532
533 outb(0x0F, VGA_PEL_MSK);
534 outb(regno, VGA_PEL_IW);
535 outb(red >> 10, VGA_PEL_D);
536 outb(green >> 10, VGA_PEL_D);
537 outb(blue >> 10, VGA_PEL_D);
538 break;
539 case 8:
540 if (regno >= 256)
541 return -EINVAL;
542
543 outb(0xFF, VGA_PEL_MSK);
544 outb(regno, VGA_PEL_IW);
545 outb(red >> 10, VGA_PEL_D);
546 outb(green >> 10, VGA_PEL_D);
547 outb(blue >> 10, VGA_PEL_D);
548 break;
549 case 16:
550 if (regno >= 16)
551 return 0;
552
553 if (fb->var.green.length == 5)
554 ((u32*)fb->pseudo_palette)[regno] = ((red & 0xF800) >> 1) |
555 ((green & 0xF800) >> 6) | ((blue & 0xF800) >> 11);
556 else if (fb->var.green.length == 6)
557 ((u32*)fb->pseudo_palette)[regno] = (red & 0xF800) |
558 ((green & 0xFC00) >> 5) | ((blue & 0xF800) >> 11);
559 else
560 return -EINVAL;
561 break;
562 case 24:
563 case 32:
564 if (regno >= 16)
565 return 0;
566
567 /* ((transp & 0xFF00) << 16) */
568 ((u32*)fb->pseudo_palette)[regno] = ((red & 0xFF00) << 8) |
569 (green & 0xFF00) | ((blue & 0xFF00) >> 8);
570 break;
571 default:
572 return -EINVAL;
573 }
574
575 return 0;
576 }
577
578
vt8623fb_blank(int blank_mode,struct fb_info * info)579 static int vt8623fb_blank(int blank_mode, struct fb_info *info)
580 {
581 struct vt8623fb_info *par = info->par;
582
583 switch (blank_mode) {
584 case FB_BLANK_UNBLANK:
585 fb_dbg(info, "unblank\n");
586 svga_wcrt_mask(par->state.vgabase, 0x36, 0x00, 0x30);
587 svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20);
588 break;
589 case FB_BLANK_NORMAL:
590 fb_dbg(info, "blank\n");
591 svga_wcrt_mask(par->state.vgabase, 0x36, 0x00, 0x30);
592 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
593 break;
594 case FB_BLANK_HSYNC_SUSPEND:
595 fb_dbg(info, "DPMS standby (hsync off)\n");
596 svga_wcrt_mask(par->state.vgabase, 0x36, 0x10, 0x30);
597 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
598 break;
599 case FB_BLANK_VSYNC_SUSPEND:
600 fb_dbg(info, "DPMS suspend (vsync off)\n");
601 svga_wcrt_mask(par->state.vgabase, 0x36, 0x20, 0x30);
602 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
603 break;
604 case FB_BLANK_POWERDOWN:
605 fb_dbg(info, "DPMS off (no sync)\n");
606 svga_wcrt_mask(par->state.vgabase, 0x36, 0x30, 0x30);
607 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
608 break;
609 }
610
611 return 0;
612 }
613
614
vt8623fb_pan_display(struct fb_var_screeninfo * var,struct fb_info * info)615 static int vt8623fb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
616 {
617 struct vt8623fb_info *par = info->par;
618 unsigned int offset;
619
620 /* Calculate the offset */
621 if (info->var.bits_per_pixel == 0) {
622 offset = (var->yoffset / 16) * info->var.xres_virtual
623 + var->xoffset;
624 offset = offset >> 3;
625 } else {
626 offset = (var->yoffset * info->fix.line_length) +
627 (var->xoffset * info->var.bits_per_pixel / 8);
628 offset = offset >> ((info->var.bits_per_pixel == 4) ? 2 : 1);
629 }
630
631 /* Set the offset */
632 svga_wcrt_multi(par->state.vgabase, vt8623_start_address_regs, offset);
633
634 return 0;
635 }
636
637
638 /* ------------------------------------------------------------------------- */
639
640
641 /* Frame buffer operations */
642
643 static const struct fb_ops vt8623fb_ops = {
644 .owner = THIS_MODULE,
645 .fb_open = vt8623fb_open,
646 .fb_release = vt8623fb_release,
647 .fb_check_var = vt8623fb_check_var,
648 .fb_set_par = vt8623fb_set_par,
649 .fb_setcolreg = vt8623fb_setcolreg,
650 .fb_blank = vt8623fb_blank,
651 .fb_pan_display = vt8623fb_pan_display,
652 .fb_fillrect = vt8623fb_fillrect,
653 .fb_copyarea = cfb_copyarea,
654 .fb_imageblit = vt8623fb_imageblit,
655 .fb_get_caps = svga_get_caps,
656 };
657
658
659 /* PCI probe */
660
vt8623_pci_probe(struct pci_dev * dev,const struct pci_device_id * id)661 static int vt8623_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
662 {
663 struct pci_bus_region bus_reg;
664 struct resource vga_res;
665 struct fb_info *info;
666 struct vt8623fb_info *par;
667 unsigned int memsize1, memsize2;
668 int rc;
669
670 /* Ignore secondary VGA device because there is no VGA arbitration */
671 if (! svga_primary_device(dev)) {
672 dev_info(&(dev->dev), "ignoring secondary device\n");
673 return -ENODEV;
674 }
675
676 rc = aperture_remove_conflicting_pci_devices(dev, "vt8623fb");
677 if (rc)
678 return rc;
679
680 /* Allocate and fill driver data structure */
681 info = framebuffer_alloc(sizeof(struct vt8623fb_info), &(dev->dev));
682 if (!info)
683 return -ENOMEM;
684
685 par = info->par;
686 mutex_init(&par->open_lock);
687
688 info->flags = FBINFO_PARTIAL_PAN_OK | FBINFO_HWACCEL_YPAN;
689 info->fbops = &vt8623fb_ops;
690
691 /* Prepare PCI device */
692
693 rc = pci_enable_device(dev);
694 if (rc < 0) {
695 dev_err(info->device, "cannot enable PCI device\n");
696 goto err_enable_device;
697 }
698
699 rc = pci_request_regions(dev, "vt8623fb");
700 if (rc < 0) {
701 dev_err(info->device, "cannot reserve framebuffer region\n");
702 goto err_request_regions;
703 }
704
705 info->fix.smem_start = pci_resource_start(dev, 0);
706 info->fix.smem_len = pci_resource_len(dev, 0);
707 info->fix.mmio_start = pci_resource_start(dev, 1);
708 info->fix.mmio_len = pci_resource_len(dev, 1);
709
710 /* Map physical IO memory address into kernel space */
711 info->screen_base = pci_iomap_wc(dev, 0, 0);
712 if (! info->screen_base) {
713 rc = -ENOMEM;
714 dev_err(info->device, "iomap for framebuffer failed\n");
715 goto err_iomap_1;
716 }
717
718 par->mmio_base = pci_iomap(dev, 1, 0);
719 if (! par->mmio_base) {
720 rc = -ENOMEM;
721 dev_err(info->device, "iomap for MMIO failed\n");
722 goto err_iomap_2;
723 }
724
725 bus_reg.start = 0;
726 bus_reg.end = 64 * 1024;
727
728 vga_res.flags = IORESOURCE_IO;
729
730 pcibios_bus_to_resource(dev->bus, &vga_res, &bus_reg);
731
732 par->state.vgabase = (void __iomem *) (unsigned long) vga_res.start;
733
734 /* Find how many physical memory there is on card */
735 memsize1 = (vga_rseq(par->state.vgabase, 0x34) + 1) >> 1;
736 memsize2 = vga_rseq(par->state.vgabase, 0x39) << 2;
737
738 if ((16 <= memsize1) && (memsize1 <= 64) && (memsize1 == memsize2))
739 info->screen_size = memsize1 << 20;
740 else {
741 dev_err(info->device, "memory size detection failed (%x %x), suppose 16 MB\n", memsize1, memsize2);
742 info->screen_size = 16 << 20;
743 }
744
745 info->fix.smem_len = info->screen_size;
746 strcpy(info->fix.id, "VIA VT8623");
747 info->fix.type = FB_TYPE_PACKED_PIXELS;
748 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
749 info->fix.ypanstep = 0;
750 info->fix.accel = FB_ACCEL_NONE;
751 info->pseudo_palette = (void*)par->pseudo_palette;
752
753 /* Prepare startup mode */
754
755 kernel_param_lock(THIS_MODULE);
756 rc = fb_find_mode(&(info->var), info, mode_option, NULL, 0, NULL, 8);
757 kernel_param_unlock(THIS_MODULE);
758 if (! ((rc == 1) || (rc == 2))) {
759 rc = -EINVAL;
760 dev_err(info->device, "mode %s not found\n", mode_option);
761 goto err_find_mode;
762 }
763
764 rc = fb_alloc_cmap(&info->cmap, 256, 0);
765 if (rc < 0) {
766 dev_err(info->device, "cannot allocate colormap\n");
767 goto err_alloc_cmap;
768 }
769
770 rc = register_framebuffer(info);
771 if (rc < 0) {
772 dev_err(info->device, "cannot register framebuffer\n");
773 goto err_reg_fb;
774 }
775
776 fb_info(info, "%s on %s, %d MB RAM\n",
777 info->fix.id, pci_name(dev), info->fix.smem_len >> 20);
778
779 /* Record a reference to the driver data */
780 pci_set_drvdata(dev, info);
781
782 if (mtrr)
783 par->wc_cookie = arch_phys_wc_add(info->fix.smem_start,
784 info->fix.smem_len);
785
786 return 0;
787
788 /* Error handling */
789 err_reg_fb:
790 fb_dealloc_cmap(&info->cmap);
791 err_alloc_cmap:
792 err_find_mode:
793 pci_iounmap(dev, par->mmio_base);
794 err_iomap_2:
795 pci_iounmap(dev, info->screen_base);
796 err_iomap_1:
797 pci_release_regions(dev);
798 err_request_regions:
799 /* pci_disable_device(dev); */
800 err_enable_device:
801 framebuffer_release(info);
802 return rc;
803 }
804
805 /* PCI remove */
806
vt8623_pci_remove(struct pci_dev * dev)807 static void vt8623_pci_remove(struct pci_dev *dev)
808 {
809 struct fb_info *info = pci_get_drvdata(dev);
810
811 if (info) {
812 struct vt8623fb_info *par = info->par;
813
814 arch_phys_wc_del(par->wc_cookie);
815 unregister_framebuffer(info);
816 fb_dealloc_cmap(&info->cmap);
817
818 pci_iounmap(dev, info->screen_base);
819 pci_iounmap(dev, par->mmio_base);
820 pci_release_regions(dev);
821 /* pci_disable_device(dev); */
822
823 framebuffer_release(info);
824 }
825 }
826
827
828 /* PCI suspend */
829
vt8623_pci_suspend(struct device * dev)830 static int __maybe_unused vt8623_pci_suspend(struct device *dev)
831 {
832 struct fb_info *info = dev_get_drvdata(dev);
833 struct vt8623fb_info *par = info->par;
834
835 dev_info(info->device, "suspend\n");
836
837 console_lock();
838 mutex_lock(&(par->open_lock));
839
840 if (par->ref_count == 0) {
841 mutex_unlock(&(par->open_lock));
842 console_unlock();
843 return 0;
844 }
845
846 fb_set_suspend(info, 1);
847
848 mutex_unlock(&(par->open_lock));
849 console_unlock();
850
851 return 0;
852 }
853
854
855 /* PCI resume */
856
vt8623_pci_resume(struct device * dev)857 static int __maybe_unused vt8623_pci_resume(struct device *dev)
858 {
859 struct fb_info *info = dev_get_drvdata(dev);
860 struct vt8623fb_info *par = info->par;
861
862 dev_info(info->device, "resume\n");
863
864 console_lock();
865 mutex_lock(&(par->open_lock));
866
867 if (par->ref_count == 0)
868 goto fail;
869
870 vt8623fb_set_par(info);
871 fb_set_suspend(info, 0);
872
873 fail:
874 mutex_unlock(&(par->open_lock));
875 console_unlock();
876
877 return 0;
878 }
879
880 static const struct dev_pm_ops vt8623_pci_pm_ops = {
881 #ifdef CONFIG_PM_SLEEP
882 .suspend = vt8623_pci_suspend,
883 .resume = vt8623_pci_resume,
884 .freeze = NULL,
885 .thaw = vt8623_pci_resume,
886 .poweroff = vt8623_pci_suspend,
887 .restore = vt8623_pci_resume,
888 #endif /* CONFIG_PM_SLEEP */
889 };
890
891 /* List of boards that we are trying to support */
892
893 static const struct pci_device_id vt8623_devices[] = {
894 {PCI_DEVICE(PCI_VENDOR_ID_VIA, 0x3122)},
895 {0, 0, 0, 0, 0, 0, 0}
896 };
897
898 MODULE_DEVICE_TABLE(pci, vt8623_devices);
899
900 static struct pci_driver vt8623fb_pci_driver = {
901 .name = "vt8623fb",
902 .id_table = vt8623_devices,
903 .probe = vt8623_pci_probe,
904 .remove = vt8623_pci_remove,
905 .driver.pm = &vt8623_pci_pm_ops,
906 };
907
908 /* Cleanup */
909
vt8623fb_cleanup(void)910 static void __exit vt8623fb_cleanup(void)
911 {
912 pr_debug("vt8623fb: cleaning up\n");
913 pci_unregister_driver(&vt8623fb_pci_driver);
914 }
915
916 /* Driver Initialisation */
917
vt8623fb_init(void)918 static int __init vt8623fb_init(void)
919 {
920
921 #ifndef MODULE
922 char *option = NULL;
923 #endif
924
925 if (fb_modesetting_disabled("vt8623fb"))
926 return -ENODEV;
927
928 #ifndef MODULE
929 if (fb_get_options("vt8623fb", &option))
930 return -ENODEV;
931
932 if (option && *option)
933 mode_option = option;
934 #endif
935
936 pr_debug("vt8623fb: initializing\n");
937 return pci_register_driver(&vt8623fb_pci_driver);
938 }
939
940 /* ------------------------------------------------------------------------- */
941
942 /* Modularization */
943
944 module_init(vt8623fb_init);
945 module_exit(vt8623fb_cleanup);
946