1 /* 2 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved. 3 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved. 4 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public 7 * License as published by the Free Software Foundation; 8 * either version 2, or (at your option) any later version. 9 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even 12 * the implied warranty of MERCHANTABILITY or FITNESS FOR 13 * A PARTICULAR PURPOSE.See the GNU General Public License 14 * for more details. 15 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 19 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 20 */ 21 #ifndef __CHIP_H__ 22 #define __CHIP_H__ 23 24 #include "global.h" 25 26 /***************************************/ 27 /* Definition Graphic Chip Information */ 28 /***************************************/ 29 30 #define PCI_VIA_VENDOR_ID 0x1106 31 32 /* Define VIA Graphic Chip Name */ 33 #define UNICHROME_CLE266 1 34 #define UNICHROME_CLE266_DID 0x3122 35 #define CLE266_REVISION_AX 0x0A 36 #define CLE266_REVISION_CX 0x0C 37 38 #define UNICHROME_K400 2 39 #define UNICHROME_K400_DID 0x7205 40 41 #define UNICHROME_K800 3 42 #define UNICHROME_K800_DID 0x3108 43 44 #define UNICHROME_PM800 4 45 #define UNICHROME_PM800_DID 0x3118 46 47 #define UNICHROME_CN700 5 48 #define UNICHROME_CN700_DID 0x3344 49 50 #define UNICHROME_CX700 6 51 #define UNICHROME_CX700_DID 0x3157 52 #define CX700_REVISION_700 0x0 53 #define CX700_REVISION_700M 0x1 54 #define CX700_REVISION_700M2 0x2 55 56 #define UNICHROME_CN750 7 57 #define UNICHROME_CN750_DID 0x3225 58 59 #define UNICHROME_K8M890 8 60 #define UNICHROME_K8M890_DID 0x3230 61 62 #define UNICHROME_P4M890 9 63 #define UNICHROME_P4M890_DID 0x3343 64 65 #define UNICHROME_P4M900 10 66 #define UNICHROME_P4M900_DID 0x3371 67 68 #define UNICHROME_VX800 11 69 #define UNICHROME_VX800_DID 0x1122 70 71 #define UNICHROME_VX855 12 72 #define UNICHROME_VX855_DID 0x5122 73 74 #define UNICHROME_VX900 13 75 #define UNICHROME_VX900_DID 0x7122 76 77 /**************************************************/ 78 /* Definition TMDS Trasmitter Information */ 79 /**************************************************/ 80 81 /* Definition TMDS Trasmitter Index */ 82 #define NON_TMDS_TRANSMITTER 0x00 83 #define VT1632_TMDS 0x01 84 #define INTEGRATED_TMDS 0x42 85 86 /* Definition TMDS Trasmitter I2C Slave Address */ 87 #define VT1632_TMDS_I2C_ADDR 0x10 88 89 /**************************************************/ 90 /* Definition LVDS Trasmitter Information */ 91 /**************************************************/ 92 93 /* Definition LVDS Trasmitter Index */ 94 #define NON_LVDS_TRANSMITTER 0x00 95 #define VT1631_LVDS 0x01 96 #define VT1636_LVDS 0x0E 97 #define INTEGRATED_LVDS 0x41 98 99 /* Definition Digital Transmitter Mode */ 100 #define TX_DATA_12_BITS 0x01 101 #define TX_DATA_24_BITS 0x02 102 #define TX_DATA_DDR_MODE 0x04 103 #define TX_DATA_SDR_MODE 0x08 104 105 /* Definition LVDS Trasmitter I2C Slave Address */ 106 #define VT1631_LVDS_I2C_ADDR 0x70 107 #define VT3271_LVDS_I2C_ADDR 0x80 108 #define VT1636_LVDS_I2C_ADDR 0x80 109 110 struct tmds_chip_information { 111 int tmds_chip_name; 112 int tmds_chip_slave_addr; 113 int output_interface; 114 int i2c_port; 115 }; 116 117 struct lvds_chip_information { 118 int lvds_chip_name; 119 int lvds_chip_slave_addr; 120 int output_interface; 121 int i2c_port; 122 }; 123 124 /* The type of 2D engine */ 125 enum via_2d_engine { 126 VIA_2D_ENG_H2, 127 VIA_2D_ENG_H5, 128 VIA_2D_ENG_M1, 129 }; 130 131 struct chip_information { 132 int gfx_chip_name; 133 int gfx_chip_revision; 134 enum via_2d_engine twod_engine; 135 struct tmds_chip_information tmds_chip_info; 136 struct lvds_chip_information lvds_chip_info; 137 struct lvds_chip_information lvds_chip_info2; 138 }; 139 140 struct tmds_setting_information { 141 int iga_path; 142 int h_active; 143 int v_active; 144 int max_pixel_clock; 145 }; 146 147 struct lvds_setting_information { 148 int iga_path; 149 int lcd_panel_hres; 150 int lcd_panel_vres; 151 int display_method; 152 int device_lcd_dualedge; 153 int LCDDithering; 154 int lcd_mode; 155 u32 vclk; /*panel mode clock value */ 156 }; 157 158 struct GFX_DPA_SETTING { 159 int ClkRangeIndex; 160 u8 DVP0; /* CR96[3:0] */ 161 u8 DVP0DataDri_S1; /* SR2A[5] */ 162 u8 DVP0DataDri_S; /* SR1B[1] */ 163 u8 DVP0ClockDri_S1; /* SR2A[4] */ 164 u8 DVP0ClockDri_S; /* SR1E[2] */ 165 u8 DVP1; /* CR9B[3:0] */ 166 u8 DVP1Driving; /* SR65[3:0], Data and Clock driving */ 167 u8 DFPHigh; /* CR97[3:0] */ 168 u8 DFPLow; /* CR99[3:0] */ 169 170 }; 171 172 struct VT1636_DPA_SETTING { 173 u8 CLK_SEL_ST1; 174 u8 CLK_SEL_ST2; 175 }; 176 #endif /* __CHIP_H__ */ 177