xref: /openbmc/linux/drivers/video/fbdev/tridentfb.c (revision f052febd)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Frame buffer driver for Trident TGUI, Blade and Image series
4  *
5  * Copyright 2001, 2002 - Jani Monoses   <jani@iv.ro>
6  * Copyright 2009 Krzysztof Helt <krzysztof.h1@wp.pl>
7  *
8  * CREDITS:(in order of appearance)
9  *	skeletonfb.c by Geert Uytterhoeven and other fb code in drivers/video
10  *	Special thanks ;) to Mattia Crivellini <tia@mclink.it>
11  *	much inspired by the XFree86 4.x Trident driver sources
12  *	by Alan Hourihane the FreeVGA project
13  *	Francesco Salvestrini <salvestrini@users.sf.net> XP support,
14  *	code, suggestions
15  * TODO:
16  *	timing value tweaking so it looks good on every monitor in every mode
17  */
18 
19 #include <linux/aperture.h>
20 #include <linux/module.h>
21 #include <linux/fb.h>
22 #include <linux/init.h>
23 #include <linux/pci.h>
24 #include <linux/slab.h>
25 
26 #include <linux/delay.h>
27 #include <video/vga.h>
28 #include <video/trident.h>
29 
30 #include <linux/i2c.h>
31 #include <linux/i2c-algo-bit.h>
32 
33 struct tridentfb_par {
34 	void __iomem *io_virt;	/* iospace virtual memory address */
35 	u32 pseudo_pal[16];
36 	int chip_id;
37 	int flatpanel;
38 	void (*init_accel) (struct tridentfb_par *, int, int);
39 	void (*wait_engine) (struct tridentfb_par *);
40 	void (*fill_rect)
41 		(struct tridentfb_par *par, u32, u32, u32, u32, u32, u32);
42 	void (*copy_rect)
43 		(struct tridentfb_par *par, u32, u32, u32, u32, u32, u32);
44 	void (*image_blit)
45 		(struct tridentfb_par *par, const char*,
46 		 u32, u32, u32, u32, u32, u32);
47 	unsigned char eng_oper;	/* engine operation... */
48 	bool ddc_registered;
49 	struct i2c_adapter ddc_adapter;
50 	struct i2c_algo_bit_data ddc_algo;
51 };
52 
53 static struct fb_fix_screeninfo tridentfb_fix = {
54 	.id = "Trident",
55 	.type = FB_TYPE_PACKED_PIXELS,
56 	.ypanstep = 1,
57 	.visual = FB_VISUAL_PSEUDOCOLOR,
58 	.accel = FB_ACCEL_NONE,
59 };
60 
61 /* defaults which are normally overriden by user values */
62 
63 /* video mode */
64 static char *mode_option;
65 static int bpp = 8;
66 
67 static int noaccel;
68 
69 static int center;
70 static int stretch;
71 
72 static int fp;
73 static int crt;
74 
75 static int memsize;
76 static int memdiff;
77 static int nativex;
78 
79 module_param(mode_option, charp, 0);
80 MODULE_PARM_DESC(mode_option, "Initial video mode e.g. '648x480-8@60'");
81 module_param_named(mode, mode_option, charp, 0);
82 MODULE_PARM_DESC(mode, "Initial video mode e.g. '648x480-8@60' (deprecated)");
83 module_param(bpp, int, 0);
84 module_param(center, int, 0);
85 module_param(stretch, int, 0);
86 module_param(noaccel, int, 0);
87 module_param(memsize, int, 0);
88 module_param(memdiff, int, 0);
89 module_param(nativex, int, 0);
90 module_param(fp, int, 0);
91 MODULE_PARM_DESC(fp, "Define if flatpanel is connected");
92 module_param(crt, int, 0);
93 MODULE_PARM_DESC(crt, "Define if CRT is connected");
94 
95 static inline int is_oldclock(int id)
96 {
97 	return	(id == TGUI9440) ||
98 		(id == TGUI9660) ||
99 		(id == CYBER9320);
100 }
101 
102 static inline int is_oldprotect(int id)
103 {
104 	return	is_oldclock(id) ||
105 		(id == PROVIDIA9685) ||
106 		(id == CYBER9382) ||
107 		(id == CYBER9385);
108 }
109 
110 static inline int is_blade(int id)
111 {
112 	return	(id == BLADE3D) ||
113 		(id == CYBERBLADEE4) ||
114 		(id == CYBERBLADEi7) ||
115 		(id == CYBERBLADEi7D) ||
116 		(id == CYBERBLADEi1) ||
117 		(id == CYBERBLADEi1D) ||
118 		(id == CYBERBLADEAi1) ||
119 		(id == CYBERBLADEAi1D);
120 }
121 
122 static inline int is_xp(int id)
123 {
124 	return	(id == CYBERBLADEXPAi1) ||
125 		(id == CYBERBLADEXPm8) ||
126 		(id == CYBERBLADEXPm16);
127 }
128 
129 static inline int is3Dchip(int id)
130 {
131 	return	is_blade(id) || is_xp(id) ||
132 		(id == CYBER9397) || (id == CYBER9397DVD) ||
133 		(id == CYBER9520) || (id == CYBER9525DVD) ||
134 		(id == IMAGE975) || (id == IMAGE985);
135 }
136 
137 static inline int iscyber(int id)
138 {
139 	switch (id) {
140 	case CYBER9388:
141 	case CYBER9382:
142 	case CYBER9385:
143 	case CYBER9397:
144 	case CYBER9397DVD:
145 	case CYBER9520:
146 	case CYBER9525DVD:
147 	case CYBERBLADEE4:
148 	case CYBERBLADEi7D:
149 	case CYBERBLADEi1:
150 	case CYBERBLADEi1D:
151 	case CYBERBLADEAi1:
152 	case CYBERBLADEAi1D:
153 	case CYBERBLADEXPAi1:
154 		return 1;
155 
156 	case CYBER9320:
157 	case CYBERBLADEi7:	/* VIA MPV4 integrated version */
158 	default:
159 		/* case CYBERBLDAEXPm8:  Strange */
160 		/* case CYBERBLDAEXPm16: Strange */
161 		return 0;
162 	}
163 }
164 
165 static inline void t_outb(struct tridentfb_par *p, u8 val, u16 reg)
166 {
167 	fb_writeb(val, p->io_virt + reg);
168 }
169 
170 static inline u8 t_inb(struct tridentfb_par *p, u16 reg)
171 {
172 	return fb_readb(p->io_virt + reg);
173 }
174 
175 static inline void writemmr(struct tridentfb_par *par, u16 r, u32 v)
176 {
177 	fb_writel(v, par->io_virt + r);
178 }
179 
180 static inline u32 readmmr(struct tridentfb_par *par, u16 r)
181 {
182 	return fb_readl(par->io_virt + r);
183 }
184 
185 #define DDC_SDA_TGUI		BIT(0)
186 #define DDC_SCL_TGUI		BIT(1)
187 #define DDC_SCL_DRIVE_TGUI	BIT(2)
188 #define DDC_SDA_DRIVE_TGUI	BIT(3)
189 #define DDC_MASK_TGUI		(DDC_SCL_DRIVE_TGUI | DDC_SDA_DRIVE_TGUI)
190 
191 static void tridentfb_ddc_setscl_tgui(void *data, int val)
192 {
193 	struct tridentfb_par *par = data;
194 	u8 reg = vga_mm_rcrt(par->io_virt, I2C) & DDC_MASK_TGUI;
195 
196 	if (val)
197 		reg &= ~DDC_SCL_DRIVE_TGUI; /* disable drive - don't drive hi */
198 	else
199 		reg |= DDC_SCL_DRIVE_TGUI; /* drive low */
200 
201 	vga_mm_wcrt(par->io_virt, I2C, reg);
202 }
203 
204 static void tridentfb_ddc_setsda_tgui(void *data, int val)
205 {
206 	struct tridentfb_par *par = data;
207 	u8 reg = vga_mm_rcrt(par->io_virt, I2C) & DDC_MASK_TGUI;
208 
209 	if (val)
210 		reg &= ~DDC_SDA_DRIVE_TGUI; /* disable drive - don't drive hi */
211 	else
212 		reg |= DDC_SDA_DRIVE_TGUI; /* drive low */
213 
214 	vga_mm_wcrt(par->io_virt, I2C, reg);
215 }
216 
217 static int tridentfb_ddc_getsda_tgui(void *data)
218 {
219 	struct tridentfb_par *par = data;
220 
221 	return !!(vga_mm_rcrt(par->io_virt, I2C) & DDC_SDA_TGUI);
222 }
223 
224 #define DDC_SDA_IN	BIT(0)
225 #define DDC_SCL_OUT	BIT(1)
226 #define DDC_SDA_OUT	BIT(3)
227 #define DDC_SCL_IN	BIT(6)
228 #define DDC_MASK	(DDC_SCL_OUT | DDC_SDA_OUT)
229 
230 static void tridentfb_ddc_setscl(void *data, int val)
231 {
232 	struct tridentfb_par *par = data;
233 	unsigned char reg;
234 
235 	reg = vga_mm_rcrt(par->io_virt, I2C) & DDC_MASK;
236 	if (val)
237 		reg |= DDC_SCL_OUT;
238 	else
239 		reg &= ~DDC_SCL_OUT;
240 	vga_mm_wcrt(par->io_virt, I2C, reg);
241 }
242 
243 static void tridentfb_ddc_setsda(void *data, int val)
244 {
245 	struct tridentfb_par *par = data;
246 	unsigned char reg;
247 
248 	reg = vga_mm_rcrt(par->io_virt, I2C) & DDC_MASK;
249 	if (!val)
250 		reg |= DDC_SDA_OUT;
251 	else
252 		reg &= ~DDC_SDA_OUT;
253 	vga_mm_wcrt(par->io_virt, I2C, reg);
254 }
255 
256 static int tridentfb_ddc_getscl(void *data)
257 {
258 	struct tridentfb_par *par = data;
259 
260 	return !!(vga_mm_rcrt(par->io_virt, I2C) & DDC_SCL_IN);
261 }
262 
263 static int tridentfb_ddc_getsda(void *data)
264 {
265 	struct tridentfb_par *par = data;
266 
267 	return !!(vga_mm_rcrt(par->io_virt, I2C) & DDC_SDA_IN);
268 }
269 
270 static int tridentfb_setup_ddc_bus(struct fb_info *info)
271 {
272 	struct tridentfb_par *par = info->par;
273 
274 	strscpy(par->ddc_adapter.name, info->fix.id,
275 		sizeof(par->ddc_adapter.name));
276 	par->ddc_adapter.owner		= THIS_MODULE;
277 	par->ddc_adapter.class		= I2C_CLASS_DDC;
278 	par->ddc_adapter.algo_data	= &par->ddc_algo;
279 	par->ddc_adapter.dev.parent	= info->device;
280 	if (is_oldclock(par->chip_id)) { /* not sure if this check is OK */
281 		par->ddc_algo.setsda	= tridentfb_ddc_setsda_tgui;
282 		par->ddc_algo.setscl	= tridentfb_ddc_setscl_tgui;
283 		par->ddc_algo.getsda	= tridentfb_ddc_getsda_tgui;
284 		/* no getscl */
285 	} else {
286 		par->ddc_algo.setsda	= tridentfb_ddc_setsda;
287 		par->ddc_algo.setscl	= tridentfb_ddc_setscl;
288 		par->ddc_algo.getsda	= tridentfb_ddc_getsda;
289 		par->ddc_algo.getscl	= tridentfb_ddc_getscl;
290 	}
291 	par->ddc_algo.udelay		= 10;
292 	par->ddc_algo.timeout		= 20;
293 	par->ddc_algo.data		= par;
294 
295 	i2c_set_adapdata(&par->ddc_adapter, par);
296 
297 	return i2c_bit_add_bus(&par->ddc_adapter);
298 }
299 
300 /*
301  * Blade specific acceleration.
302  */
303 
304 #define point(x, y) ((y) << 16 | (x))
305 
306 static void blade_init_accel(struct tridentfb_par *par, int pitch, int bpp)
307 {
308 	int v1 = (pitch >> 3) << 20;
309 	int tmp = bpp == 24 ? 2 : (bpp >> 4);
310 	int v2 = v1 | (tmp << 29);
311 
312 	writemmr(par, 0x21C0, v2);
313 	writemmr(par, 0x21C4, v2);
314 	writemmr(par, 0x21B8, v2);
315 	writemmr(par, 0x21BC, v2);
316 	writemmr(par, 0x21D0, v1);
317 	writemmr(par, 0x21D4, v1);
318 	writemmr(par, 0x21C8, v1);
319 	writemmr(par, 0x21CC, v1);
320 	writemmr(par, 0x216C, 0);
321 }
322 
323 static void blade_wait_engine(struct tridentfb_par *par)
324 {
325 	while (readmmr(par, STATUS) & 0xFA800000)
326 		cpu_relax();
327 }
328 
329 static void blade_fill_rect(struct tridentfb_par *par,
330 			    u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop)
331 {
332 	writemmr(par, COLOR, c);
333 	writemmr(par, ROP, rop ? ROP_X : ROP_S);
334 	writemmr(par, CMD, 0x20000000 | 1 << 19 | 1 << 4 | 2 << 2);
335 
336 	writemmr(par, DST1, point(x, y));
337 	writemmr(par, DST2, point(x + w - 1, y + h - 1));
338 }
339 
340 static void blade_image_blit(struct tridentfb_par *par, const char *data,
341 			     u32 x, u32 y, u32 w, u32 h, u32 c, u32 b)
342 {
343 	unsigned size = ((w + 31) >> 5) * h;
344 
345 	writemmr(par, COLOR, c);
346 	writemmr(par, BGCOLOR, b);
347 	writemmr(par, CMD, 0xa0000000 | 3 << 19);
348 
349 	writemmr(par, DST1, point(x, y));
350 	writemmr(par, DST2, point(x + w - 1, y + h - 1));
351 
352 	iowrite32_rep(par->io_virt + 0x10000, data, size);
353 }
354 
355 static void blade_copy_rect(struct tridentfb_par *par,
356 			    u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h)
357 {
358 	int direction = 2;
359 	u32 s1 = point(x1, y1);
360 	u32 s2 = point(x1 + w - 1, y1 + h - 1);
361 	u32 d1 = point(x2, y2);
362 	u32 d2 = point(x2 + w - 1, y2 + h - 1);
363 
364 	if ((y1 > y2) || ((y1 == y2) && (x1 > x2)))
365 		direction = 0;
366 
367 	writemmr(par, ROP, ROP_S);
368 	writemmr(par, CMD, 0xE0000000 | 1 << 19 | 1 << 4 | 1 << 2 | direction);
369 
370 	writemmr(par, SRC1, direction ? s2 : s1);
371 	writemmr(par, SRC2, direction ? s1 : s2);
372 	writemmr(par, DST1, direction ? d2 : d1);
373 	writemmr(par, DST2, direction ? d1 : d2);
374 }
375 
376 /*
377  * BladeXP specific acceleration functions
378  */
379 
380 static void xp_init_accel(struct tridentfb_par *par, int pitch, int bpp)
381 {
382 	unsigned char x = bpp == 24 ? 3 : (bpp >> 4);
383 	int v1 = pitch << (bpp == 24 ? 20 : (18 + x));
384 
385 	switch (pitch << (bpp >> 3)) {
386 	case 8192:
387 	case 512:
388 		x |= 0x00;
389 		break;
390 	case 1024:
391 		x |= 0x04;
392 		break;
393 	case 2048:
394 		x |= 0x08;
395 		break;
396 	case 4096:
397 		x |= 0x0C;
398 		break;
399 	}
400 
401 	t_outb(par, x, 0x2125);
402 
403 	par->eng_oper = x | 0x40;
404 
405 	writemmr(par, 0x2154, v1);
406 	writemmr(par, 0x2150, v1);
407 	t_outb(par, 3, 0x2126);
408 }
409 
410 static void xp_wait_engine(struct tridentfb_par *par)
411 {
412 	int count = 0;
413 	int timeout = 0;
414 
415 	while (t_inb(par, STATUS) & 0x80) {
416 		count++;
417 		if (count == 10000000) {
418 			/* Timeout */
419 			count = 9990000;
420 			timeout++;
421 			if (timeout == 8) {
422 				/* Reset engine */
423 				t_outb(par, 0x00, STATUS);
424 				return;
425 			}
426 		}
427 		cpu_relax();
428 	}
429 }
430 
431 static void xp_fill_rect(struct tridentfb_par *par,
432 			 u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop)
433 {
434 	writemmr(par, 0x2127, ROP_P);
435 	writemmr(par, 0x2158, c);
436 	writemmr(par, DRAWFL, 0x4000);
437 	writemmr(par, OLDDIM, point(h, w));
438 	writemmr(par, OLDDST, point(y, x));
439 	t_outb(par, 0x01, OLDCMD);
440 	t_outb(par, par->eng_oper, 0x2125);
441 }
442 
443 static void xp_copy_rect(struct tridentfb_par *par,
444 			 u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h)
445 {
446 	u32 x1_tmp, x2_tmp, y1_tmp, y2_tmp;
447 	int direction = 0x0004;
448 
449 	if ((x1 < x2) && (y1 == y2)) {
450 		direction |= 0x0200;
451 		x1_tmp = x1 + w - 1;
452 		x2_tmp = x2 + w - 1;
453 	} else {
454 		x1_tmp = x1;
455 		x2_tmp = x2;
456 	}
457 
458 	if (y1 < y2) {
459 		direction |= 0x0100;
460 		y1_tmp = y1 + h - 1;
461 		y2_tmp = y2 + h - 1;
462 	} else {
463 		y1_tmp = y1;
464 		y2_tmp = y2;
465 	}
466 
467 	writemmr(par, DRAWFL, direction);
468 	t_outb(par, ROP_S, 0x2127);
469 	writemmr(par, OLDSRC, point(y1_tmp, x1_tmp));
470 	writemmr(par, OLDDST, point(y2_tmp, x2_tmp));
471 	writemmr(par, OLDDIM, point(h, w));
472 	t_outb(par, 0x01, OLDCMD);
473 }
474 
475 /*
476  * Image specific acceleration functions
477  */
478 static void image_init_accel(struct tridentfb_par *par, int pitch, int bpp)
479 {
480 	int tmp = bpp == 24 ? 2: (bpp >> 4);
481 
482 	writemmr(par, 0x2120, 0xF0000000);
483 	writemmr(par, 0x2120, 0x40000000 | tmp);
484 	writemmr(par, 0x2120, 0x80000000);
485 	writemmr(par, 0x2144, 0x00000000);
486 	writemmr(par, 0x2148, 0x00000000);
487 	writemmr(par, 0x2150, 0x00000000);
488 	writemmr(par, 0x2154, 0x00000000);
489 	writemmr(par, 0x2120, 0x60000000 | (pitch << 16) | pitch);
490 	writemmr(par, 0x216C, 0x00000000);
491 	writemmr(par, 0x2170, 0x00000000);
492 	writemmr(par, 0x217C, 0x00000000);
493 	writemmr(par, 0x2120, 0x10000000);
494 	writemmr(par, 0x2130, (2047 << 16) | 2047);
495 }
496 
497 static void image_wait_engine(struct tridentfb_par *par)
498 {
499 	while (readmmr(par, 0x2164) & 0xF0000000)
500 		cpu_relax();
501 }
502 
503 static void image_fill_rect(struct tridentfb_par *par,
504 			    u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop)
505 {
506 	writemmr(par, 0x2120, 0x80000000);
507 	writemmr(par, 0x2120, 0x90000000 | ROP_S);
508 
509 	writemmr(par, 0x2144, c);
510 
511 	writemmr(par, DST1, point(x, y));
512 	writemmr(par, DST2, point(x + w - 1, y + h - 1));
513 
514 	writemmr(par, 0x2124, 0x80000000 | 3 << 22 | 1 << 10 | 1 << 9);
515 }
516 
517 static void image_copy_rect(struct tridentfb_par *par,
518 			    u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h)
519 {
520 	int direction = 0x4;
521 	u32 s1 = point(x1, y1);
522 	u32 s2 = point(x1 + w - 1, y1 + h - 1);
523 	u32 d1 = point(x2, y2);
524 	u32 d2 = point(x2 + w - 1, y2 + h - 1);
525 
526 	if ((y1 > y2) || ((y1 == y2) && (x1 > x2)))
527 		direction = 0;
528 
529 	writemmr(par, 0x2120, 0x80000000);
530 	writemmr(par, 0x2120, 0x90000000 | ROP_S);
531 
532 	writemmr(par, SRC1, direction ? s2 : s1);
533 	writemmr(par, SRC2, direction ? s1 : s2);
534 	writemmr(par, DST1, direction ? d2 : d1);
535 	writemmr(par, DST2, direction ? d1 : d2);
536 	writemmr(par, 0x2124,
537 		 0x80000000 | 1 << 22 | 1 << 10 | 1 << 7 | direction);
538 }
539 
540 /*
541  * TGUI 9440/96XX acceleration
542  */
543 
544 static void tgui_init_accel(struct tridentfb_par *par, int pitch, int bpp)
545 {
546 	unsigned char x = bpp == 24 ? 3 : (bpp >> 4);
547 
548 	/* disable clipping */
549 	writemmr(par, 0x2148, 0);
550 	writemmr(par, 0x214C, point(4095, 2047));
551 
552 	switch ((pitch * bpp) / 8) {
553 	case 8192:
554 	case 512:
555 		x |= 0x00;
556 		break;
557 	case 1024:
558 		x |= 0x04;
559 		break;
560 	case 2048:
561 		x |= 0x08;
562 		break;
563 	case 4096:
564 		x |= 0x0C;
565 		break;
566 	}
567 
568 	fb_writew(x, par->io_virt + 0x2122);
569 }
570 
571 static void tgui_fill_rect(struct tridentfb_par *par,
572 			   u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop)
573 {
574 	t_outb(par, ROP_P, 0x2127);
575 	writemmr(par, OLDCLR, c);
576 	writemmr(par, DRAWFL, 0x4020);
577 	writemmr(par, OLDDIM, point(w - 1, h - 1));
578 	writemmr(par, OLDDST, point(x, y));
579 	t_outb(par, 1, OLDCMD);
580 }
581 
582 static void tgui_copy_rect(struct tridentfb_par *par,
583 			   u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h)
584 {
585 	int flags = 0;
586 	u16 x1_tmp, x2_tmp, y1_tmp, y2_tmp;
587 
588 	if ((x1 < x2) && (y1 == y2)) {
589 		flags |= 0x0200;
590 		x1_tmp = x1 + w - 1;
591 		x2_tmp = x2 + w - 1;
592 	} else {
593 		x1_tmp = x1;
594 		x2_tmp = x2;
595 	}
596 
597 	if (y1 < y2) {
598 		flags |= 0x0100;
599 		y1_tmp = y1 + h - 1;
600 		y2_tmp = y2 + h - 1;
601 	} else {
602 		y1_tmp = y1;
603 		y2_tmp = y2;
604 	}
605 
606 	writemmr(par, DRAWFL, 0x4 | flags);
607 	t_outb(par, ROP_S, 0x2127);
608 	writemmr(par, OLDSRC, point(x1_tmp, y1_tmp));
609 	writemmr(par, OLDDST, point(x2_tmp, y2_tmp));
610 	writemmr(par, OLDDIM, point(w - 1, h - 1));
611 	t_outb(par, 1, OLDCMD);
612 }
613 
614 /*
615  * Accel functions called by the upper layers
616  */
617 static void tridentfb_fillrect(struct fb_info *info,
618 			       const struct fb_fillrect *fr)
619 {
620 	struct tridentfb_par *par = info->par;
621 	int col;
622 
623 	if (info->flags & FBINFO_HWACCEL_DISABLED) {
624 		cfb_fillrect(info, fr);
625 		return;
626 	}
627 	if (info->var.bits_per_pixel == 8) {
628 		col = fr->color;
629 		col |= col << 8;
630 		col |= col << 16;
631 	} else
632 		col = ((u32 *)(info->pseudo_palette))[fr->color];
633 
634 	par->wait_engine(par);
635 	par->fill_rect(par, fr->dx, fr->dy, fr->width,
636 		       fr->height, col, fr->rop);
637 }
638 
639 static void tridentfb_imageblit(struct fb_info *info,
640 				const struct fb_image *img)
641 {
642 	struct tridentfb_par *par = info->par;
643 	int col, bgcol;
644 
645 	if ((info->flags & FBINFO_HWACCEL_DISABLED) || img->depth != 1) {
646 		cfb_imageblit(info, img);
647 		return;
648 	}
649 	if (info->var.bits_per_pixel == 8) {
650 		col = img->fg_color;
651 		col |= col << 8;
652 		col |= col << 16;
653 		bgcol = img->bg_color;
654 		bgcol |= bgcol << 8;
655 		bgcol |= bgcol << 16;
656 	} else {
657 		col = ((u32 *)(info->pseudo_palette))[img->fg_color];
658 		bgcol = ((u32 *)(info->pseudo_palette))[img->bg_color];
659 	}
660 
661 	par->wait_engine(par);
662 	if (par->image_blit)
663 		par->image_blit(par, img->data, img->dx, img->dy,
664 				img->width, img->height, col, bgcol);
665 	else
666 		cfb_imageblit(info, img);
667 }
668 
669 static void tridentfb_copyarea(struct fb_info *info,
670 			       const struct fb_copyarea *ca)
671 {
672 	struct tridentfb_par *par = info->par;
673 
674 	if (info->flags & FBINFO_HWACCEL_DISABLED) {
675 		cfb_copyarea(info, ca);
676 		return;
677 	}
678 	par->wait_engine(par);
679 	par->copy_rect(par, ca->sx, ca->sy, ca->dx, ca->dy,
680 		       ca->width, ca->height);
681 }
682 
683 static int tridentfb_sync(struct fb_info *info)
684 {
685 	struct tridentfb_par *par = info->par;
686 
687 	if (!(info->flags & FBINFO_HWACCEL_DISABLED))
688 		par->wait_engine(par);
689 	return 0;
690 }
691 
692 /*
693  * Hardware access functions
694  */
695 
696 static inline unsigned char read3X4(struct tridentfb_par *par, int reg)
697 {
698 	return vga_mm_rcrt(par->io_virt, reg);
699 }
700 
701 static inline void write3X4(struct tridentfb_par *par, int reg,
702 			    unsigned char val)
703 {
704 	vga_mm_wcrt(par->io_virt, reg, val);
705 }
706 
707 static inline unsigned char read3CE(struct tridentfb_par *par,
708 				    unsigned char reg)
709 {
710 	return vga_mm_rgfx(par->io_virt, reg);
711 }
712 
713 static inline void writeAttr(struct tridentfb_par *par, int reg,
714 			     unsigned char val)
715 {
716 	fb_readb(par->io_virt + VGA_IS1_RC);	/* flip-flop to index */
717 	vga_mm_wattr(par->io_virt, reg, val);
718 }
719 
720 static inline void write3CE(struct tridentfb_par *par, int reg,
721 			    unsigned char val)
722 {
723 	vga_mm_wgfx(par->io_virt, reg, val);
724 }
725 
726 static void enable_mmio(struct tridentfb_par *par)
727 {
728 	/* Goto New Mode */
729 	vga_io_rseq(0x0B);
730 
731 	/* Unprotect registers */
732 	vga_io_wseq(NewMode1, 0x80);
733 	if (!is_oldprotect(par->chip_id))
734 		vga_io_wseq(Protection, 0x92);
735 
736 	/* Enable MMIO */
737 	outb(PCIReg, 0x3D4);
738 	outb(inb(0x3D5) | 0x01, 0x3D5);
739 }
740 
741 static void disable_mmio(struct tridentfb_par *par)
742 {
743 	/* Goto New Mode */
744 	vga_mm_rseq(par->io_virt, 0x0B);
745 
746 	/* Unprotect registers */
747 	vga_mm_wseq(par->io_virt, NewMode1, 0x80);
748 	if (!is_oldprotect(par->chip_id))
749 		vga_mm_wseq(par->io_virt, Protection, 0x92);
750 
751 	/* Disable MMIO */
752 	t_outb(par, PCIReg, 0x3D4);
753 	t_outb(par, t_inb(par, 0x3D5) & ~0x01, 0x3D5);
754 }
755 
756 static inline void crtc_unlock(struct tridentfb_par *par)
757 {
758 	write3X4(par, VGA_CRTC_V_SYNC_END,
759 		 read3X4(par, VGA_CRTC_V_SYNC_END) & 0x7F);
760 }
761 
762 /*  Return flat panel's maximum x resolution */
763 static int get_nativex(struct tridentfb_par *par)
764 {
765 	int x, y, tmp;
766 
767 	if (nativex)
768 		return nativex;
769 
770 	tmp = (read3CE(par, VertStretch) >> 4) & 3;
771 
772 	switch (tmp) {
773 	case 0:
774 		x = 1280; y = 1024;
775 		break;
776 	case 2:
777 		x = 1024; y = 768;
778 		break;
779 	case 3:
780 		x = 800; y = 600;
781 		break;
782 	case 1:
783 	default:
784 		x = 640;  y = 480;
785 		break;
786 	}
787 
788 	output("%dx%d flat panel found\n", x, y);
789 	return x;
790 }
791 
792 /* Set pitch */
793 static inline void set_lwidth(struct tridentfb_par *par, int width)
794 {
795 	write3X4(par, VGA_CRTC_OFFSET, width & 0xFF);
796 	/* chips older than TGUI9660 have only 1 width bit in AddColReg */
797 	/* touching the other one breaks I2C/DDC */
798 	if (par->chip_id == TGUI9440 || par->chip_id == CYBER9320)
799 		write3X4(par, AddColReg,
800 		     (read3X4(par, AddColReg) & 0xEF) | ((width & 0x100) >> 4));
801 	else
802 		write3X4(par, AddColReg,
803 		     (read3X4(par, AddColReg) & 0xCF) | ((width & 0x300) >> 4));
804 }
805 
806 /* For resolutions smaller than FP resolution stretch */
807 static void screen_stretch(struct tridentfb_par *par)
808 {
809 	if (par->chip_id != CYBERBLADEXPAi1)
810 		write3CE(par, BiosReg, 0);
811 	else
812 		write3CE(par, BiosReg, 8);
813 	write3CE(par, VertStretch, (read3CE(par, VertStretch) & 0x7C) | 1);
814 	write3CE(par, HorStretch, (read3CE(par, HorStretch) & 0x7C) | 1);
815 }
816 
817 /* For resolutions smaller than FP resolution center */
818 static inline void screen_center(struct tridentfb_par *par)
819 {
820 	write3CE(par, VertStretch, (read3CE(par, VertStretch) & 0x7C) | 0x80);
821 	write3CE(par, HorStretch, (read3CE(par, HorStretch) & 0x7C) | 0x80);
822 }
823 
824 /* Address of first shown pixel in display memory */
825 static void set_screen_start(struct tridentfb_par *par, int base)
826 {
827 	u8 tmp;
828 	write3X4(par, VGA_CRTC_START_LO, base & 0xFF);
829 	write3X4(par, VGA_CRTC_START_HI, (base & 0xFF00) >> 8);
830 	tmp = read3X4(par, CRTCModuleTest) & 0xDF;
831 	write3X4(par, CRTCModuleTest, tmp | ((base & 0x10000) >> 11));
832 	tmp = read3X4(par, CRTHiOrd) & 0xF8;
833 	write3X4(par, CRTHiOrd, tmp | ((base & 0xE0000) >> 17));
834 }
835 
836 /* Set dotclock frequency */
837 static void set_vclk(struct tridentfb_par *par, unsigned long freq)
838 {
839 	int m, n, k;
840 	unsigned long fi, d, di;
841 	unsigned char best_m = 0, best_n = 0, best_k = 0;
842 	unsigned char hi, lo;
843 	unsigned char shift = !is_oldclock(par->chip_id) ? 2 : 1;
844 
845 	d = 20000;
846 	for (k = shift; k >= 0; k--)
847 		for (m = 1; m < 32; m++) {
848 			n = ((m + 2) << shift) - 8;
849 			for (n = (n < 0 ? 0 : n); n < 122; n++) {
850 				fi = ((14318l * (n + 8)) / (m + 2)) >> k;
851 				di = abs(fi - freq);
852 				if (di < d || (di == d && k == best_k)) {
853 					d = di;
854 					best_n = n;
855 					best_m = m;
856 					best_k = k;
857 				}
858 				if (fi > freq)
859 					break;
860 			}
861 		}
862 
863 	if (is_oldclock(par->chip_id)) {
864 		lo = best_n | (best_m << 7);
865 		hi = (best_m >> 1) | (best_k << 4);
866 	} else {
867 		lo = best_n;
868 		hi = best_m | (best_k << 6);
869 	}
870 
871 	if (is3Dchip(par->chip_id)) {
872 		vga_mm_wseq(par->io_virt, ClockHigh, hi);
873 		vga_mm_wseq(par->io_virt, ClockLow, lo);
874 	} else {
875 		t_outb(par, lo, 0x43C8);
876 		t_outb(par, hi, 0x43C9);
877 	}
878 	debug("VCLK = %X %X\n", hi, lo);
879 }
880 
881 /* Set number of lines for flat panels*/
882 static void set_number_of_lines(struct tridentfb_par *par, int lines)
883 {
884 	int tmp = read3CE(par, CyberEnhance) & 0x8F;
885 	if (lines > 1024)
886 		tmp |= 0x50;
887 	else if (lines > 768)
888 		tmp |= 0x30;
889 	else if (lines > 600)
890 		tmp |= 0x20;
891 	else if (lines > 480)
892 		tmp |= 0x10;
893 	write3CE(par, CyberEnhance, tmp);
894 }
895 
896 /*
897  * If we see that FP is active we assume we have one.
898  * Otherwise we have a CRT display. User can override.
899  */
900 static int is_flatpanel(struct tridentfb_par *par)
901 {
902 	if (fp)
903 		return 1;
904 	if (crt || !iscyber(par->chip_id))
905 		return 0;
906 	return (read3CE(par, FPConfig) & 0x10) ? 1 : 0;
907 }
908 
909 /* Try detecting the video memory size */
910 static unsigned int get_memsize(struct tridentfb_par *par)
911 {
912 	unsigned char tmp, tmp2;
913 	unsigned int k;
914 
915 	/* If memory size provided by user */
916 	if (memsize)
917 		k = memsize * Kb;
918 	else
919 		switch (par->chip_id) {
920 		case CYBER9525DVD:
921 			k = 2560 * Kb;
922 			break;
923 		default:
924 			tmp = read3X4(par, SPR) & 0x0F;
925 			switch (tmp) {
926 
927 			case 0x01:
928 				k = 512 * Kb;
929 				break;
930 			case 0x02:
931 				k = 6 * Mb;	/* XP */
932 				break;
933 			case 0x03:
934 				k = 1 * Mb;
935 				break;
936 			case 0x04:
937 				k = 8 * Mb;
938 				break;
939 			case 0x06:
940 				k = 10 * Mb;	/* XP */
941 				break;
942 			case 0x07:
943 				k = 2 * Mb;
944 				break;
945 			case 0x08:
946 				k = 12 * Mb;	/* XP */
947 				break;
948 			case 0x0A:
949 				k = 14 * Mb;	/* XP */
950 				break;
951 			case 0x0C:
952 				k = 16 * Mb;	/* XP */
953 				break;
954 			case 0x0E:		/* XP */
955 
956 				tmp2 = vga_mm_rseq(par->io_virt, 0xC1);
957 				switch (tmp2) {
958 				case 0x00:
959 					k = 20 * Mb;
960 					break;
961 				case 0x01:
962 					k = 24 * Mb;
963 					break;
964 				case 0x10:
965 					k = 28 * Mb;
966 					break;
967 				case 0x11:
968 					k = 32 * Mb;
969 					break;
970 				default:
971 					k = 1 * Mb;
972 					break;
973 				}
974 				break;
975 
976 			case 0x0F:
977 				k = 4 * Mb;
978 				break;
979 			default:
980 				k = 1 * Mb;
981 				break;
982 			}
983 		}
984 
985 	k -= memdiff * Kb;
986 	output("framebuffer size = %d Kb\n", k / Kb);
987 	return k;
988 }
989 
990 /* See if we can handle the video mode described in var */
991 static int tridentfb_check_var(struct fb_var_screeninfo *var,
992 			       struct fb_info *info)
993 {
994 	struct tridentfb_par *par = info->par;
995 	int bpp = var->bits_per_pixel;
996 	int line_length;
997 	int ramdac = 230000; /* 230MHz for most 3D chips */
998 	debug("enter\n");
999 
1000 	if (!var->pixclock)
1001 		return -EINVAL;
1002 
1003 	/* check color depth */
1004 	if (bpp == 24)
1005 		bpp = var->bits_per_pixel = 32;
1006 	if (bpp != 8 && bpp != 16 && bpp != 32)
1007 		return -EINVAL;
1008 	if (par->chip_id == TGUI9440 && bpp == 32)
1009 		return -EINVAL;
1010 	/* check whether resolution fits on panel and in memory */
1011 	if (par->flatpanel && nativex && var->xres > nativex)
1012 		return -EINVAL;
1013 	/* various resolution checks */
1014 	var->xres = (var->xres + 7) & ~0x7;
1015 	if (var->xres > var->xres_virtual)
1016 		var->xres_virtual = var->xres;
1017 	if (var->yres > var->yres_virtual)
1018 		var->yres_virtual = var->yres;
1019 	if (var->xres_virtual > 4095 || var->yres > 2048)
1020 		return -EINVAL;
1021 	/* prevent from position overflow for acceleration */
1022 	if (var->yres_virtual > 0xffff)
1023 		return -EINVAL;
1024 	line_length = var->xres_virtual * bpp / 8;
1025 
1026 	if (!is3Dchip(par->chip_id) &&
1027 	    !(info->flags & FBINFO_HWACCEL_DISABLED)) {
1028 		/* acceleration requires line length to be power of 2 */
1029 		if (line_length <= 512)
1030 			var->xres_virtual = 512 * 8 / bpp;
1031 		else if (line_length <= 1024)
1032 			var->xres_virtual = 1024 * 8 / bpp;
1033 		else if (line_length <= 2048)
1034 			var->xres_virtual = 2048 * 8 / bpp;
1035 		else if (line_length <= 4096)
1036 			var->xres_virtual = 4096 * 8 / bpp;
1037 		else if (line_length <= 8192)
1038 			var->xres_virtual = 8192 * 8 / bpp;
1039 		else
1040 			return -EINVAL;
1041 
1042 		line_length = var->xres_virtual * bpp / 8;
1043 	}
1044 
1045 	/* datasheet specifies how to set panning only up to 4 MB */
1046 	if (line_length * (var->yres_virtual - var->yres) > (4 << 20))
1047 		var->yres_virtual = ((4 << 20) / line_length) + var->yres;
1048 
1049 	if (line_length * var->yres_virtual > info->fix.smem_len)
1050 		return -EINVAL;
1051 
1052 	switch (bpp) {
1053 	case 8:
1054 		var->red.offset = 0;
1055 		var->red.length = 8;
1056 		var->green = var->red;
1057 		var->blue = var->red;
1058 		break;
1059 	case 16:
1060 		var->red.offset = 11;
1061 		var->green.offset = 5;
1062 		var->blue.offset = 0;
1063 		var->red.length = 5;
1064 		var->green.length = 6;
1065 		var->blue.length = 5;
1066 		break;
1067 	case 32:
1068 		var->red.offset = 16;
1069 		var->green.offset = 8;
1070 		var->blue.offset = 0;
1071 		var->red.length = 8;
1072 		var->green.length = 8;
1073 		var->blue.length = 8;
1074 		break;
1075 	default:
1076 		return -EINVAL;
1077 	}
1078 
1079 	if (is_xp(par->chip_id))
1080 		ramdac = 350000;
1081 
1082 	switch (par->chip_id) {
1083 	case TGUI9440:
1084 		ramdac = (bpp >= 16) ? 45000 : 90000;
1085 		break;
1086 	case CYBER9320:
1087 	case TGUI9660:
1088 		ramdac = 135000;
1089 		break;
1090 	case PROVIDIA9685:
1091 	case CYBER9388:
1092 	case CYBER9382:
1093 	case CYBER9385:
1094 		ramdac = 170000;
1095 		break;
1096 	}
1097 
1098 	/* The clock is doubled for 32 bpp */
1099 	if (bpp == 32)
1100 		ramdac /= 2;
1101 
1102 	if (PICOS2KHZ(var->pixclock) > ramdac)
1103 		return -EINVAL;
1104 
1105 	debug("exit\n");
1106 
1107 	return 0;
1108 
1109 }
1110 
1111 /* Pan the display */
1112 static int tridentfb_pan_display(struct fb_var_screeninfo *var,
1113 				 struct fb_info *info)
1114 {
1115 	struct tridentfb_par *par = info->par;
1116 	unsigned int offset;
1117 
1118 	debug("enter\n");
1119 	offset = (var->xoffset + (var->yoffset * info->var.xres_virtual))
1120 		* info->var.bits_per_pixel / 32;
1121 	set_screen_start(par, offset);
1122 	debug("exit\n");
1123 	return 0;
1124 }
1125 
1126 static inline void shadowmode_on(struct tridentfb_par *par)
1127 {
1128 	write3CE(par, CyberControl, read3CE(par, CyberControl) | 0x81);
1129 }
1130 
1131 /* Set the hardware to the requested video mode */
1132 static int tridentfb_set_par(struct fb_info *info)
1133 {
1134 	struct tridentfb_par *par = info->par;
1135 	u32 htotal, hdispend, hsyncstart, hsyncend, hblankstart, hblankend;
1136 	u32 vtotal, vdispend, vsyncstart, vsyncend, vblankstart, vblankend;
1137 	struct fb_var_screeninfo *var = &info->var;
1138 	int bpp = var->bits_per_pixel;
1139 	unsigned char tmp;
1140 	unsigned long vclk;
1141 
1142 	debug("enter\n");
1143 	hdispend = var->xres / 8 - 1;
1144 	hsyncstart = (var->xres + var->right_margin) / 8;
1145 	hsyncend = (var->xres + var->right_margin + var->hsync_len) / 8;
1146 	htotal = (var->xres + var->left_margin + var->right_margin +
1147 		  var->hsync_len) / 8 - 5;
1148 	hblankstart = hdispend + 1;
1149 	hblankend = htotal + 3;
1150 
1151 	vdispend = var->yres - 1;
1152 	vsyncstart = var->yres + var->lower_margin;
1153 	vsyncend = vsyncstart + var->vsync_len;
1154 	vtotal = var->upper_margin + vsyncend - 2;
1155 	vblankstart = vdispend + 1;
1156 	vblankend = vtotal;
1157 
1158 	if (info->var.vmode & FB_VMODE_INTERLACED) {
1159 		vtotal /= 2;
1160 		vdispend /= 2;
1161 		vsyncstart /= 2;
1162 		vsyncend /= 2;
1163 		vblankstart /= 2;
1164 		vblankend /= 2;
1165 	}
1166 
1167 	enable_mmio(par);
1168 	crtc_unlock(par);
1169 	write3CE(par, CyberControl, 8);
1170 	tmp = 0xEB;
1171 	if (var->sync & FB_SYNC_HOR_HIGH_ACT)
1172 		tmp &= ~0x40;
1173 	if (var->sync & FB_SYNC_VERT_HIGH_ACT)
1174 		tmp &= ~0x80;
1175 
1176 	if (par->flatpanel && var->xres < nativex) {
1177 		/*
1178 		 * on flat panels with native size larger
1179 		 * than requested resolution decide whether
1180 		 * we stretch or center
1181 		 */
1182 		t_outb(par, tmp | 0xC0, VGA_MIS_W);
1183 
1184 		shadowmode_on(par);
1185 
1186 		if (center)
1187 			screen_center(par);
1188 		else if (stretch)
1189 			screen_stretch(par);
1190 
1191 	} else {
1192 		t_outb(par, tmp, VGA_MIS_W);
1193 		write3CE(par, CyberControl, 8);
1194 	}
1195 
1196 	/* vertical timing values */
1197 	write3X4(par, VGA_CRTC_V_TOTAL, vtotal & 0xFF);
1198 	write3X4(par, VGA_CRTC_V_DISP_END, vdispend & 0xFF);
1199 	write3X4(par, VGA_CRTC_V_SYNC_START, vsyncstart & 0xFF);
1200 	write3X4(par, VGA_CRTC_V_SYNC_END, (vsyncend & 0x0F));
1201 	write3X4(par, VGA_CRTC_V_BLANK_START, vblankstart & 0xFF);
1202 	write3X4(par, VGA_CRTC_V_BLANK_END, vblankend & 0xFF);
1203 
1204 	/* horizontal timing values */
1205 	write3X4(par, VGA_CRTC_H_TOTAL, htotal & 0xFF);
1206 	write3X4(par, VGA_CRTC_H_DISP, hdispend & 0xFF);
1207 	write3X4(par, VGA_CRTC_H_SYNC_START, hsyncstart & 0xFF);
1208 	write3X4(par, VGA_CRTC_H_SYNC_END,
1209 		 (hsyncend & 0x1F) | ((hblankend & 0x20) << 2));
1210 	write3X4(par, VGA_CRTC_H_BLANK_START, hblankstart & 0xFF);
1211 	write3X4(par, VGA_CRTC_H_BLANK_END, hblankend & 0x1F);
1212 
1213 	/* higher bits of vertical timing values */
1214 	tmp = 0x10;
1215 	if (vtotal & 0x100) tmp |= 0x01;
1216 	if (vdispend & 0x100) tmp |= 0x02;
1217 	if (vsyncstart & 0x100) tmp |= 0x04;
1218 	if (vblankstart & 0x100) tmp |= 0x08;
1219 
1220 	if (vtotal & 0x200) tmp |= 0x20;
1221 	if (vdispend & 0x200) tmp |= 0x40;
1222 	if (vsyncstart & 0x200) tmp |= 0x80;
1223 	write3X4(par, VGA_CRTC_OVERFLOW, tmp);
1224 
1225 	tmp = read3X4(par, CRTHiOrd) & 0x07;
1226 	tmp |= 0x08;	/* line compare bit 10 */
1227 	if (vtotal & 0x400) tmp |= 0x80;
1228 	if (vblankstart & 0x400) tmp |= 0x40;
1229 	if (vsyncstart & 0x400) tmp |= 0x20;
1230 	if (vdispend & 0x400) tmp |= 0x10;
1231 	write3X4(par, CRTHiOrd, tmp);
1232 
1233 	tmp = (htotal >> 8) & 0x01;
1234 	tmp |= (hdispend >> 7) & 0x02;
1235 	tmp |= (hsyncstart >> 5) & 0x08;
1236 	tmp |= (hblankstart >> 4) & 0x10;
1237 	write3X4(par, HorizOverflow, tmp);
1238 
1239 	tmp = 0x40;
1240 	if (vblankstart & 0x200) tmp |= 0x20;
1241 //FIXME	if (info->var.vmode & FB_VMODE_DOUBLE) tmp |= 0x80;  /* double scan for 200 line modes */
1242 	write3X4(par, VGA_CRTC_MAX_SCAN, tmp);
1243 
1244 	write3X4(par, VGA_CRTC_LINE_COMPARE, 0xFF);
1245 	write3X4(par, VGA_CRTC_PRESET_ROW, 0);
1246 	write3X4(par, VGA_CRTC_MODE, 0xC3);
1247 
1248 	write3X4(par, LinearAddReg, 0x20);	/* enable linear addressing */
1249 
1250 	tmp = (info->var.vmode & FB_VMODE_INTERLACED) ? 0x84 : 0x80;
1251 	/* enable access extended memory */
1252 	write3X4(par, CRTCModuleTest, tmp);
1253 	tmp = read3CE(par, MiscIntContReg) & ~0x4;
1254 	if (info->var.vmode & FB_VMODE_INTERLACED)
1255 		tmp |= 0x4;
1256 	write3CE(par, MiscIntContReg, tmp);
1257 
1258 	/* enable GE for text acceleration */
1259 	write3X4(par, GraphEngReg, 0x80);
1260 
1261 	switch (bpp) {
1262 	case 8:
1263 		tmp = 0x00;
1264 		break;
1265 	case 16:
1266 		tmp = 0x05;
1267 		break;
1268 	case 24:
1269 		tmp = 0x29;
1270 		break;
1271 	case 32:
1272 		tmp = 0x09;
1273 		break;
1274 	}
1275 
1276 	write3X4(par, PixelBusReg, tmp);
1277 
1278 	tmp = read3X4(par, DRAMControl);
1279 	if (!is_oldprotect(par->chip_id))
1280 		tmp |= 0x10;
1281 	if (iscyber(par->chip_id))
1282 		tmp |= 0x20;
1283 	write3X4(par, DRAMControl, tmp);	/* both IO, linear enable */
1284 
1285 	write3X4(par, InterfaceSel, read3X4(par, InterfaceSel) | 0x40);
1286 	if (!is_xp(par->chip_id))
1287 		write3X4(par, Performance, read3X4(par, Performance) | 0x10);
1288 	/* MMIO & PCI read and write burst enable */
1289 	if (par->chip_id != TGUI9440 && par->chip_id != IMAGE975)
1290 		write3X4(par, PCIReg, read3X4(par, PCIReg) | 0x06);
1291 
1292 	vga_mm_wseq(par->io_virt, 0, 3);
1293 	vga_mm_wseq(par->io_virt, 1, 1); /* set char clock 8 dots wide */
1294 	/* enable 4 maps because needed in chain4 mode */
1295 	vga_mm_wseq(par->io_virt, 2, 0x0F);
1296 	vga_mm_wseq(par->io_virt, 3, 0);
1297 	vga_mm_wseq(par->io_virt, 4, 0x0E); /* memory mode enable bitmaps ?? */
1298 
1299 	/* convert from picoseconds to kHz */
1300 	vclk = PICOS2KHZ(info->var.pixclock);
1301 
1302 	/* divide clock by 2 if 32bpp chain4 mode display and CPU path */
1303 	tmp = read3CE(par, MiscExtFunc) & 0xF0;
1304 	if (bpp == 32 || (par->chip_id == TGUI9440 && bpp == 16)) {
1305 		tmp |= 8;
1306 		vclk *= 2;
1307 	}
1308 	set_vclk(par, vclk);
1309 	write3CE(par, MiscExtFunc, tmp | 0x12);
1310 	write3CE(par, 0x5, 0x40);	/* no CGA compat, allow 256 col */
1311 	write3CE(par, 0x6, 0x05);	/* graphics mode */
1312 	write3CE(par, 0x7, 0x0F);	/* planes? */
1313 
1314 	/* graphics mode and support 256 color modes */
1315 	writeAttr(par, 0x10, 0x41);
1316 	writeAttr(par, 0x12, 0x0F);	/* planes */
1317 	writeAttr(par, 0x13, 0);	/* horizontal pel panning */
1318 
1319 	/* colors */
1320 	for (tmp = 0; tmp < 0x10; tmp++)
1321 		writeAttr(par, tmp, tmp);
1322 	fb_readb(par->io_virt + VGA_IS1_RC);	/* flip-flop to index */
1323 	t_outb(par, 0x20, VGA_ATT_W);		/* enable attr */
1324 
1325 	switch (bpp) {
1326 	case 8:
1327 		tmp = 0;
1328 		break;
1329 	case 16:
1330 		tmp = 0x30;
1331 		break;
1332 	case 24:
1333 	case 32:
1334 		tmp = 0xD0;
1335 		break;
1336 	}
1337 
1338 	t_inb(par, VGA_PEL_IW);
1339 	t_inb(par, VGA_PEL_MSK);
1340 	t_inb(par, VGA_PEL_MSK);
1341 	t_inb(par, VGA_PEL_MSK);
1342 	t_inb(par, VGA_PEL_MSK);
1343 	t_outb(par, tmp, VGA_PEL_MSK);
1344 	t_inb(par, VGA_PEL_IW);
1345 
1346 	if (par->flatpanel)
1347 		set_number_of_lines(par, info->var.yres);
1348 	info->fix.line_length = info->var.xres_virtual * bpp / 8;
1349 	set_lwidth(par, info->fix.line_length / 8);
1350 
1351 	if (!(info->flags & FBINFO_HWACCEL_DISABLED))
1352 		par->init_accel(par, info->var.xres_virtual, bpp);
1353 
1354 	info->fix.visual = (bpp == 8) ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
1355 	info->cmap.len = (bpp == 8) ? 256 : 16;
1356 	debug("exit\n");
1357 	return 0;
1358 }
1359 
1360 /* Set one color register */
1361 static int tridentfb_setcolreg(unsigned regno, unsigned red, unsigned green,
1362 			       unsigned blue, unsigned transp,
1363 			       struct fb_info *info)
1364 {
1365 	int bpp = info->var.bits_per_pixel;
1366 	struct tridentfb_par *par = info->par;
1367 
1368 	if (regno >= info->cmap.len)
1369 		return 1;
1370 
1371 	if (bpp == 8) {
1372 		t_outb(par, 0xFF, VGA_PEL_MSK);
1373 		t_outb(par, regno, VGA_PEL_IW);
1374 
1375 		t_outb(par, red >> 10, VGA_PEL_D);
1376 		t_outb(par, green >> 10, VGA_PEL_D);
1377 		t_outb(par, blue >> 10, VGA_PEL_D);
1378 
1379 	} else if (regno < 16) {
1380 		if (bpp == 16) {	/* RGB 565 */
1381 			u32 col;
1382 
1383 			col = (red & 0xF800) | ((green & 0xFC00) >> 5) |
1384 				((blue & 0xF800) >> 11);
1385 			col |= col << 16;
1386 			((u32 *)(info->pseudo_palette))[regno] = col;
1387 		} else if (bpp == 32)		/* ARGB 8888 */
1388 			((u32 *)info->pseudo_palette)[regno] =
1389 				((transp & 0xFF00) << 16)	|
1390 				((red & 0xFF00) << 8)		|
1391 				((green & 0xFF00))		|
1392 				((blue & 0xFF00) >> 8);
1393 	}
1394 
1395 	return 0;
1396 }
1397 
1398 /* Try blanking the screen. For flat panels it does nothing */
1399 static int tridentfb_blank(int blank_mode, struct fb_info *info)
1400 {
1401 	unsigned char PMCont, DPMSCont;
1402 	struct tridentfb_par *par = info->par;
1403 
1404 	debug("enter\n");
1405 	if (par->flatpanel)
1406 		return 0;
1407 	t_outb(par, 0x04, 0x83C8); /* Read DPMS Control */
1408 	PMCont = t_inb(par, 0x83C6) & 0xFC;
1409 	DPMSCont = read3CE(par, PowerStatus) & 0xFC;
1410 	switch (blank_mode) {
1411 	case FB_BLANK_UNBLANK:
1412 		/* Screen: On, HSync: On, VSync: On */
1413 	case FB_BLANK_NORMAL:
1414 		/* Screen: Off, HSync: On, VSync: On */
1415 		PMCont |= 0x03;
1416 		DPMSCont |= 0x00;
1417 		break;
1418 	case FB_BLANK_HSYNC_SUSPEND:
1419 		/* Screen: Off, HSync: Off, VSync: On */
1420 		PMCont |= 0x02;
1421 		DPMSCont |= 0x01;
1422 		break;
1423 	case FB_BLANK_VSYNC_SUSPEND:
1424 		/* Screen: Off, HSync: On, VSync: Off */
1425 		PMCont |= 0x02;
1426 		DPMSCont |= 0x02;
1427 		break;
1428 	case FB_BLANK_POWERDOWN:
1429 		/* Screen: Off, HSync: Off, VSync: Off */
1430 		PMCont |= 0x00;
1431 		DPMSCont |= 0x03;
1432 		break;
1433 	}
1434 
1435 	write3CE(par, PowerStatus, DPMSCont);
1436 	t_outb(par, 4, 0x83C8);
1437 	t_outb(par, PMCont, 0x83C6);
1438 
1439 	debug("exit\n");
1440 
1441 	/* let fbcon do a softblank for us */
1442 	return (blank_mode == FB_BLANK_NORMAL) ? 1 : 0;
1443 }
1444 
1445 static const struct fb_ops tridentfb_ops = {
1446 	.owner = THIS_MODULE,
1447 	.fb_setcolreg = tridentfb_setcolreg,
1448 	.fb_pan_display = tridentfb_pan_display,
1449 	.fb_blank = tridentfb_blank,
1450 	.fb_check_var = tridentfb_check_var,
1451 	.fb_set_par = tridentfb_set_par,
1452 	.fb_fillrect = tridentfb_fillrect,
1453 	.fb_copyarea = tridentfb_copyarea,
1454 	.fb_imageblit = tridentfb_imageblit,
1455 	.fb_sync = tridentfb_sync,
1456 };
1457 
1458 static int trident_pci_probe(struct pci_dev *dev,
1459 			     const struct pci_device_id *id)
1460 {
1461 	int err;
1462 	unsigned char revision;
1463 	struct fb_info *info;
1464 	struct tridentfb_par *default_par;
1465 	int chip3D;
1466 	int chip_id;
1467 	bool found = false;
1468 
1469 	err = aperture_remove_conflicting_pci_devices(dev, "tridentfb");
1470 	if (err)
1471 		return err;
1472 
1473 	err = pcim_enable_device(dev);
1474 	if (err)
1475 		return err;
1476 
1477 	info = framebuffer_alloc(sizeof(struct tridentfb_par), &dev->dev);
1478 	if (!info)
1479 		return -ENOMEM;
1480 	default_par = info->par;
1481 
1482 	chip_id = id->device;
1483 
1484 	/* If PCI id is 0x9660 then further detect chip type */
1485 
1486 	if (chip_id == TGUI9660) {
1487 		revision = vga_io_rseq(RevisionID);
1488 
1489 		switch (revision) {
1490 		case 0x21:
1491 			chip_id = PROVIDIA9685;
1492 			break;
1493 		case 0x22:
1494 		case 0x23:
1495 			chip_id = CYBER9397;
1496 			break;
1497 		case 0x2A:
1498 			chip_id = CYBER9397DVD;
1499 			break;
1500 		case 0x30:
1501 		case 0x33:
1502 		case 0x34:
1503 		case 0x35:
1504 		case 0x38:
1505 		case 0x3A:
1506 		case 0xB3:
1507 			chip_id = CYBER9385;
1508 			break;
1509 		case 0x40 ... 0x43:
1510 			chip_id = CYBER9382;
1511 			break;
1512 		case 0x4A:
1513 			chip_id = CYBER9388;
1514 			break;
1515 		default:
1516 			break;
1517 		}
1518 	}
1519 
1520 	chip3D = is3Dchip(chip_id);
1521 
1522 	if (is_xp(chip_id)) {
1523 		default_par->init_accel = xp_init_accel;
1524 		default_par->wait_engine = xp_wait_engine;
1525 		default_par->fill_rect = xp_fill_rect;
1526 		default_par->copy_rect = xp_copy_rect;
1527 		tridentfb_fix.accel = FB_ACCEL_TRIDENT_BLADEXP;
1528 	} else if (is_blade(chip_id)) {
1529 		default_par->init_accel = blade_init_accel;
1530 		default_par->wait_engine = blade_wait_engine;
1531 		default_par->fill_rect = blade_fill_rect;
1532 		default_par->copy_rect = blade_copy_rect;
1533 		default_par->image_blit = blade_image_blit;
1534 		tridentfb_fix.accel = FB_ACCEL_TRIDENT_BLADE3D;
1535 	} else if (chip3D) {			/* 3DImage family left */
1536 		default_par->init_accel = image_init_accel;
1537 		default_par->wait_engine = image_wait_engine;
1538 		default_par->fill_rect = image_fill_rect;
1539 		default_par->copy_rect = image_copy_rect;
1540 		tridentfb_fix.accel = FB_ACCEL_TRIDENT_3DIMAGE;
1541 	} else { 				/* TGUI 9440/96XX family */
1542 		default_par->init_accel = tgui_init_accel;
1543 		default_par->wait_engine = xp_wait_engine;
1544 		default_par->fill_rect = tgui_fill_rect;
1545 		default_par->copy_rect = tgui_copy_rect;
1546 		tridentfb_fix.accel = FB_ACCEL_TRIDENT_TGUI;
1547 	}
1548 
1549 	default_par->chip_id = chip_id;
1550 
1551 	/* setup MMIO region */
1552 	tridentfb_fix.mmio_start = pci_resource_start(dev, 1);
1553 	tridentfb_fix.mmio_len = pci_resource_len(dev, 1);
1554 
1555 	if (!request_mem_region(tridentfb_fix.mmio_start,
1556 				tridentfb_fix.mmio_len, "tridentfb")) {
1557 		debug("request_region failed!\n");
1558 		framebuffer_release(info);
1559 		return -1;
1560 	}
1561 
1562 	default_par->io_virt = ioremap(tridentfb_fix.mmio_start,
1563 					       tridentfb_fix.mmio_len);
1564 
1565 	if (!default_par->io_virt) {
1566 		debug("ioremap failed\n");
1567 		err = -1;
1568 		goto out_unmap1;
1569 	}
1570 
1571 	enable_mmio(default_par);
1572 
1573 	/* setup framebuffer memory */
1574 	tridentfb_fix.smem_start = pci_resource_start(dev, 0);
1575 	tridentfb_fix.smem_len = get_memsize(default_par);
1576 
1577 	if (!request_mem_region(tridentfb_fix.smem_start,
1578 				tridentfb_fix.smem_len, "tridentfb")) {
1579 		debug("request_mem_region failed!\n");
1580 		disable_mmio(info->par);
1581 		err = -1;
1582 		goto out_unmap1;
1583 	}
1584 
1585 	info->screen_base = ioremap(tridentfb_fix.smem_start,
1586 					    tridentfb_fix.smem_len);
1587 
1588 	if (!info->screen_base) {
1589 		debug("ioremap failed\n");
1590 		err = -1;
1591 		goto out_unmap2;
1592 	}
1593 
1594 	default_par->flatpanel = is_flatpanel(default_par);
1595 
1596 	if (default_par->flatpanel)
1597 		nativex = get_nativex(default_par);
1598 
1599 	info->fix = tridentfb_fix;
1600 	info->fbops = &tridentfb_ops;
1601 	info->pseudo_palette = default_par->pseudo_pal;
1602 
1603 	info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN;
1604 	if (!noaccel && default_par->init_accel) {
1605 		info->flags &= ~FBINFO_HWACCEL_DISABLED;
1606 		info->flags |= FBINFO_HWACCEL_COPYAREA;
1607 		info->flags |= FBINFO_HWACCEL_FILLRECT;
1608 	} else
1609 		info->flags |= FBINFO_HWACCEL_DISABLED;
1610 
1611 	if (is_blade(chip_id) && chip_id != BLADE3D)
1612 		info->flags |= FBINFO_READS_FAST;
1613 
1614 	info->pixmap.addr = kmalloc(4096, GFP_KERNEL);
1615 	if (!info->pixmap.addr) {
1616 		err = -ENOMEM;
1617 		goto out_unmap2;
1618 	}
1619 
1620 	info->pixmap.size = 4096;
1621 	info->pixmap.buf_align = 4;
1622 	info->pixmap.scan_align = 1;
1623 	info->pixmap.access_align = 32;
1624 	info->pixmap.flags = FB_PIXMAP_SYSTEM;
1625 	info->var.bits_per_pixel = 8;
1626 
1627 	if (default_par->image_blit) {
1628 		info->flags |= FBINFO_HWACCEL_IMAGEBLIT;
1629 		info->pixmap.scan_align = 4;
1630 	}
1631 
1632 	if (noaccel) {
1633 		printk(KERN_DEBUG "disabling acceleration\n");
1634 		info->flags |= FBINFO_HWACCEL_DISABLED;
1635 		info->pixmap.scan_align = 1;
1636 	}
1637 
1638 	if (tridentfb_setup_ddc_bus(info) == 0) {
1639 		u8 *edid = fb_ddc_read(&default_par->ddc_adapter);
1640 
1641 		default_par->ddc_registered = true;
1642 		if (edid) {
1643 			fb_edid_to_monspecs(edid, &info->monspecs);
1644 			kfree(edid);
1645 			if (!info->monspecs.modedb)
1646 				dev_err(info->device, "error getting mode database\n");
1647 			else {
1648 				const struct fb_videomode *m;
1649 
1650 				fb_videomode_to_modelist(info->monspecs.modedb,
1651 						 info->monspecs.modedb_len,
1652 						 &info->modelist);
1653 				m = fb_find_best_display(&info->monspecs,
1654 							 &info->modelist);
1655 				if (m) {
1656 					fb_videomode_to_var(&info->var, m);
1657 					/* fill all other info->var's fields */
1658 					if (tridentfb_check_var(&info->var,
1659 								info) == 0)
1660 						found = true;
1661 				}
1662 			}
1663 		}
1664 	}
1665 
1666 	if (!mode_option && !found)
1667 		mode_option = "640x480-8@60";
1668 
1669 	/* Prepare startup mode */
1670 	if (mode_option) {
1671 		err = fb_find_mode(&info->var, info, mode_option,
1672 				   info->monspecs.modedb,
1673 				   info->monspecs.modedb_len,
1674 				   NULL, info->var.bits_per_pixel);
1675 		if (!err || err == 4) {
1676 			err = -EINVAL;
1677 			dev_err(info->device, "mode %s not found\n",
1678 								mode_option);
1679 			fb_destroy_modedb(info->monspecs.modedb);
1680 			info->monspecs.modedb = NULL;
1681 			goto out_unmap2;
1682 		}
1683 	}
1684 
1685 	fb_destroy_modedb(info->monspecs.modedb);
1686 	info->monspecs.modedb = NULL;
1687 
1688 	err = fb_alloc_cmap(&info->cmap, 256, 0);
1689 	if (err < 0)
1690 		goto out_unmap2;
1691 
1692 	info->var.activate |= FB_ACTIVATE_NOW;
1693 	info->device = &dev->dev;
1694 	if (register_framebuffer(info) < 0) {
1695 		printk(KERN_ERR "tridentfb: could not register framebuffer\n");
1696 		fb_dealloc_cmap(&info->cmap);
1697 		err = -EINVAL;
1698 		goto out_unmap2;
1699 	}
1700 	output("fb%d: %s frame buffer device %dx%d-%dbpp\n",
1701 	   info->node, info->fix.id, info->var.xres,
1702 	   info->var.yres, info->var.bits_per_pixel);
1703 
1704 	pci_set_drvdata(dev, info);
1705 	return 0;
1706 
1707 out_unmap2:
1708 	if (default_par->ddc_registered)
1709 		i2c_del_adapter(&default_par->ddc_adapter);
1710 	kfree(info->pixmap.addr);
1711 	if (info->screen_base)
1712 		iounmap(info->screen_base);
1713 	disable_mmio(info->par);
1714 out_unmap1:
1715 	if (default_par->io_virt)
1716 		iounmap(default_par->io_virt);
1717 	framebuffer_release(info);
1718 	return err;
1719 }
1720 
1721 static void trident_pci_remove(struct pci_dev *dev)
1722 {
1723 	struct fb_info *info = pci_get_drvdata(dev);
1724 	struct tridentfb_par *par = info->par;
1725 
1726 	unregister_framebuffer(info);
1727 	if (par->ddc_registered)
1728 		i2c_del_adapter(&par->ddc_adapter);
1729 	iounmap(par->io_virt);
1730 	iounmap(info->screen_base);
1731 	kfree(info->pixmap.addr);
1732 	fb_dealloc_cmap(&info->cmap);
1733 	framebuffer_release(info);
1734 }
1735 
1736 /* List of boards that we are trying to support */
1737 static const struct pci_device_id trident_devices[] = {
1738 	{PCI_VENDOR_ID_TRIDENT,	BLADE3D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1739 	{PCI_VENDOR_ID_TRIDENT,	CYBERBLADEi7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1740 	{PCI_VENDOR_ID_TRIDENT,	CYBERBLADEi7D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1741 	{PCI_VENDOR_ID_TRIDENT,	CYBERBLADEi1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1742 	{PCI_VENDOR_ID_TRIDENT,	CYBERBLADEi1D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1743 	{PCI_VENDOR_ID_TRIDENT,	CYBERBLADEAi1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1744 	{PCI_VENDOR_ID_TRIDENT,	CYBERBLADEAi1D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1745 	{PCI_VENDOR_ID_TRIDENT,	CYBERBLADEE4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1746 	{PCI_VENDOR_ID_TRIDENT,	TGUI9440, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1747 	{PCI_VENDOR_ID_TRIDENT,	TGUI9660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1748 	{PCI_VENDOR_ID_TRIDENT,	IMAGE975, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1749 	{PCI_VENDOR_ID_TRIDENT,	IMAGE985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1750 	{PCI_VENDOR_ID_TRIDENT,	CYBER9320, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1751 	{PCI_VENDOR_ID_TRIDENT,	CYBER9388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1752 	{PCI_VENDOR_ID_TRIDENT,	CYBER9520, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1753 	{PCI_VENDOR_ID_TRIDENT,	CYBER9525DVD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1754 	{PCI_VENDOR_ID_TRIDENT,	CYBER9397, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1755 	{PCI_VENDOR_ID_TRIDENT,	CYBER9397DVD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1756 	{PCI_VENDOR_ID_TRIDENT,	CYBERBLADEXPAi1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1757 	{PCI_VENDOR_ID_TRIDENT,	CYBERBLADEXPm8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1758 	{PCI_VENDOR_ID_TRIDENT,	CYBERBLADEXPm16, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1759 	{0,}
1760 };
1761 
1762 MODULE_DEVICE_TABLE(pci, trident_devices);
1763 
1764 static struct pci_driver tridentfb_pci_driver = {
1765 	.name = "tridentfb",
1766 	.id_table = trident_devices,
1767 	.probe = trident_pci_probe,
1768 	.remove = trident_pci_remove,
1769 };
1770 
1771 /*
1772  * Parse user specified options (`video=trident:')
1773  * example:
1774  *	video=trident:800x600,bpp=16,noaccel
1775  */
1776 #ifndef MODULE
1777 static int __init tridentfb_setup(char *options)
1778 {
1779 	char *opt;
1780 	if (!options || !*options)
1781 		return 0;
1782 	while ((opt = strsep(&options, ",")) != NULL) {
1783 		if (!*opt)
1784 			continue;
1785 		if (!strncmp(opt, "noaccel", 7))
1786 			noaccel = 1;
1787 		else if (!strncmp(opt, "fp", 2))
1788 			fp = 1;
1789 		else if (!strncmp(opt, "crt", 3))
1790 			fp = 0;
1791 		else if (!strncmp(opt, "bpp=", 4))
1792 			bpp = simple_strtoul(opt + 4, NULL, 0);
1793 		else if (!strncmp(opt, "center", 6))
1794 			center = 1;
1795 		else if (!strncmp(opt, "stretch", 7))
1796 			stretch = 1;
1797 		else if (!strncmp(opt, "memsize=", 8))
1798 			memsize = simple_strtoul(opt + 8, NULL, 0);
1799 		else if (!strncmp(opt, "memdiff=", 8))
1800 			memdiff = simple_strtoul(opt + 8, NULL, 0);
1801 		else if (!strncmp(opt, "nativex=", 8))
1802 			nativex = simple_strtoul(opt + 8, NULL, 0);
1803 		else
1804 			mode_option = opt;
1805 	}
1806 	return 0;
1807 }
1808 #endif
1809 
1810 static int __init tridentfb_init(void)
1811 {
1812 #ifndef MODULE
1813 	char *option = NULL;
1814 
1815 	if (fb_get_options("tridentfb", &option))
1816 		return -ENODEV;
1817 	tridentfb_setup(option);
1818 #endif
1819 	return pci_register_driver(&tridentfb_pci_driver);
1820 }
1821 
1822 static void __exit tridentfb_exit(void)
1823 {
1824 	pci_unregister_driver(&tridentfb_pci_driver);
1825 }
1826 
1827 module_init(tridentfb_init);
1828 module_exit(tridentfb_exit);
1829 
1830 MODULE_AUTHOR("Jani Monoses <jani@iv.ro>");
1831 MODULE_DESCRIPTION("Framebuffer driver for Trident cards");
1832 MODULE_LICENSE("GPL");
1833 MODULE_ALIAS("cyblafb");
1834 
1835