1 /* sunxvr500.c: Sun 3DLABS XVR-500 Expert3D fb driver for sparc64 systems 2 * 3 * License: GPL 4 * 5 * Copyright (C) 2007 David S. Miller (davem@davemloft.net) 6 */ 7 8 #include <linux/aperture.h> 9 #include <linux/kernel.h> 10 #include <linux/fb.h> 11 #include <linux/pci.h> 12 #include <linux/init.h> 13 #include <linux/of_device.h> 14 15 #include <asm/io.h> 16 17 /* XXX This device has a 'dev-comm' property which apparently is 18 * XXX a pointer into the openfirmware's address space which is 19 * XXX a shared area the kernel driver can use to keep OBP 20 * XXX informed about the current resolution setting. The idea 21 * XXX is that the kernel can change resolutions, and as long 22 * XXX as the values in the 'dev-comm' area are accurate then 23 * XXX OBP can still render text properly to the console. 24 * XXX 25 * XXX I'm still working out the layout of this and whether there 26 * XXX are any signatures we need to look for etc. 27 */ 28 struct e3d_info { 29 struct fb_info *info; 30 struct pci_dev *pdev; 31 32 spinlock_t lock; 33 34 char __iomem *fb_base; 35 unsigned long fb_base_phys; 36 37 unsigned long fb8_buf_diff; 38 unsigned long regs_base_phys; 39 40 void __iomem *ramdac; 41 42 struct device_node *of_node; 43 44 unsigned int width; 45 unsigned int height; 46 unsigned int depth; 47 unsigned int fb_size; 48 49 u32 fb_base_reg; 50 u32 fb8_0_off; 51 u32 fb8_1_off; 52 53 u32 pseudo_palette[16]; 54 }; 55 56 static int e3d_get_props(struct e3d_info *ep) 57 { 58 ep->width = of_getintprop_default(ep->of_node, "width", 0); 59 ep->height = of_getintprop_default(ep->of_node, "height", 0); 60 ep->depth = of_getintprop_default(ep->of_node, "depth", 8); 61 62 if (!ep->width || !ep->height) { 63 printk(KERN_ERR "e3d: Critical properties missing for %s\n", 64 pci_name(ep->pdev)); 65 return -EINVAL; 66 } 67 68 return 0; 69 } 70 71 /* My XVR-500 comes up, at 1280x768 and a FB base register value of 72 * 0x04000000, the following video layout register values: 73 * 74 * RAMDAC_VID_WH 0x03ff04ff 75 * RAMDAC_VID_CFG 0x1a0b0088 76 * RAMDAC_VID_32FB_0 0x04000000 77 * RAMDAC_VID_32FB_1 0x04800000 78 * RAMDAC_VID_8FB_0 0x05000000 79 * RAMDAC_VID_8FB_1 0x05200000 80 * RAMDAC_VID_XXXFB 0x05400000 81 * RAMDAC_VID_YYYFB 0x05c00000 82 * RAMDAC_VID_ZZZFB 0x05e00000 83 */ 84 /* Video layout registers */ 85 #define RAMDAC_VID_WH 0x00000070UL /* (height-1)<<16 | (width-1) */ 86 #define RAMDAC_VID_CFG 0x00000074UL /* 0x1a000088|(linesz_log2<<16) */ 87 #define RAMDAC_VID_32FB_0 0x00000078UL /* PCI base 32bpp FB buffer 0 */ 88 #define RAMDAC_VID_32FB_1 0x0000007cUL /* PCI base 32bpp FB buffer 1 */ 89 #define RAMDAC_VID_8FB_0 0x00000080UL /* PCI base 8bpp FB buffer 0 */ 90 #define RAMDAC_VID_8FB_1 0x00000084UL /* PCI base 8bpp FB buffer 1 */ 91 #define RAMDAC_VID_XXXFB 0x00000088UL /* PCI base of XXX FB */ 92 #define RAMDAC_VID_YYYFB 0x0000008cUL /* PCI base of YYY FB */ 93 #define RAMDAC_VID_ZZZFB 0x00000090UL /* PCI base of ZZZ FB */ 94 95 /* CLUT registers */ 96 #define RAMDAC_INDEX 0x000000bcUL 97 #define RAMDAC_DATA 0x000000c0UL 98 99 static void e3d_clut_write(struct e3d_info *ep, int index, u32 val) 100 { 101 void __iomem *ramdac = ep->ramdac; 102 unsigned long flags; 103 104 spin_lock_irqsave(&ep->lock, flags); 105 106 writel(index, ramdac + RAMDAC_INDEX); 107 writel(val, ramdac + RAMDAC_DATA); 108 109 spin_unlock_irqrestore(&ep->lock, flags); 110 } 111 112 static int e3d_setcolreg(unsigned regno, 113 unsigned red, unsigned green, unsigned blue, 114 unsigned transp, struct fb_info *info) 115 { 116 struct e3d_info *ep = info->par; 117 u32 red_8, green_8, blue_8; 118 u32 red_10, green_10, blue_10; 119 u32 value; 120 121 if (regno >= 256) 122 return 1; 123 124 red_8 = red >> 8; 125 green_8 = green >> 8; 126 blue_8 = blue >> 8; 127 128 value = (blue_8 << 24) | (green_8 << 16) | (red_8 << 8); 129 130 if (info->fix.visual == FB_VISUAL_TRUECOLOR && regno < 16) 131 ((u32 *)info->pseudo_palette)[regno] = value; 132 133 134 red_10 = red >> 6; 135 green_10 = green >> 6; 136 blue_10 = blue >> 6; 137 138 value = (blue_10 << 20) | (green_10 << 10) | (red_10 << 0); 139 e3d_clut_write(ep, regno, value); 140 141 return 0; 142 } 143 144 /* XXX This is a bit of a hack. I can't figure out exactly how the 145 * XXX two 8bpp areas of the framebuffer work. I imagine there is 146 * XXX a WID attribute somewhere else in the framebuffer which tells 147 * XXX the ramdac which of the two 8bpp framebuffer regions to take 148 * XXX the pixel from. So, for now, render into both regions to make 149 * XXX sure the pixel shows up. 150 */ 151 static void e3d_imageblit(struct fb_info *info, const struct fb_image *image) 152 { 153 struct e3d_info *ep = info->par; 154 unsigned long flags; 155 156 spin_lock_irqsave(&ep->lock, flags); 157 cfb_imageblit(info, image); 158 info->screen_base += ep->fb8_buf_diff; 159 cfb_imageblit(info, image); 160 info->screen_base -= ep->fb8_buf_diff; 161 spin_unlock_irqrestore(&ep->lock, flags); 162 } 163 164 static void e3d_fillrect(struct fb_info *info, const struct fb_fillrect *rect) 165 { 166 struct e3d_info *ep = info->par; 167 unsigned long flags; 168 169 spin_lock_irqsave(&ep->lock, flags); 170 cfb_fillrect(info, rect); 171 info->screen_base += ep->fb8_buf_diff; 172 cfb_fillrect(info, rect); 173 info->screen_base -= ep->fb8_buf_diff; 174 spin_unlock_irqrestore(&ep->lock, flags); 175 } 176 177 static void e3d_copyarea(struct fb_info *info, const struct fb_copyarea *area) 178 { 179 struct e3d_info *ep = info->par; 180 unsigned long flags; 181 182 spin_lock_irqsave(&ep->lock, flags); 183 cfb_copyarea(info, area); 184 info->screen_base += ep->fb8_buf_diff; 185 cfb_copyarea(info, area); 186 info->screen_base -= ep->fb8_buf_diff; 187 spin_unlock_irqrestore(&ep->lock, flags); 188 } 189 190 static const struct fb_ops e3d_ops = { 191 .owner = THIS_MODULE, 192 .fb_setcolreg = e3d_setcolreg, 193 .fb_fillrect = e3d_fillrect, 194 .fb_copyarea = e3d_copyarea, 195 .fb_imageblit = e3d_imageblit, 196 }; 197 198 static int e3d_set_fbinfo(struct e3d_info *ep) 199 { 200 struct fb_info *info = ep->info; 201 struct fb_var_screeninfo *var = &info->var; 202 203 info->flags = FBINFO_DEFAULT; 204 info->fbops = &e3d_ops; 205 info->screen_base = ep->fb_base; 206 info->screen_size = ep->fb_size; 207 208 info->pseudo_palette = ep->pseudo_palette; 209 210 /* Fill fix common fields */ 211 strscpy(info->fix.id, "e3d", sizeof(info->fix.id)); 212 info->fix.smem_start = ep->fb_base_phys; 213 info->fix.smem_len = ep->fb_size; 214 info->fix.type = FB_TYPE_PACKED_PIXELS; 215 if (ep->depth == 32 || ep->depth == 24) 216 info->fix.visual = FB_VISUAL_TRUECOLOR; 217 else 218 info->fix.visual = FB_VISUAL_PSEUDOCOLOR; 219 220 var->xres = ep->width; 221 var->yres = ep->height; 222 var->xres_virtual = var->xres; 223 var->yres_virtual = var->yres; 224 var->bits_per_pixel = ep->depth; 225 226 var->red.offset = 8; 227 var->red.length = 8; 228 var->green.offset = 16; 229 var->green.length = 8; 230 var->blue.offset = 24; 231 var->blue.length = 8; 232 var->transp.offset = 0; 233 var->transp.length = 0; 234 235 if (fb_alloc_cmap(&info->cmap, 256, 0)) { 236 printk(KERN_ERR "e3d: Cannot allocate color map.\n"); 237 return -ENOMEM; 238 } 239 240 return 0; 241 } 242 243 static int e3d_pci_register(struct pci_dev *pdev, 244 const struct pci_device_id *ent) 245 { 246 struct device_node *of_node; 247 const char *device_type; 248 struct fb_info *info; 249 struct e3d_info *ep; 250 unsigned int line_length; 251 int err; 252 253 err = aperture_remove_conflicting_pci_devices(pdev, "e3dfb"); 254 if (err) 255 return err; 256 257 of_node = pci_device_to_OF_node(pdev); 258 if (!of_node) { 259 printk(KERN_ERR "e3d: Cannot find OF node of %s\n", 260 pci_name(pdev)); 261 return -ENODEV; 262 } 263 264 device_type = of_get_property(of_node, "device_type", NULL); 265 if (!device_type) { 266 printk(KERN_INFO "e3d: Ignoring secondary output device " 267 "at %s\n", pci_name(pdev)); 268 return -ENODEV; 269 } 270 271 err = pci_enable_device(pdev); 272 if (err < 0) { 273 printk(KERN_ERR "e3d: Cannot enable PCI device %s\n", 274 pci_name(pdev)); 275 goto err_out; 276 } 277 278 info = framebuffer_alloc(sizeof(struct e3d_info), &pdev->dev); 279 if (!info) { 280 err = -ENOMEM; 281 goto err_disable; 282 } 283 284 ep = info->par; 285 ep->info = info; 286 ep->pdev = pdev; 287 spin_lock_init(&ep->lock); 288 ep->of_node = of_node; 289 290 /* Read the PCI base register of the frame buffer, which we 291 * need in order to interpret the RAMDAC_VID_*FB* values in 292 * the ramdac correctly. 293 */ 294 pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0, 295 &ep->fb_base_reg); 296 ep->fb_base_reg &= PCI_BASE_ADDRESS_MEM_MASK; 297 298 ep->regs_base_phys = pci_resource_start (pdev, 1); 299 err = pci_request_region(pdev, 1, "e3d regs"); 300 if (err < 0) { 301 printk("e3d: Cannot request region 1 for %s\n", 302 pci_name(pdev)); 303 goto err_release_fb; 304 } 305 ep->ramdac = ioremap(ep->regs_base_phys + 0x8000, 0x1000); 306 if (!ep->ramdac) { 307 err = -ENOMEM; 308 goto err_release_pci1; 309 } 310 311 ep->fb8_0_off = readl(ep->ramdac + RAMDAC_VID_8FB_0); 312 ep->fb8_0_off -= ep->fb_base_reg; 313 314 ep->fb8_1_off = readl(ep->ramdac + RAMDAC_VID_8FB_1); 315 ep->fb8_1_off -= ep->fb_base_reg; 316 317 ep->fb8_buf_diff = ep->fb8_1_off - ep->fb8_0_off; 318 319 ep->fb_base_phys = pci_resource_start (pdev, 0); 320 ep->fb_base_phys += ep->fb8_0_off; 321 322 err = pci_request_region(pdev, 0, "e3d framebuffer"); 323 if (err < 0) { 324 printk("e3d: Cannot request region 0 for %s\n", 325 pci_name(pdev)); 326 goto err_unmap_ramdac; 327 } 328 329 err = e3d_get_props(ep); 330 if (err) 331 goto err_release_pci0; 332 333 line_length = (readl(ep->ramdac + RAMDAC_VID_CFG) >> 16) & 0xff; 334 line_length = 1 << line_length; 335 336 switch (ep->depth) { 337 case 8: 338 info->fix.line_length = line_length; 339 break; 340 case 16: 341 info->fix.line_length = line_length * 2; 342 break; 343 case 24: 344 info->fix.line_length = line_length * 3; 345 break; 346 case 32: 347 info->fix.line_length = line_length * 4; 348 break; 349 } 350 ep->fb_size = info->fix.line_length * ep->height; 351 352 ep->fb_base = ioremap(ep->fb_base_phys, ep->fb_size); 353 if (!ep->fb_base) { 354 err = -ENOMEM; 355 goto err_release_pci0; 356 } 357 358 err = e3d_set_fbinfo(ep); 359 if (err) 360 goto err_unmap_fb; 361 362 pci_set_drvdata(pdev, info); 363 364 printk("e3d: Found device at %s\n", pci_name(pdev)); 365 366 err = register_framebuffer(info); 367 if (err < 0) { 368 printk(KERN_ERR "e3d: Could not register framebuffer %s\n", 369 pci_name(pdev)); 370 goto err_free_cmap; 371 } 372 373 return 0; 374 375 err_free_cmap: 376 fb_dealloc_cmap(&info->cmap); 377 378 err_unmap_fb: 379 iounmap(ep->fb_base); 380 381 err_release_pci0: 382 pci_release_region(pdev, 0); 383 384 err_unmap_ramdac: 385 iounmap(ep->ramdac); 386 387 err_release_pci1: 388 pci_release_region(pdev, 1); 389 390 err_release_fb: 391 framebuffer_release(info); 392 393 err_disable: 394 pci_disable_device(pdev); 395 396 err_out: 397 return err; 398 } 399 400 static const struct pci_device_id e3d_pci_table[] = { 401 { PCI_DEVICE(PCI_VENDOR_ID_3DLABS, 0x7a0), }, 402 { PCI_DEVICE(0x1091, 0x7a0), }, 403 { PCI_DEVICE(PCI_VENDOR_ID_3DLABS, 0x7a2), }, 404 { .vendor = PCI_VENDOR_ID_3DLABS, 405 .device = PCI_ANY_ID, 406 .subvendor = PCI_VENDOR_ID_3DLABS, 407 .subdevice = 0x0108, 408 }, 409 { .vendor = PCI_VENDOR_ID_3DLABS, 410 .device = PCI_ANY_ID, 411 .subvendor = PCI_VENDOR_ID_3DLABS, 412 .subdevice = 0x0140, 413 }, 414 { .vendor = PCI_VENDOR_ID_3DLABS, 415 .device = PCI_ANY_ID, 416 .subvendor = PCI_VENDOR_ID_3DLABS, 417 .subdevice = 0x1024, 418 }, 419 { 0, } 420 }; 421 422 static struct pci_driver e3d_driver = { 423 .driver = { 424 .suppress_bind_attrs = true, 425 }, 426 .name = "e3d", 427 .id_table = e3d_pci_table, 428 .probe = e3d_pci_register, 429 }; 430 431 static int __init e3d_init(void) 432 { 433 if (fb_get_options("e3d", NULL)) 434 return -ENODEV; 435 436 return pci_register_driver(&e3d_driver); 437 } 438 device_initcall(e3d_init); 439