1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * smscufx.c -- Framebuffer driver for SMSC UFX USB controller 4 * 5 * Copyright (C) 2011 Steve Glendinning <steve.glendinning@shawell.net> 6 * Copyright (C) 2009 Roberto De Ioris <roberto@unbit.it> 7 * Copyright (C) 2009 Jaya Kumar <jayakumar.lkml@gmail.com> 8 * Copyright (C) 2009 Bernie Thompson <bernie@plugable.com> 9 * 10 * Based on udlfb, with work from Florian Echtler, Henrik Bjerregaard Pedersen, 11 * and others. 12 * 13 * Works well with Bernie Thompson's X DAMAGE patch to xf86-video-fbdev 14 * available from http://git.plugable.com 15 * 16 * Layout is based on skeletonfb by James Simmons and Geert Uytterhoeven, 17 * usb-skeleton by GregKH. 18 */ 19 20 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 21 22 #include <linux/module.h> 23 #include <linux/kernel.h> 24 #include <linux/init.h> 25 #include <linux/usb.h> 26 #include <linux/uaccess.h> 27 #include <linux/mm.h> 28 #include <linux/fb.h> 29 #include <linux/vmalloc.h> 30 #include <linux/slab.h> 31 #include <linux/delay.h> 32 #include "edid.h" 33 34 #define check_warn(status, fmt, args...) \ 35 ({ if (status < 0) pr_warn(fmt, ##args); }) 36 37 #define check_warn_return(status, fmt, args...) \ 38 ({ if (status < 0) { pr_warn(fmt, ##args); return status; } }) 39 40 #define check_warn_goto_error(status, fmt, args...) \ 41 ({ if (status < 0) { pr_warn(fmt, ##args); goto error; } }) 42 43 #define all_bits_set(x, bits) (((x) & (bits)) == (bits)) 44 45 #define USB_VENDOR_REQUEST_WRITE_REGISTER 0xA0 46 #define USB_VENDOR_REQUEST_READ_REGISTER 0xA1 47 48 /* 49 * TODO: Propose standard fb.h ioctl for reporting damage, 50 * using _IOWR() and one of the existing area structs from fb.h 51 * Consider these ioctls deprecated, but they're still used by the 52 * DisplayLink X server as yet - need both to be modified in tandem 53 * when new ioctl(s) are ready. 54 */ 55 #define UFX_IOCTL_RETURN_EDID (0xAD) 56 #define UFX_IOCTL_REPORT_DAMAGE (0xAA) 57 58 /* -BULK_SIZE as per usb-skeleton. Can we get full page and avoid overhead? */ 59 #define BULK_SIZE (512) 60 #define MAX_TRANSFER (PAGE_SIZE*16 - BULK_SIZE) 61 #define WRITES_IN_FLIGHT (4) 62 63 #define GET_URB_TIMEOUT (HZ) 64 #define FREE_URB_TIMEOUT (HZ*2) 65 66 #define BPP 2 67 68 #define UFX_DEFIO_WRITE_DELAY 5 /* fb_deferred_io.delay in jiffies */ 69 #define UFX_DEFIO_WRITE_DISABLE (HZ*60) /* "disable" with long delay */ 70 71 struct dloarea { 72 int x, y; 73 int w, h; 74 }; 75 76 struct urb_node { 77 struct list_head entry; 78 struct ufx_data *dev; 79 struct delayed_work release_urb_work; 80 struct urb *urb; 81 }; 82 83 struct urb_list { 84 struct list_head list; 85 spinlock_t lock; 86 struct semaphore limit_sem; 87 int available; 88 int count; 89 size_t size; 90 }; 91 92 struct ufx_data { 93 struct usb_device *udev; 94 struct device *gdev; /* &udev->dev */ 95 struct fb_info *info; 96 struct urb_list urbs; 97 struct kref kref; 98 int fb_count; 99 bool virtualized; /* true when physical usb device not present */ 100 struct delayed_work free_framebuffer_work; 101 atomic_t usb_active; /* 0 = update virtual buffer, but no usb traffic */ 102 atomic_t lost_pixels; /* 1 = a render op failed. Need screen refresh */ 103 u8 *edid; /* null until we read edid from hw or get from sysfs */ 104 size_t edid_size; 105 u32 pseudo_palette[256]; 106 }; 107 108 static struct fb_fix_screeninfo ufx_fix = { 109 .id = "smscufx", 110 .type = FB_TYPE_PACKED_PIXELS, 111 .visual = FB_VISUAL_TRUECOLOR, 112 .xpanstep = 0, 113 .ypanstep = 0, 114 .ywrapstep = 0, 115 .accel = FB_ACCEL_NONE, 116 }; 117 118 static const u32 smscufx_info_flags = FBINFO_DEFAULT | FBINFO_READS_FAST | 119 FBINFO_VIRTFB | FBINFO_HWACCEL_IMAGEBLIT | FBINFO_HWACCEL_FILLRECT | 120 FBINFO_HWACCEL_COPYAREA | FBINFO_MISC_ALWAYS_SETPAR; 121 122 static const struct usb_device_id id_table[] = { 123 {USB_DEVICE(0x0424, 0x9d00),}, 124 {USB_DEVICE(0x0424, 0x9d01),}, 125 {}, 126 }; 127 MODULE_DEVICE_TABLE(usb, id_table); 128 129 /* module options */ 130 static bool console; /* Optionally allow fbcon to consume first framebuffer */ 131 static bool fb_defio = true; /* Optionally enable fb_defio mmap support */ 132 133 /* ufx keeps a list of urbs for efficient bulk transfers */ 134 static void ufx_urb_completion(struct urb *urb); 135 static struct urb *ufx_get_urb(struct ufx_data *dev); 136 static int ufx_submit_urb(struct ufx_data *dev, struct urb * urb, size_t len); 137 static int ufx_alloc_urb_list(struct ufx_data *dev, int count, size_t size); 138 static void ufx_free_urb_list(struct ufx_data *dev); 139 140 /* reads a control register */ 141 static int ufx_reg_read(struct ufx_data *dev, u32 index, u32 *data) 142 { 143 u32 *buf = kmalloc(4, GFP_KERNEL); 144 int ret; 145 146 BUG_ON(!dev); 147 148 if (!buf) 149 return -ENOMEM; 150 151 ret = usb_control_msg(dev->udev, usb_rcvctrlpipe(dev->udev, 0), 152 USB_VENDOR_REQUEST_READ_REGISTER, 153 USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE, 154 00, index, buf, 4, USB_CTRL_GET_TIMEOUT); 155 156 le32_to_cpus(buf); 157 *data = *buf; 158 kfree(buf); 159 160 if (unlikely(ret < 0)) 161 pr_warn("Failed to read register index 0x%08x\n", index); 162 163 return ret; 164 } 165 166 /* writes a control register */ 167 static int ufx_reg_write(struct ufx_data *dev, u32 index, u32 data) 168 { 169 u32 *buf = kmalloc(4, GFP_KERNEL); 170 int ret; 171 172 BUG_ON(!dev); 173 174 if (!buf) 175 return -ENOMEM; 176 177 *buf = data; 178 cpu_to_le32s(buf); 179 180 ret = usb_control_msg(dev->udev, usb_sndctrlpipe(dev->udev, 0), 181 USB_VENDOR_REQUEST_WRITE_REGISTER, 182 USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE, 183 00, index, buf, 4, USB_CTRL_SET_TIMEOUT); 184 185 kfree(buf); 186 187 if (unlikely(ret < 0)) 188 pr_warn("Failed to write register index 0x%08x with value " 189 "0x%08x\n", index, data); 190 191 return ret; 192 } 193 194 static int ufx_reg_clear_and_set_bits(struct ufx_data *dev, u32 index, 195 u32 bits_to_clear, u32 bits_to_set) 196 { 197 u32 data; 198 int status = ufx_reg_read(dev, index, &data); 199 check_warn_return(status, "ufx_reg_clear_and_set_bits error reading " 200 "0x%x", index); 201 202 data &= (~bits_to_clear); 203 data |= bits_to_set; 204 205 status = ufx_reg_write(dev, index, data); 206 check_warn_return(status, "ufx_reg_clear_and_set_bits error writing " 207 "0x%x", index); 208 209 return 0; 210 } 211 212 static int ufx_reg_set_bits(struct ufx_data *dev, u32 index, u32 bits) 213 { 214 return ufx_reg_clear_and_set_bits(dev, index, 0, bits); 215 } 216 217 static int ufx_reg_clear_bits(struct ufx_data *dev, u32 index, u32 bits) 218 { 219 return ufx_reg_clear_and_set_bits(dev, index, bits, 0); 220 } 221 222 static int ufx_lite_reset(struct ufx_data *dev) 223 { 224 int status; 225 u32 value; 226 227 status = ufx_reg_write(dev, 0x3008, 0x00000001); 228 check_warn_return(status, "ufx_lite_reset error writing 0x3008"); 229 230 status = ufx_reg_read(dev, 0x3008, &value); 231 check_warn_return(status, "ufx_lite_reset error reading 0x3008"); 232 233 return (value == 0) ? 0 : -EIO; 234 } 235 236 /* If display is unblanked, then blank it */ 237 static int ufx_blank(struct ufx_data *dev, bool wait) 238 { 239 u32 dc_ctrl, dc_sts; 240 int i; 241 242 int status = ufx_reg_read(dev, 0x2004, &dc_sts); 243 check_warn_return(status, "ufx_blank error reading 0x2004"); 244 245 status = ufx_reg_read(dev, 0x2000, &dc_ctrl); 246 check_warn_return(status, "ufx_blank error reading 0x2000"); 247 248 /* return success if display is already blanked */ 249 if ((dc_sts & 0x00000100) || (dc_ctrl & 0x00000100)) 250 return 0; 251 252 /* request the DC to blank the display */ 253 dc_ctrl |= 0x00000100; 254 status = ufx_reg_write(dev, 0x2000, dc_ctrl); 255 check_warn_return(status, "ufx_blank error writing 0x2000"); 256 257 /* return success immediately if we don't have to wait */ 258 if (!wait) 259 return 0; 260 261 for (i = 0; i < 250; i++) { 262 status = ufx_reg_read(dev, 0x2004, &dc_sts); 263 check_warn_return(status, "ufx_blank error reading 0x2004"); 264 265 if (dc_sts & 0x00000100) 266 return 0; 267 } 268 269 /* timed out waiting for display to blank */ 270 return -EIO; 271 } 272 273 /* If display is blanked, then unblank it */ 274 static int ufx_unblank(struct ufx_data *dev, bool wait) 275 { 276 u32 dc_ctrl, dc_sts; 277 int i; 278 279 int status = ufx_reg_read(dev, 0x2004, &dc_sts); 280 check_warn_return(status, "ufx_unblank error reading 0x2004"); 281 282 status = ufx_reg_read(dev, 0x2000, &dc_ctrl); 283 check_warn_return(status, "ufx_unblank error reading 0x2000"); 284 285 /* return success if display is already unblanked */ 286 if (((dc_sts & 0x00000100) == 0) || ((dc_ctrl & 0x00000100) == 0)) 287 return 0; 288 289 /* request the DC to unblank the display */ 290 dc_ctrl &= ~0x00000100; 291 status = ufx_reg_write(dev, 0x2000, dc_ctrl); 292 check_warn_return(status, "ufx_unblank error writing 0x2000"); 293 294 /* return success immediately if we don't have to wait */ 295 if (!wait) 296 return 0; 297 298 for (i = 0; i < 250; i++) { 299 status = ufx_reg_read(dev, 0x2004, &dc_sts); 300 check_warn_return(status, "ufx_unblank error reading 0x2004"); 301 302 if ((dc_sts & 0x00000100) == 0) 303 return 0; 304 } 305 306 /* timed out waiting for display to unblank */ 307 return -EIO; 308 } 309 310 /* If display is enabled, then disable it */ 311 static int ufx_disable(struct ufx_data *dev, bool wait) 312 { 313 u32 dc_ctrl, dc_sts; 314 int i; 315 316 int status = ufx_reg_read(dev, 0x2004, &dc_sts); 317 check_warn_return(status, "ufx_disable error reading 0x2004"); 318 319 status = ufx_reg_read(dev, 0x2000, &dc_ctrl); 320 check_warn_return(status, "ufx_disable error reading 0x2000"); 321 322 /* return success if display is already disabled */ 323 if (((dc_sts & 0x00000001) == 0) || ((dc_ctrl & 0x00000001) == 0)) 324 return 0; 325 326 /* request the DC to disable the display */ 327 dc_ctrl &= ~(0x00000001); 328 status = ufx_reg_write(dev, 0x2000, dc_ctrl); 329 check_warn_return(status, "ufx_disable error writing 0x2000"); 330 331 /* return success immediately if we don't have to wait */ 332 if (!wait) 333 return 0; 334 335 for (i = 0; i < 250; i++) { 336 status = ufx_reg_read(dev, 0x2004, &dc_sts); 337 check_warn_return(status, "ufx_disable error reading 0x2004"); 338 339 if ((dc_sts & 0x00000001) == 0) 340 return 0; 341 } 342 343 /* timed out waiting for display to disable */ 344 return -EIO; 345 } 346 347 /* If display is disabled, then enable it */ 348 static int ufx_enable(struct ufx_data *dev, bool wait) 349 { 350 u32 dc_ctrl, dc_sts; 351 int i; 352 353 int status = ufx_reg_read(dev, 0x2004, &dc_sts); 354 check_warn_return(status, "ufx_enable error reading 0x2004"); 355 356 status = ufx_reg_read(dev, 0x2000, &dc_ctrl); 357 check_warn_return(status, "ufx_enable error reading 0x2000"); 358 359 /* return success if display is already enabled */ 360 if ((dc_sts & 0x00000001) || (dc_ctrl & 0x00000001)) 361 return 0; 362 363 /* request the DC to enable the display */ 364 dc_ctrl |= 0x00000001; 365 status = ufx_reg_write(dev, 0x2000, dc_ctrl); 366 check_warn_return(status, "ufx_enable error writing 0x2000"); 367 368 /* return success immediately if we don't have to wait */ 369 if (!wait) 370 return 0; 371 372 for (i = 0; i < 250; i++) { 373 status = ufx_reg_read(dev, 0x2004, &dc_sts); 374 check_warn_return(status, "ufx_enable error reading 0x2004"); 375 376 if (dc_sts & 0x00000001) 377 return 0; 378 } 379 380 /* timed out waiting for display to enable */ 381 return -EIO; 382 } 383 384 static int ufx_config_sys_clk(struct ufx_data *dev) 385 { 386 int status = ufx_reg_write(dev, 0x700C, 0x8000000F); 387 check_warn_return(status, "error writing 0x700C"); 388 389 status = ufx_reg_write(dev, 0x7014, 0x0010024F); 390 check_warn_return(status, "error writing 0x7014"); 391 392 status = ufx_reg_write(dev, 0x7010, 0x00000000); 393 check_warn_return(status, "error writing 0x7010"); 394 395 status = ufx_reg_clear_bits(dev, 0x700C, 0x0000000A); 396 check_warn_return(status, "error clearing PLL1 bypass in 0x700C"); 397 msleep(1); 398 399 status = ufx_reg_clear_bits(dev, 0x700C, 0x80000000); 400 check_warn_return(status, "error clearing output gate in 0x700C"); 401 402 return 0; 403 } 404 405 static int ufx_config_ddr2(struct ufx_data *dev) 406 { 407 int status, i = 0; 408 u32 tmp; 409 410 status = ufx_reg_write(dev, 0x0004, 0x001F0F77); 411 check_warn_return(status, "error writing 0x0004"); 412 413 status = ufx_reg_write(dev, 0x0008, 0xFFF00000); 414 check_warn_return(status, "error writing 0x0008"); 415 416 status = ufx_reg_write(dev, 0x000C, 0x0FFF2222); 417 check_warn_return(status, "error writing 0x000C"); 418 419 status = ufx_reg_write(dev, 0x0010, 0x00030814); 420 check_warn_return(status, "error writing 0x0010"); 421 422 status = ufx_reg_write(dev, 0x0014, 0x00500019); 423 check_warn_return(status, "error writing 0x0014"); 424 425 status = ufx_reg_write(dev, 0x0018, 0x020D0F15); 426 check_warn_return(status, "error writing 0x0018"); 427 428 status = ufx_reg_write(dev, 0x001C, 0x02532305); 429 check_warn_return(status, "error writing 0x001C"); 430 431 status = ufx_reg_write(dev, 0x0020, 0x0B030905); 432 check_warn_return(status, "error writing 0x0020"); 433 434 status = ufx_reg_write(dev, 0x0024, 0x00000827); 435 check_warn_return(status, "error writing 0x0024"); 436 437 status = ufx_reg_write(dev, 0x0028, 0x00000000); 438 check_warn_return(status, "error writing 0x0028"); 439 440 status = ufx_reg_write(dev, 0x002C, 0x00000042); 441 check_warn_return(status, "error writing 0x002C"); 442 443 status = ufx_reg_write(dev, 0x0030, 0x09520000); 444 check_warn_return(status, "error writing 0x0030"); 445 446 status = ufx_reg_write(dev, 0x0034, 0x02223314); 447 check_warn_return(status, "error writing 0x0034"); 448 449 status = ufx_reg_write(dev, 0x0038, 0x00430043); 450 check_warn_return(status, "error writing 0x0038"); 451 452 status = ufx_reg_write(dev, 0x003C, 0xF00F000F); 453 check_warn_return(status, "error writing 0x003C"); 454 455 status = ufx_reg_write(dev, 0x0040, 0xF380F00F); 456 check_warn_return(status, "error writing 0x0040"); 457 458 status = ufx_reg_write(dev, 0x0044, 0xF00F0496); 459 check_warn_return(status, "error writing 0x0044"); 460 461 status = ufx_reg_write(dev, 0x0048, 0x03080406); 462 check_warn_return(status, "error writing 0x0048"); 463 464 status = ufx_reg_write(dev, 0x004C, 0x00001000); 465 check_warn_return(status, "error writing 0x004C"); 466 467 status = ufx_reg_write(dev, 0x005C, 0x00000007); 468 check_warn_return(status, "error writing 0x005C"); 469 470 status = ufx_reg_write(dev, 0x0100, 0x54F00012); 471 check_warn_return(status, "error writing 0x0100"); 472 473 status = ufx_reg_write(dev, 0x0104, 0x00004012); 474 check_warn_return(status, "error writing 0x0104"); 475 476 status = ufx_reg_write(dev, 0x0118, 0x40404040); 477 check_warn_return(status, "error writing 0x0118"); 478 479 status = ufx_reg_write(dev, 0x0000, 0x00000001); 480 check_warn_return(status, "error writing 0x0000"); 481 482 while (i++ < 500) { 483 status = ufx_reg_read(dev, 0x0000, &tmp); 484 check_warn_return(status, "error reading 0x0000"); 485 486 if (all_bits_set(tmp, 0xC0000000)) 487 return 0; 488 } 489 490 pr_err("DDR2 initialisation timed out, reg 0x0000=0x%08x", tmp); 491 return -ETIMEDOUT; 492 } 493 494 struct pll_values { 495 u32 div_r0; 496 u32 div_f0; 497 u32 div_q0; 498 u32 range0; 499 u32 div_r1; 500 u32 div_f1; 501 u32 div_q1; 502 u32 range1; 503 }; 504 505 static u32 ufx_calc_range(u32 ref_freq) 506 { 507 if (ref_freq >= 88000000) 508 return 7; 509 510 if (ref_freq >= 54000000) 511 return 6; 512 513 if (ref_freq >= 34000000) 514 return 5; 515 516 if (ref_freq >= 21000000) 517 return 4; 518 519 if (ref_freq >= 13000000) 520 return 3; 521 522 if (ref_freq >= 8000000) 523 return 2; 524 525 return 1; 526 } 527 528 /* calculates PLL divider settings for a desired target frequency */ 529 static void ufx_calc_pll_values(const u32 clk_pixel_pll, struct pll_values *asic_pll) 530 { 531 const u32 ref_clk = 25000000; 532 u32 div_r0, div_f0, div_q0, div_r1, div_f1, div_q1; 533 u32 min_error = clk_pixel_pll; 534 535 for (div_r0 = 1; div_r0 <= 32; div_r0++) { 536 u32 ref_freq0 = ref_clk / div_r0; 537 if (ref_freq0 < 5000000) 538 break; 539 540 if (ref_freq0 > 200000000) 541 continue; 542 543 for (div_f0 = 1; div_f0 <= 256; div_f0++) { 544 u32 vco_freq0 = ref_freq0 * div_f0; 545 546 if (vco_freq0 < 350000000) 547 continue; 548 549 if (vco_freq0 > 700000000) 550 break; 551 552 for (div_q0 = 0; div_q0 < 7; div_q0++) { 553 u32 pllout_freq0 = vco_freq0 / (1 << div_q0); 554 555 if (pllout_freq0 < 5000000) 556 break; 557 558 if (pllout_freq0 > 200000000) 559 continue; 560 561 for (div_r1 = 1; div_r1 <= 32; div_r1++) { 562 u32 ref_freq1 = pllout_freq0 / div_r1; 563 564 if (ref_freq1 < 5000000) 565 break; 566 567 for (div_f1 = 1; div_f1 <= 256; div_f1++) { 568 u32 vco_freq1 = ref_freq1 * div_f1; 569 570 if (vco_freq1 < 350000000) 571 continue; 572 573 if (vco_freq1 > 700000000) 574 break; 575 576 for (div_q1 = 0; div_q1 < 7; div_q1++) { 577 u32 pllout_freq1 = vco_freq1 / (1 << div_q1); 578 int error = abs(pllout_freq1 - clk_pixel_pll); 579 580 if (pllout_freq1 < 5000000) 581 break; 582 583 if (pllout_freq1 > 700000000) 584 continue; 585 586 if (error < min_error) { 587 min_error = error; 588 589 /* final returned value is equal to calculated value - 1 590 * because a value of 0 = divide by 1 */ 591 asic_pll->div_r0 = div_r0 - 1; 592 asic_pll->div_f0 = div_f0 - 1; 593 asic_pll->div_q0 = div_q0; 594 asic_pll->div_r1 = div_r1 - 1; 595 asic_pll->div_f1 = div_f1 - 1; 596 asic_pll->div_q1 = div_q1; 597 598 asic_pll->range0 = ufx_calc_range(ref_freq0); 599 asic_pll->range1 = ufx_calc_range(ref_freq1); 600 601 if (min_error == 0) 602 return; 603 } 604 } 605 } 606 } 607 } 608 } 609 } 610 } 611 612 /* sets analog bit PLL configuration values */ 613 static int ufx_config_pix_clk(struct ufx_data *dev, u32 pixclock) 614 { 615 struct pll_values asic_pll = {0}; 616 u32 value, clk_pixel, clk_pixel_pll; 617 int status; 618 619 /* convert pixclock (in ps) to frequency (in Hz) */ 620 clk_pixel = PICOS2KHZ(pixclock) * 1000; 621 pr_debug("pixclock %d ps = clk_pixel %d Hz", pixclock, clk_pixel); 622 623 /* clk_pixel = 1/2 clk_pixel_pll */ 624 clk_pixel_pll = clk_pixel * 2; 625 626 ufx_calc_pll_values(clk_pixel_pll, &asic_pll); 627 628 /* Keep BYPASS and RESET signals asserted until configured */ 629 status = ufx_reg_write(dev, 0x7000, 0x8000000F); 630 check_warn_return(status, "error writing 0x7000"); 631 632 value = (asic_pll.div_f1 | (asic_pll.div_r1 << 8) | 633 (asic_pll.div_q1 << 16) | (asic_pll.range1 << 20)); 634 status = ufx_reg_write(dev, 0x7008, value); 635 check_warn_return(status, "error writing 0x7008"); 636 637 value = (asic_pll.div_f0 | (asic_pll.div_r0 << 8) | 638 (asic_pll.div_q0 << 16) | (asic_pll.range0 << 20)); 639 status = ufx_reg_write(dev, 0x7004, value); 640 check_warn_return(status, "error writing 0x7004"); 641 642 status = ufx_reg_clear_bits(dev, 0x7000, 0x00000005); 643 check_warn_return(status, 644 "error clearing PLL0 bypass bits in 0x7000"); 645 msleep(1); 646 647 status = ufx_reg_clear_bits(dev, 0x7000, 0x0000000A); 648 check_warn_return(status, 649 "error clearing PLL1 bypass bits in 0x7000"); 650 msleep(1); 651 652 status = ufx_reg_clear_bits(dev, 0x7000, 0x80000000); 653 check_warn_return(status, "error clearing gate bits in 0x7000"); 654 655 return 0; 656 } 657 658 static int ufx_set_vid_mode(struct ufx_data *dev, struct fb_var_screeninfo *var) 659 { 660 u32 temp; 661 u16 h_total, h_active, h_blank_start, h_blank_end, h_sync_start, h_sync_end; 662 u16 v_total, v_active, v_blank_start, v_blank_end, v_sync_start, v_sync_end; 663 664 int status = ufx_reg_write(dev, 0x8028, 0); 665 check_warn_return(status, "ufx_set_vid_mode error disabling RGB pad"); 666 667 status = ufx_reg_write(dev, 0x8024, 0); 668 check_warn_return(status, "ufx_set_vid_mode error disabling VDAC"); 669 670 /* shut everything down before changing timing */ 671 status = ufx_blank(dev, true); 672 check_warn_return(status, "ufx_set_vid_mode error blanking display"); 673 674 status = ufx_disable(dev, true); 675 check_warn_return(status, "ufx_set_vid_mode error disabling display"); 676 677 status = ufx_config_pix_clk(dev, var->pixclock); 678 check_warn_return(status, "ufx_set_vid_mode error configuring pixclock"); 679 680 status = ufx_reg_write(dev, 0x2000, 0x00000104); 681 check_warn_return(status, "ufx_set_vid_mode error writing 0x2000"); 682 683 /* set horizontal timings */ 684 h_total = var->xres + var->right_margin + var->hsync_len + var->left_margin; 685 h_active = var->xres; 686 h_blank_start = var->xres + var->right_margin; 687 h_blank_end = var->xres + var->right_margin + var->hsync_len; 688 h_sync_start = var->xres + var->right_margin; 689 h_sync_end = var->xres + var->right_margin + var->hsync_len; 690 691 temp = ((h_total - 1) << 16) | (h_active - 1); 692 status = ufx_reg_write(dev, 0x2008, temp); 693 check_warn_return(status, "ufx_set_vid_mode error writing 0x2008"); 694 695 temp = ((h_blank_start - 1) << 16) | (h_blank_end - 1); 696 status = ufx_reg_write(dev, 0x200C, temp); 697 check_warn_return(status, "ufx_set_vid_mode error writing 0x200C"); 698 699 temp = ((h_sync_start - 1) << 16) | (h_sync_end - 1); 700 status = ufx_reg_write(dev, 0x2010, temp); 701 check_warn_return(status, "ufx_set_vid_mode error writing 0x2010"); 702 703 /* set vertical timings */ 704 v_total = var->upper_margin + var->yres + var->lower_margin + var->vsync_len; 705 v_active = var->yres; 706 v_blank_start = var->yres + var->lower_margin; 707 v_blank_end = var->yres + var->lower_margin + var->vsync_len; 708 v_sync_start = var->yres + var->lower_margin; 709 v_sync_end = var->yres + var->lower_margin + var->vsync_len; 710 711 temp = ((v_total - 1) << 16) | (v_active - 1); 712 status = ufx_reg_write(dev, 0x2014, temp); 713 check_warn_return(status, "ufx_set_vid_mode error writing 0x2014"); 714 715 temp = ((v_blank_start - 1) << 16) | (v_blank_end - 1); 716 status = ufx_reg_write(dev, 0x2018, temp); 717 check_warn_return(status, "ufx_set_vid_mode error writing 0x2018"); 718 719 temp = ((v_sync_start - 1) << 16) | (v_sync_end - 1); 720 status = ufx_reg_write(dev, 0x201C, temp); 721 check_warn_return(status, "ufx_set_vid_mode error writing 0x201C"); 722 723 status = ufx_reg_write(dev, 0x2020, 0x00000000); 724 check_warn_return(status, "ufx_set_vid_mode error writing 0x2020"); 725 726 status = ufx_reg_write(dev, 0x2024, 0x00000000); 727 check_warn_return(status, "ufx_set_vid_mode error writing 0x2024"); 728 729 /* Set the frame length register (#pix * 2 bytes/pixel) */ 730 temp = var->xres * var->yres * 2; 731 temp = (temp + 7) & (~0x7); 732 status = ufx_reg_write(dev, 0x2028, temp); 733 check_warn_return(status, "ufx_set_vid_mode error writing 0x2028"); 734 735 /* enable desired output interface & disable others */ 736 status = ufx_reg_write(dev, 0x2040, 0); 737 check_warn_return(status, "ufx_set_vid_mode error writing 0x2040"); 738 739 status = ufx_reg_write(dev, 0x2044, 0); 740 check_warn_return(status, "ufx_set_vid_mode error writing 0x2044"); 741 742 status = ufx_reg_write(dev, 0x2048, 0); 743 check_warn_return(status, "ufx_set_vid_mode error writing 0x2048"); 744 745 /* set the sync polarities & enable bit */ 746 temp = 0x00000001; 747 if (var->sync & FB_SYNC_HOR_HIGH_ACT) 748 temp |= 0x00000010; 749 750 if (var->sync & FB_SYNC_VERT_HIGH_ACT) 751 temp |= 0x00000008; 752 753 status = ufx_reg_write(dev, 0x2040, temp); 754 check_warn_return(status, "ufx_set_vid_mode error writing 0x2040"); 755 756 /* start everything back up */ 757 status = ufx_enable(dev, true); 758 check_warn_return(status, "ufx_set_vid_mode error enabling display"); 759 760 /* Unblank the display */ 761 status = ufx_unblank(dev, true); 762 check_warn_return(status, "ufx_set_vid_mode error unblanking display"); 763 764 /* enable RGB pad */ 765 status = ufx_reg_write(dev, 0x8028, 0x00000003); 766 check_warn_return(status, "ufx_set_vid_mode error enabling RGB pad"); 767 768 /* enable VDAC */ 769 status = ufx_reg_write(dev, 0x8024, 0x00000007); 770 check_warn_return(status, "ufx_set_vid_mode error enabling VDAC"); 771 772 return 0; 773 } 774 775 static int ufx_ops_mmap(struct fb_info *info, struct vm_area_struct *vma) 776 { 777 unsigned long start = vma->vm_start; 778 unsigned long size = vma->vm_end - vma->vm_start; 779 unsigned long offset = vma->vm_pgoff << PAGE_SHIFT; 780 unsigned long page, pos; 781 782 if (vma->vm_pgoff > (~0UL >> PAGE_SHIFT)) 783 return -EINVAL; 784 if (size > info->fix.smem_len) 785 return -EINVAL; 786 if (offset > info->fix.smem_len - size) 787 return -EINVAL; 788 789 pos = (unsigned long)info->fix.smem_start + offset; 790 791 pr_debug("mmap() framebuffer addr:%lu size:%lu\n", 792 pos, size); 793 794 while (size > 0) { 795 page = vmalloc_to_pfn((void *)pos); 796 if (remap_pfn_range(vma, start, page, PAGE_SIZE, PAGE_SHARED)) 797 return -EAGAIN; 798 799 start += PAGE_SIZE; 800 pos += PAGE_SIZE; 801 if (size > PAGE_SIZE) 802 size -= PAGE_SIZE; 803 else 804 size = 0; 805 } 806 807 return 0; 808 } 809 810 static void ufx_raw_rect(struct ufx_data *dev, u16 *cmd, int x, int y, 811 int width, int height) 812 { 813 size_t packed_line_len = ALIGN((width * 2), 4); 814 size_t packed_rect_len = packed_line_len * height; 815 int line; 816 817 BUG_ON(!dev); 818 BUG_ON(!dev->info); 819 820 /* command word */ 821 *((u32 *)&cmd[0]) = cpu_to_le32(0x01); 822 823 /* length word */ 824 *((u32 *)&cmd[2]) = cpu_to_le32(packed_rect_len + 16); 825 826 cmd[4] = cpu_to_le16(x); 827 cmd[5] = cpu_to_le16(y); 828 cmd[6] = cpu_to_le16(width); 829 cmd[7] = cpu_to_le16(height); 830 831 /* frame base address */ 832 *((u32 *)&cmd[8]) = cpu_to_le32(0); 833 834 /* color mode and horizontal resolution */ 835 cmd[10] = cpu_to_le16(0x4000 | dev->info->var.xres); 836 837 /* vertical resolution */ 838 cmd[11] = cpu_to_le16(dev->info->var.yres); 839 840 /* packed data */ 841 for (line = 0; line < height; line++) { 842 const int line_offset = dev->info->fix.line_length * (y + line); 843 const int byte_offset = line_offset + (x * BPP); 844 memcpy(&cmd[(24 + (packed_line_len * line)) / 2], 845 (char *)dev->info->fix.smem_start + byte_offset, width * BPP); 846 } 847 } 848 849 static int ufx_handle_damage(struct ufx_data *dev, int x, int y, 850 int width, int height) 851 { 852 size_t packed_line_len = ALIGN((width * 2), 4); 853 int len, status, urb_lines, start_line = 0; 854 855 if ((width <= 0) || (height <= 0) || 856 (x + width > dev->info->var.xres) || 857 (y + height > dev->info->var.yres)) 858 return -EINVAL; 859 860 if (!atomic_read(&dev->usb_active)) 861 return 0; 862 863 while (start_line < height) { 864 struct urb *urb = ufx_get_urb(dev); 865 if (!urb) { 866 pr_warn("ufx_handle_damage unable to get urb"); 867 return 0; 868 } 869 870 /* assume we have enough space to transfer at least one line */ 871 BUG_ON(urb->transfer_buffer_length < (24 + (width * 2))); 872 873 /* calculate the maximum number of lines we could fit in */ 874 urb_lines = (urb->transfer_buffer_length - 24) / packed_line_len; 875 876 /* but we might not need this many */ 877 urb_lines = min(urb_lines, (height - start_line)); 878 879 memset(urb->transfer_buffer, 0, urb->transfer_buffer_length); 880 881 ufx_raw_rect(dev, urb->transfer_buffer, x, (y + start_line), width, urb_lines); 882 len = 24 + (packed_line_len * urb_lines); 883 884 status = ufx_submit_urb(dev, urb, len); 885 check_warn_return(status, "Error submitting URB"); 886 887 start_line += urb_lines; 888 } 889 890 return 0; 891 } 892 893 /* Path triggered by usermode clients who write to filesystem 894 * e.g. cat filename > /dev/fb1 895 * Not used by X Windows or text-mode console. But useful for testing. 896 * Slow because of extra copy and we must assume all pixels dirty. */ 897 static ssize_t ufx_ops_write(struct fb_info *info, const char __user *buf, 898 size_t count, loff_t *ppos) 899 { 900 ssize_t result; 901 struct ufx_data *dev = info->par; 902 u32 offset = (u32) *ppos; 903 904 result = fb_sys_write(info, buf, count, ppos); 905 906 if (result > 0) { 907 int start = max((int)(offset / info->fix.line_length), 0); 908 int lines = min((u32)((result / info->fix.line_length) + 1), 909 (u32)info->var.yres); 910 911 ufx_handle_damage(dev, 0, start, info->var.xres, lines); 912 } 913 914 return result; 915 } 916 917 static void ufx_ops_copyarea(struct fb_info *info, 918 const struct fb_copyarea *area) 919 { 920 921 struct ufx_data *dev = info->par; 922 923 sys_copyarea(info, area); 924 925 ufx_handle_damage(dev, area->dx, area->dy, 926 area->width, area->height); 927 } 928 929 static void ufx_ops_imageblit(struct fb_info *info, 930 const struct fb_image *image) 931 { 932 struct ufx_data *dev = info->par; 933 934 sys_imageblit(info, image); 935 936 ufx_handle_damage(dev, image->dx, image->dy, 937 image->width, image->height); 938 } 939 940 static void ufx_ops_fillrect(struct fb_info *info, 941 const struct fb_fillrect *rect) 942 { 943 struct ufx_data *dev = info->par; 944 945 sys_fillrect(info, rect); 946 947 ufx_handle_damage(dev, rect->dx, rect->dy, rect->width, 948 rect->height); 949 } 950 951 /* NOTE: fb_defio.c is holding info->fbdefio.mutex 952 * Touching ANY framebuffer memory that triggers a page fault 953 * in fb_defio will cause a deadlock, when it also tries to 954 * grab the same mutex. */ 955 static void ufx_dpy_deferred_io(struct fb_info *info, 956 struct list_head *pagelist) 957 { 958 struct page *cur; 959 struct fb_deferred_io *fbdefio = info->fbdefio; 960 struct ufx_data *dev = info->par; 961 962 if (!fb_defio) 963 return; 964 965 if (!atomic_read(&dev->usb_active)) 966 return; 967 968 /* walk the written page list and render each to device */ 969 list_for_each_entry(cur, &fbdefio->pagelist, lru) { 970 /* create a rectangle of full screen width that encloses the 971 * entire dirty framebuffer page */ 972 const int x = 0; 973 const int width = dev->info->var.xres; 974 const int y = (cur->index << PAGE_SHIFT) / (width * 2); 975 int height = (PAGE_SIZE / (width * 2)) + 1; 976 height = min(height, (int)(dev->info->var.yres - y)); 977 978 BUG_ON(y >= dev->info->var.yres); 979 BUG_ON((y + height) > dev->info->var.yres); 980 981 ufx_handle_damage(dev, x, y, width, height); 982 } 983 } 984 985 static int ufx_ops_ioctl(struct fb_info *info, unsigned int cmd, 986 unsigned long arg) 987 { 988 struct ufx_data *dev = info->par; 989 struct dloarea *area = NULL; 990 991 if (!atomic_read(&dev->usb_active)) 992 return 0; 993 994 /* TODO: Update X server to get this from sysfs instead */ 995 if (cmd == UFX_IOCTL_RETURN_EDID) { 996 u8 __user *edid = (u8 __user *)arg; 997 if (copy_to_user(edid, dev->edid, dev->edid_size)) 998 return -EFAULT; 999 return 0; 1000 } 1001 1002 /* TODO: Help propose a standard fb.h ioctl to report mmap damage */ 1003 if (cmd == UFX_IOCTL_REPORT_DAMAGE) { 1004 /* If we have a damage-aware client, turn fb_defio "off" 1005 * To avoid perf imact of unnecessary page fault handling. 1006 * Done by resetting the delay for this fb_info to a very 1007 * long period. Pages will become writable and stay that way. 1008 * Reset to normal value when all clients have closed this fb. 1009 */ 1010 if (info->fbdefio) 1011 info->fbdefio->delay = UFX_DEFIO_WRITE_DISABLE; 1012 1013 area = (struct dloarea *)arg; 1014 1015 if (area->x < 0) 1016 area->x = 0; 1017 1018 if (area->x > info->var.xres) 1019 area->x = info->var.xres; 1020 1021 if (area->y < 0) 1022 area->y = 0; 1023 1024 if (area->y > info->var.yres) 1025 area->y = info->var.yres; 1026 1027 ufx_handle_damage(dev, area->x, area->y, area->w, area->h); 1028 } 1029 1030 return 0; 1031 } 1032 1033 /* taken from vesafb */ 1034 static int 1035 ufx_ops_setcolreg(unsigned regno, unsigned red, unsigned green, 1036 unsigned blue, unsigned transp, struct fb_info *info) 1037 { 1038 int err = 0; 1039 1040 if (regno >= info->cmap.len) 1041 return 1; 1042 1043 if (regno < 16) { 1044 if (info->var.red.offset == 10) { 1045 /* 1:5:5:5 */ 1046 ((u32 *) (info->pseudo_palette))[regno] = 1047 ((red & 0xf800) >> 1) | 1048 ((green & 0xf800) >> 6) | ((blue & 0xf800) >> 11); 1049 } else { 1050 /* 0:5:6:5 */ 1051 ((u32 *) (info->pseudo_palette))[regno] = 1052 ((red & 0xf800)) | 1053 ((green & 0xfc00) >> 5) | ((blue & 0xf800) >> 11); 1054 } 1055 } 1056 1057 return err; 1058 } 1059 1060 /* It's common for several clients to have framebuffer open simultaneously. 1061 * e.g. both fbcon and X. Makes things interesting. 1062 * Assumes caller is holding info->lock (for open and release at least) */ 1063 static int ufx_ops_open(struct fb_info *info, int user) 1064 { 1065 struct ufx_data *dev = info->par; 1066 1067 /* fbcon aggressively connects to first framebuffer it finds, 1068 * preventing other clients (X) from working properly. Usually 1069 * not what the user wants. Fail by default with option to enable. */ 1070 if (user == 0 && !console) 1071 return -EBUSY; 1072 1073 /* If the USB device is gone, we don't accept new opens */ 1074 if (dev->virtualized) 1075 return -ENODEV; 1076 1077 dev->fb_count++; 1078 1079 kref_get(&dev->kref); 1080 1081 if (fb_defio && (info->fbdefio == NULL)) { 1082 /* enable defio at last moment if not disabled by client */ 1083 1084 struct fb_deferred_io *fbdefio; 1085 1086 fbdefio = kzalloc(sizeof(*fbdefio), GFP_KERNEL); 1087 if (fbdefio) { 1088 fbdefio->delay = UFX_DEFIO_WRITE_DELAY; 1089 fbdefio->deferred_io = ufx_dpy_deferred_io; 1090 } 1091 1092 info->fbdefio = fbdefio; 1093 fb_deferred_io_init(info); 1094 } 1095 1096 pr_debug("open /dev/fb%d user=%d fb_info=%p count=%d", 1097 info->node, user, info, dev->fb_count); 1098 1099 return 0; 1100 } 1101 1102 /* 1103 * Called when all client interfaces to start transactions have been disabled, 1104 * and all references to our device instance (ufx_data) are released. 1105 * Every transaction must have a reference, so we know are fully spun down 1106 */ 1107 static void ufx_free(struct kref *kref) 1108 { 1109 struct ufx_data *dev = container_of(kref, struct ufx_data, kref); 1110 1111 /* this function will wait for all in-flight urbs to complete */ 1112 if (dev->urbs.count > 0) 1113 ufx_free_urb_list(dev); 1114 1115 pr_debug("freeing ufx_data %p", dev); 1116 1117 kfree(dev); 1118 } 1119 1120 static void ufx_release_urb_work(struct work_struct *work) 1121 { 1122 struct urb_node *unode = container_of(work, struct urb_node, 1123 release_urb_work.work); 1124 1125 up(&unode->dev->urbs.limit_sem); 1126 } 1127 1128 static void ufx_free_framebuffer_work(struct work_struct *work) 1129 { 1130 struct ufx_data *dev = container_of(work, struct ufx_data, 1131 free_framebuffer_work.work); 1132 struct fb_info *info = dev->info; 1133 int node = info->node; 1134 1135 unregister_framebuffer(info); 1136 1137 if (info->cmap.len != 0) 1138 fb_dealloc_cmap(&info->cmap); 1139 if (info->monspecs.modedb) 1140 fb_destroy_modedb(info->monspecs.modedb); 1141 vfree(info->screen_base); 1142 1143 fb_destroy_modelist(&info->modelist); 1144 1145 dev->info = NULL; 1146 1147 /* Assume info structure is freed after this point */ 1148 framebuffer_release(info); 1149 1150 pr_debug("fb_info for /dev/fb%d has been freed", node); 1151 1152 /* ref taken in probe() as part of registering framebfufer */ 1153 kref_put(&dev->kref, ufx_free); 1154 } 1155 1156 /* 1157 * Assumes caller is holding info->lock mutex (for open and release at least) 1158 */ 1159 static int ufx_ops_release(struct fb_info *info, int user) 1160 { 1161 struct ufx_data *dev = info->par; 1162 1163 dev->fb_count--; 1164 1165 /* We can't free fb_info here - fbmem will touch it when we return */ 1166 if (dev->virtualized && (dev->fb_count == 0)) 1167 schedule_delayed_work(&dev->free_framebuffer_work, HZ); 1168 1169 if ((dev->fb_count == 0) && (info->fbdefio)) { 1170 fb_deferred_io_cleanup(info); 1171 kfree(info->fbdefio); 1172 info->fbdefio = NULL; 1173 } 1174 1175 pr_debug("released /dev/fb%d user=%d count=%d", 1176 info->node, user, dev->fb_count); 1177 1178 kref_put(&dev->kref, ufx_free); 1179 1180 return 0; 1181 } 1182 1183 /* Check whether a video mode is supported by the chip 1184 * We start from monitor's modes, so don't need to filter that here */ 1185 static int ufx_is_valid_mode(struct fb_videomode *mode, 1186 struct fb_info *info) 1187 { 1188 if ((mode->xres * mode->yres) > (2048 * 1152)) { 1189 pr_debug("%dx%d too many pixels", 1190 mode->xres, mode->yres); 1191 return 0; 1192 } 1193 1194 if (mode->pixclock < 5000) { 1195 pr_debug("%dx%d %dps pixel clock too fast", 1196 mode->xres, mode->yres, mode->pixclock); 1197 return 0; 1198 } 1199 1200 pr_debug("%dx%d (pixclk %dps %dMHz) valid mode", mode->xres, mode->yres, 1201 mode->pixclock, (1000000 / mode->pixclock)); 1202 return 1; 1203 } 1204 1205 static void ufx_var_color_format(struct fb_var_screeninfo *var) 1206 { 1207 const struct fb_bitfield red = { 11, 5, 0 }; 1208 const struct fb_bitfield green = { 5, 6, 0 }; 1209 const struct fb_bitfield blue = { 0, 5, 0 }; 1210 1211 var->bits_per_pixel = 16; 1212 var->red = red; 1213 var->green = green; 1214 var->blue = blue; 1215 } 1216 1217 static int ufx_ops_check_var(struct fb_var_screeninfo *var, 1218 struct fb_info *info) 1219 { 1220 struct fb_videomode mode; 1221 1222 /* TODO: support dynamically changing framebuffer size */ 1223 if ((var->xres * var->yres * 2) > info->fix.smem_len) 1224 return -EINVAL; 1225 1226 /* set device-specific elements of var unrelated to mode */ 1227 ufx_var_color_format(var); 1228 1229 fb_var_to_videomode(&mode, var); 1230 1231 if (!ufx_is_valid_mode(&mode, info)) 1232 return -EINVAL; 1233 1234 return 0; 1235 } 1236 1237 static int ufx_ops_set_par(struct fb_info *info) 1238 { 1239 struct ufx_data *dev = info->par; 1240 int result; 1241 u16 *pix_framebuffer; 1242 int i; 1243 1244 pr_debug("set_par mode %dx%d", info->var.xres, info->var.yres); 1245 result = ufx_set_vid_mode(dev, &info->var); 1246 1247 if ((result == 0) && (dev->fb_count == 0)) { 1248 /* paint greenscreen */ 1249 pix_framebuffer = (u16 *) info->screen_base; 1250 for (i = 0; i < info->fix.smem_len / 2; i++) 1251 pix_framebuffer[i] = 0x37e6; 1252 1253 ufx_handle_damage(dev, 0, 0, info->var.xres, info->var.yres); 1254 } 1255 1256 /* re-enable defio if previously disabled by damage tracking */ 1257 if (info->fbdefio) 1258 info->fbdefio->delay = UFX_DEFIO_WRITE_DELAY; 1259 1260 return result; 1261 } 1262 1263 /* In order to come back from full DPMS off, we need to set the mode again */ 1264 static int ufx_ops_blank(int blank_mode, struct fb_info *info) 1265 { 1266 struct ufx_data *dev = info->par; 1267 ufx_set_vid_mode(dev, &info->var); 1268 return 0; 1269 } 1270 1271 static const struct fb_ops ufx_ops = { 1272 .owner = THIS_MODULE, 1273 .fb_read = fb_sys_read, 1274 .fb_write = ufx_ops_write, 1275 .fb_setcolreg = ufx_ops_setcolreg, 1276 .fb_fillrect = ufx_ops_fillrect, 1277 .fb_copyarea = ufx_ops_copyarea, 1278 .fb_imageblit = ufx_ops_imageblit, 1279 .fb_mmap = ufx_ops_mmap, 1280 .fb_ioctl = ufx_ops_ioctl, 1281 .fb_open = ufx_ops_open, 1282 .fb_release = ufx_ops_release, 1283 .fb_blank = ufx_ops_blank, 1284 .fb_check_var = ufx_ops_check_var, 1285 .fb_set_par = ufx_ops_set_par, 1286 }; 1287 1288 /* Assumes &info->lock held by caller 1289 * Assumes no active clients have framebuffer open */ 1290 static int ufx_realloc_framebuffer(struct ufx_data *dev, struct fb_info *info) 1291 { 1292 int old_len = info->fix.smem_len; 1293 int new_len; 1294 unsigned char *old_fb = info->screen_base; 1295 unsigned char *new_fb; 1296 1297 pr_debug("Reallocating framebuffer. Addresses will change!"); 1298 1299 new_len = info->fix.line_length * info->var.yres; 1300 1301 if (PAGE_ALIGN(new_len) > old_len) { 1302 /* 1303 * Alloc system memory for virtual framebuffer 1304 */ 1305 new_fb = vmalloc(new_len); 1306 if (!new_fb) 1307 return -ENOMEM; 1308 1309 if (info->screen_base) { 1310 memcpy(new_fb, old_fb, old_len); 1311 vfree(info->screen_base); 1312 } 1313 1314 info->screen_base = new_fb; 1315 info->fix.smem_len = PAGE_ALIGN(new_len); 1316 info->fix.smem_start = (unsigned long) new_fb; 1317 info->flags = smscufx_info_flags; 1318 } 1319 return 0; 1320 } 1321 1322 /* sets up I2C Controller for 100 Kbps, std. speed, 7-bit addr, master, 1323 * restart enabled, but no start byte, enable controller */ 1324 static int ufx_i2c_init(struct ufx_data *dev) 1325 { 1326 u32 tmp; 1327 1328 /* disable the controller before it can be reprogrammed */ 1329 int status = ufx_reg_write(dev, 0x106C, 0x00); 1330 check_warn_return(status, "failed to disable I2C"); 1331 1332 /* Setup the clock count registers 1333 * (12+1) = 13 clks @ 2.5 MHz = 5.2 uS */ 1334 status = ufx_reg_write(dev, 0x1018, 12); 1335 check_warn_return(status, "error writing 0x1018"); 1336 1337 /* (6+8) = 14 clks @ 2.5 MHz = 5.6 uS */ 1338 status = ufx_reg_write(dev, 0x1014, 6); 1339 check_warn_return(status, "error writing 0x1014"); 1340 1341 status = ufx_reg_read(dev, 0x1000, &tmp); 1342 check_warn_return(status, "error reading 0x1000"); 1343 1344 /* set speed to std mode */ 1345 tmp &= ~(0x06); 1346 tmp |= 0x02; 1347 1348 /* 7-bit (not 10-bit) addressing */ 1349 tmp &= ~(0x10); 1350 1351 /* enable restart conditions and master mode */ 1352 tmp |= 0x21; 1353 1354 status = ufx_reg_write(dev, 0x1000, tmp); 1355 check_warn_return(status, "error writing 0x1000"); 1356 1357 /* Set normal tx using target address 0 */ 1358 status = ufx_reg_clear_and_set_bits(dev, 0x1004, 0xC00, 0x000); 1359 check_warn_return(status, "error setting TX mode bits in 0x1004"); 1360 1361 /* Enable the controller */ 1362 status = ufx_reg_write(dev, 0x106C, 0x01); 1363 check_warn_return(status, "failed to enable I2C"); 1364 1365 return 0; 1366 } 1367 1368 /* sets the I2C port mux and target address */ 1369 static int ufx_i2c_configure(struct ufx_data *dev) 1370 { 1371 int status = ufx_reg_write(dev, 0x106C, 0x00); 1372 check_warn_return(status, "failed to disable I2C"); 1373 1374 status = ufx_reg_write(dev, 0x3010, 0x00000000); 1375 check_warn_return(status, "failed to write 0x3010"); 1376 1377 /* A0h is std for any EDID, right shifted by one */ 1378 status = ufx_reg_clear_and_set_bits(dev, 0x1004, 0x3FF, (0xA0 >> 1)); 1379 check_warn_return(status, "failed to set TAR bits in 0x1004"); 1380 1381 status = ufx_reg_write(dev, 0x106C, 0x01); 1382 check_warn_return(status, "failed to enable I2C"); 1383 1384 return 0; 1385 } 1386 1387 /* wait for BUSY to clear, with a timeout of 50ms with 10ms sleeps. if no 1388 * monitor is connected, there is no error except for timeout */ 1389 static int ufx_i2c_wait_busy(struct ufx_data *dev) 1390 { 1391 u32 tmp; 1392 int i, status; 1393 1394 for (i = 0; i < 15; i++) { 1395 status = ufx_reg_read(dev, 0x1100, &tmp); 1396 check_warn_return(status, "0x1100 read failed"); 1397 1398 /* if BUSY is clear, check for error */ 1399 if ((tmp & 0x80000000) == 0) { 1400 if (tmp & 0x20000000) { 1401 pr_warn("I2C read failed, 0x1100=0x%08x", tmp); 1402 return -EIO; 1403 } 1404 1405 return 0; 1406 } 1407 1408 /* perform the first 10 retries without delay */ 1409 if (i >= 10) 1410 msleep(10); 1411 } 1412 1413 pr_warn("I2C access timed out, resetting I2C hardware"); 1414 status = ufx_reg_write(dev, 0x1100, 0x40000000); 1415 check_warn_return(status, "0x1100 write failed"); 1416 1417 return -ETIMEDOUT; 1418 } 1419 1420 /* reads a 128-byte EDID block from the currently selected port and TAR */ 1421 static int ufx_read_edid(struct ufx_data *dev, u8 *edid, int edid_len) 1422 { 1423 int i, j, status; 1424 u32 *edid_u32 = (u32 *)edid; 1425 1426 BUG_ON(edid_len != EDID_LENGTH); 1427 1428 status = ufx_i2c_configure(dev); 1429 if (status < 0) { 1430 pr_err("ufx_i2c_configure failed"); 1431 return status; 1432 } 1433 1434 memset(edid, 0xff, EDID_LENGTH); 1435 1436 /* Read the 128-byte EDID as 2 bursts of 64 bytes */ 1437 for (i = 0; i < 2; i++) { 1438 u32 temp = 0x28070000 | (63 << 20) | (((u32)(i * 64)) << 8); 1439 status = ufx_reg_write(dev, 0x1100, temp); 1440 check_warn_return(status, "Failed to write 0x1100"); 1441 1442 temp |= 0x80000000; 1443 status = ufx_reg_write(dev, 0x1100, temp); 1444 check_warn_return(status, "Failed to write 0x1100"); 1445 1446 status = ufx_i2c_wait_busy(dev); 1447 check_warn_return(status, "Timeout waiting for I2C BUSY to clear"); 1448 1449 for (j = 0; j < 16; j++) { 1450 u32 data_reg_addr = 0x1110 + (j * 4); 1451 status = ufx_reg_read(dev, data_reg_addr, edid_u32++); 1452 check_warn_return(status, "Error reading i2c data"); 1453 } 1454 } 1455 1456 /* all FF's in the first 16 bytes indicates nothing is connected */ 1457 for (i = 0; i < 16; i++) { 1458 if (edid[i] != 0xFF) { 1459 pr_debug("edid data read successfully"); 1460 return EDID_LENGTH; 1461 } 1462 } 1463 1464 pr_warn("edid data contains all 0xff"); 1465 return -ETIMEDOUT; 1466 } 1467 1468 /* 1) use sw default 1469 * 2) Parse into various fb_info structs 1470 * 3) Allocate virtual framebuffer memory to back highest res mode 1471 * 1472 * Parses EDID into three places used by various parts of fbdev: 1473 * fb_var_screeninfo contains the timing of the monitor's preferred mode 1474 * fb_info.monspecs is full parsed EDID info, including monspecs.modedb 1475 * fb_info.modelist is a linked list of all monitor & VESA modes which work 1476 * 1477 * If EDID is not readable/valid, then modelist is all VESA modes, 1478 * monspecs is NULL, and fb_var_screeninfo is set to safe VESA mode 1479 * Returns 0 if successful */ 1480 static int ufx_setup_modes(struct ufx_data *dev, struct fb_info *info, 1481 char *default_edid, size_t default_edid_size) 1482 { 1483 const struct fb_videomode *default_vmode = NULL; 1484 u8 *edid; 1485 int i, result = 0, tries = 3; 1486 1487 if (info->dev) /* only use mutex if info has been registered */ 1488 mutex_lock(&info->lock); 1489 1490 edid = kmalloc(EDID_LENGTH, GFP_KERNEL); 1491 if (!edid) { 1492 result = -ENOMEM; 1493 goto error; 1494 } 1495 1496 fb_destroy_modelist(&info->modelist); 1497 memset(&info->monspecs, 0, sizeof(info->monspecs)); 1498 1499 /* Try to (re)read EDID from hardware first 1500 * EDID data may return, but not parse as valid 1501 * Try again a few times, in case of e.g. analog cable noise */ 1502 while (tries--) { 1503 i = ufx_read_edid(dev, edid, EDID_LENGTH); 1504 1505 if (i >= EDID_LENGTH) 1506 fb_edid_to_monspecs(edid, &info->monspecs); 1507 1508 if (info->monspecs.modedb_len > 0) { 1509 dev->edid = edid; 1510 dev->edid_size = i; 1511 break; 1512 } 1513 } 1514 1515 /* If that fails, use a previously returned EDID if available */ 1516 if (info->monspecs.modedb_len == 0) { 1517 pr_err("Unable to get valid EDID from device/display\n"); 1518 1519 if (dev->edid) { 1520 fb_edid_to_monspecs(dev->edid, &info->monspecs); 1521 if (info->monspecs.modedb_len > 0) 1522 pr_err("Using previously queried EDID\n"); 1523 } 1524 } 1525 1526 /* If that fails, use the default EDID we were handed */ 1527 if (info->monspecs.modedb_len == 0) { 1528 if (default_edid_size >= EDID_LENGTH) { 1529 fb_edid_to_monspecs(default_edid, &info->monspecs); 1530 if (info->monspecs.modedb_len > 0) { 1531 memcpy(edid, default_edid, default_edid_size); 1532 dev->edid = edid; 1533 dev->edid_size = default_edid_size; 1534 pr_err("Using default/backup EDID\n"); 1535 } 1536 } 1537 } 1538 1539 /* If we've got modes, let's pick a best default mode */ 1540 if (info->monspecs.modedb_len > 0) { 1541 1542 for (i = 0; i < info->monspecs.modedb_len; i++) { 1543 if (ufx_is_valid_mode(&info->monspecs.modedb[i], info)) 1544 fb_add_videomode(&info->monspecs.modedb[i], 1545 &info->modelist); 1546 else /* if we've removed top/best mode */ 1547 info->monspecs.misc &= ~FB_MISC_1ST_DETAIL; 1548 } 1549 1550 default_vmode = fb_find_best_display(&info->monspecs, 1551 &info->modelist); 1552 } 1553 1554 /* If everything else has failed, fall back to safe default mode */ 1555 if (default_vmode == NULL) { 1556 1557 struct fb_videomode fb_vmode = {0}; 1558 1559 /* Add the standard VESA modes to our modelist 1560 * Since we don't have EDID, there may be modes that 1561 * overspec monitor and/or are incorrect aspect ratio, etc. 1562 * But at least the user has a chance to choose 1563 */ 1564 for (i = 0; i < VESA_MODEDB_SIZE; i++) { 1565 if (ufx_is_valid_mode((struct fb_videomode *) 1566 &vesa_modes[i], info)) 1567 fb_add_videomode(&vesa_modes[i], 1568 &info->modelist); 1569 } 1570 1571 /* default to resolution safe for projectors 1572 * (since they are most common case without EDID) 1573 */ 1574 fb_vmode.xres = 800; 1575 fb_vmode.yres = 600; 1576 fb_vmode.refresh = 60; 1577 default_vmode = fb_find_nearest_mode(&fb_vmode, 1578 &info->modelist); 1579 } 1580 1581 /* If we have good mode and no active clients */ 1582 if ((default_vmode != NULL) && (dev->fb_count == 0)) { 1583 1584 fb_videomode_to_var(&info->var, default_vmode); 1585 ufx_var_color_format(&info->var); 1586 1587 /* with mode size info, we can now alloc our framebuffer */ 1588 memcpy(&info->fix, &ufx_fix, sizeof(ufx_fix)); 1589 info->fix.line_length = info->var.xres * 1590 (info->var.bits_per_pixel / 8); 1591 1592 result = ufx_realloc_framebuffer(dev, info); 1593 1594 } else 1595 result = -EINVAL; 1596 1597 error: 1598 if (edid && (dev->edid != edid)) 1599 kfree(edid); 1600 1601 if (info->dev) 1602 mutex_unlock(&info->lock); 1603 1604 return result; 1605 } 1606 1607 static int ufx_usb_probe(struct usb_interface *interface, 1608 const struct usb_device_id *id) 1609 { 1610 struct usb_device *usbdev; 1611 struct ufx_data *dev; 1612 struct fb_info *info; 1613 int retval; 1614 u32 id_rev, fpga_rev; 1615 1616 /* usb initialization */ 1617 usbdev = interface_to_usbdev(interface); 1618 BUG_ON(!usbdev); 1619 1620 dev = kzalloc(sizeof(*dev), GFP_KERNEL); 1621 if (dev == NULL) { 1622 dev_err(&usbdev->dev, "ufx_usb_probe: failed alloc of dev struct\n"); 1623 return -ENOMEM; 1624 } 1625 1626 /* we need to wait for both usb and fbdev to spin down on disconnect */ 1627 kref_init(&dev->kref); /* matching kref_put in usb .disconnect fn */ 1628 kref_get(&dev->kref); /* matching kref_put in free_framebuffer_work */ 1629 1630 dev->udev = usbdev; 1631 dev->gdev = &usbdev->dev; /* our generic struct device * */ 1632 usb_set_intfdata(interface, dev); 1633 1634 dev_dbg(dev->gdev, "%s %s - serial #%s\n", 1635 usbdev->manufacturer, usbdev->product, usbdev->serial); 1636 dev_dbg(dev->gdev, "vid_%04x&pid_%04x&rev_%04x driver's ufx_data struct at %p\n", 1637 le16_to_cpu(usbdev->descriptor.idVendor), 1638 le16_to_cpu(usbdev->descriptor.idProduct), 1639 le16_to_cpu(usbdev->descriptor.bcdDevice), dev); 1640 dev_dbg(dev->gdev, "console enable=%d\n", console); 1641 dev_dbg(dev->gdev, "fb_defio enable=%d\n", fb_defio); 1642 1643 if (!ufx_alloc_urb_list(dev, WRITES_IN_FLIGHT, MAX_TRANSFER)) { 1644 dev_err(dev->gdev, "ufx_alloc_urb_list failed\n"); 1645 goto e_nomem; 1646 } 1647 1648 /* We don't register a new USB class. Our client interface is fbdev */ 1649 1650 /* allocates framebuffer driver structure, not framebuffer memory */ 1651 info = framebuffer_alloc(0, &usbdev->dev); 1652 if (!info) 1653 goto e_nomem; 1654 1655 dev->info = info; 1656 info->par = dev; 1657 info->pseudo_palette = dev->pseudo_palette; 1658 info->fbops = &ufx_ops; 1659 INIT_LIST_HEAD(&info->modelist); 1660 1661 retval = fb_alloc_cmap(&info->cmap, 256, 0); 1662 if (retval < 0) { 1663 dev_err(dev->gdev, "fb_alloc_cmap failed %x\n", retval); 1664 goto destroy_modedb; 1665 } 1666 1667 INIT_DELAYED_WORK(&dev->free_framebuffer_work, 1668 ufx_free_framebuffer_work); 1669 1670 retval = ufx_reg_read(dev, 0x3000, &id_rev); 1671 check_warn_goto_error(retval, "error %d reading 0x3000 register from device", retval); 1672 dev_dbg(dev->gdev, "ID_REV register value 0x%08x", id_rev); 1673 1674 retval = ufx_reg_read(dev, 0x3004, &fpga_rev); 1675 check_warn_goto_error(retval, "error %d reading 0x3004 register from device", retval); 1676 dev_dbg(dev->gdev, "FPGA_REV register value 0x%08x", fpga_rev); 1677 1678 dev_dbg(dev->gdev, "resetting device"); 1679 retval = ufx_lite_reset(dev); 1680 check_warn_goto_error(retval, "error %d resetting device", retval); 1681 1682 dev_dbg(dev->gdev, "configuring system clock"); 1683 retval = ufx_config_sys_clk(dev); 1684 check_warn_goto_error(retval, "error %d configuring system clock", retval); 1685 1686 dev_dbg(dev->gdev, "configuring DDR2 controller"); 1687 retval = ufx_config_ddr2(dev); 1688 check_warn_goto_error(retval, "error %d initialising DDR2 controller", retval); 1689 1690 dev_dbg(dev->gdev, "configuring I2C controller"); 1691 retval = ufx_i2c_init(dev); 1692 check_warn_goto_error(retval, "error %d initialising I2C controller", retval); 1693 1694 dev_dbg(dev->gdev, "selecting display mode"); 1695 retval = ufx_setup_modes(dev, info, NULL, 0); 1696 check_warn_goto_error(retval, "unable to find common mode for display and adapter"); 1697 1698 retval = ufx_reg_set_bits(dev, 0x4000, 0x00000001); 1699 check_warn_goto_error(retval, "error %d enabling graphics engine", retval); 1700 1701 /* ready to begin using device */ 1702 atomic_set(&dev->usb_active, 1); 1703 1704 dev_dbg(dev->gdev, "checking var"); 1705 retval = ufx_ops_check_var(&info->var, info); 1706 check_warn_goto_error(retval, "error %d ufx_ops_check_var", retval); 1707 1708 dev_dbg(dev->gdev, "setting par"); 1709 retval = ufx_ops_set_par(info); 1710 check_warn_goto_error(retval, "error %d ufx_ops_set_par", retval); 1711 1712 dev_dbg(dev->gdev, "registering framebuffer"); 1713 retval = register_framebuffer(info); 1714 check_warn_goto_error(retval, "error %d register_framebuffer", retval); 1715 1716 dev_info(dev->gdev, "SMSC UDX USB device /dev/fb%d attached. %dx%d resolution." 1717 " Using %dK framebuffer memory\n", info->node, 1718 info->var.xres, info->var.yres, info->fix.smem_len >> 10); 1719 1720 return 0; 1721 1722 error: 1723 fb_dealloc_cmap(&info->cmap); 1724 destroy_modedb: 1725 fb_destroy_modedb(info->monspecs.modedb); 1726 vfree(info->screen_base); 1727 fb_destroy_modelist(&info->modelist); 1728 framebuffer_release(info); 1729 put_ref: 1730 kref_put(&dev->kref, ufx_free); /* ref for framebuffer */ 1731 kref_put(&dev->kref, ufx_free); /* last ref from kref_init */ 1732 return retval; 1733 1734 e_nomem: 1735 retval = -ENOMEM; 1736 goto put_ref; 1737 } 1738 1739 static void ufx_usb_disconnect(struct usb_interface *interface) 1740 { 1741 struct ufx_data *dev; 1742 1743 dev = usb_get_intfdata(interface); 1744 1745 pr_debug("USB disconnect starting\n"); 1746 1747 /* we virtualize until all fb clients release. Then we free */ 1748 dev->virtualized = true; 1749 1750 /* When non-active we'll update virtual framebuffer, but no new urbs */ 1751 atomic_set(&dev->usb_active, 0); 1752 1753 usb_set_intfdata(interface, NULL); 1754 1755 /* if clients still have us open, will be freed on last close */ 1756 if (dev->fb_count == 0) 1757 schedule_delayed_work(&dev->free_framebuffer_work, 0); 1758 1759 /* release reference taken by kref_init in probe() */ 1760 kref_put(&dev->kref, ufx_free); 1761 1762 /* consider ufx_data freed */ 1763 } 1764 1765 static struct usb_driver ufx_driver = { 1766 .name = "smscufx", 1767 .probe = ufx_usb_probe, 1768 .disconnect = ufx_usb_disconnect, 1769 .id_table = id_table, 1770 }; 1771 1772 module_usb_driver(ufx_driver); 1773 1774 static void ufx_urb_completion(struct urb *urb) 1775 { 1776 struct urb_node *unode = urb->context; 1777 struct ufx_data *dev = unode->dev; 1778 unsigned long flags; 1779 1780 /* sync/async unlink faults aren't errors */ 1781 if (urb->status) { 1782 if (!(urb->status == -ENOENT || 1783 urb->status == -ECONNRESET || 1784 urb->status == -ESHUTDOWN)) { 1785 pr_err("%s - nonzero write bulk status received: %d\n", 1786 __func__, urb->status); 1787 atomic_set(&dev->lost_pixels, 1); 1788 } 1789 } 1790 1791 urb->transfer_buffer_length = dev->urbs.size; /* reset to actual */ 1792 1793 spin_lock_irqsave(&dev->urbs.lock, flags); 1794 list_add_tail(&unode->entry, &dev->urbs.list); 1795 dev->urbs.available++; 1796 spin_unlock_irqrestore(&dev->urbs.lock, flags); 1797 1798 /* When using fb_defio, we deadlock if up() is called 1799 * while another is waiting. So queue to another process */ 1800 if (fb_defio) 1801 schedule_delayed_work(&unode->release_urb_work, 0); 1802 else 1803 up(&dev->urbs.limit_sem); 1804 } 1805 1806 static void ufx_free_urb_list(struct ufx_data *dev) 1807 { 1808 int count = dev->urbs.count; 1809 struct list_head *node; 1810 struct urb_node *unode; 1811 struct urb *urb; 1812 int ret; 1813 unsigned long flags; 1814 1815 pr_debug("Waiting for completes and freeing all render urbs\n"); 1816 1817 /* keep waiting and freeing, until we've got 'em all */ 1818 while (count--) { 1819 /* Getting interrupted means a leak, but ok at shutdown*/ 1820 ret = down_interruptible(&dev->urbs.limit_sem); 1821 if (ret) 1822 break; 1823 1824 spin_lock_irqsave(&dev->urbs.lock, flags); 1825 1826 node = dev->urbs.list.next; /* have reserved one with sem */ 1827 list_del_init(node); 1828 1829 spin_unlock_irqrestore(&dev->urbs.lock, flags); 1830 1831 unode = list_entry(node, struct urb_node, entry); 1832 urb = unode->urb; 1833 1834 /* Free each separately allocated piece */ 1835 usb_free_coherent(urb->dev, dev->urbs.size, 1836 urb->transfer_buffer, urb->transfer_dma); 1837 usb_free_urb(urb); 1838 kfree(node); 1839 } 1840 } 1841 1842 static int ufx_alloc_urb_list(struct ufx_data *dev, int count, size_t size) 1843 { 1844 int i = 0; 1845 struct urb *urb; 1846 struct urb_node *unode; 1847 char *buf; 1848 1849 spin_lock_init(&dev->urbs.lock); 1850 1851 dev->urbs.size = size; 1852 INIT_LIST_HEAD(&dev->urbs.list); 1853 1854 while (i < count) { 1855 unode = kzalloc(sizeof(*unode), GFP_KERNEL); 1856 if (!unode) 1857 break; 1858 unode->dev = dev; 1859 1860 INIT_DELAYED_WORK(&unode->release_urb_work, 1861 ufx_release_urb_work); 1862 1863 urb = usb_alloc_urb(0, GFP_KERNEL); 1864 if (!urb) { 1865 kfree(unode); 1866 break; 1867 } 1868 unode->urb = urb; 1869 1870 buf = usb_alloc_coherent(dev->udev, size, GFP_KERNEL, 1871 &urb->transfer_dma); 1872 if (!buf) { 1873 kfree(unode); 1874 usb_free_urb(urb); 1875 break; 1876 } 1877 1878 /* urb->transfer_buffer_length set to actual before submit */ 1879 usb_fill_bulk_urb(urb, dev->udev, usb_sndbulkpipe(dev->udev, 1), 1880 buf, size, ufx_urb_completion, unode); 1881 urb->transfer_flags |= URB_NO_TRANSFER_DMA_MAP; 1882 1883 list_add_tail(&unode->entry, &dev->urbs.list); 1884 1885 i++; 1886 } 1887 1888 sema_init(&dev->urbs.limit_sem, i); 1889 dev->urbs.count = i; 1890 dev->urbs.available = i; 1891 1892 pr_debug("allocated %d %d byte urbs\n", i, (int) size); 1893 1894 return i; 1895 } 1896 1897 static struct urb *ufx_get_urb(struct ufx_data *dev) 1898 { 1899 int ret = 0; 1900 struct list_head *entry; 1901 struct urb_node *unode; 1902 struct urb *urb = NULL; 1903 unsigned long flags; 1904 1905 /* Wait for an in-flight buffer to complete and get re-queued */ 1906 ret = down_timeout(&dev->urbs.limit_sem, GET_URB_TIMEOUT); 1907 if (ret) { 1908 atomic_set(&dev->lost_pixels, 1); 1909 pr_warn("wait for urb interrupted: %x available: %d\n", 1910 ret, dev->urbs.available); 1911 goto error; 1912 } 1913 1914 spin_lock_irqsave(&dev->urbs.lock, flags); 1915 1916 BUG_ON(list_empty(&dev->urbs.list)); /* reserved one with limit_sem */ 1917 entry = dev->urbs.list.next; 1918 list_del_init(entry); 1919 dev->urbs.available--; 1920 1921 spin_unlock_irqrestore(&dev->urbs.lock, flags); 1922 1923 unode = list_entry(entry, struct urb_node, entry); 1924 urb = unode->urb; 1925 1926 error: 1927 return urb; 1928 } 1929 1930 static int ufx_submit_urb(struct ufx_data *dev, struct urb *urb, size_t len) 1931 { 1932 int ret; 1933 1934 BUG_ON(len > dev->urbs.size); 1935 1936 urb->transfer_buffer_length = len; /* set to actual payload len */ 1937 ret = usb_submit_urb(urb, GFP_KERNEL); 1938 if (ret) { 1939 ufx_urb_completion(urb); /* because no one else will */ 1940 atomic_set(&dev->lost_pixels, 1); 1941 pr_err("usb_submit_urb error %x\n", ret); 1942 } 1943 return ret; 1944 } 1945 1946 module_param(console, bool, S_IWUSR | S_IRUSR | S_IWGRP | S_IRGRP); 1947 MODULE_PARM_DESC(console, "Allow fbcon to be used on this display"); 1948 1949 module_param(fb_defio, bool, S_IWUSR | S_IRUSR | S_IWGRP | S_IRGRP); 1950 MODULE_PARM_DESC(fb_defio, "Enable fb_defio mmap support"); 1951 1952 MODULE_AUTHOR("Steve Glendinning <steve.glendinning@shawell.net>"); 1953 MODULE_DESCRIPTION("SMSC UFX kernel framebuffer driver"); 1954 MODULE_LICENSE("GPL"); 1955