1 /* 2 * Silicon Motion SM712 frame buffer device 3 * 4 * Copyright (C) 2006 Silicon Motion Technology Corp. 5 * Authors: Ge Wang, gewang@siliconmotion.com 6 * Boyod boyod.yang@siliconmotion.com.cn 7 * 8 * Copyright (C) 2009 Lemote, Inc. 9 * Author: Wu Zhangjin, wuzhangjin@gmail.com 10 * 11 * This file is subject to the terms and conditions of the GNU General Public 12 * License. See the file COPYING in the main directory of this archive for 13 * more details. 14 */ 15 16 #define FB_ACCEL_SMI_LYNX 88 17 18 #define SCREEN_X_RES 1024 19 #define SCREEN_Y_RES 600 20 #define SCREEN_BPP 16 21 22 #define dac_reg (0x3c8) 23 #define dac_val (0x3c9) 24 25 extern void __iomem *smtc_regbaseaddress; 26 #define smtc_mmiowb(dat, reg) writeb(dat, smtc_regbaseaddress + reg) 27 28 #define smtc_mmiorb(reg) readb(smtc_regbaseaddress + reg) 29 30 #define SIZE_SR00_SR04 (0x04 - 0x00 + 1) 31 #define SIZE_SR10_SR24 (0x24 - 0x10 + 1) 32 #define SIZE_SR30_SR75 (0x75 - 0x30 + 1) 33 #define SIZE_SR80_SR93 (0x93 - 0x80 + 1) 34 #define SIZE_SRA0_SRAF (0xAF - 0xA0 + 1) 35 #define SIZE_GR00_GR08 (0x08 - 0x00 + 1) 36 #define SIZE_AR00_AR14 (0x14 - 0x00 + 1) 37 #define SIZE_CR00_CR18 (0x18 - 0x00 + 1) 38 #define SIZE_CR30_CR4D (0x4D - 0x30 + 1) 39 #define SIZE_CR90_CRA7 (0xA7 - 0x90 + 1) 40 41 static inline void smtc_crtcw(int reg, int val) 42 { 43 smtc_mmiowb(reg, 0x3d4); 44 smtc_mmiowb(val, 0x3d5); 45 } 46 47 static inline void smtc_grphw(int reg, int val) 48 { 49 smtc_mmiowb(reg, 0x3ce); 50 smtc_mmiowb(val, 0x3cf); 51 } 52 53 static inline void smtc_attrw(int reg, int val) 54 { 55 smtc_mmiorb(0x3da); 56 smtc_mmiowb(reg, 0x3c0); 57 smtc_mmiorb(0x3c1); 58 smtc_mmiowb(val, 0x3c0); 59 } 60 61 static inline void smtc_seqw(int reg, int val) 62 { 63 smtc_mmiowb(reg, 0x3c4); 64 smtc_mmiowb(val, 0x3c5); 65 } 66 67 static inline unsigned int smtc_seqr(int reg) 68 { 69 smtc_mmiowb(reg, 0x3c4); 70 return smtc_mmiorb(0x3c5); 71 } 72 73 /* The next structure holds all information relevant for a specific video mode. 74 */ 75 76 struct modeinit { 77 int mmsizex; 78 int mmsizey; 79 int bpp; 80 int hz; 81 unsigned char init_misc; 82 unsigned char init_sr00_sr04[SIZE_SR00_SR04]; 83 unsigned char init_sr10_sr24[SIZE_SR10_SR24]; 84 unsigned char init_sr30_sr75[SIZE_SR30_SR75]; 85 unsigned char init_sr80_sr93[SIZE_SR80_SR93]; 86 unsigned char init_sra0_sraf[SIZE_SRA0_SRAF]; 87 unsigned char init_gr00_gr08[SIZE_GR00_GR08]; 88 unsigned char init_ar00_ar14[SIZE_AR00_AR14]; 89 unsigned char init_cr00_cr18[SIZE_CR00_CR18]; 90 unsigned char init_cr30_cr4d[SIZE_CR30_CR4D]; 91 unsigned char init_cr90_cra7[SIZE_CR90_CRA7]; 92 }; 93 94 #ifdef __BIG_ENDIAN 95 #define pal_rgb(r, g, b, val) (((r & 0xf800) >> 8) | \ 96 ((g & 0xe000) >> 13) | \ 97 ((g & 0x1c00) << 3) | \ 98 ((b & 0xf800) >> 3)) 99 #define big_addr 0x800000 100 #define mmio_addr 0x00800000 101 #define seqw17() smtc_seqw(0x17, 0x30) 102 #define big_pixel_depth(p, d) {if (p == 24) {p = 32; d = 32; } } 103 #define big_swap(p) ((p & 0xff00ff00 >> 8) | (p & 0x00ff00ff << 8)) 104 #else 105 #define pal_rgb(r, g, b, val) val 106 #define big_addr 0 107 #define mmio_addr 0x00c00000 108 #define seqw17() do { } while (0) 109 #define big_pixel_depth(p, d) do { } while (0) 110 #define big_swap(p) p 111 #endif 112