1 /* 2 * linux/drivers/video/savagefb.c -- S3 Savage Framebuffer Driver 3 * 4 * Copyright (c) 2001-2002 Denis Oliver Kropp <dok@directfb.org> 5 * Sven Neumann <neo@directfb.org> 6 * 7 * 8 * Card specific code is based on XFree86's savage driver. 9 * Framebuffer framework code is based on code of cyber2000fb and tdfxfb. 10 * 11 * This file is subject to the terms and conditions of the GNU General 12 * Public License. See the file COPYING in the main directory of this 13 * archive for more details. 14 * 15 * 0.4.0 (neo) 16 * - hardware accelerated clear and move 17 * 18 * 0.3.2 (dok) 19 * - wait for vertical retrace before writing to cr67 20 * at the beginning of savagefb_set_par 21 * - use synchronization registers cr23 and cr26 22 * 23 * 0.3.1 (dok) 24 * - reset 3D engine 25 * - don't return alpha bits for 32bit format 26 * 27 * 0.3.0 (dok) 28 * - added WaitIdle functions for all Savage types 29 * - do WaitIdle before mode switching 30 * - code cleanup 31 * 32 * 0.2.0 (dok) 33 * - first working version 34 * 35 * 36 * TODO 37 * - clock validations in decode_var 38 * 39 * BUGS 40 * - white margin on bootup 41 * 42 */ 43 44 #include <linux/module.h> 45 #include <linux/kernel.h> 46 #include <linux/errno.h> 47 #include <linux/string.h> 48 #include <linux/mm.h> 49 #include <linux/slab.h> 50 #include <linux/delay.h> 51 #include <linux/fb.h> 52 #include <linux/pci.h> 53 #include <linux/init.h> 54 #include <linux/console.h> 55 56 #include <asm/io.h> 57 #include <asm/irq.h> 58 #include <asm/pgtable.h> 59 60 #include "savagefb.h" 61 62 63 #define SAVAGEFB_VERSION "0.4.0_2.6" 64 65 /* --------------------------------------------------------------------- */ 66 67 68 static char *mode_option = NULL; 69 70 #ifdef MODULE 71 72 MODULE_AUTHOR("(c) 2001-2002 Denis Oliver Kropp <dok@directfb.org>"); 73 MODULE_LICENSE("GPL"); 74 MODULE_DESCRIPTION("FBDev driver for S3 Savage PCI/AGP Chips"); 75 76 #endif 77 78 79 /* --------------------------------------------------------------------- */ 80 81 static void vgaHWSeqReset(struct savagefb_par *par, int start) 82 { 83 if (start) 84 VGAwSEQ(0x00, 0x01, par); /* Synchronous Reset */ 85 else 86 VGAwSEQ(0x00, 0x03, par); /* End Reset */ 87 } 88 89 static void vgaHWProtect(struct savagefb_par *par, int on) 90 { 91 unsigned char tmp; 92 93 if (on) { 94 /* 95 * Turn off screen and disable sequencer. 96 */ 97 tmp = VGArSEQ(0x01, par); 98 99 vgaHWSeqReset(par, 1); /* start synchronous reset */ 100 VGAwSEQ(0x01, tmp | 0x20, par);/* disable the display */ 101 102 VGAenablePalette(par); 103 } else { 104 /* 105 * Reenable sequencer, then turn on screen. 106 */ 107 108 tmp = VGArSEQ(0x01, par); 109 110 VGAwSEQ(0x01, tmp & ~0x20, par);/* reenable display */ 111 vgaHWSeqReset(par, 0); /* clear synchronous reset */ 112 113 VGAdisablePalette(par); 114 } 115 } 116 117 static void vgaHWRestore(struct savagefb_par *par, struct savage_reg *reg) 118 { 119 int i; 120 121 VGAwMISC(reg->MiscOutReg, par); 122 123 for (i = 1; i < 5; i++) 124 VGAwSEQ(i, reg->Sequencer[i], par); 125 126 /* Ensure CRTC registers 0-7 are unlocked by clearing bit 7 or 127 CRTC[17] */ 128 VGAwCR(17, reg->CRTC[17] & ~0x80, par); 129 130 for (i = 0; i < 25; i++) 131 VGAwCR(i, reg->CRTC[i], par); 132 133 for (i = 0; i < 9; i++) 134 VGAwGR(i, reg->Graphics[i], par); 135 136 VGAenablePalette(par); 137 138 for (i = 0; i < 21; i++) 139 VGAwATTR(i, reg->Attribute[i], par); 140 141 VGAdisablePalette(par); 142 } 143 144 static void vgaHWInit(struct fb_var_screeninfo *var, 145 struct savagefb_par *par, 146 struct xtimings *timings, 147 struct savage_reg *reg) 148 { 149 reg->MiscOutReg = 0x23; 150 151 if (!(timings->sync & FB_SYNC_HOR_HIGH_ACT)) 152 reg->MiscOutReg |= 0x40; 153 154 if (!(timings->sync & FB_SYNC_VERT_HIGH_ACT)) 155 reg->MiscOutReg |= 0x80; 156 157 /* 158 * Time Sequencer 159 */ 160 reg->Sequencer[0x00] = 0x00; 161 reg->Sequencer[0x01] = 0x01; 162 reg->Sequencer[0x02] = 0x0F; 163 reg->Sequencer[0x03] = 0x00; /* Font select */ 164 reg->Sequencer[0x04] = 0x0E; /* Misc */ 165 166 /* 167 * CRTC Controller 168 */ 169 reg->CRTC[0x00] = (timings->HTotal >> 3) - 5; 170 reg->CRTC[0x01] = (timings->HDisplay >> 3) - 1; 171 reg->CRTC[0x02] = (timings->HSyncStart >> 3) - 1; 172 reg->CRTC[0x03] = (((timings->HSyncEnd >> 3) - 1) & 0x1f) | 0x80; 173 reg->CRTC[0x04] = (timings->HSyncStart >> 3); 174 reg->CRTC[0x05] = ((((timings->HSyncEnd >> 3) - 1) & 0x20) << 2) | 175 (((timings->HSyncEnd >> 3)) & 0x1f); 176 reg->CRTC[0x06] = (timings->VTotal - 2) & 0xFF; 177 reg->CRTC[0x07] = (((timings->VTotal - 2) & 0x100) >> 8) | 178 (((timings->VDisplay - 1) & 0x100) >> 7) | 179 ((timings->VSyncStart & 0x100) >> 6) | 180 (((timings->VSyncStart - 1) & 0x100) >> 5) | 181 0x10 | 182 (((timings->VTotal - 2) & 0x200) >> 4) | 183 (((timings->VDisplay - 1) & 0x200) >> 3) | 184 ((timings->VSyncStart & 0x200) >> 2); 185 reg->CRTC[0x08] = 0x00; 186 reg->CRTC[0x09] = (((timings->VSyncStart - 1) & 0x200) >> 4) | 0x40; 187 188 if (timings->dblscan) 189 reg->CRTC[0x09] |= 0x80; 190 191 reg->CRTC[0x0a] = 0x00; 192 reg->CRTC[0x0b] = 0x00; 193 reg->CRTC[0x0c] = 0x00; 194 reg->CRTC[0x0d] = 0x00; 195 reg->CRTC[0x0e] = 0x00; 196 reg->CRTC[0x0f] = 0x00; 197 reg->CRTC[0x10] = timings->VSyncStart & 0xff; 198 reg->CRTC[0x11] = (timings->VSyncEnd & 0x0f) | 0x20; 199 reg->CRTC[0x12] = (timings->VDisplay - 1) & 0xff; 200 reg->CRTC[0x13] = var->xres_virtual >> 4; 201 reg->CRTC[0x14] = 0x00; 202 reg->CRTC[0x15] = (timings->VSyncStart - 1) & 0xff; 203 reg->CRTC[0x16] = (timings->VSyncEnd - 1) & 0xff; 204 reg->CRTC[0x17] = 0xc3; 205 reg->CRTC[0x18] = 0xff; 206 207 /* 208 * are these unnecessary? 209 * vgaHWHBlankKGA(mode, regp, 0, KGA_FIX_OVERSCAN|KGA_ENABLE_ON_ZERO); 210 * vgaHWVBlankKGA(mode, regp, 0, KGA_FIX_OVERSCAN|KGA_ENABLE_ON_ZERO); 211 */ 212 213 /* 214 * Graphics Display Controller 215 */ 216 reg->Graphics[0x00] = 0x00; 217 reg->Graphics[0x01] = 0x00; 218 reg->Graphics[0x02] = 0x00; 219 reg->Graphics[0x03] = 0x00; 220 reg->Graphics[0x04] = 0x00; 221 reg->Graphics[0x05] = 0x40; 222 reg->Graphics[0x06] = 0x05; /* only map 64k VGA memory !!!! */ 223 reg->Graphics[0x07] = 0x0F; 224 reg->Graphics[0x08] = 0xFF; 225 226 227 reg->Attribute[0x00] = 0x00; /* standard colormap translation */ 228 reg->Attribute[0x01] = 0x01; 229 reg->Attribute[0x02] = 0x02; 230 reg->Attribute[0x03] = 0x03; 231 reg->Attribute[0x04] = 0x04; 232 reg->Attribute[0x05] = 0x05; 233 reg->Attribute[0x06] = 0x06; 234 reg->Attribute[0x07] = 0x07; 235 reg->Attribute[0x08] = 0x08; 236 reg->Attribute[0x09] = 0x09; 237 reg->Attribute[0x0a] = 0x0A; 238 reg->Attribute[0x0b] = 0x0B; 239 reg->Attribute[0x0c] = 0x0C; 240 reg->Attribute[0x0d] = 0x0D; 241 reg->Attribute[0x0e] = 0x0E; 242 reg->Attribute[0x0f] = 0x0F; 243 reg->Attribute[0x10] = 0x41; 244 reg->Attribute[0x11] = 0xFF; 245 reg->Attribute[0x12] = 0x0F; 246 reg->Attribute[0x13] = 0x00; 247 reg->Attribute[0x14] = 0x00; 248 } 249 250 /* -------------------- Hardware specific routines ------------------------- */ 251 252 /* 253 * Hardware Acceleration for SavageFB 254 */ 255 256 /* Wait for fifo space */ 257 static void 258 savage3D_waitfifo(struct savagefb_par *par, int space) 259 { 260 int slots = MAXFIFO - space; 261 262 while ((savage_in32(0x48C00, par) & 0x0000ffff) > slots); 263 } 264 265 static void 266 savage4_waitfifo(struct savagefb_par *par, int space) 267 { 268 int slots = MAXFIFO - space; 269 270 while ((savage_in32(0x48C60, par) & 0x001fffff) > slots); 271 } 272 273 static void 274 savage2000_waitfifo(struct savagefb_par *par, int space) 275 { 276 int slots = MAXFIFO - space; 277 278 while ((savage_in32(0x48C60, par) & 0x0000ffff) > slots); 279 } 280 281 /* Wait for idle accelerator */ 282 static void 283 savage3D_waitidle(struct savagefb_par *par) 284 { 285 while ((savage_in32(0x48C00, par) & 0x0008ffff) != 0x80000); 286 } 287 288 static void 289 savage4_waitidle(struct savagefb_par *par) 290 { 291 while ((savage_in32(0x48C60, par) & 0x00a00000) != 0x00a00000); 292 } 293 294 static void 295 savage2000_waitidle(struct savagefb_par *par) 296 { 297 while ((savage_in32(0x48C60, par) & 0x009fffff)); 298 } 299 300 #ifdef CONFIG_FB_SAVAGE_ACCEL 301 static void 302 SavageSetup2DEngine(struct savagefb_par *par) 303 { 304 unsigned long GlobalBitmapDescriptor; 305 306 GlobalBitmapDescriptor = 1 | 8 | BCI_BD_BW_DISABLE; 307 BCI_BD_SET_BPP(GlobalBitmapDescriptor, par->depth); 308 BCI_BD_SET_STRIDE(GlobalBitmapDescriptor, par->vwidth); 309 310 switch(par->chip) { 311 case S3_SAVAGE3D: 312 case S3_SAVAGE_MX: 313 /* Disable BCI */ 314 savage_out32(0x48C18, savage_in32(0x48C18, par) & 0x3FF0, par); 315 /* Setup BCI command overflow buffer */ 316 savage_out32(0x48C14, 317 (par->cob_offset >> 11) | (par->cob_index << 29), 318 par); 319 /* Program shadow status update. */ 320 savage_out32(0x48C10, 0x78207220, par); 321 savage_out32(0x48C0C, 0, par); 322 /* Enable BCI and command overflow buffer */ 323 savage_out32(0x48C18, savage_in32(0x48C18, par) | 0x0C, par); 324 break; 325 case S3_SAVAGE4: 326 case S3_TWISTER: 327 case S3_PROSAVAGE: 328 case S3_PROSAVAGEDDR: 329 case S3_SUPERSAVAGE: 330 /* Disable BCI */ 331 savage_out32(0x48C18, savage_in32(0x48C18, par) & 0x3FF0, par); 332 /* Program shadow status update */ 333 savage_out32(0x48C10, 0x00700040, par); 334 savage_out32(0x48C0C, 0, par); 335 /* Enable BCI without the COB */ 336 savage_out32(0x48C18, savage_in32(0x48C18, par) | 0x08, par); 337 break; 338 case S3_SAVAGE2000: 339 /* Disable BCI */ 340 savage_out32(0x48C18, 0, par); 341 /* Setup BCI command overflow buffer */ 342 savage_out32(0x48C18, 343 (par->cob_offset >> 7) | (par->cob_index), 344 par); 345 /* Disable shadow status update */ 346 savage_out32(0x48A30, 0, par); 347 /* Enable BCI and command overflow buffer */ 348 savage_out32(0x48C18, savage_in32(0x48C18, par) | 0x00280000, 349 par); 350 break; 351 default: 352 break; 353 } 354 /* Turn on 16-bit register access. */ 355 vga_out8(0x3d4, 0x31, par); 356 vga_out8(0x3d5, 0x0c, par); 357 358 /* Set stride to use GBD. */ 359 vga_out8(0x3d4, 0x50, par); 360 vga_out8(0x3d5, vga_in8(0x3d5, par) | 0xC1, par); 361 362 /* Enable 2D engine. */ 363 vga_out8(0x3d4, 0x40, par); 364 vga_out8(0x3d5, 0x01, par); 365 366 savage_out32(MONO_PAT_0, ~0, par); 367 savage_out32(MONO_PAT_1, ~0, par); 368 369 /* Setup plane masks */ 370 savage_out32(0x8128, ~0, par); /* enable all write planes */ 371 savage_out32(0x812C, ~0, par); /* enable all read planes */ 372 savage_out16(0x8134, 0x27, par); 373 savage_out16(0x8136, 0x07, par); 374 375 /* Now set the GBD */ 376 par->bci_ptr = 0; 377 par->SavageWaitFifo(par, 4); 378 379 BCI_SEND(BCI_CMD_SETREG | (1 << 16) | BCI_GBD1); 380 BCI_SEND(0); 381 BCI_SEND(BCI_CMD_SETREG | (1 << 16) | BCI_GBD2); 382 BCI_SEND(GlobalBitmapDescriptor); 383 384 /* 385 * I don't know why, sending this twice fixes the initial black screen, 386 * prevents X from crashing at least in Toshiba laptops with SavageIX. 387 * --Tony 388 */ 389 par->bci_ptr = 0; 390 par->SavageWaitFifo(par, 4); 391 392 BCI_SEND(BCI_CMD_SETREG | (1 << 16) | BCI_GBD1); 393 BCI_SEND(0); 394 BCI_SEND(BCI_CMD_SETREG | (1 << 16) | BCI_GBD2); 395 BCI_SEND(GlobalBitmapDescriptor); 396 } 397 398 static void savagefb_set_clip(struct fb_info *info) 399 { 400 struct savagefb_par *par = info->par; 401 int cmd; 402 403 cmd = BCI_CMD_NOP | BCI_CMD_CLIP_NEW; 404 par->bci_ptr = 0; 405 par->SavageWaitFifo(par,3); 406 BCI_SEND(cmd); 407 BCI_SEND(BCI_CLIP_TL(0, 0)); 408 BCI_SEND(BCI_CLIP_BR(0xfff, 0xfff)); 409 } 410 #else 411 static void SavageSetup2DEngine(struct savagefb_par *par) {} 412 413 #endif 414 415 static void SavageCalcClock(long freq, int min_m, int min_n1, int max_n1, 416 int min_n2, int max_n2, long freq_min, 417 long freq_max, unsigned int *mdiv, 418 unsigned int *ndiv, unsigned int *r) 419 { 420 long diff, best_diff; 421 unsigned int m; 422 unsigned char n1, n2, best_n1=16+2, best_n2=2, best_m=125+2; 423 424 if (freq < freq_min / (1 << max_n2)) { 425 printk(KERN_ERR "invalid frequency %ld Khz\n", freq); 426 freq = freq_min / (1 << max_n2); 427 } 428 if (freq > freq_max / (1 << min_n2)) { 429 printk(KERN_ERR "invalid frequency %ld Khz\n", freq); 430 freq = freq_max / (1 << min_n2); 431 } 432 433 /* work out suitable timings */ 434 best_diff = freq; 435 436 for (n2=min_n2; n2<=max_n2; n2++) { 437 for (n1=min_n1+2; n1<=max_n1+2; n1++) { 438 m = (freq * n1 * (1 << n2) + HALF_BASE_FREQ) / 439 BASE_FREQ; 440 if (m < min_m+2 || m > 127+2) 441 continue; 442 if ((m * BASE_FREQ >= freq_min * n1) && 443 (m * BASE_FREQ <= freq_max * n1)) { 444 diff = freq * (1 << n2) * n1 - BASE_FREQ * m; 445 if (diff < 0) 446 diff = -diff; 447 if (diff < best_diff) { 448 best_diff = diff; 449 best_m = m; 450 best_n1 = n1; 451 best_n2 = n2; 452 } 453 } 454 } 455 } 456 457 *ndiv = best_n1 - 2; 458 *r = best_n2; 459 *mdiv = best_m - 2; 460 } 461 462 static int common_calc_clock(long freq, int min_m, int min_n1, int max_n1, 463 int min_n2, int max_n2, long freq_min, 464 long freq_max, unsigned char *mdiv, 465 unsigned char *ndiv) 466 { 467 long diff, best_diff; 468 unsigned int m; 469 unsigned char n1, n2; 470 unsigned char best_n1 = 16+2, best_n2 = 2, best_m = 125+2; 471 472 best_diff = freq; 473 474 for (n2 = min_n2; n2 <= max_n2; n2++) { 475 for (n1 = min_n1+2; n1 <= max_n1+2; n1++) { 476 m = (freq * n1 * (1 << n2) + HALF_BASE_FREQ) / 477 BASE_FREQ; 478 if (m < min_m + 2 || m > 127+2) 479 continue; 480 if ((m * BASE_FREQ >= freq_min * n1) && 481 (m * BASE_FREQ <= freq_max * n1)) { 482 diff = freq * (1 << n2) * n1 - BASE_FREQ * m; 483 if (diff < 0) 484 diff = -diff; 485 if (diff < best_diff) { 486 best_diff = diff; 487 best_m = m; 488 best_n1 = n1; 489 best_n2 = n2; 490 } 491 } 492 } 493 } 494 495 if (max_n1 == 63) 496 *ndiv = (best_n1 - 2) | (best_n2 << 6); 497 else 498 *ndiv = (best_n1 - 2) | (best_n2 << 5); 499 500 *mdiv = best_m - 2; 501 502 return 0; 503 } 504 505 #ifdef SAVAGEFB_DEBUG 506 /* This function is used to debug, it prints out the contents of s3 regs */ 507 508 static void SavagePrintRegs(struct savagefb_par *par) 509 { 510 unsigned char i; 511 int vgaCRIndex = 0x3d4; 512 int vgaCRReg = 0x3d5; 513 514 printk(KERN_DEBUG "SR x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 xA xB xC xD xE " 515 "xF"); 516 517 for (i = 0; i < 0x70; i++) { 518 if (!(i % 16)) 519 printk(KERN_DEBUG "\nSR%xx ", i >> 4); 520 vga_out8(0x3c4, i, par); 521 printk(KERN_DEBUG " %02x", vga_in8(0x3c5, par)); 522 } 523 524 printk(KERN_DEBUG "\n\nCR x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 xA xB xC " 525 "xD xE xF"); 526 527 for (i = 0; i < 0xB7; i++) { 528 if (!(i % 16)) 529 printk(KERN_DEBUG "\nCR%xx ", i >> 4); 530 vga_out8(vgaCRIndex, i, par); 531 printk(KERN_DEBUG " %02x", vga_in8(vgaCRReg, par)); 532 } 533 534 printk(KERN_DEBUG "\n\n"); 535 } 536 #endif 537 538 /* --------------------------------------------------------------------- */ 539 540 static void savage_get_default_par(struct savagefb_par *par, struct savage_reg *reg) 541 { 542 unsigned char cr3a, cr53, cr66; 543 544 vga_out16(0x3d4, 0x4838, par); 545 vga_out16(0x3d4, 0xa039, par); 546 vga_out16(0x3c4, 0x0608, par); 547 548 vga_out8(0x3d4, 0x66, par); 549 cr66 = vga_in8(0x3d5, par); 550 vga_out8(0x3d5, cr66 | 0x80, par); 551 vga_out8(0x3d4, 0x3a, par); 552 cr3a = vga_in8(0x3d5, par); 553 vga_out8(0x3d5, cr3a | 0x80, par); 554 vga_out8(0x3d4, 0x53, par); 555 cr53 = vga_in8(0x3d5, par); 556 vga_out8(0x3d5, cr53 & 0x7f, par); 557 558 vga_out8(0x3d4, 0x66, par); 559 vga_out8(0x3d5, cr66, par); 560 vga_out8(0x3d4, 0x3a, par); 561 vga_out8(0x3d5, cr3a, par); 562 563 vga_out8(0x3d4, 0x66, par); 564 vga_out8(0x3d5, cr66, par); 565 vga_out8(0x3d4, 0x3a, par); 566 vga_out8(0x3d5, cr3a, par); 567 568 /* unlock extended seq regs */ 569 vga_out8(0x3c4, 0x08, par); 570 reg->SR08 = vga_in8(0x3c5, par); 571 vga_out8(0x3c5, 0x06, par); 572 573 /* now save all the extended regs we need */ 574 vga_out8(0x3d4, 0x31, par); 575 reg->CR31 = vga_in8(0x3d5, par); 576 vga_out8(0x3d4, 0x32, par); 577 reg->CR32 = vga_in8(0x3d5, par); 578 vga_out8(0x3d4, 0x34, par); 579 reg->CR34 = vga_in8(0x3d5, par); 580 vga_out8(0x3d4, 0x36, par); 581 reg->CR36 = vga_in8(0x3d5, par); 582 vga_out8(0x3d4, 0x3a, par); 583 reg->CR3A = vga_in8(0x3d5, par); 584 vga_out8(0x3d4, 0x40, par); 585 reg->CR40 = vga_in8(0x3d5, par); 586 vga_out8(0x3d4, 0x42, par); 587 reg->CR42 = vga_in8(0x3d5, par); 588 vga_out8(0x3d4, 0x45, par); 589 reg->CR45 = vga_in8(0x3d5, par); 590 vga_out8(0x3d4, 0x50, par); 591 reg->CR50 = vga_in8(0x3d5, par); 592 vga_out8(0x3d4, 0x51, par); 593 reg->CR51 = vga_in8(0x3d5, par); 594 vga_out8(0x3d4, 0x53, par); 595 reg->CR53 = vga_in8(0x3d5, par); 596 vga_out8(0x3d4, 0x58, par); 597 reg->CR58 = vga_in8(0x3d5, par); 598 vga_out8(0x3d4, 0x60, par); 599 reg->CR60 = vga_in8(0x3d5, par); 600 vga_out8(0x3d4, 0x66, par); 601 reg->CR66 = vga_in8(0x3d5, par); 602 vga_out8(0x3d4, 0x67, par); 603 reg->CR67 = vga_in8(0x3d5, par); 604 vga_out8(0x3d4, 0x68, par); 605 reg->CR68 = vga_in8(0x3d5, par); 606 vga_out8(0x3d4, 0x69, par); 607 reg->CR69 = vga_in8(0x3d5, par); 608 vga_out8(0x3d4, 0x6f, par); 609 reg->CR6F = vga_in8(0x3d5, par); 610 611 vga_out8(0x3d4, 0x33, par); 612 reg->CR33 = vga_in8(0x3d5, par); 613 vga_out8(0x3d4, 0x86, par); 614 reg->CR86 = vga_in8(0x3d5, par); 615 vga_out8(0x3d4, 0x88, par); 616 reg->CR88 = vga_in8(0x3d5, par); 617 vga_out8(0x3d4, 0x90, par); 618 reg->CR90 = vga_in8(0x3d5, par); 619 vga_out8(0x3d4, 0x91, par); 620 reg->CR91 = vga_in8(0x3d5, par); 621 vga_out8(0x3d4, 0xb0, par); 622 reg->CRB0 = vga_in8(0x3d5, par) | 0x80; 623 624 /* extended mode timing regs */ 625 vga_out8(0x3d4, 0x3b, par); 626 reg->CR3B = vga_in8(0x3d5, par); 627 vga_out8(0x3d4, 0x3c, par); 628 reg->CR3C = vga_in8(0x3d5, par); 629 vga_out8(0x3d4, 0x43, par); 630 reg->CR43 = vga_in8(0x3d5, par); 631 vga_out8(0x3d4, 0x5d, par); 632 reg->CR5D = vga_in8(0x3d5, par); 633 vga_out8(0x3d4, 0x5e, par); 634 reg->CR5E = vga_in8(0x3d5, par); 635 vga_out8(0x3d4, 0x65, par); 636 reg->CR65 = vga_in8(0x3d5, par); 637 638 /* save seq extended regs for DCLK PLL programming */ 639 vga_out8(0x3c4, 0x0e, par); 640 reg->SR0E = vga_in8(0x3c5, par); 641 vga_out8(0x3c4, 0x0f, par); 642 reg->SR0F = vga_in8(0x3c5, par); 643 vga_out8(0x3c4, 0x10, par); 644 reg->SR10 = vga_in8(0x3c5, par); 645 vga_out8(0x3c4, 0x11, par); 646 reg->SR11 = vga_in8(0x3c5, par); 647 vga_out8(0x3c4, 0x12, par); 648 reg->SR12 = vga_in8(0x3c5, par); 649 vga_out8(0x3c4, 0x13, par); 650 reg->SR13 = vga_in8(0x3c5, par); 651 vga_out8(0x3c4, 0x29, par); 652 reg->SR29 = vga_in8(0x3c5, par); 653 654 vga_out8(0x3c4, 0x15, par); 655 reg->SR15 = vga_in8(0x3c5, par); 656 vga_out8(0x3c4, 0x30, par); 657 reg->SR30 = vga_in8(0x3c5, par); 658 vga_out8(0x3c4, 0x18, par); 659 reg->SR18 = vga_in8(0x3c5, par); 660 661 /* Save flat panel expansion registers. */ 662 if (par->chip == S3_SAVAGE_MX) { 663 int i; 664 665 for (i = 0; i < 8; i++) { 666 vga_out8(0x3c4, 0x54+i, par); 667 reg->SR54[i] = vga_in8(0x3c5, par); 668 } 669 } 670 671 vga_out8(0x3d4, 0x66, par); 672 cr66 = vga_in8(0x3d5, par); 673 vga_out8(0x3d5, cr66 | 0x80, par); 674 vga_out8(0x3d4, 0x3a, par); 675 cr3a = vga_in8(0x3d5, par); 676 vga_out8(0x3d5, cr3a | 0x80, par); 677 678 /* now save MIU regs */ 679 if (par->chip != S3_SAVAGE_MX) { 680 reg->MMPR0 = savage_in32(FIFO_CONTROL_REG, par); 681 reg->MMPR1 = savage_in32(MIU_CONTROL_REG, par); 682 reg->MMPR2 = savage_in32(STREAMS_TIMEOUT_REG, par); 683 reg->MMPR3 = savage_in32(MISC_TIMEOUT_REG, par); 684 } 685 686 vga_out8(0x3d4, 0x3a, par); 687 vga_out8(0x3d5, cr3a, par); 688 vga_out8(0x3d4, 0x66, par); 689 vga_out8(0x3d5, cr66, par); 690 } 691 692 static void savage_set_default_par(struct savagefb_par *par, 693 struct savage_reg *reg) 694 { 695 unsigned char cr3a, cr53, cr66; 696 697 vga_out16(0x3d4, 0x4838, par); 698 vga_out16(0x3d4, 0xa039, par); 699 vga_out16(0x3c4, 0x0608, par); 700 701 vga_out8(0x3d4, 0x66, par); 702 cr66 = vga_in8(0x3d5, par); 703 vga_out8(0x3d5, cr66 | 0x80, par); 704 vga_out8(0x3d4, 0x3a, par); 705 cr3a = vga_in8(0x3d5, par); 706 vga_out8(0x3d5, cr3a | 0x80, par); 707 vga_out8(0x3d4, 0x53, par); 708 cr53 = vga_in8(0x3d5, par); 709 vga_out8(0x3d5, cr53 & 0x7f, par); 710 711 vga_out8(0x3d4, 0x66, par); 712 vga_out8(0x3d5, cr66, par); 713 vga_out8(0x3d4, 0x3a, par); 714 vga_out8(0x3d5, cr3a, par); 715 716 vga_out8(0x3d4, 0x66, par); 717 vga_out8(0x3d5, cr66, par); 718 vga_out8(0x3d4, 0x3a, par); 719 vga_out8(0x3d5, cr3a, par); 720 721 /* unlock extended seq regs */ 722 vga_out8(0x3c4, 0x08, par); 723 vga_out8(0x3c5, reg->SR08, par); 724 vga_out8(0x3c5, 0x06, par); 725 726 /* now restore all the extended regs we need */ 727 vga_out8(0x3d4, 0x31, par); 728 vga_out8(0x3d5, reg->CR31, par); 729 vga_out8(0x3d4, 0x32, par); 730 vga_out8(0x3d5, reg->CR32, par); 731 vga_out8(0x3d4, 0x34, par); 732 vga_out8(0x3d5, reg->CR34, par); 733 vga_out8(0x3d4, 0x36, par); 734 vga_out8(0x3d5,reg->CR36, par); 735 vga_out8(0x3d4, 0x3a, par); 736 vga_out8(0x3d5, reg->CR3A, par); 737 vga_out8(0x3d4, 0x40, par); 738 vga_out8(0x3d5, reg->CR40, par); 739 vga_out8(0x3d4, 0x42, par); 740 vga_out8(0x3d5, reg->CR42, par); 741 vga_out8(0x3d4, 0x45, par); 742 vga_out8(0x3d5, reg->CR45, par); 743 vga_out8(0x3d4, 0x50, par); 744 vga_out8(0x3d5, reg->CR50, par); 745 vga_out8(0x3d4, 0x51, par); 746 vga_out8(0x3d5, reg->CR51, par); 747 vga_out8(0x3d4, 0x53, par); 748 vga_out8(0x3d5, reg->CR53, par); 749 vga_out8(0x3d4, 0x58, par); 750 vga_out8(0x3d5, reg->CR58, par); 751 vga_out8(0x3d4, 0x60, par); 752 vga_out8(0x3d5, reg->CR60, par); 753 vga_out8(0x3d4, 0x66, par); 754 vga_out8(0x3d5, reg->CR66, par); 755 vga_out8(0x3d4, 0x67, par); 756 vga_out8(0x3d5, reg->CR67, par); 757 vga_out8(0x3d4, 0x68, par); 758 vga_out8(0x3d5, reg->CR68, par); 759 vga_out8(0x3d4, 0x69, par); 760 vga_out8(0x3d5, reg->CR69, par); 761 vga_out8(0x3d4, 0x6f, par); 762 vga_out8(0x3d5, reg->CR6F, par); 763 764 vga_out8(0x3d4, 0x33, par); 765 vga_out8(0x3d5, reg->CR33, par); 766 vga_out8(0x3d4, 0x86, par); 767 vga_out8(0x3d5, reg->CR86, par); 768 vga_out8(0x3d4, 0x88, par); 769 vga_out8(0x3d5, reg->CR88, par); 770 vga_out8(0x3d4, 0x90, par); 771 vga_out8(0x3d5, reg->CR90, par); 772 vga_out8(0x3d4, 0x91, par); 773 vga_out8(0x3d5, reg->CR91, par); 774 vga_out8(0x3d4, 0xb0, par); 775 vga_out8(0x3d5, reg->CRB0, par); 776 777 /* extended mode timing regs */ 778 vga_out8(0x3d4, 0x3b, par); 779 vga_out8(0x3d5, reg->CR3B, par); 780 vga_out8(0x3d4, 0x3c, par); 781 vga_out8(0x3d5, reg->CR3C, par); 782 vga_out8(0x3d4, 0x43, par); 783 vga_out8(0x3d5, reg->CR43, par); 784 vga_out8(0x3d4, 0x5d, par); 785 vga_out8(0x3d5, reg->CR5D, par); 786 vga_out8(0x3d4, 0x5e, par); 787 vga_out8(0x3d5, reg->CR5E, par); 788 vga_out8(0x3d4, 0x65, par); 789 vga_out8(0x3d5, reg->CR65, par); 790 791 /* save seq extended regs for DCLK PLL programming */ 792 vga_out8(0x3c4, 0x0e, par); 793 vga_out8(0x3c5, reg->SR0E, par); 794 vga_out8(0x3c4, 0x0f, par); 795 vga_out8(0x3c5, reg->SR0F, par); 796 vga_out8(0x3c4, 0x10, par); 797 vga_out8(0x3c5, reg->SR10, par); 798 vga_out8(0x3c4, 0x11, par); 799 vga_out8(0x3c5, reg->SR11, par); 800 vga_out8(0x3c4, 0x12, par); 801 vga_out8(0x3c5, reg->SR12, par); 802 vga_out8(0x3c4, 0x13, par); 803 vga_out8(0x3c5, reg->SR13, par); 804 vga_out8(0x3c4, 0x29, par); 805 vga_out8(0x3c5, reg->SR29, par); 806 807 vga_out8(0x3c4, 0x15, par); 808 vga_out8(0x3c5, reg->SR15, par); 809 vga_out8(0x3c4, 0x30, par); 810 vga_out8(0x3c5, reg->SR30, par); 811 vga_out8(0x3c4, 0x18, par); 812 vga_out8(0x3c5, reg->SR18, par); 813 814 /* Save flat panel expansion registers. */ 815 if (par->chip == S3_SAVAGE_MX) { 816 int i; 817 818 for (i = 0; i < 8; i++) { 819 vga_out8(0x3c4, 0x54+i, par); 820 vga_out8(0x3c5, reg->SR54[i], par); 821 } 822 } 823 824 vga_out8(0x3d4, 0x66, par); 825 cr66 = vga_in8(0x3d5, par); 826 vga_out8(0x3d5, cr66 | 0x80, par); 827 vga_out8(0x3d4, 0x3a, par); 828 cr3a = vga_in8(0x3d5, par); 829 vga_out8(0x3d5, cr3a | 0x80, par); 830 831 /* now save MIU regs */ 832 if (par->chip != S3_SAVAGE_MX) { 833 savage_out32(FIFO_CONTROL_REG, reg->MMPR0, par); 834 savage_out32(MIU_CONTROL_REG, reg->MMPR1, par); 835 savage_out32(STREAMS_TIMEOUT_REG, reg->MMPR2, par); 836 savage_out32(MISC_TIMEOUT_REG, reg->MMPR3, par); 837 } 838 839 vga_out8(0x3d4, 0x3a, par); 840 vga_out8(0x3d5, cr3a, par); 841 vga_out8(0x3d4, 0x66, par); 842 vga_out8(0x3d5, cr66, par); 843 } 844 845 static void savage_update_var(struct fb_var_screeninfo *var, 846 const struct fb_videomode *modedb) 847 { 848 var->xres = var->xres_virtual = modedb->xres; 849 var->yres = modedb->yres; 850 if (var->yres_virtual < var->yres) 851 var->yres_virtual = var->yres; 852 var->xoffset = var->yoffset = 0; 853 var->pixclock = modedb->pixclock; 854 var->left_margin = modedb->left_margin; 855 var->right_margin = modedb->right_margin; 856 var->upper_margin = modedb->upper_margin; 857 var->lower_margin = modedb->lower_margin; 858 var->hsync_len = modedb->hsync_len; 859 var->vsync_len = modedb->vsync_len; 860 var->sync = modedb->sync; 861 var->vmode = modedb->vmode; 862 } 863 864 static int savagefb_check_var(struct fb_var_screeninfo *var, 865 struct fb_info *info) 866 { 867 struct savagefb_par *par = info->par; 868 int memlen, vramlen, mode_valid = 0; 869 870 DBG("savagefb_check_var"); 871 872 var->transp.offset = 0; 873 var->transp.length = 0; 874 switch (var->bits_per_pixel) { 875 case 8: 876 var->red.offset = var->green.offset = 877 var->blue.offset = 0; 878 var->red.length = var->green.length = 879 var->blue.length = var->bits_per_pixel; 880 break; 881 case 16: 882 var->red.offset = 11; 883 var->red.length = 5; 884 var->green.offset = 5; 885 var->green.length = 6; 886 var->blue.offset = 0; 887 var->blue.length = 5; 888 break; 889 case 32: 890 var->transp.offset = 24; 891 var->transp.length = 8; 892 var->red.offset = 16; 893 var->red.length = 8; 894 var->green.offset = 8; 895 var->green.length = 8; 896 var->blue.offset = 0; 897 var->blue.length = 8; 898 break; 899 900 default: 901 return -EINVAL; 902 } 903 904 if (!info->monspecs.hfmax || !info->monspecs.vfmax || 905 !info->monspecs.dclkmax || !fb_validate_mode(var, info)) 906 mode_valid = 1; 907 908 /* calculate modeline if supported by monitor */ 909 if (!mode_valid && info->monspecs.gtf) { 910 if (!fb_get_mode(FB_MAXTIMINGS, 0, var, info)) 911 mode_valid = 1; 912 } 913 914 if (!mode_valid) { 915 const struct fb_videomode *mode; 916 917 mode = fb_find_best_mode(var, &info->modelist); 918 if (mode) { 919 savage_update_var(var, mode); 920 mode_valid = 1; 921 } 922 } 923 924 if (!mode_valid && info->monspecs.modedb_len) 925 return -EINVAL; 926 927 /* Is the mode larger than the LCD panel? */ 928 if (par->SavagePanelWidth && 929 (var->xres > par->SavagePanelWidth || 930 var->yres > par->SavagePanelHeight)) { 931 printk(KERN_INFO "Mode (%dx%d) larger than the LCD panel " 932 "(%dx%d)\n", var->xres, var->yres, 933 par->SavagePanelWidth, 934 par->SavagePanelHeight); 935 return -1; 936 } 937 938 if (var->yres_virtual < var->yres) 939 var->yres_virtual = var->yres; 940 if (var->xres_virtual < var->xres) 941 var->xres_virtual = var->xres; 942 943 vramlen = info->fix.smem_len; 944 945 memlen = var->xres_virtual * var->bits_per_pixel * 946 var->yres_virtual / 8; 947 if (memlen > vramlen) { 948 var->yres_virtual = vramlen * 8 / 949 (var->xres_virtual * var->bits_per_pixel); 950 memlen = var->xres_virtual * var->bits_per_pixel * 951 var->yres_virtual / 8; 952 } 953 954 /* we must round yres/xres down, we already rounded y/xres_virtual up 955 if it was possible. We should return -EINVAL, but I disagree */ 956 if (var->yres_virtual < var->yres) 957 var->yres = var->yres_virtual; 958 if (var->xres_virtual < var->xres) 959 var->xres = var->xres_virtual; 960 if (var->xoffset + var->xres > var->xres_virtual) 961 var->xoffset = var->xres_virtual - var->xres; 962 if (var->yoffset + var->yres > var->yres_virtual) 963 var->yoffset = var->yres_virtual - var->yres; 964 965 return 0; 966 } 967 968 969 static int savagefb_decode_var(struct fb_var_screeninfo *var, 970 struct savagefb_par *par, 971 struct savage_reg *reg) 972 { 973 struct xtimings timings; 974 int width, dclk, i, j; /*, refresh; */ 975 unsigned int m, n, r; 976 unsigned char tmp = 0; 977 unsigned int pixclock = var->pixclock; 978 979 DBG("savagefb_decode_var"); 980 981 memset(&timings, 0, sizeof(timings)); 982 983 if (!pixclock) pixclock = 10000; /* 10ns = 100MHz */ 984 timings.Clock = 1000000000 / pixclock; 985 if (timings.Clock < 1) timings.Clock = 1; 986 timings.dblscan = var->vmode & FB_VMODE_DOUBLE; 987 timings.interlaced = var->vmode & FB_VMODE_INTERLACED; 988 timings.HDisplay = var->xres; 989 timings.HSyncStart = timings.HDisplay + var->right_margin; 990 timings.HSyncEnd = timings.HSyncStart + var->hsync_len; 991 timings.HTotal = timings.HSyncEnd + var->left_margin; 992 timings.VDisplay = var->yres; 993 timings.VSyncStart = timings.VDisplay + var->lower_margin; 994 timings.VSyncEnd = timings.VSyncStart + var->vsync_len; 995 timings.VTotal = timings.VSyncEnd + var->upper_margin; 996 timings.sync = var->sync; 997 998 999 par->depth = var->bits_per_pixel; 1000 par->vwidth = var->xres_virtual; 1001 1002 if (var->bits_per_pixel == 16 && par->chip == S3_SAVAGE3D) { 1003 timings.HDisplay *= 2; 1004 timings.HSyncStart *= 2; 1005 timings.HSyncEnd *= 2; 1006 timings.HTotal *= 2; 1007 } 1008 1009 /* 1010 * This will allocate the datastructure and initialize all of the 1011 * generic VGA registers. 1012 */ 1013 vgaHWInit(var, par, &timings, reg); 1014 1015 /* We need to set CR67 whether or not we use the BIOS. */ 1016 1017 dclk = timings.Clock; 1018 reg->CR67 = 0x00; 1019 1020 switch(var->bits_per_pixel) { 1021 case 8: 1022 if ((par->chip == S3_SAVAGE2000) && (dclk >= 230000)) 1023 reg->CR67 = 0x10; /* 8bpp, 2 pixels/clock */ 1024 else 1025 reg->CR67 = 0x00; /* 8bpp, 1 pixel/clock */ 1026 break; 1027 case 15: 1028 if (S3_SAVAGE_MOBILE_SERIES(par->chip) || 1029 ((par->chip == S3_SAVAGE2000) && (dclk >= 230000))) 1030 reg->CR67 = 0x30; /* 15bpp, 2 pixel/clock */ 1031 else 1032 reg->CR67 = 0x20; /* 15bpp, 1 pixels/clock */ 1033 break; 1034 case 16: 1035 if (S3_SAVAGE_MOBILE_SERIES(par->chip) || 1036 ((par->chip == S3_SAVAGE2000) && (dclk >= 230000))) 1037 reg->CR67 = 0x50; /* 16bpp, 2 pixel/clock */ 1038 else 1039 reg->CR67 = 0x40; /* 16bpp, 1 pixels/clock */ 1040 break; 1041 case 24: 1042 reg->CR67 = 0x70; 1043 break; 1044 case 32: 1045 reg->CR67 = 0xd0; 1046 break; 1047 } 1048 1049 /* 1050 * Either BIOS use is disabled, or we failed to find a suitable 1051 * match. Fall back to traditional register-crunching. 1052 */ 1053 1054 vga_out8(0x3d4, 0x3a, par); 1055 tmp = vga_in8(0x3d5, par); 1056 if (1 /*FIXME:psav->pci_burst*/) 1057 reg->CR3A = (tmp & 0x7f) | 0x15; 1058 else 1059 reg->CR3A = tmp | 0x95; 1060 1061 reg->CR53 = 0x00; 1062 reg->CR31 = 0x8c; 1063 reg->CR66 = 0x89; 1064 1065 vga_out8(0x3d4, 0x58, par); 1066 reg->CR58 = vga_in8(0x3d5, par) & 0x80; 1067 reg->CR58 |= 0x13; 1068 1069 reg->SR15 = 0x03 | 0x80; 1070 reg->SR18 = 0x00; 1071 reg->CR43 = reg->CR45 = reg->CR65 = 0x00; 1072 1073 vga_out8(0x3d4, 0x40, par); 1074 reg->CR40 = vga_in8(0x3d5, par) & ~0x01; 1075 1076 reg->MMPR0 = 0x010400; 1077 reg->MMPR1 = 0x00; 1078 reg->MMPR2 = 0x0808; 1079 reg->MMPR3 = 0x08080810; 1080 1081 SavageCalcClock(dclk, 1, 1, 127, 0, 4, 180000, 360000, &m, &n, &r); 1082 /* m = 107; n = 4; r = 2; */ 1083 1084 if (par->MCLK <= 0) { 1085 reg->SR10 = 255; 1086 reg->SR11 = 255; 1087 } else { 1088 common_calc_clock(par->MCLK, 1, 1, 31, 0, 3, 135000, 270000, 1089 ®->SR11, ®->SR10); 1090 /* reg->SR10 = 80; // MCLK == 286000 */ 1091 /* reg->SR11 = 125; */ 1092 } 1093 1094 reg->SR12 = (r << 6) | (n & 0x3f); 1095 reg->SR13 = m & 0xff; 1096 reg->SR29 = (r & 4) | (m & 0x100) >> 5 | (n & 0x40) >> 2; 1097 1098 if (var->bits_per_pixel < 24) 1099 reg->MMPR0 -= 0x8000; 1100 else 1101 reg->MMPR0 -= 0x4000; 1102 1103 if (timings.interlaced) 1104 reg->CR42 = 0x20; 1105 else 1106 reg->CR42 = 0x00; 1107 1108 reg->CR34 = 0x10; /* display fifo */ 1109 1110 i = ((((timings.HTotal >> 3) - 5) & 0x100) >> 8) | 1111 ((((timings.HDisplay >> 3) - 1) & 0x100) >> 7) | 1112 ((((timings.HSyncStart >> 3) - 1) & 0x100) >> 6) | 1113 ((timings.HSyncStart & 0x800) >> 7); 1114 1115 if ((timings.HSyncEnd >> 3) - (timings.HSyncStart >> 3) > 64) 1116 i |= 0x08; 1117 if ((timings.HSyncEnd >> 3) - (timings.HSyncStart >> 3) > 32) 1118 i |= 0x20; 1119 1120 j = (reg->CRTC[0] + ((i & 0x01) << 8) + 1121 reg->CRTC[4] + ((i & 0x10) << 4) + 1) / 2; 1122 1123 if (j - (reg->CRTC[4] + ((i & 0x10) << 4)) < 4) { 1124 if (reg->CRTC[4] + ((i & 0x10) << 4) + 4 <= 1125 reg->CRTC[0] + ((i & 0x01) << 8)) 1126 j = reg->CRTC[4] + ((i & 0x10) << 4) + 4; 1127 else 1128 j = reg->CRTC[0] + ((i & 0x01) << 8) + 1; 1129 } 1130 1131 reg->CR3B = j & 0xff; 1132 i |= (j & 0x100) >> 2; 1133 reg->CR3C = (reg->CRTC[0] + ((i & 0x01) << 8)) / 2; 1134 reg->CR5D = i; 1135 reg->CR5E = (((timings.VTotal - 2) & 0x400) >> 10) | 1136 (((timings.VDisplay - 1) & 0x400) >> 9) | 1137 (((timings.VSyncStart) & 0x400) >> 8) | 1138 (((timings.VSyncStart) & 0x400) >> 6) | 0x40; 1139 width = (var->xres_virtual * ((var->bits_per_pixel+7) / 8)) >> 3; 1140 reg->CR91 = reg->CRTC[19] = 0xff & width; 1141 reg->CR51 = (0x300 & width) >> 4; 1142 reg->CR90 = 0x80 | (width >> 8); 1143 reg->MiscOutReg |= 0x0c; 1144 1145 /* Set frame buffer description. */ 1146 1147 if (var->bits_per_pixel <= 8) 1148 reg->CR50 = 0; 1149 else if (var->bits_per_pixel <= 16) 1150 reg->CR50 = 0x10; 1151 else 1152 reg->CR50 = 0x30; 1153 1154 if (var->xres_virtual <= 640) 1155 reg->CR50 |= 0x40; 1156 else if (var->xres_virtual == 800) 1157 reg->CR50 |= 0x80; 1158 else if (var->xres_virtual == 1024) 1159 reg->CR50 |= 0x00; 1160 else if (var->xres_virtual == 1152) 1161 reg->CR50 |= 0x01; 1162 else if (var->xres_virtual == 1280) 1163 reg->CR50 |= 0xc0; 1164 else if (var->xres_virtual == 1600) 1165 reg->CR50 |= 0x81; 1166 else 1167 reg->CR50 |= 0xc1; /* Use GBD */ 1168 1169 if (par->chip == S3_SAVAGE2000) 1170 reg->CR33 = 0x08; 1171 else 1172 reg->CR33 = 0x20; 1173 1174 reg->CRTC[0x17] = 0xeb; 1175 1176 reg->CR67 |= 1; 1177 1178 vga_out8(0x3d4, 0x36, par); 1179 reg->CR36 = vga_in8(0x3d5, par); 1180 vga_out8(0x3d4, 0x68, par); 1181 reg->CR68 = vga_in8(0x3d5, par); 1182 reg->CR69 = 0; 1183 vga_out8(0x3d4, 0x6f, par); 1184 reg->CR6F = vga_in8(0x3d5, par); 1185 vga_out8(0x3d4, 0x86, par); 1186 reg->CR86 = vga_in8(0x3d5, par); 1187 vga_out8(0x3d4, 0x88, par); 1188 reg->CR88 = vga_in8(0x3d5, par) | 0x08; 1189 vga_out8(0x3d4, 0xb0, par); 1190 reg->CRB0 = vga_in8(0x3d5, par) | 0x80; 1191 1192 return 0; 1193 } 1194 1195 /* --------------------------------------------------------------------- */ 1196 1197 /* 1198 * Set a single color register. Return != 0 for invalid regno. 1199 */ 1200 static int savagefb_setcolreg(unsigned regno, 1201 unsigned red, 1202 unsigned green, 1203 unsigned blue, 1204 unsigned transp, 1205 struct fb_info *info) 1206 { 1207 struct savagefb_par *par = info->par; 1208 1209 if (regno >= NR_PALETTE) 1210 return -EINVAL; 1211 1212 par->palette[regno].red = red; 1213 par->palette[regno].green = green; 1214 par->palette[regno].blue = blue; 1215 par->palette[regno].transp = transp; 1216 1217 switch (info->var.bits_per_pixel) { 1218 case 8: 1219 vga_out8(0x3c8, regno, par); 1220 1221 vga_out8(0x3c9, red >> 10, par); 1222 vga_out8(0x3c9, green >> 10, par); 1223 vga_out8(0x3c9, blue >> 10, par); 1224 break; 1225 1226 case 16: 1227 if (regno < 16) 1228 ((u32 *)info->pseudo_palette)[regno] = 1229 ((red & 0xf800) ) | 1230 ((green & 0xfc00) >> 5) | 1231 ((blue & 0xf800) >> 11); 1232 break; 1233 1234 case 24: 1235 if (regno < 16) 1236 ((u32 *)info->pseudo_palette)[regno] = 1237 ((red & 0xff00) << 8) | 1238 ((green & 0xff00) ) | 1239 ((blue & 0xff00) >> 8); 1240 break; 1241 case 32: 1242 if (regno < 16) 1243 ((u32 *)info->pseudo_palette)[regno] = 1244 ((transp & 0xff00) << 16) | 1245 ((red & 0xff00) << 8) | 1246 ((green & 0xff00) ) | 1247 ((blue & 0xff00) >> 8); 1248 break; 1249 1250 default: 1251 return 1; 1252 } 1253 1254 return 0; 1255 } 1256 1257 static void savagefb_set_par_int(struct savagefb_par *par, struct savage_reg *reg) 1258 { 1259 unsigned char tmp, cr3a, cr66, cr67; 1260 1261 DBG("savagefb_set_par_int"); 1262 1263 par->SavageWaitIdle(par); 1264 1265 vga_out8(0x3c2, 0x23, par); 1266 1267 vga_out16(0x3d4, 0x4838, par); 1268 vga_out16(0x3d4, 0xa539, par); 1269 vga_out16(0x3c4, 0x0608, par); 1270 1271 vgaHWProtect(par, 1); 1272 1273 /* 1274 * Some Savage/MX and /IX systems go nuts when trying to exit the 1275 * server after WindowMaker has displayed a gradient background. I 1276 * haven't been able to find what causes it, but a non-destructive 1277 * switch to mode 3 here seems to eliminate the issue. 1278 */ 1279 1280 VerticalRetraceWait(par); 1281 vga_out8(0x3d4, 0x67, par); 1282 cr67 = vga_in8(0x3d5, par); 1283 vga_out8(0x3d5, cr67/*par->CR67*/ & ~0x0c, par); /* no STREAMS yet */ 1284 1285 vga_out8(0x3d4, 0x23, par); 1286 vga_out8(0x3d5, 0x00, par); 1287 vga_out8(0x3d4, 0x26, par); 1288 vga_out8(0x3d5, 0x00, par); 1289 1290 /* restore extended regs */ 1291 vga_out8(0x3d4, 0x66, par); 1292 vga_out8(0x3d5, reg->CR66, par); 1293 vga_out8(0x3d4, 0x3a, par); 1294 vga_out8(0x3d5, reg->CR3A, par); 1295 vga_out8(0x3d4, 0x31, par); 1296 vga_out8(0x3d5, reg->CR31, par); 1297 vga_out8(0x3d4, 0x32, par); 1298 vga_out8(0x3d5, reg->CR32, par); 1299 vga_out8(0x3d4, 0x58, par); 1300 vga_out8(0x3d5, reg->CR58, par); 1301 vga_out8(0x3d4, 0x53, par); 1302 vga_out8(0x3d5, reg->CR53 & 0x7f, par); 1303 1304 vga_out16(0x3c4, 0x0608, par); 1305 1306 /* Restore DCLK registers. */ 1307 1308 vga_out8(0x3c4, 0x0e, par); 1309 vga_out8(0x3c5, reg->SR0E, par); 1310 vga_out8(0x3c4, 0x0f, par); 1311 vga_out8(0x3c5, reg->SR0F, par); 1312 vga_out8(0x3c4, 0x29, par); 1313 vga_out8(0x3c5, reg->SR29, par); 1314 vga_out8(0x3c4, 0x15, par); 1315 vga_out8(0x3c5, reg->SR15, par); 1316 1317 /* Restore flat panel expansion registers. */ 1318 if (par->chip == S3_SAVAGE_MX) { 1319 int i; 1320 1321 for (i = 0; i < 8; i++) { 1322 vga_out8(0x3c4, 0x54+i, par); 1323 vga_out8(0x3c5, reg->SR54[i], par); 1324 } 1325 } 1326 1327 vgaHWRestore (par, reg); 1328 1329 /* extended mode timing registers */ 1330 vga_out8(0x3d4, 0x53, par); 1331 vga_out8(0x3d5, reg->CR53, par); 1332 vga_out8(0x3d4, 0x5d, par); 1333 vga_out8(0x3d5, reg->CR5D, par); 1334 vga_out8(0x3d4, 0x5e, par); 1335 vga_out8(0x3d5, reg->CR5E, par); 1336 vga_out8(0x3d4, 0x3b, par); 1337 vga_out8(0x3d5, reg->CR3B, par); 1338 vga_out8(0x3d4, 0x3c, par); 1339 vga_out8(0x3d5, reg->CR3C, par); 1340 vga_out8(0x3d4, 0x43, par); 1341 vga_out8(0x3d5, reg->CR43, par); 1342 vga_out8(0x3d4, 0x65, par); 1343 vga_out8(0x3d5, reg->CR65, par); 1344 1345 /* restore the desired video mode with cr67 */ 1346 vga_out8(0x3d4, 0x67, par); 1347 /* following part not present in X11 driver */ 1348 cr67 = vga_in8(0x3d5, par) & 0xf; 1349 vga_out8(0x3d5, 0x50 | cr67, par); 1350 mdelay(10); 1351 vga_out8(0x3d4, 0x67, par); 1352 /* end of part */ 1353 vga_out8(0x3d5, reg->CR67 & ~0x0c, par); 1354 1355 /* other mode timing and extended regs */ 1356 vga_out8(0x3d4, 0x34, par); 1357 vga_out8(0x3d5, reg->CR34, par); 1358 vga_out8(0x3d4, 0x40, par); 1359 vga_out8(0x3d5, reg->CR40, par); 1360 vga_out8(0x3d4, 0x42, par); 1361 vga_out8(0x3d5, reg->CR42, par); 1362 vga_out8(0x3d4, 0x45, par); 1363 vga_out8(0x3d5, reg->CR45, par); 1364 vga_out8(0x3d4, 0x50, par); 1365 vga_out8(0x3d5, reg->CR50, par); 1366 vga_out8(0x3d4, 0x51, par); 1367 vga_out8(0x3d5, reg->CR51, par); 1368 1369 /* memory timings */ 1370 vga_out8(0x3d4, 0x36, par); 1371 vga_out8(0x3d5, reg->CR36, par); 1372 vga_out8(0x3d4, 0x60, par); 1373 vga_out8(0x3d5, reg->CR60, par); 1374 vga_out8(0x3d4, 0x68, par); 1375 vga_out8(0x3d5, reg->CR68, par); 1376 vga_out8(0x3d4, 0x69, par); 1377 vga_out8(0x3d5, reg->CR69, par); 1378 vga_out8(0x3d4, 0x6f, par); 1379 vga_out8(0x3d5, reg->CR6F, par); 1380 1381 vga_out8(0x3d4, 0x33, par); 1382 vga_out8(0x3d5, reg->CR33, par); 1383 vga_out8(0x3d4, 0x86, par); 1384 vga_out8(0x3d5, reg->CR86, par); 1385 vga_out8(0x3d4, 0x88, par); 1386 vga_out8(0x3d5, reg->CR88, par); 1387 vga_out8(0x3d4, 0x90, par); 1388 vga_out8(0x3d5, reg->CR90, par); 1389 vga_out8(0x3d4, 0x91, par); 1390 vga_out8(0x3d5, reg->CR91, par); 1391 1392 if (par->chip == S3_SAVAGE4) { 1393 vga_out8(0x3d4, 0xb0, par); 1394 vga_out8(0x3d5, reg->CRB0, par); 1395 } 1396 1397 vga_out8(0x3d4, 0x32, par); 1398 vga_out8(0x3d5, reg->CR32, par); 1399 1400 /* unlock extended seq regs */ 1401 vga_out8(0x3c4, 0x08, par); 1402 vga_out8(0x3c5, 0x06, par); 1403 1404 /* Restore extended sequencer regs for MCLK. SR10 == 255 indicates 1405 * that we should leave the default SR10 and SR11 values there. 1406 */ 1407 if (reg->SR10 != 255) { 1408 vga_out8(0x3c4, 0x10, par); 1409 vga_out8(0x3c5, reg->SR10, par); 1410 vga_out8(0x3c4, 0x11, par); 1411 vga_out8(0x3c5, reg->SR11, par); 1412 } 1413 1414 /* restore extended seq regs for dclk */ 1415 vga_out8(0x3c4, 0x0e, par); 1416 vga_out8(0x3c5, reg->SR0E, par); 1417 vga_out8(0x3c4, 0x0f, par); 1418 vga_out8(0x3c5, reg->SR0F, par); 1419 vga_out8(0x3c4, 0x12, par); 1420 vga_out8(0x3c5, reg->SR12, par); 1421 vga_out8(0x3c4, 0x13, par); 1422 vga_out8(0x3c5, reg->SR13, par); 1423 vga_out8(0x3c4, 0x29, par); 1424 vga_out8(0x3c5, reg->SR29, par); 1425 vga_out8(0x3c4, 0x18, par); 1426 vga_out8(0x3c5, reg->SR18, par); 1427 1428 /* load new m, n pll values for dclk & mclk */ 1429 vga_out8(0x3c4, 0x15, par); 1430 tmp = vga_in8(0x3c5, par) & ~0x21; 1431 1432 vga_out8(0x3c5, tmp | 0x03, par); 1433 vga_out8(0x3c5, tmp | 0x23, par); 1434 vga_out8(0x3c5, tmp | 0x03, par); 1435 vga_out8(0x3c5, reg->SR15, par); 1436 udelay(100); 1437 1438 vga_out8(0x3c4, 0x30, par); 1439 vga_out8(0x3c5, reg->SR30, par); 1440 vga_out8(0x3c4, 0x08, par); 1441 vga_out8(0x3c5, reg->SR08, par); 1442 1443 /* now write out cr67 in full, possibly starting STREAMS */ 1444 VerticalRetraceWait(par); 1445 vga_out8(0x3d4, 0x67, par); 1446 vga_out8(0x3d5, reg->CR67, par); 1447 1448 vga_out8(0x3d4, 0x66, par); 1449 cr66 = vga_in8(0x3d5, par); 1450 vga_out8(0x3d5, cr66 | 0x80, par); 1451 vga_out8(0x3d4, 0x3a, par); 1452 cr3a = vga_in8(0x3d5, par); 1453 vga_out8(0x3d5, cr3a | 0x80, par); 1454 1455 if (par->chip != S3_SAVAGE_MX) { 1456 VerticalRetraceWait(par); 1457 savage_out32(FIFO_CONTROL_REG, reg->MMPR0, par); 1458 par->SavageWaitIdle(par); 1459 savage_out32(MIU_CONTROL_REG, reg->MMPR1, par); 1460 par->SavageWaitIdle(par); 1461 savage_out32(STREAMS_TIMEOUT_REG, reg->MMPR2, par); 1462 par->SavageWaitIdle(par); 1463 savage_out32(MISC_TIMEOUT_REG, reg->MMPR3, par); 1464 } 1465 1466 vga_out8(0x3d4, 0x66, par); 1467 vga_out8(0x3d5, cr66, par); 1468 vga_out8(0x3d4, 0x3a, par); 1469 vga_out8(0x3d5, cr3a, par); 1470 1471 SavageSetup2DEngine(par); 1472 vgaHWProtect(par, 0); 1473 } 1474 1475 static void savagefb_update_start(struct savagefb_par *par, int base) 1476 { 1477 /* program the start address registers */ 1478 vga_out16(0x3d4, (base & 0x00ff00) | 0x0c, par); 1479 vga_out16(0x3d4, ((base & 0x00ff) << 8) | 0x0d, par); 1480 vga_out8(0x3d4, 0x69, par); 1481 vga_out8(0x3d5, (base & 0x7f0000) >> 16, par); 1482 } 1483 1484 1485 static void savagefb_set_fix(struct fb_info *info) 1486 { 1487 info->fix.line_length = info->var.xres_virtual * 1488 info->var.bits_per_pixel / 8; 1489 1490 if (info->var.bits_per_pixel == 8) { 1491 info->fix.visual = FB_VISUAL_PSEUDOCOLOR; 1492 info->fix.xpanstep = 4; 1493 } else { 1494 info->fix.visual = FB_VISUAL_TRUECOLOR; 1495 info->fix.xpanstep = 2; 1496 } 1497 1498 } 1499 1500 static int savagefb_set_par(struct fb_info *info) 1501 { 1502 struct savagefb_par *par = info->par; 1503 struct fb_var_screeninfo *var = &info->var; 1504 int err; 1505 1506 DBG("savagefb_set_par"); 1507 err = savagefb_decode_var(var, par, &par->state); 1508 if (err) 1509 return err; 1510 1511 if (par->dacSpeedBpp <= 0) { 1512 if (var->bits_per_pixel > 24) 1513 par->dacSpeedBpp = par->clock[3]; 1514 else if (var->bits_per_pixel >= 24) 1515 par->dacSpeedBpp = par->clock[2]; 1516 else if ((var->bits_per_pixel > 8) && (var->bits_per_pixel < 24)) 1517 par->dacSpeedBpp = par->clock[1]; 1518 else if (var->bits_per_pixel <= 8) 1519 par->dacSpeedBpp = par->clock[0]; 1520 } 1521 1522 /* Set ramdac limits */ 1523 par->maxClock = par->dacSpeedBpp; 1524 par->minClock = 10000; 1525 1526 savagefb_set_par_int(par, &par->state); 1527 fb_set_cmap(&info->cmap, info); 1528 savagefb_set_fix(info); 1529 savagefb_set_clip(info); 1530 1531 SavagePrintRegs(par); 1532 return 0; 1533 } 1534 1535 /* 1536 * Pan or Wrap the Display 1537 */ 1538 static int savagefb_pan_display(struct fb_var_screeninfo *var, 1539 struct fb_info *info) 1540 { 1541 struct savagefb_par *par = info->par; 1542 int base; 1543 1544 base = (var->yoffset * info->fix.line_length 1545 + (var->xoffset & ~1) * ((info->var.bits_per_pixel+7) / 8)) >> 2; 1546 1547 savagefb_update_start(par, base); 1548 return 0; 1549 } 1550 1551 static int savagefb_blank(int blank, struct fb_info *info) 1552 { 1553 struct savagefb_par *par = info->par; 1554 u8 sr8 = 0, srd = 0; 1555 1556 if (par->display_type == DISP_CRT) { 1557 vga_out8(0x3c4, 0x08, par); 1558 sr8 = vga_in8(0x3c5, par); 1559 sr8 |= 0x06; 1560 vga_out8(0x3c5, sr8, par); 1561 vga_out8(0x3c4, 0x0d, par); 1562 srd = vga_in8(0x3c5, par); 1563 srd &= 0x50; 1564 1565 switch (blank) { 1566 case FB_BLANK_UNBLANK: 1567 case FB_BLANK_NORMAL: 1568 break; 1569 case FB_BLANK_VSYNC_SUSPEND: 1570 srd |= 0x10; 1571 break; 1572 case FB_BLANK_HSYNC_SUSPEND: 1573 srd |= 0x40; 1574 break; 1575 case FB_BLANK_POWERDOWN: 1576 srd |= 0x50; 1577 break; 1578 } 1579 1580 vga_out8(0x3c4, 0x0d, par); 1581 vga_out8(0x3c5, srd, par); 1582 } 1583 1584 if (par->display_type == DISP_LCD || 1585 par->display_type == DISP_DFP) { 1586 switch(blank) { 1587 case FB_BLANK_UNBLANK: 1588 case FB_BLANK_NORMAL: 1589 vga_out8(0x3c4, 0x31, par); /* SR31 bit 4 - FP enable */ 1590 vga_out8(0x3c5, vga_in8(0x3c5, par) | 0x10, par); 1591 break; 1592 case FB_BLANK_VSYNC_SUSPEND: 1593 case FB_BLANK_HSYNC_SUSPEND: 1594 case FB_BLANK_POWERDOWN: 1595 vga_out8(0x3c4, 0x31, par); /* SR31 bit 4 - FP enable */ 1596 vga_out8(0x3c5, vga_in8(0x3c5, par) & ~0x10, par); 1597 break; 1598 } 1599 } 1600 1601 return (blank == FB_BLANK_NORMAL) ? 1 : 0; 1602 } 1603 1604 static int savagefb_open(struct fb_info *info, int user) 1605 { 1606 struct savagefb_par *par = info->par; 1607 1608 mutex_lock(&par->open_lock); 1609 1610 if (!par->open_count) { 1611 memset(&par->vgastate, 0, sizeof(par->vgastate)); 1612 par->vgastate.flags = VGA_SAVE_CMAP | VGA_SAVE_FONTS | 1613 VGA_SAVE_MODE; 1614 par->vgastate.vgabase = par->mmio.vbase + 0x8000; 1615 save_vga(&par->vgastate); 1616 savage_get_default_par(par, &par->initial); 1617 } 1618 1619 par->open_count++; 1620 mutex_unlock(&par->open_lock); 1621 return 0; 1622 } 1623 1624 static int savagefb_release(struct fb_info *info, int user) 1625 { 1626 struct savagefb_par *par = info->par; 1627 1628 mutex_lock(&par->open_lock); 1629 1630 if (par->open_count == 1) { 1631 savage_set_default_par(par, &par->initial); 1632 restore_vga(&par->vgastate); 1633 } 1634 1635 par->open_count--; 1636 mutex_unlock(&par->open_lock); 1637 return 0; 1638 } 1639 1640 static struct fb_ops savagefb_ops = { 1641 .owner = THIS_MODULE, 1642 .fb_open = savagefb_open, 1643 .fb_release = savagefb_release, 1644 .fb_check_var = savagefb_check_var, 1645 .fb_set_par = savagefb_set_par, 1646 .fb_setcolreg = savagefb_setcolreg, 1647 .fb_pan_display = savagefb_pan_display, 1648 .fb_blank = savagefb_blank, 1649 #if defined(CONFIG_FB_SAVAGE_ACCEL) 1650 .fb_fillrect = savagefb_fillrect, 1651 .fb_copyarea = savagefb_copyarea, 1652 .fb_imageblit = savagefb_imageblit, 1653 .fb_sync = savagefb_sync, 1654 #else 1655 .fb_fillrect = cfb_fillrect, 1656 .fb_copyarea = cfb_copyarea, 1657 .fb_imageblit = cfb_imageblit, 1658 #endif 1659 }; 1660 1661 /* --------------------------------------------------------------------- */ 1662 1663 static const struct fb_var_screeninfo savagefb_var800x600x8 = { 1664 .accel_flags = FB_ACCELF_TEXT, 1665 .xres = 800, 1666 .yres = 600, 1667 .xres_virtual = 800, 1668 .yres_virtual = 600, 1669 .bits_per_pixel = 8, 1670 .pixclock = 25000, 1671 .left_margin = 88, 1672 .right_margin = 40, 1673 .upper_margin = 23, 1674 .lower_margin = 1, 1675 .hsync_len = 128, 1676 .vsync_len = 4, 1677 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, 1678 .vmode = FB_VMODE_NONINTERLACED 1679 }; 1680 1681 static void savage_enable_mmio(struct savagefb_par *par) 1682 { 1683 unsigned char val; 1684 1685 DBG("savage_enable_mmio\n"); 1686 1687 val = vga_in8(0x3c3, par); 1688 vga_out8(0x3c3, val | 0x01, par); 1689 val = vga_in8(0x3cc, par); 1690 vga_out8(0x3c2, val | 0x01, par); 1691 1692 if (par->chip >= S3_SAVAGE4) { 1693 vga_out8(0x3d4, 0x40, par); 1694 val = vga_in8(0x3d5, par); 1695 vga_out8(0x3d5, val | 1, par); 1696 } 1697 } 1698 1699 1700 static void savage_disable_mmio(struct savagefb_par *par) 1701 { 1702 unsigned char val; 1703 1704 DBG("savage_disable_mmio\n"); 1705 1706 if (par->chip >= S3_SAVAGE4) { 1707 vga_out8(0x3d4, 0x40, par); 1708 val = vga_in8(0x3d5, par); 1709 vga_out8(0x3d5, val | 1, par); 1710 } 1711 } 1712 1713 1714 static int savage_map_mmio(struct fb_info *info) 1715 { 1716 struct savagefb_par *par = info->par; 1717 DBG("savage_map_mmio"); 1718 1719 if (S3_SAVAGE3D_SERIES(par->chip)) 1720 par->mmio.pbase = pci_resource_start(par->pcidev, 0) + 1721 SAVAGE_NEWMMIO_REGBASE_S3; 1722 else 1723 par->mmio.pbase = pci_resource_start(par->pcidev, 0) + 1724 SAVAGE_NEWMMIO_REGBASE_S4; 1725 1726 par->mmio.len = SAVAGE_NEWMMIO_REGSIZE; 1727 1728 par->mmio.vbase = ioremap(par->mmio.pbase, par->mmio.len); 1729 if (!par->mmio.vbase) { 1730 printk("savagefb: unable to map memory mapped IO\n"); 1731 return -ENOMEM; 1732 } else 1733 printk(KERN_INFO "savagefb: mapped io at %p\n", 1734 par->mmio.vbase); 1735 1736 info->fix.mmio_start = par->mmio.pbase; 1737 info->fix.mmio_len = par->mmio.len; 1738 1739 par->bci_base = (u32 __iomem *)(par->mmio.vbase + BCI_BUFFER_OFFSET); 1740 par->bci_ptr = 0; 1741 1742 savage_enable_mmio(par); 1743 1744 return 0; 1745 } 1746 1747 static void savage_unmap_mmio(struct fb_info *info) 1748 { 1749 struct savagefb_par *par = info->par; 1750 DBG("savage_unmap_mmio"); 1751 1752 savage_disable_mmio(par); 1753 1754 if (par->mmio.vbase) { 1755 iounmap(par->mmio.vbase); 1756 par->mmio.vbase = NULL; 1757 } 1758 } 1759 1760 static int savage_map_video(struct fb_info *info, int video_len) 1761 { 1762 struct savagefb_par *par = info->par; 1763 int resource; 1764 1765 DBG("savage_map_video"); 1766 1767 if (S3_SAVAGE3D_SERIES(par->chip)) 1768 resource = 0; 1769 else 1770 resource = 1; 1771 1772 par->video.pbase = pci_resource_start(par->pcidev, resource); 1773 par->video.len = video_len; 1774 par->video.vbase = ioremap_wc(par->video.pbase, par->video.len); 1775 1776 if (!par->video.vbase) { 1777 printk("savagefb: unable to map screen memory\n"); 1778 return -ENOMEM; 1779 } else 1780 printk(KERN_INFO "savagefb: mapped framebuffer at %p, " 1781 "pbase == %x\n", par->video.vbase, par->video.pbase); 1782 1783 info->fix.smem_start = par->video.pbase; 1784 info->fix.smem_len = par->video.len - par->cob_size; 1785 info->screen_base = par->video.vbase; 1786 par->video.wc_cookie = arch_phys_wc_add(par->video.pbase, video_len); 1787 1788 /* Clear framebuffer, it's all white in memory after boot */ 1789 memset_io(par->video.vbase, 0, par->video.len); 1790 1791 return 0; 1792 } 1793 1794 static void savage_unmap_video(struct fb_info *info) 1795 { 1796 struct savagefb_par *par = info->par; 1797 1798 DBG("savage_unmap_video"); 1799 1800 if (par->video.vbase) { 1801 arch_phys_wc_del(par->video.wc_cookie); 1802 iounmap(par->video.vbase); 1803 par->video.vbase = NULL; 1804 info->screen_base = NULL; 1805 } 1806 } 1807 1808 static int savage_init_hw(struct savagefb_par *par) 1809 { 1810 unsigned char config1, m, n, n1, n2, sr8, cr3f, cr66 = 0, tmp; 1811 1812 static unsigned char RamSavage3D[] = { 8, 4, 4, 2 }; 1813 static unsigned char RamSavage4[] = { 2, 4, 8, 12, 16, 32, 64, 32 }; 1814 static unsigned char RamSavageMX[] = { 2, 8, 4, 16, 8, 16, 4, 16 }; 1815 static unsigned char RamSavageNB[] = { 0, 2, 4, 8, 16, 32, 2, 2 }; 1816 int videoRam, videoRambytes, dvi; 1817 1818 DBG("savage_init_hw"); 1819 1820 /* unprotect CRTC[0-7] */ 1821 vga_out8(0x3d4, 0x11, par); 1822 tmp = vga_in8(0x3d5, par); 1823 vga_out8(0x3d5, tmp & 0x7f, par); 1824 1825 /* unlock extended regs */ 1826 vga_out16(0x3d4, 0x4838, par); 1827 vga_out16(0x3d4, 0xa039, par); 1828 vga_out16(0x3c4, 0x0608, par); 1829 1830 vga_out8(0x3d4, 0x40, par); 1831 tmp = vga_in8(0x3d5, par); 1832 vga_out8(0x3d5, tmp & ~0x01, par); 1833 1834 /* unlock sys regs */ 1835 vga_out8(0x3d4, 0x38, par); 1836 vga_out8(0x3d5, 0x48, par); 1837 1838 /* Unlock system registers. */ 1839 vga_out16(0x3d4, 0x4838, par); 1840 1841 /* Next go on to detect amount of installed ram */ 1842 1843 vga_out8(0x3d4, 0x36, par); /* for register CR36 (CONFG_REG1), */ 1844 config1 = vga_in8(0x3d5, par); /* get amount of vram installed */ 1845 1846 /* Compute the amount of video memory and offscreen memory. */ 1847 1848 switch (par->chip) { 1849 case S3_SAVAGE3D: 1850 videoRam = RamSavage3D[(config1 & 0xC0) >> 6 ] * 1024; 1851 break; 1852 1853 case S3_SAVAGE4: 1854 /* 1855 * The Savage4 has one ugly special case to consider. On 1856 * systems with 4 banks of 2Mx32 SDRAM, the BIOS says 4MB 1857 * when it really means 8MB. Why do it the same when you 1858 * can do it different... 1859 */ 1860 vga_out8(0x3d4, 0x68, par); /* memory control 1 */ 1861 if ((vga_in8(0x3d5, par) & 0xC0) == (0x01 << 6)) 1862 RamSavage4[1] = 8; 1863 1864 /*FALLTHROUGH*/ 1865 1866 case S3_SAVAGE2000: 1867 videoRam = RamSavage4[(config1 & 0xE0) >> 5] * 1024; 1868 break; 1869 1870 case S3_SAVAGE_MX: 1871 case S3_SUPERSAVAGE: 1872 videoRam = RamSavageMX[(config1 & 0x0E) >> 1] * 1024; 1873 break; 1874 1875 case S3_PROSAVAGE: 1876 case S3_PROSAVAGEDDR: 1877 case S3_TWISTER: 1878 videoRam = RamSavageNB[(config1 & 0xE0) >> 5] * 1024; 1879 break; 1880 1881 default: 1882 /* How did we get here? */ 1883 videoRam = 0; 1884 break; 1885 } 1886 1887 videoRambytes = videoRam * 1024; 1888 1889 printk(KERN_INFO "savagefb: probed videoram: %dk\n", videoRam); 1890 1891 /* reset graphics engine to avoid memory corruption */ 1892 vga_out8(0x3d4, 0x66, par); 1893 cr66 = vga_in8(0x3d5, par); 1894 vga_out8(0x3d5, cr66 | 0x02, par); 1895 usleep_range(10000, 11000); 1896 1897 vga_out8(0x3d4, 0x66, par); 1898 vga_out8(0x3d5, cr66 & ~0x02, par); /* clear reset flag */ 1899 usleep_range(10000, 11000); 1900 1901 1902 /* 1903 * reset memory interface, 3D engine, AGP master, PCI master, 1904 * master engine unit, motion compensation/LPB 1905 */ 1906 vga_out8(0x3d4, 0x3f, par); 1907 cr3f = vga_in8(0x3d5, par); 1908 vga_out8(0x3d5, cr3f | 0x08, par); 1909 usleep_range(10000, 11000); 1910 1911 vga_out8(0x3d4, 0x3f, par); 1912 vga_out8(0x3d5, cr3f & ~0x08, par); /* clear reset flags */ 1913 usleep_range(10000, 11000); 1914 1915 /* Savage ramdac speeds */ 1916 par->numClocks = 4; 1917 par->clock[0] = 250000; 1918 par->clock[1] = 250000; 1919 par->clock[2] = 220000; 1920 par->clock[3] = 220000; 1921 1922 /* detect current mclk */ 1923 vga_out8(0x3c4, 0x08, par); 1924 sr8 = vga_in8(0x3c5, par); 1925 vga_out8(0x3c5, 0x06, par); 1926 vga_out8(0x3c4, 0x10, par); 1927 n = vga_in8(0x3c5, par); 1928 vga_out8(0x3c4, 0x11, par); 1929 m = vga_in8(0x3c5, par); 1930 vga_out8(0x3c4, 0x08, par); 1931 vga_out8(0x3c5, sr8, par); 1932 m &= 0x7f; 1933 n1 = n & 0x1f; 1934 n2 = (n >> 5) & 0x03; 1935 par->MCLK = ((1431818 * (m+2)) / (n1+2) / (1 << n2) + 50) / 100; 1936 printk(KERN_INFO "savagefb: Detected current MCLK value of %d kHz\n", 1937 par->MCLK); 1938 1939 /* check for DVI/flat panel */ 1940 dvi = 0; 1941 1942 if (par->chip == S3_SAVAGE4) { 1943 unsigned char sr30 = 0x00; 1944 1945 vga_out8(0x3c4, 0x30, par); 1946 /* clear bit 1 */ 1947 vga_out8(0x3c5, vga_in8(0x3c5, par) & ~0x02, par); 1948 sr30 = vga_in8(0x3c5, par); 1949 if (sr30 & 0x02 /*0x04 */) { 1950 dvi = 1; 1951 printk("savagefb: Digital Flat Panel Detected\n"); 1952 } 1953 } 1954 1955 if ((S3_SAVAGE_MOBILE_SERIES(par->chip) || 1956 S3_MOBILE_TWISTER_SERIES(par->chip)) && !par->crtonly) 1957 par->display_type = DISP_LCD; 1958 else if (dvi || (par->chip == S3_SAVAGE4 && par->dvi)) 1959 par->display_type = DISP_DFP; 1960 else 1961 par->display_type = DISP_CRT; 1962 1963 /* Check LCD panel parrmation */ 1964 1965 if (par->display_type == DISP_LCD) { 1966 unsigned char cr6b = VGArCR(0x6b, par); 1967 1968 int panelX = (VGArSEQ(0x61, par) + 1969 ((VGArSEQ(0x66, par) & 0x02) << 7) + 1) * 8; 1970 int panelY = (VGArSEQ(0x69, par) + 1971 ((VGArSEQ(0x6e, par) & 0x70) << 4) + 1); 1972 1973 char * sTechnology = "Unknown"; 1974 1975 /* OK, I admit it. I don't know how to limit the max dot clock 1976 * for LCD panels of various sizes. I thought I copied the 1977 * formula from the BIOS, but many users have parrmed me of 1978 * my folly. 1979 * 1980 * Instead, I'll abandon any attempt to automatically limit the 1981 * clock, and add an LCDClock option to XF86Config. Some day, 1982 * I should come back to this. 1983 */ 1984 1985 enum ACTIVE_DISPLAYS { /* These are the bits in CR6B */ 1986 ActiveCRT = 0x01, 1987 ActiveLCD = 0x02, 1988 ActiveTV = 0x04, 1989 ActiveCRT2 = 0x20, 1990 ActiveDUO = 0x80 1991 }; 1992 1993 if ((VGArSEQ(0x39, par) & 0x03) == 0) { 1994 sTechnology = "TFT"; 1995 } else if ((VGArSEQ(0x30, par) & 0x01) == 0) { 1996 sTechnology = "DSTN"; 1997 } else { 1998 sTechnology = "STN"; 1999 } 2000 2001 printk(KERN_INFO "savagefb: %dx%d %s LCD panel detected %s\n", 2002 panelX, panelY, sTechnology, 2003 cr6b & ActiveLCD ? "and active" : "but not active"); 2004 2005 if (cr6b & ActiveLCD) { 2006 /* 2007 * If the LCD is active and panel expansion is enabled, 2008 * we probably want to kill the HW cursor. 2009 */ 2010 2011 printk(KERN_INFO "savagefb: Limiting video mode to " 2012 "%dx%d\n", panelX, panelY); 2013 2014 par->SavagePanelWidth = panelX; 2015 par->SavagePanelHeight = panelY; 2016 2017 } else 2018 par->display_type = DISP_CRT; 2019 } 2020 2021 savage_get_default_par(par, &par->state); 2022 par->save = par->state; 2023 2024 if (S3_SAVAGE4_SERIES(par->chip)) { 2025 /* 2026 * The Savage4 and ProSavage have COB coherency bugs which 2027 * render the buffer useless. We disable it. 2028 */ 2029 par->cob_index = 2; 2030 par->cob_size = 0x8000 << par->cob_index; 2031 par->cob_offset = videoRambytes; 2032 } else { 2033 /* We use 128kB for the COB on all chips. */ 2034 2035 par->cob_index = 7; 2036 par->cob_size = 0x400 << par->cob_index; 2037 par->cob_offset = videoRambytes - par->cob_size; 2038 } 2039 2040 return videoRambytes; 2041 } 2042 2043 static int savage_init_fb_info(struct fb_info *info, struct pci_dev *dev, 2044 const struct pci_device_id *id) 2045 { 2046 struct savagefb_par *par = info->par; 2047 int err = 0; 2048 2049 par->pcidev = dev; 2050 2051 info->fix.type = FB_TYPE_PACKED_PIXELS; 2052 info->fix.type_aux = 0; 2053 info->fix.ypanstep = 1; 2054 info->fix.ywrapstep = 0; 2055 info->fix.accel = id->driver_data; 2056 2057 switch (info->fix.accel) { 2058 case FB_ACCEL_SUPERSAVAGE: 2059 par->chip = S3_SUPERSAVAGE; 2060 snprintf(info->fix.id, 16, "SuperSavage"); 2061 break; 2062 case FB_ACCEL_SAVAGE4: 2063 par->chip = S3_SAVAGE4; 2064 snprintf(info->fix.id, 16, "Savage4"); 2065 break; 2066 case FB_ACCEL_SAVAGE3D: 2067 par->chip = S3_SAVAGE3D; 2068 snprintf(info->fix.id, 16, "Savage3D"); 2069 break; 2070 case FB_ACCEL_SAVAGE3D_MV: 2071 par->chip = S3_SAVAGE3D; 2072 snprintf(info->fix.id, 16, "Savage3D-MV"); 2073 break; 2074 case FB_ACCEL_SAVAGE2000: 2075 par->chip = S3_SAVAGE2000; 2076 snprintf(info->fix.id, 16, "Savage2000"); 2077 break; 2078 case FB_ACCEL_SAVAGE_MX_MV: 2079 par->chip = S3_SAVAGE_MX; 2080 snprintf(info->fix.id, 16, "Savage/MX-MV"); 2081 break; 2082 case FB_ACCEL_SAVAGE_MX: 2083 par->chip = S3_SAVAGE_MX; 2084 snprintf(info->fix.id, 16, "Savage/MX"); 2085 break; 2086 case FB_ACCEL_SAVAGE_IX_MV: 2087 par->chip = S3_SAVAGE_MX; 2088 snprintf(info->fix.id, 16, "Savage/IX-MV"); 2089 break; 2090 case FB_ACCEL_SAVAGE_IX: 2091 par->chip = S3_SAVAGE_MX; 2092 snprintf(info->fix.id, 16, "Savage/IX"); 2093 break; 2094 case FB_ACCEL_PROSAVAGE_PM: 2095 par->chip = S3_PROSAVAGE; 2096 snprintf(info->fix.id, 16, "ProSavagePM"); 2097 break; 2098 case FB_ACCEL_PROSAVAGE_KM: 2099 par->chip = S3_PROSAVAGE; 2100 snprintf(info->fix.id, 16, "ProSavageKM"); 2101 break; 2102 case FB_ACCEL_S3TWISTER_P: 2103 par->chip = S3_TWISTER; 2104 snprintf(info->fix.id, 16, "TwisterP"); 2105 break; 2106 case FB_ACCEL_S3TWISTER_K: 2107 par->chip = S3_TWISTER; 2108 snprintf(info->fix.id, 16, "TwisterK"); 2109 break; 2110 case FB_ACCEL_PROSAVAGE_DDR: 2111 par->chip = S3_PROSAVAGEDDR; 2112 snprintf(info->fix.id, 16, "ProSavageDDR"); 2113 break; 2114 case FB_ACCEL_PROSAVAGE_DDRK: 2115 par->chip = S3_PROSAVAGEDDR; 2116 snprintf(info->fix.id, 16, "ProSavage8"); 2117 break; 2118 } 2119 2120 if (S3_SAVAGE3D_SERIES(par->chip)) { 2121 par->SavageWaitIdle = savage3D_waitidle; 2122 par->SavageWaitFifo = savage3D_waitfifo; 2123 } else if (S3_SAVAGE4_SERIES(par->chip) || 2124 S3_SUPERSAVAGE == par->chip) { 2125 par->SavageWaitIdle = savage4_waitidle; 2126 par->SavageWaitFifo = savage4_waitfifo; 2127 } else { 2128 par->SavageWaitIdle = savage2000_waitidle; 2129 par->SavageWaitFifo = savage2000_waitfifo; 2130 } 2131 2132 info->var.nonstd = 0; 2133 info->var.activate = FB_ACTIVATE_NOW; 2134 info->var.width = -1; 2135 info->var.height = -1; 2136 info->var.accel_flags = 0; 2137 2138 info->fbops = &savagefb_ops; 2139 info->flags = FBINFO_DEFAULT | 2140 FBINFO_HWACCEL_YPAN | 2141 FBINFO_HWACCEL_XPAN; 2142 2143 info->pseudo_palette = par->pseudo_palette; 2144 2145 #if defined(CONFIG_FB_SAVAGE_ACCEL) 2146 /* FIFO size + padding for commands */ 2147 info->pixmap.addr = kcalloc(8, 1024, GFP_KERNEL); 2148 2149 err = -ENOMEM; 2150 if (info->pixmap.addr) { 2151 info->pixmap.size = 8*1024; 2152 info->pixmap.scan_align = 4; 2153 info->pixmap.buf_align = 4; 2154 info->pixmap.access_align = 32; 2155 2156 err = fb_alloc_cmap(&info->cmap, NR_PALETTE, 0); 2157 if (!err) 2158 info->flags |= FBINFO_HWACCEL_COPYAREA | 2159 FBINFO_HWACCEL_FILLRECT | 2160 FBINFO_HWACCEL_IMAGEBLIT; 2161 } 2162 #endif 2163 return err; 2164 } 2165 2166 /* --------------------------------------------------------------------- */ 2167 2168 static int savagefb_probe(struct pci_dev *dev, const struct pci_device_id *id) 2169 { 2170 struct fb_info *info; 2171 struct savagefb_par *par; 2172 u_int h_sync, v_sync; 2173 int err, lpitch; 2174 int video_len; 2175 2176 DBG("savagefb_probe"); 2177 2178 info = framebuffer_alloc(sizeof(struct savagefb_par), &dev->dev); 2179 if (!info) 2180 return -ENOMEM; 2181 par = info->par; 2182 mutex_init(&par->open_lock); 2183 err = pci_enable_device(dev); 2184 if (err) 2185 goto failed_enable; 2186 2187 if ((err = pci_request_regions(dev, "savagefb"))) { 2188 printk(KERN_ERR "cannot request PCI regions\n"); 2189 goto failed_enable; 2190 } 2191 2192 err = -ENOMEM; 2193 2194 if ((err = savage_init_fb_info(info, dev, id))) 2195 goto failed_init; 2196 2197 err = savage_map_mmio(info); 2198 if (err) 2199 goto failed_mmio; 2200 2201 video_len = savage_init_hw(par); 2202 /* FIXME: can't be negative */ 2203 if (video_len < 0) { 2204 err = video_len; 2205 goto failed_mmio; 2206 } 2207 2208 err = savage_map_video(info, video_len); 2209 if (err) 2210 goto failed_video; 2211 2212 INIT_LIST_HEAD(&info->modelist); 2213 #if defined(CONFIG_FB_SAVAGE_I2C) 2214 savagefb_create_i2c_busses(info); 2215 savagefb_probe_i2c_connector(info, &par->edid); 2216 fb_edid_to_monspecs(par->edid, &info->monspecs); 2217 kfree(par->edid); 2218 fb_videomode_to_modelist(info->monspecs.modedb, 2219 info->monspecs.modedb_len, 2220 &info->modelist); 2221 #endif 2222 info->var = savagefb_var800x600x8; 2223 /* if a panel was detected, default to a CVT mode instead */ 2224 if (par->SavagePanelWidth) { 2225 struct fb_videomode cvt_mode; 2226 2227 memset(&cvt_mode, 0, sizeof(cvt_mode)); 2228 cvt_mode.xres = par->SavagePanelWidth; 2229 cvt_mode.yres = par->SavagePanelHeight; 2230 cvt_mode.refresh = 60; 2231 /* FIXME: if we know there is only the panel 2232 * we can enable reduced blanking as well */ 2233 if (fb_find_mode_cvt(&cvt_mode, 0, 0)) 2234 printk(KERN_WARNING "No CVT mode found for panel\n"); 2235 else if (fb_find_mode(&info->var, info, NULL, NULL, 0, 2236 &cvt_mode, 0) != 3) 2237 info->var = savagefb_var800x600x8; 2238 } 2239 2240 if (mode_option) { 2241 fb_find_mode(&info->var, info, mode_option, 2242 info->monspecs.modedb, info->monspecs.modedb_len, 2243 NULL, 8); 2244 } else if (info->monspecs.modedb != NULL) { 2245 const struct fb_videomode *mode; 2246 2247 mode = fb_find_best_display(&info->monspecs, &info->modelist); 2248 savage_update_var(&info->var, mode); 2249 } 2250 2251 /* maximize virtual vertical length */ 2252 lpitch = info->var.xres_virtual*((info->var.bits_per_pixel + 7) >> 3); 2253 info->var.yres_virtual = info->fix.smem_len/lpitch; 2254 2255 if (info->var.yres_virtual < info->var.yres) { 2256 err = -ENOMEM; 2257 goto failed; 2258 } 2259 2260 #if defined(CONFIG_FB_SAVAGE_ACCEL) 2261 /* 2262 * The clipping coordinates are masked with 0xFFF, so limit our 2263 * virtual resolutions to these sizes. 2264 */ 2265 if (info->var.yres_virtual > 0x1000) 2266 info->var.yres_virtual = 0x1000; 2267 2268 if (info->var.xres_virtual > 0x1000) 2269 info->var.xres_virtual = 0x1000; 2270 #endif 2271 savagefb_check_var(&info->var, info); 2272 savagefb_set_fix(info); 2273 2274 /* 2275 * Calculate the hsync and vsync frequencies. Note that 2276 * we split the 1e12 constant up so that we can preserve 2277 * the precision and fit the results into 32-bit registers. 2278 * (1953125000 * 512 = 1e12) 2279 */ 2280 h_sync = 1953125000 / info->var.pixclock; 2281 h_sync = h_sync * 512 / (info->var.xres + info->var.left_margin + 2282 info->var.right_margin + 2283 info->var.hsync_len); 2284 v_sync = h_sync / (info->var.yres + info->var.upper_margin + 2285 info->var.lower_margin + info->var.vsync_len); 2286 2287 printk(KERN_INFO "savagefb v" SAVAGEFB_VERSION ": " 2288 "%dkB VRAM, using %dx%d, %d.%03dkHz, %dHz\n", 2289 info->fix.smem_len >> 10, 2290 info->var.xres, info->var.yres, 2291 h_sync / 1000, h_sync % 1000, v_sync); 2292 2293 2294 fb_destroy_modedb(info->monspecs.modedb); 2295 info->monspecs.modedb = NULL; 2296 2297 err = register_framebuffer(info); 2298 if (err < 0) 2299 goto failed; 2300 2301 printk(KERN_INFO "fb: S3 %s frame buffer device\n", 2302 info->fix.id); 2303 2304 /* 2305 * Our driver data 2306 */ 2307 pci_set_drvdata(dev, info); 2308 2309 return 0; 2310 2311 failed: 2312 #ifdef CONFIG_FB_SAVAGE_I2C 2313 savagefb_delete_i2c_busses(info); 2314 #endif 2315 fb_alloc_cmap(&info->cmap, 0, 0); 2316 savage_unmap_video(info); 2317 failed_video: 2318 savage_unmap_mmio(info); 2319 failed_mmio: 2320 kfree(info->pixmap.addr); 2321 failed_init: 2322 pci_release_regions(dev); 2323 failed_enable: 2324 framebuffer_release(info); 2325 2326 return err; 2327 } 2328 2329 static void savagefb_remove(struct pci_dev *dev) 2330 { 2331 struct fb_info *info = pci_get_drvdata(dev); 2332 2333 DBG("savagefb_remove"); 2334 2335 if (info) { 2336 /* 2337 * If unregister_framebuffer fails, then 2338 * we will be leaving hooks that could cause 2339 * oopsen laying around. 2340 */ 2341 if (unregister_framebuffer(info)) 2342 printk(KERN_WARNING "savagefb: danger danger! " 2343 "Oopsen imminent!\n"); 2344 2345 #ifdef CONFIG_FB_SAVAGE_I2C 2346 savagefb_delete_i2c_busses(info); 2347 #endif 2348 fb_alloc_cmap(&info->cmap, 0, 0); 2349 savage_unmap_video(info); 2350 savage_unmap_mmio(info); 2351 kfree(info->pixmap.addr); 2352 pci_release_regions(dev); 2353 framebuffer_release(info); 2354 } 2355 } 2356 2357 static int savagefb_suspend(struct pci_dev *dev, pm_message_t mesg) 2358 { 2359 struct fb_info *info = pci_get_drvdata(dev); 2360 struct savagefb_par *par = info->par; 2361 2362 DBG("savagefb_suspend"); 2363 2364 if (mesg.event == PM_EVENT_PRETHAW) 2365 mesg.event = PM_EVENT_FREEZE; 2366 par->pm_state = mesg.event; 2367 dev->dev.power.power_state = mesg; 2368 2369 /* 2370 * For PM_EVENT_FREEZE, do not power down so the console 2371 * can remain active. 2372 */ 2373 if (mesg.event == PM_EVENT_FREEZE) 2374 return 0; 2375 2376 console_lock(); 2377 fb_set_suspend(info, 1); 2378 2379 if (info->fbops->fb_sync) 2380 info->fbops->fb_sync(info); 2381 2382 savagefb_blank(FB_BLANK_POWERDOWN, info); 2383 savage_set_default_par(par, &par->save); 2384 savage_disable_mmio(par); 2385 pci_save_state(dev); 2386 pci_disable_device(dev); 2387 pci_set_power_state(dev, pci_choose_state(dev, mesg)); 2388 console_unlock(); 2389 2390 return 0; 2391 } 2392 2393 static int savagefb_resume(struct pci_dev* dev) 2394 { 2395 struct fb_info *info = pci_get_drvdata(dev); 2396 struct savagefb_par *par = info->par; 2397 int cur_state = par->pm_state; 2398 2399 DBG("savage_resume"); 2400 2401 par->pm_state = PM_EVENT_ON; 2402 2403 /* 2404 * The adapter was not powered down coming back from a 2405 * PM_EVENT_FREEZE. 2406 */ 2407 if (cur_state == PM_EVENT_FREEZE) { 2408 pci_set_power_state(dev, PCI_D0); 2409 return 0; 2410 } 2411 2412 console_lock(); 2413 2414 pci_set_power_state(dev, PCI_D0); 2415 pci_restore_state(dev); 2416 2417 if (pci_enable_device(dev)) 2418 DBG("err"); 2419 2420 pci_set_master(dev); 2421 savage_enable_mmio(par); 2422 savage_init_hw(par); 2423 savagefb_set_par(info); 2424 fb_set_suspend(info, 0); 2425 savagefb_blank(FB_BLANK_UNBLANK, info); 2426 console_unlock(); 2427 2428 return 0; 2429 } 2430 2431 2432 static const struct pci_device_id savagefb_devices[] = { 2433 {PCI_VENDOR_ID_S3, PCI_CHIP_SUPSAV_MX128, 2434 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SUPERSAVAGE}, 2435 2436 {PCI_VENDOR_ID_S3, PCI_CHIP_SUPSAV_MX64, 2437 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SUPERSAVAGE}, 2438 2439 {PCI_VENDOR_ID_S3, PCI_CHIP_SUPSAV_MX64C, 2440 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SUPERSAVAGE}, 2441 2442 {PCI_VENDOR_ID_S3, PCI_CHIP_SUPSAV_IX128SDR, 2443 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SUPERSAVAGE}, 2444 2445 {PCI_VENDOR_ID_S3, PCI_CHIP_SUPSAV_IX128DDR, 2446 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SUPERSAVAGE}, 2447 2448 {PCI_VENDOR_ID_S3, PCI_CHIP_SUPSAV_IX64SDR, 2449 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SUPERSAVAGE}, 2450 2451 {PCI_VENDOR_ID_S3, PCI_CHIP_SUPSAV_IX64DDR, 2452 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SUPERSAVAGE}, 2453 2454 {PCI_VENDOR_ID_S3, PCI_CHIP_SUPSAV_IXCSDR, 2455 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SUPERSAVAGE}, 2456 2457 {PCI_VENDOR_ID_S3, PCI_CHIP_SUPSAV_IXCDDR, 2458 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SUPERSAVAGE}, 2459 2460 {PCI_VENDOR_ID_S3, PCI_CHIP_SAVAGE4, 2461 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SAVAGE4}, 2462 2463 {PCI_VENDOR_ID_S3, PCI_CHIP_SAVAGE3D, 2464 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SAVAGE3D}, 2465 2466 {PCI_VENDOR_ID_S3, PCI_CHIP_SAVAGE3D_MV, 2467 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SAVAGE3D_MV}, 2468 2469 {PCI_VENDOR_ID_S3, PCI_CHIP_SAVAGE2000, 2470 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SAVAGE2000}, 2471 2472 {PCI_VENDOR_ID_S3, PCI_CHIP_SAVAGE_MX_MV, 2473 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SAVAGE_MX_MV}, 2474 2475 {PCI_VENDOR_ID_S3, PCI_CHIP_SAVAGE_MX, 2476 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SAVAGE_MX}, 2477 2478 {PCI_VENDOR_ID_S3, PCI_CHIP_SAVAGE_IX_MV, 2479 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SAVAGE_IX_MV}, 2480 2481 {PCI_VENDOR_ID_S3, PCI_CHIP_SAVAGE_IX, 2482 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SAVAGE_IX}, 2483 2484 {PCI_VENDOR_ID_S3, PCI_CHIP_PROSAVAGE_PM, 2485 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_PROSAVAGE_PM}, 2486 2487 {PCI_VENDOR_ID_S3, PCI_CHIP_PROSAVAGE_KM, 2488 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_PROSAVAGE_KM}, 2489 2490 {PCI_VENDOR_ID_S3, PCI_CHIP_S3TWISTER_P, 2491 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_S3TWISTER_P}, 2492 2493 {PCI_VENDOR_ID_S3, PCI_CHIP_S3TWISTER_K, 2494 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_S3TWISTER_K}, 2495 2496 {PCI_VENDOR_ID_S3, PCI_CHIP_PROSAVAGE_DDR, 2497 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_PROSAVAGE_DDR}, 2498 2499 {PCI_VENDOR_ID_S3, PCI_CHIP_PROSAVAGE_DDRK, 2500 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_PROSAVAGE_DDRK}, 2501 2502 {0, 0, 0, 0, 0, 0, 0} 2503 }; 2504 2505 MODULE_DEVICE_TABLE(pci, savagefb_devices); 2506 2507 static struct pci_driver savagefb_driver = { 2508 .name = "savagefb", 2509 .id_table = savagefb_devices, 2510 .probe = savagefb_probe, 2511 .suspend = savagefb_suspend, 2512 .resume = savagefb_resume, 2513 .remove = savagefb_remove, 2514 }; 2515 2516 /* **************************** exit-time only **************************** */ 2517 2518 static void __exit savage_done(void) 2519 { 2520 DBG("savage_done"); 2521 pci_unregister_driver(&savagefb_driver); 2522 } 2523 2524 2525 /* ************************* init in-kernel code ************************** */ 2526 2527 static int __init savagefb_setup(char *options) 2528 { 2529 #ifndef MODULE 2530 char *this_opt; 2531 2532 if (!options || !*options) 2533 return 0; 2534 2535 while ((this_opt = strsep(&options, ",")) != NULL) { 2536 mode_option = this_opt; 2537 } 2538 #endif /* !MODULE */ 2539 return 0; 2540 } 2541 2542 static int __init savagefb_init(void) 2543 { 2544 char *option; 2545 2546 DBG("savagefb_init"); 2547 2548 if (fb_get_options("savagefb", &option)) 2549 return -ENODEV; 2550 2551 savagefb_setup(option); 2552 return pci_register_driver(&savagefb_driver); 2553 2554 } 2555 2556 module_init(savagefb_init); 2557 module_exit(savage_done); 2558 2559 module_param(mode_option, charp, 0); 2560 MODULE_PARM_DESC(mode_option, "Specify initial video mode"); 2561