1 /* 2 * linux/drivers/video/s3fb.c -- Frame buffer device driver for S3 Trio/Virge 3 * 4 * Copyright (c) 2006-2007 Ondrej Zajicek <santiago@crfreenet.org> 5 * 6 * This file is subject to the terms and conditions of the GNU General Public 7 * License. See the file COPYING in the main directory of this archive for 8 * more details. 9 * 10 * Code is based on David Boucher's viafb (http://davesdomain.org.uk/viafb/) 11 * which is based on the code of neofb. 12 */ 13 14 #include <linux/module.h> 15 #include <linux/kernel.h> 16 #include <linux/errno.h> 17 #include <linux/string.h> 18 #include <linux/mm.h> 19 #include <linux/tty.h> 20 #include <linux/delay.h> 21 #include <linux/fb.h> 22 #include <linux/svga.h> 23 #include <linux/init.h> 24 #include <linux/pci.h> 25 #include <linux/console.h> /* Why should fb driver call console functions? because console_lock() */ 26 #include <video/vga.h> 27 28 #include <linux/i2c.h> 29 #include <linux/i2c-algo-bit.h> 30 31 struct s3fb_info { 32 int chip, rev, mclk_freq; 33 int wc_cookie; 34 struct vgastate state; 35 struct mutex open_lock; 36 unsigned int ref_count; 37 u32 pseudo_palette[16]; 38 #ifdef CONFIG_FB_S3_DDC 39 u8 __iomem *mmio; 40 bool ddc_registered; 41 struct i2c_adapter ddc_adapter; 42 struct i2c_algo_bit_data ddc_algo; 43 #endif 44 }; 45 46 47 /* ------------------------------------------------------------------------- */ 48 49 static const struct svga_fb_format s3fb_formats[] = { 50 { 0, {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0}, 0, 51 FB_TYPE_TEXT, FB_AUX_TEXT_SVGA_STEP4, FB_VISUAL_PSEUDOCOLOR, 8, 16}, 52 { 4, {0, 4, 0}, {0, 4, 0}, {0, 4, 0}, {0, 0, 0}, 0, 53 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_PSEUDOCOLOR, 8, 16}, 54 { 4, {0, 4, 0}, {0, 4, 0}, {0, 4, 0}, {0, 0, 0}, 1, 55 FB_TYPE_INTERLEAVED_PLANES, 1, FB_VISUAL_PSEUDOCOLOR, 8, 16}, 56 { 8, {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0}, 0, 57 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_PSEUDOCOLOR, 4, 8}, 58 {16, {10, 5, 0}, {5, 5, 0}, {0, 5, 0}, {0, 0, 0}, 0, 59 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 2, 4}, 60 {16, {11, 5, 0}, {5, 6, 0}, {0, 5, 0}, {0, 0, 0}, 0, 61 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 2, 4}, 62 {24, {16, 8, 0}, {8, 8, 0}, {0, 8, 0}, {0, 0, 0}, 0, 63 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 1, 2}, 64 {32, {16, 8, 0}, {8, 8, 0}, {0, 8, 0}, {0, 0, 0}, 0, 65 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 1, 2}, 66 SVGA_FORMAT_END 67 }; 68 69 70 static const struct svga_pll s3_pll = {3, 129, 3, 33, 0, 3, 71 35000, 240000, 14318}; 72 static const struct svga_pll s3_trio3d_pll = {3, 129, 3, 31, 0, 4, 73 230000, 460000, 14318}; 74 75 static const int s3_memsizes[] = {4096, 0, 3072, 8192, 2048, 6144, 1024, 512}; 76 77 static const char * const s3_names[] = {"S3 Unknown", "S3 Trio32", "S3 Trio64", "S3 Trio64V+", 78 "S3 Trio64UV+", "S3 Trio64V2/DX", "S3 Trio64V2/GX", 79 "S3 Plato/PX", "S3 Aurora64V+", "S3 Virge", 80 "S3 Virge/VX", "S3 Virge/DX", "S3 Virge/GX", 81 "S3 Virge/GX2", "S3 Virge/GX2+", "", 82 "S3 Trio3D/1X", "S3 Trio3D/2X", "S3 Trio3D/2X", 83 "S3 Trio3D", "S3 Virge/MX"}; 84 85 #define CHIP_UNKNOWN 0x00 86 #define CHIP_732_TRIO32 0x01 87 #define CHIP_764_TRIO64 0x02 88 #define CHIP_765_TRIO64VP 0x03 89 #define CHIP_767_TRIO64UVP 0x04 90 #define CHIP_775_TRIO64V2_DX 0x05 91 #define CHIP_785_TRIO64V2_GX 0x06 92 #define CHIP_551_PLATO_PX 0x07 93 #define CHIP_M65_AURORA64VP 0x08 94 #define CHIP_325_VIRGE 0x09 95 #define CHIP_988_VIRGE_VX 0x0A 96 #define CHIP_375_VIRGE_DX 0x0B 97 #define CHIP_385_VIRGE_GX 0x0C 98 #define CHIP_357_VIRGE_GX2 0x0D 99 #define CHIP_359_VIRGE_GX2P 0x0E 100 #define CHIP_360_TRIO3D_1X 0x10 101 #define CHIP_362_TRIO3D_2X 0x11 102 #define CHIP_368_TRIO3D_2X 0x12 103 #define CHIP_365_TRIO3D 0x13 104 #define CHIP_260_VIRGE_MX 0x14 105 106 #define CHIP_XXX_TRIO 0x80 107 #define CHIP_XXX_TRIO64V2_DXGX 0x81 108 #define CHIP_XXX_VIRGE_DXGX 0x82 109 #define CHIP_36X_TRIO3D_1X_2X 0x83 110 111 #define CHIP_UNDECIDED_FLAG 0x80 112 #define CHIP_MASK 0xFF 113 114 #define MMIO_OFFSET 0x1000000 115 #define MMIO_SIZE 0x10000 116 117 /* CRT timing register sets */ 118 119 static const struct vga_regset s3_h_total_regs[] = {{0x00, 0, 7}, {0x5D, 0, 0}, VGA_REGSET_END}; 120 static const struct vga_regset s3_h_display_regs[] = {{0x01, 0, 7}, {0x5D, 1, 1}, VGA_REGSET_END}; 121 static const struct vga_regset s3_h_blank_start_regs[] = {{0x02, 0, 7}, {0x5D, 2, 2}, VGA_REGSET_END}; 122 static const struct vga_regset s3_h_blank_end_regs[] = {{0x03, 0, 4}, {0x05, 7, 7}, VGA_REGSET_END}; 123 static const struct vga_regset s3_h_sync_start_regs[] = {{0x04, 0, 7}, {0x5D, 4, 4}, VGA_REGSET_END}; 124 static const struct vga_regset s3_h_sync_end_regs[] = {{0x05, 0, 4}, VGA_REGSET_END}; 125 126 static const struct vga_regset s3_v_total_regs[] = {{0x06, 0, 7}, {0x07, 0, 0}, {0x07, 5, 5}, {0x5E, 0, 0}, VGA_REGSET_END}; 127 static const struct vga_regset s3_v_display_regs[] = {{0x12, 0, 7}, {0x07, 1, 1}, {0x07, 6, 6}, {0x5E, 1, 1}, VGA_REGSET_END}; 128 static const struct vga_regset s3_v_blank_start_regs[] = {{0x15, 0, 7}, {0x07, 3, 3}, {0x09, 5, 5}, {0x5E, 2, 2}, VGA_REGSET_END}; 129 static const struct vga_regset s3_v_blank_end_regs[] = {{0x16, 0, 7}, VGA_REGSET_END}; 130 static const struct vga_regset s3_v_sync_start_regs[] = {{0x10, 0, 7}, {0x07, 2, 2}, {0x07, 7, 7}, {0x5E, 4, 4}, VGA_REGSET_END}; 131 static const struct vga_regset s3_v_sync_end_regs[] = {{0x11, 0, 3}, VGA_REGSET_END}; 132 133 static const struct vga_regset s3_line_compare_regs[] = {{0x18, 0, 7}, {0x07, 4, 4}, {0x09, 6, 6}, {0x5E, 6, 6}, VGA_REGSET_END}; 134 static const struct vga_regset s3_start_address_regs[] = {{0x0d, 0, 7}, {0x0c, 0, 7}, {0x69, 0, 4}, VGA_REGSET_END}; 135 static const struct vga_regset s3_offset_regs[] = {{0x13, 0, 7}, {0x51, 4, 5}, VGA_REGSET_END}; /* set 0x43 bit 2 to 0 */ 136 137 static const struct vga_regset s3_dtpc_regs[] = {{0x3B, 0, 7}, {0x5D, 6, 6}, VGA_REGSET_END}; 138 139 static const struct svga_timing_regs s3_timing_regs = { 140 s3_h_total_regs, s3_h_display_regs, s3_h_blank_start_regs, 141 s3_h_blank_end_regs, s3_h_sync_start_regs, s3_h_sync_end_regs, 142 s3_v_total_regs, s3_v_display_regs, s3_v_blank_start_regs, 143 s3_v_blank_end_regs, s3_v_sync_start_regs, s3_v_sync_end_regs, 144 }; 145 146 147 /* ------------------------------------------------------------------------- */ 148 149 /* Module parameters */ 150 151 152 static char *mode_option; 153 static int mtrr = 1; 154 static int fasttext = 1; 155 156 157 MODULE_AUTHOR("(c) 2006-2007 Ondrej Zajicek <santiago@crfreenet.org>"); 158 MODULE_LICENSE("GPL"); 159 MODULE_DESCRIPTION("fbdev driver for S3 Trio/Virge"); 160 161 module_param(mode_option, charp, 0444); 162 MODULE_PARM_DESC(mode_option, "Default video mode ('640x480-8@60', etc)"); 163 module_param_named(mode, mode_option, charp, 0444); 164 MODULE_PARM_DESC(mode, "Default video mode ('640x480-8@60', etc) (deprecated)"); 165 module_param(mtrr, int, 0444); 166 MODULE_PARM_DESC(mtrr, "Enable write-combining with MTRR (1=enable, 0=disable, default=1)"); 167 168 module_param(fasttext, int, 0644); 169 MODULE_PARM_DESC(fasttext, "Enable S3 fast text mode (1=enable, 0=disable, default=1)"); 170 171 172 /* ------------------------------------------------------------------------- */ 173 174 #ifdef CONFIG_FB_S3_DDC 175 176 #define DDC_REG 0xaa /* Trio 3D/1X/2X */ 177 #define DDC_MMIO_REG 0xff20 /* all other chips */ 178 #define DDC_SCL_OUT (1 << 0) 179 #define DDC_SDA_OUT (1 << 1) 180 #define DDC_SCL_IN (1 << 2) 181 #define DDC_SDA_IN (1 << 3) 182 #define DDC_DRIVE_EN (1 << 4) 183 184 static bool s3fb_ddc_needs_mmio(int chip) 185 { 186 return !(chip == CHIP_360_TRIO3D_1X || 187 chip == CHIP_362_TRIO3D_2X || 188 chip == CHIP_368_TRIO3D_2X); 189 } 190 191 static u8 s3fb_ddc_read(struct s3fb_info *par) 192 { 193 if (s3fb_ddc_needs_mmio(par->chip)) 194 return readb(par->mmio + DDC_MMIO_REG); 195 else 196 return vga_rcrt(par->state.vgabase, DDC_REG); 197 } 198 199 static void s3fb_ddc_write(struct s3fb_info *par, u8 val) 200 { 201 if (s3fb_ddc_needs_mmio(par->chip)) 202 writeb(val, par->mmio + DDC_MMIO_REG); 203 else 204 vga_wcrt(par->state.vgabase, DDC_REG, val); 205 } 206 207 static void s3fb_ddc_setscl(void *data, int val) 208 { 209 struct s3fb_info *par = data; 210 unsigned char reg; 211 212 reg = s3fb_ddc_read(par) | DDC_DRIVE_EN; 213 if (val) 214 reg |= DDC_SCL_OUT; 215 else 216 reg &= ~DDC_SCL_OUT; 217 s3fb_ddc_write(par, reg); 218 } 219 220 static void s3fb_ddc_setsda(void *data, int val) 221 { 222 struct s3fb_info *par = data; 223 unsigned char reg; 224 225 reg = s3fb_ddc_read(par) | DDC_DRIVE_EN; 226 if (val) 227 reg |= DDC_SDA_OUT; 228 else 229 reg &= ~DDC_SDA_OUT; 230 s3fb_ddc_write(par, reg); 231 } 232 233 static int s3fb_ddc_getscl(void *data) 234 { 235 struct s3fb_info *par = data; 236 237 return !!(s3fb_ddc_read(par) & DDC_SCL_IN); 238 } 239 240 static int s3fb_ddc_getsda(void *data) 241 { 242 struct s3fb_info *par = data; 243 244 return !!(s3fb_ddc_read(par) & DDC_SDA_IN); 245 } 246 247 static int s3fb_setup_ddc_bus(struct fb_info *info) 248 { 249 struct s3fb_info *par = info->par; 250 251 strscpy(par->ddc_adapter.name, info->fix.id, 252 sizeof(par->ddc_adapter.name)); 253 par->ddc_adapter.owner = THIS_MODULE; 254 par->ddc_adapter.class = I2C_CLASS_DDC; 255 par->ddc_adapter.algo_data = &par->ddc_algo; 256 par->ddc_adapter.dev.parent = info->device; 257 par->ddc_algo.setsda = s3fb_ddc_setsda; 258 par->ddc_algo.setscl = s3fb_ddc_setscl; 259 par->ddc_algo.getsda = s3fb_ddc_getsda; 260 par->ddc_algo.getscl = s3fb_ddc_getscl; 261 par->ddc_algo.udelay = 10; 262 par->ddc_algo.timeout = 20; 263 par->ddc_algo.data = par; 264 265 i2c_set_adapdata(&par->ddc_adapter, par); 266 267 /* 268 * some Virge cards have external MUX to switch chip I2C bus between 269 * DDC and extension pins - switch it do DDC 270 */ 271 /* vga_wseq(par->state.vgabase, 0x08, 0x06); - not needed, already unlocked */ 272 if (par->chip == CHIP_357_VIRGE_GX2 || 273 par->chip == CHIP_359_VIRGE_GX2P || 274 par->chip == CHIP_260_VIRGE_MX) 275 svga_wseq_mask(par->state.vgabase, 0x0d, 0x01, 0x03); 276 else 277 svga_wseq_mask(par->state.vgabase, 0x0d, 0x00, 0x03); 278 /* some Virge need this or the DDC is ignored */ 279 svga_wcrt_mask(par->state.vgabase, 0x5c, 0x03, 0x03); 280 281 return i2c_bit_add_bus(&par->ddc_adapter); 282 } 283 #endif /* CONFIG_FB_S3_DDC */ 284 285 286 /* ------------------------------------------------------------------------- */ 287 288 /* Set font in S3 fast text mode */ 289 290 static void s3fb_settile_fast(struct fb_info *info, struct fb_tilemap *map) 291 { 292 const u8 *font = map->data; 293 u8 __iomem *fb = (u8 __iomem *) info->screen_base; 294 int i, c; 295 296 if ((map->width != 8) || (map->height != 16) || 297 (map->depth != 1) || (map->length != 256)) { 298 fb_err(info, "unsupported font parameters: width %d, height %d, depth %d, length %d\n", 299 map->width, map->height, map->depth, map->length); 300 return; 301 } 302 303 fb += 2; 304 for (i = 0; i < map->height; i++) { 305 for (c = 0; c < map->length; c++) { 306 fb_writeb(font[c * map->height + i], fb + c * 4); 307 } 308 fb += 1024; 309 } 310 } 311 312 static void s3fb_tilecursor(struct fb_info *info, struct fb_tilecursor *cursor) 313 { 314 struct s3fb_info *par = info->par; 315 316 svga_tilecursor(par->state.vgabase, info, cursor); 317 } 318 319 static struct fb_tile_ops s3fb_tile_ops = { 320 .fb_settile = svga_settile, 321 .fb_tilecopy = svga_tilecopy, 322 .fb_tilefill = svga_tilefill, 323 .fb_tileblit = svga_tileblit, 324 .fb_tilecursor = s3fb_tilecursor, 325 .fb_get_tilemax = svga_get_tilemax, 326 }; 327 328 static struct fb_tile_ops s3fb_fast_tile_ops = { 329 .fb_settile = s3fb_settile_fast, 330 .fb_tilecopy = svga_tilecopy, 331 .fb_tilefill = svga_tilefill, 332 .fb_tileblit = svga_tileblit, 333 .fb_tilecursor = s3fb_tilecursor, 334 .fb_get_tilemax = svga_get_tilemax, 335 }; 336 337 338 /* ------------------------------------------------------------------------- */ 339 340 /* image data is MSB-first, fb structure is MSB-first too */ 341 static inline u32 expand_color(u32 c) 342 { 343 return ((c & 1) | ((c & 2) << 7) | ((c & 4) << 14) | ((c & 8) << 21)) * 0xFF; 344 } 345 346 /* s3fb_iplan_imageblit silently assumes that almost everything is 8-pixel aligned */ 347 static void s3fb_iplan_imageblit(struct fb_info *info, const struct fb_image *image) 348 { 349 u32 fg = expand_color(image->fg_color); 350 u32 bg = expand_color(image->bg_color); 351 const u8 *src1, *src; 352 u8 __iomem *dst1; 353 u32 __iomem *dst; 354 u32 val; 355 int x, y; 356 357 src1 = image->data; 358 dst1 = info->screen_base + (image->dy * info->fix.line_length) 359 + ((image->dx / 8) * 4); 360 361 for (y = 0; y < image->height; y++) { 362 src = src1; 363 dst = (u32 __iomem *) dst1; 364 for (x = 0; x < image->width; x += 8) { 365 val = *(src++) * 0x01010101; 366 val = (val & fg) | (~val & bg); 367 fb_writel(val, dst++); 368 } 369 src1 += image->width / 8; 370 dst1 += info->fix.line_length; 371 } 372 373 } 374 375 /* s3fb_iplan_fillrect silently assumes that almost everything is 8-pixel aligned */ 376 static void s3fb_iplan_fillrect(struct fb_info *info, const struct fb_fillrect *rect) 377 { 378 u32 fg = expand_color(rect->color); 379 u8 __iomem *dst1; 380 u32 __iomem *dst; 381 int x, y; 382 383 dst1 = info->screen_base + (rect->dy * info->fix.line_length) 384 + ((rect->dx / 8) * 4); 385 386 for (y = 0; y < rect->height; y++) { 387 dst = (u32 __iomem *) dst1; 388 for (x = 0; x < rect->width; x += 8) { 389 fb_writel(fg, dst++); 390 } 391 dst1 += info->fix.line_length; 392 } 393 } 394 395 396 /* image data is MSB-first, fb structure is high-nibble-in-low-byte-first */ 397 static inline u32 expand_pixel(u32 c) 398 { 399 return (((c & 1) << 24) | ((c & 2) << 27) | ((c & 4) << 14) | ((c & 8) << 17) | 400 ((c & 16) << 4) | ((c & 32) << 7) | ((c & 64) >> 6) | ((c & 128) >> 3)) * 0xF; 401 } 402 403 /* s3fb_cfb4_imageblit silently assumes that almost everything is 8-pixel aligned */ 404 static void s3fb_cfb4_imageblit(struct fb_info *info, const struct fb_image *image) 405 { 406 u32 fg = image->fg_color * 0x11111111; 407 u32 bg = image->bg_color * 0x11111111; 408 const u8 *src1, *src; 409 u8 __iomem *dst1; 410 u32 __iomem *dst; 411 u32 val; 412 int x, y; 413 414 src1 = image->data; 415 dst1 = info->screen_base + (image->dy * info->fix.line_length) 416 + ((image->dx / 8) * 4); 417 418 for (y = 0; y < image->height; y++) { 419 src = src1; 420 dst = (u32 __iomem *) dst1; 421 for (x = 0; x < image->width; x += 8) { 422 val = expand_pixel(*(src++)); 423 val = (val & fg) | (~val & bg); 424 fb_writel(val, dst++); 425 } 426 src1 += image->width / 8; 427 dst1 += info->fix.line_length; 428 } 429 } 430 431 static void s3fb_imageblit(struct fb_info *info, const struct fb_image *image) 432 { 433 if ((info->var.bits_per_pixel == 4) && (image->depth == 1) 434 && ((image->width % 8) == 0) && ((image->dx % 8) == 0)) { 435 if (info->fix.type == FB_TYPE_INTERLEAVED_PLANES) 436 s3fb_iplan_imageblit(info, image); 437 else 438 s3fb_cfb4_imageblit(info, image); 439 } else 440 cfb_imageblit(info, image); 441 } 442 443 static void s3fb_fillrect(struct fb_info *info, const struct fb_fillrect *rect) 444 { 445 if ((info->var.bits_per_pixel == 4) 446 && ((rect->width % 8) == 0) && ((rect->dx % 8) == 0) 447 && (info->fix.type == FB_TYPE_INTERLEAVED_PLANES)) 448 s3fb_iplan_fillrect(info, rect); 449 else 450 cfb_fillrect(info, rect); 451 } 452 453 454 455 /* ------------------------------------------------------------------------- */ 456 457 458 static void s3_set_pixclock(struct fb_info *info, u32 pixclock) 459 { 460 struct s3fb_info *par = info->par; 461 u16 m, n, r; 462 u8 regval; 463 int rv; 464 465 rv = svga_compute_pll((par->chip == CHIP_365_TRIO3D) ? &s3_trio3d_pll : &s3_pll, 466 1000000000 / pixclock, &m, &n, &r, info->node); 467 if (rv < 0) { 468 fb_err(info, "cannot set requested pixclock, keeping old value\n"); 469 return; 470 } 471 472 /* Set VGA misc register */ 473 regval = vga_r(par->state.vgabase, VGA_MIS_R); 474 vga_w(par->state.vgabase, VGA_MIS_W, regval | VGA_MIS_ENB_PLL_LOAD); 475 476 /* Set S3 clock registers */ 477 if (par->chip == CHIP_357_VIRGE_GX2 || 478 par->chip == CHIP_359_VIRGE_GX2P || 479 par->chip == CHIP_360_TRIO3D_1X || 480 par->chip == CHIP_362_TRIO3D_2X || 481 par->chip == CHIP_368_TRIO3D_2X || 482 par->chip == CHIP_260_VIRGE_MX) { 483 vga_wseq(par->state.vgabase, 0x12, (n - 2) | ((r & 3) << 6)); /* n and two bits of r */ 484 vga_wseq(par->state.vgabase, 0x29, r >> 2); /* remaining highest bit of r */ 485 } else 486 vga_wseq(par->state.vgabase, 0x12, (n - 2) | (r << 5)); 487 vga_wseq(par->state.vgabase, 0x13, m - 2); 488 489 udelay(1000); 490 491 /* Activate clock - write 0, 1, 0 to seq/15 bit 5 */ 492 regval = vga_rseq (par->state.vgabase, 0x15); /* | 0x80; */ 493 vga_wseq(par->state.vgabase, 0x15, regval & ~(1<<5)); 494 vga_wseq(par->state.vgabase, 0x15, regval | (1<<5)); 495 vga_wseq(par->state.vgabase, 0x15, regval & ~(1<<5)); 496 } 497 498 499 /* Open framebuffer */ 500 501 static int s3fb_open(struct fb_info *info, int user) 502 { 503 struct s3fb_info *par = info->par; 504 505 mutex_lock(&(par->open_lock)); 506 if (par->ref_count == 0) { 507 void __iomem *vgabase = par->state.vgabase; 508 509 memset(&(par->state), 0, sizeof(struct vgastate)); 510 par->state.vgabase = vgabase; 511 par->state.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS | VGA_SAVE_CMAP; 512 par->state.num_crtc = 0x70; 513 par->state.num_seq = 0x20; 514 save_vga(&(par->state)); 515 } 516 517 par->ref_count++; 518 mutex_unlock(&(par->open_lock)); 519 520 return 0; 521 } 522 523 /* Close framebuffer */ 524 525 static int s3fb_release(struct fb_info *info, int user) 526 { 527 struct s3fb_info *par = info->par; 528 529 mutex_lock(&(par->open_lock)); 530 if (par->ref_count == 0) { 531 mutex_unlock(&(par->open_lock)); 532 return -EINVAL; 533 } 534 535 if (par->ref_count == 1) 536 restore_vga(&(par->state)); 537 538 par->ref_count--; 539 mutex_unlock(&(par->open_lock)); 540 541 return 0; 542 } 543 544 /* Validate passed in var */ 545 546 static int s3fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) 547 { 548 struct s3fb_info *par = info->par; 549 int rv, mem, step; 550 u16 m, n, r; 551 552 if (!var->pixclock) 553 return -EINVAL; 554 555 /* Find appropriate format */ 556 rv = svga_match_format (s3fb_formats, var, NULL); 557 558 /* 32bpp mode is not supported on VIRGE VX, 559 24bpp is not supported on others */ 560 if ((par->chip == CHIP_988_VIRGE_VX) ? (rv == 7) : (rv == 6)) 561 rv = -EINVAL; 562 563 if (rv < 0) { 564 fb_err(info, "unsupported mode requested\n"); 565 return rv; 566 } 567 568 /* Do not allow to have real resoulution larger than virtual */ 569 if (var->xres > var->xres_virtual) 570 var->xres_virtual = var->xres; 571 572 if (var->yres > var->yres_virtual) 573 var->yres_virtual = var->yres; 574 575 /* Round up xres_virtual to have proper alignment of lines */ 576 step = s3fb_formats[rv].xresstep - 1; 577 var->xres_virtual = (var->xres_virtual+step) & ~step; 578 579 /* Check whether have enough memory */ 580 mem = ((var->bits_per_pixel * var->xres_virtual) >> 3) * var->yres_virtual; 581 if (mem > info->screen_size) { 582 fb_err(info, "not enough framebuffer memory (%d kB requested , %u kB available)\n", 583 mem >> 10, (unsigned int) (info->screen_size >> 10)); 584 return -EINVAL; 585 } 586 587 rv = svga_check_timings (&s3_timing_regs, var, info->node); 588 if (rv < 0) { 589 fb_err(info, "invalid timings requested\n"); 590 return rv; 591 } 592 593 rv = svga_compute_pll(&s3_pll, PICOS2KHZ(var->pixclock), &m, &n, &r, 594 info->node); 595 if (rv < 0) { 596 fb_err(info, "invalid pixclock value requested\n"); 597 return rv; 598 } 599 600 return 0; 601 } 602 603 /* Set video mode from par */ 604 605 static int s3fb_set_par(struct fb_info *info) 606 { 607 struct s3fb_info *par = info->par; 608 u32 value, mode, hmul, offset_value, screen_size, multiplex, dbytes; 609 u32 bpp = info->var.bits_per_pixel; 610 u32 htotal, hsstart; 611 612 if (bpp != 0) { 613 info->fix.ypanstep = 1; 614 info->fix.line_length = (info->var.xres_virtual * bpp) / 8; 615 616 info->flags &= ~FBINFO_MISC_TILEBLITTING; 617 info->tileops = NULL; 618 619 /* in 4bpp supports 8p wide tiles only, any tiles otherwise */ 620 info->pixmap.blit_x = (bpp == 4) ? (1 << (8 - 1)) : (~(u32)0); 621 info->pixmap.blit_y = ~(u32)0; 622 623 offset_value = (info->var.xres_virtual * bpp) / 64; 624 screen_size = info->var.yres_virtual * info->fix.line_length; 625 } else { 626 info->fix.ypanstep = 16; 627 info->fix.line_length = 0; 628 629 info->flags |= FBINFO_MISC_TILEBLITTING; 630 info->tileops = fasttext ? &s3fb_fast_tile_ops : &s3fb_tile_ops; 631 632 /* supports 8x16 tiles only */ 633 info->pixmap.blit_x = 1 << (8 - 1); 634 info->pixmap.blit_y = 1 << (16 - 1); 635 636 offset_value = info->var.xres_virtual / 16; 637 screen_size = (info->var.xres_virtual * info->var.yres_virtual) / 64; 638 } 639 640 info->var.xoffset = 0; 641 info->var.yoffset = 0; 642 info->var.activate = FB_ACTIVATE_NOW; 643 644 /* Unlock registers */ 645 vga_wcrt(par->state.vgabase, 0x38, 0x48); 646 vga_wcrt(par->state.vgabase, 0x39, 0xA5); 647 vga_wseq(par->state.vgabase, 0x08, 0x06); 648 svga_wcrt_mask(par->state.vgabase, 0x11, 0x00, 0x80); 649 650 /* Blank screen and turn off sync */ 651 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); 652 svga_wcrt_mask(par->state.vgabase, 0x17, 0x00, 0x80); 653 654 /* Set default values */ 655 svga_set_default_gfx_regs(par->state.vgabase); 656 svga_set_default_atc_regs(par->state.vgabase); 657 svga_set_default_seq_regs(par->state.vgabase); 658 svga_set_default_crt_regs(par->state.vgabase); 659 svga_wcrt_multi(par->state.vgabase, s3_line_compare_regs, 0xFFFFFFFF); 660 svga_wcrt_multi(par->state.vgabase, s3_start_address_regs, 0); 661 662 /* S3 specific initialization */ 663 svga_wcrt_mask(par->state.vgabase, 0x58, 0x10, 0x10); /* enable linear framebuffer */ 664 svga_wcrt_mask(par->state.vgabase, 0x31, 0x08, 0x08); /* enable sequencer access to framebuffer above 256 kB */ 665 666 /* svga_wcrt_mask(par->state.vgabase, 0x33, 0x08, 0x08); */ /* DDR ? */ 667 /* svga_wcrt_mask(par->state.vgabase, 0x43, 0x01, 0x01); */ /* DDR ? */ 668 svga_wcrt_mask(par->state.vgabase, 0x33, 0x00, 0x08); /* no DDR ? */ 669 svga_wcrt_mask(par->state.vgabase, 0x43, 0x00, 0x01); /* no DDR ? */ 670 671 svga_wcrt_mask(par->state.vgabase, 0x5D, 0x00, 0x28); /* Clear strange HSlen bits */ 672 673 /* svga_wcrt_mask(par->state.vgabase, 0x58, 0x03, 0x03); */ 674 675 /* svga_wcrt_mask(par->state.vgabase, 0x53, 0x12, 0x13); */ /* enable MMIO */ 676 /* svga_wcrt_mask(par->state.vgabase, 0x40, 0x08, 0x08); */ /* enable write buffer */ 677 678 679 /* Set the offset register */ 680 fb_dbg(info, "offset register : %d\n", offset_value); 681 svga_wcrt_multi(par->state.vgabase, s3_offset_regs, offset_value); 682 683 if (par->chip != CHIP_357_VIRGE_GX2 && 684 par->chip != CHIP_359_VIRGE_GX2P && 685 par->chip != CHIP_360_TRIO3D_1X && 686 par->chip != CHIP_362_TRIO3D_2X && 687 par->chip != CHIP_368_TRIO3D_2X && 688 par->chip != CHIP_260_VIRGE_MX) { 689 vga_wcrt(par->state.vgabase, 0x54, 0x18); /* M parameter */ 690 vga_wcrt(par->state.vgabase, 0x60, 0xff); /* N parameter */ 691 vga_wcrt(par->state.vgabase, 0x61, 0xff); /* L parameter */ 692 vga_wcrt(par->state.vgabase, 0x62, 0xff); /* L parameter */ 693 } 694 695 vga_wcrt(par->state.vgabase, 0x3A, 0x35); 696 svga_wattr(par->state.vgabase, 0x33, 0x00); 697 698 if (info->var.vmode & FB_VMODE_DOUBLE) 699 svga_wcrt_mask(par->state.vgabase, 0x09, 0x80, 0x80); 700 else 701 svga_wcrt_mask(par->state.vgabase, 0x09, 0x00, 0x80); 702 703 if (info->var.vmode & FB_VMODE_INTERLACED) 704 svga_wcrt_mask(par->state.vgabase, 0x42, 0x20, 0x20); 705 else 706 svga_wcrt_mask(par->state.vgabase, 0x42, 0x00, 0x20); 707 708 /* Disable hardware graphics cursor */ 709 svga_wcrt_mask(par->state.vgabase, 0x45, 0x00, 0x01); 710 /* Disable Streams engine */ 711 svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0x0C); 712 713 mode = svga_match_format(s3fb_formats, &(info->var), &(info->fix)); 714 715 /* S3 virge DX hack */ 716 if (par->chip == CHIP_375_VIRGE_DX) { 717 vga_wcrt(par->state.vgabase, 0x86, 0x80); 718 vga_wcrt(par->state.vgabase, 0x90, 0x00); 719 } 720 721 /* S3 virge VX hack */ 722 if (par->chip == CHIP_988_VIRGE_VX) { 723 vga_wcrt(par->state.vgabase, 0x50, 0x00); 724 vga_wcrt(par->state.vgabase, 0x67, 0x50); 725 msleep(10); /* screen remains blank sometimes without this */ 726 vga_wcrt(par->state.vgabase, 0x63, (mode <= 2) ? 0x90 : 0x09); 727 vga_wcrt(par->state.vgabase, 0x66, 0x90); 728 } 729 730 if (par->chip == CHIP_357_VIRGE_GX2 || 731 par->chip == CHIP_359_VIRGE_GX2P || 732 par->chip == CHIP_360_TRIO3D_1X || 733 par->chip == CHIP_362_TRIO3D_2X || 734 par->chip == CHIP_368_TRIO3D_2X || 735 par->chip == CHIP_365_TRIO3D || 736 par->chip == CHIP_375_VIRGE_DX || 737 par->chip == CHIP_385_VIRGE_GX || 738 par->chip == CHIP_260_VIRGE_MX) { 739 dbytes = info->var.xres * ((bpp+7)/8); 740 vga_wcrt(par->state.vgabase, 0x91, (dbytes + 7) / 8); 741 vga_wcrt(par->state.vgabase, 0x90, (((dbytes + 7) / 8) >> 8) | 0x80); 742 743 vga_wcrt(par->state.vgabase, 0x66, 0x81); 744 } 745 746 if (par->chip == CHIP_357_VIRGE_GX2 || 747 par->chip == CHIP_359_VIRGE_GX2P || 748 par->chip == CHIP_360_TRIO3D_1X || 749 par->chip == CHIP_362_TRIO3D_2X || 750 par->chip == CHIP_368_TRIO3D_2X || 751 par->chip == CHIP_260_VIRGE_MX) 752 vga_wcrt(par->state.vgabase, 0x34, 0x00); 753 else /* enable Data Transfer Position Control (DTPC) */ 754 vga_wcrt(par->state.vgabase, 0x34, 0x10); 755 756 svga_wcrt_mask(par->state.vgabase, 0x31, 0x00, 0x40); 757 multiplex = 0; 758 hmul = 1; 759 760 /* Set mode-specific register values */ 761 switch (mode) { 762 case 0: 763 fb_dbg(info, "text mode\n"); 764 svga_set_textmode_vga_regs(par->state.vgabase); 765 766 /* Set additional registers like in 8-bit mode */ 767 svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30); 768 svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0); 769 770 /* Disable enhanced mode */ 771 svga_wcrt_mask(par->state.vgabase, 0x3A, 0x00, 0x30); 772 773 if (fasttext) { 774 fb_dbg(info, "high speed text mode set\n"); 775 svga_wcrt_mask(par->state.vgabase, 0x31, 0x40, 0x40); 776 } 777 break; 778 case 1: 779 fb_dbg(info, "4 bit pseudocolor\n"); 780 vga_wgfx(par->state.vgabase, VGA_GFX_MODE, 0x40); 781 782 /* Set additional registers like in 8-bit mode */ 783 svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30); 784 svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0); 785 786 /* disable enhanced mode */ 787 svga_wcrt_mask(par->state.vgabase, 0x3A, 0x00, 0x30); 788 break; 789 case 2: 790 fb_dbg(info, "4 bit pseudocolor, planar\n"); 791 792 /* Set additional registers like in 8-bit mode */ 793 svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30); 794 svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0); 795 796 /* disable enhanced mode */ 797 svga_wcrt_mask(par->state.vgabase, 0x3A, 0x00, 0x30); 798 break; 799 case 3: 800 fb_dbg(info, "8 bit pseudocolor\n"); 801 svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30); 802 if (info->var.pixclock > 20000 || 803 par->chip == CHIP_357_VIRGE_GX2 || 804 par->chip == CHIP_359_VIRGE_GX2P || 805 par->chip == CHIP_360_TRIO3D_1X || 806 par->chip == CHIP_362_TRIO3D_2X || 807 par->chip == CHIP_368_TRIO3D_2X || 808 par->chip == CHIP_260_VIRGE_MX) 809 svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0); 810 else { 811 svga_wcrt_mask(par->state.vgabase, 0x67, 0x10, 0xF0); 812 multiplex = 1; 813 } 814 break; 815 case 4: 816 fb_dbg(info, "5/5/5 truecolor\n"); 817 if (par->chip == CHIP_988_VIRGE_VX) { 818 if (info->var.pixclock > 20000) 819 svga_wcrt_mask(par->state.vgabase, 0x67, 0x20, 0xF0); 820 else 821 svga_wcrt_mask(par->state.vgabase, 0x67, 0x30, 0xF0); 822 } else if (par->chip == CHIP_365_TRIO3D) { 823 svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30); 824 if (info->var.pixclock > 8695) { 825 svga_wcrt_mask(par->state.vgabase, 0x67, 0x30, 0xF0); 826 hmul = 2; 827 } else { 828 svga_wcrt_mask(par->state.vgabase, 0x67, 0x20, 0xF0); 829 multiplex = 1; 830 } 831 } else { 832 svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30); 833 svga_wcrt_mask(par->state.vgabase, 0x67, 0x30, 0xF0); 834 if (par->chip != CHIP_357_VIRGE_GX2 && 835 par->chip != CHIP_359_VIRGE_GX2P && 836 par->chip != CHIP_360_TRIO3D_1X && 837 par->chip != CHIP_362_TRIO3D_2X && 838 par->chip != CHIP_368_TRIO3D_2X && 839 par->chip != CHIP_260_VIRGE_MX) 840 hmul = 2; 841 } 842 break; 843 case 5: 844 fb_dbg(info, "5/6/5 truecolor\n"); 845 if (par->chip == CHIP_988_VIRGE_VX) { 846 if (info->var.pixclock > 20000) 847 svga_wcrt_mask(par->state.vgabase, 0x67, 0x40, 0xF0); 848 else 849 svga_wcrt_mask(par->state.vgabase, 0x67, 0x50, 0xF0); 850 } else if (par->chip == CHIP_365_TRIO3D) { 851 svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30); 852 if (info->var.pixclock > 8695) { 853 svga_wcrt_mask(par->state.vgabase, 0x67, 0x50, 0xF0); 854 hmul = 2; 855 } else { 856 svga_wcrt_mask(par->state.vgabase, 0x67, 0x40, 0xF0); 857 multiplex = 1; 858 } 859 } else { 860 svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30); 861 svga_wcrt_mask(par->state.vgabase, 0x67, 0x50, 0xF0); 862 if (par->chip != CHIP_357_VIRGE_GX2 && 863 par->chip != CHIP_359_VIRGE_GX2P && 864 par->chip != CHIP_360_TRIO3D_1X && 865 par->chip != CHIP_362_TRIO3D_2X && 866 par->chip != CHIP_368_TRIO3D_2X && 867 par->chip != CHIP_260_VIRGE_MX) 868 hmul = 2; 869 } 870 break; 871 case 6: 872 /* VIRGE VX case */ 873 fb_dbg(info, "8/8/8 truecolor\n"); 874 svga_wcrt_mask(par->state.vgabase, 0x67, 0xD0, 0xF0); 875 break; 876 case 7: 877 fb_dbg(info, "8/8/8/8 truecolor\n"); 878 svga_wcrt_mask(par->state.vgabase, 0x50, 0x30, 0x30); 879 svga_wcrt_mask(par->state.vgabase, 0x67, 0xD0, 0xF0); 880 break; 881 default: 882 fb_err(info, "unsupported mode - bug\n"); 883 return -EINVAL; 884 } 885 886 if (par->chip != CHIP_988_VIRGE_VX) { 887 svga_wseq_mask(par->state.vgabase, 0x15, multiplex ? 0x10 : 0x00, 0x10); 888 svga_wseq_mask(par->state.vgabase, 0x18, multiplex ? 0x80 : 0x00, 0x80); 889 } 890 891 s3_set_pixclock(info, info->var.pixclock); 892 svga_set_timings(par->state.vgabase, &s3_timing_regs, &(info->var), hmul, 1, 893 (info->var.vmode & FB_VMODE_DOUBLE) ? 2 : 1, 894 (info->var.vmode & FB_VMODE_INTERLACED) ? 2 : 1, 895 hmul, info->node); 896 897 /* Set interlaced mode start/end register */ 898 htotal = info->var.xres + info->var.left_margin + info->var.right_margin + info->var.hsync_len; 899 htotal = ((htotal * hmul) / 8) - 5; 900 vga_wcrt(par->state.vgabase, 0x3C, (htotal + 1) / 2); 901 902 /* Set Data Transfer Position */ 903 hsstart = ((info->var.xres + info->var.right_margin) * hmul) / 8; 904 /* + 2 is needed for Virge/VX, does no harm on other cards */ 905 value = clamp((htotal + hsstart + 1) / 2 + 2, hsstart + 4, htotal + 1); 906 svga_wcrt_multi(par->state.vgabase, s3_dtpc_regs, value); 907 908 if (screen_size > info->screen_size) 909 screen_size = info->screen_size; 910 memset_io(info->screen_base, 0x00, screen_size); 911 /* Device and screen back on */ 912 svga_wcrt_mask(par->state.vgabase, 0x17, 0x80, 0x80); 913 svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20); 914 915 return 0; 916 } 917 918 /* Set a colour register */ 919 920 static int s3fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, 921 u_int transp, struct fb_info *fb) 922 { 923 switch (fb->var.bits_per_pixel) { 924 case 0: 925 case 4: 926 if (regno >= 16) 927 return -EINVAL; 928 929 if ((fb->var.bits_per_pixel == 4) && 930 (fb->var.nonstd == 0)) { 931 outb(0xF0, VGA_PEL_MSK); 932 outb(regno*16, VGA_PEL_IW); 933 } else { 934 outb(0x0F, VGA_PEL_MSK); 935 outb(regno, VGA_PEL_IW); 936 } 937 outb(red >> 10, VGA_PEL_D); 938 outb(green >> 10, VGA_PEL_D); 939 outb(blue >> 10, VGA_PEL_D); 940 break; 941 case 8: 942 if (regno >= 256) 943 return -EINVAL; 944 945 outb(0xFF, VGA_PEL_MSK); 946 outb(regno, VGA_PEL_IW); 947 outb(red >> 10, VGA_PEL_D); 948 outb(green >> 10, VGA_PEL_D); 949 outb(blue >> 10, VGA_PEL_D); 950 break; 951 case 16: 952 if (regno >= 16) 953 return 0; 954 955 if (fb->var.green.length == 5) 956 ((u32*)fb->pseudo_palette)[regno] = ((red & 0xF800) >> 1) | 957 ((green & 0xF800) >> 6) | ((blue & 0xF800) >> 11); 958 else if (fb->var.green.length == 6) 959 ((u32*)fb->pseudo_palette)[regno] = (red & 0xF800) | 960 ((green & 0xFC00) >> 5) | ((blue & 0xF800) >> 11); 961 else return -EINVAL; 962 break; 963 case 24: 964 case 32: 965 if (regno >= 16) 966 return 0; 967 968 ((u32*)fb->pseudo_palette)[regno] = ((red & 0xFF00) << 8) | 969 (green & 0xFF00) | ((blue & 0xFF00) >> 8); 970 break; 971 default: 972 return -EINVAL; 973 } 974 975 return 0; 976 } 977 978 979 /* Set the display blanking state */ 980 981 static int s3fb_blank(int blank_mode, struct fb_info *info) 982 { 983 struct s3fb_info *par = info->par; 984 985 switch (blank_mode) { 986 case FB_BLANK_UNBLANK: 987 fb_dbg(info, "unblank\n"); 988 svga_wcrt_mask(par->state.vgabase, 0x56, 0x00, 0x06); 989 svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20); 990 break; 991 case FB_BLANK_NORMAL: 992 fb_dbg(info, "blank\n"); 993 svga_wcrt_mask(par->state.vgabase, 0x56, 0x00, 0x06); 994 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); 995 break; 996 case FB_BLANK_HSYNC_SUSPEND: 997 fb_dbg(info, "hsync\n"); 998 svga_wcrt_mask(par->state.vgabase, 0x56, 0x02, 0x06); 999 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); 1000 break; 1001 case FB_BLANK_VSYNC_SUSPEND: 1002 fb_dbg(info, "vsync\n"); 1003 svga_wcrt_mask(par->state.vgabase, 0x56, 0x04, 0x06); 1004 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); 1005 break; 1006 case FB_BLANK_POWERDOWN: 1007 fb_dbg(info, "sync down\n"); 1008 svga_wcrt_mask(par->state.vgabase, 0x56, 0x06, 0x06); 1009 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); 1010 break; 1011 } 1012 1013 return 0; 1014 } 1015 1016 1017 /* Pan the display */ 1018 1019 static int s3fb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info) 1020 { 1021 struct s3fb_info *par = info->par; 1022 unsigned int offset; 1023 1024 /* Calculate the offset */ 1025 if (info->var.bits_per_pixel == 0) { 1026 offset = (var->yoffset / 16) * (info->var.xres_virtual / 2) 1027 + (var->xoffset / 2); 1028 offset = offset >> 2; 1029 } else { 1030 offset = (var->yoffset * info->fix.line_length) + 1031 (var->xoffset * info->var.bits_per_pixel / 8); 1032 offset = offset >> 2; 1033 } 1034 1035 /* Set the offset */ 1036 svga_wcrt_multi(par->state.vgabase, s3_start_address_regs, offset); 1037 1038 return 0; 1039 } 1040 1041 /* ------------------------------------------------------------------------- */ 1042 1043 /* Frame buffer operations */ 1044 1045 static const struct fb_ops s3fb_ops = { 1046 .owner = THIS_MODULE, 1047 .fb_open = s3fb_open, 1048 .fb_release = s3fb_release, 1049 .fb_check_var = s3fb_check_var, 1050 .fb_set_par = s3fb_set_par, 1051 .fb_setcolreg = s3fb_setcolreg, 1052 .fb_blank = s3fb_blank, 1053 .fb_pan_display = s3fb_pan_display, 1054 .fb_fillrect = s3fb_fillrect, 1055 .fb_copyarea = cfb_copyarea, 1056 .fb_imageblit = s3fb_imageblit, 1057 .fb_get_caps = svga_get_caps, 1058 }; 1059 1060 /* ------------------------------------------------------------------------- */ 1061 1062 static int s3_identification(struct s3fb_info *par) 1063 { 1064 int chip = par->chip; 1065 1066 if (chip == CHIP_XXX_TRIO) { 1067 u8 cr30 = vga_rcrt(par->state.vgabase, 0x30); 1068 u8 cr2e = vga_rcrt(par->state.vgabase, 0x2e); 1069 u8 cr2f = vga_rcrt(par->state.vgabase, 0x2f); 1070 1071 if ((cr30 == 0xE0) || (cr30 == 0xE1)) { 1072 if (cr2e == 0x10) 1073 return CHIP_732_TRIO32; 1074 if (cr2e == 0x11) { 1075 if (! (cr2f & 0x40)) 1076 return CHIP_764_TRIO64; 1077 else 1078 return CHIP_765_TRIO64VP; 1079 } 1080 } 1081 } 1082 1083 if (chip == CHIP_XXX_TRIO64V2_DXGX) { 1084 u8 cr6f = vga_rcrt(par->state.vgabase, 0x6f); 1085 1086 if (! (cr6f & 0x01)) 1087 return CHIP_775_TRIO64V2_DX; 1088 else 1089 return CHIP_785_TRIO64V2_GX; 1090 } 1091 1092 if (chip == CHIP_XXX_VIRGE_DXGX) { 1093 u8 cr6f = vga_rcrt(par->state.vgabase, 0x6f); 1094 1095 if (! (cr6f & 0x01)) 1096 return CHIP_375_VIRGE_DX; 1097 else 1098 return CHIP_385_VIRGE_GX; 1099 } 1100 1101 if (chip == CHIP_36X_TRIO3D_1X_2X) { 1102 switch (vga_rcrt(par->state.vgabase, 0x2f)) { 1103 case 0x00: 1104 return CHIP_360_TRIO3D_1X; 1105 case 0x01: 1106 return CHIP_362_TRIO3D_2X; 1107 case 0x02: 1108 return CHIP_368_TRIO3D_2X; 1109 } 1110 } 1111 1112 return CHIP_UNKNOWN; 1113 } 1114 1115 1116 /* PCI probe */ 1117 1118 static int s3_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) 1119 { 1120 struct pci_bus_region bus_reg; 1121 struct resource vga_res; 1122 struct fb_info *info; 1123 struct s3fb_info *par; 1124 int rc; 1125 u8 regval, cr38, cr39; 1126 bool found = false; 1127 1128 /* Ignore secondary VGA device because there is no VGA arbitration */ 1129 if (! svga_primary_device(dev)) { 1130 dev_info(&(dev->dev), "ignoring secondary device\n"); 1131 return -ENODEV; 1132 } 1133 1134 /* Allocate and fill driver data structure */ 1135 info = framebuffer_alloc(sizeof(struct s3fb_info), &(dev->dev)); 1136 if (!info) 1137 return -ENOMEM; 1138 1139 par = info->par; 1140 mutex_init(&par->open_lock); 1141 1142 info->flags = FBINFO_PARTIAL_PAN_OK | FBINFO_HWACCEL_YPAN; 1143 info->fbops = &s3fb_ops; 1144 1145 /* Prepare PCI device */ 1146 rc = pci_enable_device(dev); 1147 if (rc < 0) { 1148 dev_err(info->device, "cannot enable PCI device\n"); 1149 goto err_enable_device; 1150 } 1151 1152 rc = pci_request_regions(dev, "s3fb"); 1153 if (rc < 0) { 1154 dev_err(info->device, "cannot reserve framebuffer region\n"); 1155 goto err_request_regions; 1156 } 1157 1158 1159 info->fix.smem_start = pci_resource_start(dev, 0); 1160 info->fix.smem_len = pci_resource_len(dev, 0); 1161 1162 /* Map physical IO memory address into kernel space */ 1163 info->screen_base = pci_iomap_wc(dev, 0, 0); 1164 if (! info->screen_base) { 1165 rc = -ENOMEM; 1166 dev_err(info->device, "iomap for framebuffer failed\n"); 1167 goto err_iomap; 1168 } 1169 1170 bus_reg.start = 0; 1171 bus_reg.end = 64 * 1024; 1172 1173 vga_res.flags = IORESOURCE_IO; 1174 1175 pcibios_bus_to_resource(dev->bus, &vga_res, &bus_reg); 1176 1177 par->state.vgabase = (void __iomem *) (unsigned long) vga_res.start; 1178 1179 /* Unlock regs */ 1180 cr38 = vga_rcrt(par->state.vgabase, 0x38); 1181 cr39 = vga_rcrt(par->state.vgabase, 0x39); 1182 vga_wseq(par->state.vgabase, 0x08, 0x06); 1183 vga_wcrt(par->state.vgabase, 0x38, 0x48); 1184 vga_wcrt(par->state.vgabase, 0x39, 0xA5); 1185 1186 /* Identify chip type */ 1187 par->chip = id->driver_data & CHIP_MASK; 1188 par->rev = vga_rcrt(par->state.vgabase, 0x2f); 1189 if (par->chip & CHIP_UNDECIDED_FLAG) 1190 par->chip = s3_identification(par); 1191 1192 /* Find how many physical memory there is on card */ 1193 /* 0x36 register is accessible even if other registers are locked */ 1194 regval = vga_rcrt(par->state.vgabase, 0x36); 1195 if (par->chip == CHIP_360_TRIO3D_1X || 1196 par->chip == CHIP_362_TRIO3D_2X || 1197 par->chip == CHIP_368_TRIO3D_2X || 1198 par->chip == CHIP_365_TRIO3D) { 1199 switch ((regval & 0xE0) >> 5) { 1200 case 0: /* 8MB -- only 4MB usable for display */ 1201 case 1: /* 4MB with 32-bit bus */ 1202 case 2: /* 4MB */ 1203 info->screen_size = 4 << 20; 1204 break; 1205 case 4: /* 2MB on 365 Trio3D */ 1206 case 6: /* 2MB */ 1207 info->screen_size = 2 << 20; 1208 break; 1209 } 1210 } else if (par->chip == CHIP_357_VIRGE_GX2 || 1211 par->chip == CHIP_359_VIRGE_GX2P || 1212 par->chip == CHIP_260_VIRGE_MX) { 1213 switch ((regval & 0xC0) >> 6) { 1214 case 1: /* 4MB */ 1215 info->screen_size = 4 << 20; 1216 break; 1217 case 3: /* 2MB */ 1218 info->screen_size = 2 << 20; 1219 break; 1220 } 1221 } else if (par->chip == CHIP_988_VIRGE_VX) { 1222 switch ((regval & 0x60) >> 5) { 1223 case 0: /* 2MB */ 1224 info->screen_size = 2 << 20; 1225 break; 1226 case 1: /* 4MB */ 1227 info->screen_size = 4 << 20; 1228 break; 1229 case 2: /* 6MB */ 1230 info->screen_size = 6 << 20; 1231 break; 1232 case 3: /* 8MB */ 1233 info->screen_size = 8 << 20; 1234 break; 1235 } 1236 /* off-screen memory */ 1237 regval = vga_rcrt(par->state.vgabase, 0x37); 1238 switch ((regval & 0x60) >> 5) { 1239 case 1: /* 4MB */ 1240 info->screen_size -= 4 << 20; 1241 break; 1242 case 2: /* 2MB */ 1243 info->screen_size -= 2 << 20; 1244 break; 1245 } 1246 } else 1247 info->screen_size = s3_memsizes[regval >> 5] << 10; 1248 info->fix.smem_len = info->screen_size; 1249 1250 /* Find MCLK frequency */ 1251 regval = vga_rseq(par->state.vgabase, 0x10); 1252 par->mclk_freq = ((vga_rseq(par->state.vgabase, 0x11) + 2) * 14318) / ((regval & 0x1F) + 2); 1253 par->mclk_freq = par->mclk_freq >> (regval >> 5); 1254 1255 /* Restore locks */ 1256 vga_wcrt(par->state.vgabase, 0x38, cr38); 1257 vga_wcrt(par->state.vgabase, 0x39, cr39); 1258 1259 strcpy(info->fix.id, s3_names [par->chip]); 1260 info->fix.mmio_start = 0; 1261 info->fix.mmio_len = 0; 1262 info->fix.type = FB_TYPE_PACKED_PIXELS; 1263 info->fix.visual = FB_VISUAL_PSEUDOCOLOR; 1264 info->fix.ypanstep = 0; 1265 info->fix.accel = FB_ACCEL_NONE; 1266 info->pseudo_palette = (void*) (par->pseudo_palette); 1267 info->var.bits_per_pixel = 8; 1268 1269 #ifdef CONFIG_FB_S3_DDC 1270 /* Enable MMIO if needed */ 1271 if (s3fb_ddc_needs_mmio(par->chip)) { 1272 par->mmio = ioremap(info->fix.smem_start + MMIO_OFFSET, MMIO_SIZE); 1273 if (par->mmio) 1274 svga_wcrt_mask(par->state.vgabase, 0x53, 0x08, 0x08); /* enable MMIO */ 1275 else 1276 dev_err(info->device, "unable to map MMIO at 0x%lx, disabling DDC", 1277 info->fix.smem_start + MMIO_OFFSET); 1278 } 1279 if (!s3fb_ddc_needs_mmio(par->chip) || par->mmio) 1280 if (s3fb_setup_ddc_bus(info) == 0) { 1281 u8 *edid = fb_ddc_read(&par->ddc_adapter); 1282 par->ddc_registered = true; 1283 if (edid) { 1284 fb_edid_to_monspecs(edid, &info->monspecs); 1285 kfree(edid); 1286 if (!info->monspecs.modedb) 1287 dev_err(info->device, "error getting mode database\n"); 1288 else { 1289 const struct fb_videomode *m; 1290 1291 fb_videomode_to_modelist(info->monspecs.modedb, 1292 info->monspecs.modedb_len, 1293 &info->modelist); 1294 m = fb_find_best_display(&info->monspecs, &info->modelist); 1295 if (m) { 1296 fb_videomode_to_var(&info->var, m); 1297 /* fill all other info->var's fields */ 1298 if (s3fb_check_var(&info->var, info) == 0) 1299 found = true; 1300 } 1301 } 1302 } 1303 } 1304 #endif 1305 if (!mode_option && !found) 1306 mode_option = "640x480-8@60"; 1307 1308 /* Prepare startup mode */ 1309 if (mode_option) { 1310 rc = fb_find_mode(&info->var, info, mode_option, 1311 info->monspecs.modedb, info->monspecs.modedb_len, 1312 NULL, info->var.bits_per_pixel); 1313 if (!rc || rc == 4) { 1314 rc = -EINVAL; 1315 dev_err(info->device, "mode %s not found\n", mode_option); 1316 fb_destroy_modedb(info->monspecs.modedb); 1317 info->monspecs.modedb = NULL; 1318 goto err_find_mode; 1319 } 1320 } 1321 1322 fb_destroy_modedb(info->monspecs.modedb); 1323 info->monspecs.modedb = NULL; 1324 1325 /* maximize virtual vertical size for fast scrolling */ 1326 info->var.yres_virtual = info->fix.smem_len * 8 / 1327 (info->var.bits_per_pixel * info->var.xres_virtual); 1328 if (info->var.yres_virtual < info->var.yres) { 1329 dev_err(info->device, "virtual vertical size smaller than real\n"); 1330 rc = -EINVAL; 1331 goto err_find_mode; 1332 } 1333 1334 rc = fb_alloc_cmap(&info->cmap, 256, 0); 1335 if (rc < 0) { 1336 dev_err(info->device, "cannot allocate colormap\n"); 1337 goto err_alloc_cmap; 1338 } 1339 1340 rc = register_framebuffer(info); 1341 if (rc < 0) { 1342 dev_err(info->device, "cannot register framebuffer\n"); 1343 goto err_reg_fb; 1344 } 1345 1346 fb_info(info, "%s on %s, %d MB RAM, %d MHz MCLK\n", 1347 info->fix.id, pci_name(dev), 1348 info->fix.smem_len >> 20, (par->mclk_freq + 500) / 1000); 1349 1350 if (par->chip == CHIP_UNKNOWN) 1351 fb_info(info, "unknown chip, CR2D=%x, CR2E=%x, CRT2F=%x, CRT30=%x\n", 1352 vga_rcrt(par->state.vgabase, 0x2d), 1353 vga_rcrt(par->state.vgabase, 0x2e), 1354 vga_rcrt(par->state.vgabase, 0x2f), 1355 vga_rcrt(par->state.vgabase, 0x30)); 1356 1357 /* Record a reference to the driver data */ 1358 pci_set_drvdata(dev, info); 1359 1360 if (mtrr) 1361 par->wc_cookie = arch_phys_wc_add(info->fix.smem_start, 1362 info->fix.smem_len); 1363 1364 return 0; 1365 1366 /* Error handling */ 1367 err_reg_fb: 1368 fb_dealloc_cmap(&info->cmap); 1369 err_alloc_cmap: 1370 err_find_mode: 1371 #ifdef CONFIG_FB_S3_DDC 1372 if (par->ddc_registered) 1373 i2c_del_adapter(&par->ddc_adapter); 1374 if (par->mmio) 1375 iounmap(par->mmio); 1376 #endif 1377 pci_iounmap(dev, info->screen_base); 1378 err_iomap: 1379 pci_release_regions(dev); 1380 err_request_regions: 1381 /* pci_disable_device(dev); */ 1382 err_enable_device: 1383 framebuffer_release(info); 1384 return rc; 1385 } 1386 1387 1388 /* PCI remove */ 1389 1390 static void s3_pci_remove(struct pci_dev *dev) 1391 { 1392 struct fb_info *info = pci_get_drvdata(dev); 1393 struct s3fb_info __maybe_unused *par; 1394 1395 if (info) { 1396 par = info->par; 1397 arch_phys_wc_del(par->wc_cookie); 1398 unregister_framebuffer(info); 1399 fb_dealloc_cmap(&info->cmap); 1400 1401 #ifdef CONFIG_FB_S3_DDC 1402 if (par->ddc_registered) 1403 i2c_del_adapter(&par->ddc_adapter); 1404 if (par->mmio) 1405 iounmap(par->mmio); 1406 #endif 1407 1408 pci_iounmap(dev, info->screen_base); 1409 pci_release_regions(dev); 1410 /* pci_disable_device(dev); */ 1411 1412 framebuffer_release(info); 1413 } 1414 } 1415 1416 /* PCI suspend */ 1417 1418 static int __maybe_unused s3_pci_suspend(struct device *dev) 1419 { 1420 struct fb_info *info = dev_get_drvdata(dev); 1421 struct s3fb_info *par = info->par; 1422 1423 dev_info(info->device, "suspend\n"); 1424 1425 console_lock(); 1426 mutex_lock(&(par->open_lock)); 1427 1428 if (par->ref_count == 0) { 1429 mutex_unlock(&(par->open_lock)); 1430 console_unlock(); 1431 return 0; 1432 } 1433 1434 fb_set_suspend(info, 1); 1435 1436 mutex_unlock(&(par->open_lock)); 1437 console_unlock(); 1438 1439 return 0; 1440 } 1441 1442 1443 /* PCI resume */ 1444 1445 static int __maybe_unused s3_pci_resume(struct device *dev) 1446 { 1447 struct fb_info *info = dev_get_drvdata(dev); 1448 struct s3fb_info *par = info->par; 1449 1450 dev_info(info->device, "resume\n"); 1451 1452 console_lock(); 1453 mutex_lock(&(par->open_lock)); 1454 1455 if (par->ref_count == 0) { 1456 mutex_unlock(&(par->open_lock)); 1457 console_unlock(); 1458 return 0; 1459 } 1460 1461 s3fb_set_par(info); 1462 fb_set_suspend(info, 0); 1463 1464 mutex_unlock(&(par->open_lock)); 1465 console_unlock(); 1466 1467 return 0; 1468 } 1469 1470 static const struct dev_pm_ops s3_pci_pm_ops = { 1471 #ifdef CONFIG_PM_SLEEP 1472 .suspend = s3_pci_suspend, 1473 .resume = s3_pci_resume, 1474 .freeze = NULL, 1475 .thaw = s3_pci_resume, 1476 .poweroff = s3_pci_suspend, 1477 .restore = s3_pci_resume, 1478 #endif 1479 }; 1480 1481 /* List of boards that we are trying to support */ 1482 1483 static const struct pci_device_id s3_devices[] = { 1484 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8810), .driver_data = CHIP_XXX_TRIO}, 1485 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8811), .driver_data = CHIP_XXX_TRIO}, 1486 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8812), .driver_data = CHIP_M65_AURORA64VP}, 1487 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8814), .driver_data = CHIP_767_TRIO64UVP}, 1488 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8901), .driver_data = CHIP_XXX_TRIO64V2_DXGX}, 1489 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8902), .driver_data = CHIP_551_PLATO_PX}, 1490 1491 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x5631), .driver_data = CHIP_325_VIRGE}, 1492 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x883D), .driver_data = CHIP_988_VIRGE_VX}, 1493 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A01), .driver_data = CHIP_XXX_VIRGE_DXGX}, 1494 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A10), .driver_data = CHIP_357_VIRGE_GX2}, 1495 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A11), .driver_data = CHIP_359_VIRGE_GX2P}, 1496 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A12), .driver_data = CHIP_359_VIRGE_GX2P}, 1497 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A13), .driver_data = CHIP_36X_TRIO3D_1X_2X}, 1498 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8904), .driver_data = CHIP_365_TRIO3D}, 1499 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8C01), .driver_data = CHIP_260_VIRGE_MX}, 1500 1501 {0, 0, 0, 0, 0, 0, 0} 1502 }; 1503 1504 1505 MODULE_DEVICE_TABLE(pci, s3_devices); 1506 1507 static struct pci_driver s3fb_pci_driver = { 1508 .name = "s3fb", 1509 .id_table = s3_devices, 1510 .probe = s3_pci_probe, 1511 .remove = s3_pci_remove, 1512 .driver.pm = &s3_pci_pm_ops, 1513 }; 1514 1515 /* Parse user specified options */ 1516 1517 #ifndef MODULE 1518 static int __init s3fb_setup(char *options) 1519 { 1520 char *opt; 1521 1522 if (!options || !*options) 1523 return 0; 1524 1525 while ((opt = strsep(&options, ",")) != NULL) { 1526 1527 if (!*opt) 1528 continue; 1529 else if (!strncmp(opt, "mtrr:", 5)) 1530 mtrr = simple_strtoul(opt + 5, NULL, 0); 1531 else if (!strncmp(opt, "fasttext:", 9)) 1532 fasttext = simple_strtoul(opt + 9, NULL, 0); 1533 else 1534 mode_option = opt; 1535 } 1536 1537 return 0; 1538 } 1539 #endif 1540 1541 /* Cleanup */ 1542 1543 static void __exit s3fb_cleanup(void) 1544 { 1545 pr_debug("s3fb: cleaning up\n"); 1546 pci_unregister_driver(&s3fb_pci_driver); 1547 } 1548 1549 /* Driver Initialisation */ 1550 1551 static int __init s3fb_init(void) 1552 { 1553 1554 #ifndef MODULE 1555 char *option = NULL; 1556 1557 if (fb_get_options("s3fb", &option)) 1558 return -ENODEV; 1559 s3fb_setup(option); 1560 #endif 1561 1562 pr_debug("s3fb: initializing\n"); 1563 return pci_register_driver(&s3fb_pci_driver); 1564 } 1565 1566 /* ------------------------------------------------------------------------- */ 1567 1568 /* Modularization */ 1569 1570 module_init(s3fb_init); 1571 module_exit(s3fb_cleanup); 1572