1 /***************************************************************************\ 2 |* *| 3 |* Copyright 1993-1999 NVIDIA, Corporation. All rights reserved. *| 4 |* *| 5 |* NOTICE TO USER: The source code is copyrighted under U.S. and *| 6 |* international laws. Users and possessors of this source code are *| 7 |* hereby granted a nonexclusive, royalty-free copyright license to *| 8 |* use this code in individual and commercial software. *| 9 |* *| 10 |* Any use of this source code must include, in the user documenta- *| 11 |* tion and internal comments to the code, notices to the end user *| 12 |* as follows: *| 13 |* *| 14 |* Copyright 1993-1999 NVIDIA, Corporation. All rights reserved. *| 15 |* *| 16 |* NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY *| 17 |* OF THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" *| 18 |* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *| 19 |* ATION DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, *| 20 |* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *| 21 |* MENT, AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL *| 22 |* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *| 23 |* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *| 24 |* SULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION *| 25 |* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF *| 26 |* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE. *| 27 |* *| 28 |* U.S. Government End Users. This source code is a "commercial *| 29 |* item," as that term is defined at 48 C.F.R. 2.101 (OCT 1995), *| 30 |* consisting of "commercial computer software" and "commercial *| 31 |* computer software documentation," as such terms are used in *| 32 |* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *| 33 |* ment only as a commercial end item. Consistent with 48 C.F.R. *| 34 |* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *| 35 |* all U.S. Government End Users acquire the source code with only *| 36 |* those rights set forth herein. *| 37 |* *| 38 \***************************************************************************/ 39 40 /* 41 * GPL licensing note -- nVidia is allowing a liberal interpretation of 42 * the documentation restriction above, to merely say that this nVidia's 43 * copyright and disclaimer should be included with all code derived 44 * from this source. -- Jeff Garzik <jgarzik@pobox.com>, 01/Nov/99 45 */ 46 47 /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/riva_hw.c,v 1.33 2002/08/05 20:47:06 mvojkovi Exp $ */ 48 49 #include <linux/kernel.h> 50 #include <linux/pci.h> 51 #include <linux/pci_ids.h> 52 #include "riva_hw.h" 53 #include "riva_tbl.h" 54 #include "nv_type.h" 55 56 /* 57 * This file is an OS-agnostic file used to make RIVA 128 and RIVA TNT 58 * operate identically (except TNT has more memory and better 3D quality. 59 */ 60 static int nv3Busy 61 ( 62 RIVA_HW_INST *chip 63 ) 64 { 65 return ((NV_RD32(&chip->Rop->FifoFree, 0) < chip->FifoEmptyCount) || 66 NV_RD32(&chip->PGRAPH[0x000006B0/4], 0) & 0x01); 67 } 68 static int nv4Busy 69 ( 70 RIVA_HW_INST *chip 71 ) 72 { 73 return ((NV_RD32(&chip->Rop->FifoFree, 0) < chip->FifoEmptyCount) || 74 NV_RD32(&chip->PGRAPH[0x00000700/4], 0) & 0x01); 75 } 76 static int nv10Busy 77 ( 78 RIVA_HW_INST *chip 79 ) 80 { 81 return ((NV_RD32(&chip->Rop->FifoFree, 0) < chip->FifoEmptyCount) || 82 NV_RD32(&chip->PGRAPH[0x00000700/4], 0) & 0x01); 83 } 84 85 static void vgaLockUnlock 86 ( 87 RIVA_HW_INST *chip, 88 int Lock 89 ) 90 { 91 U008 cr11; 92 VGA_WR08(chip->PCIO, 0x3D4, 0x11); 93 cr11 = VGA_RD08(chip->PCIO, 0x3D5); 94 if(Lock) cr11 |= 0x80; 95 else cr11 &= ~0x80; 96 VGA_WR08(chip->PCIO, 0x3D5, cr11); 97 } 98 static void nv3LockUnlock 99 ( 100 RIVA_HW_INST *chip, 101 int Lock 102 ) 103 { 104 VGA_WR08(chip->PVIO, 0x3C4, 0x06); 105 VGA_WR08(chip->PVIO, 0x3C5, Lock ? 0x99 : 0x57); 106 vgaLockUnlock(chip, Lock); 107 } 108 static void nv4LockUnlock 109 ( 110 RIVA_HW_INST *chip, 111 int Lock 112 ) 113 { 114 VGA_WR08(chip->PCIO, 0x3D4, 0x1F); 115 VGA_WR08(chip->PCIO, 0x3D5, Lock ? 0x99 : 0x57); 116 vgaLockUnlock(chip, Lock); 117 } 118 119 static int ShowHideCursor 120 ( 121 RIVA_HW_INST *chip, 122 int ShowHide 123 ) 124 { 125 int cursor; 126 cursor = chip->CurrentState->cursor1; 127 chip->CurrentState->cursor1 = (chip->CurrentState->cursor1 & 0xFE) | 128 (ShowHide & 0x01); 129 VGA_WR08(chip->PCIO, 0x3D4, 0x31); 130 VGA_WR08(chip->PCIO, 0x3D5, chip->CurrentState->cursor1); 131 return (cursor & 0x01); 132 } 133 134 /****************************************************************************\ 135 * * 136 * The video arbitration routines calculate some "magic" numbers. Fixes * 137 * the snow seen when accessing the framebuffer without it. * 138 * It just works (I hope). * 139 * * 140 \****************************************************************************/ 141 142 #define DEFAULT_GR_LWM 100 143 #define DEFAULT_VID_LWM 100 144 #define DEFAULT_GR_BURST_SIZE 256 145 #define DEFAULT_VID_BURST_SIZE 128 146 #define VIDEO 0 147 #define GRAPHICS 1 148 #define MPORT 2 149 #define ENGINE 3 150 #define GFIFO_SIZE 320 151 #define GFIFO_SIZE_128 256 152 #define MFIFO_SIZE 120 153 #define VFIFO_SIZE 256 154 155 typedef struct { 156 int gdrain_rate; 157 int vdrain_rate; 158 int mdrain_rate; 159 int gburst_size; 160 int vburst_size; 161 char vid_en; 162 char gr_en; 163 int wcmocc, wcgocc, wcvocc, wcvlwm, wcglwm; 164 int by_gfacc; 165 char vid_only_once; 166 char gr_only_once; 167 char first_vacc; 168 char first_gacc; 169 char first_macc; 170 int vocc; 171 int gocc; 172 int mocc; 173 char cur; 174 char engine_en; 175 char converged; 176 int priority; 177 } nv3_arb_info; 178 typedef struct { 179 int graphics_lwm; 180 int video_lwm; 181 int graphics_burst_size; 182 int video_burst_size; 183 int graphics_hi_priority; 184 int media_hi_priority; 185 int rtl_values; 186 int valid; 187 } nv3_fifo_info; 188 typedef struct { 189 char pix_bpp; 190 char enable_video; 191 char gr_during_vid; 192 char enable_mp; 193 int memory_width; 194 int video_scale; 195 int pclk_khz; 196 int mclk_khz; 197 int mem_page_miss; 198 int mem_latency; 199 char mem_aligned; 200 } nv3_sim_state; 201 typedef struct { 202 int graphics_lwm; 203 int video_lwm; 204 int graphics_burst_size; 205 int video_burst_size; 206 int valid; 207 } nv4_fifo_info; 208 typedef struct { 209 int pclk_khz; 210 int mclk_khz; 211 int nvclk_khz; 212 char mem_page_miss; 213 char mem_latency; 214 int memory_width; 215 char enable_video; 216 char gr_during_vid; 217 char pix_bpp; 218 char mem_aligned; 219 char enable_mp; 220 } nv4_sim_state; 221 typedef struct { 222 int graphics_lwm; 223 int video_lwm; 224 int graphics_burst_size; 225 int video_burst_size; 226 int valid; 227 } nv10_fifo_info; 228 typedef struct { 229 int pclk_khz; 230 int mclk_khz; 231 int nvclk_khz; 232 char mem_page_miss; 233 char mem_latency; 234 u32 memory_type; 235 int memory_width; 236 char enable_video; 237 char gr_during_vid; 238 char pix_bpp; 239 char mem_aligned; 240 char enable_mp; 241 } nv10_sim_state; 242 static int nv3_iterate(nv3_fifo_info *res_info, nv3_sim_state * state, nv3_arb_info *ainfo) 243 { 244 int iter = 0; 245 int tmp; 246 int vfsize, mfsize, gfsize; 247 int mburst_size = 32; 248 int mmisses, gmisses, vmisses; 249 int misses; 250 int vlwm, glwm; 251 int last, next, cur; 252 int max_gfsize ; 253 long ns; 254 255 vlwm = 0; 256 glwm = 0; 257 vfsize = 0; 258 gfsize = 0; 259 cur = ainfo->cur; 260 mmisses = 2; 261 gmisses = 2; 262 vmisses = 2; 263 if (ainfo->gburst_size == 128) max_gfsize = GFIFO_SIZE_128; 264 else max_gfsize = GFIFO_SIZE; 265 max_gfsize = GFIFO_SIZE; 266 while (1) 267 { 268 if (ainfo->vid_en) 269 { 270 if (ainfo->wcvocc > ainfo->vocc) ainfo->wcvocc = ainfo->vocc; 271 if (ainfo->wcvlwm > vlwm) ainfo->wcvlwm = vlwm ; 272 ns = 1000000 * ainfo->vburst_size/(state->memory_width/8)/state->mclk_khz; 273 vfsize = ns * ainfo->vdrain_rate / 1000000; 274 vfsize = ainfo->wcvlwm - ainfo->vburst_size + vfsize; 275 } 276 if (state->enable_mp) 277 { 278 if (ainfo->wcmocc > ainfo->mocc) ainfo->wcmocc = ainfo->mocc; 279 } 280 if (ainfo->gr_en) 281 { 282 if (ainfo->wcglwm > glwm) ainfo->wcglwm = glwm ; 283 if (ainfo->wcgocc > ainfo->gocc) ainfo->wcgocc = ainfo->gocc; 284 ns = 1000000 * (ainfo->gburst_size/(state->memory_width/8))/state->mclk_khz; 285 gfsize = (ns * (long) ainfo->gdrain_rate)/1000000; 286 gfsize = ainfo->wcglwm - ainfo->gburst_size + gfsize; 287 } 288 mfsize = 0; 289 if (!state->gr_during_vid && ainfo->vid_en) 290 if (ainfo->vid_en && (ainfo->vocc < 0) && !ainfo->vid_only_once) 291 next = VIDEO; 292 else if (ainfo->mocc < 0) 293 next = MPORT; 294 else if (ainfo->gocc< ainfo->by_gfacc) 295 next = GRAPHICS; 296 else return (0); 297 else switch (ainfo->priority) 298 { 299 case VIDEO: 300 if (ainfo->vid_en && ainfo->vocc<0 && !ainfo->vid_only_once) 301 next = VIDEO; 302 else if (ainfo->gr_en && ainfo->gocc<0 && !ainfo->gr_only_once) 303 next = GRAPHICS; 304 else if (ainfo->mocc<0) 305 next = MPORT; 306 else return (0); 307 break; 308 case GRAPHICS: 309 if (ainfo->gr_en && ainfo->gocc<0 && !ainfo->gr_only_once) 310 next = GRAPHICS; 311 else if (ainfo->vid_en && ainfo->vocc<0 && !ainfo->vid_only_once) 312 next = VIDEO; 313 else if (ainfo->mocc<0) 314 next = MPORT; 315 else return (0); 316 break; 317 default: 318 if (ainfo->mocc<0) 319 next = MPORT; 320 else if (ainfo->gr_en && ainfo->gocc<0 && !ainfo->gr_only_once) 321 next = GRAPHICS; 322 else if (ainfo->vid_en && ainfo->vocc<0 && !ainfo->vid_only_once) 323 next = VIDEO; 324 else return (0); 325 break; 326 } 327 last = cur; 328 cur = next; 329 iter++; 330 switch (cur) 331 { 332 case VIDEO: 333 if (last==cur) misses = 0; 334 else if (ainfo->first_vacc) misses = vmisses; 335 else misses = 1; 336 ainfo->first_vacc = 0; 337 if (last!=cur) 338 { 339 ns = 1000000 * (vmisses*state->mem_page_miss + state->mem_latency)/state->mclk_khz; 340 vlwm = ns * ainfo->vdrain_rate/ 1000000; 341 vlwm = ainfo->vocc - vlwm; 342 } 343 ns = 1000000*(misses*state->mem_page_miss + ainfo->vburst_size)/(state->memory_width/8)/state->mclk_khz; 344 ainfo->vocc = ainfo->vocc + ainfo->vburst_size - ns*ainfo->vdrain_rate/1000000; 345 ainfo->gocc = ainfo->gocc - ns*ainfo->gdrain_rate/1000000; 346 ainfo->mocc = ainfo->mocc - ns*ainfo->mdrain_rate/1000000; 347 break; 348 case GRAPHICS: 349 if (last==cur) misses = 0; 350 else if (ainfo->first_gacc) misses = gmisses; 351 else misses = 1; 352 ainfo->first_gacc = 0; 353 if (last!=cur) 354 { 355 ns = 1000000*(gmisses*state->mem_page_miss + state->mem_latency)/state->mclk_khz ; 356 glwm = ns * ainfo->gdrain_rate/1000000; 357 glwm = ainfo->gocc - glwm; 358 } 359 ns = 1000000*(misses*state->mem_page_miss + ainfo->gburst_size/(state->memory_width/8))/state->mclk_khz; 360 ainfo->vocc = ainfo->vocc + 0 - ns*ainfo->vdrain_rate/1000000; 361 ainfo->gocc = ainfo->gocc + ainfo->gburst_size - ns*ainfo->gdrain_rate/1000000; 362 ainfo->mocc = ainfo->mocc + 0 - ns*ainfo->mdrain_rate/1000000; 363 break; 364 default: 365 if (last==cur) misses = 0; 366 else if (ainfo->first_macc) misses = mmisses; 367 else misses = 1; 368 ainfo->first_macc = 0; 369 ns = 1000000*(misses*state->mem_page_miss + mburst_size/(state->memory_width/8))/state->mclk_khz; 370 ainfo->vocc = ainfo->vocc + 0 - ns*ainfo->vdrain_rate/1000000; 371 ainfo->gocc = ainfo->gocc + 0 - ns*ainfo->gdrain_rate/1000000; 372 ainfo->mocc = ainfo->mocc + mburst_size - ns*ainfo->mdrain_rate/1000000; 373 break; 374 } 375 if (iter>100) 376 { 377 ainfo->converged = 0; 378 return (1); 379 } 380 ns = 1000000*ainfo->gburst_size/(state->memory_width/8)/state->mclk_khz; 381 tmp = ns * ainfo->gdrain_rate/1000000; 382 if (abs(ainfo->gburst_size) + ((abs(ainfo->wcglwm) + 16 ) & ~0x7) - tmp > max_gfsize) 383 { 384 ainfo->converged = 0; 385 return (1); 386 } 387 ns = 1000000*ainfo->vburst_size/(state->memory_width/8)/state->mclk_khz; 388 tmp = ns * ainfo->vdrain_rate/1000000; 389 if (abs(ainfo->vburst_size) + (abs(ainfo->wcvlwm + 32) & ~0xf) - tmp> VFIFO_SIZE) 390 { 391 ainfo->converged = 0; 392 return (1); 393 } 394 if (abs(ainfo->gocc) > max_gfsize) 395 { 396 ainfo->converged = 0; 397 return (1); 398 } 399 if (abs(ainfo->vocc) > VFIFO_SIZE) 400 { 401 ainfo->converged = 0; 402 return (1); 403 } 404 if (abs(ainfo->mocc) > MFIFO_SIZE) 405 { 406 ainfo->converged = 0; 407 return (1); 408 } 409 if (abs(vfsize) > VFIFO_SIZE) 410 { 411 ainfo->converged = 0; 412 return (1); 413 } 414 if (abs(gfsize) > max_gfsize) 415 { 416 ainfo->converged = 0; 417 return (1); 418 } 419 if (abs(mfsize) > MFIFO_SIZE) 420 { 421 ainfo->converged = 0; 422 return (1); 423 } 424 } 425 } 426 static char nv3_arb(nv3_fifo_info * res_info, nv3_sim_state * state, nv3_arb_info *ainfo) 427 { 428 long ens, vns, mns, gns; 429 int mmisses, gmisses, vmisses, eburst_size, mburst_size; 430 int refresh_cycle; 431 432 refresh_cycle = 2*(state->mclk_khz/state->pclk_khz) + 5; 433 mmisses = 2; 434 if (state->mem_aligned) gmisses = 2; 435 else gmisses = 3; 436 vmisses = 2; 437 eburst_size = state->memory_width * 1; 438 mburst_size = 32; 439 gns = 1000000 * (gmisses*state->mem_page_miss + state->mem_latency)/state->mclk_khz; 440 ainfo->by_gfacc = gns*ainfo->gdrain_rate/1000000; 441 ainfo->wcmocc = 0; 442 ainfo->wcgocc = 0; 443 ainfo->wcvocc = 0; 444 ainfo->wcvlwm = 0; 445 ainfo->wcglwm = 0; 446 ainfo->engine_en = 1; 447 ainfo->converged = 1; 448 if (ainfo->engine_en) 449 { 450 ens = 1000000*(state->mem_page_miss + eburst_size/(state->memory_width/8) +refresh_cycle)/state->mclk_khz; 451 ainfo->mocc = state->enable_mp ? 0-ens*ainfo->mdrain_rate/1000000 : 0; 452 ainfo->vocc = ainfo->vid_en ? 0-ens*ainfo->vdrain_rate/1000000 : 0; 453 ainfo->gocc = ainfo->gr_en ? 0-ens*ainfo->gdrain_rate/1000000 : 0; 454 ainfo->cur = ENGINE; 455 ainfo->first_vacc = 1; 456 ainfo->first_gacc = 1; 457 ainfo->first_macc = 1; 458 nv3_iterate(res_info, state,ainfo); 459 } 460 if (state->enable_mp) 461 { 462 mns = 1000000 * (mmisses*state->mem_page_miss + mburst_size/(state->memory_width/8) + refresh_cycle)/state->mclk_khz; 463 ainfo->mocc = state->enable_mp ? 0 : mburst_size - mns*ainfo->mdrain_rate/1000000; 464 ainfo->vocc = ainfo->vid_en ? 0 : 0- mns*ainfo->vdrain_rate/1000000; 465 ainfo->gocc = ainfo->gr_en ? 0: 0- mns*ainfo->gdrain_rate/1000000; 466 ainfo->cur = MPORT; 467 ainfo->first_vacc = 1; 468 ainfo->first_gacc = 1; 469 ainfo->first_macc = 0; 470 nv3_iterate(res_info, state,ainfo); 471 } 472 if (ainfo->gr_en) 473 { 474 ainfo->first_vacc = 1; 475 ainfo->first_gacc = 0; 476 ainfo->first_macc = 1; 477 gns = 1000000*(gmisses*state->mem_page_miss + ainfo->gburst_size/(state->memory_width/8) + refresh_cycle)/state->mclk_khz; 478 ainfo->gocc = ainfo->gburst_size - gns*ainfo->gdrain_rate/1000000; 479 ainfo->vocc = ainfo->vid_en? 0-gns*ainfo->vdrain_rate/1000000 : 0; 480 ainfo->mocc = state->enable_mp ? 0-gns*ainfo->mdrain_rate/1000000: 0; 481 ainfo->cur = GRAPHICS; 482 nv3_iterate(res_info, state,ainfo); 483 } 484 if (ainfo->vid_en) 485 { 486 ainfo->first_vacc = 0; 487 ainfo->first_gacc = 1; 488 ainfo->first_macc = 1; 489 vns = 1000000*(vmisses*state->mem_page_miss + ainfo->vburst_size/(state->memory_width/8) + refresh_cycle)/state->mclk_khz; 490 ainfo->vocc = ainfo->vburst_size - vns*ainfo->vdrain_rate/1000000; 491 ainfo->gocc = ainfo->gr_en? (0-vns*ainfo->gdrain_rate/1000000) : 0; 492 ainfo->mocc = state->enable_mp? 0-vns*ainfo->mdrain_rate/1000000 :0 ; 493 ainfo->cur = VIDEO; 494 nv3_iterate(res_info, state, ainfo); 495 } 496 if (ainfo->converged) 497 { 498 res_info->graphics_lwm = (int)abs(ainfo->wcglwm) + 16; 499 res_info->video_lwm = (int)abs(ainfo->wcvlwm) + 32; 500 res_info->graphics_burst_size = ainfo->gburst_size; 501 res_info->video_burst_size = ainfo->vburst_size; 502 res_info->graphics_hi_priority = (ainfo->priority == GRAPHICS); 503 res_info->media_hi_priority = (ainfo->priority == MPORT); 504 if (res_info->video_lwm > 160) 505 { 506 res_info->graphics_lwm = 256; 507 res_info->video_lwm = 128; 508 res_info->graphics_burst_size = 64; 509 res_info->video_burst_size = 64; 510 res_info->graphics_hi_priority = 0; 511 res_info->media_hi_priority = 0; 512 ainfo->converged = 0; 513 return (0); 514 } 515 if (res_info->video_lwm > 128) 516 { 517 res_info->video_lwm = 128; 518 } 519 return (1); 520 } 521 else 522 { 523 res_info->graphics_lwm = 256; 524 res_info->video_lwm = 128; 525 res_info->graphics_burst_size = 64; 526 res_info->video_burst_size = 64; 527 res_info->graphics_hi_priority = 0; 528 res_info->media_hi_priority = 0; 529 return (0); 530 } 531 } 532 static char nv3_get_param(nv3_fifo_info *res_info, nv3_sim_state * state, nv3_arb_info *ainfo) 533 { 534 int done, g,v, p; 535 536 done = 0; 537 for (p=0; p < 2; p++) 538 { 539 for (g=128 ; g > 32; g= g>> 1) 540 { 541 for (v=128; v >=32; v = v>> 1) 542 { 543 ainfo->priority = p; 544 ainfo->gburst_size = g; 545 ainfo->vburst_size = v; 546 done = nv3_arb(res_info, state,ainfo); 547 if (done && (g==128)) 548 if ((res_info->graphics_lwm + g) > 256) 549 done = 0; 550 if (done) 551 goto Done; 552 } 553 } 554 } 555 556 Done: 557 return done; 558 } 559 static void nv3CalcArbitration 560 ( 561 nv3_fifo_info * res_info, 562 nv3_sim_state * state 563 ) 564 { 565 nv3_fifo_info save_info; 566 nv3_arb_info ainfo; 567 char res_gr, res_vid; 568 569 ainfo.gr_en = 1; 570 ainfo.vid_en = state->enable_video; 571 ainfo.vid_only_once = 0; 572 ainfo.gr_only_once = 0; 573 ainfo.gdrain_rate = (int) state->pclk_khz * (state->pix_bpp/8); 574 ainfo.vdrain_rate = (int) state->pclk_khz * 2; 575 if (state->video_scale != 0) 576 ainfo.vdrain_rate = ainfo.vdrain_rate/state->video_scale; 577 ainfo.mdrain_rate = 33000; 578 res_info->rtl_values = 0; 579 if (!state->gr_during_vid && state->enable_video) 580 { 581 ainfo.gr_only_once = 1; 582 ainfo.gr_en = 1; 583 ainfo.gdrain_rate = 0; 584 res_vid = nv3_get_param(res_info, state, &ainfo); 585 res_vid = ainfo.converged; 586 save_info.video_lwm = res_info->video_lwm; 587 save_info.video_burst_size = res_info->video_burst_size; 588 ainfo.vid_en = 1; 589 ainfo.vid_only_once = 1; 590 ainfo.gr_en = 1; 591 ainfo.gdrain_rate = (int) state->pclk_khz * (state->pix_bpp/8); 592 ainfo.vdrain_rate = 0; 593 res_gr = nv3_get_param(res_info, state, &ainfo); 594 res_gr = ainfo.converged; 595 res_info->video_lwm = save_info.video_lwm; 596 res_info->video_burst_size = save_info.video_burst_size; 597 res_info->valid = res_gr & res_vid; 598 } 599 else 600 { 601 if (!ainfo.gr_en) ainfo.gdrain_rate = 0; 602 if (!ainfo.vid_en) ainfo.vdrain_rate = 0; 603 res_gr = nv3_get_param(res_info, state, &ainfo); 604 res_info->valid = ainfo.converged; 605 } 606 } 607 static void nv3UpdateArbitrationSettings 608 ( 609 unsigned VClk, 610 unsigned pixelDepth, 611 unsigned *burst, 612 unsigned *lwm, 613 RIVA_HW_INST *chip 614 ) 615 { 616 nv3_fifo_info fifo_data; 617 nv3_sim_state sim_data; 618 unsigned int M, N, P, pll, MClk; 619 620 pll = NV_RD32(&chip->PRAMDAC0[0x00000504/4], 0); 621 M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F; 622 MClk = (N * chip->CrystalFreqKHz / M) >> P; 623 sim_data.pix_bpp = (char)pixelDepth; 624 sim_data.enable_video = 0; 625 sim_data.enable_mp = 0; 626 sim_data.video_scale = 1; 627 sim_data.memory_width = (NV_RD32(&chip->PEXTDEV[0x00000000/4], 0) & 0x10) ? 628 128 : 64; 629 sim_data.memory_width = 128; 630 631 sim_data.mem_latency = 9; 632 sim_data.mem_aligned = 1; 633 sim_data.mem_page_miss = 11; 634 sim_data.gr_during_vid = 0; 635 sim_data.pclk_khz = VClk; 636 sim_data.mclk_khz = MClk; 637 nv3CalcArbitration(&fifo_data, &sim_data); 638 if (fifo_data.valid) 639 { 640 int b = fifo_data.graphics_burst_size >> 4; 641 *burst = 0; 642 while (b >>= 1) 643 (*burst)++; 644 *lwm = fifo_data.graphics_lwm >> 3; 645 } 646 else 647 { 648 *lwm = 0x24; 649 *burst = 0x2; 650 } 651 } 652 static void nv4CalcArbitration 653 ( 654 nv4_fifo_info *fifo, 655 nv4_sim_state *arb 656 ) 657 { 658 int data, pagemiss, cas,width, video_enable, bpp; 659 int nvclks, mclks, pclks, vpagemiss, crtpagemiss, vbs; 660 int found, mclk_extra, mclk_loop, cbs, m1, p1; 661 int mclk_freq, pclk_freq, nvclk_freq, mp_enable; 662 int us_m, us_n, us_p, video_drain_rate, crtc_drain_rate; 663 int vpm_us, us_video, vlwm, video_fill_us, cpm_us, us_crt,clwm; 664 665 fifo->valid = 1; 666 pclk_freq = arb->pclk_khz; 667 mclk_freq = arb->mclk_khz; 668 nvclk_freq = arb->nvclk_khz; 669 pagemiss = arb->mem_page_miss; 670 cas = arb->mem_latency; 671 width = arb->memory_width >> 6; 672 video_enable = arb->enable_video; 673 bpp = arb->pix_bpp; 674 mp_enable = arb->enable_mp; 675 clwm = 0; 676 vlwm = 0; 677 cbs = 128; 678 pclks = 2; 679 nvclks = 2; 680 nvclks += 2; 681 nvclks += 1; 682 mclks = 5; 683 mclks += 3; 684 mclks += 1; 685 mclks += cas; 686 mclks += 1; 687 mclks += 1; 688 mclks += 1; 689 mclks += 1; 690 mclk_extra = 3; 691 nvclks += 2; 692 nvclks += 1; 693 nvclks += 1; 694 nvclks += 1; 695 if (mp_enable) 696 mclks+=4; 697 nvclks += 0; 698 pclks += 0; 699 found = 0; 700 vbs = 0; 701 while (found != 1) 702 { 703 fifo->valid = 1; 704 found = 1; 705 mclk_loop = mclks+mclk_extra; 706 us_m = mclk_loop *1000*1000 / mclk_freq; 707 us_n = nvclks*1000*1000 / nvclk_freq; 708 us_p = nvclks*1000*1000 / pclk_freq; 709 if (video_enable) 710 { 711 video_drain_rate = pclk_freq * 2; 712 crtc_drain_rate = pclk_freq * bpp/8; 713 vpagemiss = 2; 714 vpagemiss += 1; 715 crtpagemiss = 2; 716 vpm_us = (vpagemiss * pagemiss)*1000*1000/mclk_freq; 717 if (nvclk_freq * 2 > mclk_freq * width) 718 video_fill_us = cbs*1000*1000 / 16 / nvclk_freq ; 719 else 720 video_fill_us = cbs*1000*1000 / (8 * width) / mclk_freq; 721 us_video = vpm_us + us_m + us_n + us_p + video_fill_us; 722 vlwm = us_video * video_drain_rate/(1000*1000); 723 vlwm++; 724 vbs = 128; 725 if (vlwm > 128) vbs = 64; 726 if (vlwm > (256-64)) vbs = 32; 727 if (nvclk_freq * 2 > mclk_freq * width) 728 video_fill_us = vbs *1000*1000/ 16 / nvclk_freq ; 729 else 730 video_fill_us = vbs*1000*1000 / (8 * width) / mclk_freq; 731 cpm_us = crtpagemiss * pagemiss *1000*1000/ mclk_freq; 732 us_crt = 733 us_video 734 +video_fill_us 735 +cpm_us 736 +us_m + us_n +us_p 737 ; 738 clwm = us_crt * crtc_drain_rate/(1000*1000); 739 clwm++; 740 } 741 else 742 { 743 crtc_drain_rate = pclk_freq * bpp/8; 744 crtpagemiss = 2; 745 crtpagemiss += 1; 746 cpm_us = crtpagemiss * pagemiss *1000*1000/ mclk_freq; 747 us_crt = cpm_us + us_m + us_n + us_p ; 748 clwm = us_crt * crtc_drain_rate/(1000*1000); 749 clwm++; 750 } 751 m1 = clwm + cbs - 512; 752 p1 = m1 * pclk_freq / mclk_freq; 753 p1 = p1 * bpp / 8; 754 if ((p1 < m1) && (m1 > 0)) 755 { 756 fifo->valid = 0; 757 found = 0; 758 if (mclk_extra ==0) found = 1; 759 mclk_extra--; 760 } 761 else if (video_enable) 762 { 763 if ((clwm > 511) || (vlwm > 255)) 764 { 765 fifo->valid = 0; 766 found = 0; 767 if (mclk_extra ==0) found = 1; 768 mclk_extra--; 769 } 770 } 771 else 772 { 773 if (clwm > 519) 774 { 775 fifo->valid = 0; 776 found = 0; 777 if (mclk_extra ==0) found = 1; 778 mclk_extra--; 779 } 780 } 781 if (clwm < 384) clwm = 384; 782 if (vlwm < 128) vlwm = 128; 783 data = (int)(clwm); 784 fifo->graphics_lwm = data; 785 fifo->graphics_burst_size = 128; 786 data = (int)((vlwm+15)); 787 fifo->video_lwm = data; 788 fifo->video_burst_size = vbs; 789 } 790 } 791 static void nv4UpdateArbitrationSettings 792 ( 793 unsigned VClk, 794 unsigned pixelDepth, 795 unsigned *burst, 796 unsigned *lwm, 797 RIVA_HW_INST *chip 798 ) 799 { 800 nv4_fifo_info fifo_data; 801 nv4_sim_state sim_data; 802 unsigned int M, N, P, pll, MClk, NVClk, cfg1; 803 804 pll = NV_RD32(&chip->PRAMDAC0[0x00000504/4], 0); 805 M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F; 806 MClk = (N * chip->CrystalFreqKHz / M) >> P; 807 pll = NV_RD32(&chip->PRAMDAC0[0x00000500/4], 0); 808 M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F; 809 NVClk = (N * chip->CrystalFreqKHz / M) >> P; 810 cfg1 = NV_RD32(&chip->PFB[0x00000204/4], 0); 811 sim_data.pix_bpp = (char)pixelDepth; 812 sim_data.enable_video = 0; 813 sim_data.enable_mp = 0; 814 sim_data.memory_width = (NV_RD32(&chip->PEXTDEV[0x00000000/4], 0) & 0x10) ? 815 128 : 64; 816 sim_data.mem_latency = (char)cfg1 & 0x0F; 817 sim_data.mem_aligned = 1; 818 sim_data.mem_page_miss = (char)(((cfg1 >> 4) &0x0F) + ((cfg1 >> 31) & 0x01)); 819 sim_data.gr_during_vid = 0; 820 sim_data.pclk_khz = VClk; 821 sim_data.mclk_khz = MClk; 822 sim_data.nvclk_khz = NVClk; 823 nv4CalcArbitration(&fifo_data, &sim_data); 824 if (fifo_data.valid) 825 { 826 int b = fifo_data.graphics_burst_size >> 4; 827 *burst = 0; 828 while (b >>= 1) 829 (*burst)++; 830 *lwm = fifo_data.graphics_lwm >> 3; 831 } 832 } 833 static void nv10CalcArbitration 834 ( 835 nv10_fifo_info *fifo, 836 nv10_sim_state *arb 837 ) 838 { 839 int data, pagemiss, cas,width, video_enable, bpp; 840 int nvclks, mclks, pclks, vpagemiss, crtpagemiss, vbs; 841 int nvclk_fill, us_extra; 842 int found, mclk_extra, mclk_loop, cbs, m1; 843 int mclk_freq, pclk_freq, nvclk_freq, mp_enable; 844 int us_m, us_m_min, us_n, us_p, video_drain_rate, crtc_drain_rate; 845 int vus_m, vus_n, vus_p; 846 int vpm_us, us_video, vlwm, cpm_us, us_crt,clwm; 847 int clwm_rnd_down; 848 int craw, m2us, us_pipe, us_pipe_min, vus_pipe, p1clk, p2; 849 int pclks_2_top_fifo, min_mclk_extra; 850 int us_min_mclk_extra; 851 852 fifo->valid = 1; 853 pclk_freq = arb->pclk_khz; /* freq in KHz */ 854 mclk_freq = arb->mclk_khz; 855 nvclk_freq = arb->nvclk_khz; 856 pagemiss = arb->mem_page_miss; 857 cas = arb->mem_latency; 858 width = arb->memory_width/64; 859 video_enable = arb->enable_video; 860 bpp = arb->pix_bpp; 861 mp_enable = arb->enable_mp; 862 clwm = 0; 863 vlwm = 1024; 864 865 cbs = 512; 866 vbs = 512; 867 868 pclks = 4; /* lwm detect. */ 869 870 nvclks = 3; /* lwm -> sync. */ 871 nvclks += 2; /* fbi bus cycles (1 req + 1 busy) */ 872 873 mclks = 1; /* 2 edge sync. may be very close to edge so just put one. */ 874 875 mclks += 1; /* arb_hp_req */ 876 mclks += 5; /* ap_hp_req tiling pipeline */ 877 878 mclks += 2; /* tc_req latency fifo */ 879 mclks += 2; /* fb_cas_n_ memory request to fbio block */ 880 mclks += 7; /* sm_d_rdv data returned from fbio block */ 881 882 /* fb.rd.d.Put_gc need to accumulate 256 bits for read */ 883 if (arb->memory_type == 0) 884 if (arb->memory_width == 64) /* 64 bit bus */ 885 mclks += 4; 886 else 887 mclks += 2; 888 else 889 if (arb->memory_width == 64) /* 64 bit bus */ 890 mclks += 2; 891 else 892 mclks += 1; 893 894 if ((!video_enable) && (arb->memory_width == 128)) 895 { 896 mclk_extra = (bpp == 32) ? 31 : 42; /* Margin of error */ 897 min_mclk_extra = 17; 898 } 899 else 900 { 901 mclk_extra = (bpp == 32) ? 8 : 4; /* Margin of error */ 902 /* mclk_extra = 4; */ /* Margin of error */ 903 min_mclk_extra = 18; 904 } 905 906 nvclks += 1; /* 2 edge sync. may be very close to edge so just put one. */ 907 nvclks += 1; /* fbi_d_rdv_n */ 908 nvclks += 1; /* Fbi_d_rdata */ 909 nvclks += 1; /* crtfifo load */ 910 911 if(mp_enable) 912 mclks+=4; /* Mp can get in with a burst of 8. */ 913 /* Extra clocks determined by heuristics */ 914 915 nvclks += 0; 916 pclks += 0; 917 found = 0; 918 while(found != 1) { 919 fifo->valid = 1; 920 found = 1; 921 mclk_loop = mclks+mclk_extra; 922 us_m = mclk_loop *1000*1000 / mclk_freq; /* Mclk latency in us */ 923 us_m_min = mclks * 1000*1000 / mclk_freq; /* Minimum Mclk latency in us */ 924 us_min_mclk_extra = min_mclk_extra *1000*1000 / mclk_freq; 925 us_n = nvclks*1000*1000 / nvclk_freq;/* nvclk latency in us */ 926 us_p = pclks*1000*1000 / pclk_freq;/* nvclk latency in us */ 927 us_pipe = us_m + us_n + us_p; 928 us_pipe_min = us_m_min + us_n + us_p; 929 us_extra = 0; 930 931 vus_m = mclk_loop *1000*1000 / mclk_freq; /* Mclk latency in us */ 932 vus_n = (4)*1000*1000 / nvclk_freq;/* nvclk latency in us */ 933 vus_p = 0*1000*1000 / pclk_freq;/* pclk latency in us */ 934 vus_pipe = vus_m + vus_n + vus_p; 935 936 if(video_enable) { 937 video_drain_rate = pclk_freq * 4; /* MB/s */ 938 crtc_drain_rate = pclk_freq * bpp/8; /* MB/s */ 939 940 vpagemiss = 1; /* self generating page miss */ 941 vpagemiss += 1; /* One higher priority before */ 942 943 crtpagemiss = 2; /* self generating page miss */ 944 if(mp_enable) 945 crtpagemiss += 1; /* if MA0 conflict */ 946 947 vpm_us = (vpagemiss * pagemiss)*1000*1000/mclk_freq; 948 949 us_video = vpm_us + vus_m; /* Video has separate read return path */ 950 951 cpm_us = crtpagemiss * pagemiss *1000*1000/ mclk_freq; 952 us_crt = 953 us_video /* Wait for video */ 954 +cpm_us /* CRT Page miss */ 955 +us_m + us_n +us_p /* other latency */ 956 ; 957 958 clwm = us_crt * crtc_drain_rate/(1000*1000); 959 clwm++; /* fixed point <= float_point - 1. Fixes that */ 960 } else { 961 crtc_drain_rate = pclk_freq * bpp/8; /* bpp * pclk/8 */ 962 963 crtpagemiss = 1; /* self generating page miss */ 964 crtpagemiss += 1; /* MA0 page miss */ 965 if(mp_enable) 966 crtpagemiss += 1; /* if MA0 conflict */ 967 cpm_us = crtpagemiss * pagemiss *1000*1000/ mclk_freq; 968 us_crt = cpm_us + us_m + us_n + us_p ; 969 clwm = us_crt * crtc_drain_rate/(1000*1000); 970 clwm++; /* fixed point <= float_point - 1. Fixes that */ 971 972 /* 973 // 974 // Another concern, only for high pclks so don't do this 975 // with video: 976 // What happens if the latency to fetch the cbs is so large that 977 // fifo empties. In that case we need to have an alternate clwm value 978 // based off the total burst fetch 979 // 980 us_crt = (cbs * 1000 * 1000)/ (8*width)/mclk_freq ; 981 us_crt = us_crt + us_m + us_n + us_p + (4 * 1000 * 1000)/mclk_freq; 982 clwm_mt = us_crt * crtc_drain_rate/(1000*1000); 983 clwm_mt ++; 984 if(clwm_mt > clwm) 985 clwm = clwm_mt; 986 */ 987 /* Finally, a heuristic check when width == 64 bits */ 988 if(width == 1){ 989 nvclk_fill = nvclk_freq * 8; 990 if(crtc_drain_rate * 100 >= nvclk_fill * 102) 991 clwm = 0xfff; /*Large number to fail */ 992 993 else if(crtc_drain_rate * 100 >= nvclk_fill * 98) { 994 clwm = 1024; 995 cbs = 512; 996 us_extra = (cbs * 1000 * 1000)/ (8*width)/mclk_freq ; 997 } 998 } 999 } 1000 1001 1002 /* 1003 Overfill check: 1004 1005 */ 1006 1007 clwm_rnd_down = ((int)clwm/8)*8; 1008 if (clwm_rnd_down < clwm) 1009 clwm += 8; 1010 1011 m1 = clwm + cbs - 1024; /* Amount of overfill */ 1012 m2us = us_pipe_min + us_min_mclk_extra; 1013 pclks_2_top_fifo = (1024-clwm)/(8*width); 1014 1015 /* pclk cycles to drain */ 1016 p1clk = m2us * pclk_freq/(1000*1000); 1017 p2 = p1clk * bpp / 8; /* bytes drained. */ 1018 1019 if((p2 < m1) && (m1 > 0)) { 1020 fifo->valid = 0; 1021 found = 0; 1022 if(min_mclk_extra == 0) { 1023 if(cbs <= 32) { 1024 found = 1; /* Can't adjust anymore! */ 1025 } else { 1026 cbs = cbs/2; /* reduce the burst size */ 1027 } 1028 } else { 1029 min_mclk_extra--; 1030 } 1031 } else { 1032 if (clwm > 1023){ /* Have some margin */ 1033 fifo->valid = 0; 1034 found = 0; 1035 if(min_mclk_extra == 0) 1036 found = 1; /* Can't adjust anymore! */ 1037 else 1038 min_mclk_extra--; 1039 } 1040 } 1041 craw = clwm; 1042 1043 if(clwm < (1024-cbs+8)) clwm = 1024-cbs+8; 1044 data = (int)(clwm); 1045 /* printf("CRT LWM: %f bytes, prog: 0x%x, bs: 256\n", clwm, data ); */ 1046 fifo->graphics_lwm = data; fifo->graphics_burst_size = cbs; 1047 1048 /* printf("VID LWM: %f bytes, prog: 0x%x, bs: %d\n, ", vlwm, data, vbs ); */ 1049 fifo->video_lwm = 1024; fifo->video_burst_size = 512; 1050 } 1051 } 1052 static void nv10UpdateArbitrationSettings 1053 ( 1054 unsigned VClk, 1055 unsigned pixelDepth, 1056 unsigned *burst, 1057 unsigned *lwm, 1058 RIVA_HW_INST *chip 1059 ) 1060 { 1061 nv10_fifo_info fifo_data; 1062 nv10_sim_state sim_data; 1063 unsigned int M, N, P, pll, MClk, NVClk, cfg1; 1064 1065 pll = NV_RD32(&chip->PRAMDAC0[0x00000504/4], 0); 1066 M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F; 1067 MClk = (N * chip->CrystalFreqKHz / M) >> P; 1068 pll = NV_RD32(&chip->PRAMDAC0[0x00000500/4], 0); 1069 M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F; 1070 NVClk = (N * chip->CrystalFreqKHz / M) >> P; 1071 cfg1 = NV_RD32(&chip->PFB[0x00000204/4], 0); 1072 sim_data.pix_bpp = (char)pixelDepth; 1073 sim_data.enable_video = 0; 1074 sim_data.enable_mp = 0; 1075 sim_data.memory_type = (NV_RD32(&chip->PFB[0x00000200/4], 0) & 0x01) ? 1076 1 : 0; 1077 sim_data.memory_width = (NV_RD32(&chip->PEXTDEV[0x00000000/4], 0) & 0x10) ? 1078 128 : 64; 1079 sim_data.mem_latency = (char)cfg1 & 0x0F; 1080 sim_data.mem_aligned = 1; 1081 sim_data.mem_page_miss = (char)(((cfg1 >> 4) &0x0F) + ((cfg1 >> 31) & 0x01)); 1082 sim_data.gr_during_vid = 0; 1083 sim_data.pclk_khz = VClk; 1084 sim_data.mclk_khz = MClk; 1085 sim_data.nvclk_khz = NVClk; 1086 nv10CalcArbitration(&fifo_data, &sim_data); 1087 if (fifo_data.valid) 1088 { 1089 int b = fifo_data.graphics_burst_size >> 4; 1090 *burst = 0; 1091 while (b >>= 1) 1092 (*burst)++; 1093 *lwm = fifo_data.graphics_lwm >> 3; 1094 } 1095 } 1096 1097 static void nForceUpdateArbitrationSettings 1098 ( 1099 unsigned VClk, 1100 unsigned pixelDepth, 1101 unsigned *burst, 1102 unsigned *lwm, 1103 RIVA_HW_INST *chip, 1104 struct pci_dev *pdev 1105 ) 1106 { 1107 nv10_fifo_info fifo_data; 1108 nv10_sim_state sim_data; 1109 unsigned int M, N, P, pll, MClk, NVClk; 1110 unsigned int uMClkPostDiv; 1111 struct pci_dev *dev; 1112 int domain = pci_domain_nr(pdev->bus); 1113 1114 dev = pci_get_domain_bus_and_slot(domain, 0, 3); 1115 pci_read_config_dword(dev, 0x6C, &uMClkPostDiv); 1116 pci_dev_put(dev); 1117 uMClkPostDiv = (uMClkPostDiv >> 8) & 0xf; 1118 1119 if(!uMClkPostDiv) uMClkPostDiv = 4; 1120 MClk = 400000 / uMClkPostDiv; 1121 1122 pll = NV_RD32(&chip->PRAMDAC0[0x00000500/4], 0); 1123 M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F; 1124 NVClk = (N * chip->CrystalFreqKHz / M) >> P; 1125 sim_data.pix_bpp = (char)pixelDepth; 1126 sim_data.enable_video = 0; 1127 sim_data.enable_mp = 0; 1128 1129 dev = pci_get_domain_bus_and_slot(domain, 0, 1); 1130 pci_read_config_dword(dev, 0x7C, &sim_data.memory_type); 1131 pci_dev_put(dev); 1132 sim_data.memory_type = (sim_data.memory_type >> 12) & 1; 1133 1134 sim_data.memory_width = 64; 1135 sim_data.mem_latency = 3; 1136 sim_data.mem_aligned = 1; 1137 sim_data.mem_page_miss = 10; 1138 sim_data.gr_during_vid = 0; 1139 sim_data.pclk_khz = VClk; 1140 sim_data.mclk_khz = MClk; 1141 sim_data.nvclk_khz = NVClk; 1142 nv10CalcArbitration(&fifo_data, &sim_data); 1143 if (fifo_data.valid) 1144 { 1145 int b = fifo_data.graphics_burst_size >> 4; 1146 *burst = 0; 1147 while (b >>= 1) 1148 (*burst)++; 1149 *lwm = fifo_data.graphics_lwm >> 3; 1150 } 1151 } 1152 1153 /****************************************************************************\ 1154 * * 1155 * RIVA Mode State Routines * 1156 * * 1157 \****************************************************************************/ 1158 1159 /* 1160 * Calculate the Video Clock parameters for the PLL. 1161 */ 1162 static int CalcVClock 1163 ( 1164 int clockIn, 1165 int *clockOut, 1166 int *mOut, 1167 int *nOut, 1168 int *pOut, 1169 RIVA_HW_INST *chip 1170 ) 1171 { 1172 unsigned lowM, highM, highP; 1173 unsigned DeltaNew, DeltaOld; 1174 unsigned VClk, Freq; 1175 unsigned M, N, P; 1176 1177 DeltaOld = 0xFFFFFFFF; 1178 1179 VClk = (unsigned)clockIn; 1180 1181 if (chip->CrystalFreqKHz == 13500) 1182 { 1183 lowM = 7; 1184 highM = 13 - (chip->Architecture == NV_ARCH_03); 1185 } 1186 else 1187 { 1188 lowM = 8; 1189 highM = 14 - (chip->Architecture == NV_ARCH_03); 1190 } 1191 1192 highP = 4 - (chip->Architecture == NV_ARCH_03); 1193 for (P = 0; P <= highP; P ++) 1194 { 1195 Freq = VClk << P; 1196 if ((Freq >= 128000) && (Freq <= chip->MaxVClockFreqKHz)) 1197 { 1198 for (M = lowM; M <= highM; M++) 1199 { 1200 N = (VClk << P) * M / chip->CrystalFreqKHz; 1201 if(N <= 255) { 1202 Freq = (chip->CrystalFreqKHz * N / M) >> P; 1203 if (Freq > VClk) 1204 DeltaNew = Freq - VClk; 1205 else 1206 DeltaNew = VClk - Freq; 1207 if (DeltaNew < DeltaOld) 1208 { 1209 *mOut = M; 1210 *nOut = N; 1211 *pOut = P; 1212 *clockOut = Freq; 1213 DeltaOld = DeltaNew; 1214 } 1215 } 1216 } 1217 } 1218 } 1219 1220 /* non-zero: M/N/P/clock values assigned. zero: error (not set) */ 1221 return (DeltaOld != 0xFFFFFFFF); 1222 } 1223 /* 1224 * Calculate extended mode parameters (SVGA) and save in a 1225 * mode state structure. 1226 */ 1227 int CalcStateExt 1228 ( 1229 RIVA_HW_INST *chip, 1230 RIVA_HW_STATE *state, 1231 struct pci_dev *pdev, 1232 int bpp, 1233 int width, 1234 int hDisplaySize, 1235 int height, 1236 int dotClock 1237 ) 1238 { 1239 int pixelDepth; 1240 int VClk, m, n, p; 1241 1242 /* 1243 * Save mode parameters. 1244 */ 1245 state->bpp = bpp; /* this is not bitsPerPixel, it's 8,15,16,32 */ 1246 state->width = width; 1247 state->height = height; 1248 /* 1249 * Extended RIVA registers. 1250 */ 1251 pixelDepth = (bpp + 1)/8; 1252 if (!CalcVClock(dotClock, &VClk, &m, &n, &p, chip)) 1253 return -EINVAL; 1254 1255 switch (chip->Architecture) 1256 { 1257 case NV_ARCH_03: 1258 nv3UpdateArbitrationSettings(VClk, 1259 pixelDepth * 8, 1260 &(state->arbitration0), 1261 &(state->arbitration1), 1262 chip); 1263 state->cursor0 = 0x00; 1264 state->cursor1 = 0x78; 1265 state->cursor2 = 0x00000000; 1266 state->pllsel = 0x10010100; 1267 state->config = ((width + 31)/32) 1268 | (((pixelDepth > 2) ? 3 : pixelDepth) << 8) 1269 | 0x1000; 1270 state->general = 0x00100100; 1271 state->repaint1 = hDisplaySize < 1280 ? 0x06 : 0x02; 1272 break; 1273 case NV_ARCH_04: 1274 nv4UpdateArbitrationSettings(VClk, 1275 pixelDepth * 8, 1276 &(state->arbitration0), 1277 &(state->arbitration1), 1278 chip); 1279 state->cursor0 = 0x00; 1280 state->cursor1 = 0xFC; 1281 state->cursor2 = 0x00000000; 1282 state->pllsel = 0x10000700; 1283 state->config = 0x00001114; 1284 state->general = bpp == 16 ? 0x00101100 : 0x00100100; 1285 state->repaint1 = hDisplaySize < 1280 ? 0x04 : 0x00; 1286 break; 1287 case NV_ARCH_10: 1288 case NV_ARCH_20: 1289 case NV_ARCH_30: 1290 if((chip->Chipset == NV_CHIP_IGEFORCE2) || 1291 (chip->Chipset == NV_CHIP_0x01F0)) 1292 { 1293 nForceUpdateArbitrationSettings(VClk, 1294 pixelDepth * 8, 1295 &(state->arbitration0), 1296 &(state->arbitration1), 1297 chip, pdev); 1298 } else { 1299 nv10UpdateArbitrationSettings(VClk, 1300 pixelDepth * 8, 1301 &(state->arbitration0), 1302 &(state->arbitration1), 1303 chip); 1304 } 1305 state->cursor0 = 0x80 | (chip->CursorStart >> 17); 1306 state->cursor1 = (chip->CursorStart >> 11) << 2; 1307 state->cursor2 = chip->CursorStart >> 24; 1308 state->pllsel = 0x10000700; 1309 state->config = NV_RD32(&chip->PFB[0x00000200/4], 0); 1310 state->general = bpp == 16 ? 0x00101100 : 0x00100100; 1311 state->repaint1 = hDisplaySize < 1280 ? 0x04 : 0x00; 1312 break; 1313 } 1314 1315 /* Paul Richards: below if block borks things in kernel for some reason */ 1316 /* Tony: Below is needed to set hardware in DirectColor */ 1317 if((bpp != 8) && (chip->Architecture != NV_ARCH_03)) 1318 state->general |= 0x00000030; 1319 1320 state->vpll = (p << 16) | (n << 8) | m; 1321 state->repaint0 = (((width/8)*pixelDepth) & 0x700) >> 3; 1322 state->pixel = pixelDepth > 2 ? 3 : pixelDepth; 1323 state->offset0 = 1324 state->offset1 = 1325 state->offset2 = 1326 state->offset3 = 0; 1327 state->pitch0 = 1328 state->pitch1 = 1329 state->pitch2 = 1330 state->pitch3 = pixelDepth * width; 1331 1332 return 0; 1333 } 1334 /* 1335 * Load fixed function state and pre-calculated/stored state. 1336 */ 1337 #define LOAD_FIXED_STATE(tbl,dev) \ 1338 for (i = 0; i < sizeof(tbl##Table##dev)/8; i++) \ 1339 NV_WR32(&chip->dev[tbl##Table##dev[i][0]], 0, tbl##Table##dev[i][1]) 1340 #define LOAD_FIXED_STATE_8BPP(tbl,dev) \ 1341 for (i = 0; i < sizeof(tbl##Table##dev##_8BPP)/8; i++) \ 1342 NV_WR32(&chip->dev[tbl##Table##dev##_8BPP[i][0]], 0, tbl##Table##dev##_8BPP[i][1]) 1343 #define LOAD_FIXED_STATE_15BPP(tbl,dev) \ 1344 for (i = 0; i < sizeof(tbl##Table##dev##_15BPP)/8; i++) \ 1345 NV_WR32(&chip->dev[tbl##Table##dev##_15BPP[i][0]], 0, tbl##Table##dev##_15BPP[i][1]) 1346 #define LOAD_FIXED_STATE_16BPP(tbl,dev) \ 1347 for (i = 0; i < sizeof(tbl##Table##dev##_16BPP)/8; i++) \ 1348 NV_WR32(&chip->dev[tbl##Table##dev##_16BPP[i][0]], 0, tbl##Table##dev##_16BPP[i][1]) 1349 #define LOAD_FIXED_STATE_32BPP(tbl,dev) \ 1350 for (i = 0; i < sizeof(tbl##Table##dev##_32BPP)/8; i++) \ 1351 NV_WR32(&chip->dev[tbl##Table##dev##_32BPP[i][0]], 0, tbl##Table##dev##_32BPP[i][1]) 1352 1353 static void UpdateFifoState 1354 ( 1355 RIVA_HW_INST *chip 1356 ) 1357 { 1358 int i; 1359 1360 switch (chip->Architecture) 1361 { 1362 case NV_ARCH_04: 1363 LOAD_FIXED_STATE(nv4,FIFO); 1364 chip->Tri03 = NULL; 1365 chip->Tri05 = (RivaTexturedTriangle05 __iomem *)&(chip->FIFO[0x0000E000/4]); 1366 break; 1367 case NV_ARCH_10: 1368 case NV_ARCH_20: 1369 case NV_ARCH_30: 1370 /* 1371 * Initialize state for the RivaTriangle3D05 routines. 1372 */ 1373 LOAD_FIXED_STATE(nv10tri05,PGRAPH); 1374 LOAD_FIXED_STATE(nv10,FIFO); 1375 chip->Tri03 = NULL; 1376 chip->Tri05 = (RivaTexturedTriangle05 __iomem *)&(chip->FIFO[0x0000E000/4]); 1377 break; 1378 } 1379 } 1380 static void LoadStateExt 1381 ( 1382 RIVA_HW_INST *chip, 1383 RIVA_HW_STATE *state 1384 ) 1385 { 1386 int i; 1387 1388 /* 1389 * Load HW fixed function state. 1390 */ 1391 LOAD_FIXED_STATE(Riva,PMC); 1392 LOAD_FIXED_STATE(Riva,PTIMER); 1393 switch (chip->Architecture) 1394 { 1395 case NV_ARCH_03: 1396 /* 1397 * Make sure frame buffer config gets set before loading PRAMIN. 1398 */ 1399 NV_WR32(chip->PFB, 0x00000200, state->config); 1400 LOAD_FIXED_STATE(nv3,PFIFO); 1401 LOAD_FIXED_STATE(nv3,PRAMIN); 1402 LOAD_FIXED_STATE(nv3,PGRAPH); 1403 switch (state->bpp) 1404 { 1405 case 15: 1406 case 16: 1407 LOAD_FIXED_STATE_15BPP(nv3,PRAMIN); 1408 LOAD_FIXED_STATE_15BPP(nv3,PGRAPH); 1409 chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]); 1410 break; 1411 case 24: 1412 case 32: 1413 LOAD_FIXED_STATE_32BPP(nv3,PRAMIN); 1414 LOAD_FIXED_STATE_32BPP(nv3,PGRAPH); 1415 chip->Tri03 = NULL; 1416 break; 1417 case 8: 1418 default: 1419 LOAD_FIXED_STATE_8BPP(nv3,PRAMIN); 1420 LOAD_FIXED_STATE_8BPP(nv3,PGRAPH); 1421 chip->Tri03 = NULL; 1422 break; 1423 } 1424 for (i = 0x00000; i < 0x00800; i++) 1425 NV_WR32(&chip->PRAMIN[0x00000502 + i], 0, (i << 12) | 0x03); 1426 NV_WR32(chip->PGRAPH, 0x00000630, state->offset0); 1427 NV_WR32(chip->PGRAPH, 0x00000634, state->offset1); 1428 NV_WR32(chip->PGRAPH, 0x00000638, state->offset2); 1429 NV_WR32(chip->PGRAPH, 0x0000063C, state->offset3); 1430 NV_WR32(chip->PGRAPH, 0x00000650, state->pitch0); 1431 NV_WR32(chip->PGRAPH, 0x00000654, state->pitch1); 1432 NV_WR32(chip->PGRAPH, 0x00000658, state->pitch2); 1433 NV_WR32(chip->PGRAPH, 0x0000065C, state->pitch3); 1434 break; 1435 case NV_ARCH_04: 1436 /* 1437 * Make sure frame buffer config gets set before loading PRAMIN. 1438 */ 1439 NV_WR32(chip->PFB, 0x00000200, state->config); 1440 LOAD_FIXED_STATE(nv4,PFIFO); 1441 LOAD_FIXED_STATE(nv4,PRAMIN); 1442 LOAD_FIXED_STATE(nv4,PGRAPH); 1443 switch (state->bpp) 1444 { 1445 case 15: 1446 LOAD_FIXED_STATE_15BPP(nv4,PRAMIN); 1447 LOAD_FIXED_STATE_15BPP(nv4,PGRAPH); 1448 chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]); 1449 break; 1450 case 16: 1451 LOAD_FIXED_STATE_16BPP(nv4,PRAMIN); 1452 LOAD_FIXED_STATE_16BPP(nv4,PGRAPH); 1453 chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]); 1454 break; 1455 case 24: 1456 case 32: 1457 LOAD_FIXED_STATE_32BPP(nv4,PRAMIN); 1458 LOAD_FIXED_STATE_32BPP(nv4,PGRAPH); 1459 chip->Tri03 = NULL; 1460 break; 1461 case 8: 1462 default: 1463 LOAD_FIXED_STATE_8BPP(nv4,PRAMIN); 1464 LOAD_FIXED_STATE_8BPP(nv4,PGRAPH); 1465 chip->Tri03 = NULL; 1466 break; 1467 } 1468 NV_WR32(chip->PGRAPH, 0x00000640, state->offset0); 1469 NV_WR32(chip->PGRAPH, 0x00000644, state->offset1); 1470 NV_WR32(chip->PGRAPH, 0x00000648, state->offset2); 1471 NV_WR32(chip->PGRAPH, 0x0000064C, state->offset3); 1472 NV_WR32(chip->PGRAPH, 0x00000670, state->pitch0); 1473 NV_WR32(chip->PGRAPH, 0x00000674, state->pitch1); 1474 NV_WR32(chip->PGRAPH, 0x00000678, state->pitch2); 1475 NV_WR32(chip->PGRAPH, 0x0000067C, state->pitch3); 1476 break; 1477 case NV_ARCH_10: 1478 case NV_ARCH_20: 1479 case NV_ARCH_30: 1480 if(chip->twoHeads) { 1481 VGA_WR08(chip->PCIO, 0x03D4, 0x44); 1482 VGA_WR08(chip->PCIO, 0x03D5, state->crtcOwner); 1483 chip->LockUnlock(chip, 0); 1484 } 1485 1486 LOAD_FIXED_STATE(nv10,PFIFO); 1487 LOAD_FIXED_STATE(nv10,PRAMIN); 1488 LOAD_FIXED_STATE(nv10,PGRAPH); 1489 switch (state->bpp) 1490 { 1491 case 15: 1492 LOAD_FIXED_STATE_15BPP(nv10,PRAMIN); 1493 LOAD_FIXED_STATE_15BPP(nv10,PGRAPH); 1494 chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]); 1495 break; 1496 case 16: 1497 LOAD_FIXED_STATE_16BPP(nv10,PRAMIN); 1498 LOAD_FIXED_STATE_16BPP(nv10,PGRAPH); 1499 chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]); 1500 break; 1501 case 24: 1502 case 32: 1503 LOAD_FIXED_STATE_32BPP(nv10,PRAMIN); 1504 LOAD_FIXED_STATE_32BPP(nv10,PGRAPH); 1505 chip->Tri03 = NULL; 1506 break; 1507 case 8: 1508 default: 1509 LOAD_FIXED_STATE_8BPP(nv10,PRAMIN); 1510 LOAD_FIXED_STATE_8BPP(nv10,PGRAPH); 1511 chip->Tri03 = NULL; 1512 break; 1513 } 1514 1515 if(chip->Architecture == NV_ARCH_10) { 1516 NV_WR32(chip->PGRAPH, 0x00000640, state->offset0); 1517 NV_WR32(chip->PGRAPH, 0x00000644, state->offset1); 1518 NV_WR32(chip->PGRAPH, 0x00000648, state->offset2); 1519 NV_WR32(chip->PGRAPH, 0x0000064C, state->offset3); 1520 NV_WR32(chip->PGRAPH, 0x00000670, state->pitch0); 1521 NV_WR32(chip->PGRAPH, 0x00000674, state->pitch1); 1522 NV_WR32(chip->PGRAPH, 0x00000678, state->pitch2); 1523 NV_WR32(chip->PGRAPH, 0x0000067C, state->pitch3); 1524 NV_WR32(chip->PGRAPH, 0x00000680, state->pitch3); 1525 } else { 1526 NV_WR32(chip->PGRAPH, 0x00000820, state->offset0); 1527 NV_WR32(chip->PGRAPH, 0x00000824, state->offset1); 1528 NV_WR32(chip->PGRAPH, 0x00000828, state->offset2); 1529 NV_WR32(chip->PGRAPH, 0x0000082C, state->offset3); 1530 NV_WR32(chip->PGRAPH, 0x00000850, state->pitch0); 1531 NV_WR32(chip->PGRAPH, 0x00000854, state->pitch1); 1532 NV_WR32(chip->PGRAPH, 0x00000858, state->pitch2); 1533 NV_WR32(chip->PGRAPH, 0x0000085C, state->pitch3); 1534 NV_WR32(chip->PGRAPH, 0x00000860, state->pitch3); 1535 NV_WR32(chip->PGRAPH, 0x00000864, state->pitch3); 1536 NV_WR32(chip->PGRAPH, 0x000009A4, NV_RD32(chip->PFB, 0x00000200)); 1537 NV_WR32(chip->PGRAPH, 0x000009A8, NV_RD32(chip->PFB, 0x00000204)); 1538 } 1539 if(chip->twoHeads) { 1540 NV_WR32(chip->PCRTC0, 0x00000860, state->head); 1541 NV_WR32(chip->PCRTC0, 0x00002860, state->head2); 1542 } 1543 NV_WR32(chip->PRAMDAC, 0x00000404, NV_RD32(chip->PRAMDAC, 0x00000404) | (1 << 25)); 1544 1545 NV_WR32(chip->PMC, 0x00008704, 1); 1546 NV_WR32(chip->PMC, 0x00008140, 0); 1547 NV_WR32(chip->PMC, 0x00008920, 0); 1548 NV_WR32(chip->PMC, 0x00008924, 0); 1549 NV_WR32(chip->PMC, 0x00008908, 0x01ffffff); 1550 NV_WR32(chip->PMC, 0x0000890C, 0x01ffffff); 1551 NV_WR32(chip->PMC, 0x00001588, 0); 1552 1553 NV_WR32(chip->PFB, 0x00000240, 0); 1554 NV_WR32(chip->PFB, 0x00000250, 0); 1555 NV_WR32(chip->PFB, 0x00000260, 0); 1556 NV_WR32(chip->PFB, 0x00000270, 0); 1557 NV_WR32(chip->PFB, 0x00000280, 0); 1558 NV_WR32(chip->PFB, 0x00000290, 0); 1559 NV_WR32(chip->PFB, 0x000002A0, 0); 1560 NV_WR32(chip->PFB, 0x000002B0, 0); 1561 1562 NV_WR32(chip->PGRAPH, 0x00000B00, NV_RD32(chip->PFB, 0x00000240)); 1563 NV_WR32(chip->PGRAPH, 0x00000B04, NV_RD32(chip->PFB, 0x00000244)); 1564 NV_WR32(chip->PGRAPH, 0x00000B08, NV_RD32(chip->PFB, 0x00000248)); 1565 NV_WR32(chip->PGRAPH, 0x00000B0C, NV_RD32(chip->PFB, 0x0000024C)); 1566 NV_WR32(chip->PGRAPH, 0x00000B10, NV_RD32(chip->PFB, 0x00000250)); 1567 NV_WR32(chip->PGRAPH, 0x00000B14, NV_RD32(chip->PFB, 0x00000254)); 1568 NV_WR32(chip->PGRAPH, 0x00000B18, NV_RD32(chip->PFB, 0x00000258)); 1569 NV_WR32(chip->PGRAPH, 0x00000B1C, NV_RD32(chip->PFB, 0x0000025C)); 1570 NV_WR32(chip->PGRAPH, 0x00000B20, NV_RD32(chip->PFB, 0x00000260)); 1571 NV_WR32(chip->PGRAPH, 0x00000B24, NV_RD32(chip->PFB, 0x00000264)); 1572 NV_WR32(chip->PGRAPH, 0x00000B28, NV_RD32(chip->PFB, 0x00000268)); 1573 NV_WR32(chip->PGRAPH, 0x00000B2C, NV_RD32(chip->PFB, 0x0000026C)); 1574 NV_WR32(chip->PGRAPH, 0x00000B30, NV_RD32(chip->PFB, 0x00000270)); 1575 NV_WR32(chip->PGRAPH, 0x00000B34, NV_RD32(chip->PFB, 0x00000274)); 1576 NV_WR32(chip->PGRAPH, 0x00000B38, NV_RD32(chip->PFB, 0x00000278)); 1577 NV_WR32(chip->PGRAPH, 0x00000B3C, NV_RD32(chip->PFB, 0x0000027C)); 1578 NV_WR32(chip->PGRAPH, 0x00000B40, NV_RD32(chip->PFB, 0x00000280)); 1579 NV_WR32(chip->PGRAPH, 0x00000B44, NV_RD32(chip->PFB, 0x00000284)); 1580 NV_WR32(chip->PGRAPH, 0x00000B48, NV_RD32(chip->PFB, 0x00000288)); 1581 NV_WR32(chip->PGRAPH, 0x00000B4C, NV_RD32(chip->PFB, 0x0000028C)); 1582 NV_WR32(chip->PGRAPH, 0x00000B50, NV_RD32(chip->PFB, 0x00000290)); 1583 NV_WR32(chip->PGRAPH, 0x00000B54, NV_RD32(chip->PFB, 0x00000294)); 1584 NV_WR32(chip->PGRAPH, 0x00000B58, NV_RD32(chip->PFB, 0x00000298)); 1585 NV_WR32(chip->PGRAPH, 0x00000B5C, NV_RD32(chip->PFB, 0x0000029C)); 1586 NV_WR32(chip->PGRAPH, 0x00000B60, NV_RD32(chip->PFB, 0x000002A0)); 1587 NV_WR32(chip->PGRAPH, 0x00000B64, NV_RD32(chip->PFB, 0x000002A4)); 1588 NV_WR32(chip->PGRAPH, 0x00000B68, NV_RD32(chip->PFB, 0x000002A8)); 1589 NV_WR32(chip->PGRAPH, 0x00000B6C, NV_RD32(chip->PFB, 0x000002AC)); 1590 NV_WR32(chip->PGRAPH, 0x00000B70, NV_RD32(chip->PFB, 0x000002B0)); 1591 NV_WR32(chip->PGRAPH, 0x00000B74, NV_RD32(chip->PFB, 0x000002B4)); 1592 NV_WR32(chip->PGRAPH, 0x00000B78, NV_RD32(chip->PFB, 0x000002B8)); 1593 NV_WR32(chip->PGRAPH, 0x00000B7C, NV_RD32(chip->PFB, 0x000002BC)); 1594 NV_WR32(chip->PGRAPH, 0x00000F40, 0x10000000); 1595 NV_WR32(chip->PGRAPH, 0x00000F44, 0x00000000); 1596 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00000040); 1597 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000008); 1598 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00000200); 1599 for (i = 0; i < (3*16); i++) 1600 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); 1601 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00000040); 1602 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); 1603 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00000800); 1604 for (i = 0; i < (16*16); i++) 1605 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); 1606 NV_WR32(chip->PGRAPH, 0x00000F40, 0x30000000); 1607 NV_WR32(chip->PGRAPH, 0x00000F44, 0x00000004); 1608 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00006400); 1609 for (i = 0; i < (59*4); i++) 1610 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); 1611 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00006800); 1612 for (i = 0; i < (47*4); i++) 1613 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); 1614 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00006C00); 1615 for (i = 0; i < (3*4); i++) 1616 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); 1617 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00007000); 1618 for (i = 0; i < (19*4); i++) 1619 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); 1620 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00007400); 1621 for (i = 0; i < (12*4); i++) 1622 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); 1623 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00007800); 1624 for (i = 0; i < (12*4); i++) 1625 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); 1626 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00004400); 1627 for (i = 0; i < (8*4); i++) 1628 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); 1629 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00000000); 1630 for (i = 0; i < 16; i++) 1631 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); 1632 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00000040); 1633 for (i = 0; i < 4; i++) 1634 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); 1635 1636 NV_WR32(chip->PCRTC, 0x00000810, state->cursorConfig); 1637 1638 if(chip->flatPanel) { 1639 if((chip->Chipset & 0x0ff0) == 0x0110) { 1640 NV_WR32(chip->PRAMDAC, 0x0528, state->dither); 1641 } else 1642 if((chip->Chipset & 0x0ff0) >= 0x0170) { 1643 NV_WR32(chip->PRAMDAC, 0x083C, state->dither); 1644 } 1645 1646 VGA_WR08(chip->PCIO, 0x03D4, 0x53); 1647 VGA_WR08(chip->PCIO, 0x03D5, 0); 1648 VGA_WR08(chip->PCIO, 0x03D4, 0x54); 1649 VGA_WR08(chip->PCIO, 0x03D5, 0); 1650 VGA_WR08(chip->PCIO, 0x03D4, 0x21); 1651 VGA_WR08(chip->PCIO, 0x03D5, 0xfa); 1652 } 1653 1654 VGA_WR08(chip->PCIO, 0x03D4, 0x41); 1655 VGA_WR08(chip->PCIO, 0x03D5, state->extra); 1656 } 1657 LOAD_FIXED_STATE(Riva,FIFO); 1658 UpdateFifoState(chip); 1659 /* 1660 * Load HW mode state. 1661 */ 1662 VGA_WR08(chip->PCIO, 0x03D4, 0x19); 1663 VGA_WR08(chip->PCIO, 0x03D5, state->repaint0); 1664 VGA_WR08(chip->PCIO, 0x03D4, 0x1A); 1665 VGA_WR08(chip->PCIO, 0x03D5, state->repaint1); 1666 VGA_WR08(chip->PCIO, 0x03D4, 0x25); 1667 VGA_WR08(chip->PCIO, 0x03D5, state->screen); 1668 VGA_WR08(chip->PCIO, 0x03D4, 0x28); 1669 VGA_WR08(chip->PCIO, 0x03D5, state->pixel); 1670 VGA_WR08(chip->PCIO, 0x03D4, 0x2D); 1671 VGA_WR08(chip->PCIO, 0x03D5, state->horiz); 1672 VGA_WR08(chip->PCIO, 0x03D4, 0x1B); 1673 VGA_WR08(chip->PCIO, 0x03D5, state->arbitration0); 1674 VGA_WR08(chip->PCIO, 0x03D4, 0x20); 1675 VGA_WR08(chip->PCIO, 0x03D5, state->arbitration1); 1676 VGA_WR08(chip->PCIO, 0x03D4, 0x30); 1677 VGA_WR08(chip->PCIO, 0x03D5, state->cursor0); 1678 VGA_WR08(chip->PCIO, 0x03D4, 0x31); 1679 VGA_WR08(chip->PCIO, 0x03D5, state->cursor1); 1680 VGA_WR08(chip->PCIO, 0x03D4, 0x2F); 1681 VGA_WR08(chip->PCIO, 0x03D5, state->cursor2); 1682 VGA_WR08(chip->PCIO, 0x03D4, 0x39); 1683 VGA_WR08(chip->PCIO, 0x03D5, state->interlace); 1684 1685 if(!chip->flatPanel) { 1686 NV_WR32(chip->PRAMDAC0, 0x00000508, state->vpll); 1687 NV_WR32(chip->PRAMDAC0, 0x0000050C, state->pllsel); 1688 if(chip->twoHeads) 1689 NV_WR32(chip->PRAMDAC0, 0x00000520, state->vpll2); 1690 } else { 1691 NV_WR32(chip->PRAMDAC, 0x00000848 , state->scale); 1692 } 1693 NV_WR32(chip->PRAMDAC, 0x00000600 , state->general); 1694 1695 /* 1696 * Turn off VBlank enable and reset. 1697 */ 1698 NV_WR32(chip->PCRTC, 0x00000140, 0); 1699 NV_WR32(chip->PCRTC, 0x00000100, chip->VBlankBit); 1700 /* 1701 * Set interrupt enable. 1702 */ 1703 NV_WR32(chip->PMC, 0x00000140, chip->EnableIRQ & 0x01); 1704 /* 1705 * Set current state pointer. 1706 */ 1707 chip->CurrentState = state; 1708 /* 1709 * Reset FIFO free and empty counts. 1710 */ 1711 chip->FifoFreeCount = 0; 1712 /* Free count from first subchannel */ 1713 chip->FifoEmptyCount = NV_RD32(&chip->Rop->FifoFree, 0); 1714 } 1715 static void UnloadStateExt 1716 ( 1717 RIVA_HW_INST *chip, 1718 RIVA_HW_STATE *state 1719 ) 1720 { 1721 /* 1722 * Save current HW state. 1723 */ 1724 VGA_WR08(chip->PCIO, 0x03D4, 0x19); 1725 state->repaint0 = VGA_RD08(chip->PCIO, 0x03D5); 1726 VGA_WR08(chip->PCIO, 0x03D4, 0x1A); 1727 state->repaint1 = VGA_RD08(chip->PCIO, 0x03D5); 1728 VGA_WR08(chip->PCIO, 0x03D4, 0x25); 1729 state->screen = VGA_RD08(chip->PCIO, 0x03D5); 1730 VGA_WR08(chip->PCIO, 0x03D4, 0x28); 1731 state->pixel = VGA_RD08(chip->PCIO, 0x03D5); 1732 VGA_WR08(chip->PCIO, 0x03D4, 0x2D); 1733 state->horiz = VGA_RD08(chip->PCIO, 0x03D5); 1734 VGA_WR08(chip->PCIO, 0x03D4, 0x1B); 1735 state->arbitration0 = VGA_RD08(chip->PCIO, 0x03D5); 1736 VGA_WR08(chip->PCIO, 0x03D4, 0x20); 1737 state->arbitration1 = VGA_RD08(chip->PCIO, 0x03D5); 1738 VGA_WR08(chip->PCIO, 0x03D4, 0x30); 1739 state->cursor0 = VGA_RD08(chip->PCIO, 0x03D5); 1740 VGA_WR08(chip->PCIO, 0x03D4, 0x31); 1741 state->cursor1 = VGA_RD08(chip->PCIO, 0x03D5); 1742 VGA_WR08(chip->PCIO, 0x03D4, 0x2F); 1743 state->cursor2 = VGA_RD08(chip->PCIO, 0x03D5); 1744 VGA_WR08(chip->PCIO, 0x03D4, 0x39); 1745 state->interlace = VGA_RD08(chip->PCIO, 0x03D5); 1746 state->vpll = NV_RD32(chip->PRAMDAC0, 0x00000508); 1747 state->vpll2 = NV_RD32(chip->PRAMDAC0, 0x00000520); 1748 state->pllsel = NV_RD32(chip->PRAMDAC0, 0x0000050C); 1749 state->general = NV_RD32(chip->PRAMDAC, 0x00000600); 1750 state->scale = NV_RD32(chip->PRAMDAC, 0x00000848); 1751 state->config = NV_RD32(chip->PFB, 0x00000200); 1752 switch (chip->Architecture) 1753 { 1754 case NV_ARCH_03: 1755 state->offset0 = NV_RD32(chip->PGRAPH, 0x00000630); 1756 state->offset1 = NV_RD32(chip->PGRAPH, 0x00000634); 1757 state->offset2 = NV_RD32(chip->PGRAPH, 0x00000638); 1758 state->offset3 = NV_RD32(chip->PGRAPH, 0x0000063C); 1759 state->pitch0 = NV_RD32(chip->PGRAPH, 0x00000650); 1760 state->pitch1 = NV_RD32(chip->PGRAPH, 0x00000654); 1761 state->pitch2 = NV_RD32(chip->PGRAPH, 0x00000658); 1762 state->pitch3 = NV_RD32(chip->PGRAPH, 0x0000065C); 1763 break; 1764 case NV_ARCH_04: 1765 state->offset0 = NV_RD32(chip->PGRAPH, 0x00000640); 1766 state->offset1 = NV_RD32(chip->PGRAPH, 0x00000644); 1767 state->offset2 = NV_RD32(chip->PGRAPH, 0x00000648); 1768 state->offset3 = NV_RD32(chip->PGRAPH, 0x0000064C); 1769 state->pitch0 = NV_RD32(chip->PGRAPH, 0x00000670); 1770 state->pitch1 = NV_RD32(chip->PGRAPH, 0x00000674); 1771 state->pitch2 = NV_RD32(chip->PGRAPH, 0x00000678); 1772 state->pitch3 = NV_RD32(chip->PGRAPH, 0x0000067C); 1773 break; 1774 case NV_ARCH_10: 1775 case NV_ARCH_20: 1776 case NV_ARCH_30: 1777 state->offset0 = NV_RD32(chip->PGRAPH, 0x00000640); 1778 state->offset1 = NV_RD32(chip->PGRAPH, 0x00000644); 1779 state->offset2 = NV_RD32(chip->PGRAPH, 0x00000648); 1780 state->offset3 = NV_RD32(chip->PGRAPH, 0x0000064C); 1781 state->pitch0 = NV_RD32(chip->PGRAPH, 0x00000670); 1782 state->pitch1 = NV_RD32(chip->PGRAPH, 0x00000674); 1783 state->pitch2 = NV_RD32(chip->PGRAPH, 0x00000678); 1784 state->pitch3 = NV_RD32(chip->PGRAPH, 0x0000067C); 1785 if(chip->twoHeads) { 1786 state->head = NV_RD32(chip->PCRTC0, 0x00000860); 1787 state->head2 = NV_RD32(chip->PCRTC0, 0x00002860); 1788 VGA_WR08(chip->PCIO, 0x03D4, 0x44); 1789 state->crtcOwner = VGA_RD08(chip->PCIO, 0x03D5); 1790 } 1791 VGA_WR08(chip->PCIO, 0x03D4, 0x41); 1792 state->extra = VGA_RD08(chip->PCIO, 0x03D5); 1793 state->cursorConfig = NV_RD32(chip->PCRTC, 0x00000810); 1794 1795 if((chip->Chipset & 0x0ff0) == 0x0110) { 1796 state->dither = NV_RD32(chip->PRAMDAC, 0x0528); 1797 } else 1798 if((chip->Chipset & 0x0ff0) >= 0x0170) { 1799 state->dither = NV_RD32(chip->PRAMDAC, 0x083C); 1800 } 1801 break; 1802 } 1803 } 1804 static void SetStartAddress 1805 ( 1806 RIVA_HW_INST *chip, 1807 unsigned start 1808 ) 1809 { 1810 NV_WR32(chip->PCRTC, 0x800, start); 1811 } 1812 1813 static void SetStartAddress3 1814 ( 1815 RIVA_HW_INST *chip, 1816 unsigned start 1817 ) 1818 { 1819 int offset = start >> 2; 1820 int pan = (start & 3) << 1; 1821 unsigned char tmp; 1822 1823 /* 1824 * Unlock extended registers. 1825 */ 1826 chip->LockUnlock(chip, 0); 1827 /* 1828 * Set start address. 1829 */ 1830 VGA_WR08(chip->PCIO, 0x3D4, 0x0D); VGA_WR08(chip->PCIO, 0x3D5, offset); 1831 offset >>= 8; 1832 VGA_WR08(chip->PCIO, 0x3D4, 0x0C); VGA_WR08(chip->PCIO, 0x3D5, offset); 1833 offset >>= 8; 1834 VGA_WR08(chip->PCIO, 0x3D4, 0x19); tmp = VGA_RD08(chip->PCIO, 0x3D5); 1835 VGA_WR08(chip->PCIO, 0x3D5, (offset & 0x01F) | (tmp & ~0x1F)); 1836 VGA_WR08(chip->PCIO, 0x3D4, 0x2D); tmp = VGA_RD08(chip->PCIO, 0x3D5); 1837 VGA_WR08(chip->PCIO, 0x3D5, (offset & 0x60) | (tmp & ~0x60)); 1838 /* 1839 * 4 pixel pan register. 1840 */ 1841 offset = VGA_RD08(chip->PCIO, chip->IO + 0x0A); 1842 VGA_WR08(chip->PCIO, 0x3C0, 0x13); 1843 VGA_WR08(chip->PCIO, 0x3C0, pan); 1844 } 1845 static void nv3SetSurfaces2D 1846 ( 1847 RIVA_HW_INST *chip, 1848 unsigned surf0, 1849 unsigned surf1 1850 ) 1851 { 1852 RivaSurface __iomem *Surface = 1853 (RivaSurface __iomem *)&(chip->FIFO[0x0000E000/4]); 1854 1855 RIVA_FIFO_FREE(*chip,Tri03,5); 1856 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000003); 1857 NV_WR32(&Surface->Offset, 0, surf0); 1858 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000004); 1859 NV_WR32(&Surface->Offset, 0, surf1); 1860 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000013); 1861 } 1862 static void nv4SetSurfaces2D 1863 ( 1864 RIVA_HW_INST *chip, 1865 unsigned surf0, 1866 unsigned surf1 1867 ) 1868 { 1869 RivaSurface __iomem *Surface = 1870 (RivaSurface __iomem *)&(chip->FIFO[0x0000E000/4]); 1871 1872 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000003); 1873 NV_WR32(&Surface->Offset, 0, surf0); 1874 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000004); 1875 NV_WR32(&Surface->Offset, 0, surf1); 1876 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000014); 1877 } 1878 static void nv10SetSurfaces2D 1879 ( 1880 RIVA_HW_INST *chip, 1881 unsigned surf0, 1882 unsigned surf1 1883 ) 1884 { 1885 RivaSurface __iomem *Surface = 1886 (RivaSurface __iomem *)&(chip->FIFO[0x0000E000/4]); 1887 1888 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000003); 1889 NV_WR32(&Surface->Offset, 0, surf0); 1890 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000004); 1891 NV_WR32(&Surface->Offset, 0, surf1); 1892 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000014); 1893 } 1894 static void nv3SetSurfaces3D 1895 ( 1896 RIVA_HW_INST *chip, 1897 unsigned surf0, 1898 unsigned surf1 1899 ) 1900 { 1901 RivaSurface __iomem *Surface = 1902 (RivaSurface __iomem *)&(chip->FIFO[0x0000E000/4]); 1903 1904 RIVA_FIFO_FREE(*chip,Tri03,5); 1905 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000005); 1906 NV_WR32(&Surface->Offset, 0, surf0); 1907 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000006); 1908 NV_WR32(&Surface->Offset, 0, surf1); 1909 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000013); 1910 } 1911 static void nv4SetSurfaces3D 1912 ( 1913 RIVA_HW_INST *chip, 1914 unsigned surf0, 1915 unsigned surf1 1916 ) 1917 { 1918 RivaSurface __iomem *Surface = 1919 (RivaSurface __iomem *)&(chip->FIFO[0x0000E000/4]); 1920 1921 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000005); 1922 NV_WR32(&Surface->Offset, 0, surf0); 1923 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000006); 1924 NV_WR32(&Surface->Offset, 0, surf1); 1925 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000014); 1926 } 1927 static void nv10SetSurfaces3D 1928 ( 1929 RIVA_HW_INST *chip, 1930 unsigned surf0, 1931 unsigned surf1 1932 ) 1933 { 1934 RivaSurface3D __iomem *Surfaces3D = 1935 (RivaSurface3D __iomem *)&(chip->FIFO[0x0000E000/4]); 1936 1937 RIVA_FIFO_FREE(*chip,Tri03,4); 1938 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000007); 1939 NV_WR32(&Surfaces3D->RenderBufferOffset, 0, surf0); 1940 NV_WR32(&Surfaces3D->ZBufferOffset, 0, surf1); 1941 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000014); 1942 } 1943 1944 /****************************************************************************\ 1945 * * 1946 * Probe RIVA Chip Configuration * 1947 * * 1948 \****************************************************************************/ 1949 1950 static void nv3GetConfig 1951 ( 1952 RIVA_HW_INST *chip 1953 ) 1954 { 1955 /* 1956 * Fill in chip configuration. 1957 */ 1958 if (NV_RD32(&chip->PFB[0x00000000/4], 0) & 0x00000020) 1959 { 1960 if (((NV_RD32(chip->PMC, 0x00000000) & 0xF0) == 0x20) 1961 && ((NV_RD32(chip->PMC, 0x00000000) & 0x0F) >= 0x02)) 1962 { 1963 /* 1964 * SDRAM 128 ZX. 1965 */ 1966 chip->RamBandwidthKBytesPerSec = 800000; 1967 switch (NV_RD32(chip->PFB, 0x00000000) & 0x03) 1968 { 1969 case 2: 1970 chip->RamAmountKBytes = 1024 * 4; 1971 break; 1972 case 1: 1973 chip->RamAmountKBytes = 1024 * 2; 1974 break; 1975 default: 1976 chip->RamAmountKBytes = 1024 * 8; 1977 break; 1978 } 1979 } 1980 else 1981 { 1982 chip->RamBandwidthKBytesPerSec = 1000000; 1983 chip->RamAmountKBytes = 1024 * 8; 1984 } 1985 } 1986 else 1987 { 1988 /* 1989 * SGRAM 128. 1990 */ 1991 chip->RamBandwidthKBytesPerSec = 1000000; 1992 switch (NV_RD32(chip->PFB, 0x00000000) & 0x00000003) 1993 { 1994 case 0: 1995 chip->RamAmountKBytes = 1024 * 8; 1996 break; 1997 case 2: 1998 chip->RamAmountKBytes = 1024 * 4; 1999 break; 2000 default: 2001 chip->RamAmountKBytes = 1024 * 2; 2002 break; 2003 } 2004 } 2005 chip->CrystalFreqKHz = (NV_RD32(chip->PEXTDEV, 0x00000000) & 0x00000040) ? 14318 : 13500; 2006 chip->CURSOR = &(chip->PRAMIN[0x00008000/4 - 0x0800/4]); 2007 chip->VBlankBit = 0x00000100; 2008 chip->MaxVClockFreqKHz = 256000; 2009 /* 2010 * Set chip functions. 2011 */ 2012 chip->Busy = nv3Busy; 2013 chip->ShowHideCursor = ShowHideCursor; 2014 chip->LoadStateExt = LoadStateExt; 2015 chip->UnloadStateExt = UnloadStateExt; 2016 chip->SetStartAddress = SetStartAddress3; 2017 chip->SetSurfaces2D = nv3SetSurfaces2D; 2018 chip->SetSurfaces3D = nv3SetSurfaces3D; 2019 chip->LockUnlock = nv3LockUnlock; 2020 } 2021 static void nv4GetConfig 2022 ( 2023 RIVA_HW_INST *chip 2024 ) 2025 { 2026 /* 2027 * Fill in chip configuration. 2028 */ 2029 if (NV_RD32(chip->PFB, 0x00000000) & 0x00000100) 2030 { 2031 chip->RamAmountKBytes = ((NV_RD32(chip->PFB, 0x00000000) >> 12) & 0x0F) * 1024 * 2 2032 + 1024 * 2; 2033 } 2034 else 2035 { 2036 switch (NV_RD32(chip->PFB, 0x00000000) & 0x00000003) 2037 { 2038 case 0: 2039 chip->RamAmountKBytes = 1024 * 32; 2040 break; 2041 case 1: 2042 chip->RamAmountKBytes = 1024 * 4; 2043 break; 2044 case 2: 2045 chip->RamAmountKBytes = 1024 * 8; 2046 break; 2047 case 3: 2048 default: 2049 chip->RamAmountKBytes = 1024 * 16; 2050 break; 2051 } 2052 } 2053 switch ((NV_RD32(chip->PFB, 0x00000000) >> 3) & 0x00000003) 2054 { 2055 case 3: 2056 chip->RamBandwidthKBytesPerSec = 800000; 2057 break; 2058 default: 2059 chip->RamBandwidthKBytesPerSec = 1000000; 2060 break; 2061 } 2062 chip->CrystalFreqKHz = (NV_RD32(chip->PEXTDEV, 0x00000000) & 0x00000040) ? 14318 : 13500; 2063 chip->CURSOR = &(chip->PRAMIN[0x00010000/4 - 0x0800/4]); 2064 chip->VBlankBit = 0x00000001; 2065 chip->MaxVClockFreqKHz = 350000; 2066 /* 2067 * Set chip functions. 2068 */ 2069 chip->Busy = nv4Busy; 2070 chip->ShowHideCursor = ShowHideCursor; 2071 chip->LoadStateExt = LoadStateExt; 2072 chip->UnloadStateExt = UnloadStateExt; 2073 chip->SetStartAddress = SetStartAddress; 2074 chip->SetSurfaces2D = nv4SetSurfaces2D; 2075 chip->SetSurfaces3D = nv4SetSurfaces3D; 2076 chip->LockUnlock = nv4LockUnlock; 2077 } 2078 static void nv10GetConfig 2079 ( 2080 RIVA_HW_INST *chip, 2081 struct pci_dev *pdev, 2082 unsigned int chipset 2083 ) 2084 { 2085 struct pci_dev* dev; 2086 int domain = pci_domain_nr(pdev->bus); 2087 u32 amt; 2088 2089 #ifdef __BIG_ENDIAN 2090 /* turn on big endian register access */ 2091 if(!(NV_RD32(chip->PMC, 0x00000004) & 0x01000001)) 2092 NV_WR32(chip->PMC, 0x00000004, 0x01000001); 2093 #endif 2094 2095 /* 2096 * Fill in chip configuration. 2097 */ 2098 if(chipset == NV_CHIP_IGEFORCE2) { 2099 dev = pci_get_domain_bus_and_slot(domain, 0, 1); 2100 pci_read_config_dword(dev, 0x7C, &amt); 2101 pci_dev_put(dev); 2102 chip->RamAmountKBytes = (((amt >> 6) & 31) + 1) * 1024; 2103 } else if(chipset == NV_CHIP_0x01F0) { 2104 dev = pci_get_domain_bus_and_slot(domain, 0, 1); 2105 pci_read_config_dword(dev, 0x84, &amt); 2106 pci_dev_put(dev); 2107 chip->RamAmountKBytes = (((amt >> 4) & 127) + 1) * 1024; 2108 } else { 2109 switch ((NV_RD32(chip->PFB, 0x0000020C) >> 20) & 0x000000FF) 2110 { 2111 case 0x02: 2112 chip->RamAmountKBytes = 1024 * 2; 2113 break; 2114 case 0x04: 2115 chip->RamAmountKBytes = 1024 * 4; 2116 break; 2117 case 0x08: 2118 chip->RamAmountKBytes = 1024 * 8; 2119 break; 2120 case 0x10: 2121 chip->RamAmountKBytes = 1024 * 16; 2122 break; 2123 case 0x20: 2124 chip->RamAmountKBytes = 1024 * 32; 2125 break; 2126 case 0x40: 2127 chip->RamAmountKBytes = 1024 * 64; 2128 break; 2129 case 0x80: 2130 chip->RamAmountKBytes = 1024 * 128; 2131 break; 2132 default: 2133 chip->RamAmountKBytes = 1024 * 16; 2134 break; 2135 } 2136 } 2137 switch ((NV_RD32(chip->PFB, 0x00000000) >> 3) & 0x00000003) 2138 { 2139 case 3: 2140 chip->RamBandwidthKBytesPerSec = 800000; 2141 break; 2142 default: 2143 chip->RamBandwidthKBytesPerSec = 1000000; 2144 break; 2145 } 2146 chip->CrystalFreqKHz = (NV_RD32(chip->PEXTDEV, 0x0000) & (1 << 6)) ? 2147 14318 : 13500; 2148 2149 switch (chipset & 0x0ff0) { 2150 case 0x0170: 2151 case 0x0180: 2152 case 0x01F0: 2153 case 0x0250: 2154 case 0x0280: 2155 case 0x0300: 2156 case 0x0310: 2157 case 0x0320: 2158 case 0x0330: 2159 case 0x0340: 2160 if(NV_RD32(chip->PEXTDEV, 0x0000) & (1 << 22)) 2161 chip->CrystalFreqKHz = 27000; 2162 break; 2163 default: 2164 break; 2165 } 2166 2167 chip->CursorStart = (chip->RamAmountKBytes - 128) * 1024; 2168 chip->CURSOR = NULL; /* can't set this here */ 2169 chip->VBlankBit = 0x00000001; 2170 chip->MaxVClockFreqKHz = 350000; 2171 /* 2172 * Set chip functions. 2173 */ 2174 chip->Busy = nv10Busy; 2175 chip->ShowHideCursor = ShowHideCursor; 2176 chip->LoadStateExt = LoadStateExt; 2177 chip->UnloadStateExt = UnloadStateExt; 2178 chip->SetStartAddress = SetStartAddress; 2179 chip->SetSurfaces2D = nv10SetSurfaces2D; 2180 chip->SetSurfaces3D = nv10SetSurfaces3D; 2181 chip->LockUnlock = nv4LockUnlock; 2182 2183 switch(chipset & 0x0ff0) { 2184 case 0x0110: 2185 case 0x0170: 2186 case 0x0180: 2187 case 0x01F0: 2188 case 0x0250: 2189 case 0x0280: 2190 case 0x0300: 2191 case 0x0310: 2192 case 0x0320: 2193 case 0x0330: 2194 case 0x0340: 2195 chip->twoHeads = TRUE; 2196 break; 2197 default: 2198 chip->twoHeads = FALSE; 2199 break; 2200 } 2201 } 2202 int RivaGetConfig 2203 ( 2204 RIVA_HW_INST *chip, 2205 struct pci_dev *pdev, 2206 unsigned int chipset 2207 ) 2208 { 2209 /* 2210 * Save this so future SW know whats it's dealing with. 2211 */ 2212 chip->Version = RIVA_SW_VERSION; 2213 /* 2214 * Chip specific configuration. 2215 */ 2216 switch (chip->Architecture) 2217 { 2218 case NV_ARCH_03: 2219 nv3GetConfig(chip); 2220 break; 2221 case NV_ARCH_04: 2222 nv4GetConfig(chip); 2223 break; 2224 case NV_ARCH_10: 2225 case NV_ARCH_20: 2226 case NV_ARCH_30: 2227 nv10GetConfig(chip, pdev, chipset); 2228 break; 2229 default: 2230 return (-1); 2231 } 2232 chip->Chipset = chipset; 2233 /* 2234 * Fill in FIFO pointers. 2235 */ 2236 chip->Rop = (RivaRop __iomem *)&(chip->FIFO[0x00000000/4]); 2237 chip->Clip = (RivaClip __iomem *)&(chip->FIFO[0x00002000/4]); 2238 chip->Patt = (RivaPattern __iomem *)&(chip->FIFO[0x00004000/4]); 2239 chip->Pixmap = (RivaPixmap __iomem *)&(chip->FIFO[0x00006000/4]); 2240 chip->Blt = (RivaScreenBlt __iomem *)&(chip->FIFO[0x00008000/4]); 2241 chip->Bitmap = (RivaBitmap __iomem *)&(chip->FIFO[0x0000A000/4]); 2242 chip->Line = (RivaLine __iomem *)&(chip->FIFO[0x0000C000/4]); 2243 chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]); 2244 return (0); 2245 } 2246 2247