1 /* 2 * linux/drivers/video/riva/fbdev.c - nVidia RIVA 128/TNT/TNT2 fb driver 3 * 4 * Maintained by Ani Joshi <ajoshi@shell.unixbox.com> 5 * 6 * Copyright 1999-2000 Jeff Garzik 7 * 8 * Contributors: 9 * 10 * Ani Joshi: Lots of debugging and cleanup work, really helped 11 * get the driver going 12 * 13 * Ferenc Bakonyi: Bug fixes, cleanup, modularization 14 * 15 * Jindrich Makovicka: Accel code help, hw cursor, mtrr 16 * 17 * Paul Richards: Bug fixes, updates 18 * 19 * Initial template from skeletonfb.c, created 28 Dec 1997 by Geert Uytterhoeven 20 * Includes riva_hw.c from nVidia, see copyright below. 21 * KGI code provided the basis for state storage, init, and mode switching. 22 * 23 * This file is subject to the terms and conditions of the GNU General Public 24 * License. See the file COPYING in the main directory of this archive 25 * for more details. 26 * 27 * Known bugs and issues: 28 * restoring text mode fails 29 * doublescan modes are broken 30 */ 31 32 #include <linux/module.h> 33 #include <linux/kernel.h> 34 #include <linux/errno.h> 35 #include <linux/string.h> 36 #include <linux/mm.h> 37 #include <linux/slab.h> 38 #include <linux/delay.h> 39 #include <linux/fb.h> 40 #include <linux/init.h> 41 #include <linux/pci.h> 42 #include <linux/backlight.h> 43 #include <linux/bitrev.h> 44 #ifdef CONFIG_MTRR 45 #include <asm/mtrr.h> 46 #endif 47 #ifdef CONFIG_PPC_OF 48 #include <asm/prom.h> 49 #include <asm/pci-bridge.h> 50 #endif 51 #ifdef CONFIG_PMAC_BACKLIGHT 52 #include <asm/machdep.h> 53 #include <asm/backlight.h> 54 #endif 55 56 #include "rivafb.h" 57 #include "nvreg.h" 58 59 /* version number of this driver */ 60 #define RIVAFB_VERSION "0.9.5b" 61 62 /* ------------------------------------------------------------------------- * 63 * 64 * various helpful macros and constants 65 * 66 * ------------------------------------------------------------------------- */ 67 #ifdef CONFIG_FB_RIVA_DEBUG 68 #define NVTRACE printk 69 #else 70 #define NVTRACE if(0) printk 71 #endif 72 73 #define NVTRACE_ENTER(...) NVTRACE("%s START\n", __func__) 74 #define NVTRACE_LEAVE(...) NVTRACE("%s END\n", __func__) 75 76 #ifdef CONFIG_FB_RIVA_DEBUG 77 #define assert(expr) \ 78 if(!(expr)) { \ 79 printk( "Assertion failed! %s,%s,%s,line=%d\n",\ 80 #expr,__FILE__,__func__,__LINE__); \ 81 BUG(); \ 82 } 83 #else 84 #define assert(expr) 85 #endif 86 87 #define PFX "rivafb: " 88 89 /* macro that allows you to set overflow bits */ 90 #define SetBitField(value,from,to) SetBF(to,GetBF(value,from)) 91 #define SetBit(n) (1<<(n)) 92 #define Set8Bits(value) ((value)&0xff) 93 94 /* HW cursor parameters */ 95 #define MAX_CURS 32 96 97 /* ------------------------------------------------------------------------- * 98 * 99 * prototypes 100 * 101 * ------------------------------------------------------------------------- */ 102 103 static int rivafb_blank(int blank, struct fb_info *info); 104 105 /* ------------------------------------------------------------------------- * 106 * 107 * card identification 108 * 109 * ------------------------------------------------------------------------- */ 110 111 static struct pci_device_id rivafb_pci_tbl[] = { 112 { PCI_VENDOR_ID_NVIDIA_SGS, PCI_DEVICE_ID_NVIDIA_SGS_RIVA128, 113 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 114 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT, 115 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 116 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT2, 117 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 118 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_UTNT2, 119 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 120 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_VTNT2, 121 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 122 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_UVTNT2, 123 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 124 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_ITNT2, 125 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 126 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_SDR, 127 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 128 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_DDR, 129 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 130 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO, 131 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 132 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX, 133 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 134 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX2, 135 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 136 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GO, 137 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 138 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO2_MXR, 139 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 140 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS, 141 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 142 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS2, 143 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 144 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_ULTRA, 145 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 146 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO2_PRO, 147 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 148 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_460, 149 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 150 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440, 151 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 152 // NF2/IGP version, GeForce 4 MX, NV18 153 { PCI_VENDOR_ID_NVIDIA, 0x01f0, 154 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 155 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_420, 156 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 157 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO, 158 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 159 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO, 160 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 161 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO_M32, 162 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 163 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_500XGL, 164 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 165 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO_M64, 166 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 167 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_200, 168 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 169 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_550XGL, 170 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 171 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_500_GOGL, 172 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 173 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_IGEFORCE2, 174 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 175 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3, 176 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 177 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3_1, 178 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 179 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3_2, 180 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 181 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_DDC, 182 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 183 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4600, 184 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 185 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4400, 186 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 187 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4200, 188 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 189 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_900XGL, 190 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 191 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_750XGL, 192 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 193 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_700XGL, 194 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 195 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO_5200, 196 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 197 { 0, } /* terminate list */ 198 }; 199 MODULE_DEVICE_TABLE(pci, rivafb_pci_tbl); 200 201 /* ------------------------------------------------------------------------- * 202 * 203 * global variables 204 * 205 * ------------------------------------------------------------------------- */ 206 207 /* command line data, set in rivafb_setup() */ 208 static int flatpanel = -1; /* Autodetect later */ 209 static int forceCRTC = -1; 210 static bool noaccel = 0; 211 #ifdef CONFIG_MTRR 212 static bool nomtrr = 0; 213 #endif 214 #ifdef CONFIG_PMAC_BACKLIGHT 215 static int backlight = 1; 216 #else 217 static int backlight = 0; 218 #endif 219 220 static char *mode_option = NULL; 221 static bool strictmode = 0; 222 223 static struct fb_fix_screeninfo rivafb_fix = { 224 .type = FB_TYPE_PACKED_PIXELS, 225 .xpanstep = 1, 226 .ypanstep = 1, 227 }; 228 229 static struct fb_var_screeninfo rivafb_default_var = { 230 .xres = 640, 231 .yres = 480, 232 .xres_virtual = 640, 233 .yres_virtual = 480, 234 .bits_per_pixel = 8, 235 .red = {0, 8, 0}, 236 .green = {0, 8, 0}, 237 .blue = {0, 8, 0}, 238 .transp = {0, 0, 0}, 239 .activate = FB_ACTIVATE_NOW, 240 .height = -1, 241 .width = -1, 242 .pixclock = 39721, 243 .left_margin = 40, 244 .right_margin = 24, 245 .upper_margin = 32, 246 .lower_margin = 11, 247 .hsync_len = 96, 248 .vsync_len = 2, 249 .vmode = FB_VMODE_NONINTERLACED 250 }; 251 252 /* from GGI */ 253 static const struct riva_regs reg_template = { 254 {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, /* ATTR */ 255 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, 256 0x41, 0x01, 0x0F, 0x00, 0x00}, 257 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* CRT */ 258 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 259 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE3, /* 0x10 */ 260 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 261 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x20 */ 262 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 263 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x30 */ 264 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 265 0x00, /* 0x40 */ 266 }, 267 {0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F, /* GRA */ 268 0xFF}, 269 {0x03, 0x01, 0x0F, 0x00, 0x0E}, /* SEQ */ 270 0xEB /* MISC */ 271 }; 272 273 /* 274 * Backlight control 275 */ 276 #ifdef CONFIG_FB_RIVA_BACKLIGHT 277 /* We do not have any information about which values are allowed, thus 278 * we used safe values. 279 */ 280 #define MIN_LEVEL 0x158 281 #define MAX_LEVEL 0x534 282 #define LEVEL_STEP ((MAX_LEVEL - MIN_LEVEL) / FB_BACKLIGHT_MAX) 283 284 static int riva_bl_get_level_brightness(struct riva_par *par, 285 int level) 286 { 287 struct fb_info *info = pci_get_drvdata(par->pdev); 288 int nlevel; 289 290 /* Get and convert the value */ 291 /* No locking on bl_curve since accessing a single value */ 292 nlevel = MIN_LEVEL + info->bl_curve[level] * LEVEL_STEP; 293 294 if (nlevel < 0) 295 nlevel = 0; 296 else if (nlevel < MIN_LEVEL) 297 nlevel = MIN_LEVEL; 298 else if (nlevel > MAX_LEVEL) 299 nlevel = MAX_LEVEL; 300 301 return nlevel; 302 } 303 304 static int riva_bl_update_status(struct backlight_device *bd) 305 { 306 struct riva_par *par = bl_get_data(bd); 307 U032 tmp_pcrt, tmp_pmc; 308 int level; 309 310 if (bd->props.power != FB_BLANK_UNBLANK || 311 bd->props.fb_blank != FB_BLANK_UNBLANK) 312 level = 0; 313 else 314 level = bd->props.brightness; 315 316 tmp_pmc = NV_RD32(par->riva.PMC, 0x10F0) & 0x0000FFFF; 317 tmp_pcrt = NV_RD32(par->riva.PCRTC0, 0x081C) & 0xFFFFFFFC; 318 if(level > 0) { 319 tmp_pcrt |= 0x1; 320 tmp_pmc |= (1 << 31); /* backlight bit */ 321 tmp_pmc |= riva_bl_get_level_brightness(par, level) << 16; /* level */ 322 } 323 NV_WR32(par->riva.PCRTC0, 0x081C, tmp_pcrt); 324 NV_WR32(par->riva.PMC, 0x10F0, tmp_pmc); 325 326 return 0; 327 } 328 329 static int riva_bl_get_brightness(struct backlight_device *bd) 330 { 331 return bd->props.brightness; 332 } 333 334 static const struct backlight_ops riva_bl_ops = { 335 .get_brightness = riva_bl_get_brightness, 336 .update_status = riva_bl_update_status, 337 }; 338 339 static void riva_bl_init(struct riva_par *par) 340 { 341 struct backlight_properties props; 342 struct fb_info *info = pci_get_drvdata(par->pdev); 343 struct backlight_device *bd; 344 char name[12]; 345 346 if (!par->FlatPanel) 347 return; 348 349 #ifdef CONFIG_PMAC_BACKLIGHT 350 if (!machine_is(powermac) || 351 !pmac_has_backlight_type("mnca")) 352 return; 353 #endif 354 355 snprintf(name, sizeof(name), "rivabl%d", info->node); 356 357 memset(&props, 0, sizeof(struct backlight_properties)); 358 props.type = BACKLIGHT_RAW; 359 props.max_brightness = FB_BACKLIGHT_LEVELS - 1; 360 bd = backlight_device_register(name, info->dev, par, &riva_bl_ops, 361 &props); 362 if (IS_ERR(bd)) { 363 info->bl_dev = NULL; 364 printk(KERN_WARNING "riva: Backlight registration failed\n"); 365 goto error; 366 } 367 368 info->bl_dev = bd; 369 fb_bl_default_curve(info, 0, 370 MIN_LEVEL * FB_BACKLIGHT_MAX / MAX_LEVEL, 371 FB_BACKLIGHT_MAX); 372 373 bd->props.brightness = bd->props.max_brightness; 374 bd->props.power = FB_BLANK_UNBLANK; 375 backlight_update_status(bd); 376 377 printk("riva: Backlight initialized (%s)\n", name); 378 379 return; 380 381 error: 382 return; 383 } 384 385 static void riva_bl_exit(struct fb_info *info) 386 { 387 struct backlight_device *bd = info->bl_dev; 388 389 backlight_device_unregister(bd); 390 printk("riva: Backlight unloaded\n"); 391 } 392 #else 393 static inline void riva_bl_init(struct riva_par *par) {} 394 static inline void riva_bl_exit(struct fb_info *info) {} 395 #endif /* CONFIG_FB_RIVA_BACKLIGHT */ 396 397 /* ------------------------------------------------------------------------- * 398 * 399 * MMIO access macros 400 * 401 * ------------------------------------------------------------------------- */ 402 403 static inline void CRTCout(struct riva_par *par, unsigned char index, 404 unsigned char val) 405 { 406 VGA_WR08(par->riva.PCIO, 0x3d4, index); 407 VGA_WR08(par->riva.PCIO, 0x3d5, val); 408 } 409 410 static inline unsigned char CRTCin(struct riva_par *par, 411 unsigned char index) 412 { 413 VGA_WR08(par->riva.PCIO, 0x3d4, index); 414 return (VGA_RD08(par->riva.PCIO, 0x3d5)); 415 } 416 417 static inline void GRAout(struct riva_par *par, unsigned char index, 418 unsigned char val) 419 { 420 VGA_WR08(par->riva.PVIO, 0x3ce, index); 421 VGA_WR08(par->riva.PVIO, 0x3cf, val); 422 } 423 424 static inline unsigned char GRAin(struct riva_par *par, 425 unsigned char index) 426 { 427 VGA_WR08(par->riva.PVIO, 0x3ce, index); 428 return (VGA_RD08(par->riva.PVIO, 0x3cf)); 429 } 430 431 static inline void SEQout(struct riva_par *par, unsigned char index, 432 unsigned char val) 433 { 434 VGA_WR08(par->riva.PVIO, 0x3c4, index); 435 VGA_WR08(par->riva.PVIO, 0x3c5, val); 436 } 437 438 static inline unsigned char SEQin(struct riva_par *par, 439 unsigned char index) 440 { 441 VGA_WR08(par->riva.PVIO, 0x3c4, index); 442 return (VGA_RD08(par->riva.PVIO, 0x3c5)); 443 } 444 445 static inline void ATTRout(struct riva_par *par, unsigned char index, 446 unsigned char val) 447 { 448 VGA_WR08(par->riva.PCIO, 0x3c0, index); 449 VGA_WR08(par->riva.PCIO, 0x3c0, val); 450 } 451 452 static inline unsigned char ATTRin(struct riva_par *par, 453 unsigned char index) 454 { 455 VGA_WR08(par->riva.PCIO, 0x3c0, index); 456 return (VGA_RD08(par->riva.PCIO, 0x3c1)); 457 } 458 459 static inline void MISCout(struct riva_par *par, unsigned char val) 460 { 461 VGA_WR08(par->riva.PVIO, 0x3c2, val); 462 } 463 464 static inline unsigned char MISCin(struct riva_par *par) 465 { 466 return (VGA_RD08(par->riva.PVIO, 0x3cc)); 467 } 468 469 static inline void reverse_order(u32 *l) 470 { 471 u8 *a = (u8 *)l; 472 a[0] = bitrev8(a[0]); 473 a[1] = bitrev8(a[1]); 474 a[2] = bitrev8(a[2]); 475 a[3] = bitrev8(a[3]); 476 } 477 478 /* ------------------------------------------------------------------------- * 479 * 480 * cursor stuff 481 * 482 * ------------------------------------------------------------------------- */ 483 484 /** 485 * rivafb_load_cursor_image - load cursor image to hardware 486 * @data: address to monochrome bitmap (1 = foreground color, 0 = background) 487 * @par: pointer to private data 488 * @w: width of cursor image in pixels 489 * @h: height of cursor image in scanlines 490 * @bg: background color (ARGB1555) - alpha bit determines opacity 491 * @fg: foreground color (ARGB1555) 492 * 493 * DESCRIPTiON: 494 * Loads cursor image based on a monochrome source and mask bitmap. The 495 * image bits determines the color of the pixel, 0 for background, 1 for 496 * foreground. Only the affected region (as determined by @w and @h 497 * parameters) will be updated. 498 * 499 * CALLED FROM: 500 * rivafb_cursor() 501 */ 502 static void rivafb_load_cursor_image(struct riva_par *par, u8 *data8, 503 u16 bg, u16 fg, u32 w, u32 h) 504 { 505 int i, j, k = 0; 506 u32 b, tmp; 507 u32 *data = (u32 *)data8; 508 bg = le16_to_cpu(bg); 509 fg = le16_to_cpu(fg); 510 511 w = (w + 1) & ~1; 512 513 for (i = 0; i < h; i++) { 514 b = *data++; 515 reverse_order(&b); 516 517 for (j = 0; j < w/2; j++) { 518 tmp = 0; 519 #if defined (__BIG_ENDIAN) 520 tmp = (b & (1 << 31)) ? fg << 16 : bg << 16; 521 b <<= 1; 522 tmp |= (b & (1 << 31)) ? fg : bg; 523 b <<= 1; 524 #else 525 tmp = (b & 1) ? fg : bg; 526 b >>= 1; 527 tmp |= (b & 1) ? fg << 16 : bg << 16; 528 b >>= 1; 529 #endif 530 writel(tmp, &par->riva.CURSOR[k++]); 531 } 532 k += (MAX_CURS - w)/2; 533 } 534 } 535 536 /* ------------------------------------------------------------------------- * 537 * 538 * general utility functions 539 * 540 * ------------------------------------------------------------------------- */ 541 542 /** 543 * riva_wclut - set CLUT entry 544 * @chip: pointer to RIVA_HW_INST object 545 * @regnum: register number 546 * @red: red component 547 * @green: green component 548 * @blue: blue component 549 * 550 * DESCRIPTION: 551 * Sets color register @regnum. 552 * 553 * CALLED FROM: 554 * rivafb_setcolreg() 555 */ 556 static void riva_wclut(RIVA_HW_INST *chip, 557 unsigned char regnum, unsigned char red, 558 unsigned char green, unsigned char blue) 559 { 560 VGA_WR08(chip->PDIO, 0x3c8, regnum); 561 VGA_WR08(chip->PDIO, 0x3c9, red); 562 VGA_WR08(chip->PDIO, 0x3c9, green); 563 VGA_WR08(chip->PDIO, 0x3c9, blue); 564 } 565 566 /** 567 * riva_rclut - read fromCLUT register 568 * @chip: pointer to RIVA_HW_INST object 569 * @regnum: register number 570 * @red: red component 571 * @green: green component 572 * @blue: blue component 573 * 574 * DESCRIPTION: 575 * Reads red, green, and blue from color register @regnum. 576 * 577 * CALLED FROM: 578 * rivafb_setcolreg() 579 */ 580 static void riva_rclut(RIVA_HW_INST *chip, 581 unsigned char regnum, unsigned char *red, 582 unsigned char *green, unsigned char *blue) 583 { 584 585 VGA_WR08(chip->PDIO, 0x3c7, regnum); 586 *red = VGA_RD08(chip->PDIO, 0x3c9); 587 *green = VGA_RD08(chip->PDIO, 0x3c9); 588 *blue = VGA_RD08(chip->PDIO, 0x3c9); 589 } 590 591 /** 592 * riva_save_state - saves current chip state 593 * @par: pointer to riva_par object containing info for current riva board 594 * @regs: pointer to riva_regs object 595 * 596 * DESCRIPTION: 597 * Saves current chip state to @regs. 598 * 599 * CALLED FROM: 600 * rivafb_probe() 601 */ 602 /* from GGI */ 603 static void riva_save_state(struct riva_par *par, struct riva_regs *regs) 604 { 605 int i; 606 607 NVTRACE_ENTER(); 608 par->riva.LockUnlock(&par->riva, 0); 609 610 par->riva.UnloadStateExt(&par->riva, ®s->ext); 611 612 regs->misc_output = MISCin(par); 613 614 for (i = 0; i < NUM_CRT_REGS; i++) 615 regs->crtc[i] = CRTCin(par, i); 616 617 for (i = 0; i < NUM_ATC_REGS; i++) 618 regs->attr[i] = ATTRin(par, i); 619 620 for (i = 0; i < NUM_GRC_REGS; i++) 621 regs->gra[i] = GRAin(par, i); 622 623 for (i = 0; i < NUM_SEQ_REGS; i++) 624 regs->seq[i] = SEQin(par, i); 625 NVTRACE_LEAVE(); 626 } 627 628 /** 629 * riva_load_state - loads current chip state 630 * @par: pointer to riva_par object containing info for current riva board 631 * @regs: pointer to riva_regs object 632 * 633 * DESCRIPTION: 634 * Loads chip state from @regs. 635 * 636 * CALLED FROM: 637 * riva_load_video_mode() 638 * rivafb_probe() 639 * rivafb_remove() 640 */ 641 /* from GGI */ 642 static void riva_load_state(struct riva_par *par, struct riva_regs *regs) 643 { 644 RIVA_HW_STATE *state = ®s->ext; 645 int i; 646 647 NVTRACE_ENTER(); 648 CRTCout(par, 0x11, 0x00); 649 650 par->riva.LockUnlock(&par->riva, 0); 651 652 par->riva.LoadStateExt(&par->riva, state); 653 654 MISCout(par, regs->misc_output); 655 656 for (i = 0; i < NUM_CRT_REGS; i++) { 657 switch (i) { 658 case 0x19: 659 case 0x20 ... 0x40: 660 break; 661 default: 662 CRTCout(par, i, regs->crtc[i]); 663 } 664 } 665 666 for (i = 0; i < NUM_ATC_REGS; i++) 667 ATTRout(par, i, regs->attr[i]); 668 669 for (i = 0; i < NUM_GRC_REGS; i++) 670 GRAout(par, i, regs->gra[i]); 671 672 for (i = 0; i < NUM_SEQ_REGS; i++) 673 SEQout(par, i, regs->seq[i]); 674 NVTRACE_LEAVE(); 675 } 676 677 /** 678 * riva_load_video_mode - calculate timings 679 * @info: pointer to fb_info object containing info for current riva board 680 * 681 * DESCRIPTION: 682 * Calculate some timings and then send em off to riva_load_state(). 683 * 684 * CALLED FROM: 685 * rivafb_set_par() 686 */ 687 static int riva_load_video_mode(struct fb_info *info) 688 { 689 int bpp, width, hDisplaySize, hDisplay, hStart, 690 hEnd, hTotal, height, vDisplay, vStart, vEnd, vTotal, dotClock; 691 int hBlankStart, hBlankEnd, vBlankStart, vBlankEnd; 692 int rc; 693 struct riva_par *par = info->par; 694 struct riva_regs newmode; 695 696 NVTRACE_ENTER(); 697 /* time to calculate */ 698 rivafb_blank(FB_BLANK_NORMAL, info); 699 700 bpp = info->var.bits_per_pixel; 701 if (bpp == 16 && info->var.green.length == 5) 702 bpp = 15; 703 width = info->var.xres_virtual; 704 hDisplaySize = info->var.xres; 705 hDisplay = (hDisplaySize / 8) - 1; 706 hStart = (hDisplaySize + info->var.right_margin) / 8 - 1; 707 hEnd = (hDisplaySize + info->var.right_margin + 708 info->var.hsync_len) / 8 - 1; 709 hTotal = (hDisplaySize + info->var.right_margin + 710 info->var.hsync_len + info->var.left_margin) / 8 - 5; 711 hBlankStart = hDisplay; 712 hBlankEnd = hTotal + 4; 713 714 height = info->var.yres_virtual; 715 vDisplay = info->var.yres - 1; 716 vStart = info->var.yres + info->var.lower_margin - 1; 717 vEnd = info->var.yres + info->var.lower_margin + 718 info->var.vsync_len - 1; 719 vTotal = info->var.yres + info->var.lower_margin + 720 info->var.vsync_len + info->var.upper_margin + 2; 721 vBlankStart = vDisplay; 722 vBlankEnd = vTotal + 1; 723 dotClock = 1000000000 / info->var.pixclock; 724 725 memcpy(&newmode, ®_template, sizeof(struct riva_regs)); 726 727 if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) 728 vTotal |= 1; 729 730 if (par->FlatPanel) { 731 vStart = vTotal - 3; 732 vEnd = vTotal - 2; 733 vBlankStart = vStart; 734 hStart = hTotal - 3; 735 hEnd = hTotal - 2; 736 hBlankEnd = hTotal + 4; 737 } 738 739 newmode.crtc[0x0] = Set8Bits (hTotal); 740 newmode.crtc[0x1] = Set8Bits (hDisplay); 741 newmode.crtc[0x2] = Set8Bits (hBlankStart); 742 newmode.crtc[0x3] = SetBitField (hBlankEnd, 4: 0, 4:0) | SetBit (7); 743 newmode.crtc[0x4] = Set8Bits (hStart); 744 newmode.crtc[0x5] = SetBitField (hBlankEnd, 5: 5, 7:7) 745 | SetBitField (hEnd, 4: 0, 4:0); 746 newmode.crtc[0x6] = SetBitField (vTotal, 7: 0, 7:0); 747 newmode.crtc[0x7] = SetBitField (vTotal, 8: 8, 0:0) 748 | SetBitField (vDisplay, 8: 8, 1:1) 749 | SetBitField (vStart, 8: 8, 2:2) 750 | SetBitField (vBlankStart, 8: 8, 3:3) 751 | SetBit (4) 752 | SetBitField (vTotal, 9: 9, 5:5) 753 | SetBitField (vDisplay, 9: 9, 6:6) 754 | SetBitField (vStart, 9: 9, 7:7); 755 newmode.crtc[0x9] = SetBitField (vBlankStart, 9: 9, 5:5) 756 | SetBit (6); 757 newmode.crtc[0x10] = Set8Bits (vStart); 758 newmode.crtc[0x11] = SetBitField (vEnd, 3: 0, 3:0) 759 | SetBit (5); 760 newmode.crtc[0x12] = Set8Bits (vDisplay); 761 newmode.crtc[0x13] = (width / 8) * ((bpp + 1) / 8); 762 newmode.crtc[0x15] = Set8Bits (vBlankStart); 763 newmode.crtc[0x16] = Set8Bits (vBlankEnd); 764 765 newmode.ext.screen = SetBitField(hBlankEnd,6:6,4:4) 766 | SetBitField(vBlankStart,10:10,3:3) 767 | SetBitField(vStart,10:10,2:2) 768 | SetBitField(vDisplay,10:10,1:1) 769 | SetBitField(vTotal,10:10,0:0); 770 newmode.ext.horiz = SetBitField(hTotal,8:8,0:0) 771 | SetBitField(hDisplay,8:8,1:1) 772 | SetBitField(hBlankStart,8:8,2:2) 773 | SetBitField(hStart,8:8,3:3); 774 newmode.ext.extra = SetBitField(vTotal,11:11,0:0) 775 | SetBitField(vDisplay,11:11,2:2) 776 | SetBitField(vStart,11:11,4:4) 777 | SetBitField(vBlankStart,11:11,6:6); 778 779 if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) { 780 int tmp = (hTotal >> 1) & ~1; 781 newmode.ext.interlace = Set8Bits(tmp); 782 newmode.ext.horiz |= SetBitField(tmp, 8:8,4:4); 783 } else 784 newmode.ext.interlace = 0xff; /* interlace off */ 785 786 if (par->riva.Architecture >= NV_ARCH_10) 787 par->riva.CURSOR = (U032 __iomem *)(info->screen_base + par->riva.CursorStart); 788 789 if (info->var.sync & FB_SYNC_HOR_HIGH_ACT) 790 newmode.misc_output &= ~0x40; 791 else 792 newmode.misc_output |= 0x40; 793 if (info->var.sync & FB_SYNC_VERT_HIGH_ACT) 794 newmode.misc_output &= ~0x80; 795 else 796 newmode.misc_output |= 0x80; 797 798 rc = CalcStateExt(&par->riva, &newmode.ext, bpp, width, 799 hDisplaySize, height, dotClock); 800 if (rc) 801 goto out; 802 803 newmode.ext.scale = NV_RD32(par->riva.PRAMDAC, 0x00000848) & 804 0xfff000ff; 805 if (par->FlatPanel == 1) { 806 newmode.ext.pixel |= (1 << 7); 807 newmode.ext.scale |= (1 << 8); 808 } 809 if (par->SecondCRTC) { 810 newmode.ext.head = NV_RD32(par->riva.PCRTC0, 0x00000860) & 811 ~0x00001000; 812 newmode.ext.head2 = NV_RD32(par->riva.PCRTC0, 0x00002860) | 813 0x00001000; 814 newmode.ext.crtcOwner = 3; 815 newmode.ext.pllsel |= 0x20000800; 816 newmode.ext.vpll2 = newmode.ext.vpll; 817 } else if (par->riva.twoHeads) { 818 newmode.ext.head = NV_RD32(par->riva.PCRTC0, 0x00000860) | 819 0x00001000; 820 newmode.ext.head2 = NV_RD32(par->riva.PCRTC0, 0x00002860) & 821 ~0x00001000; 822 newmode.ext.crtcOwner = 0; 823 newmode.ext.vpll2 = NV_RD32(par->riva.PRAMDAC0, 0x00000520); 824 } 825 if (par->FlatPanel == 1) { 826 newmode.ext.pixel |= (1 << 7); 827 newmode.ext.scale |= (1 << 8); 828 } 829 newmode.ext.cursorConfig = 0x02000100; 830 par->current_state = newmode; 831 riva_load_state(par, &par->current_state); 832 par->riva.LockUnlock(&par->riva, 0); /* important for HW cursor */ 833 834 out: 835 rivafb_blank(FB_BLANK_UNBLANK, info); 836 NVTRACE_LEAVE(); 837 838 return rc; 839 } 840 841 static void riva_update_var(struct fb_var_screeninfo *var, 842 const struct fb_videomode *modedb) 843 { 844 NVTRACE_ENTER(); 845 var->xres = var->xres_virtual = modedb->xres; 846 var->yres = modedb->yres; 847 if (var->yres_virtual < var->yres) 848 var->yres_virtual = var->yres; 849 var->xoffset = var->yoffset = 0; 850 var->pixclock = modedb->pixclock; 851 var->left_margin = modedb->left_margin; 852 var->right_margin = modedb->right_margin; 853 var->upper_margin = modedb->upper_margin; 854 var->lower_margin = modedb->lower_margin; 855 var->hsync_len = modedb->hsync_len; 856 var->vsync_len = modedb->vsync_len; 857 var->sync = modedb->sync; 858 var->vmode = modedb->vmode; 859 NVTRACE_LEAVE(); 860 } 861 862 /** 863 * rivafb_do_maximize - 864 * @info: pointer to fb_info object containing info for current riva board 865 * @var: 866 * @nom: 867 * @den: 868 * 869 * DESCRIPTION: 870 * . 871 * 872 * RETURNS: 873 * -EINVAL on failure, 0 on success 874 * 875 * 876 * CALLED FROM: 877 * rivafb_check_var() 878 */ 879 static int rivafb_do_maximize(struct fb_info *info, 880 struct fb_var_screeninfo *var, 881 int nom, int den) 882 { 883 static struct { 884 int xres, yres; 885 } modes[] = { 886 {1600, 1280}, 887 {1280, 1024}, 888 {1024, 768}, 889 {800, 600}, 890 {640, 480}, 891 {-1, -1} 892 }; 893 int i; 894 895 NVTRACE_ENTER(); 896 /* use highest possible virtual resolution */ 897 if (var->xres_virtual == -1 && var->yres_virtual == -1) { 898 printk(KERN_WARNING PFX 899 "using maximum available virtual resolution\n"); 900 for (i = 0; modes[i].xres != -1; i++) { 901 if (modes[i].xres * nom / den * modes[i].yres < 902 info->fix.smem_len) 903 break; 904 } 905 if (modes[i].xres == -1) { 906 printk(KERN_ERR PFX 907 "could not find a virtual resolution that fits into video memory!!\n"); 908 NVTRACE("EXIT - EINVAL error\n"); 909 return -EINVAL; 910 } 911 var->xres_virtual = modes[i].xres; 912 var->yres_virtual = modes[i].yres; 913 914 printk(KERN_INFO PFX 915 "virtual resolution set to maximum of %dx%d\n", 916 var->xres_virtual, var->yres_virtual); 917 } else if (var->xres_virtual == -1) { 918 var->xres_virtual = (info->fix.smem_len * den / 919 (nom * var->yres_virtual)) & ~15; 920 printk(KERN_WARNING PFX 921 "setting virtual X resolution to %d\n", var->xres_virtual); 922 } else if (var->yres_virtual == -1) { 923 var->xres_virtual = (var->xres_virtual + 15) & ~15; 924 var->yres_virtual = info->fix.smem_len * den / 925 (nom * var->xres_virtual); 926 printk(KERN_WARNING PFX 927 "setting virtual Y resolution to %d\n", var->yres_virtual); 928 } else { 929 var->xres_virtual = (var->xres_virtual + 15) & ~15; 930 if (var->xres_virtual * nom / den * var->yres_virtual > info->fix.smem_len) { 931 printk(KERN_ERR PFX 932 "mode %dx%dx%d rejected...resolution too high to fit into video memory!\n", 933 var->xres, var->yres, var->bits_per_pixel); 934 NVTRACE("EXIT - EINVAL error\n"); 935 return -EINVAL; 936 } 937 } 938 939 if (var->xres_virtual * nom / den >= 8192) { 940 printk(KERN_WARNING PFX 941 "virtual X resolution (%d) is too high, lowering to %d\n", 942 var->xres_virtual, 8192 * den / nom - 16); 943 var->xres_virtual = 8192 * den / nom - 16; 944 } 945 946 if (var->xres_virtual < var->xres) { 947 printk(KERN_ERR PFX 948 "virtual X resolution (%d) is smaller than real\n", var->xres_virtual); 949 return -EINVAL; 950 } 951 952 if (var->yres_virtual < var->yres) { 953 printk(KERN_ERR PFX 954 "virtual Y resolution (%d) is smaller than real\n", var->yres_virtual); 955 return -EINVAL; 956 } 957 if (var->yres_virtual > 0x7fff/nom) 958 var->yres_virtual = 0x7fff/nom; 959 if (var->xres_virtual > 0x7fff/nom) 960 var->xres_virtual = 0x7fff/nom; 961 NVTRACE_LEAVE(); 962 return 0; 963 } 964 965 static void 966 riva_set_pattern(struct riva_par *par, int clr0, int clr1, int pat0, int pat1) 967 { 968 RIVA_FIFO_FREE(par->riva, Patt, 4); 969 NV_WR32(&par->riva.Patt->Color0, 0, clr0); 970 NV_WR32(&par->riva.Patt->Color1, 0, clr1); 971 NV_WR32(par->riva.Patt->Monochrome, 0, pat0); 972 NV_WR32(par->riva.Patt->Monochrome, 4, pat1); 973 } 974 975 /* acceleration routines */ 976 static inline void wait_for_idle(struct riva_par *par) 977 { 978 while (par->riva.Busy(&par->riva)); 979 } 980 981 /* 982 * Set ROP. Translate X rop into ROP3. Internal routine. 983 */ 984 static void 985 riva_set_rop_solid(struct riva_par *par, int rop) 986 { 987 riva_set_pattern(par, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF); 988 RIVA_FIFO_FREE(par->riva, Rop, 1); 989 NV_WR32(&par->riva.Rop->Rop3, 0, rop); 990 991 } 992 993 static void riva_setup_accel(struct fb_info *info) 994 { 995 struct riva_par *par = info->par; 996 997 RIVA_FIFO_FREE(par->riva, Clip, 2); 998 NV_WR32(&par->riva.Clip->TopLeft, 0, 0x0); 999 NV_WR32(&par->riva.Clip->WidthHeight, 0, 1000 (info->var.xres_virtual & 0xffff) | 1001 (info->var.yres_virtual << 16)); 1002 riva_set_rop_solid(par, 0xcc); 1003 wait_for_idle(par); 1004 } 1005 1006 /** 1007 * riva_get_cmap_len - query current color map length 1008 * @var: standard kernel fb changeable data 1009 * 1010 * DESCRIPTION: 1011 * Get current color map length. 1012 * 1013 * RETURNS: 1014 * Length of color map 1015 * 1016 * CALLED FROM: 1017 * rivafb_setcolreg() 1018 */ 1019 static int riva_get_cmap_len(const struct fb_var_screeninfo *var) 1020 { 1021 int rc = 256; /* reasonable default */ 1022 1023 switch (var->green.length) { 1024 case 8: 1025 rc = 256; /* 256 entries (2^8), 8 bpp and RGB8888 */ 1026 break; 1027 case 5: 1028 rc = 32; /* 32 entries (2^5), 16 bpp, RGB555 */ 1029 break; 1030 case 6: 1031 rc = 64; /* 64 entries (2^6), 16 bpp, RGB565 */ 1032 break; 1033 default: 1034 /* should not occur */ 1035 break; 1036 } 1037 return rc; 1038 } 1039 1040 /* ------------------------------------------------------------------------- * 1041 * 1042 * framebuffer operations 1043 * 1044 * ------------------------------------------------------------------------- */ 1045 1046 static int rivafb_open(struct fb_info *info, int user) 1047 { 1048 struct riva_par *par = info->par; 1049 1050 NVTRACE_ENTER(); 1051 mutex_lock(&par->open_lock); 1052 if (!par->ref_count) { 1053 #ifdef CONFIG_X86 1054 memset(&par->state, 0, sizeof(struct vgastate)); 1055 par->state.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS; 1056 /* save the DAC for Riva128 */ 1057 if (par->riva.Architecture == NV_ARCH_03) 1058 par->state.flags |= VGA_SAVE_CMAP; 1059 save_vga(&par->state); 1060 #endif 1061 /* vgaHWunlock() + riva unlock (0x7F) */ 1062 CRTCout(par, 0x11, 0xFF); 1063 par->riva.LockUnlock(&par->riva, 0); 1064 1065 riva_save_state(par, &par->initial_state); 1066 } 1067 par->ref_count++; 1068 mutex_unlock(&par->open_lock); 1069 NVTRACE_LEAVE(); 1070 return 0; 1071 } 1072 1073 static int rivafb_release(struct fb_info *info, int user) 1074 { 1075 struct riva_par *par = info->par; 1076 1077 NVTRACE_ENTER(); 1078 mutex_lock(&par->open_lock); 1079 if (!par->ref_count) { 1080 mutex_unlock(&par->open_lock); 1081 return -EINVAL; 1082 } 1083 if (par->ref_count == 1) { 1084 par->riva.LockUnlock(&par->riva, 0); 1085 par->riva.LoadStateExt(&par->riva, &par->initial_state.ext); 1086 riva_load_state(par, &par->initial_state); 1087 #ifdef CONFIG_X86 1088 restore_vga(&par->state); 1089 #endif 1090 par->riva.LockUnlock(&par->riva, 1); 1091 } 1092 par->ref_count--; 1093 mutex_unlock(&par->open_lock); 1094 NVTRACE_LEAVE(); 1095 return 0; 1096 } 1097 1098 static int rivafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) 1099 { 1100 const struct fb_videomode *mode; 1101 struct riva_par *par = info->par; 1102 int nom, den; /* translating from pixels->bytes */ 1103 int mode_valid = 0; 1104 1105 NVTRACE_ENTER(); 1106 switch (var->bits_per_pixel) { 1107 case 1 ... 8: 1108 var->red.offset = var->green.offset = var->blue.offset = 0; 1109 var->red.length = var->green.length = var->blue.length = 8; 1110 var->bits_per_pixel = 8; 1111 nom = den = 1; 1112 break; 1113 case 9 ... 15: 1114 var->green.length = 5; 1115 /* fall through */ 1116 case 16: 1117 var->bits_per_pixel = 16; 1118 /* The Riva128 supports RGB555 only */ 1119 if (par->riva.Architecture == NV_ARCH_03) 1120 var->green.length = 5; 1121 if (var->green.length == 5) { 1122 /* 0rrrrrgg gggbbbbb */ 1123 var->red.offset = 10; 1124 var->green.offset = 5; 1125 var->blue.offset = 0; 1126 var->red.length = 5; 1127 var->green.length = 5; 1128 var->blue.length = 5; 1129 } else { 1130 /* rrrrrggg gggbbbbb */ 1131 var->red.offset = 11; 1132 var->green.offset = 5; 1133 var->blue.offset = 0; 1134 var->red.length = 5; 1135 var->green.length = 6; 1136 var->blue.length = 5; 1137 } 1138 nom = 2; 1139 den = 1; 1140 break; 1141 case 17 ... 32: 1142 var->red.length = var->green.length = var->blue.length = 8; 1143 var->bits_per_pixel = 32; 1144 var->red.offset = 16; 1145 var->green.offset = 8; 1146 var->blue.offset = 0; 1147 nom = 4; 1148 den = 1; 1149 break; 1150 default: 1151 printk(KERN_ERR PFX 1152 "mode %dx%dx%d rejected...color depth not supported.\n", 1153 var->xres, var->yres, var->bits_per_pixel); 1154 NVTRACE("EXIT, returning -EINVAL\n"); 1155 return -EINVAL; 1156 } 1157 1158 if (!strictmode) { 1159 if (!info->monspecs.vfmax || !info->monspecs.hfmax || 1160 !info->monspecs.dclkmax || !fb_validate_mode(var, info)) 1161 mode_valid = 1; 1162 } 1163 1164 /* calculate modeline if supported by monitor */ 1165 if (!mode_valid && info->monspecs.gtf) { 1166 if (!fb_get_mode(FB_MAXTIMINGS, 0, var, info)) 1167 mode_valid = 1; 1168 } 1169 1170 if (!mode_valid) { 1171 mode = fb_find_best_mode(var, &info->modelist); 1172 if (mode) { 1173 riva_update_var(var, mode); 1174 mode_valid = 1; 1175 } 1176 } 1177 1178 if (!mode_valid && info->monspecs.modedb_len) 1179 return -EINVAL; 1180 1181 if (var->xres_virtual < var->xres) 1182 var->xres_virtual = var->xres; 1183 if (var->yres_virtual <= var->yres) 1184 var->yres_virtual = -1; 1185 if (rivafb_do_maximize(info, var, nom, den) < 0) 1186 return -EINVAL; 1187 1188 /* truncate xoffset and yoffset to maximum if too high */ 1189 if (var->xoffset > var->xres_virtual - var->xres) 1190 var->xoffset = var->xres_virtual - var->xres - 1; 1191 1192 if (var->yoffset > var->yres_virtual - var->yres) 1193 var->yoffset = var->yres_virtual - var->yres - 1; 1194 1195 var->red.msb_right = 1196 var->green.msb_right = 1197 var->blue.msb_right = 1198 var->transp.offset = var->transp.length = var->transp.msb_right = 0; 1199 NVTRACE_LEAVE(); 1200 return 0; 1201 } 1202 1203 static int rivafb_set_par(struct fb_info *info) 1204 { 1205 struct riva_par *par = info->par; 1206 int rc = 0; 1207 1208 NVTRACE_ENTER(); 1209 /* vgaHWunlock() + riva unlock (0x7F) */ 1210 CRTCout(par, 0x11, 0xFF); 1211 par->riva.LockUnlock(&par->riva, 0); 1212 rc = riva_load_video_mode(info); 1213 if (rc) 1214 goto out; 1215 if(!(info->flags & FBINFO_HWACCEL_DISABLED)) 1216 riva_setup_accel(info); 1217 1218 par->cursor_reset = 1; 1219 info->fix.line_length = (info->var.xres_virtual * (info->var.bits_per_pixel >> 3)); 1220 info->fix.visual = (info->var.bits_per_pixel == 8) ? 1221 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR; 1222 1223 if (info->flags & FBINFO_HWACCEL_DISABLED) 1224 info->pixmap.scan_align = 1; 1225 else 1226 info->pixmap.scan_align = 4; 1227 1228 out: 1229 NVTRACE_LEAVE(); 1230 return rc; 1231 } 1232 1233 /** 1234 * rivafb_pan_display 1235 * @var: standard kernel fb changeable data 1236 * @con: TODO 1237 * @info: pointer to fb_info object containing info for current riva board 1238 * 1239 * DESCRIPTION: 1240 * Pan (or wrap, depending on the `vmode' field) the display using the 1241 * `xoffset' and `yoffset' fields of the `var' structure. 1242 * If the values don't fit, return -EINVAL. 1243 * 1244 * This call looks only at xoffset, yoffset and the FB_VMODE_YWRAP flag 1245 */ 1246 static int rivafb_pan_display(struct fb_var_screeninfo *var, 1247 struct fb_info *info) 1248 { 1249 struct riva_par *par = info->par; 1250 unsigned int base; 1251 1252 NVTRACE_ENTER(); 1253 base = var->yoffset * info->fix.line_length + var->xoffset; 1254 par->riva.SetStartAddress(&par->riva, base); 1255 NVTRACE_LEAVE(); 1256 return 0; 1257 } 1258 1259 static int rivafb_blank(int blank, struct fb_info *info) 1260 { 1261 struct riva_par *par= info->par; 1262 unsigned char tmp, vesa; 1263 1264 tmp = SEQin(par, 0x01) & ~0x20; /* screen on/off */ 1265 vesa = CRTCin(par, 0x1a) & ~0xc0; /* sync on/off */ 1266 1267 NVTRACE_ENTER(); 1268 1269 if (blank) 1270 tmp |= 0x20; 1271 1272 switch (blank) { 1273 case FB_BLANK_UNBLANK: 1274 case FB_BLANK_NORMAL: 1275 break; 1276 case FB_BLANK_VSYNC_SUSPEND: 1277 vesa |= 0x80; 1278 break; 1279 case FB_BLANK_HSYNC_SUSPEND: 1280 vesa |= 0x40; 1281 break; 1282 case FB_BLANK_POWERDOWN: 1283 vesa |= 0xc0; 1284 break; 1285 } 1286 1287 SEQout(par, 0x01, tmp); 1288 CRTCout(par, 0x1a, vesa); 1289 1290 NVTRACE_LEAVE(); 1291 1292 return 0; 1293 } 1294 1295 /** 1296 * rivafb_setcolreg 1297 * @regno: register index 1298 * @red: red component 1299 * @green: green component 1300 * @blue: blue component 1301 * @transp: transparency 1302 * @info: pointer to fb_info object containing info for current riva board 1303 * 1304 * DESCRIPTION: 1305 * Set a single color register. The values supplied have a 16 bit 1306 * magnitude. 1307 * 1308 * RETURNS: 1309 * Return != 0 for invalid regno. 1310 * 1311 * CALLED FROM: 1312 * fbcmap.c:fb_set_cmap() 1313 */ 1314 static int rivafb_setcolreg(unsigned regno, unsigned red, unsigned green, 1315 unsigned blue, unsigned transp, 1316 struct fb_info *info) 1317 { 1318 struct riva_par *par = info->par; 1319 RIVA_HW_INST *chip = &par->riva; 1320 int i; 1321 1322 if (regno >= riva_get_cmap_len(&info->var)) 1323 return -EINVAL; 1324 1325 if (info->var.grayscale) { 1326 /* gray = 0.30*R + 0.59*G + 0.11*B */ 1327 red = green = blue = 1328 (red * 77 + green * 151 + blue * 28) >> 8; 1329 } 1330 1331 if (regno < 16 && info->fix.visual == FB_VISUAL_DIRECTCOLOR) { 1332 ((u32 *) info->pseudo_palette)[regno] = 1333 (regno << info->var.red.offset) | 1334 (regno << info->var.green.offset) | 1335 (regno << info->var.blue.offset); 1336 /* 1337 * The Riva128 2D engine requires color information in 1338 * TrueColor format even if framebuffer is in DirectColor 1339 */ 1340 if (par->riva.Architecture == NV_ARCH_03) { 1341 switch (info->var.bits_per_pixel) { 1342 case 16: 1343 par->palette[regno] = ((red & 0xf800) >> 1) | 1344 ((green & 0xf800) >> 6) | 1345 ((blue & 0xf800) >> 11); 1346 break; 1347 case 32: 1348 par->palette[regno] = ((red & 0xff00) << 8) | 1349 ((green & 0xff00)) | 1350 ((blue & 0xff00) >> 8); 1351 break; 1352 } 1353 } 1354 } 1355 1356 switch (info->var.bits_per_pixel) { 1357 case 8: 1358 /* "transparent" stuff is completely ignored. */ 1359 riva_wclut(chip, regno, red >> 8, green >> 8, blue >> 8); 1360 break; 1361 case 16: 1362 if (info->var.green.length == 5) { 1363 for (i = 0; i < 8; i++) { 1364 riva_wclut(chip, regno*8+i, red >> 8, 1365 green >> 8, blue >> 8); 1366 } 1367 } else { 1368 u8 r, g, b; 1369 1370 if (regno < 32) { 1371 for (i = 0; i < 8; i++) { 1372 riva_wclut(chip, regno*8+i, 1373 red >> 8, green >> 8, 1374 blue >> 8); 1375 } 1376 } 1377 riva_rclut(chip, regno*4, &r, &g, &b); 1378 for (i = 0; i < 4; i++) 1379 riva_wclut(chip, regno*4+i, r, 1380 green >> 8, b); 1381 } 1382 break; 1383 case 32: 1384 riva_wclut(chip, regno, red >> 8, green >> 8, blue >> 8); 1385 break; 1386 default: 1387 /* do nothing */ 1388 break; 1389 } 1390 return 0; 1391 } 1392 1393 /** 1394 * rivafb_fillrect - hardware accelerated color fill function 1395 * @info: pointer to fb_info structure 1396 * @rect: pointer to fb_fillrect structure 1397 * 1398 * DESCRIPTION: 1399 * This function fills up a region of framebuffer memory with a solid 1400 * color with a choice of two different ROP's, copy or invert. 1401 * 1402 * CALLED FROM: 1403 * framebuffer hook 1404 */ 1405 static void rivafb_fillrect(struct fb_info *info, const struct fb_fillrect *rect) 1406 { 1407 struct riva_par *par = info->par; 1408 u_int color, rop = 0; 1409 1410 if ((info->flags & FBINFO_HWACCEL_DISABLED)) { 1411 cfb_fillrect(info, rect); 1412 return; 1413 } 1414 1415 if (info->var.bits_per_pixel == 8) 1416 color = rect->color; 1417 else { 1418 if (par->riva.Architecture != NV_ARCH_03) 1419 color = ((u32 *)info->pseudo_palette)[rect->color]; 1420 else 1421 color = par->palette[rect->color]; 1422 } 1423 1424 switch (rect->rop) { 1425 case ROP_XOR: 1426 rop = 0x66; 1427 break; 1428 case ROP_COPY: 1429 default: 1430 rop = 0xCC; 1431 break; 1432 } 1433 1434 riva_set_rop_solid(par, rop); 1435 1436 RIVA_FIFO_FREE(par->riva, Bitmap, 1); 1437 NV_WR32(&par->riva.Bitmap->Color1A, 0, color); 1438 1439 RIVA_FIFO_FREE(par->riva, Bitmap, 2); 1440 NV_WR32(&par->riva.Bitmap->UnclippedRectangle[0].TopLeft, 0, 1441 (rect->dx << 16) | rect->dy); 1442 mb(); 1443 NV_WR32(&par->riva.Bitmap->UnclippedRectangle[0].WidthHeight, 0, 1444 (rect->width << 16) | rect->height); 1445 mb(); 1446 riva_set_rop_solid(par, 0xcc); 1447 1448 } 1449 1450 /** 1451 * rivafb_copyarea - hardware accelerated blit function 1452 * @info: pointer to fb_info structure 1453 * @region: pointer to fb_copyarea structure 1454 * 1455 * DESCRIPTION: 1456 * This copies an area of pixels from one location to another 1457 * 1458 * CALLED FROM: 1459 * framebuffer hook 1460 */ 1461 static void rivafb_copyarea(struct fb_info *info, const struct fb_copyarea *region) 1462 { 1463 struct riva_par *par = info->par; 1464 1465 if ((info->flags & FBINFO_HWACCEL_DISABLED)) { 1466 cfb_copyarea(info, region); 1467 return; 1468 } 1469 1470 RIVA_FIFO_FREE(par->riva, Blt, 3); 1471 NV_WR32(&par->riva.Blt->TopLeftSrc, 0, 1472 (region->sy << 16) | region->sx); 1473 NV_WR32(&par->riva.Blt->TopLeftDst, 0, 1474 (region->dy << 16) | region->dx); 1475 mb(); 1476 NV_WR32(&par->riva.Blt->WidthHeight, 0, 1477 (region->height << 16) | region->width); 1478 mb(); 1479 } 1480 1481 static inline void convert_bgcolor_16(u32 *col) 1482 { 1483 *col = ((*col & 0x0000F800) << 8) 1484 | ((*col & 0x00007E0) << 5) 1485 | ((*col & 0x0000001F) << 3) 1486 | 0xFF000000; 1487 mb(); 1488 } 1489 1490 /** 1491 * rivafb_imageblit: hardware accelerated color expand function 1492 * @info: pointer to fb_info structure 1493 * @image: pointer to fb_image structure 1494 * 1495 * DESCRIPTION: 1496 * If the source is a monochrome bitmap, the function fills up a a region 1497 * of framebuffer memory with pixels whose color is determined by the bit 1498 * setting of the bitmap, 1 - foreground, 0 - background. 1499 * 1500 * If the source is not a monochrome bitmap, color expansion is not done. 1501 * In this case, it is channeled to a software function. 1502 * 1503 * CALLED FROM: 1504 * framebuffer hook 1505 */ 1506 static void rivafb_imageblit(struct fb_info *info, 1507 const struct fb_image *image) 1508 { 1509 struct riva_par *par = info->par; 1510 u32 fgx = 0, bgx = 0, width, tmp; 1511 u8 *cdat = (u8 *) image->data; 1512 volatile u32 __iomem *d; 1513 int i, size; 1514 1515 if ((info->flags & FBINFO_HWACCEL_DISABLED) || image->depth != 1) { 1516 cfb_imageblit(info, image); 1517 return; 1518 } 1519 1520 switch (info->var.bits_per_pixel) { 1521 case 8: 1522 fgx = image->fg_color; 1523 bgx = image->bg_color; 1524 break; 1525 case 16: 1526 case 32: 1527 if (par->riva.Architecture != NV_ARCH_03) { 1528 fgx = ((u32 *)info->pseudo_palette)[image->fg_color]; 1529 bgx = ((u32 *)info->pseudo_palette)[image->bg_color]; 1530 } else { 1531 fgx = par->palette[image->fg_color]; 1532 bgx = par->palette[image->bg_color]; 1533 } 1534 if (info->var.green.length == 6) 1535 convert_bgcolor_16(&bgx); 1536 break; 1537 } 1538 1539 RIVA_FIFO_FREE(par->riva, Bitmap, 7); 1540 NV_WR32(&par->riva.Bitmap->ClipE.TopLeft, 0, 1541 (image->dy << 16) | (image->dx & 0xFFFF)); 1542 NV_WR32(&par->riva.Bitmap->ClipE.BottomRight, 0, 1543 (((image->dy + image->height) << 16) | 1544 ((image->dx + image->width) & 0xffff))); 1545 NV_WR32(&par->riva.Bitmap->Color0E, 0, bgx); 1546 NV_WR32(&par->riva.Bitmap->Color1E, 0, fgx); 1547 NV_WR32(&par->riva.Bitmap->WidthHeightInE, 0, 1548 (image->height << 16) | ((image->width + 31) & ~31)); 1549 NV_WR32(&par->riva.Bitmap->WidthHeightOutE, 0, 1550 (image->height << 16) | ((image->width + 31) & ~31)); 1551 NV_WR32(&par->riva.Bitmap->PointE, 0, 1552 (image->dy << 16) | (image->dx & 0xFFFF)); 1553 1554 d = &par->riva.Bitmap->MonochromeData01E; 1555 1556 width = (image->width + 31)/32; 1557 size = width * image->height; 1558 while (size >= 16) { 1559 RIVA_FIFO_FREE(par->riva, Bitmap, 16); 1560 for (i = 0; i < 16; i++) { 1561 tmp = *((u32 *)cdat); 1562 cdat = (u8 *)((u32 *)cdat + 1); 1563 reverse_order(&tmp); 1564 NV_WR32(d, i*4, tmp); 1565 } 1566 size -= 16; 1567 } 1568 if (size) { 1569 RIVA_FIFO_FREE(par->riva, Bitmap, size); 1570 for (i = 0; i < size; i++) { 1571 tmp = *((u32 *) cdat); 1572 cdat = (u8 *)((u32 *)cdat + 1); 1573 reverse_order(&tmp); 1574 NV_WR32(d, i*4, tmp); 1575 } 1576 } 1577 } 1578 1579 /** 1580 * rivafb_cursor - hardware cursor function 1581 * @info: pointer to info structure 1582 * @cursor: pointer to fbcursor structure 1583 * 1584 * DESCRIPTION: 1585 * A cursor function that supports displaying a cursor image via hardware. 1586 * Within the kernel, copy and invert rops are supported. If exported 1587 * to user space, only the copy rop will be supported. 1588 * 1589 * CALLED FROM 1590 * framebuffer hook 1591 */ 1592 static int rivafb_cursor(struct fb_info *info, struct fb_cursor *cursor) 1593 { 1594 struct riva_par *par = info->par; 1595 u8 data[MAX_CURS * MAX_CURS/8]; 1596 int i, set = cursor->set; 1597 u16 fg, bg; 1598 1599 if (cursor->image.width > MAX_CURS || cursor->image.height > MAX_CURS) 1600 return -ENXIO; 1601 1602 par->riva.ShowHideCursor(&par->riva, 0); 1603 1604 if (par->cursor_reset) { 1605 set = FB_CUR_SETALL; 1606 par->cursor_reset = 0; 1607 } 1608 1609 if (set & FB_CUR_SETSIZE) 1610 memset_io(par->riva.CURSOR, 0, MAX_CURS * MAX_CURS * 2); 1611 1612 if (set & FB_CUR_SETPOS) { 1613 u32 xx, yy, temp; 1614 1615 yy = cursor->image.dy - info->var.yoffset; 1616 xx = cursor->image.dx - info->var.xoffset; 1617 temp = xx & 0xFFFF; 1618 temp |= yy << 16; 1619 1620 NV_WR32(par->riva.PRAMDAC, 0x0000300, temp); 1621 } 1622 1623 1624 if (set & (FB_CUR_SETSHAPE | FB_CUR_SETCMAP | FB_CUR_SETIMAGE)) { 1625 u32 bg_idx = cursor->image.bg_color; 1626 u32 fg_idx = cursor->image.fg_color; 1627 u32 s_pitch = (cursor->image.width+7) >> 3; 1628 u32 d_pitch = MAX_CURS/8; 1629 u8 *dat = (u8 *) cursor->image.data; 1630 u8 *msk = (u8 *) cursor->mask; 1631 u8 *src; 1632 1633 src = kmalloc(s_pitch * cursor->image.height, GFP_ATOMIC); 1634 1635 if (src) { 1636 switch (cursor->rop) { 1637 case ROP_XOR: 1638 for (i = 0; i < s_pitch * cursor->image.height; i++) 1639 src[i] = dat[i] ^ msk[i]; 1640 break; 1641 case ROP_COPY: 1642 default: 1643 for (i = 0; i < s_pitch * cursor->image.height; i++) 1644 src[i] = dat[i] & msk[i]; 1645 break; 1646 } 1647 1648 fb_pad_aligned_buffer(data, d_pitch, src, s_pitch, 1649 cursor->image.height); 1650 1651 bg = ((info->cmap.red[bg_idx] & 0xf8) << 7) | 1652 ((info->cmap.green[bg_idx] & 0xf8) << 2) | 1653 ((info->cmap.blue[bg_idx] & 0xf8) >> 3) | 1654 1 << 15; 1655 1656 fg = ((info->cmap.red[fg_idx] & 0xf8) << 7) | 1657 ((info->cmap.green[fg_idx] & 0xf8) << 2) | 1658 ((info->cmap.blue[fg_idx] & 0xf8) >> 3) | 1659 1 << 15; 1660 1661 par->riva.LockUnlock(&par->riva, 0); 1662 1663 rivafb_load_cursor_image(par, data, bg, fg, 1664 cursor->image.width, 1665 cursor->image.height); 1666 kfree(src); 1667 } 1668 } 1669 1670 if (cursor->enable) 1671 par->riva.ShowHideCursor(&par->riva, 1); 1672 1673 return 0; 1674 } 1675 1676 static int rivafb_sync(struct fb_info *info) 1677 { 1678 struct riva_par *par = info->par; 1679 1680 wait_for_idle(par); 1681 return 0; 1682 } 1683 1684 /* ------------------------------------------------------------------------- * 1685 * 1686 * initialization helper functions 1687 * 1688 * ------------------------------------------------------------------------- */ 1689 1690 /* kernel interface */ 1691 static struct fb_ops riva_fb_ops = { 1692 .owner = THIS_MODULE, 1693 .fb_open = rivafb_open, 1694 .fb_release = rivafb_release, 1695 .fb_check_var = rivafb_check_var, 1696 .fb_set_par = rivafb_set_par, 1697 .fb_setcolreg = rivafb_setcolreg, 1698 .fb_pan_display = rivafb_pan_display, 1699 .fb_blank = rivafb_blank, 1700 .fb_fillrect = rivafb_fillrect, 1701 .fb_copyarea = rivafb_copyarea, 1702 .fb_imageblit = rivafb_imageblit, 1703 .fb_cursor = rivafb_cursor, 1704 .fb_sync = rivafb_sync, 1705 }; 1706 1707 static int riva_set_fbinfo(struct fb_info *info) 1708 { 1709 unsigned int cmap_len; 1710 struct riva_par *par = info->par; 1711 1712 NVTRACE_ENTER(); 1713 info->flags = FBINFO_DEFAULT 1714 | FBINFO_HWACCEL_XPAN 1715 | FBINFO_HWACCEL_YPAN 1716 | FBINFO_HWACCEL_COPYAREA 1717 | FBINFO_HWACCEL_FILLRECT 1718 | FBINFO_HWACCEL_IMAGEBLIT; 1719 1720 /* Accel seems to not work properly on NV30 yet...*/ 1721 if ((par->riva.Architecture == NV_ARCH_30) || noaccel) { 1722 printk(KERN_DEBUG PFX "disabling acceleration\n"); 1723 info->flags |= FBINFO_HWACCEL_DISABLED; 1724 } 1725 1726 info->var = rivafb_default_var; 1727 info->fix.visual = (info->var.bits_per_pixel == 8) ? 1728 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR; 1729 1730 info->pseudo_palette = par->pseudo_palette; 1731 1732 cmap_len = riva_get_cmap_len(&info->var); 1733 fb_alloc_cmap(&info->cmap, cmap_len, 0); 1734 1735 info->pixmap.size = 8 * 1024; 1736 info->pixmap.buf_align = 4; 1737 info->pixmap.access_align = 32; 1738 info->pixmap.flags = FB_PIXMAP_SYSTEM; 1739 info->var.yres_virtual = -1; 1740 NVTRACE_LEAVE(); 1741 return (rivafb_check_var(&info->var, info)); 1742 } 1743 1744 #ifdef CONFIG_PPC_OF 1745 static int riva_get_EDID_OF(struct fb_info *info, struct pci_dev *pd) 1746 { 1747 struct riva_par *par = info->par; 1748 struct device_node *dp; 1749 const unsigned char *pedid = NULL; 1750 const unsigned char *disptype = NULL; 1751 static char *propnames[] = { 1752 "DFP,EDID", "LCD,EDID", "EDID", "EDID1", "EDID,B", "EDID,A", NULL }; 1753 int i; 1754 1755 NVTRACE_ENTER(); 1756 dp = pci_device_to_OF_node(pd); 1757 for (; dp != NULL; dp = dp->child) { 1758 disptype = of_get_property(dp, "display-type", NULL); 1759 if (disptype == NULL) 1760 continue; 1761 if (strncmp(disptype, "LCD", 3) != 0) 1762 continue; 1763 for (i = 0; propnames[i] != NULL; ++i) { 1764 pedid = of_get_property(dp, propnames[i], NULL); 1765 if (pedid != NULL) { 1766 par->EDID = (unsigned char *)pedid; 1767 NVTRACE("LCD found.\n"); 1768 return 1; 1769 } 1770 } 1771 } 1772 NVTRACE_LEAVE(); 1773 return 0; 1774 } 1775 #endif /* CONFIG_PPC_OF */ 1776 1777 #if defined(CONFIG_FB_RIVA_I2C) && !defined(CONFIG_PPC_OF) 1778 static int riva_get_EDID_i2c(struct fb_info *info) 1779 { 1780 struct riva_par *par = info->par; 1781 struct fb_var_screeninfo var; 1782 int i; 1783 1784 NVTRACE_ENTER(); 1785 riva_create_i2c_busses(par); 1786 for (i = 0; i < 3; i++) { 1787 if (!par->chan[i].par) 1788 continue; 1789 riva_probe_i2c_connector(par, i, &par->EDID); 1790 if (par->EDID && !fb_parse_edid(par->EDID, &var)) { 1791 printk(PFX "Found EDID Block from BUS %i\n", i); 1792 break; 1793 } 1794 } 1795 1796 NVTRACE_LEAVE(); 1797 return (par->EDID) ? 1 : 0; 1798 } 1799 #endif /* CONFIG_FB_RIVA_I2C */ 1800 1801 static void riva_update_default_var(struct fb_var_screeninfo *var, 1802 struct fb_info *info) 1803 { 1804 struct fb_monspecs *specs = &info->monspecs; 1805 struct fb_videomode modedb; 1806 1807 NVTRACE_ENTER(); 1808 /* respect mode options */ 1809 if (mode_option) { 1810 fb_find_mode(var, info, mode_option, 1811 specs->modedb, specs->modedb_len, 1812 NULL, 8); 1813 } else if (specs->modedb != NULL) { 1814 /* get first mode in database as fallback */ 1815 modedb = specs->modedb[0]; 1816 /* get preferred timing */ 1817 if (info->monspecs.misc & FB_MISC_1ST_DETAIL) { 1818 int i; 1819 1820 for (i = 0; i < specs->modedb_len; i++) { 1821 if (specs->modedb[i].flag & FB_MODE_IS_FIRST) { 1822 modedb = specs->modedb[i]; 1823 break; 1824 } 1825 } 1826 } 1827 var->bits_per_pixel = 8; 1828 riva_update_var(var, &modedb); 1829 } 1830 NVTRACE_LEAVE(); 1831 } 1832 1833 1834 static void riva_get_EDID(struct fb_info *info, struct pci_dev *pdev) 1835 { 1836 NVTRACE_ENTER(); 1837 #ifdef CONFIG_PPC_OF 1838 if (!riva_get_EDID_OF(info, pdev)) 1839 printk(PFX "could not retrieve EDID from OF\n"); 1840 #elif defined(CONFIG_FB_RIVA_I2C) 1841 if (!riva_get_EDID_i2c(info)) 1842 printk(PFX "could not retrieve EDID from DDC/I2C\n"); 1843 #endif 1844 NVTRACE_LEAVE(); 1845 } 1846 1847 1848 static void riva_get_edidinfo(struct fb_info *info) 1849 { 1850 struct fb_var_screeninfo *var = &rivafb_default_var; 1851 struct riva_par *par = info->par; 1852 1853 fb_edid_to_monspecs(par->EDID, &info->monspecs); 1854 fb_videomode_to_modelist(info->monspecs.modedb, info->monspecs.modedb_len, 1855 &info->modelist); 1856 riva_update_default_var(var, info); 1857 1858 /* if user specified flatpanel, we respect that */ 1859 if (info->monspecs.input & FB_DISP_DDI) 1860 par->FlatPanel = 1; 1861 } 1862 1863 /* ------------------------------------------------------------------------- * 1864 * 1865 * PCI bus 1866 * 1867 * ------------------------------------------------------------------------- */ 1868 1869 static u32 riva_get_arch(struct pci_dev *pd) 1870 { 1871 u32 arch = 0; 1872 1873 switch (pd->device & 0x0ff0) { 1874 case 0x0100: /* GeForce 256 */ 1875 case 0x0110: /* GeForce2 MX */ 1876 case 0x0150: /* GeForce2 */ 1877 case 0x0170: /* GeForce4 MX */ 1878 case 0x0180: /* GeForce4 MX (8x AGP) */ 1879 case 0x01A0: /* nForce */ 1880 case 0x01F0: /* nForce2 */ 1881 arch = NV_ARCH_10; 1882 break; 1883 case 0x0200: /* GeForce3 */ 1884 case 0x0250: /* GeForce4 Ti */ 1885 case 0x0280: /* GeForce4 Ti (8x AGP) */ 1886 arch = NV_ARCH_20; 1887 break; 1888 case 0x0300: /* GeForceFX 5800 */ 1889 case 0x0310: /* GeForceFX 5600 */ 1890 case 0x0320: /* GeForceFX 5200 */ 1891 case 0x0330: /* GeForceFX 5900 */ 1892 case 0x0340: /* GeForceFX 5700 */ 1893 arch = NV_ARCH_30; 1894 break; 1895 case 0x0020: /* TNT, TNT2 */ 1896 arch = NV_ARCH_04; 1897 break; 1898 case 0x0010: /* Riva128 */ 1899 arch = NV_ARCH_03; 1900 break; 1901 default: /* unknown architecture */ 1902 break; 1903 } 1904 return arch; 1905 } 1906 1907 static int rivafb_probe(struct pci_dev *pd, const struct pci_device_id *ent) 1908 { 1909 struct riva_par *default_par; 1910 struct fb_info *info; 1911 int ret; 1912 1913 NVTRACE_ENTER(); 1914 assert(pd != NULL); 1915 1916 info = framebuffer_alloc(sizeof(struct riva_par), &pd->dev); 1917 if (!info) { 1918 printk (KERN_ERR PFX "could not allocate memory\n"); 1919 ret = -ENOMEM; 1920 goto err_ret; 1921 } 1922 default_par = info->par; 1923 default_par->pdev = pd; 1924 1925 info->pixmap.addr = kzalloc(8 * 1024, GFP_KERNEL); 1926 if (info->pixmap.addr == NULL) { 1927 ret = -ENOMEM; 1928 goto err_framebuffer_release; 1929 } 1930 1931 ret = pci_enable_device(pd); 1932 if (ret < 0) { 1933 printk(KERN_ERR PFX "cannot enable PCI device\n"); 1934 goto err_free_pixmap; 1935 } 1936 1937 ret = pci_request_regions(pd, "rivafb"); 1938 if (ret < 0) { 1939 printk(KERN_ERR PFX "cannot request PCI regions\n"); 1940 goto err_disable_device; 1941 } 1942 1943 mutex_init(&default_par->open_lock); 1944 default_par->riva.Architecture = riva_get_arch(pd); 1945 1946 default_par->Chipset = (pd->vendor << 16) | pd->device; 1947 printk(KERN_INFO PFX "nVidia device/chipset %X\n",default_par->Chipset); 1948 1949 if(default_par->riva.Architecture == 0) { 1950 printk(KERN_ERR PFX "unknown NV_ARCH\n"); 1951 ret=-ENODEV; 1952 goto err_release_region; 1953 } 1954 if(default_par->riva.Architecture == NV_ARCH_10 || 1955 default_par->riva.Architecture == NV_ARCH_20 || 1956 default_par->riva.Architecture == NV_ARCH_30) { 1957 sprintf(rivafb_fix.id, "NV%x", (pd->device & 0x0ff0) >> 4); 1958 } else { 1959 sprintf(rivafb_fix.id, "NV%x", default_par->riva.Architecture); 1960 } 1961 1962 default_par->FlatPanel = flatpanel; 1963 if (flatpanel == 1) 1964 printk(KERN_INFO PFX "flatpanel support enabled\n"); 1965 default_par->forceCRTC = forceCRTC; 1966 1967 rivafb_fix.mmio_len = pci_resource_len(pd, 0); 1968 rivafb_fix.smem_len = pci_resource_len(pd, 1); 1969 1970 { 1971 /* enable IO and mem if not already done */ 1972 unsigned short cmd; 1973 1974 pci_read_config_word(pd, PCI_COMMAND, &cmd); 1975 cmd |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY); 1976 pci_write_config_word(pd, PCI_COMMAND, cmd); 1977 } 1978 1979 rivafb_fix.mmio_start = pci_resource_start(pd, 0); 1980 rivafb_fix.smem_start = pci_resource_start(pd, 1); 1981 1982 default_par->ctrl_base = ioremap(rivafb_fix.mmio_start, 1983 rivafb_fix.mmio_len); 1984 if (!default_par->ctrl_base) { 1985 printk(KERN_ERR PFX "cannot ioremap MMIO base\n"); 1986 ret = -EIO; 1987 goto err_release_region; 1988 } 1989 1990 switch (default_par->riva.Architecture) { 1991 case NV_ARCH_03: 1992 /* Riva128's PRAMIN is in the "framebuffer" space 1993 * Since these cards were never made with more than 8 megabytes 1994 * we can safely allocate this separately. 1995 */ 1996 default_par->riva.PRAMIN = ioremap(rivafb_fix.smem_start + 0x00C00000, 0x00008000); 1997 if (!default_par->riva.PRAMIN) { 1998 printk(KERN_ERR PFX "cannot ioremap PRAMIN region\n"); 1999 ret = -EIO; 2000 goto err_iounmap_ctrl_base; 2001 } 2002 break; 2003 case NV_ARCH_04: 2004 case NV_ARCH_10: 2005 case NV_ARCH_20: 2006 case NV_ARCH_30: 2007 default_par->riva.PCRTC0 = 2008 (u32 __iomem *)(default_par->ctrl_base + 0x00600000); 2009 default_par->riva.PRAMIN = 2010 (u32 __iomem *)(default_par->ctrl_base + 0x00710000); 2011 break; 2012 } 2013 riva_common_setup(default_par); 2014 2015 if (default_par->riva.Architecture == NV_ARCH_03) { 2016 default_par->riva.PCRTC = default_par->riva.PCRTC0 2017 = default_par->riva.PGRAPH; 2018 } 2019 2020 rivafb_fix.smem_len = riva_get_memlen(default_par) * 1024; 2021 default_par->dclk_max = riva_get_maxdclk(default_par) * 1000; 2022 info->screen_base = ioremap(rivafb_fix.smem_start, 2023 rivafb_fix.smem_len); 2024 if (!info->screen_base) { 2025 printk(KERN_ERR PFX "cannot ioremap FB base\n"); 2026 ret = -EIO; 2027 goto err_iounmap_pramin; 2028 } 2029 2030 #ifdef CONFIG_MTRR 2031 if (!nomtrr) { 2032 default_par->mtrr.vram = mtrr_add(rivafb_fix.smem_start, 2033 rivafb_fix.smem_len, 2034 MTRR_TYPE_WRCOMB, 1); 2035 if (default_par->mtrr.vram < 0) { 2036 printk(KERN_ERR PFX "unable to setup MTRR\n"); 2037 } else { 2038 default_par->mtrr.vram_valid = 1; 2039 /* let there be speed */ 2040 printk(KERN_INFO PFX "RIVA MTRR set to ON\n"); 2041 } 2042 } 2043 #endif /* CONFIG_MTRR */ 2044 2045 info->fbops = &riva_fb_ops; 2046 info->fix = rivafb_fix; 2047 riva_get_EDID(info, pd); 2048 riva_get_edidinfo(info); 2049 2050 ret=riva_set_fbinfo(info); 2051 if (ret < 0) { 2052 printk(KERN_ERR PFX "error setting initial video mode\n"); 2053 goto err_iounmap_screen_base; 2054 } 2055 2056 fb_destroy_modedb(info->monspecs.modedb); 2057 info->monspecs.modedb = NULL; 2058 2059 pci_set_drvdata(pd, info); 2060 2061 if (backlight) 2062 riva_bl_init(info->par); 2063 2064 ret = register_framebuffer(info); 2065 if (ret < 0) { 2066 printk(KERN_ERR PFX 2067 "error registering riva framebuffer\n"); 2068 goto err_iounmap_screen_base; 2069 } 2070 2071 printk(KERN_INFO PFX 2072 "PCI nVidia %s framebuffer ver %s (%dMB @ 0x%lX)\n", 2073 info->fix.id, 2074 RIVAFB_VERSION, 2075 info->fix.smem_len / (1024 * 1024), 2076 info->fix.smem_start); 2077 2078 NVTRACE_LEAVE(); 2079 return 0; 2080 2081 err_iounmap_screen_base: 2082 #ifdef CONFIG_FB_RIVA_I2C 2083 riva_delete_i2c_busses(info->par); 2084 #endif 2085 iounmap(info->screen_base); 2086 err_iounmap_pramin: 2087 if (default_par->riva.Architecture == NV_ARCH_03) 2088 iounmap(default_par->riva.PRAMIN); 2089 err_iounmap_ctrl_base: 2090 iounmap(default_par->ctrl_base); 2091 err_release_region: 2092 pci_release_regions(pd); 2093 err_disable_device: 2094 err_free_pixmap: 2095 kfree(info->pixmap.addr); 2096 err_framebuffer_release: 2097 framebuffer_release(info); 2098 err_ret: 2099 return ret; 2100 } 2101 2102 static void rivafb_remove(struct pci_dev *pd) 2103 { 2104 struct fb_info *info = pci_get_drvdata(pd); 2105 struct riva_par *par = info->par; 2106 2107 NVTRACE_ENTER(); 2108 2109 #ifdef CONFIG_FB_RIVA_I2C 2110 riva_delete_i2c_busses(par); 2111 kfree(par->EDID); 2112 #endif 2113 2114 unregister_framebuffer(info); 2115 2116 riva_bl_exit(info); 2117 2118 #ifdef CONFIG_MTRR 2119 if (par->mtrr.vram_valid) 2120 mtrr_del(par->mtrr.vram, info->fix.smem_start, 2121 info->fix.smem_len); 2122 #endif /* CONFIG_MTRR */ 2123 2124 iounmap(par->ctrl_base); 2125 iounmap(info->screen_base); 2126 if (par->riva.Architecture == NV_ARCH_03) 2127 iounmap(par->riva.PRAMIN); 2128 pci_release_regions(pd); 2129 kfree(info->pixmap.addr); 2130 framebuffer_release(info); 2131 NVTRACE_LEAVE(); 2132 } 2133 2134 /* ------------------------------------------------------------------------- * 2135 * 2136 * initialization 2137 * 2138 * ------------------------------------------------------------------------- */ 2139 2140 #ifndef MODULE 2141 static int rivafb_setup(char *options) 2142 { 2143 char *this_opt; 2144 2145 NVTRACE_ENTER(); 2146 if (!options || !*options) 2147 return 0; 2148 2149 while ((this_opt = strsep(&options, ",")) != NULL) { 2150 if (!strncmp(this_opt, "forceCRTC", 9)) { 2151 char *p; 2152 2153 p = this_opt + 9; 2154 if (!*p || !*(++p)) continue; 2155 forceCRTC = *p - '0'; 2156 if (forceCRTC < 0 || forceCRTC > 1) 2157 forceCRTC = -1; 2158 } else if (!strncmp(this_opt, "flatpanel", 9)) { 2159 flatpanel = 1; 2160 } else if (!strncmp(this_opt, "backlight:", 10)) { 2161 backlight = simple_strtoul(this_opt+10, NULL, 0); 2162 #ifdef CONFIG_MTRR 2163 } else if (!strncmp(this_opt, "nomtrr", 6)) { 2164 nomtrr = 1; 2165 #endif 2166 } else if (!strncmp(this_opt, "strictmode", 10)) { 2167 strictmode = 1; 2168 } else if (!strncmp(this_opt, "noaccel", 7)) { 2169 noaccel = 1; 2170 } else 2171 mode_option = this_opt; 2172 } 2173 NVTRACE_LEAVE(); 2174 return 0; 2175 } 2176 #endif /* !MODULE */ 2177 2178 static struct pci_driver rivafb_driver = { 2179 .name = "rivafb", 2180 .id_table = rivafb_pci_tbl, 2181 .probe = rivafb_probe, 2182 .remove = rivafb_remove, 2183 }; 2184 2185 2186 2187 /* ------------------------------------------------------------------------- * 2188 * 2189 * modularization 2190 * 2191 * ------------------------------------------------------------------------- */ 2192 2193 static int rivafb_init(void) 2194 { 2195 #ifndef MODULE 2196 char *option = NULL; 2197 2198 if (fb_get_options("rivafb", &option)) 2199 return -ENODEV; 2200 rivafb_setup(option); 2201 #endif 2202 return pci_register_driver(&rivafb_driver); 2203 } 2204 2205 2206 module_init(rivafb_init); 2207 2208 static void __exit rivafb_exit(void) 2209 { 2210 pci_unregister_driver(&rivafb_driver); 2211 } 2212 2213 module_exit(rivafb_exit); 2214 2215 module_param(noaccel, bool, 0); 2216 MODULE_PARM_DESC(noaccel, "bool: disable acceleration"); 2217 module_param(flatpanel, int, 0); 2218 MODULE_PARM_DESC(flatpanel, "Enables experimental flat panel support for some chipsets. (0 or 1=enabled) (default=0)"); 2219 module_param(forceCRTC, int, 0); 2220 MODULE_PARM_DESC(forceCRTC, "Forces usage of a particular CRTC in case autodetection fails. (0 or 1) (default=autodetect)"); 2221 #ifdef CONFIG_MTRR 2222 module_param(nomtrr, bool, 0); 2223 MODULE_PARM_DESC(nomtrr, "Disables MTRR support (0 or 1=disabled) (default=0)"); 2224 #endif 2225 module_param(strictmode, bool, 0); 2226 MODULE_PARM_DESC(strictmode, "Only use video modes from EDID"); 2227 2228 MODULE_AUTHOR("Ani Joshi, maintainer"); 2229 MODULE_DESCRIPTION("Framebuffer driver for nVidia Riva 128, TNT, TNT2, and the GeForce series"); 2230 MODULE_LICENSE("GPL"); 2231