1 /* 2 * linux/drivers/video/riva/fbdev.c - nVidia RIVA 128/TNT/TNT2 fb driver 3 * 4 * Maintained by Ani Joshi <ajoshi@shell.unixbox.com> 5 * 6 * Copyright 1999-2000 Jeff Garzik 7 * 8 * Contributors: 9 * 10 * Ani Joshi: Lots of debugging and cleanup work, really helped 11 * get the driver going 12 * 13 * Ferenc Bakonyi: Bug fixes, cleanup, modularization 14 * 15 * Jindrich Makovicka: Accel code help, hw cursor, mtrr 16 * 17 * Paul Richards: Bug fixes, updates 18 * 19 * Initial template from skeletonfb.c, created 28 Dec 1997 by Geert Uytterhoeven 20 * Includes riva_hw.c from nVidia, see copyright below. 21 * KGI code provided the basis for state storage, init, and mode switching. 22 * 23 * This file is subject to the terms and conditions of the GNU General Public 24 * License. See the file COPYING in the main directory of this archive 25 * for more details. 26 * 27 * Known bugs and issues: 28 * restoring text mode fails 29 * doublescan modes are broken 30 */ 31 32 #include <linux/module.h> 33 #include <linux/kernel.h> 34 #include <linux/errno.h> 35 #include <linux/string.h> 36 #include <linux/mm.h> 37 #include <linux/slab.h> 38 #include <linux/delay.h> 39 #include <linux/fb.h> 40 #include <linux/init.h> 41 #include <linux/pci.h> 42 #include <linux/backlight.h> 43 #include <linux/bitrev.h> 44 #ifdef CONFIG_MTRR 45 #include <asm/mtrr.h> 46 #endif 47 #ifdef CONFIG_PPC_OF 48 #include <asm/prom.h> 49 #include <asm/pci-bridge.h> 50 #endif 51 #ifdef CONFIG_PMAC_BACKLIGHT 52 #include <asm/machdep.h> 53 #include <asm/backlight.h> 54 #endif 55 56 #include "rivafb.h" 57 #include "nvreg.h" 58 59 /* version number of this driver */ 60 #define RIVAFB_VERSION "0.9.5b" 61 62 /* ------------------------------------------------------------------------- * 63 * 64 * various helpful macros and constants 65 * 66 * ------------------------------------------------------------------------- */ 67 #ifdef CONFIG_FB_RIVA_DEBUG 68 #define NVTRACE printk 69 #else 70 #define NVTRACE if(0) printk 71 #endif 72 73 #define NVTRACE_ENTER(...) NVTRACE("%s START\n", __func__) 74 #define NVTRACE_LEAVE(...) NVTRACE("%s END\n", __func__) 75 76 #ifdef CONFIG_FB_RIVA_DEBUG 77 #define assert(expr) \ 78 if(!(expr)) { \ 79 printk( "Assertion failed! %s,%s,%s,line=%d\n",\ 80 #expr,__FILE__,__func__,__LINE__); \ 81 BUG(); \ 82 } 83 #else 84 #define assert(expr) 85 #endif 86 87 #define PFX "rivafb: " 88 89 /* macro that allows you to set overflow bits */ 90 #define SetBitField(value,from,to) SetBF(to,GetBF(value,from)) 91 #define SetBit(n) (1<<(n)) 92 #define Set8Bits(value) ((value)&0xff) 93 94 /* HW cursor parameters */ 95 #define MAX_CURS 32 96 97 /* ------------------------------------------------------------------------- * 98 * 99 * prototypes 100 * 101 * ------------------------------------------------------------------------- */ 102 103 static int rivafb_blank(int blank, struct fb_info *info); 104 105 /* ------------------------------------------------------------------------- * 106 * 107 * card identification 108 * 109 * ------------------------------------------------------------------------- */ 110 111 static struct pci_device_id rivafb_pci_tbl[] = { 112 { PCI_VENDOR_ID_NVIDIA_SGS, PCI_DEVICE_ID_NVIDIA_SGS_RIVA128, 113 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 114 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT, 115 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 116 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT2, 117 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 118 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_UTNT2, 119 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 120 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_VTNT2, 121 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 122 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_UVTNT2, 123 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 124 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_ITNT2, 125 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 126 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_SDR, 127 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 128 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_DDR, 129 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 130 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO, 131 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 132 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX, 133 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 134 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX2, 135 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 136 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GO, 137 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 138 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO2_MXR, 139 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 140 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS, 141 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 142 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS2, 143 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 144 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_ULTRA, 145 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 146 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO2_PRO, 147 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 148 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_460, 149 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 150 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440, 151 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 152 // NF2/IGP version, GeForce 4 MX, NV18 153 { PCI_VENDOR_ID_NVIDIA, 0x01f0, 154 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 155 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_420, 156 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 157 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO, 158 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 159 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO, 160 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 161 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO_M32, 162 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 163 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_500XGL, 164 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 165 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO_M64, 166 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 167 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_200, 168 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 169 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_550XGL, 170 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 171 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_500_GOGL, 172 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 173 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_IGEFORCE2, 174 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 175 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3, 176 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 177 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3_1, 178 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 179 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3_2, 180 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 181 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_DDC, 182 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 183 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4600, 184 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 185 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4400, 186 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 187 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4200, 188 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 189 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_900XGL, 190 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 191 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_750XGL, 192 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 193 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_700XGL, 194 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 195 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO_5200, 196 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 197 { 0, } /* terminate list */ 198 }; 199 MODULE_DEVICE_TABLE(pci, rivafb_pci_tbl); 200 201 /* ------------------------------------------------------------------------- * 202 * 203 * global variables 204 * 205 * ------------------------------------------------------------------------- */ 206 207 /* command line data, set in rivafb_setup() */ 208 static int flatpanel = -1; /* Autodetect later */ 209 static int forceCRTC = -1; 210 static bool noaccel = 0; 211 #ifdef CONFIG_MTRR 212 static bool nomtrr = 0; 213 #endif 214 #ifdef CONFIG_PMAC_BACKLIGHT 215 static int backlight = 1; 216 #else 217 static int backlight = 0; 218 #endif 219 220 static char *mode_option = NULL; 221 static bool strictmode = 0; 222 223 static struct fb_fix_screeninfo rivafb_fix = { 224 .type = FB_TYPE_PACKED_PIXELS, 225 .xpanstep = 1, 226 .ypanstep = 1, 227 }; 228 229 static struct fb_var_screeninfo rivafb_default_var = { 230 .xres = 640, 231 .yres = 480, 232 .xres_virtual = 640, 233 .yres_virtual = 480, 234 .bits_per_pixel = 8, 235 .red = {0, 8, 0}, 236 .green = {0, 8, 0}, 237 .blue = {0, 8, 0}, 238 .transp = {0, 0, 0}, 239 .activate = FB_ACTIVATE_NOW, 240 .height = -1, 241 .width = -1, 242 .pixclock = 39721, 243 .left_margin = 40, 244 .right_margin = 24, 245 .upper_margin = 32, 246 .lower_margin = 11, 247 .hsync_len = 96, 248 .vsync_len = 2, 249 .vmode = FB_VMODE_NONINTERLACED 250 }; 251 252 /* from GGI */ 253 static const struct riva_regs reg_template = { 254 {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, /* ATTR */ 255 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, 256 0x41, 0x01, 0x0F, 0x00, 0x00}, 257 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* CRT */ 258 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 259 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE3, /* 0x10 */ 260 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 261 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x20 */ 262 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 263 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x30 */ 264 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 265 0x00, /* 0x40 */ 266 }, 267 {0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F, /* GRA */ 268 0xFF}, 269 {0x03, 0x01, 0x0F, 0x00, 0x0E}, /* SEQ */ 270 0xEB /* MISC */ 271 }; 272 273 /* 274 * Backlight control 275 */ 276 #ifdef CONFIG_FB_RIVA_BACKLIGHT 277 /* We do not have any information about which values are allowed, thus 278 * we used safe values. 279 */ 280 #define MIN_LEVEL 0x158 281 #define MAX_LEVEL 0x534 282 #define LEVEL_STEP ((MAX_LEVEL - MIN_LEVEL) / FB_BACKLIGHT_MAX) 283 284 static int riva_bl_get_level_brightness(struct riva_par *par, 285 int level) 286 { 287 struct fb_info *info = pci_get_drvdata(par->pdev); 288 int nlevel; 289 290 /* Get and convert the value */ 291 /* No locking on bl_curve since accessing a single value */ 292 nlevel = MIN_LEVEL + info->bl_curve[level] * LEVEL_STEP; 293 294 if (nlevel < 0) 295 nlevel = 0; 296 else if (nlevel < MIN_LEVEL) 297 nlevel = MIN_LEVEL; 298 else if (nlevel > MAX_LEVEL) 299 nlevel = MAX_LEVEL; 300 301 return nlevel; 302 } 303 304 static int riva_bl_update_status(struct backlight_device *bd) 305 { 306 struct riva_par *par = bl_get_data(bd); 307 U032 tmp_pcrt, tmp_pmc; 308 int level; 309 310 if (bd->props.power != FB_BLANK_UNBLANK || 311 bd->props.fb_blank != FB_BLANK_UNBLANK) 312 level = 0; 313 else 314 level = bd->props.brightness; 315 316 tmp_pmc = NV_RD32(par->riva.PMC, 0x10F0) & 0x0000FFFF; 317 tmp_pcrt = NV_RD32(par->riva.PCRTC0, 0x081C) & 0xFFFFFFFC; 318 if(level > 0) { 319 tmp_pcrt |= 0x1; 320 tmp_pmc |= (1 << 31); /* backlight bit */ 321 tmp_pmc |= riva_bl_get_level_brightness(par, level) << 16; /* level */ 322 } 323 NV_WR32(par->riva.PCRTC0, 0x081C, tmp_pcrt); 324 NV_WR32(par->riva.PMC, 0x10F0, tmp_pmc); 325 326 return 0; 327 } 328 329 static const struct backlight_ops riva_bl_ops = { 330 .update_status = riva_bl_update_status, 331 }; 332 333 static void riva_bl_init(struct riva_par *par) 334 { 335 struct backlight_properties props; 336 struct fb_info *info = pci_get_drvdata(par->pdev); 337 struct backlight_device *bd; 338 char name[12]; 339 340 if (!par->FlatPanel) 341 return; 342 343 #ifdef CONFIG_PMAC_BACKLIGHT 344 if (!machine_is(powermac) || 345 !pmac_has_backlight_type("mnca")) 346 return; 347 #endif 348 349 snprintf(name, sizeof(name), "rivabl%d", info->node); 350 351 memset(&props, 0, sizeof(struct backlight_properties)); 352 props.type = BACKLIGHT_RAW; 353 props.max_brightness = FB_BACKLIGHT_LEVELS - 1; 354 bd = backlight_device_register(name, info->dev, par, &riva_bl_ops, 355 &props); 356 if (IS_ERR(bd)) { 357 info->bl_dev = NULL; 358 printk(KERN_WARNING "riva: Backlight registration failed\n"); 359 goto error; 360 } 361 362 info->bl_dev = bd; 363 fb_bl_default_curve(info, 0, 364 MIN_LEVEL * FB_BACKLIGHT_MAX / MAX_LEVEL, 365 FB_BACKLIGHT_MAX); 366 367 bd->props.brightness = bd->props.max_brightness; 368 bd->props.power = FB_BLANK_UNBLANK; 369 backlight_update_status(bd); 370 371 printk("riva: Backlight initialized (%s)\n", name); 372 373 return; 374 375 error: 376 return; 377 } 378 379 static void riva_bl_exit(struct fb_info *info) 380 { 381 struct backlight_device *bd = info->bl_dev; 382 383 backlight_device_unregister(bd); 384 printk("riva: Backlight unloaded\n"); 385 } 386 #else 387 static inline void riva_bl_init(struct riva_par *par) {} 388 static inline void riva_bl_exit(struct fb_info *info) {} 389 #endif /* CONFIG_FB_RIVA_BACKLIGHT */ 390 391 /* ------------------------------------------------------------------------- * 392 * 393 * MMIO access macros 394 * 395 * ------------------------------------------------------------------------- */ 396 397 static inline void CRTCout(struct riva_par *par, unsigned char index, 398 unsigned char val) 399 { 400 VGA_WR08(par->riva.PCIO, 0x3d4, index); 401 VGA_WR08(par->riva.PCIO, 0x3d5, val); 402 } 403 404 static inline unsigned char CRTCin(struct riva_par *par, 405 unsigned char index) 406 { 407 VGA_WR08(par->riva.PCIO, 0x3d4, index); 408 return (VGA_RD08(par->riva.PCIO, 0x3d5)); 409 } 410 411 static inline void GRAout(struct riva_par *par, unsigned char index, 412 unsigned char val) 413 { 414 VGA_WR08(par->riva.PVIO, 0x3ce, index); 415 VGA_WR08(par->riva.PVIO, 0x3cf, val); 416 } 417 418 static inline unsigned char GRAin(struct riva_par *par, 419 unsigned char index) 420 { 421 VGA_WR08(par->riva.PVIO, 0x3ce, index); 422 return (VGA_RD08(par->riva.PVIO, 0x3cf)); 423 } 424 425 static inline void SEQout(struct riva_par *par, unsigned char index, 426 unsigned char val) 427 { 428 VGA_WR08(par->riva.PVIO, 0x3c4, index); 429 VGA_WR08(par->riva.PVIO, 0x3c5, val); 430 } 431 432 static inline unsigned char SEQin(struct riva_par *par, 433 unsigned char index) 434 { 435 VGA_WR08(par->riva.PVIO, 0x3c4, index); 436 return (VGA_RD08(par->riva.PVIO, 0x3c5)); 437 } 438 439 static inline void ATTRout(struct riva_par *par, unsigned char index, 440 unsigned char val) 441 { 442 VGA_WR08(par->riva.PCIO, 0x3c0, index); 443 VGA_WR08(par->riva.PCIO, 0x3c0, val); 444 } 445 446 static inline unsigned char ATTRin(struct riva_par *par, 447 unsigned char index) 448 { 449 VGA_WR08(par->riva.PCIO, 0x3c0, index); 450 return (VGA_RD08(par->riva.PCIO, 0x3c1)); 451 } 452 453 static inline void MISCout(struct riva_par *par, unsigned char val) 454 { 455 VGA_WR08(par->riva.PVIO, 0x3c2, val); 456 } 457 458 static inline unsigned char MISCin(struct riva_par *par) 459 { 460 return (VGA_RD08(par->riva.PVIO, 0x3cc)); 461 } 462 463 static inline void reverse_order(u32 *l) 464 { 465 u8 *a = (u8 *)l; 466 a[0] = bitrev8(a[0]); 467 a[1] = bitrev8(a[1]); 468 a[2] = bitrev8(a[2]); 469 a[3] = bitrev8(a[3]); 470 } 471 472 /* ------------------------------------------------------------------------- * 473 * 474 * cursor stuff 475 * 476 * ------------------------------------------------------------------------- */ 477 478 /** 479 * rivafb_load_cursor_image - load cursor image to hardware 480 * @data: address to monochrome bitmap (1 = foreground color, 0 = background) 481 * @par: pointer to private data 482 * @w: width of cursor image in pixels 483 * @h: height of cursor image in scanlines 484 * @bg: background color (ARGB1555) - alpha bit determines opacity 485 * @fg: foreground color (ARGB1555) 486 * 487 * DESCRIPTiON: 488 * Loads cursor image based on a monochrome source and mask bitmap. The 489 * image bits determines the color of the pixel, 0 for background, 1 for 490 * foreground. Only the affected region (as determined by @w and @h 491 * parameters) will be updated. 492 * 493 * CALLED FROM: 494 * rivafb_cursor() 495 */ 496 static void rivafb_load_cursor_image(struct riva_par *par, u8 *data8, 497 u16 bg, u16 fg, u32 w, u32 h) 498 { 499 int i, j, k = 0; 500 u32 b, tmp; 501 u32 *data = (u32 *)data8; 502 bg = le16_to_cpu(bg); 503 fg = le16_to_cpu(fg); 504 505 w = (w + 1) & ~1; 506 507 for (i = 0; i < h; i++) { 508 b = *data++; 509 reverse_order(&b); 510 511 for (j = 0; j < w/2; j++) { 512 tmp = 0; 513 #if defined (__BIG_ENDIAN) 514 tmp = (b & (1 << 31)) ? fg << 16 : bg << 16; 515 b <<= 1; 516 tmp |= (b & (1 << 31)) ? fg : bg; 517 b <<= 1; 518 #else 519 tmp = (b & 1) ? fg : bg; 520 b >>= 1; 521 tmp |= (b & 1) ? fg << 16 : bg << 16; 522 b >>= 1; 523 #endif 524 writel(tmp, &par->riva.CURSOR[k++]); 525 } 526 k += (MAX_CURS - w)/2; 527 } 528 } 529 530 /* ------------------------------------------------------------------------- * 531 * 532 * general utility functions 533 * 534 * ------------------------------------------------------------------------- */ 535 536 /** 537 * riva_wclut - set CLUT entry 538 * @chip: pointer to RIVA_HW_INST object 539 * @regnum: register number 540 * @red: red component 541 * @green: green component 542 * @blue: blue component 543 * 544 * DESCRIPTION: 545 * Sets color register @regnum. 546 * 547 * CALLED FROM: 548 * rivafb_setcolreg() 549 */ 550 static void riva_wclut(RIVA_HW_INST *chip, 551 unsigned char regnum, unsigned char red, 552 unsigned char green, unsigned char blue) 553 { 554 VGA_WR08(chip->PDIO, 0x3c8, regnum); 555 VGA_WR08(chip->PDIO, 0x3c9, red); 556 VGA_WR08(chip->PDIO, 0x3c9, green); 557 VGA_WR08(chip->PDIO, 0x3c9, blue); 558 } 559 560 /** 561 * riva_rclut - read fromCLUT register 562 * @chip: pointer to RIVA_HW_INST object 563 * @regnum: register number 564 * @red: red component 565 * @green: green component 566 * @blue: blue component 567 * 568 * DESCRIPTION: 569 * Reads red, green, and blue from color register @regnum. 570 * 571 * CALLED FROM: 572 * rivafb_setcolreg() 573 */ 574 static void riva_rclut(RIVA_HW_INST *chip, 575 unsigned char regnum, unsigned char *red, 576 unsigned char *green, unsigned char *blue) 577 { 578 579 VGA_WR08(chip->PDIO, 0x3c7, regnum); 580 *red = VGA_RD08(chip->PDIO, 0x3c9); 581 *green = VGA_RD08(chip->PDIO, 0x3c9); 582 *blue = VGA_RD08(chip->PDIO, 0x3c9); 583 } 584 585 /** 586 * riva_save_state - saves current chip state 587 * @par: pointer to riva_par object containing info for current riva board 588 * @regs: pointer to riva_regs object 589 * 590 * DESCRIPTION: 591 * Saves current chip state to @regs. 592 * 593 * CALLED FROM: 594 * rivafb_probe() 595 */ 596 /* from GGI */ 597 static void riva_save_state(struct riva_par *par, struct riva_regs *regs) 598 { 599 int i; 600 601 NVTRACE_ENTER(); 602 par->riva.LockUnlock(&par->riva, 0); 603 604 par->riva.UnloadStateExt(&par->riva, ®s->ext); 605 606 regs->misc_output = MISCin(par); 607 608 for (i = 0; i < NUM_CRT_REGS; i++) 609 regs->crtc[i] = CRTCin(par, i); 610 611 for (i = 0; i < NUM_ATC_REGS; i++) 612 regs->attr[i] = ATTRin(par, i); 613 614 for (i = 0; i < NUM_GRC_REGS; i++) 615 regs->gra[i] = GRAin(par, i); 616 617 for (i = 0; i < NUM_SEQ_REGS; i++) 618 regs->seq[i] = SEQin(par, i); 619 NVTRACE_LEAVE(); 620 } 621 622 /** 623 * riva_load_state - loads current chip state 624 * @par: pointer to riva_par object containing info for current riva board 625 * @regs: pointer to riva_regs object 626 * 627 * DESCRIPTION: 628 * Loads chip state from @regs. 629 * 630 * CALLED FROM: 631 * riva_load_video_mode() 632 * rivafb_probe() 633 * rivafb_remove() 634 */ 635 /* from GGI */ 636 static void riva_load_state(struct riva_par *par, struct riva_regs *regs) 637 { 638 RIVA_HW_STATE *state = ®s->ext; 639 int i; 640 641 NVTRACE_ENTER(); 642 CRTCout(par, 0x11, 0x00); 643 644 par->riva.LockUnlock(&par->riva, 0); 645 646 par->riva.LoadStateExt(&par->riva, state); 647 648 MISCout(par, regs->misc_output); 649 650 for (i = 0; i < NUM_CRT_REGS; i++) { 651 switch (i) { 652 case 0x19: 653 case 0x20 ... 0x40: 654 break; 655 default: 656 CRTCout(par, i, regs->crtc[i]); 657 } 658 } 659 660 for (i = 0; i < NUM_ATC_REGS; i++) 661 ATTRout(par, i, regs->attr[i]); 662 663 for (i = 0; i < NUM_GRC_REGS; i++) 664 GRAout(par, i, regs->gra[i]); 665 666 for (i = 0; i < NUM_SEQ_REGS; i++) 667 SEQout(par, i, regs->seq[i]); 668 NVTRACE_LEAVE(); 669 } 670 671 /** 672 * riva_load_video_mode - calculate timings 673 * @info: pointer to fb_info object containing info for current riva board 674 * 675 * DESCRIPTION: 676 * Calculate some timings and then send em off to riva_load_state(). 677 * 678 * CALLED FROM: 679 * rivafb_set_par() 680 */ 681 static int riva_load_video_mode(struct fb_info *info) 682 { 683 int bpp, width, hDisplaySize, hDisplay, hStart, 684 hEnd, hTotal, height, vDisplay, vStart, vEnd, vTotal, dotClock; 685 int hBlankStart, hBlankEnd, vBlankStart, vBlankEnd; 686 int rc; 687 struct riva_par *par = info->par; 688 struct riva_regs newmode; 689 690 NVTRACE_ENTER(); 691 /* time to calculate */ 692 rivafb_blank(FB_BLANK_NORMAL, info); 693 694 bpp = info->var.bits_per_pixel; 695 if (bpp == 16 && info->var.green.length == 5) 696 bpp = 15; 697 width = info->var.xres_virtual; 698 hDisplaySize = info->var.xres; 699 hDisplay = (hDisplaySize / 8) - 1; 700 hStart = (hDisplaySize + info->var.right_margin) / 8 - 1; 701 hEnd = (hDisplaySize + info->var.right_margin + 702 info->var.hsync_len) / 8 - 1; 703 hTotal = (hDisplaySize + info->var.right_margin + 704 info->var.hsync_len + info->var.left_margin) / 8 - 5; 705 hBlankStart = hDisplay; 706 hBlankEnd = hTotal + 4; 707 708 height = info->var.yres_virtual; 709 vDisplay = info->var.yres - 1; 710 vStart = info->var.yres + info->var.lower_margin - 1; 711 vEnd = info->var.yres + info->var.lower_margin + 712 info->var.vsync_len - 1; 713 vTotal = info->var.yres + info->var.lower_margin + 714 info->var.vsync_len + info->var.upper_margin + 2; 715 vBlankStart = vDisplay; 716 vBlankEnd = vTotal + 1; 717 dotClock = 1000000000 / info->var.pixclock; 718 719 memcpy(&newmode, ®_template, sizeof(struct riva_regs)); 720 721 if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) 722 vTotal |= 1; 723 724 if (par->FlatPanel) { 725 vStart = vTotal - 3; 726 vEnd = vTotal - 2; 727 vBlankStart = vStart; 728 hStart = hTotal - 3; 729 hEnd = hTotal - 2; 730 hBlankEnd = hTotal + 4; 731 } 732 733 newmode.crtc[0x0] = Set8Bits (hTotal); 734 newmode.crtc[0x1] = Set8Bits (hDisplay); 735 newmode.crtc[0x2] = Set8Bits (hBlankStart); 736 newmode.crtc[0x3] = SetBitField (hBlankEnd, 4: 0, 4:0) | SetBit (7); 737 newmode.crtc[0x4] = Set8Bits (hStart); 738 newmode.crtc[0x5] = SetBitField (hBlankEnd, 5: 5, 7:7) 739 | SetBitField (hEnd, 4: 0, 4:0); 740 newmode.crtc[0x6] = SetBitField (vTotal, 7: 0, 7:0); 741 newmode.crtc[0x7] = SetBitField (vTotal, 8: 8, 0:0) 742 | SetBitField (vDisplay, 8: 8, 1:1) 743 | SetBitField (vStart, 8: 8, 2:2) 744 | SetBitField (vBlankStart, 8: 8, 3:3) 745 | SetBit (4) 746 | SetBitField (vTotal, 9: 9, 5:5) 747 | SetBitField (vDisplay, 9: 9, 6:6) 748 | SetBitField (vStart, 9: 9, 7:7); 749 newmode.crtc[0x9] = SetBitField (vBlankStart, 9: 9, 5:5) 750 | SetBit (6); 751 newmode.crtc[0x10] = Set8Bits (vStart); 752 newmode.crtc[0x11] = SetBitField (vEnd, 3: 0, 3:0) 753 | SetBit (5); 754 newmode.crtc[0x12] = Set8Bits (vDisplay); 755 newmode.crtc[0x13] = (width / 8) * ((bpp + 1) / 8); 756 newmode.crtc[0x15] = Set8Bits (vBlankStart); 757 newmode.crtc[0x16] = Set8Bits (vBlankEnd); 758 759 newmode.ext.screen = SetBitField(hBlankEnd,6:6,4:4) 760 | SetBitField(vBlankStart,10:10,3:3) 761 | SetBitField(vStart,10:10,2:2) 762 | SetBitField(vDisplay,10:10,1:1) 763 | SetBitField(vTotal,10:10,0:0); 764 newmode.ext.horiz = SetBitField(hTotal,8:8,0:0) 765 | SetBitField(hDisplay,8:8,1:1) 766 | SetBitField(hBlankStart,8:8,2:2) 767 | SetBitField(hStart,8:8,3:3); 768 newmode.ext.extra = SetBitField(vTotal,11:11,0:0) 769 | SetBitField(vDisplay,11:11,2:2) 770 | SetBitField(vStart,11:11,4:4) 771 | SetBitField(vBlankStart,11:11,6:6); 772 773 if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) { 774 int tmp = (hTotal >> 1) & ~1; 775 newmode.ext.interlace = Set8Bits(tmp); 776 newmode.ext.horiz |= SetBitField(tmp, 8:8,4:4); 777 } else 778 newmode.ext.interlace = 0xff; /* interlace off */ 779 780 if (par->riva.Architecture >= NV_ARCH_10) 781 par->riva.CURSOR = (U032 __iomem *)(info->screen_base + par->riva.CursorStart); 782 783 if (info->var.sync & FB_SYNC_HOR_HIGH_ACT) 784 newmode.misc_output &= ~0x40; 785 else 786 newmode.misc_output |= 0x40; 787 if (info->var.sync & FB_SYNC_VERT_HIGH_ACT) 788 newmode.misc_output &= ~0x80; 789 else 790 newmode.misc_output |= 0x80; 791 792 rc = CalcStateExt(&par->riva, &newmode.ext, bpp, width, 793 hDisplaySize, height, dotClock); 794 if (rc) 795 goto out; 796 797 newmode.ext.scale = NV_RD32(par->riva.PRAMDAC, 0x00000848) & 798 0xfff000ff; 799 if (par->FlatPanel == 1) { 800 newmode.ext.pixel |= (1 << 7); 801 newmode.ext.scale |= (1 << 8); 802 } 803 if (par->SecondCRTC) { 804 newmode.ext.head = NV_RD32(par->riva.PCRTC0, 0x00000860) & 805 ~0x00001000; 806 newmode.ext.head2 = NV_RD32(par->riva.PCRTC0, 0x00002860) | 807 0x00001000; 808 newmode.ext.crtcOwner = 3; 809 newmode.ext.pllsel |= 0x20000800; 810 newmode.ext.vpll2 = newmode.ext.vpll; 811 } else if (par->riva.twoHeads) { 812 newmode.ext.head = NV_RD32(par->riva.PCRTC0, 0x00000860) | 813 0x00001000; 814 newmode.ext.head2 = NV_RD32(par->riva.PCRTC0, 0x00002860) & 815 ~0x00001000; 816 newmode.ext.crtcOwner = 0; 817 newmode.ext.vpll2 = NV_RD32(par->riva.PRAMDAC0, 0x00000520); 818 } 819 if (par->FlatPanel == 1) { 820 newmode.ext.pixel |= (1 << 7); 821 newmode.ext.scale |= (1 << 8); 822 } 823 newmode.ext.cursorConfig = 0x02000100; 824 par->current_state = newmode; 825 riva_load_state(par, &par->current_state); 826 par->riva.LockUnlock(&par->riva, 0); /* important for HW cursor */ 827 828 out: 829 rivafb_blank(FB_BLANK_UNBLANK, info); 830 NVTRACE_LEAVE(); 831 832 return rc; 833 } 834 835 static void riva_update_var(struct fb_var_screeninfo *var, 836 const struct fb_videomode *modedb) 837 { 838 NVTRACE_ENTER(); 839 var->xres = var->xres_virtual = modedb->xres; 840 var->yres = modedb->yres; 841 if (var->yres_virtual < var->yres) 842 var->yres_virtual = var->yres; 843 var->xoffset = var->yoffset = 0; 844 var->pixclock = modedb->pixclock; 845 var->left_margin = modedb->left_margin; 846 var->right_margin = modedb->right_margin; 847 var->upper_margin = modedb->upper_margin; 848 var->lower_margin = modedb->lower_margin; 849 var->hsync_len = modedb->hsync_len; 850 var->vsync_len = modedb->vsync_len; 851 var->sync = modedb->sync; 852 var->vmode = modedb->vmode; 853 NVTRACE_LEAVE(); 854 } 855 856 /** 857 * rivafb_do_maximize - 858 * @info: pointer to fb_info object containing info for current riva board 859 * @var: 860 * @nom: 861 * @den: 862 * 863 * DESCRIPTION: 864 * . 865 * 866 * RETURNS: 867 * -EINVAL on failure, 0 on success 868 * 869 * 870 * CALLED FROM: 871 * rivafb_check_var() 872 */ 873 static int rivafb_do_maximize(struct fb_info *info, 874 struct fb_var_screeninfo *var, 875 int nom, int den) 876 { 877 static struct { 878 int xres, yres; 879 } modes[] = { 880 {1600, 1280}, 881 {1280, 1024}, 882 {1024, 768}, 883 {800, 600}, 884 {640, 480}, 885 {-1, -1} 886 }; 887 int i; 888 889 NVTRACE_ENTER(); 890 /* use highest possible virtual resolution */ 891 if (var->xres_virtual == -1 && var->yres_virtual == -1) { 892 printk(KERN_WARNING PFX 893 "using maximum available virtual resolution\n"); 894 for (i = 0; modes[i].xres != -1; i++) { 895 if (modes[i].xres * nom / den * modes[i].yres < 896 info->fix.smem_len) 897 break; 898 } 899 if (modes[i].xres == -1) { 900 printk(KERN_ERR PFX 901 "could not find a virtual resolution that fits into video memory!!\n"); 902 NVTRACE("EXIT - EINVAL error\n"); 903 return -EINVAL; 904 } 905 var->xres_virtual = modes[i].xres; 906 var->yres_virtual = modes[i].yres; 907 908 printk(KERN_INFO PFX 909 "virtual resolution set to maximum of %dx%d\n", 910 var->xres_virtual, var->yres_virtual); 911 } else if (var->xres_virtual == -1) { 912 var->xres_virtual = (info->fix.smem_len * den / 913 (nom * var->yres_virtual)) & ~15; 914 printk(KERN_WARNING PFX 915 "setting virtual X resolution to %d\n", var->xres_virtual); 916 } else if (var->yres_virtual == -1) { 917 var->xres_virtual = (var->xres_virtual + 15) & ~15; 918 var->yres_virtual = info->fix.smem_len * den / 919 (nom * var->xres_virtual); 920 printk(KERN_WARNING PFX 921 "setting virtual Y resolution to %d\n", var->yres_virtual); 922 } else { 923 var->xres_virtual = (var->xres_virtual + 15) & ~15; 924 if (var->xres_virtual * nom / den * var->yres_virtual > info->fix.smem_len) { 925 printk(KERN_ERR PFX 926 "mode %dx%dx%d rejected...resolution too high to fit into video memory!\n", 927 var->xres, var->yres, var->bits_per_pixel); 928 NVTRACE("EXIT - EINVAL error\n"); 929 return -EINVAL; 930 } 931 } 932 933 if (var->xres_virtual * nom / den >= 8192) { 934 printk(KERN_WARNING PFX 935 "virtual X resolution (%d) is too high, lowering to %d\n", 936 var->xres_virtual, 8192 * den / nom - 16); 937 var->xres_virtual = 8192 * den / nom - 16; 938 } 939 940 if (var->xres_virtual < var->xres) { 941 printk(KERN_ERR PFX 942 "virtual X resolution (%d) is smaller than real\n", var->xres_virtual); 943 return -EINVAL; 944 } 945 946 if (var->yres_virtual < var->yres) { 947 printk(KERN_ERR PFX 948 "virtual Y resolution (%d) is smaller than real\n", var->yres_virtual); 949 return -EINVAL; 950 } 951 if (var->yres_virtual > 0x7fff/nom) 952 var->yres_virtual = 0x7fff/nom; 953 if (var->xres_virtual > 0x7fff/nom) 954 var->xres_virtual = 0x7fff/nom; 955 NVTRACE_LEAVE(); 956 return 0; 957 } 958 959 static void 960 riva_set_pattern(struct riva_par *par, int clr0, int clr1, int pat0, int pat1) 961 { 962 RIVA_FIFO_FREE(par->riva, Patt, 4); 963 NV_WR32(&par->riva.Patt->Color0, 0, clr0); 964 NV_WR32(&par->riva.Patt->Color1, 0, clr1); 965 NV_WR32(par->riva.Patt->Monochrome, 0, pat0); 966 NV_WR32(par->riva.Patt->Monochrome, 4, pat1); 967 } 968 969 /* acceleration routines */ 970 static inline void wait_for_idle(struct riva_par *par) 971 { 972 while (par->riva.Busy(&par->riva)); 973 } 974 975 /* 976 * Set ROP. Translate X rop into ROP3. Internal routine. 977 */ 978 static void 979 riva_set_rop_solid(struct riva_par *par, int rop) 980 { 981 riva_set_pattern(par, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF); 982 RIVA_FIFO_FREE(par->riva, Rop, 1); 983 NV_WR32(&par->riva.Rop->Rop3, 0, rop); 984 985 } 986 987 static void riva_setup_accel(struct fb_info *info) 988 { 989 struct riva_par *par = info->par; 990 991 RIVA_FIFO_FREE(par->riva, Clip, 2); 992 NV_WR32(&par->riva.Clip->TopLeft, 0, 0x0); 993 NV_WR32(&par->riva.Clip->WidthHeight, 0, 994 (info->var.xres_virtual & 0xffff) | 995 (info->var.yres_virtual << 16)); 996 riva_set_rop_solid(par, 0xcc); 997 wait_for_idle(par); 998 } 999 1000 /** 1001 * riva_get_cmap_len - query current color map length 1002 * @var: standard kernel fb changeable data 1003 * 1004 * DESCRIPTION: 1005 * Get current color map length. 1006 * 1007 * RETURNS: 1008 * Length of color map 1009 * 1010 * CALLED FROM: 1011 * rivafb_setcolreg() 1012 */ 1013 static int riva_get_cmap_len(const struct fb_var_screeninfo *var) 1014 { 1015 int rc = 256; /* reasonable default */ 1016 1017 switch (var->green.length) { 1018 case 8: 1019 rc = 256; /* 256 entries (2^8), 8 bpp and RGB8888 */ 1020 break; 1021 case 5: 1022 rc = 32; /* 32 entries (2^5), 16 bpp, RGB555 */ 1023 break; 1024 case 6: 1025 rc = 64; /* 64 entries (2^6), 16 bpp, RGB565 */ 1026 break; 1027 default: 1028 /* should not occur */ 1029 break; 1030 } 1031 return rc; 1032 } 1033 1034 /* ------------------------------------------------------------------------- * 1035 * 1036 * framebuffer operations 1037 * 1038 * ------------------------------------------------------------------------- */ 1039 1040 static int rivafb_open(struct fb_info *info, int user) 1041 { 1042 struct riva_par *par = info->par; 1043 1044 NVTRACE_ENTER(); 1045 mutex_lock(&par->open_lock); 1046 if (!par->ref_count) { 1047 #ifdef CONFIG_X86 1048 memset(&par->state, 0, sizeof(struct vgastate)); 1049 par->state.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS; 1050 /* save the DAC for Riva128 */ 1051 if (par->riva.Architecture == NV_ARCH_03) 1052 par->state.flags |= VGA_SAVE_CMAP; 1053 save_vga(&par->state); 1054 #endif 1055 /* vgaHWunlock() + riva unlock (0x7F) */ 1056 CRTCout(par, 0x11, 0xFF); 1057 par->riva.LockUnlock(&par->riva, 0); 1058 1059 riva_save_state(par, &par->initial_state); 1060 } 1061 par->ref_count++; 1062 mutex_unlock(&par->open_lock); 1063 NVTRACE_LEAVE(); 1064 return 0; 1065 } 1066 1067 static int rivafb_release(struct fb_info *info, int user) 1068 { 1069 struct riva_par *par = info->par; 1070 1071 NVTRACE_ENTER(); 1072 mutex_lock(&par->open_lock); 1073 if (!par->ref_count) { 1074 mutex_unlock(&par->open_lock); 1075 return -EINVAL; 1076 } 1077 if (par->ref_count == 1) { 1078 par->riva.LockUnlock(&par->riva, 0); 1079 par->riva.LoadStateExt(&par->riva, &par->initial_state.ext); 1080 riva_load_state(par, &par->initial_state); 1081 #ifdef CONFIG_X86 1082 restore_vga(&par->state); 1083 #endif 1084 par->riva.LockUnlock(&par->riva, 1); 1085 } 1086 par->ref_count--; 1087 mutex_unlock(&par->open_lock); 1088 NVTRACE_LEAVE(); 1089 return 0; 1090 } 1091 1092 static int rivafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) 1093 { 1094 const struct fb_videomode *mode; 1095 struct riva_par *par = info->par; 1096 int nom, den; /* translating from pixels->bytes */ 1097 int mode_valid = 0; 1098 1099 NVTRACE_ENTER(); 1100 switch (var->bits_per_pixel) { 1101 case 1 ... 8: 1102 var->red.offset = var->green.offset = var->blue.offset = 0; 1103 var->red.length = var->green.length = var->blue.length = 8; 1104 var->bits_per_pixel = 8; 1105 nom = den = 1; 1106 break; 1107 case 9 ... 15: 1108 var->green.length = 5; 1109 /* fall through */ 1110 case 16: 1111 var->bits_per_pixel = 16; 1112 /* The Riva128 supports RGB555 only */ 1113 if (par->riva.Architecture == NV_ARCH_03) 1114 var->green.length = 5; 1115 if (var->green.length == 5) { 1116 /* 0rrrrrgg gggbbbbb */ 1117 var->red.offset = 10; 1118 var->green.offset = 5; 1119 var->blue.offset = 0; 1120 var->red.length = 5; 1121 var->green.length = 5; 1122 var->blue.length = 5; 1123 } else { 1124 /* rrrrrggg gggbbbbb */ 1125 var->red.offset = 11; 1126 var->green.offset = 5; 1127 var->blue.offset = 0; 1128 var->red.length = 5; 1129 var->green.length = 6; 1130 var->blue.length = 5; 1131 } 1132 nom = 2; 1133 den = 1; 1134 break; 1135 case 17 ... 32: 1136 var->red.length = var->green.length = var->blue.length = 8; 1137 var->bits_per_pixel = 32; 1138 var->red.offset = 16; 1139 var->green.offset = 8; 1140 var->blue.offset = 0; 1141 nom = 4; 1142 den = 1; 1143 break; 1144 default: 1145 printk(KERN_ERR PFX 1146 "mode %dx%dx%d rejected...color depth not supported.\n", 1147 var->xres, var->yres, var->bits_per_pixel); 1148 NVTRACE("EXIT, returning -EINVAL\n"); 1149 return -EINVAL; 1150 } 1151 1152 if (!strictmode) { 1153 if (!info->monspecs.vfmax || !info->monspecs.hfmax || 1154 !info->monspecs.dclkmax || !fb_validate_mode(var, info)) 1155 mode_valid = 1; 1156 } 1157 1158 /* calculate modeline if supported by monitor */ 1159 if (!mode_valid && info->monspecs.gtf) { 1160 if (!fb_get_mode(FB_MAXTIMINGS, 0, var, info)) 1161 mode_valid = 1; 1162 } 1163 1164 if (!mode_valid) { 1165 mode = fb_find_best_mode(var, &info->modelist); 1166 if (mode) { 1167 riva_update_var(var, mode); 1168 mode_valid = 1; 1169 } 1170 } 1171 1172 if (!mode_valid && info->monspecs.modedb_len) 1173 return -EINVAL; 1174 1175 if (var->xres_virtual < var->xres) 1176 var->xres_virtual = var->xres; 1177 if (var->yres_virtual <= var->yres) 1178 var->yres_virtual = -1; 1179 if (rivafb_do_maximize(info, var, nom, den) < 0) 1180 return -EINVAL; 1181 1182 /* truncate xoffset and yoffset to maximum if too high */ 1183 if (var->xoffset > var->xres_virtual - var->xres) 1184 var->xoffset = var->xres_virtual - var->xres - 1; 1185 1186 if (var->yoffset > var->yres_virtual - var->yres) 1187 var->yoffset = var->yres_virtual - var->yres - 1; 1188 1189 var->red.msb_right = 1190 var->green.msb_right = 1191 var->blue.msb_right = 1192 var->transp.offset = var->transp.length = var->transp.msb_right = 0; 1193 NVTRACE_LEAVE(); 1194 return 0; 1195 } 1196 1197 static int rivafb_set_par(struct fb_info *info) 1198 { 1199 struct riva_par *par = info->par; 1200 int rc = 0; 1201 1202 NVTRACE_ENTER(); 1203 /* vgaHWunlock() + riva unlock (0x7F) */ 1204 CRTCout(par, 0x11, 0xFF); 1205 par->riva.LockUnlock(&par->riva, 0); 1206 rc = riva_load_video_mode(info); 1207 if (rc) 1208 goto out; 1209 if(!(info->flags & FBINFO_HWACCEL_DISABLED)) 1210 riva_setup_accel(info); 1211 1212 par->cursor_reset = 1; 1213 info->fix.line_length = (info->var.xres_virtual * (info->var.bits_per_pixel >> 3)); 1214 info->fix.visual = (info->var.bits_per_pixel == 8) ? 1215 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR; 1216 1217 if (info->flags & FBINFO_HWACCEL_DISABLED) 1218 info->pixmap.scan_align = 1; 1219 else 1220 info->pixmap.scan_align = 4; 1221 1222 out: 1223 NVTRACE_LEAVE(); 1224 return rc; 1225 } 1226 1227 /** 1228 * rivafb_pan_display 1229 * @var: standard kernel fb changeable data 1230 * @con: TODO 1231 * @info: pointer to fb_info object containing info for current riva board 1232 * 1233 * DESCRIPTION: 1234 * Pan (or wrap, depending on the `vmode' field) the display using the 1235 * `xoffset' and `yoffset' fields of the `var' structure. 1236 * If the values don't fit, return -EINVAL. 1237 * 1238 * This call looks only at xoffset, yoffset and the FB_VMODE_YWRAP flag 1239 */ 1240 static int rivafb_pan_display(struct fb_var_screeninfo *var, 1241 struct fb_info *info) 1242 { 1243 struct riva_par *par = info->par; 1244 unsigned int base; 1245 1246 NVTRACE_ENTER(); 1247 base = var->yoffset * info->fix.line_length + var->xoffset; 1248 par->riva.SetStartAddress(&par->riva, base); 1249 NVTRACE_LEAVE(); 1250 return 0; 1251 } 1252 1253 static int rivafb_blank(int blank, struct fb_info *info) 1254 { 1255 struct riva_par *par= info->par; 1256 unsigned char tmp, vesa; 1257 1258 tmp = SEQin(par, 0x01) & ~0x20; /* screen on/off */ 1259 vesa = CRTCin(par, 0x1a) & ~0xc0; /* sync on/off */ 1260 1261 NVTRACE_ENTER(); 1262 1263 if (blank) 1264 tmp |= 0x20; 1265 1266 switch (blank) { 1267 case FB_BLANK_UNBLANK: 1268 case FB_BLANK_NORMAL: 1269 break; 1270 case FB_BLANK_VSYNC_SUSPEND: 1271 vesa |= 0x80; 1272 break; 1273 case FB_BLANK_HSYNC_SUSPEND: 1274 vesa |= 0x40; 1275 break; 1276 case FB_BLANK_POWERDOWN: 1277 vesa |= 0xc0; 1278 break; 1279 } 1280 1281 SEQout(par, 0x01, tmp); 1282 CRTCout(par, 0x1a, vesa); 1283 1284 NVTRACE_LEAVE(); 1285 1286 return 0; 1287 } 1288 1289 /** 1290 * rivafb_setcolreg 1291 * @regno: register index 1292 * @red: red component 1293 * @green: green component 1294 * @blue: blue component 1295 * @transp: transparency 1296 * @info: pointer to fb_info object containing info for current riva board 1297 * 1298 * DESCRIPTION: 1299 * Set a single color register. The values supplied have a 16 bit 1300 * magnitude. 1301 * 1302 * RETURNS: 1303 * Return != 0 for invalid regno. 1304 * 1305 * CALLED FROM: 1306 * fbcmap.c:fb_set_cmap() 1307 */ 1308 static int rivafb_setcolreg(unsigned regno, unsigned red, unsigned green, 1309 unsigned blue, unsigned transp, 1310 struct fb_info *info) 1311 { 1312 struct riva_par *par = info->par; 1313 RIVA_HW_INST *chip = &par->riva; 1314 int i; 1315 1316 if (regno >= riva_get_cmap_len(&info->var)) 1317 return -EINVAL; 1318 1319 if (info->var.grayscale) { 1320 /* gray = 0.30*R + 0.59*G + 0.11*B */ 1321 red = green = blue = 1322 (red * 77 + green * 151 + blue * 28) >> 8; 1323 } 1324 1325 if (regno < 16 && info->fix.visual == FB_VISUAL_DIRECTCOLOR) { 1326 ((u32 *) info->pseudo_palette)[regno] = 1327 (regno << info->var.red.offset) | 1328 (regno << info->var.green.offset) | 1329 (regno << info->var.blue.offset); 1330 /* 1331 * The Riva128 2D engine requires color information in 1332 * TrueColor format even if framebuffer is in DirectColor 1333 */ 1334 if (par->riva.Architecture == NV_ARCH_03) { 1335 switch (info->var.bits_per_pixel) { 1336 case 16: 1337 par->palette[regno] = ((red & 0xf800) >> 1) | 1338 ((green & 0xf800) >> 6) | 1339 ((blue & 0xf800) >> 11); 1340 break; 1341 case 32: 1342 par->palette[regno] = ((red & 0xff00) << 8) | 1343 ((green & 0xff00)) | 1344 ((blue & 0xff00) >> 8); 1345 break; 1346 } 1347 } 1348 } 1349 1350 switch (info->var.bits_per_pixel) { 1351 case 8: 1352 /* "transparent" stuff is completely ignored. */ 1353 riva_wclut(chip, regno, red >> 8, green >> 8, blue >> 8); 1354 break; 1355 case 16: 1356 if (info->var.green.length == 5) { 1357 for (i = 0; i < 8; i++) { 1358 riva_wclut(chip, regno*8+i, red >> 8, 1359 green >> 8, blue >> 8); 1360 } 1361 } else { 1362 u8 r, g, b; 1363 1364 if (regno < 32) { 1365 for (i = 0; i < 8; i++) { 1366 riva_wclut(chip, regno*8+i, 1367 red >> 8, green >> 8, 1368 blue >> 8); 1369 } 1370 } 1371 riva_rclut(chip, regno*4, &r, &g, &b); 1372 for (i = 0; i < 4; i++) 1373 riva_wclut(chip, regno*4+i, r, 1374 green >> 8, b); 1375 } 1376 break; 1377 case 32: 1378 riva_wclut(chip, regno, red >> 8, green >> 8, blue >> 8); 1379 break; 1380 default: 1381 /* do nothing */ 1382 break; 1383 } 1384 return 0; 1385 } 1386 1387 /** 1388 * rivafb_fillrect - hardware accelerated color fill function 1389 * @info: pointer to fb_info structure 1390 * @rect: pointer to fb_fillrect structure 1391 * 1392 * DESCRIPTION: 1393 * This function fills up a region of framebuffer memory with a solid 1394 * color with a choice of two different ROP's, copy or invert. 1395 * 1396 * CALLED FROM: 1397 * framebuffer hook 1398 */ 1399 static void rivafb_fillrect(struct fb_info *info, const struct fb_fillrect *rect) 1400 { 1401 struct riva_par *par = info->par; 1402 u_int color, rop = 0; 1403 1404 if ((info->flags & FBINFO_HWACCEL_DISABLED)) { 1405 cfb_fillrect(info, rect); 1406 return; 1407 } 1408 1409 if (info->var.bits_per_pixel == 8) 1410 color = rect->color; 1411 else { 1412 if (par->riva.Architecture != NV_ARCH_03) 1413 color = ((u32 *)info->pseudo_palette)[rect->color]; 1414 else 1415 color = par->palette[rect->color]; 1416 } 1417 1418 switch (rect->rop) { 1419 case ROP_XOR: 1420 rop = 0x66; 1421 break; 1422 case ROP_COPY: 1423 default: 1424 rop = 0xCC; 1425 break; 1426 } 1427 1428 riva_set_rop_solid(par, rop); 1429 1430 RIVA_FIFO_FREE(par->riva, Bitmap, 1); 1431 NV_WR32(&par->riva.Bitmap->Color1A, 0, color); 1432 1433 RIVA_FIFO_FREE(par->riva, Bitmap, 2); 1434 NV_WR32(&par->riva.Bitmap->UnclippedRectangle[0].TopLeft, 0, 1435 (rect->dx << 16) | rect->dy); 1436 mb(); 1437 NV_WR32(&par->riva.Bitmap->UnclippedRectangle[0].WidthHeight, 0, 1438 (rect->width << 16) | rect->height); 1439 mb(); 1440 riva_set_rop_solid(par, 0xcc); 1441 1442 } 1443 1444 /** 1445 * rivafb_copyarea - hardware accelerated blit function 1446 * @info: pointer to fb_info structure 1447 * @region: pointer to fb_copyarea structure 1448 * 1449 * DESCRIPTION: 1450 * This copies an area of pixels from one location to another 1451 * 1452 * CALLED FROM: 1453 * framebuffer hook 1454 */ 1455 static void rivafb_copyarea(struct fb_info *info, const struct fb_copyarea *region) 1456 { 1457 struct riva_par *par = info->par; 1458 1459 if ((info->flags & FBINFO_HWACCEL_DISABLED)) { 1460 cfb_copyarea(info, region); 1461 return; 1462 } 1463 1464 RIVA_FIFO_FREE(par->riva, Blt, 3); 1465 NV_WR32(&par->riva.Blt->TopLeftSrc, 0, 1466 (region->sy << 16) | region->sx); 1467 NV_WR32(&par->riva.Blt->TopLeftDst, 0, 1468 (region->dy << 16) | region->dx); 1469 mb(); 1470 NV_WR32(&par->riva.Blt->WidthHeight, 0, 1471 (region->height << 16) | region->width); 1472 mb(); 1473 } 1474 1475 static inline void convert_bgcolor_16(u32 *col) 1476 { 1477 *col = ((*col & 0x0000F800) << 8) 1478 | ((*col & 0x00007E0) << 5) 1479 | ((*col & 0x0000001F) << 3) 1480 | 0xFF000000; 1481 mb(); 1482 } 1483 1484 /** 1485 * rivafb_imageblit: hardware accelerated color expand function 1486 * @info: pointer to fb_info structure 1487 * @image: pointer to fb_image structure 1488 * 1489 * DESCRIPTION: 1490 * If the source is a monochrome bitmap, the function fills up a a region 1491 * of framebuffer memory with pixels whose color is determined by the bit 1492 * setting of the bitmap, 1 - foreground, 0 - background. 1493 * 1494 * If the source is not a monochrome bitmap, color expansion is not done. 1495 * In this case, it is channeled to a software function. 1496 * 1497 * CALLED FROM: 1498 * framebuffer hook 1499 */ 1500 static void rivafb_imageblit(struct fb_info *info, 1501 const struct fb_image *image) 1502 { 1503 struct riva_par *par = info->par; 1504 u32 fgx = 0, bgx = 0, width, tmp; 1505 u8 *cdat = (u8 *) image->data; 1506 volatile u32 __iomem *d; 1507 int i, size; 1508 1509 if ((info->flags & FBINFO_HWACCEL_DISABLED) || image->depth != 1) { 1510 cfb_imageblit(info, image); 1511 return; 1512 } 1513 1514 switch (info->var.bits_per_pixel) { 1515 case 8: 1516 fgx = image->fg_color; 1517 bgx = image->bg_color; 1518 break; 1519 case 16: 1520 case 32: 1521 if (par->riva.Architecture != NV_ARCH_03) { 1522 fgx = ((u32 *)info->pseudo_palette)[image->fg_color]; 1523 bgx = ((u32 *)info->pseudo_palette)[image->bg_color]; 1524 } else { 1525 fgx = par->palette[image->fg_color]; 1526 bgx = par->palette[image->bg_color]; 1527 } 1528 if (info->var.green.length == 6) 1529 convert_bgcolor_16(&bgx); 1530 break; 1531 } 1532 1533 RIVA_FIFO_FREE(par->riva, Bitmap, 7); 1534 NV_WR32(&par->riva.Bitmap->ClipE.TopLeft, 0, 1535 (image->dy << 16) | (image->dx & 0xFFFF)); 1536 NV_WR32(&par->riva.Bitmap->ClipE.BottomRight, 0, 1537 (((image->dy + image->height) << 16) | 1538 ((image->dx + image->width) & 0xffff))); 1539 NV_WR32(&par->riva.Bitmap->Color0E, 0, bgx); 1540 NV_WR32(&par->riva.Bitmap->Color1E, 0, fgx); 1541 NV_WR32(&par->riva.Bitmap->WidthHeightInE, 0, 1542 (image->height << 16) | ((image->width + 31) & ~31)); 1543 NV_WR32(&par->riva.Bitmap->WidthHeightOutE, 0, 1544 (image->height << 16) | ((image->width + 31) & ~31)); 1545 NV_WR32(&par->riva.Bitmap->PointE, 0, 1546 (image->dy << 16) | (image->dx & 0xFFFF)); 1547 1548 d = &par->riva.Bitmap->MonochromeData01E; 1549 1550 width = (image->width + 31)/32; 1551 size = width * image->height; 1552 while (size >= 16) { 1553 RIVA_FIFO_FREE(par->riva, Bitmap, 16); 1554 for (i = 0; i < 16; i++) { 1555 tmp = *((u32 *)cdat); 1556 cdat = (u8 *)((u32 *)cdat + 1); 1557 reverse_order(&tmp); 1558 NV_WR32(d, i*4, tmp); 1559 } 1560 size -= 16; 1561 } 1562 if (size) { 1563 RIVA_FIFO_FREE(par->riva, Bitmap, size); 1564 for (i = 0; i < size; i++) { 1565 tmp = *((u32 *) cdat); 1566 cdat = (u8 *)((u32 *)cdat + 1); 1567 reverse_order(&tmp); 1568 NV_WR32(d, i*4, tmp); 1569 } 1570 } 1571 } 1572 1573 /** 1574 * rivafb_cursor - hardware cursor function 1575 * @info: pointer to info structure 1576 * @cursor: pointer to fbcursor structure 1577 * 1578 * DESCRIPTION: 1579 * A cursor function that supports displaying a cursor image via hardware. 1580 * Within the kernel, copy and invert rops are supported. If exported 1581 * to user space, only the copy rop will be supported. 1582 * 1583 * CALLED FROM 1584 * framebuffer hook 1585 */ 1586 static int rivafb_cursor(struct fb_info *info, struct fb_cursor *cursor) 1587 { 1588 struct riva_par *par = info->par; 1589 u8 data[MAX_CURS * MAX_CURS/8]; 1590 int i, set = cursor->set; 1591 u16 fg, bg; 1592 1593 if (cursor->image.width > MAX_CURS || cursor->image.height > MAX_CURS) 1594 return -ENXIO; 1595 1596 par->riva.ShowHideCursor(&par->riva, 0); 1597 1598 if (par->cursor_reset) { 1599 set = FB_CUR_SETALL; 1600 par->cursor_reset = 0; 1601 } 1602 1603 if (set & FB_CUR_SETSIZE) 1604 memset_io(par->riva.CURSOR, 0, MAX_CURS * MAX_CURS * 2); 1605 1606 if (set & FB_CUR_SETPOS) { 1607 u32 xx, yy, temp; 1608 1609 yy = cursor->image.dy - info->var.yoffset; 1610 xx = cursor->image.dx - info->var.xoffset; 1611 temp = xx & 0xFFFF; 1612 temp |= yy << 16; 1613 1614 NV_WR32(par->riva.PRAMDAC, 0x0000300, temp); 1615 } 1616 1617 1618 if (set & (FB_CUR_SETSHAPE | FB_CUR_SETCMAP | FB_CUR_SETIMAGE)) { 1619 u32 bg_idx = cursor->image.bg_color; 1620 u32 fg_idx = cursor->image.fg_color; 1621 u32 s_pitch = (cursor->image.width+7) >> 3; 1622 u32 d_pitch = MAX_CURS/8; 1623 u8 *dat = (u8 *) cursor->image.data; 1624 u8 *msk = (u8 *) cursor->mask; 1625 u8 *src; 1626 1627 src = kmalloc(s_pitch * cursor->image.height, GFP_ATOMIC); 1628 1629 if (src) { 1630 switch (cursor->rop) { 1631 case ROP_XOR: 1632 for (i = 0; i < s_pitch * cursor->image.height; i++) 1633 src[i] = dat[i] ^ msk[i]; 1634 break; 1635 case ROP_COPY: 1636 default: 1637 for (i = 0; i < s_pitch * cursor->image.height; i++) 1638 src[i] = dat[i] & msk[i]; 1639 break; 1640 } 1641 1642 fb_pad_aligned_buffer(data, d_pitch, src, s_pitch, 1643 cursor->image.height); 1644 1645 bg = ((info->cmap.red[bg_idx] & 0xf8) << 7) | 1646 ((info->cmap.green[bg_idx] & 0xf8) << 2) | 1647 ((info->cmap.blue[bg_idx] & 0xf8) >> 3) | 1648 1 << 15; 1649 1650 fg = ((info->cmap.red[fg_idx] & 0xf8) << 7) | 1651 ((info->cmap.green[fg_idx] & 0xf8) << 2) | 1652 ((info->cmap.blue[fg_idx] & 0xf8) >> 3) | 1653 1 << 15; 1654 1655 par->riva.LockUnlock(&par->riva, 0); 1656 1657 rivafb_load_cursor_image(par, data, bg, fg, 1658 cursor->image.width, 1659 cursor->image.height); 1660 kfree(src); 1661 } 1662 } 1663 1664 if (cursor->enable) 1665 par->riva.ShowHideCursor(&par->riva, 1); 1666 1667 return 0; 1668 } 1669 1670 static int rivafb_sync(struct fb_info *info) 1671 { 1672 struct riva_par *par = info->par; 1673 1674 wait_for_idle(par); 1675 return 0; 1676 } 1677 1678 /* ------------------------------------------------------------------------- * 1679 * 1680 * initialization helper functions 1681 * 1682 * ------------------------------------------------------------------------- */ 1683 1684 /* kernel interface */ 1685 static struct fb_ops riva_fb_ops = { 1686 .owner = THIS_MODULE, 1687 .fb_open = rivafb_open, 1688 .fb_release = rivafb_release, 1689 .fb_check_var = rivafb_check_var, 1690 .fb_set_par = rivafb_set_par, 1691 .fb_setcolreg = rivafb_setcolreg, 1692 .fb_pan_display = rivafb_pan_display, 1693 .fb_blank = rivafb_blank, 1694 .fb_fillrect = rivafb_fillrect, 1695 .fb_copyarea = rivafb_copyarea, 1696 .fb_imageblit = rivafb_imageblit, 1697 .fb_cursor = rivafb_cursor, 1698 .fb_sync = rivafb_sync, 1699 }; 1700 1701 static int riva_set_fbinfo(struct fb_info *info) 1702 { 1703 unsigned int cmap_len; 1704 struct riva_par *par = info->par; 1705 1706 NVTRACE_ENTER(); 1707 info->flags = FBINFO_DEFAULT 1708 | FBINFO_HWACCEL_XPAN 1709 | FBINFO_HWACCEL_YPAN 1710 | FBINFO_HWACCEL_COPYAREA 1711 | FBINFO_HWACCEL_FILLRECT 1712 | FBINFO_HWACCEL_IMAGEBLIT; 1713 1714 /* Accel seems to not work properly on NV30 yet...*/ 1715 if ((par->riva.Architecture == NV_ARCH_30) || noaccel) { 1716 printk(KERN_DEBUG PFX "disabling acceleration\n"); 1717 info->flags |= FBINFO_HWACCEL_DISABLED; 1718 } 1719 1720 info->var = rivafb_default_var; 1721 info->fix.visual = (info->var.bits_per_pixel == 8) ? 1722 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR; 1723 1724 info->pseudo_palette = par->pseudo_palette; 1725 1726 cmap_len = riva_get_cmap_len(&info->var); 1727 fb_alloc_cmap(&info->cmap, cmap_len, 0); 1728 1729 info->pixmap.size = 8 * 1024; 1730 info->pixmap.buf_align = 4; 1731 info->pixmap.access_align = 32; 1732 info->pixmap.flags = FB_PIXMAP_SYSTEM; 1733 info->var.yres_virtual = -1; 1734 NVTRACE_LEAVE(); 1735 return (rivafb_check_var(&info->var, info)); 1736 } 1737 1738 #ifdef CONFIG_PPC_OF 1739 static int riva_get_EDID_OF(struct fb_info *info, struct pci_dev *pd) 1740 { 1741 struct riva_par *par = info->par; 1742 struct device_node *dp; 1743 const unsigned char *pedid = NULL; 1744 const unsigned char *disptype = NULL; 1745 static char *propnames[] = { 1746 "DFP,EDID", "LCD,EDID", "EDID", "EDID1", "EDID,B", "EDID,A", NULL }; 1747 int i; 1748 1749 NVTRACE_ENTER(); 1750 dp = pci_device_to_OF_node(pd); 1751 for (; dp != NULL; dp = dp->child) { 1752 disptype = of_get_property(dp, "display-type", NULL); 1753 if (disptype == NULL) 1754 continue; 1755 if (strncmp(disptype, "LCD", 3) != 0) 1756 continue; 1757 for (i = 0; propnames[i] != NULL; ++i) { 1758 pedid = of_get_property(dp, propnames[i], NULL); 1759 if (pedid != NULL) { 1760 par->EDID = (unsigned char *)pedid; 1761 NVTRACE("LCD found.\n"); 1762 return 1; 1763 } 1764 } 1765 } 1766 NVTRACE_LEAVE(); 1767 return 0; 1768 } 1769 #endif /* CONFIG_PPC_OF */ 1770 1771 #if defined(CONFIG_FB_RIVA_I2C) && !defined(CONFIG_PPC_OF) 1772 static int riva_get_EDID_i2c(struct fb_info *info) 1773 { 1774 struct riva_par *par = info->par; 1775 struct fb_var_screeninfo var; 1776 int i; 1777 1778 NVTRACE_ENTER(); 1779 riva_create_i2c_busses(par); 1780 for (i = 0; i < 3; i++) { 1781 if (!par->chan[i].par) 1782 continue; 1783 riva_probe_i2c_connector(par, i, &par->EDID); 1784 if (par->EDID && !fb_parse_edid(par->EDID, &var)) { 1785 printk(PFX "Found EDID Block from BUS %i\n", i); 1786 break; 1787 } 1788 } 1789 1790 NVTRACE_LEAVE(); 1791 return (par->EDID) ? 1 : 0; 1792 } 1793 #endif /* CONFIG_FB_RIVA_I2C */ 1794 1795 static void riva_update_default_var(struct fb_var_screeninfo *var, 1796 struct fb_info *info) 1797 { 1798 struct fb_monspecs *specs = &info->monspecs; 1799 struct fb_videomode modedb; 1800 1801 NVTRACE_ENTER(); 1802 /* respect mode options */ 1803 if (mode_option) { 1804 fb_find_mode(var, info, mode_option, 1805 specs->modedb, specs->modedb_len, 1806 NULL, 8); 1807 } else if (specs->modedb != NULL) { 1808 /* get first mode in database as fallback */ 1809 modedb = specs->modedb[0]; 1810 /* get preferred timing */ 1811 if (info->monspecs.misc & FB_MISC_1ST_DETAIL) { 1812 int i; 1813 1814 for (i = 0; i < specs->modedb_len; i++) { 1815 if (specs->modedb[i].flag & FB_MODE_IS_FIRST) { 1816 modedb = specs->modedb[i]; 1817 break; 1818 } 1819 } 1820 } 1821 var->bits_per_pixel = 8; 1822 riva_update_var(var, &modedb); 1823 } 1824 NVTRACE_LEAVE(); 1825 } 1826 1827 1828 static void riva_get_EDID(struct fb_info *info, struct pci_dev *pdev) 1829 { 1830 NVTRACE_ENTER(); 1831 #ifdef CONFIG_PPC_OF 1832 if (!riva_get_EDID_OF(info, pdev)) 1833 printk(PFX "could not retrieve EDID from OF\n"); 1834 #elif defined(CONFIG_FB_RIVA_I2C) 1835 if (!riva_get_EDID_i2c(info)) 1836 printk(PFX "could not retrieve EDID from DDC/I2C\n"); 1837 #endif 1838 NVTRACE_LEAVE(); 1839 } 1840 1841 1842 static void riva_get_edidinfo(struct fb_info *info) 1843 { 1844 struct fb_var_screeninfo *var = &rivafb_default_var; 1845 struct riva_par *par = info->par; 1846 1847 fb_edid_to_monspecs(par->EDID, &info->monspecs); 1848 fb_videomode_to_modelist(info->monspecs.modedb, info->monspecs.modedb_len, 1849 &info->modelist); 1850 riva_update_default_var(var, info); 1851 1852 /* if user specified flatpanel, we respect that */ 1853 if (info->monspecs.input & FB_DISP_DDI) 1854 par->FlatPanel = 1; 1855 } 1856 1857 /* ------------------------------------------------------------------------- * 1858 * 1859 * PCI bus 1860 * 1861 * ------------------------------------------------------------------------- */ 1862 1863 static u32 riva_get_arch(struct pci_dev *pd) 1864 { 1865 u32 arch = 0; 1866 1867 switch (pd->device & 0x0ff0) { 1868 case 0x0100: /* GeForce 256 */ 1869 case 0x0110: /* GeForce2 MX */ 1870 case 0x0150: /* GeForce2 */ 1871 case 0x0170: /* GeForce4 MX */ 1872 case 0x0180: /* GeForce4 MX (8x AGP) */ 1873 case 0x01A0: /* nForce */ 1874 case 0x01F0: /* nForce2 */ 1875 arch = NV_ARCH_10; 1876 break; 1877 case 0x0200: /* GeForce3 */ 1878 case 0x0250: /* GeForce4 Ti */ 1879 case 0x0280: /* GeForce4 Ti (8x AGP) */ 1880 arch = NV_ARCH_20; 1881 break; 1882 case 0x0300: /* GeForceFX 5800 */ 1883 case 0x0310: /* GeForceFX 5600 */ 1884 case 0x0320: /* GeForceFX 5200 */ 1885 case 0x0330: /* GeForceFX 5900 */ 1886 case 0x0340: /* GeForceFX 5700 */ 1887 arch = NV_ARCH_30; 1888 break; 1889 case 0x0020: /* TNT, TNT2 */ 1890 arch = NV_ARCH_04; 1891 break; 1892 case 0x0010: /* Riva128 */ 1893 arch = NV_ARCH_03; 1894 break; 1895 default: /* unknown architecture */ 1896 break; 1897 } 1898 return arch; 1899 } 1900 1901 static int rivafb_probe(struct pci_dev *pd, const struct pci_device_id *ent) 1902 { 1903 struct riva_par *default_par; 1904 struct fb_info *info; 1905 int ret; 1906 1907 NVTRACE_ENTER(); 1908 assert(pd != NULL); 1909 1910 info = framebuffer_alloc(sizeof(struct riva_par), &pd->dev); 1911 if (!info) { 1912 printk (KERN_ERR PFX "could not allocate memory\n"); 1913 ret = -ENOMEM; 1914 goto err_ret; 1915 } 1916 default_par = info->par; 1917 default_par->pdev = pd; 1918 1919 info->pixmap.addr = kzalloc(8 * 1024, GFP_KERNEL); 1920 if (info->pixmap.addr == NULL) { 1921 ret = -ENOMEM; 1922 goto err_framebuffer_release; 1923 } 1924 1925 ret = pci_enable_device(pd); 1926 if (ret < 0) { 1927 printk(KERN_ERR PFX "cannot enable PCI device\n"); 1928 goto err_free_pixmap; 1929 } 1930 1931 ret = pci_request_regions(pd, "rivafb"); 1932 if (ret < 0) { 1933 printk(KERN_ERR PFX "cannot request PCI regions\n"); 1934 goto err_disable_device; 1935 } 1936 1937 mutex_init(&default_par->open_lock); 1938 default_par->riva.Architecture = riva_get_arch(pd); 1939 1940 default_par->Chipset = (pd->vendor << 16) | pd->device; 1941 printk(KERN_INFO PFX "nVidia device/chipset %X\n",default_par->Chipset); 1942 1943 if(default_par->riva.Architecture == 0) { 1944 printk(KERN_ERR PFX "unknown NV_ARCH\n"); 1945 ret=-ENODEV; 1946 goto err_release_region; 1947 } 1948 if(default_par->riva.Architecture == NV_ARCH_10 || 1949 default_par->riva.Architecture == NV_ARCH_20 || 1950 default_par->riva.Architecture == NV_ARCH_30) { 1951 sprintf(rivafb_fix.id, "NV%x", (pd->device & 0x0ff0) >> 4); 1952 } else { 1953 sprintf(rivafb_fix.id, "NV%x", default_par->riva.Architecture); 1954 } 1955 1956 default_par->FlatPanel = flatpanel; 1957 if (flatpanel == 1) 1958 printk(KERN_INFO PFX "flatpanel support enabled\n"); 1959 default_par->forceCRTC = forceCRTC; 1960 1961 rivafb_fix.mmio_len = pci_resource_len(pd, 0); 1962 rivafb_fix.smem_len = pci_resource_len(pd, 1); 1963 1964 { 1965 /* enable IO and mem if not already done */ 1966 unsigned short cmd; 1967 1968 pci_read_config_word(pd, PCI_COMMAND, &cmd); 1969 cmd |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY); 1970 pci_write_config_word(pd, PCI_COMMAND, cmd); 1971 } 1972 1973 rivafb_fix.mmio_start = pci_resource_start(pd, 0); 1974 rivafb_fix.smem_start = pci_resource_start(pd, 1); 1975 1976 default_par->ctrl_base = ioremap(rivafb_fix.mmio_start, 1977 rivafb_fix.mmio_len); 1978 if (!default_par->ctrl_base) { 1979 printk(KERN_ERR PFX "cannot ioremap MMIO base\n"); 1980 ret = -EIO; 1981 goto err_release_region; 1982 } 1983 1984 switch (default_par->riva.Architecture) { 1985 case NV_ARCH_03: 1986 /* Riva128's PRAMIN is in the "framebuffer" space 1987 * Since these cards were never made with more than 8 megabytes 1988 * we can safely allocate this separately. 1989 */ 1990 default_par->riva.PRAMIN = ioremap(rivafb_fix.smem_start + 0x00C00000, 0x00008000); 1991 if (!default_par->riva.PRAMIN) { 1992 printk(KERN_ERR PFX "cannot ioremap PRAMIN region\n"); 1993 ret = -EIO; 1994 goto err_iounmap_ctrl_base; 1995 } 1996 break; 1997 case NV_ARCH_04: 1998 case NV_ARCH_10: 1999 case NV_ARCH_20: 2000 case NV_ARCH_30: 2001 default_par->riva.PCRTC0 = 2002 (u32 __iomem *)(default_par->ctrl_base + 0x00600000); 2003 default_par->riva.PRAMIN = 2004 (u32 __iomem *)(default_par->ctrl_base + 0x00710000); 2005 break; 2006 } 2007 riva_common_setup(default_par); 2008 2009 if (default_par->riva.Architecture == NV_ARCH_03) { 2010 default_par->riva.PCRTC = default_par->riva.PCRTC0 2011 = default_par->riva.PGRAPH; 2012 } 2013 2014 rivafb_fix.smem_len = riva_get_memlen(default_par) * 1024; 2015 default_par->dclk_max = riva_get_maxdclk(default_par) * 1000; 2016 info->screen_base = ioremap(rivafb_fix.smem_start, 2017 rivafb_fix.smem_len); 2018 if (!info->screen_base) { 2019 printk(KERN_ERR PFX "cannot ioremap FB base\n"); 2020 ret = -EIO; 2021 goto err_iounmap_pramin; 2022 } 2023 2024 #ifdef CONFIG_MTRR 2025 if (!nomtrr) { 2026 default_par->mtrr.vram = mtrr_add(rivafb_fix.smem_start, 2027 rivafb_fix.smem_len, 2028 MTRR_TYPE_WRCOMB, 1); 2029 if (default_par->mtrr.vram < 0) { 2030 printk(KERN_ERR PFX "unable to setup MTRR\n"); 2031 } else { 2032 default_par->mtrr.vram_valid = 1; 2033 /* let there be speed */ 2034 printk(KERN_INFO PFX "RIVA MTRR set to ON\n"); 2035 } 2036 } 2037 #endif /* CONFIG_MTRR */ 2038 2039 info->fbops = &riva_fb_ops; 2040 info->fix = rivafb_fix; 2041 riva_get_EDID(info, pd); 2042 riva_get_edidinfo(info); 2043 2044 ret=riva_set_fbinfo(info); 2045 if (ret < 0) { 2046 printk(KERN_ERR PFX "error setting initial video mode\n"); 2047 goto err_iounmap_screen_base; 2048 } 2049 2050 fb_destroy_modedb(info->monspecs.modedb); 2051 info->monspecs.modedb = NULL; 2052 2053 pci_set_drvdata(pd, info); 2054 2055 if (backlight) 2056 riva_bl_init(info->par); 2057 2058 ret = register_framebuffer(info); 2059 if (ret < 0) { 2060 printk(KERN_ERR PFX 2061 "error registering riva framebuffer\n"); 2062 goto err_iounmap_screen_base; 2063 } 2064 2065 printk(KERN_INFO PFX 2066 "PCI nVidia %s framebuffer ver %s (%dMB @ 0x%lX)\n", 2067 info->fix.id, 2068 RIVAFB_VERSION, 2069 info->fix.smem_len / (1024 * 1024), 2070 info->fix.smem_start); 2071 2072 NVTRACE_LEAVE(); 2073 return 0; 2074 2075 err_iounmap_screen_base: 2076 #ifdef CONFIG_FB_RIVA_I2C 2077 riva_delete_i2c_busses(info->par); 2078 #endif 2079 iounmap(info->screen_base); 2080 err_iounmap_pramin: 2081 if (default_par->riva.Architecture == NV_ARCH_03) 2082 iounmap(default_par->riva.PRAMIN); 2083 err_iounmap_ctrl_base: 2084 iounmap(default_par->ctrl_base); 2085 err_release_region: 2086 pci_release_regions(pd); 2087 err_disable_device: 2088 err_free_pixmap: 2089 kfree(info->pixmap.addr); 2090 err_framebuffer_release: 2091 framebuffer_release(info); 2092 err_ret: 2093 return ret; 2094 } 2095 2096 static void rivafb_remove(struct pci_dev *pd) 2097 { 2098 struct fb_info *info = pci_get_drvdata(pd); 2099 struct riva_par *par = info->par; 2100 2101 NVTRACE_ENTER(); 2102 2103 #ifdef CONFIG_FB_RIVA_I2C 2104 riva_delete_i2c_busses(par); 2105 kfree(par->EDID); 2106 #endif 2107 2108 unregister_framebuffer(info); 2109 2110 riva_bl_exit(info); 2111 2112 #ifdef CONFIG_MTRR 2113 if (par->mtrr.vram_valid) 2114 mtrr_del(par->mtrr.vram, info->fix.smem_start, 2115 info->fix.smem_len); 2116 #endif /* CONFIG_MTRR */ 2117 2118 iounmap(par->ctrl_base); 2119 iounmap(info->screen_base); 2120 if (par->riva.Architecture == NV_ARCH_03) 2121 iounmap(par->riva.PRAMIN); 2122 pci_release_regions(pd); 2123 kfree(info->pixmap.addr); 2124 framebuffer_release(info); 2125 NVTRACE_LEAVE(); 2126 } 2127 2128 /* ------------------------------------------------------------------------- * 2129 * 2130 * initialization 2131 * 2132 * ------------------------------------------------------------------------- */ 2133 2134 #ifndef MODULE 2135 static int rivafb_setup(char *options) 2136 { 2137 char *this_opt; 2138 2139 NVTRACE_ENTER(); 2140 if (!options || !*options) 2141 return 0; 2142 2143 while ((this_opt = strsep(&options, ",")) != NULL) { 2144 if (!strncmp(this_opt, "forceCRTC", 9)) { 2145 char *p; 2146 2147 p = this_opt + 9; 2148 if (!*p || !*(++p)) continue; 2149 forceCRTC = *p - '0'; 2150 if (forceCRTC < 0 || forceCRTC > 1) 2151 forceCRTC = -1; 2152 } else if (!strncmp(this_opt, "flatpanel", 9)) { 2153 flatpanel = 1; 2154 } else if (!strncmp(this_opt, "backlight:", 10)) { 2155 backlight = simple_strtoul(this_opt+10, NULL, 0); 2156 #ifdef CONFIG_MTRR 2157 } else if (!strncmp(this_opt, "nomtrr", 6)) { 2158 nomtrr = 1; 2159 #endif 2160 } else if (!strncmp(this_opt, "strictmode", 10)) { 2161 strictmode = 1; 2162 } else if (!strncmp(this_opt, "noaccel", 7)) { 2163 noaccel = 1; 2164 } else 2165 mode_option = this_opt; 2166 } 2167 NVTRACE_LEAVE(); 2168 return 0; 2169 } 2170 #endif /* !MODULE */ 2171 2172 static struct pci_driver rivafb_driver = { 2173 .name = "rivafb", 2174 .id_table = rivafb_pci_tbl, 2175 .probe = rivafb_probe, 2176 .remove = rivafb_remove, 2177 }; 2178 2179 2180 2181 /* ------------------------------------------------------------------------- * 2182 * 2183 * modularization 2184 * 2185 * ------------------------------------------------------------------------- */ 2186 2187 static int rivafb_init(void) 2188 { 2189 #ifndef MODULE 2190 char *option = NULL; 2191 2192 if (fb_get_options("rivafb", &option)) 2193 return -ENODEV; 2194 rivafb_setup(option); 2195 #endif 2196 return pci_register_driver(&rivafb_driver); 2197 } 2198 2199 2200 module_init(rivafb_init); 2201 2202 static void __exit rivafb_exit(void) 2203 { 2204 pci_unregister_driver(&rivafb_driver); 2205 } 2206 2207 module_exit(rivafb_exit); 2208 2209 module_param(noaccel, bool, 0); 2210 MODULE_PARM_DESC(noaccel, "bool: disable acceleration"); 2211 module_param(flatpanel, int, 0); 2212 MODULE_PARM_DESC(flatpanel, "Enables experimental flat panel support for some chipsets. (0 or 1=enabled) (default=0)"); 2213 module_param(forceCRTC, int, 0); 2214 MODULE_PARM_DESC(forceCRTC, "Forces usage of a particular CRTC in case autodetection fails. (0 or 1) (default=autodetect)"); 2215 #ifdef CONFIG_MTRR 2216 module_param(nomtrr, bool, 0); 2217 MODULE_PARM_DESC(nomtrr, "Disables MTRR support (0 or 1=disabled) (default=0)"); 2218 #endif 2219 module_param(strictmode, bool, 0); 2220 MODULE_PARM_DESC(strictmode, "Only use video modes from EDID"); 2221 2222 MODULE_AUTHOR("Ani Joshi, maintainer"); 2223 MODULE_DESCRIPTION("Framebuffer driver for nVidia Riva 128, TNT, TNT2, and the GeForce series"); 2224 MODULE_LICENSE("GPL"); 2225