xref: /openbmc/linux/drivers/video/fbdev/riva/fbdev.c (revision 0b26ca68)
1 /*
2  * linux/drivers/video/riva/fbdev.c - nVidia RIVA 128/TNT/TNT2 fb driver
3  *
4  * Maintained by Ani Joshi <ajoshi@shell.unixbox.com>
5  *
6  * Copyright 1999-2000 Jeff Garzik
7  *
8  * Contributors:
9  *
10  *	Ani Joshi:  Lots of debugging and cleanup work, really helped
11  *	get the driver going
12  *
13  *	Ferenc Bakonyi:  Bug fixes, cleanup, modularization
14  *
15  *	Jindrich Makovicka:  Accel code help, hw cursor, mtrr
16  *
17  *	Paul Richards:  Bug fixes, updates
18  *
19  * Initial template from skeletonfb.c, created 28 Dec 1997 by Geert Uytterhoeven
20  * Includes riva_hw.c from nVidia, see copyright below.
21  * KGI code provided the basis for state storage, init, and mode switching.
22  *
23  * This file is subject to the terms and conditions of the GNU General Public
24  * License.  See the file COPYING in the main directory of this archive
25  * for more details.
26  *
27  * Known bugs and issues:
28  *	restoring text mode fails
29  *	doublescan modes are broken
30  */
31 
32 #include <linux/module.h>
33 #include <linux/kernel.h>
34 #include <linux/errno.h>
35 #include <linux/string.h>
36 #include <linux/mm.h>
37 #include <linux/slab.h>
38 #include <linux/delay.h>
39 #include <linux/fb.h>
40 #include <linux/init.h>
41 #include <linux/pci.h>
42 #include <linux/backlight.h>
43 #include <linux/bitrev.h>
44 #ifdef CONFIG_PMAC_BACKLIGHT
45 #include <asm/machdep.h>
46 #include <asm/backlight.h>
47 #endif
48 
49 #include "rivafb.h"
50 #include "nvreg.h"
51 
52 /* version number of this driver */
53 #define RIVAFB_VERSION "0.9.5b"
54 
55 /* ------------------------------------------------------------------------- *
56  *
57  * various helpful macros and constants
58  *
59  * ------------------------------------------------------------------------- */
60 #ifdef CONFIG_FB_RIVA_DEBUG
61 #define NVTRACE          printk
62 #else
63 #define NVTRACE          if(0) printk
64 #endif
65 
66 #define NVTRACE_ENTER(...)  NVTRACE("%s START\n", __func__)
67 #define NVTRACE_LEAVE(...)  NVTRACE("%s END\n", __func__)
68 
69 #ifdef CONFIG_FB_RIVA_DEBUG
70 #define assert(expr) \
71 	if(!(expr)) { \
72 	printk( "Assertion failed! %s,%s,%s,line=%d\n",\
73 	#expr,__FILE__,__func__,__LINE__); \
74 	BUG(); \
75 	}
76 #else
77 #define assert(expr)
78 #endif
79 
80 #define PFX "rivafb: "
81 
82 /* macro that allows you to set overflow bits */
83 #define SetBitField(value,from,to) SetBF(to,GetBF(value,from))
84 #define SetBit(n)		(1<<(n))
85 #define Set8Bits(value)		((value)&0xff)
86 
87 /* HW cursor parameters */
88 #define MAX_CURS		32
89 
90 /* ------------------------------------------------------------------------- *
91  *
92  * prototypes
93  *
94  * ------------------------------------------------------------------------- */
95 
96 static int rivafb_blank(int blank, struct fb_info *info);
97 
98 /* ------------------------------------------------------------------------- *
99  *
100  * card identification
101  *
102  * ------------------------------------------------------------------------- */
103 
104 static const struct pci_device_id rivafb_pci_tbl[] = {
105 	{ PCI_VENDOR_ID_NVIDIA_SGS, PCI_DEVICE_ID_NVIDIA_SGS_RIVA128,
106 	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
107 	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT,
108 	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
109 	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT2,
110 	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
111 	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_UTNT2,
112 	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
113 	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_VTNT2,
114 	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
115 	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_UVTNT2,
116 	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
117 	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_ITNT2,
118 	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
119 	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_SDR,
120 	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
121 	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_DDR,
122 	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
123 	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO,
124 	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
125 	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX,
126 	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
127 	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX2,
128 	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
129 	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GO,
130 	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
131 	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO2_MXR,
132 	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
133 	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS,
134 	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
135 	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS2,
136 	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
137 	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_ULTRA,
138 	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
139 	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO2_PRO,
140 	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
141 	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_460,
142 	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
143 	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440,
144 	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
145 	// NF2/IGP version, GeForce 4 MX, NV18
146 	{ PCI_VENDOR_ID_NVIDIA, 0x01f0,
147 	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
148 	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_420,
149 	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
150 	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO,
151 	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
152 	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO,
153 	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
154 	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO_M32,
155 	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
156 	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_500XGL,
157 	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
158 	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO_M64,
159 	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
160 	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_200,
161 	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
162 	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_550XGL,
163 	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
164 	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_500_GOGL,
165 	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
166 	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_IGEFORCE2,
167 	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
168 	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3,
169 	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
170 	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3_1,
171 	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
172 	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3_2,
173 	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
174 	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_DDC,
175 	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
176 	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4600,
177 	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
178 	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4400,
179 	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
180 	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4200,
181 	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
182  	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_900XGL,
183 	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
184 	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_750XGL,
185 	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
186 	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_700XGL,
187 	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
188 	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO_5200,
189 	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
190 	{ 0, } /* terminate list */
191 };
192 MODULE_DEVICE_TABLE(pci, rivafb_pci_tbl);
193 
194 /* ------------------------------------------------------------------------- *
195  *
196  * global variables
197  *
198  * ------------------------------------------------------------------------- */
199 
200 /* command line data, set in rivafb_setup() */
201 static int flatpanel = -1; /* Autodetect later */
202 static int forceCRTC = -1;
203 static bool noaccel  = 0;
204 static bool nomtrr = 0;
205 static int backlight = IS_BUILTIN(CONFIG_PMAC_BACKLIGHT);
206 
207 static char *mode_option = NULL;
208 static bool strictmode       = 0;
209 
210 static struct fb_fix_screeninfo rivafb_fix = {
211 	.type		= FB_TYPE_PACKED_PIXELS,
212 	.xpanstep	= 1,
213 	.ypanstep	= 1,
214 };
215 
216 static struct fb_var_screeninfo rivafb_default_var = {
217 	.xres		= 640,
218 	.yres		= 480,
219 	.xres_virtual	= 640,
220 	.yres_virtual	= 480,
221 	.bits_per_pixel	= 8,
222 	.red		= {0, 8, 0},
223 	.green		= {0, 8, 0},
224 	.blue		= {0, 8, 0},
225 	.transp		= {0, 0, 0},
226 	.activate	= FB_ACTIVATE_NOW,
227 	.height		= -1,
228 	.width		= -1,
229 	.pixclock	= 39721,
230 	.left_margin	= 40,
231 	.right_margin	= 24,
232 	.upper_margin	= 32,
233 	.lower_margin	= 11,
234 	.hsync_len	= 96,
235 	.vsync_len	= 2,
236 	.vmode		= FB_VMODE_NONINTERLACED
237 };
238 
239 /* from GGI */
240 static const struct riva_regs reg_template = {
241 	{0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,	/* ATTR */
242 	 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
243 	 0x41, 0x01, 0x0F, 0x00, 0x00},
244 	{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,	/* CRT  */
245 	 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00,
246 	 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE3,	/* 0x10 */
247 	 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
248 	 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,	/* 0x20 */
249 	 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
250 	 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,	/* 0x30 */
251 	 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
252 	 0x00,							/* 0x40 */
253 	 },
254 	{0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F,	/* GRA  */
255 	 0xFF},
256 	{0x03, 0x01, 0x0F, 0x00, 0x0E},				/* SEQ  */
257 	0xEB							/* MISC */
258 };
259 
260 /*
261  * Backlight control
262  */
263 #ifdef CONFIG_FB_RIVA_BACKLIGHT
264 /* We do not have any information about which values are allowed, thus
265  * we used safe values.
266  */
267 #define MIN_LEVEL 0x158
268 #define MAX_LEVEL 0x534
269 #define LEVEL_STEP ((MAX_LEVEL - MIN_LEVEL) / FB_BACKLIGHT_MAX)
270 
271 static int riva_bl_get_level_brightness(struct riva_par *par,
272 		int level)
273 {
274 	struct fb_info *info = pci_get_drvdata(par->pdev);
275 	int nlevel;
276 
277 	/* Get and convert the value */
278 	/* No locking on bl_curve since accessing a single value */
279 	nlevel = MIN_LEVEL + info->bl_curve[level] * LEVEL_STEP;
280 
281 	if (nlevel < 0)
282 		nlevel = 0;
283 	else if (nlevel < MIN_LEVEL)
284 		nlevel = MIN_LEVEL;
285 	else if (nlevel > MAX_LEVEL)
286 		nlevel = MAX_LEVEL;
287 
288 	return nlevel;
289 }
290 
291 static int riva_bl_update_status(struct backlight_device *bd)
292 {
293 	struct riva_par *par = bl_get_data(bd);
294 	U032 tmp_pcrt, tmp_pmc;
295 	int level;
296 
297 	if (bd->props.power != FB_BLANK_UNBLANK ||
298 	    bd->props.fb_blank != FB_BLANK_UNBLANK)
299 		level = 0;
300 	else
301 		level = bd->props.brightness;
302 
303 	tmp_pmc = NV_RD32(par->riva.PMC, 0x10F0) & 0x0000FFFF;
304 	tmp_pcrt = NV_RD32(par->riva.PCRTC0, 0x081C) & 0xFFFFFFFC;
305 	if(level > 0) {
306 		tmp_pcrt |= 0x1;
307 		tmp_pmc |= (1 << 31); /* backlight bit */
308 		tmp_pmc |= riva_bl_get_level_brightness(par, level) << 16; /* level */
309 	}
310 	NV_WR32(par->riva.PCRTC0, 0x081C, tmp_pcrt);
311 	NV_WR32(par->riva.PMC, 0x10F0, tmp_pmc);
312 
313 	return 0;
314 }
315 
316 static const struct backlight_ops riva_bl_ops = {
317 	.update_status	= riva_bl_update_status,
318 };
319 
320 static void riva_bl_init(struct riva_par *par)
321 {
322 	struct backlight_properties props;
323 	struct fb_info *info = pci_get_drvdata(par->pdev);
324 	struct backlight_device *bd;
325 	char name[12];
326 
327 	if (!par->FlatPanel)
328 		return;
329 
330 #ifdef CONFIG_PMAC_BACKLIGHT
331 	if (!machine_is(powermac) ||
332 	    !pmac_has_backlight_type("mnca"))
333 		return;
334 #endif
335 
336 	snprintf(name, sizeof(name), "rivabl%d", info->node);
337 
338 	memset(&props, 0, sizeof(struct backlight_properties));
339 	props.type = BACKLIGHT_RAW;
340 	props.max_brightness = FB_BACKLIGHT_LEVELS - 1;
341 	bd = backlight_device_register(name, info->dev, par, &riva_bl_ops,
342 				       &props);
343 	if (IS_ERR(bd)) {
344 		info->bl_dev = NULL;
345 		printk(KERN_WARNING "riva: Backlight registration failed\n");
346 		goto error;
347 	}
348 
349 	info->bl_dev = bd;
350 	fb_bl_default_curve(info, 0,
351 		MIN_LEVEL * FB_BACKLIGHT_MAX / MAX_LEVEL,
352 		FB_BACKLIGHT_MAX);
353 
354 	bd->props.brightness = bd->props.max_brightness;
355 	bd->props.power = FB_BLANK_UNBLANK;
356 	backlight_update_status(bd);
357 
358 	printk("riva: Backlight initialized (%s)\n", name);
359 
360 	return;
361 
362 error:
363 	return;
364 }
365 
366 static void riva_bl_exit(struct fb_info *info)
367 {
368 	struct backlight_device *bd = info->bl_dev;
369 
370 	backlight_device_unregister(bd);
371 	printk("riva: Backlight unloaded\n");
372 }
373 #else
374 static inline void riva_bl_init(struct riva_par *par) {}
375 static inline void riva_bl_exit(struct fb_info *info) {}
376 #endif /* CONFIG_FB_RIVA_BACKLIGHT */
377 
378 /* ------------------------------------------------------------------------- *
379  *
380  * MMIO access macros
381  *
382  * ------------------------------------------------------------------------- */
383 
384 static inline void CRTCout(struct riva_par *par, unsigned char index,
385 			   unsigned char val)
386 {
387 	VGA_WR08(par->riva.PCIO, 0x3d4, index);
388 	VGA_WR08(par->riva.PCIO, 0x3d5, val);
389 }
390 
391 static inline unsigned char CRTCin(struct riva_par *par,
392 				   unsigned char index)
393 {
394 	VGA_WR08(par->riva.PCIO, 0x3d4, index);
395 	return (VGA_RD08(par->riva.PCIO, 0x3d5));
396 }
397 
398 static inline void GRAout(struct riva_par *par, unsigned char index,
399 			  unsigned char val)
400 {
401 	VGA_WR08(par->riva.PVIO, 0x3ce, index);
402 	VGA_WR08(par->riva.PVIO, 0x3cf, val);
403 }
404 
405 static inline unsigned char GRAin(struct riva_par *par,
406 				  unsigned char index)
407 {
408 	VGA_WR08(par->riva.PVIO, 0x3ce, index);
409 	return (VGA_RD08(par->riva.PVIO, 0x3cf));
410 }
411 
412 static inline void SEQout(struct riva_par *par, unsigned char index,
413 			  unsigned char val)
414 {
415 	VGA_WR08(par->riva.PVIO, 0x3c4, index);
416 	VGA_WR08(par->riva.PVIO, 0x3c5, val);
417 }
418 
419 static inline unsigned char SEQin(struct riva_par *par,
420 				  unsigned char index)
421 {
422 	VGA_WR08(par->riva.PVIO, 0x3c4, index);
423 	return (VGA_RD08(par->riva.PVIO, 0x3c5));
424 }
425 
426 static inline void ATTRout(struct riva_par *par, unsigned char index,
427 			   unsigned char val)
428 {
429 	VGA_WR08(par->riva.PCIO, 0x3c0, index);
430 	VGA_WR08(par->riva.PCIO, 0x3c0, val);
431 }
432 
433 static inline unsigned char ATTRin(struct riva_par *par,
434 				   unsigned char index)
435 {
436 	VGA_WR08(par->riva.PCIO, 0x3c0, index);
437 	return (VGA_RD08(par->riva.PCIO, 0x3c1));
438 }
439 
440 static inline void MISCout(struct riva_par *par, unsigned char val)
441 {
442 	VGA_WR08(par->riva.PVIO, 0x3c2, val);
443 }
444 
445 static inline unsigned char MISCin(struct riva_par *par)
446 {
447 	return (VGA_RD08(par->riva.PVIO, 0x3cc));
448 }
449 
450 static inline void reverse_order(u32 *l)
451 {
452 	u8 *a = (u8 *)l;
453 	a[0] = bitrev8(a[0]);
454 	a[1] = bitrev8(a[1]);
455 	a[2] = bitrev8(a[2]);
456 	a[3] = bitrev8(a[3]);
457 }
458 
459 /* ------------------------------------------------------------------------- *
460  *
461  * cursor stuff
462  *
463  * ------------------------------------------------------------------------- */
464 
465 /**
466  * rivafb_load_cursor_image - load cursor image to hardware
467  * @data8: address to monochrome bitmap (1 = foreground color, 0 = background)
468  * @par:  pointer to private data
469  * @w:    width of cursor image in pixels
470  * @h:    height of cursor image in scanlines
471  * @bg:   background color (ARGB1555) - alpha bit determines opacity
472  * @fg:   foreground color (ARGB1555)
473  *
474  * DESCRIPTiON:
475  * Loads cursor image based on a monochrome source and mask bitmap.  The
476  * image bits determines the color of the pixel, 0 for background, 1 for
477  * foreground.  Only the affected region (as determined by @w and @h
478  * parameters) will be updated.
479  *
480  * CALLED FROM:
481  * rivafb_cursor()
482  */
483 static void rivafb_load_cursor_image(struct riva_par *par, u8 *data8,
484 				     u16 bg, u16 fg, u32 w, u32 h)
485 {
486 	int i, j, k = 0;
487 	u32 b, tmp;
488 	u32 *data = (u32 *)data8;
489 	bg = le16_to_cpu(bg);
490 	fg = le16_to_cpu(fg);
491 
492 	w = (w + 1) & ~1;
493 
494 	for (i = 0; i < h; i++) {
495 		b = *data++;
496 		reverse_order(&b);
497 
498 		for (j = 0; j < w/2; j++) {
499 			tmp = 0;
500 #if defined (__BIG_ENDIAN)
501 			tmp = (b & (1 << 31)) ? fg << 16 : bg << 16;
502 			b <<= 1;
503 			tmp |= (b & (1 << 31)) ? fg : bg;
504 			b <<= 1;
505 #else
506 			tmp = (b & 1) ? fg : bg;
507 			b >>= 1;
508 			tmp |= (b & 1) ? fg << 16 : bg << 16;
509 			b >>= 1;
510 #endif
511 			writel(tmp, &par->riva.CURSOR[k++]);
512 		}
513 		k += (MAX_CURS - w)/2;
514 	}
515 }
516 
517 /* ------------------------------------------------------------------------- *
518  *
519  * general utility functions
520  *
521  * ------------------------------------------------------------------------- */
522 
523 /**
524  * riva_wclut - set CLUT entry
525  * @chip: pointer to RIVA_HW_INST object
526  * @regnum: register number
527  * @red: red component
528  * @green: green component
529  * @blue: blue component
530  *
531  * DESCRIPTION:
532  * Sets color register @regnum.
533  *
534  * CALLED FROM:
535  * rivafb_setcolreg()
536  */
537 static void riva_wclut(RIVA_HW_INST *chip,
538 		       unsigned char regnum, unsigned char red,
539 		       unsigned char green, unsigned char blue)
540 {
541 	VGA_WR08(chip->PDIO, 0x3c8, regnum);
542 	VGA_WR08(chip->PDIO, 0x3c9, red);
543 	VGA_WR08(chip->PDIO, 0x3c9, green);
544 	VGA_WR08(chip->PDIO, 0x3c9, blue);
545 }
546 
547 /**
548  * riva_rclut - read fromCLUT register
549  * @chip: pointer to RIVA_HW_INST object
550  * @regnum: register number
551  * @red: red component
552  * @green: green component
553  * @blue: blue component
554  *
555  * DESCRIPTION:
556  * Reads red, green, and blue from color register @regnum.
557  *
558  * CALLED FROM:
559  * rivafb_setcolreg()
560  */
561 static void riva_rclut(RIVA_HW_INST *chip,
562 		       unsigned char regnum, unsigned char *red,
563 		       unsigned char *green, unsigned char *blue)
564 {
565 
566 	VGA_WR08(chip->PDIO, 0x3c7, regnum);
567 	*red = VGA_RD08(chip->PDIO, 0x3c9);
568 	*green = VGA_RD08(chip->PDIO, 0x3c9);
569 	*blue = VGA_RD08(chip->PDIO, 0x3c9);
570 }
571 
572 /**
573  * riva_save_state - saves current chip state
574  * @par: pointer to riva_par object containing info for current riva board
575  * @regs: pointer to riva_regs object
576  *
577  * DESCRIPTION:
578  * Saves current chip state to @regs.
579  *
580  * CALLED FROM:
581  * rivafb_probe()
582  */
583 /* from GGI */
584 static void riva_save_state(struct riva_par *par, struct riva_regs *regs)
585 {
586 	int i;
587 
588 	NVTRACE_ENTER();
589 	par->riva.LockUnlock(&par->riva, 0);
590 
591 	par->riva.UnloadStateExt(&par->riva, &regs->ext);
592 
593 	regs->misc_output = MISCin(par);
594 
595 	for (i = 0; i < NUM_CRT_REGS; i++)
596 		regs->crtc[i] = CRTCin(par, i);
597 
598 	for (i = 0; i < NUM_ATC_REGS; i++)
599 		regs->attr[i] = ATTRin(par, i);
600 
601 	for (i = 0; i < NUM_GRC_REGS; i++)
602 		regs->gra[i] = GRAin(par, i);
603 
604 	for (i = 0; i < NUM_SEQ_REGS; i++)
605 		regs->seq[i] = SEQin(par, i);
606 	NVTRACE_LEAVE();
607 }
608 
609 /**
610  * riva_load_state - loads current chip state
611  * @par: pointer to riva_par object containing info for current riva board
612  * @regs: pointer to riva_regs object
613  *
614  * DESCRIPTION:
615  * Loads chip state from @regs.
616  *
617  * CALLED FROM:
618  * riva_load_video_mode()
619  * rivafb_probe()
620  * rivafb_remove()
621  */
622 /* from GGI */
623 static void riva_load_state(struct riva_par *par, struct riva_regs *regs)
624 {
625 	RIVA_HW_STATE *state = &regs->ext;
626 	int i;
627 
628 	NVTRACE_ENTER();
629 	CRTCout(par, 0x11, 0x00);
630 
631 	par->riva.LockUnlock(&par->riva, 0);
632 
633 	par->riva.LoadStateExt(&par->riva, state);
634 
635 	MISCout(par, regs->misc_output);
636 
637 	for (i = 0; i < NUM_CRT_REGS; i++) {
638 		switch (i) {
639 		case 0x19:
640 		case 0x20 ... 0x40:
641 			break;
642 		default:
643 			CRTCout(par, i, regs->crtc[i]);
644 		}
645 	}
646 
647 	for (i = 0; i < NUM_ATC_REGS; i++)
648 		ATTRout(par, i, regs->attr[i]);
649 
650 	for (i = 0; i < NUM_GRC_REGS; i++)
651 		GRAout(par, i, regs->gra[i]);
652 
653 	for (i = 0; i < NUM_SEQ_REGS; i++)
654 		SEQout(par, i, regs->seq[i]);
655 	NVTRACE_LEAVE();
656 }
657 
658 /**
659  * riva_load_video_mode - calculate timings
660  * @info: pointer to fb_info object containing info for current riva board
661  *
662  * DESCRIPTION:
663  * Calculate some timings and then send em off to riva_load_state().
664  *
665  * CALLED FROM:
666  * rivafb_set_par()
667  */
668 static int riva_load_video_mode(struct fb_info *info)
669 {
670 	int bpp, width, hDisplaySize, hDisplay, hStart,
671 	    hEnd, hTotal, height, vDisplay, vStart, vEnd, vTotal, dotClock;
672 	int hBlankStart, hBlankEnd, vBlankStart, vBlankEnd;
673 	int rc;
674 	struct riva_par *par = info->par;
675 	struct riva_regs newmode;
676 
677 	NVTRACE_ENTER();
678 	/* time to calculate */
679 	rivafb_blank(FB_BLANK_NORMAL, info);
680 
681 	bpp = info->var.bits_per_pixel;
682 	if (bpp == 16 && info->var.green.length == 5)
683 		bpp = 15;
684 	width = info->var.xres_virtual;
685 	hDisplaySize = info->var.xres;
686 	hDisplay = (hDisplaySize / 8) - 1;
687 	hStart = (hDisplaySize + info->var.right_margin) / 8 - 1;
688 	hEnd = (hDisplaySize + info->var.right_margin +
689 		info->var.hsync_len) / 8 - 1;
690 	hTotal = (hDisplaySize + info->var.right_margin +
691 		  info->var.hsync_len + info->var.left_margin) / 8 - 5;
692 	hBlankStart = hDisplay;
693 	hBlankEnd = hTotal + 4;
694 
695 	height = info->var.yres_virtual;
696 	vDisplay = info->var.yres - 1;
697 	vStart = info->var.yres + info->var.lower_margin - 1;
698 	vEnd = info->var.yres + info->var.lower_margin +
699 	       info->var.vsync_len - 1;
700 	vTotal = info->var.yres + info->var.lower_margin +
701 		 info->var.vsync_len + info->var.upper_margin + 2;
702 	vBlankStart = vDisplay;
703 	vBlankEnd = vTotal + 1;
704 	dotClock = 1000000000 / info->var.pixclock;
705 
706 	memcpy(&newmode, &reg_template, sizeof(struct riva_regs));
707 
708 	if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED)
709 		vTotal |= 1;
710 
711 	if (par->FlatPanel) {
712 		vStart = vTotal - 3;
713 		vEnd = vTotal - 2;
714 		vBlankStart = vStart;
715 		hStart = hTotal - 3;
716 		hEnd = hTotal - 2;
717 		hBlankEnd = hTotal + 4;
718 	}
719 
720 	newmode.crtc[0x0] = Set8Bits (hTotal);
721 	newmode.crtc[0x1] = Set8Bits (hDisplay);
722 	newmode.crtc[0x2] = Set8Bits (hBlankStart);
723 	newmode.crtc[0x3] = SetBitField (hBlankEnd, 4: 0, 4:0) | SetBit (7);
724 	newmode.crtc[0x4] = Set8Bits (hStart);
725 	newmode.crtc[0x5] = SetBitField (hBlankEnd, 5: 5, 7:7)
726 		| SetBitField (hEnd, 4: 0, 4:0);
727 	newmode.crtc[0x6] = SetBitField (vTotal, 7: 0, 7:0);
728 	newmode.crtc[0x7] = SetBitField (vTotal, 8: 8, 0:0)
729 		| SetBitField (vDisplay, 8: 8, 1:1)
730 		| SetBitField (vStart, 8: 8, 2:2)
731 		| SetBitField (vBlankStart, 8: 8, 3:3)
732 		| SetBit (4)
733 		| SetBitField (vTotal, 9: 9, 5:5)
734 		| SetBitField (vDisplay, 9: 9, 6:6)
735 		| SetBitField (vStart, 9: 9, 7:7);
736 	newmode.crtc[0x9] = SetBitField (vBlankStart, 9: 9, 5:5)
737 		| SetBit (6);
738 	newmode.crtc[0x10] = Set8Bits (vStart);
739 	newmode.crtc[0x11] = SetBitField (vEnd, 3: 0, 3:0)
740 		| SetBit (5);
741 	newmode.crtc[0x12] = Set8Bits (vDisplay);
742 	newmode.crtc[0x13] = (width / 8) * ((bpp + 1) / 8);
743 	newmode.crtc[0x15] = Set8Bits (vBlankStart);
744 	newmode.crtc[0x16] = Set8Bits (vBlankEnd);
745 
746 	newmode.ext.screen = SetBitField(hBlankEnd,6:6,4:4)
747 		| SetBitField(vBlankStart,10:10,3:3)
748 		| SetBitField(vStart,10:10,2:2)
749 		| SetBitField(vDisplay,10:10,1:1)
750 		| SetBitField(vTotal,10:10,0:0);
751 	newmode.ext.horiz  = SetBitField(hTotal,8:8,0:0)
752 		| SetBitField(hDisplay,8:8,1:1)
753 		| SetBitField(hBlankStart,8:8,2:2)
754 		| SetBitField(hStart,8:8,3:3);
755 	newmode.ext.extra  = SetBitField(vTotal,11:11,0:0)
756 		| SetBitField(vDisplay,11:11,2:2)
757 		| SetBitField(vStart,11:11,4:4)
758 		| SetBitField(vBlankStart,11:11,6:6);
759 
760 	if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) {
761 		int tmp = (hTotal >> 1) & ~1;
762 		newmode.ext.interlace = Set8Bits(tmp);
763 		newmode.ext.horiz |= SetBitField(tmp, 8:8,4:4);
764 	} else
765 		newmode.ext.interlace = 0xff; /* interlace off */
766 
767 	if (par->riva.Architecture >= NV_ARCH_10)
768 		par->riva.CURSOR = (U032 __iomem *)(info->screen_base + par->riva.CursorStart);
769 
770 	if (info->var.sync & FB_SYNC_HOR_HIGH_ACT)
771 		newmode.misc_output &= ~0x40;
772 	else
773 		newmode.misc_output |= 0x40;
774 	if (info->var.sync & FB_SYNC_VERT_HIGH_ACT)
775 		newmode.misc_output &= ~0x80;
776 	else
777 		newmode.misc_output |= 0x80;
778 
779 	rc = CalcStateExt(&par->riva, &newmode.ext, par->pdev, bpp, width,
780 			  hDisplaySize, height, dotClock);
781 	if (rc)
782 		goto out;
783 
784 	newmode.ext.scale = NV_RD32(par->riva.PRAMDAC, 0x00000848) &
785 		0xfff000ff;
786 	if (par->FlatPanel == 1) {
787 		newmode.ext.pixel |= (1 << 7);
788 		newmode.ext.scale |= (1 << 8);
789 	}
790 	if (par->SecondCRTC) {
791 		newmode.ext.head  = NV_RD32(par->riva.PCRTC0, 0x00000860) &
792 			~0x00001000;
793 		newmode.ext.head2 = NV_RD32(par->riva.PCRTC0, 0x00002860) |
794 			0x00001000;
795 		newmode.ext.crtcOwner = 3;
796 		newmode.ext.pllsel |= 0x20000800;
797 		newmode.ext.vpll2 = newmode.ext.vpll;
798 	} else if (par->riva.twoHeads) {
799 		newmode.ext.head  =  NV_RD32(par->riva.PCRTC0, 0x00000860) |
800 			0x00001000;
801 		newmode.ext.head2 =  NV_RD32(par->riva.PCRTC0, 0x00002860) &
802 			~0x00001000;
803 		newmode.ext.crtcOwner = 0;
804 		newmode.ext.vpll2 = NV_RD32(par->riva.PRAMDAC0, 0x00000520);
805 	}
806 	if (par->FlatPanel == 1) {
807 		newmode.ext.pixel |= (1 << 7);
808 		newmode.ext.scale |= (1 << 8);
809 	}
810 	newmode.ext.cursorConfig = 0x02000100;
811 	par->current_state = newmode;
812 	riva_load_state(par, &par->current_state);
813 	par->riva.LockUnlock(&par->riva, 0); /* important for HW cursor */
814 
815 out:
816 	rivafb_blank(FB_BLANK_UNBLANK, info);
817 	NVTRACE_LEAVE();
818 
819 	return rc;
820 }
821 
822 static void riva_update_var(struct fb_var_screeninfo *var,
823 			    const struct fb_videomode *modedb)
824 {
825 	NVTRACE_ENTER();
826 	var->xres = var->xres_virtual = modedb->xres;
827 	var->yres = modedb->yres;
828         if (var->yres_virtual < var->yres)
829 	    var->yres_virtual = var->yres;
830         var->xoffset = var->yoffset = 0;
831         var->pixclock = modedb->pixclock;
832         var->left_margin = modedb->left_margin;
833         var->right_margin = modedb->right_margin;
834         var->upper_margin = modedb->upper_margin;
835         var->lower_margin = modedb->lower_margin;
836         var->hsync_len = modedb->hsync_len;
837         var->vsync_len = modedb->vsync_len;
838         var->sync = modedb->sync;
839         var->vmode = modedb->vmode;
840 	NVTRACE_LEAVE();
841 }
842 
843 /**
844  * rivafb_do_maximize -
845  * @info: pointer to fb_info object containing info for current riva board
846  * @var: standard kernel fb changeable data
847  * @nom: nom
848  * @den: den
849  *
850  * DESCRIPTION:
851  * .
852  *
853  * RETURNS:
854  * -EINVAL on failure, 0 on success
855  *
856  *
857  * CALLED FROM:
858  * rivafb_check_var()
859  */
860 static int rivafb_do_maximize(struct fb_info *info,
861 			      struct fb_var_screeninfo *var,
862 			      int nom, int den)
863 {
864 	static struct {
865 		int xres, yres;
866 	} modes[] = {
867 		{1600, 1280},
868 		{1280, 1024},
869 		{1024, 768},
870 		{800, 600},
871 		{640, 480},
872 		{-1, -1}
873 	};
874 	int i;
875 
876 	NVTRACE_ENTER();
877 	/* use highest possible virtual resolution */
878 	if (var->xres_virtual == -1 && var->yres_virtual == -1) {
879 		printk(KERN_WARNING PFX
880 		       "using maximum available virtual resolution\n");
881 		for (i = 0; modes[i].xres != -1; i++) {
882 			if (modes[i].xres * nom / den * modes[i].yres <
883 			    info->fix.smem_len)
884 				break;
885 		}
886 		if (modes[i].xres == -1) {
887 			printk(KERN_ERR PFX
888 			       "could not find a virtual resolution that fits into video memory!!\n");
889 			NVTRACE("EXIT - EINVAL error\n");
890 			return -EINVAL;
891 		}
892 		var->xres_virtual = modes[i].xres;
893 		var->yres_virtual = modes[i].yres;
894 
895 		printk(KERN_INFO PFX
896 		       "virtual resolution set to maximum of %dx%d\n",
897 		       var->xres_virtual, var->yres_virtual);
898 	} else if (var->xres_virtual == -1) {
899 		var->xres_virtual = (info->fix.smem_len * den /
900 			(nom * var->yres_virtual)) & ~15;
901 		printk(KERN_WARNING PFX
902 		       "setting virtual X resolution to %d\n", var->xres_virtual);
903 	} else if (var->yres_virtual == -1) {
904 		var->xres_virtual = (var->xres_virtual + 15) & ~15;
905 		var->yres_virtual = info->fix.smem_len * den /
906 			(nom * var->xres_virtual);
907 		printk(KERN_WARNING PFX
908 		       "setting virtual Y resolution to %d\n", var->yres_virtual);
909 	} else {
910 		var->xres_virtual = (var->xres_virtual + 15) & ~15;
911 		if (var->xres_virtual * nom / den * var->yres_virtual > info->fix.smem_len) {
912 			printk(KERN_ERR PFX
913 			       "mode %dx%dx%d rejected...resolution too high to fit into video memory!\n",
914 			       var->xres, var->yres, var->bits_per_pixel);
915 			NVTRACE("EXIT - EINVAL error\n");
916 			return -EINVAL;
917 		}
918 	}
919 
920 	if (var->xres_virtual * nom / den >= 8192) {
921 		printk(KERN_WARNING PFX
922 		       "virtual X resolution (%d) is too high, lowering to %d\n",
923 		       var->xres_virtual, 8192 * den / nom - 16);
924 		var->xres_virtual = 8192 * den / nom - 16;
925 	}
926 
927 	if (var->xres_virtual < var->xres) {
928 		printk(KERN_ERR PFX
929 		       "virtual X resolution (%d) is smaller than real\n", var->xres_virtual);
930 		return -EINVAL;
931 	}
932 
933 	if (var->yres_virtual < var->yres) {
934 		printk(KERN_ERR PFX
935 		       "virtual Y resolution (%d) is smaller than real\n", var->yres_virtual);
936 		return -EINVAL;
937 	}
938 	if (var->yres_virtual > 0x7fff/nom)
939 		var->yres_virtual = 0x7fff/nom;
940 	if (var->xres_virtual > 0x7fff/nom)
941 		var->xres_virtual = 0x7fff/nom;
942 	NVTRACE_LEAVE();
943 	return 0;
944 }
945 
946 static void
947 riva_set_pattern(struct riva_par *par, int clr0, int clr1, int pat0, int pat1)
948 {
949 	RIVA_FIFO_FREE(par->riva, Patt, 4);
950 	NV_WR32(&par->riva.Patt->Color0, 0, clr0);
951 	NV_WR32(&par->riva.Patt->Color1, 0, clr1);
952 	NV_WR32(par->riva.Patt->Monochrome, 0, pat0);
953 	NV_WR32(par->riva.Patt->Monochrome, 4, pat1);
954 }
955 
956 /* acceleration routines */
957 static inline void wait_for_idle(struct riva_par *par)
958 {
959 	while (par->riva.Busy(&par->riva));
960 }
961 
962 /*
963  * Set ROP.  Translate X rop into ROP3.  Internal routine.
964  */
965 static void
966 riva_set_rop_solid(struct riva_par *par, int rop)
967 {
968 	riva_set_pattern(par, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF);
969         RIVA_FIFO_FREE(par->riva, Rop, 1);
970         NV_WR32(&par->riva.Rop->Rop3, 0, rop);
971 
972 }
973 
974 static void riva_setup_accel(struct fb_info *info)
975 {
976 	struct riva_par *par = info->par;
977 
978 	RIVA_FIFO_FREE(par->riva, Clip, 2);
979 	NV_WR32(&par->riva.Clip->TopLeft, 0, 0x0);
980 	NV_WR32(&par->riva.Clip->WidthHeight, 0,
981 		(info->var.xres_virtual & 0xffff) |
982 		(info->var.yres_virtual << 16));
983 	riva_set_rop_solid(par, 0xcc);
984 	wait_for_idle(par);
985 }
986 
987 /**
988  * riva_get_cmap_len - query current color map length
989  * @var: standard kernel fb changeable data
990  *
991  * DESCRIPTION:
992  * Get current color map length.
993  *
994  * RETURNS:
995  * Length of color map
996  *
997  * CALLED FROM:
998  * rivafb_setcolreg()
999  */
1000 static int riva_get_cmap_len(const struct fb_var_screeninfo *var)
1001 {
1002 	int rc = 256;		/* reasonable default */
1003 
1004 	switch (var->green.length) {
1005 	case 8:
1006 		rc = 256;	/* 256 entries (2^8), 8 bpp and RGB8888 */
1007 		break;
1008 	case 5:
1009 		rc = 32;	/* 32 entries (2^5), 16 bpp, RGB555 */
1010 		break;
1011 	case 6:
1012 		rc = 64;	/* 64 entries (2^6), 16 bpp, RGB565 */
1013 		break;
1014 	default:
1015 		/* should not occur */
1016 		break;
1017 	}
1018 	return rc;
1019 }
1020 
1021 /* ------------------------------------------------------------------------- *
1022  *
1023  * framebuffer operations
1024  *
1025  * ------------------------------------------------------------------------- */
1026 
1027 static int rivafb_open(struct fb_info *info, int user)
1028 {
1029 	struct riva_par *par = info->par;
1030 
1031 	NVTRACE_ENTER();
1032 	mutex_lock(&par->open_lock);
1033 	if (!par->ref_count) {
1034 #ifdef CONFIG_X86
1035 		memset(&par->state, 0, sizeof(struct vgastate));
1036 		par->state.flags = VGA_SAVE_MODE  | VGA_SAVE_FONTS;
1037 		/* save the DAC for Riva128 */
1038 		if (par->riva.Architecture == NV_ARCH_03)
1039 			par->state.flags |= VGA_SAVE_CMAP;
1040 		save_vga(&par->state);
1041 #endif
1042 		/* vgaHWunlock() + riva unlock (0x7F) */
1043 		CRTCout(par, 0x11, 0xFF);
1044 		par->riva.LockUnlock(&par->riva, 0);
1045 
1046 		riva_save_state(par, &par->initial_state);
1047 	}
1048 	par->ref_count++;
1049 	mutex_unlock(&par->open_lock);
1050 	NVTRACE_LEAVE();
1051 	return 0;
1052 }
1053 
1054 static int rivafb_release(struct fb_info *info, int user)
1055 {
1056 	struct riva_par *par = info->par;
1057 
1058 	NVTRACE_ENTER();
1059 	mutex_lock(&par->open_lock);
1060 	if (!par->ref_count) {
1061 		mutex_unlock(&par->open_lock);
1062 		return -EINVAL;
1063 	}
1064 	if (par->ref_count == 1) {
1065 		par->riva.LockUnlock(&par->riva, 0);
1066 		par->riva.LoadStateExt(&par->riva, &par->initial_state.ext);
1067 		riva_load_state(par, &par->initial_state);
1068 #ifdef CONFIG_X86
1069 		restore_vga(&par->state);
1070 #endif
1071 		par->riva.LockUnlock(&par->riva, 1);
1072 	}
1073 	par->ref_count--;
1074 	mutex_unlock(&par->open_lock);
1075 	NVTRACE_LEAVE();
1076 	return 0;
1077 }
1078 
1079 static int rivafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
1080 {
1081 	const struct fb_videomode *mode;
1082 	struct riva_par *par = info->par;
1083 	int nom, den;		/* translating from pixels->bytes */
1084 	int mode_valid = 0;
1085 
1086 	NVTRACE_ENTER();
1087 	switch (var->bits_per_pixel) {
1088 	case 1 ... 8:
1089 		var->red.offset = var->green.offset = var->blue.offset = 0;
1090 		var->red.length = var->green.length = var->blue.length = 8;
1091 		var->bits_per_pixel = 8;
1092 		nom = den = 1;
1093 		break;
1094 	case 9 ... 15:
1095 		var->green.length = 5;
1096 		fallthrough;
1097 	case 16:
1098 		var->bits_per_pixel = 16;
1099 		/* The Riva128 supports RGB555 only */
1100 		if (par->riva.Architecture == NV_ARCH_03)
1101 			var->green.length = 5;
1102 		if (var->green.length == 5) {
1103 			/* 0rrrrrgg gggbbbbb */
1104 			var->red.offset = 10;
1105 			var->green.offset = 5;
1106 			var->blue.offset = 0;
1107 			var->red.length = 5;
1108 			var->green.length = 5;
1109 			var->blue.length = 5;
1110 		} else {
1111 			/* rrrrrggg gggbbbbb */
1112 			var->red.offset = 11;
1113 			var->green.offset = 5;
1114 			var->blue.offset = 0;
1115 			var->red.length = 5;
1116 			var->green.length = 6;
1117 			var->blue.length = 5;
1118 		}
1119 		nom = 2;
1120 		den = 1;
1121 		break;
1122 	case 17 ... 32:
1123 		var->red.length = var->green.length = var->blue.length = 8;
1124 		var->bits_per_pixel = 32;
1125 		var->red.offset = 16;
1126 		var->green.offset = 8;
1127 		var->blue.offset = 0;
1128 		nom = 4;
1129 		den = 1;
1130 		break;
1131 	default:
1132 		printk(KERN_ERR PFX
1133 		       "mode %dx%dx%d rejected...color depth not supported.\n",
1134 		       var->xres, var->yres, var->bits_per_pixel);
1135 		NVTRACE("EXIT, returning -EINVAL\n");
1136 		return -EINVAL;
1137 	}
1138 
1139 	if (!strictmode) {
1140 		if (!info->monspecs.vfmax || !info->monspecs.hfmax ||
1141 		    !info->monspecs.dclkmax || !fb_validate_mode(var, info))
1142 			mode_valid = 1;
1143 	}
1144 
1145 	/* calculate modeline if supported by monitor */
1146 	if (!mode_valid && info->monspecs.gtf) {
1147 		if (!fb_get_mode(FB_MAXTIMINGS, 0, var, info))
1148 			mode_valid = 1;
1149 	}
1150 
1151 	if (!mode_valid) {
1152 		mode = fb_find_best_mode(var, &info->modelist);
1153 		if (mode) {
1154 			riva_update_var(var, mode);
1155 			mode_valid = 1;
1156 		}
1157 	}
1158 
1159 	if (!mode_valid && info->monspecs.modedb_len)
1160 		return -EINVAL;
1161 
1162 	if (var->xres_virtual < var->xres)
1163 		var->xres_virtual = var->xres;
1164 	if (var->yres_virtual <= var->yres)
1165 		var->yres_virtual = -1;
1166 	if (rivafb_do_maximize(info, var, nom, den) < 0)
1167 		return -EINVAL;
1168 
1169 	/* truncate xoffset and yoffset to maximum if too high */
1170 	if (var->xoffset > var->xres_virtual - var->xres)
1171 		var->xoffset = var->xres_virtual - var->xres - 1;
1172 
1173 	if (var->yoffset > var->yres_virtual - var->yres)
1174 		var->yoffset = var->yres_virtual - var->yres - 1;
1175 
1176 	var->red.msb_right =
1177 	    var->green.msb_right =
1178 	    var->blue.msb_right =
1179 	    var->transp.offset = var->transp.length = var->transp.msb_right = 0;
1180 	NVTRACE_LEAVE();
1181 	return 0;
1182 }
1183 
1184 static int rivafb_set_par(struct fb_info *info)
1185 {
1186 	struct riva_par *par = info->par;
1187 	int rc = 0;
1188 
1189 	NVTRACE_ENTER();
1190 	/* vgaHWunlock() + riva unlock (0x7F) */
1191 	CRTCout(par, 0x11, 0xFF);
1192 	par->riva.LockUnlock(&par->riva, 0);
1193 	rc = riva_load_video_mode(info);
1194 	if (rc)
1195 		goto out;
1196 	if(!(info->flags & FBINFO_HWACCEL_DISABLED))
1197 		riva_setup_accel(info);
1198 
1199 	par->cursor_reset = 1;
1200 	info->fix.line_length = (info->var.xres_virtual * (info->var.bits_per_pixel >> 3));
1201 	info->fix.visual = (info->var.bits_per_pixel == 8) ?
1202 				FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
1203 
1204 	if (info->flags & FBINFO_HWACCEL_DISABLED)
1205 		info->pixmap.scan_align = 1;
1206 	else
1207 		info->pixmap.scan_align = 4;
1208 
1209 out:
1210 	NVTRACE_LEAVE();
1211 	return rc;
1212 }
1213 
1214 /**
1215  * rivafb_pan_display
1216  * @var: standard kernel fb changeable data
1217  * @info: pointer to fb_info object containing info for current riva board
1218  *
1219  * DESCRIPTION:
1220  * Pan (or wrap, depending on the `vmode' field) the display using the
1221  * `xoffset' and `yoffset' fields of the `var' structure.
1222  * If the values don't fit, return -EINVAL.
1223  *
1224  * This call looks only at xoffset, yoffset and the FB_VMODE_YWRAP flag
1225  */
1226 static int rivafb_pan_display(struct fb_var_screeninfo *var,
1227 			      struct fb_info *info)
1228 {
1229 	struct riva_par *par = info->par;
1230 	unsigned int base;
1231 
1232 	NVTRACE_ENTER();
1233 	base = var->yoffset * info->fix.line_length + var->xoffset;
1234 	par->riva.SetStartAddress(&par->riva, base);
1235 	NVTRACE_LEAVE();
1236 	return 0;
1237 }
1238 
1239 static int rivafb_blank(int blank, struct fb_info *info)
1240 {
1241 	struct riva_par *par= info->par;
1242 	unsigned char tmp, vesa;
1243 
1244 	tmp = SEQin(par, 0x01) & ~0x20;	/* screen on/off */
1245 	vesa = CRTCin(par, 0x1a) & ~0xc0;	/* sync on/off */
1246 
1247 	NVTRACE_ENTER();
1248 
1249 	if (blank)
1250 		tmp |= 0x20;
1251 
1252 	switch (blank) {
1253 	case FB_BLANK_UNBLANK:
1254 	case FB_BLANK_NORMAL:
1255 		break;
1256 	case FB_BLANK_VSYNC_SUSPEND:
1257 		vesa |= 0x80;
1258 		break;
1259 	case FB_BLANK_HSYNC_SUSPEND:
1260 		vesa |= 0x40;
1261 		break;
1262 	case FB_BLANK_POWERDOWN:
1263 		vesa |= 0xc0;
1264 		break;
1265 	}
1266 
1267 	SEQout(par, 0x01, tmp);
1268 	CRTCout(par, 0x1a, vesa);
1269 
1270 	NVTRACE_LEAVE();
1271 
1272 	return 0;
1273 }
1274 
1275 /**
1276  * rivafb_setcolreg
1277  * @regno: register index
1278  * @red: red component
1279  * @green: green component
1280  * @blue: blue component
1281  * @transp: transparency
1282  * @info: pointer to fb_info object containing info for current riva board
1283  *
1284  * DESCRIPTION:
1285  * Set a single color register. The values supplied have a 16 bit
1286  * magnitude.
1287  *
1288  * RETURNS:
1289  * Return != 0 for invalid regno.
1290  *
1291  * CALLED FROM:
1292  * fbcmap.c:fb_set_cmap()
1293  */
1294 static int rivafb_setcolreg(unsigned regno, unsigned red, unsigned green,
1295 			  unsigned blue, unsigned transp,
1296 			  struct fb_info *info)
1297 {
1298 	struct riva_par *par = info->par;
1299 	RIVA_HW_INST *chip = &par->riva;
1300 	int i;
1301 
1302 	if (regno >= riva_get_cmap_len(&info->var))
1303 			return -EINVAL;
1304 
1305 	if (info->var.grayscale) {
1306 		/* gray = 0.30*R + 0.59*G + 0.11*B */
1307 		red = green = blue =
1308 		    (red * 77 + green * 151 + blue * 28) >> 8;
1309 	}
1310 
1311 	if (regno < 16 && info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
1312 		((u32 *) info->pseudo_palette)[regno] =
1313 			(regno << info->var.red.offset) |
1314 			(regno << info->var.green.offset) |
1315 			(regno << info->var.blue.offset);
1316 		/*
1317 		 * The Riva128 2D engine requires color information in
1318 		 * TrueColor format even if framebuffer is in DirectColor
1319 		 */
1320 		if (par->riva.Architecture == NV_ARCH_03) {
1321 			switch (info->var.bits_per_pixel) {
1322 			case 16:
1323 				par->palette[regno] = ((red & 0xf800) >> 1) |
1324 					((green & 0xf800) >> 6) |
1325 					((blue & 0xf800) >> 11);
1326 				break;
1327 			case 32:
1328 				par->palette[regno] = ((red & 0xff00) << 8) |
1329 					((green & 0xff00)) |
1330 					((blue & 0xff00) >> 8);
1331 				break;
1332 			}
1333 		}
1334 	}
1335 
1336 	switch (info->var.bits_per_pixel) {
1337 	case 8:
1338 		/* "transparent" stuff is completely ignored. */
1339 		riva_wclut(chip, regno, red >> 8, green >> 8, blue >> 8);
1340 		break;
1341 	case 16:
1342 		if (info->var.green.length == 5) {
1343 			for (i = 0; i < 8; i++) {
1344 				riva_wclut(chip, regno*8+i, red >> 8,
1345 					   green >> 8, blue >> 8);
1346 			}
1347 		} else {
1348 			u8 r, g, b;
1349 
1350 			if (regno < 32) {
1351 				for (i = 0; i < 8; i++) {
1352 					riva_wclut(chip, regno*8+i,
1353 						   red >> 8, green >> 8,
1354 						   blue >> 8);
1355 				}
1356 			}
1357 			riva_rclut(chip, regno*4, &r, &g, &b);
1358 			for (i = 0; i < 4; i++)
1359 				riva_wclut(chip, regno*4+i, r,
1360 					   green >> 8, b);
1361 		}
1362 		break;
1363 	case 32:
1364 		riva_wclut(chip, regno, red >> 8, green >> 8, blue >> 8);
1365 		break;
1366 	default:
1367 		/* do nothing */
1368 		break;
1369 	}
1370 	return 0;
1371 }
1372 
1373 /**
1374  * rivafb_fillrect - hardware accelerated color fill function
1375  * @info: pointer to fb_info structure
1376  * @rect: pointer to fb_fillrect structure
1377  *
1378  * DESCRIPTION:
1379  * This function fills up a region of framebuffer memory with a solid
1380  * color with a choice of two different ROP's, copy or invert.
1381  *
1382  * CALLED FROM:
1383  * framebuffer hook
1384  */
1385 static void rivafb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
1386 {
1387 	struct riva_par *par = info->par;
1388 	u_int color, rop = 0;
1389 
1390 	if ((info->flags & FBINFO_HWACCEL_DISABLED)) {
1391 		cfb_fillrect(info, rect);
1392 		return;
1393 	}
1394 
1395 	if (info->var.bits_per_pixel == 8)
1396 		color = rect->color;
1397 	else {
1398 		if (par->riva.Architecture != NV_ARCH_03)
1399 			color = ((u32 *)info->pseudo_palette)[rect->color];
1400 		else
1401 			color = par->palette[rect->color];
1402 	}
1403 
1404 	switch (rect->rop) {
1405 	case ROP_XOR:
1406 		rop = 0x66;
1407 		break;
1408 	case ROP_COPY:
1409 	default:
1410 		rop = 0xCC;
1411 		break;
1412 	}
1413 
1414 	riva_set_rop_solid(par, rop);
1415 
1416 	RIVA_FIFO_FREE(par->riva, Bitmap, 1);
1417 	NV_WR32(&par->riva.Bitmap->Color1A, 0, color);
1418 
1419 	RIVA_FIFO_FREE(par->riva, Bitmap, 2);
1420 	NV_WR32(&par->riva.Bitmap->UnclippedRectangle[0].TopLeft, 0,
1421 		(rect->dx << 16) | rect->dy);
1422 	mb();
1423 	NV_WR32(&par->riva.Bitmap->UnclippedRectangle[0].WidthHeight, 0,
1424 		(rect->width << 16) | rect->height);
1425 	mb();
1426 	riva_set_rop_solid(par, 0xcc);
1427 
1428 }
1429 
1430 /**
1431  * rivafb_copyarea - hardware accelerated blit function
1432  * @info: pointer to fb_info structure
1433  * @region: pointer to fb_copyarea structure
1434  *
1435  * DESCRIPTION:
1436  * This copies an area of pixels from one location to another
1437  *
1438  * CALLED FROM:
1439  * framebuffer hook
1440  */
1441 static void rivafb_copyarea(struct fb_info *info, const struct fb_copyarea *region)
1442 {
1443 	struct riva_par *par = info->par;
1444 
1445 	if ((info->flags & FBINFO_HWACCEL_DISABLED)) {
1446 		cfb_copyarea(info, region);
1447 		return;
1448 	}
1449 
1450 	RIVA_FIFO_FREE(par->riva, Blt, 3);
1451 	NV_WR32(&par->riva.Blt->TopLeftSrc, 0,
1452 		(region->sy << 16) | region->sx);
1453 	NV_WR32(&par->riva.Blt->TopLeftDst, 0,
1454 		(region->dy << 16) | region->dx);
1455 	mb();
1456 	NV_WR32(&par->riva.Blt->WidthHeight, 0,
1457 		(region->height << 16) | region->width);
1458 	mb();
1459 }
1460 
1461 static inline void convert_bgcolor_16(u32 *col)
1462 {
1463 	*col = ((*col & 0x0000F800) << 8)
1464 		| ((*col & 0x00007E0) << 5)
1465 		| ((*col & 0x0000001F) << 3)
1466 		|	   0xFF000000;
1467 	mb();
1468 }
1469 
1470 /**
1471  * rivafb_imageblit: hardware accelerated color expand function
1472  * @info: pointer to fb_info structure
1473  * @image: pointer to fb_image structure
1474  *
1475  * DESCRIPTION:
1476  * If the source is a monochrome bitmap, the function fills up a a region
1477  * of framebuffer memory with pixels whose color is determined by the bit
1478  * setting of the bitmap, 1 - foreground, 0 - background.
1479  *
1480  * If the source is not a monochrome bitmap, color expansion is not done.
1481  * In this case, it is channeled to a software function.
1482  *
1483  * CALLED FROM:
1484  * framebuffer hook
1485  */
1486 static void rivafb_imageblit(struct fb_info *info,
1487 			     const struct fb_image *image)
1488 {
1489 	struct riva_par *par = info->par;
1490 	u32 fgx = 0, bgx = 0, width, tmp;
1491 	u8 *cdat = (u8 *) image->data;
1492 	volatile u32 __iomem *d;
1493 	int i, size;
1494 
1495 	if ((info->flags & FBINFO_HWACCEL_DISABLED) || image->depth != 1) {
1496 		cfb_imageblit(info, image);
1497 		return;
1498 	}
1499 
1500 	switch (info->var.bits_per_pixel) {
1501 	case 8:
1502 		fgx = image->fg_color;
1503 		bgx = image->bg_color;
1504 		break;
1505 	case 16:
1506 	case 32:
1507 		if (par->riva.Architecture != NV_ARCH_03) {
1508 			fgx = ((u32 *)info->pseudo_palette)[image->fg_color];
1509 			bgx = ((u32 *)info->pseudo_palette)[image->bg_color];
1510 		} else {
1511 			fgx = par->palette[image->fg_color];
1512 			bgx = par->palette[image->bg_color];
1513 		}
1514 		if (info->var.green.length == 6)
1515 			convert_bgcolor_16(&bgx);
1516 		break;
1517 	}
1518 
1519 	RIVA_FIFO_FREE(par->riva, Bitmap, 7);
1520 	NV_WR32(&par->riva.Bitmap->ClipE.TopLeft, 0,
1521 		(image->dy << 16) | (image->dx & 0xFFFF));
1522 	NV_WR32(&par->riva.Bitmap->ClipE.BottomRight, 0,
1523 		(((image->dy + image->height) << 16) |
1524 		 ((image->dx + image->width) & 0xffff)));
1525 	NV_WR32(&par->riva.Bitmap->Color0E, 0, bgx);
1526 	NV_WR32(&par->riva.Bitmap->Color1E, 0, fgx);
1527 	NV_WR32(&par->riva.Bitmap->WidthHeightInE, 0,
1528 		(image->height << 16) | ((image->width + 31) & ~31));
1529 	NV_WR32(&par->riva.Bitmap->WidthHeightOutE, 0,
1530 		(image->height << 16) | ((image->width + 31) & ~31));
1531 	NV_WR32(&par->riva.Bitmap->PointE, 0,
1532 		(image->dy << 16) | (image->dx & 0xFFFF));
1533 
1534 	d = &par->riva.Bitmap->MonochromeData01E;
1535 
1536 	width = (image->width + 31)/32;
1537 	size = width * image->height;
1538 	while (size >= 16) {
1539 		RIVA_FIFO_FREE(par->riva, Bitmap, 16);
1540 		for (i = 0; i < 16; i++) {
1541 			tmp = *((u32 *)cdat);
1542 			cdat = (u8 *)((u32 *)cdat + 1);
1543 			reverse_order(&tmp);
1544 			NV_WR32(d, i*4, tmp);
1545 		}
1546 		size -= 16;
1547 	}
1548 	if (size) {
1549 		RIVA_FIFO_FREE(par->riva, Bitmap, size);
1550 		for (i = 0; i < size; i++) {
1551 			tmp = *((u32 *) cdat);
1552 			cdat = (u8 *)((u32 *)cdat + 1);
1553 			reverse_order(&tmp);
1554 			NV_WR32(d, i*4, tmp);
1555 		}
1556 	}
1557 }
1558 
1559 /**
1560  * rivafb_cursor - hardware cursor function
1561  * @info: pointer to info structure
1562  * @cursor: pointer to fbcursor structure
1563  *
1564  * DESCRIPTION:
1565  * A cursor function that supports displaying a cursor image via hardware.
1566  * Within the kernel, copy and invert rops are supported.  If exported
1567  * to user space, only the copy rop will be supported.
1568  *
1569  * CALLED FROM
1570  * framebuffer hook
1571  */
1572 static int rivafb_cursor(struct fb_info *info, struct fb_cursor *cursor)
1573 {
1574 	struct riva_par *par = info->par;
1575 	u8 data[MAX_CURS * MAX_CURS/8];
1576 	int i, set = cursor->set;
1577 	u16 fg, bg;
1578 
1579 	if (cursor->image.width > MAX_CURS || cursor->image.height > MAX_CURS)
1580 		return -ENXIO;
1581 
1582 	par->riva.ShowHideCursor(&par->riva, 0);
1583 
1584 	if (par->cursor_reset) {
1585 		set = FB_CUR_SETALL;
1586 		par->cursor_reset = 0;
1587 	}
1588 
1589 	if (set & FB_CUR_SETSIZE)
1590 		memset_io(par->riva.CURSOR, 0, MAX_CURS * MAX_CURS * 2);
1591 
1592 	if (set & FB_CUR_SETPOS) {
1593 		u32 xx, yy, temp;
1594 
1595 		yy = cursor->image.dy - info->var.yoffset;
1596 		xx = cursor->image.dx - info->var.xoffset;
1597 		temp = xx & 0xFFFF;
1598 		temp |= yy << 16;
1599 
1600 		NV_WR32(par->riva.PRAMDAC, 0x0000300, temp);
1601 	}
1602 
1603 
1604 	if (set & (FB_CUR_SETSHAPE | FB_CUR_SETCMAP | FB_CUR_SETIMAGE)) {
1605 		u32 bg_idx = cursor->image.bg_color;
1606 		u32 fg_idx = cursor->image.fg_color;
1607 		u32 s_pitch = (cursor->image.width+7) >> 3;
1608 		u32 d_pitch = MAX_CURS/8;
1609 		u8 *dat = (u8 *) cursor->image.data;
1610 		u8 *msk = (u8 *) cursor->mask;
1611 		u8 *src;
1612 
1613 		src = kmalloc_array(s_pitch, cursor->image.height, GFP_ATOMIC);
1614 
1615 		if (src) {
1616 			switch (cursor->rop) {
1617 			case ROP_XOR:
1618 				for (i = 0; i < s_pitch * cursor->image.height; i++)
1619 					src[i] = dat[i] ^ msk[i];
1620 				break;
1621 			case ROP_COPY:
1622 			default:
1623 				for (i = 0; i < s_pitch * cursor->image.height; i++)
1624 					src[i] = dat[i] & msk[i];
1625 				break;
1626 			}
1627 
1628 			fb_pad_aligned_buffer(data, d_pitch, src, s_pitch,
1629 						cursor->image.height);
1630 
1631 			bg = ((info->cmap.red[bg_idx] & 0xf8) << 7) |
1632 				((info->cmap.green[bg_idx] & 0xf8) << 2) |
1633 				((info->cmap.blue[bg_idx] & 0xf8) >> 3) |
1634 				1 << 15;
1635 
1636 			fg = ((info->cmap.red[fg_idx] & 0xf8) << 7) |
1637 				((info->cmap.green[fg_idx] & 0xf8) << 2) |
1638 				((info->cmap.blue[fg_idx] & 0xf8) >> 3) |
1639 				1 << 15;
1640 
1641 			par->riva.LockUnlock(&par->riva, 0);
1642 
1643 			rivafb_load_cursor_image(par, data, bg, fg,
1644 						 cursor->image.width,
1645 						 cursor->image.height);
1646 			kfree(src);
1647 		}
1648 	}
1649 
1650 	if (cursor->enable)
1651 		par->riva.ShowHideCursor(&par->riva, 1);
1652 
1653 	return 0;
1654 }
1655 
1656 static int rivafb_sync(struct fb_info *info)
1657 {
1658 	struct riva_par *par = info->par;
1659 
1660 	wait_for_idle(par);
1661 	return 0;
1662 }
1663 
1664 /* ------------------------------------------------------------------------- *
1665  *
1666  * initialization helper functions
1667  *
1668  * ------------------------------------------------------------------------- */
1669 
1670 /* kernel interface */
1671 static const struct fb_ops riva_fb_ops = {
1672 	.owner 		= THIS_MODULE,
1673 	.fb_open	= rivafb_open,
1674 	.fb_release	= rivafb_release,
1675 	.fb_check_var 	= rivafb_check_var,
1676 	.fb_set_par 	= rivafb_set_par,
1677 	.fb_setcolreg 	= rivafb_setcolreg,
1678 	.fb_pan_display	= rivafb_pan_display,
1679 	.fb_blank 	= rivafb_blank,
1680 	.fb_fillrect 	= rivafb_fillrect,
1681 	.fb_copyarea 	= rivafb_copyarea,
1682 	.fb_imageblit 	= rivafb_imageblit,
1683 	.fb_cursor	= rivafb_cursor,
1684 	.fb_sync 	= rivafb_sync,
1685 };
1686 
1687 static int riva_set_fbinfo(struct fb_info *info)
1688 {
1689 	unsigned int cmap_len;
1690 	struct riva_par *par = info->par;
1691 
1692 	NVTRACE_ENTER();
1693 	info->flags = FBINFO_DEFAULT
1694 		    | FBINFO_HWACCEL_XPAN
1695 		    | FBINFO_HWACCEL_YPAN
1696 		    | FBINFO_HWACCEL_COPYAREA
1697 		    | FBINFO_HWACCEL_FILLRECT
1698 	            | FBINFO_HWACCEL_IMAGEBLIT;
1699 
1700 	/* Accel seems to not work properly on NV30 yet...*/
1701 	if ((par->riva.Architecture == NV_ARCH_30) || noaccel) {
1702 	    	printk(KERN_DEBUG PFX "disabling acceleration\n");
1703   		info->flags |= FBINFO_HWACCEL_DISABLED;
1704 	}
1705 
1706 	info->var = rivafb_default_var;
1707 	info->fix.visual = (info->var.bits_per_pixel == 8) ?
1708 				FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
1709 
1710 	info->pseudo_palette = par->pseudo_palette;
1711 
1712 	cmap_len = riva_get_cmap_len(&info->var);
1713 	fb_alloc_cmap(&info->cmap, cmap_len, 0);
1714 
1715 	info->pixmap.size = 8 * 1024;
1716 	info->pixmap.buf_align = 4;
1717 	info->pixmap.access_align = 32;
1718 	info->pixmap.flags = FB_PIXMAP_SYSTEM;
1719 	info->var.yres_virtual = -1;
1720 	NVTRACE_LEAVE();
1721 	return (rivafb_check_var(&info->var, info));
1722 }
1723 
1724 static int riva_get_EDID_OF(struct fb_info *info, struct pci_dev *pd)
1725 {
1726 	struct riva_par *par = info->par;
1727 	struct device_node *dp;
1728 	const unsigned char *pedid = NULL;
1729 	const unsigned char *disptype = NULL;
1730 	static char *propnames[] = {
1731 		"DFP,EDID", "LCD,EDID", "EDID", "EDID1", "EDID,B", "EDID,A", NULL };
1732 	int i;
1733 
1734 	NVTRACE_ENTER();
1735 	dp = pci_device_to_OF_node(pd);
1736 	for (; dp != NULL; dp = dp->child) {
1737 		disptype = of_get_property(dp, "display-type", NULL);
1738 		if (disptype == NULL)
1739 			continue;
1740 		if (strncmp(disptype, "LCD", 3) != 0)
1741 			continue;
1742 		for (i = 0; propnames[i] != NULL; ++i) {
1743 			pedid = of_get_property(dp, propnames[i], NULL);
1744 			if (pedid != NULL) {
1745 				par->EDID = (unsigned char *)pedid;
1746 				NVTRACE("LCD found.\n");
1747 				return 1;
1748 			}
1749 		}
1750 	}
1751 	NVTRACE_LEAVE();
1752 	return 0;
1753 }
1754 
1755 #if defined(CONFIG_FB_RIVA_I2C)
1756 static int riva_get_EDID_i2c(struct fb_info *info)
1757 {
1758 	struct riva_par *par = info->par;
1759 	struct fb_var_screeninfo var;
1760 	int i;
1761 
1762 	NVTRACE_ENTER();
1763 	par->riva.LockUnlock(&par->riva, 0);
1764 	riva_create_i2c_busses(par);
1765 	for (i = 0; i < 3; i++) {
1766 		if (!par->chan[i].par)
1767 			continue;
1768 		riva_probe_i2c_connector(par, i, &par->EDID);
1769 		if (par->EDID && !fb_parse_edid(par->EDID, &var)) {
1770 			printk(PFX "Found EDID Block from BUS %i\n", i);
1771 			break;
1772 		}
1773 	}
1774 
1775 	NVTRACE_LEAVE();
1776 	return (par->EDID) ? 1 : 0;
1777 }
1778 #endif /* CONFIG_FB_RIVA_I2C */
1779 
1780 static void riva_update_default_var(struct fb_var_screeninfo *var,
1781 				    struct fb_info *info)
1782 {
1783 	struct fb_monspecs *specs = &info->monspecs;
1784 	struct fb_videomode modedb;
1785 
1786 	NVTRACE_ENTER();
1787 	/* respect mode options */
1788 	if (mode_option) {
1789 		fb_find_mode(var, info, mode_option,
1790 			     specs->modedb, specs->modedb_len,
1791 			     NULL, 8);
1792 	} else if (specs->modedb != NULL) {
1793 		/* get first mode in database as fallback */
1794 		modedb = specs->modedb[0];
1795 		/* get preferred timing */
1796 		if (info->monspecs.misc & FB_MISC_1ST_DETAIL) {
1797 			int i;
1798 
1799 			for (i = 0; i < specs->modedb_len; i++) {
1800 				if (specs->modedb[i].flag & FB_MODE_IS_FIRST) {
1801 					modedb = specs->modedb[i];
1802 					break;
1803 				}
1804 			}
1805 		}
1806 		var->bits_per_pixel = 8;
1807 		riva_update_var(var, &modedb);
1808 	}
1809 	NVTRACE_LEAVE();
1810 }
1811 
1812 
1813 static void riva_get_EDID(struct fb_info *info, struct pci_dev *pdev)
1814 {
1815 	NVTRACE_ENTER();
1816 	if (riva_get_EDID_OF(info, pdev)) {
1817 		NVTRACE_LEAVE();
1818 		return;
1819 	}
1820 	if (IS_ENABLED(CONFIG_OF))
1821 		printk(PFX "could not retrieve EDID from OF\n");
1822 #if defined(CONFIG_FB_RIVA_I2C)
1823 	if (!riva_get_EDID_i2c(info))
1824 		printk(PFX "could not retrieve EDID from DDC/I2C\n");
1825 #endif
1826 	NVTRACE_LEAVE();
1827 }
1828 
1829 
1830 static void riva_get_edidinfo(struct fb_info *info)
1831 {
1832 	struct fb_var_screeninfo *var = &rivafb_default_var;
1833 	struct riva_par *par = info->par;
1834 
1835 	fb_edid_to_monspecs(par->EDID, &info->monspecs);
1836 	fb_videomode_to_modelist(info->monspecs.modedb, info->monspecs.modedb_len,
1837 				 &info->modelist);
1838 	riva_update_default_var(var, info);
1839 
1840 	/* if user specified flatpanel, we respect that */
1841 	if (info->monspecs.input & FB_DISP_DDI)
1842 		par->FlatPanel = 1;
1843 }
1844 
1845 /* ------------------------------------------------------------------------- *
1846  *
1847  * PCI bus
1848  *
1849  * ------------------------------------------------------------------------- */
1850 
1851 static u32 riva_get_arch(struct pci_dev *pd)
1852 {
1853     	u32 arch = 0;
1854 
1855 	switch (pd->device & 0x0ff0) {
1856 		case 0x0100:   /* GeForce 256 */
1857 		case 0x0110:   /* GeForce2 MX */
1858 		case 0x0150:   /* GeForce2 */
1859 		case 0x0170:   /* GeForce4 MX */
1860 		case 0x0180:   /* GeForce4 MX (8x AGP) */
1861 		case 0x01A0:   /* nForce */
1862 		case 0x01F0:   /* nForce2 */
1863 		     arch =  NV_ARCH_10;
1864 		     break;
1865 		case 0x0200:   /* GeForce3 */
1866 		case 0x0250:   /* GeForce4 Ti */
1867 		case 0x0280:   /* GeForce4 Ti (8x AGP) */
1868 		     arch =  NV_ARCH_20;
1869 		     break;
1870 		case 0x0300:   /* GeForceFX 5800 */
1871 		case 0x0310:   /* GeForceFX 5600 */
1872 		case 0x0320:   /* GeForceFX 5200 */
1873 		case 0x0330:   /* GeForceFX 5900 */
1874 		case 0x0340:   /* GeForceFX 5700 */
1875 		     arch =  NV_ARCH_30;
1876 		     break;
1877 		case 0x0020:   /* TNT, TNT2 */
1878 		     arch =  NV_ARCH_04;
1879 		     break;
1880 		case 0x0010:   /* Riva128 */
1881 		     arch =  NV_ARCH_03;
1882 		     break;
1883 		default:   /* unknown architecture */
1884 		     break;
1885 	}
1886 	return arch;
1887 }
1888 
1889 static int rivafb_probe(struct pci_dev *pd, const struct pci_device_id *ent)
1890 {
1891 	struct riva_par *default_par;
1892 	struct fb_info *info;
1893 	int ret;
1894 
1895 	NVTRACE_ENTER();
1896 	assert(pd != NULL);
1897 
1898 	info = framebuffer_alloc(sizeof(struct riva_par), &pd->dev);
1899 	if (!info) {
1900 		ret = -ENOMEM;
1901 		goto err_ret;
1902 	}
1903 	default_par = info->par;
1904 	default_par->pdev = pd;
1905 
1906 	info->pixmap.addr = kzalloc(8 * 1024, GFP_KERNEL);
1907 	if (info->pixmap.addr == NULL) {
1908 	    	ret = -ENOMEM;
1909 		goto err_framebuffer_release;
1910 	}
1911 
1912 	ret = pci_enable_device(pd);
1913 	if (ret < 0) {
1914 		printk(KERN_ERR PFX "cannot enable PCI device\n");
1915 		goto err_free_pixmap;
1916 	}
1917 
1918 	ret = pci_request_regions(pd, "rivafb");
1919 	if (ret < 0) {
1920 		printk(KERN_ERR PFX "cannot request PCI regions\n");
1921 		goto err_disable_device;
1922 	}
1923 
1924 	mutex_init(&default_par->open_lock);
1925 	default_par->riva.Architecture = riva_get_arch(pd);
1926 
1927 	default_par->Chipset = (pd->vendor << 16) | pd->device;
1928 	printk(KERN_INFO PFX "nVidia device/chipset %X\n",default_par->Chipset);
1929 
1930 	if(default_par->riva.Architecture == 0) {
1931 		printk(KERN_ERR PFX "unknown NV_ARCH\n");
1932 		ret=-ENODEV;
1933 		goto err_release_region;
1934 	}
1935 	if(default_par->riva.Architecture == NV_ARCH_10 ||
1936 	   default_par->riva.Architecture == NV_ARCH_20 ||
1937 	   default_par->riva.Architecture == NV_ARCH_30) {
1938 		sprintf(rivafb_fix.id, "NV%x", (pd->device & 0x0ff0) >> 4);
1939 	} else {
1940 		sprintf(rivafb_fix.id, "NV%x", default_par->riva.Architecture);
1941 	}
1942 
1943 	default_par->FlatPanel = flatpanel;
1944 	if (flatpanel == 1)
1945 		printk(KERN_INFO PFX "flatpanel support enabled\n");
1946 	default_par->forceCRTC = forceCRTC;
1947 
1948 	rivafb_fix.mmio_len = pci_resource_len(pd, 0);
1949 	rivafb_fix.smem_len = pci_resource_len(pd, 1);
1950 
1951 	{
1952 		/* enable IO and mem if not already done */
1953 		unsigned short cmd;
1954 
1955 		pci_read_config_word(pd, PCI_COMMAND, &cmd);
1956 		cmd |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
1957 		pci_write_config_word(pd, PCI_COMMAND, cmd);
1958 	}
1959 
1960 	rivafb_fix.mmio_start = pci_resource_start(pd, 0);
1961 	rivafb_fix.smem_start = pci_resource_start(pd, 1);
1962 
1963 	default_par->ctrl_base = ioremap(rivafb_fix.mmio_start,
1964 					 rivafb_fix.mmio_len);
1965 	if (!default_par->ctrl_base) {
1966 		printk(KERN_ERR PFX "cannot ioremap MMIO base\n");
1967 		ret = -EIO;
1968 		goto err_release_region;
1969 	}
1970 
1971 	switch (default_par->riva.Architecture) {
1972 	case NV_ARCH_03:
1973 		/* Riva128's PRAMIN is in the "framebuffer" space
1974 		 * Since these cards were never made with more than 8 megabytes
1975 		 * we can safely allocate this separately.
1976 		 */
1977 		default_par->riva.PRAMIN = ioremap(rivafb_fix.smem_start + 0x00C00000, 0x00008000);
1978 		if (!default_par->riva.PRAMIN) {
1979 			printk(KERN_ERR PFX "cannot ioremap PRAMIN region\n");
1980 			ret = -EIO;
1981 			goto err_iounmap_ctrl_base;
1982 		}
1983 		break;
1984 	case NV_ARCH_04:
1985 	case NV_ARCH_10:
1986 	case NV_ARCH_20:
1987 	case NV_ARCH_30:
1988 		default_par->riva.PCRTC0 =
1989 			(u32 __iomem *)(default_par->ctrl_base + 0x00600000);
1990 		default_par->riva.PRAMIN =
1991 			(u32 __iomem *)(default_par->ctrl_base + 0x00710000);
1992 		break;
1993 	}
1994 	riva_common_setup(default_par);
1995 
1996 	if (default_par->riva.Architecture == NV_ARCH_03) {
1997 		default_par->riva.PCRTC = default_par->riva.PCRTC0
1998 		                        = default_par->riva.PGRAPH;
1999 	}
2000 
2001 	rivafb_fix.smem_len = riva_get_memlen(default_par) * 1024;
2002 	default_par->dclk_max = riva_get_maxdclk(default_par) * 1000;
2003 	info->screen_base = ioremap_wc(rivafb_fix.smem_start,
2004 				       rivafb_fix.smem_len);
2005 	if (!info->screen_base) {
2006 		printk(KERN_ERR PFX "cannot ioremap FB base\n");
2007 		ret = -EIO;
2008 		goto err_iounmap_pramin;
2009 	}
2010 
2011 	if (!nomtrr)
2012 		default_par->wc_cookie =
2013 			arch_phys_wc_add(rivafb_fix.smem_start,
2014 					 rivafb_fix.smem_len);
2015 
2016 	info->fbops = &riva_fb_ops;
2017 	info->fix = rivafb_fix;
2018 	riva_get_EDID(info, pd);
2019 	riva_get_edidinfo(info);
2020 
2021 	ret=riva_set_fbinfo(info);
2022 	if (ret < 0) {
2023 		printk(KERN_ERR PFX "error setting initial video mode\n");
2024 		goto err_iounmap_screen_base;
2025 	}
2026 
2027 	fb_destroy_modedb(info->monspecs.modedb);
2028 	info->monspecs.modedb = NULL;
2029 
2030 	pci_set_drvdata(pd, info);
2031 
2032 	if (backlight)
2033 		riva_bl_init(info->par);
2034 
2035 	ret = register_framebuffer(info);
2036 	if (ret < 0) {
2037 		printk(KERN_ERR PFX
2038 			"error registering riva framebuffer\n");
2039 		goto err_iounmap_screen_base;
2040 	}
2041 
2042 	printk(KERN_INFO PFX
2043 		"PCI nVidia %s framebuffer ver %s (%dMB @ 0x%lX)\n",
2044 		info->fix.id,
2045 		RIVAFB_VERSION,
2046 		info->fix.smem_len / (1024 * 1024),
2047 		info->fix.smem_start);
2048 
2049 	NVTRACE_LEAVE();
2050 	return 0;
2051 
2052 err_iounmap_screen_base:
2053 #ifdef CONFIG_FB_RIVA_I2C
2054 	riva_delete_i2c_busses(info->par);
2055 #endif
2056 	iounmap(info->screen_base);
2057 err_iounmap_pramin:
2058 	if (default_par->riva.Architecture == NV_ARCH_03)
2059 		iounmap(default_par->riva.PRAMIN);
2060 err_iounmap_ctrl_base:
2061 	iounmap(default_par->ctrl_base);
2062 err_release_region:
2063 	pci_release_regions(pd);
2064 err_disable_device:
2065 err_free_pixmap:
2066 	kfree(info->pixmap.addr);
2067 err_framebuffer_release:
2068 	framebuffer_release(info);
2069 err_ret:
2070 	return ret;
2071 }
2072 
2073 static void rivafb_remove(struct pci_dev *pd)
2074 {
2075 	struct fb_info *info = pci_get_drvdata(pd);
2076 	struct riva_par *par = info->par;
2077 
2078 	NVTRACE_ENTER();
2079 
2080 #ifdef CONFIG_FB_RIVA_I2C
2081 	riva_delete_i2c_busses(par);
2082 	kfree(par->EDID);
2083 #endif
2084 
2085 	unregister_framebuffer(info);
2086 
2087 	riva_bl_exit(info);
2088 	arch_phys_wc_del(par->wc_cookie);
2089 	iounmap(par->ctrl_base);
2090 	iounmap(info->screen_base);
2091 	if (par->riva.Architecture == NV_ARCH_03)
2092 		iounmap(par->riva.PRAMIN);
2093 	pci_release_regions(pd);
2094 	kfree(info->pixmap.addr);
2095 	framebuffer_release(info);
2096 	NVTRACE_LEAVE();
2097 }
2098 
2099 /* ------------------------------------------------------------------------- *
2100  *
2101  * initialization
2102  *
2103  * ------------------------------------------------------------------------- */
2104 
2105 #ifndef MODULE
2106 static int rivafb_setup(char *options)
2107 {
2108 	char *this_opt;
2109 
2110 	NVTRACE_ENTER();
2111 	if (!options || !*options)
2112 		return 0;
2113 
2114 	while ((this_opt = strsep(&options, ",")) != NULL) {
2115 		if (!strncmp(this_opt, "forceCRTC", 9)) {
2116 			char *p;
2117 
2118 			p = this_opt + 9;
2119 			if (!*p || !*(++p)) continue;
2120 			forceCRTC = *p - '0';
2121 			if (forceCRTC < 0 || forceCRTC > 1)
2122 				forceCRTC = -1;
2123 		} else if (!strncmp(this_opt, "flatpanel", 9)) {
2124 			flatpanel = 1;
2125 		} else if (!strncmp(this_opt, "backlight:", 10)) {
2126 			backlight = simple_strtoul(this_opt+10, NULL, 0);
2127 		} else if (!strncmp(this_opt, "nomtrr", 6)) {
2128 			nomtrr = 1;
2129 		} else if (!strncmp(this_opt, "strictmode", 10)) {
2130 			strictmode = 1;
2131 		} else if (!strncmp(this_opt, "noaccel", 7)) {
2132 			noaccel = 1;
2133 		} else
2134 			mode_option = this_opt;
2135 	}
2136 	NVTRACE_LEAVE();
2137 	return 0;
2138 }
2139 #endif /* !MODULE */
2140 
2141 static struct pci_driver rivafb_driver = {
2142 	.name		= "rivafb",
2143 	.id_table	= rivafb_pci_tbl,
2144 	.probe		= rivafb_probe,
2145 	.remove		= rivafb_remove,
2146 };
2147 
2148 
2149 
2150 /* ------------------------------------------------------------------------- *
2151  *
2152  * modularization
2153  *
2154  * ------------------------------------------------------------------------- */
2155 
2156 static int rivafb_init(void)
2157 {
2158 #ifndef MODULE
2159 	char *option = NULL;
2160 
2161 	if (fb_get_options("rivafb", &option))
2162 		return -ENODEV;
2163 	rivafb_setup(option);
2164 #endif
2165 	return pci_register_driver(&rivafb_driver);
2166 }
2167 
2168 
2169 module_init(rivafb_init);
2170 
2171 static void __exit rivafb_exit(void)
2172 {
2173 	pci_unregister_driver(&rivafb_driver);
2174 }
2175 
2176 module_exit(rivafb_exit);
2177 
2178 module_param(noaccel, bool, 0);
2179 MODULE_PARM_DESC(noaccel, "bool: disable acceleration");
2180 module_param(flatpanel, int, 0);
2181 MODULE_PARM_DESC(flatpanel, "Enables experimental flat panel support for some chipsets. (0 or 1=enabled) (default=0)");
2182 module_param(forceCRTC, int, 0);
2183 MODULE_PARM_DESC(forceCRTC, "Forces usage of a particular CRTC in case autodetection fails. (0 or 1) (default=autodetect)");
2184 module_param(nomtrr, bool, 0);
2185 MODULE_PARM_DESC(nomtrr, "Disables MTRR support (0 or 1=disabled) (default=0)");
2186 module_param(strictmode, bool, 0);
2187 MODULE_PARM_DESC(strictmode, "Only use video modes from EDID");
2188 
2189 MODULE_AUTHOR("Ani Joshi, maintainer");
2190 MODULE_DESCRIPTION("Framebuffer driver for nVidia Riva 128, TNT, TNT2, and the GeForce series");
2191 MODULE_LICENSE("GPL");
2192