1 /* 2 * linux/drivers/video/pxafb.c 3 * 4 * Copyright (C) 1999 Eric A. Thomas. 5 * Copyright (C) 2004 Jean-Frederic Clere. 6 * Copyright (C) 2004 Ian Campbell. 7 * Copyright (C) 2004 Jeff Lackey. 8 * Based on sa1100fb.c Copyright (C) 1999 Eric A. Thomas 9 * which in turn is 10 * Based on acornfb.c Copyright (C) Russell King. 11 * 12 * This file is subject to the terms and conditions of the GNU General Public 13 * License. See the file COPYING in the main directory of this archive for 14 * more details. 15 * 16 * Intel PXA250/210 LCD Controller Frame Buffer Driver 17 * 18 * Please direct your questions and comments on this driver to the following 19 * email address: 20 * 21 * linux-arm-kernel@lists.arm.linux.org.uk 22 * 23 * Add support for overlay1 and overlay2 based on pxafb_overlay.c: 24 * 25 * Copyright (C) 2004, Intel Corporation 26 * 27 * 2003/08/27: <yu.tang@intel.com> 28 * 2004/03/10: <stanley.cai@intel.com> 29 * 2004/10/28: <yan.yin@intel.com> 30 * 31 * Copyright (C) 2006-2008 Marvell International Ltd. 32 * All Rights Reserved 33 */ 34 35 #include <linux/module.h> 36 #include <linux/moduleparam.h> 37 #include <linux/kernel.h> 38 #include <linux/sched.h> 39 #include <linux/errno.h> 40 #include <linux/string.h> 41 #include <linux/interrupt.h> 42 #include <linux/slab.h> 43 #include <linux/mm.h> 44 #include <linux/fb.h> 45 #include <linux/delay.h> 46 #include <linux/init.h> 47 #include <linux/ioport.h> 48 #include <linux/cpufreq.h> 49 #include <linux/platform_device.h> 50 #include <linux/dma-mapping.h> 51 #include <linux/clk.h> 52 #include <linux/err.h> 53 #include <linux/completion.h> 54 #include <linux/mutex.h> 55 #include <linux/kthread.h> 56 #include <linux/freezer.h> 57 #include <linux/console.h> 58 #include <linux/of_graph.h> 59 #include <video/of_display_timing.h> 60 #include <video/videomode.h> 61 62 #include <mach/hardware.h> 63 #include <asm/io.h> 64 #include <asm/irq.h> 65 #include <asm/div64.h> 66 #include <mach/bitfield.h> 67 #include <linux/platform_data/video-pxafb.h> 68 69 /* 70 * Complain if VAR is out of range. 71 */ 72 #define DEBUG_VAR 1 73 74 #include "pxafb.h" 75 76 /* Bits which should not be set in machine configuration structures */ 77 #define LCCR0_INVALID_CONFIG_MASK (LCCR0_OUM | LCCR0_BM | LCCR0_QDM |\ 78 LCCR0_DIS | LCCR0_EFM | LCCR0_IUM |\ 79 LCCR0_SFM | LCCR0_LDM | LCCR0_ENB) 80 81 #define LCCR3_INVALID_CONFIG_MASK (LCCR3_HSP | LCCR3_VSP |\ 82 LCCR3_PCD | LCCR3_BPP(0xf)) 83 84 static int pxafb_activate_var(struct fb_var_screeninfo *var, 85 struct pxafb_info *); 86 static void set_ctrlr_state(struct pxafb_info *fbi, u_int state); 87 static void setup_base_frame(struct pxafb_info *fbi, 88 struct fb_var_screeninfo *var, int branch); 89 static int setup_frame_dma(struct pxafb_info *fbi, int dma, int pal, 90 unsigned long offset, size_t size); 91 92 static unsigned long video_mem_size = 0; 93 94 static inline unsigned long 95 lcd_readl(struct pxafb_info *fbi, unsigned int off) 96 { 97 return __raw_readl(fbi->mmio_base + off); 98 } 99 100 static inline void 101 lcd_writel(struct pxafb_info *fbi, unsigned int off, unsigned long val) 102 { 103 __raw_writel(val, fbi->mmio_base + off); 104 } 105 106 static inline void pxafb_schedule_work(struct pxafb_info *fbi, u_int state) 107 { 108 unsigned long flags; 109 110 local_irq_save(flags); 111 /* 112 * We need to handle two requests being made at the same time. 113 * There are two important cases: 114 * 1. When we are changing VT (C_REENABLE) while unblanking 115 * (C_ENABLE) We must perform the unblanking, which will 116 * do our REENABLE for us. 117 * 2. When we are blanking, but immediately unblank before 118 * we have blanked. We do the "REENABLE" thing here as 119 * well, just to be sure. 120 */ 121 if (fbi->task_state == C_ENABLE && state == C_REENABLE) 122 state = (u_int) -1; 123 if (fbi->task_state == C_DISABLE && state == C_ENABLE) 124 state = C_REENABLE; 125 126 if (state != (u_int)-1) { 127 fbi->task_state = state; 128 schedule_work(&fbi->task); 129 } 130 local_irq_restore(flags); 131 } 132 133 static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf) 134 { 135 chan &= 0xffff; 136 chan >>= 16 - bf->length; 137 return chan << bf->offset; 138 } 139 140 static int 141 pxafb_setpalettereg(u_int regno, u_int red, u_int green, u_int blue, 142 u_int trans, struct fb_info *info) 143 { 144 struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb); 145 u_int val; 146 147 if (regno >= fbi->palette_size) 148 return 1; 149 150 if (fbi->fb.var.grayscale) { 151 fbi->palette_cpu[regno] = ((blue >> 8) & 0x00ff); 152 return 0; 153 } 154 155 switch (fbi->lccr4 & LCCR4_PAL_FOR_MASK) { 156 case LCCR4_PAL_FOR_0: 157 val = ((red >> 0) & 0xf800); 158 val |= ((green >> 5) & 0x07e0); 159 val |= ((blue >> 11) & 0x001f); 160 fbi->palette_cpu[regno] = val; 161 break; 162 case LCCR4_PAL_FOR_1: 163 val = ((red << 8) & 0x00f80000); 164 val |= ((green >> 0) & 0x0000fc00); 165 val |= ((blue >> 8) & 0x000000f8); 166 ((u32 *)(fbi->palette_cpu))[regno] = val; 167 break; 168 case LCCR4_PAL_FOR_2: 169 val = ((red << 8) & 0x00fc0000); 170 val |= ((green >> 0) & 0x0000fc00); 171 val |= ((blue >> 8) & 0x000000fc); 172 ((u32 *)(fbi->palette_cpu))[regno] = val; 173 break; 174 case LCCR4_PAL_FOR_3: 175 val = ((red << 8) & 0x00ff0000); 176 val |= ((green >> 0) & 0x0000ff00); 177 val |= ((blue >> 8) & 0x000000ff); 178 ((u32 *)(fbi->palette_cpu))[regno] = val; 179 break; 180 } 181 182 return 0; 183 } 184 185 static int 186 pxafb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, 187 u_int trans, struct fb_info *info) 188 { 189 struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb); 190 unsigned int val; 191 int ret = 1; 192 193 /* 194 * If inverse mode was selected, invert all the colours 195 * rather than the register number. The register number 196 * is what you poke into the framebuffer to produce the 197 * colour you requested. 198 */ 199 if (fbi->cmap_inverse) { 200 red = 0xffff - red; 201 green = 0xffff - green; 202 blue = 0xffff - blue; 203 } 204 205 /* 206 * If greyscale is true, then we convert the RGB value 207 * to greyscale no matter what visual we are using. 208 */ 209 if (fbi->fb.var.grayscale) 210 red = green = blue = (19595 * red + 38470 * green + 211 7471 * blue) >> 16; 212 213 switch (fbi->fb.fix.visual) { 214 case FB_VISUAL_TRUECOLOR: 215 /* 216 * 16-bit True Colour. We encode the RGB value 217 * according to the RGB bitfield information. 218 */ 219 if (regno < 16) { 220 u32 *pal = fbi->fb.pseudo_palette; 221 222 val = chan_to_field(red, &fbi->fb.var.red); 223 val |= chan_to_field(green, &fbi->fb.var.green); 224 val |= chan_to_field(blue, &fbi->fb.var.blue); 225 226 pal[regno] = val; 227 ret = 0; 228 } 229 break; 230 231 case FB_VISUAL_STATIC_PSEUDOCOLOR: 232 case FB_VISUAL_PSEUDOCOLOR: 233 ret = pxafb_setpalettereg(regno, red, green, blue, trans, info); 234 break; 235 } 236 237 return ret; 238 } 239 240 /* calculate pixel depth, transparency bit included, >=16bpp formats _only_ */ 241 static inline int var_to_depth(struct fb_var_screeninfo *var) 242 { 243 return var->red.length + var->green.length + 244 var->blue.length + var->transp.length; 245 } 246 247 /* calculate 4-bit BPP value for LCCR3 and OVLxC1 */ 248 static int pxafb_var_to_bpp(struct fb_var_screeninfo *var) 249 { 250 int bpp = -EINVAL; 251 252 switch (var->bits_per_pixel) { 253 case 1: bpp = 0; break; 254 case 2: bpp = 1; break; 255 case 4: bpp = 2; break; 256 case 8: bpp = 3; break; 257 case 16: bpp = 4; break; 258 case 24: 259 switch (var_to_depth(var)) { 260 case 18: bpp = 6; break; /* 18-bits/pixel packed */ 261 case 19: bpp = 8; break; /* 19-bits/pixel packed */ 262 case 24: bpp = 9; break; 263 } 264 break; 265 case 32: 266 switch (var_to_depth(var)) { 267 case 18: bpp = 5; break; /* 18-bits/pixel unpacked */ 268 case 19: bpp = 7; break; /* 19-bits/pixel unpacked */ 269 case 25: bpp = 10; break; 270 } 271 break; 272 } 273 return bpp; 274 } 275 276 /* 277 * pxafb_var_to_lccr3(): 278 * Convert a bits per pixel value to the correct bit pattern for LCCR3 279 * 280 * NOTE: for PXA27x with overlays support, the LCCR3_PDFOR_x bits have an 281 * implication of the acutal use of transparency bit, which we handle it 282 * here separatedly. See PXA27x Developer's Manual, Section <<7.4.6 Pixel 283 * Formats>> for the valid combination of PDFOR, PAL_FOR for various BPP. 284 * 285 * Transparency for palette pixel formats is not supported at the moment. 286 */ 287 static uint32_t pxafb_var_to_lccr3(struct fb_var_screeninfo *var) 288 { 289 int bpp = pxafb_var_to_bpp(var); 290 uint32_t lccr3; 291 292 if (bpp < 0) 293 return 0; 294 295 lccr3 = LCCR3_BPP(bpp); 296 297 switch (var_to_depth(var)) { 298 case 16: lccr3 |= var->transp.length ? LCCR3_PDFOR_3 : 0; break; 299 case 18: lccr3 |= LCCR3_PDFOR_3; break; 300 case 24: lccr3 |= var->transp.length ? LCCR3_PDFOR_2 : LCCR3_PDFOR_3; 301 break; 302 case 19: 303 case 25: lccr3 |= LCCR3_PDFOR_0; break; 304 } 305 return lccr3; 306 } 307 308 #define SET_PIXFMT(v, r, g, b, t) \ 309 ({ \ 310 (v)->transp.offset = (t) ? (r) + (g) + (b) : 0; \ 311 (v)->transp.length = (t) ? (t) : 0; \ 312 (v)->blue.length = (b); (v)->blue.offset = 0; \ 313 (v)->green.length = (g); (v)->green.offset = (b); \ 314 (v)->red.length = (r); (v)->red.offset = (b) + (g); \ 315 }) 316 317 /* set the RGBT bitfields of fb_var_screeninf according to 318 * var->bits_per_pixel and given depth 319 */ 320 static void pxafb_set_pixfmt(struct fb_var_screeninfo *var, int depth) 321 { 322 if (depth == 0) 323 depth = var->bits_per_pixel; 324 325 if (var->bits_per_pixel < 16) { 326 /* indexed pixel formats */ 327 var->red.offset = 0; var->red.length = 8; 328 var->green.offset = 0; var->green.length = 8; 329 var->blue.offset = 0; var->blue.length = 8; 330 var->transp.offset = 0; var->transp.length = 8; 331 } 332 333 switch (depth) { 334 case 16: var->transp.length ? 335 SET_PIXFMT(var, 5, 5, 5, 1) : /* RGBT555 */ 336 SET_PIXFMT(var, 5, 6, 5, 0); break; /* RGB565 */ 337 case 18: SET_PIXFMT(var, 6, 6, 6, 0); break; /* RGB666 */ 338 case 19: SET_PIXFMT(var, 6, 6, 6, 1); break; /* RGBT666 */ 339 case 24: var->transp.length ? 340 SET_PIXFMT(var, 8, 8, 7, 1) : /* RGBT887 */ 341 SET_PIXFMT(var, 8, 8, 8, 0); break; /* RGB888 */ 342 case 25: SET_PIXFMT(var, 8, 8, 8, 1); break; /* RGBT888 */ 343 } 344 } 345 346 #ifdef CONFIG_CPU_FREQ 347 /* 348 * pxafb_display_dma_period() 349 * Calculate the minimum period (in picoseconds) between two DMA 350 * requests for the LCD controller. If we hit this, it means we're 351 * doing nothing but LCD DMA. 352 */ 353 static unsigned int pxafb_display_dma_period(struct fb_var_screeninfo *var) 354 { 355 /* 356 * Period = pixclock * bits_per_byte * bytes_per_transfer 357 * / memory_bits_per_pixel; 358 */ 359 return var->pixclock * 8 * 16 / var->bits_per_pixel; 360 } 361 #endif 362 363 /* 364 * Select the smallest mode that allows the desired resolution to be 365 * displayed. If desired parameters can be rounded up. 366 */ 367 static struct pxafb_mode_info *pxafb_getmode(struct pxafb_mach_info *mach, 368 struct fb_var_screeninfo *var) 369 { 370 struct pxafb_mode_info *mode = NULL; 371 struct pxafb_mode_info *modelist = mach->modes; 372 unsigned int best_x = 0xffffffff, best_y = 0xffffffff; 373 unsigned int i; 374 375 for (i = 0; i < mach->num_modes; i++) { 376 if (modelist[i].xres >= var->xres && 377 modelist[i].yres >= var->yres && 378 modelist[i].xres < best_x && 379 modelist[i].yres < best_y && 380 modelist[i].bpp >= var->bits_per_pixel) { 381 best_x = modelist[i].xres; 382 best_y = modelist[i].yres; 383 mode = &modelist[i]; 384 } 385 } 386 387 return mode; 388 } 389 390 static void pxafb_setmode(struct fb_var_screeninfo *var, 391 struct pxafb_mode_info *mode) 392 { 393 var->xres = mode->xres; 394 var->yres = mode->yres; 395 var->bits_per_pixel = mode->bpp; 396 var->pixclock = mode->pixclock; 397 var->hsync_len = mode->hsync_len; 398 var->left_margin = mode->left_margin; 399 var->right_margin = mode->right_margin; 400 var->vsync_len = mode->vsync_len; 401 var->upper_margin = mode->upper_margin; 402 var->lower_margin = mode->lower_margin; 403 var->sync = mode->sync; 404 var->grayscale = mode->cmap_greyscale; 405 var->transp.length = mode->transparency; 406 407 /* set the initial RGBA bitfields */ 408 pxafb_set_pixfmt(var, mode->depth); 409 } 410 411 static int pxafb_adjust_timing(struct pxafb_info *fbi, 412 struct fb_var_screeninfo *var) 413 { 414 int line_length; 415 416 var->xres = max_t(int, var->xres, MIN_XRES); 417 var->yres = max_t(int, var->yres, MIN_YRES); 418 419 if (!(fbi->lccr0 & LCCR0_LCDT)) { 420 clamp_val(var->hsync_len, 1, 64); 421 clamp_val(var->vsync_len, 1, 64); 422 clamp_val(var->left_margin, 1, 255); 423 clamp_val(var->right_margin, 1, 255); 424 clamp_val(var->upper_margin, 1, 255); 425 clamp_val(var->lower_margin, 1, 255); 426 } 427 428 /* make sure each line is aligned on word boundary */ 429 line_length = var->xres * var->bits_per_pixel / 8; 430 line_length = ALIGN(line_length, 4); 431 var->xres = line_length * 8 / var->bits_per_pixel; 432 433 /* we don't support xpan, force xres_virtual to be equal to xres */ 434 var->xres_virtual = var->xres; 435 436 if (var->accel_flags & FB_ACCELF_TEXT) 437 var->yres_virtual = fbi->fb.fix.smem_len / line_length; 438 else 439 var->yres_virtual = max(var->yres_virtual, var->yres); 440 441 /* check for limits */ 442 if (var->xres > MAX_XRES || var->yres > MAX_YRES) 443 return -EINVAL; 444 445 if (var->yres > var->yres_virtual) 446 return -EINVAL; 447 448 return 0; 449 } 450 451 /* 452 * pxafb_check_var(): 453 * Get the video params out of 'var'. If a value doesn't fit, round it up, 454 * if it's too big, return -EINVAL. 455 * 456 * Round up in the following order: bits_per_pixel, xres, 457 * yres, xres_virtual, yres_virtual, xoffset, yoffset, grayscale, 458 * bitfields, horizontal timing, vertical timing. 459 */ 460 static int pxafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) 461 { 462 struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb); 463 struct pxafb_mach_info *inf = fbi->inf; 464 int err; 465 466 if (inf->fixed_modes) { 467 struct pxafb_mode_info *mode; 468 469 mode = pxafb_getmode(inf, var); 470 if (!mode) 471 return -EINVAL; 472 pxafb_setmode(var, mode); 473 } 474 475 /* do a test conversion to BPP fields to check the color formats */ 476 err = pxafb_var_to_bpp(var); 477 if (err < 0) 478 return err; 479 480 pxafb_set_pixfmt(var, var_to_depth(var)); 481 482 err = pxafb_adjust_timing(fbi, var); 483 if (err) 484 return err; 485 486 #ifdef CONFIG_CPU_FREQ 487 pr_debug("pxafb: dma period = %d ps\n", 488 pxafb_display_dma_period(var)); 489 #endif 490 491 return 0; 492 } 493 494 /* 495 * pxafb_set_par(): 496 * Set the user defined part of the display for the specified console 497 */ 498 static int pxafb_set_par(struct fb_info *info) 499 { 500 struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb); 501 struct fb_var_screeninfo *var = &info->var; 502 503 if (var->bits_per_pixel >= 16) 504 fbi->fb.fix.visual = FB_VISUAL_TRUECOLOR; 505 else if (!fbi->cmap_static) 506 fbi->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR; 507 else { 508 /* 509 * Some people have weird ideas about wanting static 510 * pseudocolor maps. I suspect their user space 511 * applications are broken. 512 */ 513 fbi->fb.fix.visual = FB_VISUAL_STATIC_PSEUDOCOLOR; 514 } 515 516 fbi->fb.fix.line_length = var->xres_virtual * 517 var->bits_per_pixel / 8; 518 if (var->bits_per_pixel >= 16) 519 fbi->palette_size = 0; 520 else 521 fbi->palette_size = var->bits_per_pixel == 1 ? 522 4 : 1 << var->bits_per_pixel; 523 524 fbi->palette_cpu = (u16 *)&fbi->dma_buff->palette[0]; 525 526 if (fbi->fb.var.bits_per_pixel >= 16) 527 fb_dealloc_cmap(&fbi->fb.cmap); 528 else 529 fb_alloc_cmap(&fbi->fb.cmap, 1<<fbi->fb.var.bits_per_pixel, 0); 530 531 pxafb_activate_var(var, fbi); 532 533 return 0; 534 } 535 536 static int pxafb_pan_display(struct fb_var_screeninfo *var, 537 struct fb_info *info) 538 { 539 struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb); 540 struct fb_var_screeninfo newvar; 541 int dma = DMA_MAX + DMA_BASE; 542 543 if (fbi->state != C_ENABLE) 544 return 0; 545 546 /* Only take .xoffset, .yoffset and .vmode & FB_VMODE_YWRAP from what 547 * was passed in and copy the rest from the old screeninfo. 548 */ 549 memcpy(&newvar, &fbi->fb.var, sizeof(newvar)); 550 newvar.xoffset = var->xoffset; 551 newvar.yoffset = var->yoffset; 552 newvar.vmode &= ~FB_VMODE_YWRAP; 553 newvar.vmode |= var->vmode & FB_VMODE_YWRAP; 554 555 setup_base_frame(fbi, &newvar, 1); 556 557 if (fbi->lccr0 & LCCR0_SDS) 558 lcd_writel(fbi, FBR1, fbi->fdadr[dma + 1] | 0x1); 559 560 lcd_writel(fbi, FBR0, fbi->fdadr[dma] | 0x1); 561 return 0; 562 } 563 564 /* 565 * pxafb_blank(): 566 * Blank the display by setting all palette values to zero. Note, the 567 * 16 bpp mode does not really use the palette, so this will not 568 * blank the display in all modes. 569 */ 570 static int pxafb_blank(int blank, struct fb_info *info) 571 { 572 struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb); 573 int i; 574 575 switch (blank) { 576 case FB_BLANK_POWERDOWN: 577 case FB_BLANK_VSYNC_SUSPEND: 578 case FB_BLANK_HSYNC_SUSPEND: 579 case FB_BLANK_NORMAL: 580 if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR || 581 fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR) 582 for (i = 0; i < fbi->palette_size; i++) 583 pxafb_setpalettereg(i, 0, 0, 0, 0, info); 584 585 pxafb_schedule_work(fbi, C_DISABLE); 586 /* TODO if (pxafb_blank_helper) pxafb_blank_helper(blank); */ 587 break; 588 589 case FB_BLANK_UNBLANK: 590 /* TODO if (pxafb_blank_helper) pxafb_blank_helper(blank); */ 591 if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR || 592 fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR) 593 fb_set_cmap(&fbi->fb.cmap, info); 594 pxafb_schedule_work(fbi, C_ENABLE); 595 } 596 return 0; 597 } 598 599 static struct fb_ops pxafb_ops = { 600 .owner = THIS_MODULE, 601 .fb_check_var = pxafb_check_var, 602 .fb_set_par = pxafb_set_par, 603 .fb_pan_display = pxafb_pan_display, 604 .fb_setcolreg = pxafb_setcolreg, 605 .fb_fillrect = cfb_fillrect, 606 .fb_copyarea = cfb_copyarea, 607 .fb_imageblit = cfb_imageblit, 608 .fb_blank = pxafb_blank, 609 }; 610 611 #ifdef CONFIG_FB_PXA_OVERLAY 612 static void overlay1fb_setup(struct pxafb_layer *ofb) 613 { 614 int size = ofb->fb.fix.line_length * ofb->fb.var.yres_virtual; 615 unsigned long start = ofb->video_mem_phys; 616 setup_frame_dma(ofb->fbi, DMA_OV1, PAL_NONE, start, size); 617 } 618 619 /* Depending on the enable status of overlay1/2, the DMA should be 620 * updated from FDADRx (when disabled) or FBRx (when enabled). 621 */ 622 static void overlay1fb_enable(struct pxafb_layer *ofb) 623 { 624 int enabled = lcd_readl(ofb->fbi, OVL1C1) & OVLxC1_OEN; 625 uint32_t fdadr1 = ofb->fbi->fdadr[DMA_OV1] | (enabled ? 0x1 : 0); 626 627 lcd_writel(ofb->fbi, enabled ? FBR1 : FDADR1, fdadr1); 628 lcd_writel(ofb->fbi, OVL1C2, ofb->control[1]); 629 lcd_writel(ofb->fbi, OVL1C1, ofb->control[0] | OVLxC1_OEN); 630 } 631 632 static void overlay1fb_disable(struct pxafb_layer *ofb) 633 { 634 uint32_t lccr5; 635 636 if (!(lcd_readl(ofb->fbi, OVL1C1) & OVLxC1_OEN)) 637 return; 638 639 lccr5 = lcd_readl(ofb->fbi, LCCR5); 640 641 lcd_writel(ofb->fbi, OVL1C1, ofb->control[0] & ~OVLxC1_OEN); 642 643 lcd_writel(ofb->fbi, LCSR1, LCSR1_BS(1)); 644 lcd_writel(ofb->fbi, LCCR5, lccr5 & ~LCSR1_BS(1)); 645 lcd_writel(ofb->fbi, FBR1, ofb->fbi->fdadr[DMA_OV1] | 0x3); 646 647 if (wait_for_completion_timeout(&ofb->branch_done, 1 * HZ) == 0) 648 pr_warn("%s: timeout disabling overlay1\n", __func__); 649 650 lcd_writel(ofb->fbi, LCCR5, lccr5); 651 } 652 653 static void overlay2fb_setup(struct pxafb_layer *ofb) 654 { 655 int size, div = 1, pfor = NONSTD_TO_PFOR(ofb->fb.var.nonstd); 656 unsigned long start[3] = { ofb->video_mem_phys, 0, 0 }; 657 658 if (pfor == OVERLAY_FORMAT_RGB || pfor == OVERLAY_FORMAT_YUV444_PACKED) { 659 size = ofb->fb.fix.line_length * ofb->fb.var.yres_virtual; 660 setup_frame_dma(ofb->fbi, DMA_OV2_Y, -1, start[0], size); 661 } else { 662 size = ofb->fb.var.xres_virtual * ofb->fb.var.yres_virtual; 663 switch (pfor) { 664 case OVERLAY_FORMAT_YUV444_PLANAR: div = 1; break; 665 case OVERLAY_FORMAT_YUV422_PLANAR: div = 2; break; 666 case OVERLAY_FORMAT_YUV420_PLANAR: div = 4; break; 667 } 668 start[1] = start[0] + size; 669 start[2] = start[1] + size / div; 670 setup_frame_dma(ofb->fbi, DMA_OV2_Y, -1, start[0], size); 671 setup_frame_dma(ofb->fbi, DMA_OV2_Cb, -1, start[1], size / div); 672 setup_frame_dma(ofb->fbi, DMA_OV2_Cr, -1, start[2], size / div); 673 } 674 } 675 676 static void overlay2fb_enable(struct pxafb_layer *ofb) 677 { 678 int pfor = NONSTD_TO_PFOR(ofb->fb.var.nonstd); 679 int enabled = lcd_readl(ofb->fbi, OVL2C1) & OVLxC1_OEN; 680 uint32_t fdadr2 = ofb->fbi->fdadr[DMA_OV2_Y] | (enabled ? 0x1 : 0); 681 uint32_t fdadr3 = ofb->fbi->fdadr[DMA_OV2_Cb] | (enabled ? 0x1 : 0); 682 uint32_t fdadr4 = ofb->fbi->fdadr[DMA_OV2_Cr] | (enabled ? 0x1 : 0); 683 684 if (pfor == OVERLAY_FORMAT_RGB || pfor == OVERLAY_FORMAT_YUV444_PACKED) 685 lcd_writel(ofb->fbi, enabled ? FBR2 : FDADR2, fdadr2); 686 else { 687 lcd_writel(ofb->fbi, enabled ? FBR2 : FDADR2, fdadr2); 688 lcd_writel(ofb->fbi, enabled ? FBR3 : FDADR3, fdadr3); 689 lcd_writel(ofb->fbi, enabled ? FBR4 : FDADR4, fdadr4); 690 } 691 lcd_writel(ofb->fbi, OVL2C2, ofb->control[1]); 692 lcd_writel(ofb->fbi, OVL2C1, ofb->control[0] | OVLxC1_OEN); 693 } 694 695 static void overlay2fb_disable(struct pxafb_layer *ofb) 696 { 697 uint32_t lccr5; 698 699 if (!(lcd_readl(ofb->fbi, OVL2C1) & OVLxC1_OEN)) 700 return; 701 702 lccr5 = lcd_readl(ofb->fbi, LCCR5); 703 704 lcd_writel(ofb->fbi, OVL2C1, ofb->control[0] & ~OVLxC1_OEN); 705 706 lcd_writel(ofb->fbi, LCSR1, LCSR1_BS(2)); 707 lcd_writel(ofb->fbi, LCCR5, lccr5 & ~LCSR1_BS(2)); 708 lcd_writel(ofb->fbi, FBR2, ofb->fbi->fdadr[DMA_OV2_Y] | 0x3); 709 lcd_writel(ofb->fbi, FBR3, ofb->fbi->fdadr[DMA_OV2_Cb] | 0x3); 710 lcd_writel(ofb->fbi, FBR4, ofb->fbi->fdadr[DMA_OV2_Cr] | 0x3); 711 712 if (wait_for_completion_timeout(&ofb->branch_done, 1 * HZ) == 0) 713 pr_warn("%s: timeout disabling overlay2\n", __func__); 714 } 715 716 static struct pxafb_layer_ops ofb_ops[] = { 717 [0] = { 718 .enable = overlay1fb_enable, 719 .disable = overlay1fb_disable, 720 .setup = overlay1fb_setup, 721 }, 722 [1] = { 723 .enable = overlay2fb_enable, 724 .disable = overlay2fb_disable, 725 .setup = overlay2fb_setup, 726 }, 727 }; 728 729 static int overlayfb_open(struct fb_info *info, int user) 730 { 731 struct pxafb_layer *ofb = container_of(info, struct pxafb_layer, fb); 732 733 /* no support for framebuffer console on overlay */ 734 if (user == 0) 735 return -ENODEV; 736 737 if (ofb->usage++ == 0) { 738 /* unblank the base framebuffer */ 739 console_lock(); 740 fb_blank(&ofb->fbi->fb, FB_BLANK_UNBLANK); 741 console_unlock(); 742 } 743 744 return 0; 745 } 746 747 static int overlayfb_release(struct fb_info *info, int user) 748 { 749 struct pxafb_layer *ofb = container_of(info, struct pxafb_layer, fb); 750 751 if (ofb->usage == 1) { 752 ofb->ops->disable(ofb); 753 ofb->fb.var.height = -1; 754 ofb->fb.var.width = -1; 755 ofb->fb.var.xres = ofb->fb.var.xres_virtual = 0; 756 ofb->fb.var.yres = ofb->fb.var.yres_virtual = 0; 757 758 ofb->usage--; 759 } 760 return 0; 761 } 762 763 static int overlayfb_check_var(struct fb_var_screeninfo *var, 764 struct fb_info *info) 765 { 766 struct pxafb_layer *ofb = container_of(info, struct pxafb_layer, fb); 767 struct fb_var_screeninfo *base_var = &ofb->fbi->fb.var; 768 int xpos, ypos, pfor, bpp; 769 770 xpos = NONSTD_TO_XPOS(var->nonstd); 771 ypos = NONSTD_TO_YPOS(var->nonstd); 772 pfor = NONSTD_TO_PFOR(var->nonstd); 773 774 bpp = pxafb_var_to_bpp(var); 775 if (bpp < 0) 776 return -EINVAL; 777 778 /* no support for YUV format on overlay1 */ 779 if (ofb->id == OVERLAY1 && pfor != 0) 780 return -EINVAL; 781 782 /* for YUV packed formats, bpp = 'minimum bpp of YUV components' */ 783 switch (pfor) { 784 case OVERLAY_FORMAT_RGB: 785 bpp = pxafb_var_to_bpp(var); 786 if (bpp < 0) 787 return -EINVAL; 788 789 pxafb_set_pixfmt(var, var_to_depth(var)); 790 break; 791 case OVERLAY_FORMAT_YUV444_PACKED: bpp = 24; break; 792 case OVERLAY_FORMAT_YUV444_PLANAR: bpp = 8; break; 793 case OVERLAY_FORMAT_YUV422_PLANAR: bpp = 4; break; 794 case OVERLAY_FORMAT_YUV420_PLANAR: bpp = 2; break; 795 default: 796 return -EINVAL; 797 } 798 799 /* each line must start at a 32-bit word boundary */ 800 if ((xpos * bpp) % 32) 801 return -EINVAL; 802 803 /* xres must align on 32-bit word boundary */ 804 var->xres = roundup(var->xres * bpp, 32) / bpp; 805 806 if ((xpos + var->xres > base_var->xres) || 807 (ypos + var->yres > base_var->yres)) 808 return -EINVAL; 809 810 var->xres_virtual = var->xres; 811 var->yres_virtual = max(var->yres, var->yres_virtual); 812 return 0; 813 } 814 815 static int overlayfb_check_video_memory(struct pxafb_layer *ofb) 816 { 817 struct fb_var_screeninfo *var = &ofb->fb.var; 818 int pfor = NONSTD_TO_PFOR(var->nonstd); 819 int size, bpp = 0; 820 821 switch (pfor) { 822 case OVERLAY_FORMAT_RGB: bpp = var->bits_per_pixel; break; 823 case OVERLAY_FORMAT_YUV444_PACKED: bpp = 24; break; 824 case OVERLAY_FORMAT_YUV444_PLANAR: bpp = 24; break; 825 case OVERLAY_FORMAT_YUV422_PLANAR: bpp = 16; break; 826 case OVERLAY_FORMAT_YUV420_PLANAR: bpp = 12; break; 827 } 828 829 ofb->fb.fix.line_length = var->xres_virtual * bpp / 8; 830 831 size = PAGE_ALIGN(ofb->fb.fix.line_length * var->yres_virtual); 832 833 if (ofb->video_mem) { 834 if (ofb->video_mem_size >= size) 835 return 0; 836 } 837 return -EINVAL; 838 } 839 840 static int overlayfb_set_par(struct fb_info *info) 841 { 842 struct pxafb_layer *ofb = container_of(info, struct pxafb_layer, fb); 843 struct fb_var_screeninfo *var = &info->var; 844 int xpos, ypos, pfor, bpp, ret; 845 846 ret = overlayfb_check_video_memory(ofb); 847 if (ret) 848 return ret; 849 850 bpp = pxafb_var_to_bpp(var); 851 xpos = NONSTD_TO_XPOS(var->nonstd); 852 ypos = NONSTD_TO_YPOS(var->nonstd); 853 pfor = NONSTD_TO_PFOR(var->nonstd); 854 855 ofb->control[0] = OVLxC1_PPL(var->xres) | OVLxC1_LPO(var->yres) | 856 OVLxC1_BPP(bpp); 857 ofb->control[1] = OVLxC2_XPOS(xpos) | OVLxC2_YPOS(ypos); 858 859 if (ofb->id == OVERLAY2) 860 ofb->control[1] |= OVL2C2_PFOR(pfor); 861 862 ofb->ops->setup(ofb); 863 ofb->ops->enable(ofb); 864 return 0; 865 } 866 867 static struct fb_ops overlay_fb_ops = { 868 .owner = THIS_MODULE, 869 .fb_open = overlayfb_open, 870 .fb_release = overlayfb_release, 871 .fb_check_var = overlayfb_check_var, 872 .fb_set_par = overlayfb_set_par, 873 }; 874 875 static void init_pxafb_overlay(struct pxafb_info *fbi, struct pxafb_layer *ofb, 876 int id) 877 { 878 sprintf(ofb->fb.fix.id, "overlay%d", id + 1); 879 880 ofb->fb.fix.type = FB_TYPE_PACKED_PIXELS; 881 ofb->fb.fix.xpanstep = 0; 882 ofb->fb.fix.ypanstep = 1; 883 884 ofb->fb.var.activate = FB_ACTIVATE_NOW; 885 ofb->fb.var.height = -1; 886 ofb->fb.var.width = -1; 887 ofb->fb.var.vmode = FB_VMODE_NONINTERLACED; 888 889 ofb->fb.fbops = &overlay_fb_ops; 890 ofb->fb.flags = FBINFO_FLAG_DEFAULT; 891 ofb->fb.node = -1; 892 ofb->fb.pseudo_palette = NULL; 893 894 ofb->id = id; 895 ofb->ops = &ofb_ops[id]; 896 ofb->usage = 0; 897 ofb->fbi = fbi; 898 init_completion(&ofb->branch_done); 899 } 900 901 static inline int pxafb_overlay_supported(void) 902 { 903 if (cpu_is_pxa27x() || cpu_is_pxa3xx()) 904 return 1; 905 906 return 0; 907 } 908 909 static int pxafb_overlay_map_video_memory(struct pxafb_info *pxafb, 910 struct pxafb_layer *ofb) 911 { 912 /* We assume that user will use at most video_mem_size for overlay fb, 913 * anyway, it's useless to use 16bpp main plane and 24bpp overlay 914 */ 915 ofb->video_mem = alloc_pages_exact(PAGE_ALIGN(pxafb->video_mem_size), 916 GFP_KERNEL | __GFP_ZERO); 917 if (ofb->video_mem == NULL) 918 return -ENOMEM; 919 920 ofb->video_mem_phys = virt_to_phys(ofb->video_mem); 921 ofb->video_mem_size = PAGE_ALIGN(pxafb->video_mem_size); 922 923 mutex_lock(&ofb->fb.mm_lock); 924 ofb->fb.fix.smem_start = ofb->video_mem_phys; 925 ofb->fb.fix.smem_len = pxafb->video_mem_size; 926 mutex_unlock(&ofb->fb.mm_lock); 927 928 ofb->fb.screen_base = ofb->video_mem; 929 930 return 0; 931 } 932 933 static void pxafb_overlay_init(struct pxafb_info *fbi) 934 { 935 int i, ret; 936 937 if (!pxafb_overlay_supported()) 938 return; 939 940 for (i = 0; i < 2; i++) { 941 struct pxafb_layer *ofb = &fbi->overlay[i]; 942 init_pxafb_overlay(fbi, ofb, i); 943 ret = register_framebuffer(&ofb->fb); 944 if (ret) { 945 dev_err(fbi->dev, "failed to register overlay %d\n", i); 946 continue; 947 } 948 ret = pxafb_overlay_map_video_memory(fbi, ofb); 949 if (ret) { 950 dev_err(fbi->dev, 951 "failed to map video memory for overlay %d\n", 952 i); 953 unregister_framebuffer(&ofb->fb); 954 continue; 955 } 956 ofb->registered = 1; 957 } 958 959 /* mask all IU/BS/EOF/SOF interrupts */ 960 lcd_writel(fbi, LCCR5, ~0); 961 962 pr_info("PXA Overlay driver loaded successfully!\n"); 963 } 964 965 static void pxafb_overlay_exit(struct pxafb_info *fbi) 966 { 967 int i; 968 969 if (!pxafb_overlay_supported()) 970 return; 971 972 for (i = 0; i < 2; i++) { 973 struct pxafb_layer *ofb = &fbi->overlay[i]; 974 if (ofb->registered) { 975 if (ofb->video_mem) 976 free_pages_exact(ofb->video_mem, 977 ofb->video_mem_size); 978 unregister_framebuffer(&ofb->fb); 979 } 980 } 981 } 982 #else 983 static inline void pxafb_overlay_init(struct pxafb_info *fbi) {} 984 static inline void pxafb_overlay_exit(struct pxafb_info *fbi) {} 985 #endif /* CONFIG_FB_PXA_OVERLAY */ 986 987 /* 988 * Calculate the PCD value from the clock rate (in picoseconds). 989 * We take account of the PPCR clock setting. 990 * From PXA Developer's Manual: 991 * 992 * PixelClock = LCLK 993 * ------------- 994 * 2 ( PCD + 1 ) 995 * 996 * PCD = LCLK 997 * ------------- - 1 998 * 2(PixelClock) 999 * 1000 * Where: 1001 * LCLK = LCD/Memory Clock 1002 * PCD = LCCR3[7:0] 1003 * 1004 * PixelClock here is in Hz while the pixclock argument given is the 1005 * period in picoseconds. Hence PixelClock = 1 / ( pixclock * 10^-12 ) 1006 * 1007 * The function get_lclk_frequency_10khz returns LCLK in units of 1008 * 10khz. Calling the result of this function lclk gives us the 1009 * following 1010 * 1011 * PCD = (lclk * 10^4 ) * ( pixclock * 10^-12 ) 1012 * -------------------------------------- - 1 1013 * 2 1014 * 1015 * Factoring the 10^4 and 10^-12 out gives 10^-8 == 1 / 100000000 as used below. 1016 */ 1017 static inline unsigned int get_pcd(struct pxafb_info *fbi, 1018 unsigned int pixclock) 1019 { 1020 unsigned long long pcd; 1021 1022 /* FIXME: Need to take into account Double Pixel Clock mode 1023 * (DPC) bit? or perhaps set it based on the various clock 1024 * speeds */ 1025 pcd = (unsigned long long)(clk_get_rate(fbi->clk) / 10000); 1026 pcd *= pixclock; 1027 do_div(pcd, 100000000 * 2); 1028 /* no need for this, since we should subtract 1 anyway. they cancel */ 1029 /* pcd += 1; */ /* make up for integer math truncations */ 1030 return (unsigned int)pcd; 1031 } 1032 1033 /* 1034 * Some touchscreens need hsync information from the video driver to 1035 * function correctly. We export it here. Note that 'hsync_time' and 1036 * the value returned from pxafb_get_hsync_time() is the *reciprocal* 1037 * of the hsync period in seconds. 1038 */ 1039 static inline void set_hsync_time(struct pxafb_info *fbi, unsigned int pcd) 1040 { 1041 unsigned long htime; 1042 1043 if ((pcd == 0) || (fbi->fb.var.hsync_len == 0)) { 1044 fbi->hsync_time = 0; 1045 return; 1046 } 1047 1048 htime = clk_get_rate(fbi->clk) / (pcd * fbi->fb.var.hsync_len); 1049 1050 fbi->hsync_time = htime; 1051 } 1052 1053 unsigned long pxafb_get_hsync_time(struct device *dev) 1054 { 1055 struct pxafb_info *fbi = dev_get_drvdata(dev); 1056 1057 /* If display is blanked/suspended, hsync isn't active */ 1058 if (!fbi || (fbi->state != C_ENABLE)) 1059 return 0; 1060 1061 return fbi->hsync_time; 1062 } 1063 EXPORT_SYMBOL(pxafb_get_hsync_time); 1064 1065 static int setup_frame_dma(struct pxafb_info *fbi, int dma, int pal, 1066 unsigned long start, size_t size) 1067 { 1068 struct pxafb_dma_descriptor *dma_desc, *pal_desc; 1069 unsigned int dma_desc_off, pal_desc_off; 1070 1071 if (dma < 0 || dma >= DMA_MAX * 2) 1072 return -EINVAL; 1073 1074 dma_desc = &fbi->dma_buff->dma_desc[dma]; 1075 dma_desc_off = offsetof(struct pxafb_dma_buff, dma_desc[dma]); 1076 1077 dma_desc->fsadr = start; 1078 dma_desc->fidr = 0; 1079 dma_desc->ldcmd = size; 1080 1081 if (pal < 0 || pal >= PAL_MAX * 2) { 1082 dma_desc->fdadr = fbi->dma_buff_phys + dma_desc_off; 1083 fbi->fdadr[dma] = fbi->dma_buff_phys + dma_desc_off; 1084 } else { 1085 pal_desc = &fbi->dma_buff->pal_desc[pal]; 1086 pal_desc_off = offsetof(struct pxafb_dma_buff, pal_desc[pal]); 1087 1088 pal_desc->fsadr = fbi->dma_buff_phys + pal * PALETTE_SIZE; 1089 pal_desc->fidr = 0; 1090 1091 if ((fbi->lccr4 & LCCR4_PAL_FOR_MASK) == LCCR4_PAL_FOR_0) 1092 pal_desc->ldcmd = fbi->palette_size * sizeof(u16); 1093 else 1094 pal_desc->ldcmd = fbi->palette_size * sizeof(u32); 1095 1096 pal_desc->ldcmd |= LDCMD_PAL; 1097 1098 /* flip back and forth between palette and frame buffer */ 1099 pal_desc->fdadr = fbi->dma_buff_phys + dma_desc_off; 1100 dma_desc->fdadr = fbi->dma_buff_phys + pal_desc_off; 1101 fbi->fdadr[dma] = fbi->dma_buff_phys + dma_desc_off; 1102 } 1103 1104 return 0; 1105 } 1106 1107 static void setup_base_frame(struct pxafb_info *fbi, 1108 struct fb_var_screeninfo *var, 1109 int branch) 1110 { 1111 struct fb_fix_screeninfo *fix = &fbi->fb.fix; 1112 int nbytes, dma, pal, bpp = var->bits_per_pixel; 1113 unsigned long offset; 1114 1115 dma = DMA_BASE + (branch ? DMA_MAX : 0); 1116 pal = (bpp >= 16) ? PAL_NONE : PAL_BASE + (branch ? PAL_MAX : 0); 1117 1118 nbytes = fix->line_length * var->yres; 1119 offset = fix->line_length * var->yoffset + fbi->video_mem_phys; 1120 1121 if (fbi->lccr0 & LCCR0_SDS) { 1122 nbytes = nbytes / 2; 1123 setup_frame_dma(fbi, dma + 1, PAL_NONE, offset + nbytes, nbytes); 1124 } 1125 1126 setup_frame_dma(fbi, dma, pal, offset, nbytes); 1127 } 1128 1129 #ifdef CONFIG_FB_PXA_SMARTPANEL 1130 static int setup_smart_dma(struct pxafb_info *fbi) 1131 { 1132 struct pxafb_dma_descriptor *dma_desc; 1133 unsigned long dma_desc_off, cmd_buff_off; 1134 1135 dma_desc = &fbi->dma_buff->dma_desc[DMA_CMD]; 1136 dma_desc_off = offsetof(struct pxafb_dma_buff, dma_desc[DMA_CMD]); 1137 cmd_buff_off = offsetof(struct pxafb_dma_buff, cmd_buff); 1138 1139 dma_desc->fdadr = fbi->dma_buff_phys + dma_desc_off; 1140 dma_desc->fsadr = fbi->dma_buff_phys + cmd_buff_off; 1141 dma_desc->fidr = 0; 1142 dma_desc->ldcmd = fbi->n_smart_cmds * sizeof(uint16_t); 1143 1144 fbi->fdadr[DMA_CMD] = dma_desc->fdadr; 1145 return 0; 1146 } 1147 1148 int pxafb_smart_flush(struct fb_info *info) 1149 { 1150 struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb); 1151 uint32_t prsr; 1152 int ret = 0; 1153 1154 /* disable controller until all registers are set up */ 1155 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 & ~LCCR0_ENB); 1156 1157 /* 1. make it an even number of commands to align on 32-bit boundary 1158 * 2. add the interrupt command to the end of the chain so we can 1159 * keep track of the end of the transfer 1160 */ 1161 1162 while (fbi->n_smart_cmds & 1) 1163 fbi->smart_cmds[fbi->n_smart_cmds++] = SMART_CMD_NOOP; 1164 1165 fbi->smart_cmds[fbi->n_smart_cmds++] = SMART_CMD_INTERRUPT; 1166 fbi->smart_cmds[fbi->n_smart_cmds++] = SMART_CMD_WAIT_FOR_VSYNC; 1167 setup_smart_dma(fbi); 1168 1169 /* continue to execute next command */ 1170 prsr = lcd_readl(fbi, PRSR) | PRSR_ST_OK | PRSR_CON_NT; 1171 lcd_writel(fbi, PRSR, prsr); 1172 1173 /* stop the processor in case it executed "wait for sync" cmd */ 1174 lcd_writel(fbi, CMDCR, 0x0001); 1175 1176 /* don't send interrupts for fifo underruns on channel 6 */ 1177 lcd_writel(fbi, LCCR5, LCCR5_IUM(6)); 1178 1179 lcd_writel(fbi, LCCR1, fbi->reg_lccr1); 1180 lcd_writel(fbi, LCCR2, fbi->reg_lccr2); 1181 lcd_writel(fbi, LCCR3, fbi->reg_lccr3); 1182 lcd_writel(fbi, LCCR4, fbi->reg_lccr4); 1183 lcd_writel(fbi, FDADR0, fbi->fdadr[0]); 1184 lcd_writel(fbi, FDADR6, fbi->fdadr[6]); 1185 1186 /* begin sending */ 1187 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 | LCCR0_ENB); 1188 1189 if (wait_for_completion_timeout(&fbi->command_done, HZ/2) == 0) { 1190 pr_warn("%s: timeout waiting for command done\n", __func__); 1191 ret = -ETIMEDOUT; 1192 } 1193 1194 /* quick disable */ 1195 prsr = lcd_readl(fbi, PRSR) & ~(PRSR_ST_OK | PRSR_CON_NT); 1196 lcd_writel(fbi, PRSR, prsr); 1197 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 & ~LCCR0_ENB); 1198 lcd_writel(fbi, FDADR6, 0); 1199 fbi->n_smart_cmds = 0; 1200 return ret; 1201 } 1202 1203 int pxafb_smart_queue(struct fb_info *info, uint16_t *cmds, int n_cmds) 1204 { 1205 int i; 1206 struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb); 1207 1208 for (i = 0; i < n_cmds; i++, cmds++) { 1209 /* if it is a software delay, flush and delay */ 1210 if ((*cmds & 0xff00) == SMART_CMD_DELAY) { 1211 pxafb_smart_flush(info); 1212 mdelay(*cmds & 0xff); 1213 continue; 1214 } 1215 1216 /* leave 2 commands for INTERRUPT and WAIT_FOR_SYNC */ 1217 if (fbi->n_smart_cmds == CMD_BUFF_SIZE - 8) 1218 pxafb_smart_flush(info); 1219 1220 fbi->smart_cmds[fbi->n_smart_cmds++] = *cmds; 1221 } 1222 1223 return 0; 1224 } 1225 1226 static unsigned int __smart_timing(unsigned time_ns, unsigned long lcd_clk) 1227 { 1228 unsigned int t = (time_ns * (lcd_clk / 1000000) / 1000); 1229 return (t == 0) ? 1 : t; 1230 } 1231 1232 static void setup_smart_timing(struct pxafb_info *fbi, 1233 struct fb_var_screeninfo *var) 1234 { 1235 struct pxafb_mach_info *inf = fbi->inf; 1236 struct pxafb_mode_info *mode = &inf->modes[0]; 1237 unsigned long lclk = clk_get_rate(fbi->clk); 1238 unsigned t1, t2, t3, t4; 1239 1240 t1 = max(mode->a0csrd_set_hld, mode->a0cswr_set_hld); 1241 t2 = max(mode->rd_pulse_width, mode->wr_pulse_width); 1242 t3 = mode->op_hold_time; 1243 t4 = mode->cmd_inh_time; 1244 1245 fbi->reg_lccr1 = 1246 LCCR1_DisWdth(var->xres) | 1247 LCCR1_BegLnDel(__smart_timing(t1, lclk)) | 1248 LCCR1_EndLnDel(__smart_timing(t2, lclk)) | 1249 LCCR1_HorSnchWdth(__smart_timing(t3, lclk)); 1250 1251 fbi->reg_lccr2 = LCCR2_DisHght(var->yres); 1252 fbi->reg_lccr3 = fbi->lccr3 | LCCR3_PixClkDiv(__smart_timing(t4, lclk)); 1253 fbi->reg_lccr3 |= (var->sync & FB_SYNC_HOR_HIGH_ACT) ? LCCR3_HSP : 0; 1254 fbi->reg_lccr3 |= (var->sync & FB_SYNC_VERT_HIGH_ACT) ? LCCR3_VSP : 0; 1255 1256 /* FIXME: make this configurable */ 1257 fbi->reg_cmdcr = 1; 1258 } 1259 1260 static int pxafb_smart_thread(void *arg) 1261 { 1262 struct pxafb_info *fbi = arg; 1263 struct pxafb_mach_info *inf = fbi->inf; 1264 1265 if (!inf->smart_update) { 1266 pr_err("%s: not properly initialized, thread terminated\n", 1267 __func__); 1268 return -EINVAL; 1269 } 1270 1271 pr_debug("%s(): task starting\n", __func__); 1272 1273 set_freezable(); 1274 while (!kthread_should_stop()) { 1275 1276 if (try_to_freeze()) 1277 continue; 1278 1279 mutex_lock(&fbi->ctrlr_lock); 1280 1281 if (fbi->state == C_ENABLE) { 1282 inf->smart_update(&fbi->fb); 1283 complete(&fbi->refresh_done); 1284 } 1285 1286 mutex_unlock(&fbi->ctrlr_lock); 1287 1288 set_current_state(TASK_INTERRUPTIBLE); 1289 schedule_timeout(msecs_to_jiffies(30)); 1290 } 1291 1292 pr_debug("%s(): task ending\n", __func__); 1293 return 0; 1294 } 1295 1296 static int pxafb_smart_init(struct pxafb_info *fbi) 1297 { 1298 if (!(fbi->lccr0 & LCCR0_LCDT)) 1299 return 0; 1300 1301 fbi->smart_cmds = (uint16_t *) fbi->dma_buff->cmd_buff; 1302 fbi->n_smart_cmds = 0; 1303 1304 init_completion(&fbi->command_done); 1305 init_completion(&fbi->refresh_done); 1306 1307 fbi->smart_thread = kthread_run(pxafb_smart_thread, fbi, 1308 "lcd_refresh"); 1309 if (IS_ERR(fbi->smart_thread)) { 1310 pr_err("%s: unable to create kernel thread\n", __func__); 1311 return PTR_ERR(fbi->smart_thread); 1312 } 1313 1314 return 0; 1315 } 1316 #else 1317 static inline int pxafb_smart_init(struct pxafb_info *fbi) { return 0; } 1318 #endif /* CONFIG_FB_PXA_SMARTPANEL */ 1319 1320 static void setup_parallel_timing(struct pxafb_info *fbi, 1321 struct fb_var_screeninfo *var) 1322 { 1323 unsigned int lines_per_panel, pcd = get_pcd(fbi, var->pixclock); 1324 1325 fbi->reg_lccr1 = 1326 LCCR1_DisWdth(var->xres) + 1327 LCCR1_HorSnchWdth(var->hsync_len) + 1328 LCCR1_BegLnDel(var->left_margin) + 1329 LCCR1_EndLnDel(var->right_margin); 1330 1331 /* 1332 * If we have a dual scan LCD, we need to halve 1333 * the YRES parameter. 1334 */ 1335 lines_per_panel = var->yres; 1336 if ((fbi->lccr0 & LCCR0_SDS) == LCCR0_Dual) 1337 lines_per_panel /= 2; 1338 1339 fbi->reg_lccr2 = 1340 LCCR2_DisHght(lines_per_panel) + 1341 LCCR2_VrtSnchWdth(var->vsync_len) + 1342 LCCR2_BegFrmDel(var->upper_margin) + 1343 LCCR2_EndFrmDel(var->lower_margin); 1344 1345 fbi->reg_lccr3 = fbi->lccr3 | 1346 (var->sync & FB_SYNC_HOR_HIGH_ACT ? 1347 LCCR3_HorSnchH : LCCR3_HorSnchL) | 1348 (var->sync & FB_SYNC_VERT_HIGH_ACT ? 1349 LCCR3_VrtSnchH : LCCR3_VrtSnchL); 1350 1351 if (pcd) { 1352 fbi->reg_lccr3 |= LCCR3_PixClkDiv(pcd); 1353 set_hsync_time(fbi, pcd); 1354 } 1355 } 1356 1357 /* 1358 * pxafb_activate_var(): 1359 * Configures LCD Controller based on entries in var parameter. 1360 * Settings are only written to the controller if changes were made. 1361 */ 1362 static int pxafb_activate_var(struct fb_var_screeninfo *var, 1363 struct pxafb_info *fbi) 1364 { 1365 u_long flags; 1366 1367 /* Update shadow copy atomically */ 1368 local_irq_save(flags); 1369 1370 #ifdef CONFIG_FB_PXA_SMARTPANEL 1371 if (fbi->lccr0 & LCCR0_LCDT) 1372 setup_smart_timing(fbi, var); 1373 else 1374 #endif 1375 setup_parallel_timing(fbi, var); 1376 1377 setup_base_frame(fbi, var, 0); 1378 1379 fbi->reg_lccr0 = fbi->lccr0 | 1380 (LCCR0_LDM | LCCR0_SFM | LCCR0_IUM | LCCR0_EFM | 1381 LCCR0_QDM | LCCR0_BM | LCCR0_OUM); 1382 1383 fbi->reg_lccr3 |= pxafb_var_to_lccr3(var); 1384 1385 fbi->reg_lccr4 = lcd_readl(fbi, LCCR4) & ~LCCR4_PAL_FOR_MASK; 1386 fbi->reg_lccr4 |= (fbi->lccr4 & LCCR4_PAL_FOR_MASK); 1387 local_irq_restore(flags); 1388 1389 /* 1390 * Only update the registers if the controller is enabled 1391 * and something has changed. 1392 */ 1393 if ((lcd_readl(fbi, LCCR0) != fbi->reg_lccr0) || 1394 (lcd_readl(fbi, LCCR1) != fbi->reg_lccr1) || 1395 (lcd_readl(fbi, LCCR2) != fbi->reg_lccr2) || 1396 (lcd_readl(fbi, LCCR3) != fbi->reg_lccr3) || 1397 (lcd_readl(fbi, LCCR4) != fbi->reg_lccr4) || 1398 (lcd_readl(fbi, FDADR0) != fbi->fdadr[0]) || 1399 ((fbi->lccr0 & LCCR0_SDS) && 1400 (lcd_readl(fbi, FDADR1) != fbi->fdadr[1]))) 1401 pxafb_schedule_work(fbi, C_REENABLE); 1402 1403 return 0; 1404 } 1405 1406 /* 1407 * NOTE! The following functions are purely helpers for set_ctrlr_state. 1408 * Do not call them directly; set_ctrlr_state does the correct serialisation 1409 * to ensure that things happen in the right way 100% of time time. 1410 * -- rmk 1411 */ 1412 static inline void __pxafb_backlight_power(struct pxafb_info *fbi, int on) 1413 { 1414 pr_debug("pxafb: backlight o%s\n", on ? "n" : "ff"); 1415 1416 if (fbi->backlight_power) 1417 fbi->backlight_power(on); 1418 } 1419 1420 static inline void __pxafb_lcd_power(struct pxafb_info *fbi, int on) 1421 { 1422 pr_debug("pxafb: LCD power o%s\n", on ? "n" : "ff"); 1423 1424 if (fbi->lcd_power) 1425 fbi->lcd_power(on, &fbi->fb.var); 1426 } 1427 1428 static void pxafb_enable_controller(struct pxafb_info *fbi) 1429 { 1430 pr_debug("pxafb: Enabling LCD controller\n"); 1431 pr_debug("fdadr0 0x%08x\n", (unsigned int) fbi->fdadr[0]); 1432 pr_debug("fdadr1 0x%08x\n", (unsigned int) fbi->fdadr[1]); 1433 pr_debug("reg_lccr0 0x%08x\n", (unsigned int) fbi->reg_lccr0); 1434 pr_debug("reg_lccr1 0x%08x\n", (unsigned int) fbi->reg_lccr1); 1435 pr_debug("reg_lccr2 0x%08x\n", (unsigned int) fbi->reg_lccr2); 1436 pr_debug("reg_lccr3 0x%08x\n", (unsigned int) fbi->reg_lccr3); 1437 1438 /* enable LCD controller clock */ 1439 if (clk_prepare_enable(fbi->clk)) { 1440 pr_err("%s: Failed to prepare clock\n", __func__); 1441 return; 1442 } 1443 1444 if (fbi->lccr0 & LCCR0_LCDT) 1445 return; 1446 1447 /* Sequence from 11.7.10 */ 1448 lcd_writel(fbi, LCCR4, fbi->reg_lccr4); 1449 lcd_writel(fbi, LCCR3, fbi->reg_lccr3); 1450 lcd_writel(fbi, LCCR2, fbi->reg_lccr2); 1451 lcd_writel(fbi, LCCR1, fbi->reg_lccr1); 1452 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 & ~LCCR0_ENB); 1453 1454 lcd_writel(fbi, FDADR0, fbi->fdadr[0]); 1455 if (fbi->lccr0 & LCCR0_SDS) 1456 lcd_writel(fbi, FDADR1, fbi->fdadr[1]); 1457 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 | LCCR0_ENB); 1458 } 1459 1460 static void pxafb_disable_controller(struct pxafb_info *fbi) 1461 { 1462 uint32_t lccr0; 1463 1464 #ifdef CONFIG_FB_PXA_SMARTPANEL 1465 if (fbi->lccr0 & LCCR0_LCDT) { 1466 wait_for_completion_timeout(&fbi->refresh_done, 1467 msecs_to_jiffies(200)); 1468 return; 1469 } 1470 #endif 1471 1472 /* Clear LCD Status Register */ 1473 lcd_writel(fbi, LCSR, 0xffffffff); 1474 1475 lccr0 = lcd_readl(fbi, LCCR0) & ~LCCR0_LDM; 1476 lcd_writel(fbi, LCCR0, lccr0); 1477 lcd_writel(fbi, LCCR0, lccr0 | LCCR0_DIS); 1478 1479 wait_for_completion_timeout(&fbi->disable_done, msecs_to_jiffies(200)); 1480 1481 /* disable LCD controller clock */ 1482 clk_disable_unprepare(fbi->clk); 1483 } 1484 1485 /* 1486 * pxafb_handle_irq: Handle 'LCD DONE' interrupts. 1487 */ 1488 static irqreturn_t pxafb_handle_irq(int irq, void *dev_id) 1489 { 1490 struct pxafb_info *fbi = dev_id; 1491 unsigned int lccr0, lcsr; 1492 1493 lcsr = lcd_readl(fbi, LCSR); 1494 if (lcsr & LCSR_LDD) { 1495 lccr0 = lcd_readl(fbi, LCCR0); 1496 lcd_writel(fbi, LCCR0, lccr0 | LCCR0_LDM); 1497 complete(&fbi->disable_done); 1498 } 1499 1500 #ifdef CONFIG_FB_PXA_SMARTPANEL 1501 if (lcsr & LCSR_CMD_INT) 1502 complete(&fbi->command_done); 1503 #endif 1504 lcd_writel(fbi, LCSR, lcsr); 1505 1506 #ifdef CONFIG_FB_PXA_OVERLAY 1507 { 1508 unsigned int lcsr1 = lcd_readl(fbi, LCSR1); 1509 if (lcsr1 & LCSR1_BS(1)) 1510 complete(&fbi->overlay[0].branch_done); 1511 1512 if (lcsr1 & LCSR1_BS(2)) 1513 complete(&fbi->overlay[1].branch_done); 1514 1515 lcd_writel(fbi, LCSR1, lcsr1); 1516 } 1517 #endif 1518 return IRQ_HANDLED; 1519 } 1520 1521 /* 1522 * This function must be called from task context only, since it will 1523 * sleep when disabling the LCD controller, or if we get two contending 1524 * processes trying to alter state. 1525 */ 1526 static void set_ctrlr_state(struct pxafb_info *fbi, u_int state) 1527 { 1528 u_int old_state; 1529 1530 mutex_lock(&fbi->ctrlr_lock); 1531 1532 old_state = fbi->state; 1533 1534 /* 1535 * Hack around fbcon initialisation. 1536 */ 1537 if (old_state == C_STARTUP && state == C_REENABLE) 1538 state = C_ENABLE; 1539 1540 switch (state) { 1541 case C_DISABLE_CLKCHANGE: 1542 /* 1543 * Disable controller for clock change. If the 1544 * controller is already disabled, then do nothing. 1545 */ 1546 if (old_state != C_DISABLE && old_state != C_DISABLE_PM) { 1547 fbi->state = state; 1548 /* TODO __pxafb_lcd_power(fbi, 0); */ 1549 pxafb_disable_controller(fbi); 1550 } 1551 break; 1552 1553 case C_DISABLE_PM: 1554 case C_DISABLE: 1555 /* 1556 * Disable controller 1557 */ 1558 if (old_state != C_DISABLE) { 1559 fbi->state = state; 1560 __pxafb_backlight_power(fbi, 0); 1561 __pxafb_lcd_power(fbi, 0); 1562 if (old_state != C_DISABLE_CLKCHANGE) 1563 pxafb_disable_controller(fbi); 1564 } 1565 break; 1566 1567 case C_ENABLE_CLKCHANGE: 1568 /* 1569 * Enable the controller after clock change. Only 1570 * do this if we were disabled for the clock change. 1571 */ 1572 if (old_state == C_DISABLE_CLKCHANGE) { 1573 fbi->state = C_ENABLE; 1574 pxafb_enable_controller(fbi); 1575 /* TODO __pxafb_lcd_power(fbi, 1); */ 1576 } 1577 break; 1578 1579 case C_REENABLE: 1580 /* 1581 * Re-enable the controller only if it was already 1582 * enabled. This is so we reprogram the control 1583 * registers. 1584 */ 1585 if (old_state == C_ENABLE) { 1586 __pxafb_lcd_power(fbi, 0); 1587 pxafb_disable_controller(fbi); 1588 pxafb_enable_controller(fbi); 1589 __pxafb_lcd_power(fbi, 1); 1590 } 1591 break; 1592 1593 case C_ENABLE_PM: 1594 /* 1595 * Re-enable the controller after PM. This is not 1596 * perfect - think about the case where we were doing 1597 * a clock change, and we suspended half-way through. 1598 */ 1599 if (old_state != C_DISABLE_PM) 1600 break; 1601 /* fall through */ 1602 1603 case C_ENABLE: 1604 /* 1605 * Power up the LCD screen, enable controller, and 1606 * turn on the backlight. 1607 */ 1608 if (old_state != C_ENABLE) { 1609 fbi->state = C_ENABLE; 1610 pxafb_enable_controller(fbi); 1611 __pxafb_lcd_power(fbi, 1); 1612 __pxafb_backlight_power(fbi, 1); 1613 } 1614 break; 1615 } 1616 mutex_unlock(&fbi->ctrlr_lock); 1617 } 1618 1619 /* 1620 * Our LCD controller task (which is called when we blank or unblank) 1621 * via keventd. 1622 */ 1623 static void pxafb_task(struct work_struct *work) 1624 { 1625 struct pxafb_info *fbi = 1626 container_of(work, struct pxafb_info, task); 1627 u_int state = xchg(&fbi->task_state, -1); 1628 1629 set_ctrlr_state(fbi, state); 1630 } 1631 1632 #ifdef CONFIG_CPU_FREQ 1633 /* 1634 * CPU clock speed change handler. We need to adjust the LCD timing 1635 * parameters when the CPU clock is adjusted by the power management 1636 * subsystem. 1637 * 1638 * TODO: Determine why f->new != 10*get_lclk_frequency_10khz() 1639 */ 1640 static int 1641 pxafb_freq_transition(struct notifier_block *nb, unsigned long val, void *data) 1642 { 1643 struct pxafb_info *fbi = TO_INF(nb, freq_transition); 1644 /* TODO struct cpufreq_freqs *f = data; */ 1645 u_int pcd; 1646 1647 switch (val) { 1648 case CPUFREQ_PRECHANGE: 1649 #ifdef CONFIG_FB_PXA_OVERLAY 1650 if (!(fbi->overlay[0].usage || fbi->overlay[1].usage)) 1651 #endif 1652 set_ctrlr_state(fbi, C_DISABLE_CLKCHANGE); 1653 break; 1654 1655 case CPUFREQ_POSTCHANGE: 1656 pcd = get_pcd(fbi, fbi->fb.var.pixclock); 1657 set_hsync_time(fbi, pcd); 1658 fbi->reg_lccr3 = (fbi->reg_lccr3 & ~0xff) | 1659 LCCR3_PixClkDiv(pcd); 1660 set_ctrlr_state(fbi, C_ENABLE_CLKCHANGE); 1661 break; 1662 } 1663 return 0; 1664 } 1665 1666 static int 1667 pxafb_freq_policy(struct notifier_block *nb, unsigned long val, void *data) 1668 { 1669 struct pxafb_info *fbi = TO_INF(nb, freq_policy); 1670 struct fb_var_screeninfo *var = &fbi->fb.var; 1671 struct cpufreq_policy *policy = data; 1672 1673 switch (val) { 1674 case CPUFREQ_ADJUST: 1675 pr_debug("min dma period: %d ps, " 1676 "new clock %d kHz\n", pxafb_display_dma_period(var), 1677 policy->max); 1678 /* TODO: fill in min/max values */ 1679 break; 1680 } 1681 return 0; 1682 } 1683 #endif 1684 1685 #ifdef CONFIG_PM 1686 /* 1687 * Power management hooks. Note that we won't be called from IRQ context, 1688 * unlike the blank functions above, so we may sleep. 1689 */ 1690 static int pxafb_suspend(struct device *dev) 1691 { 1692 struct pxafb_info *fbi = dev_get_drvdata(dev); 1693 1694 set_ctrlr_state(fbi, C_DISABLE_PM); 1695 return 0; 1696 } 1697 1698 static int pxafb_resume(struct device *dev) 1699 { 1700 struct pxafb_info *fbi = dev_get_drvdata(dev); 1701 1702 set_ctrlr_state(fbi, C_ENABLE_PM); 1703 return 0; 1704 } 1705 1706 static const struct dev_pm_ops pxafb_pm_ops = { 1707 .suspend = pxafb_suspend, 1708 .resume = pxafb_resume, 1709 }; 1710 #endif 1711 1712 static int pxafb_init_video_memory(struct pxafb_info *fbi) 1713 { 1714 int size = PAGE_ALIGN(fbi->video_mem_size); 1715 1716 fbi->video_mem = alloc_pages_exact(size, GFP_KERNEL | __GFP_ZERO); 1717 if (fbi->video_mem == NULL) 1718 return -ENOMEM; 1719 1720 fbi->video_mem_phys = virt_to_phys(fbi->video_mem); 1721 fbi->video_mem_size = size; 1722 1723 fbi->fb.fix.smem_start = fbi->video_mem_phys; 1724 fbi->fb.fix.smem_len = fbi->video_mem_size; 1725 fbi->fb.screen_base = fbi->video_mem; 1726 1727 return fbi->video_mem ? 0 : -ENOMEM; 1728 } 1729 1730 static void pxafb_decode_mach_info(struct pxafb_info *fbi, 1731 struct pxafb_mach_info *inf) 1732 { 1733 unsigned int lcd_conn = inf->lcd_conn; 1734 struct pxafb_mode_info *m; 1735 int i; 1736 1737 fbi->cmap_inverse = inf->cmap_inverse; 1738 fbi->cmap_static = inf->cmap_static; 1739 fbi->lccr4 = inf->lccr4; 1740 1741 switch (lcd_conn & LCD_TYPE_MASK) { 1742 case LCD_TYPE_MONO_STN: 1743 fbi->lccr0 = LCCR0_CMS; 1744 break; 1745 case LCD_TYPE_MONO_DSTN: 1746 fbi->lccr0 = LCCR0_CMS | LCCR0_SDS; 1747 break; 1748 case LCD_TYPE_COLOR_STN: 1749 fbi->lccr0 = 0; 1750 break; 1751 case LCD_TYPE_COLOR_DSTN: 1752 fbi->lccr0 = LCCR0_SDS; 1753 break; 1754 case LCD_TYPE_COLOR_TFT: 1755 fbi->lccr0 = LCCR0_PAS; 1756 break; 1757 case LCD_TYPE_SMART_PANEL: 1758 fbi->lccr0 = LCCR0_LCDT | LCCR0_PAS; 1759 break; 1760 default: 1761 /* fall back to backward compatibility way */ 1762 fbi->lccr0 = inf->lccr0; 1763 fbi->lccr3 = inf->lccr3; 1764 goto decode_mode; 1765 } 1766 1767 if (lcd_conn == LCD_MONO_STN_8BPP) 1768 fbi->lccr0 |= LCCR0_DPD; 1769 1770 fbi->lccr0 |= (lcd_conn & LCD_ALTERNATE_MAPPING) ? LCCR0_LDDALT : 0; 1771 1772 fbi->lccr3 = LCCR3_Acb((inf->lcd_conn >> 10) & 0xff); 1773 fbi->lccr3 |= (lcd_conn & LCD_BIAS_ACTIVE_LOW) ? LCCR3_OEP : 0; 1774 fbi->lccr3 |= (lcd_conn & LCD_PCLK_EDGE_FALL) ? LCCR3_PCP : 0; 1775 1776 decode_mode: 1777 pxafb_setmode(&fbi->fb.var, &inf->modes[0]); 1778 1779 /* decide video memory size as follows: 1780 * 1. default to mode of maximum resolution 1781 * 2. allow platform to override 1782 * 3. allow module parameter to override 1783 */ 1784 for (i = 0, m = &inf->modes[0]; i < inf->num_modes; i++, m++) 1785 fbi->video_mem_size = max_t(size_t, fbi->video_mem_size, 1786 m->xres * m->yres * m->bpp / 8); 1787 1788 if (inf->video_mem_size > fbi->video_mem_size) 1789 fbi->video_mem_size = inf->video_mem_size; 1790 1791 if (video_mem_size > fbi->video_mem_size) 1792 fbi->video_mem_size = video_mem_size; 1793 } 1794 1795 static struct pxafb_info *pxafb_init_fbinfo(struct device *dev, 1796 struct pxafb_mach_info *inf) 1797 { 1798 struct pxafb_info *fbi; 1799 void *addr; 1800 1801 /* Alloc the pxafb_info and pseudo_palette in one step */ 1802 fbi = kmalloc(sizeof(struct pxafb_info) + sizeof(u32) * 16, GFP_KERNEL); 1803 if (!fbi) 1804 return NULL; 1805 1806 memset(fbi, 0, sizeof(struct pxafb_info)); 1807 fbi->dev = dev; 1808 fbi->inf = inf; 1809 1810 fbi->clk = clk_get(dev, NULL); 1811 if (IS_ERR(fbi->clk)) { 1812 kfree(fbi); 1813 return NULL; 1814 } 1815 1816 strcpy(fbi->fb.fix.id, PXA_NAME); 1817 1818 fbi->fb.fix.type = FB_TYPE_PACKED_PIXELS; 1819 fbi->fb.fix.type_aux = 0; 1820 fbi->fb.fix.xpanstep = 0; 1821 fbi->fb.fix.ypanstep = 1; 1822 fbi->fb.fix.ywrapstep = 0; 1823 fbi->fb.fix.accel = FB_ACCEL_NONE; 1824 1825 fbi->fb.var.nonstd = 0; 1826 fbi->fb.var.activate = FB_ACTIVATE_NOW; 1827 fbi->fb.var.height = -1; 1828 fbi->fb.var.width = -1; 1829 fbi->fb.var.accel_flags = FB_ACCELF_TEXT; 1830 fbi->fb.var.vmode = FB_VMODE_NONINTERLACED; 1831 1832 fbi->fb.fbops = &pxafb_ops; 1833 fbi->fb.flags = FBINFO_DEFAULT; 1834 fbi->fb.node = -1; 1835 1836 addr = fbi; 1837 addr = addr + sizeof(struct pxafb_info); 1838 fbi->fb.pseudo_palette = addr; 1839 1840 fbi->state = C_STARTUP; 1841 fbi->task_state = (u_char)-1; 1842 1843 pxafb_decode_mach_info(fbi, inf); 1844 1845 #ifdef CONFIG_FB_PXA_OVERLAY 1846 /* place overlay(s) on top of base */ 1847 if (pxafb_overlay_supported()) 1848 fbi->lccr0 |= LCCR0_OUC; 1849 #endif 1850 1851 init_waitqueue_head(&fbi->ctrlr_wait); 1852 INIT_WORK(&fbi->task, pxafb_task); 1853 mutex_init(&fbi->ctrlr_lock); 1854 init_completion(&fbi->disable_done); 1855 1856 return fbi; 1857 } 1858 1859 #ifdef CONFIG_FB_PXA_PARAMETERS 1860 static int parse_opt_mode(struct device *dev, const char *this_opt, 1861 struct pxafb_mach_info *inf) 1862 { 1863 const char *name = this_opt+5; 1864 unsigned int namelen = strlen(name); 1865 int res_specified = 0, bpp_specified = 0; 1866 unsigned int xres = 0, yres = 0, bpp = 0; 1867 int yres_specified = 0; 1868 int i; 1869 for (i = namelen-1; i >= 0; i--) { 1870 switch (name[i]) { 1871 case '-': 1872 namelen = i; 1873 if (!bpp_specified && !yres_specified) { 1874 bpp = simple_strtoul(&name[i+1], NULL, 0); 1875 bpp_specified = 1; 1876 } else 1877 goto done; 1878 break; 1879 case 'x': 1880 if (!yres_specified) { 1881 yres = simple_strtoul(&name[i+1], NULL, 0); 1882 yres_specified = 1; 1883 } else 1884 goto done; 1885 break; 1886 case '0' ... '9': 1887 break; 1888 default: 1889 goto done; 1890 } 1891 } 1892 if (i < 0 && yres_specified) { 1893 xres = simple_strtoul(name, NULL, 0); 1894 res_specified = 1; 1895 } 1896 done: 1897 if (res_specified) { 1898 dev_info(dev, "overriding resolution: %dx%d\n", xres, yres); 1899 inf->modes[0].xres = xres; inf->modes[0].yres = yres; 1900 } 1901 if (bpp_specified) 1902 switch (bpp) { 1903 case 1: 1904 case 2: 1905 case 4: 1906 case 8: 1907 case 16: 1908 inf->modes[0].bpp = bpp; 1909 dev_info(dev, "overriding bit depth: %d\n", bpp); 1910 break; 1911 default: 1912 dev_err(dev, "Depth %d is not valid\n", bpp); 1913 return -EINVAL; 1914 } 1915 return 0; 1916 } 1917 1918 static int parse_opt(struct device *dev, char *this_opt, 1919 struct pxafb_mach_info *inf) 1920 { 1921 struct pxafb_mode_info *mode = &inf->modes[0]; 1922 char s[64]; 1923 1924 s[0] = '\0'; 1925 1926 if (!strncmp(this_opt, "vmem:", 5)) { 1927 video_mem_size = memparse(this_opt + 5, NULL); 1928 } else if (!strncmp(this_opt, "mode:", 5)) { 1929 return parse_opt_mode(dev, this_opt, inf); 1930 } else if (!strncmp(this_opt, "pixclock:", 9)) { 1931 mode->pixclock = simple_strtoul(this_opt+9, NULL, 0); 1932 sprintf(s, "pixclock: %ld\n", mode->pixclock); 1933 } else if (!strncmp(this_opt, "left:", 5)) { 1934 mode->left_margin = simple_strtoul(this_opt+5, NULL, 0); 1935 sprintf(s, "left: %u\n", mode->left_margin); 1936 } else if (!strncmp(this_opt, "right:", 6)) { 1937 mode->right_margin = simple_strtoul(this_opt+6, NULL, 0); 1938 sprintf(s, "right: %u\n", mode->right_margin); 1939 } else if (!strncmp(this_opt, "upper:", 6)) { 1940 mode->upper_margin = simple_strtoul(this_opt+6, NULL, 0); 1941 sprintf(s, "upper: %u\n", mode->upper_margin); 1942 } else if (!strncmp(this_opt, "lower:", 6)) { 1943 mode->lower_margin = simple_strtoul(this_opt+6, NULL, 0); 1944 sprintf(s, "lower: %u\n", mode->lower_margin); 1945 } else if (!strncmp(this_opt, "hsynclen:", 9)) { 1946 mode->hsync_len = simple_strtoul(this_opt+9, NULL, 0); 1947 sprintf(s, "hsynclen: %u\n", mode->hsync_len); 1948 } else if (!strncmp(this_opt, "vsynclen:", 9)) { 1949 mode->vsync_len = simple_strtoul(this_opt+9, NULL, 0); 1950 sprintf(s, "vsynclen: %u\n", mode->vsync_len); 1951 } else if (!strncmp(this_opt, "hsync:", 6)) { 1952 if (simple_strtoul(this_opt+6, NULL, 0) == 0) { 1953 sprintf(s, "hsync: Active Low\n"); 1954 mode->sync &= ~FB_SYNC_HOR_HIGH_ACT; 1955 } else { 1956 sprintf(s, "hsync: Active High\n"); 1957 mode->sync |= FB_SYNC_HOR_HIGH_ACT; 1958 } 1959 } else if (!strncmp(this_opt, "vsync:", 6)) { 1960 if (simple_strtoul(this_opt+6, NULL, 0) == 0) { 1961 sprintf(s, "vsync: Active Low\n"); 1962 mode->sync &= ~FB_SYNC_VERT_HIGH_ACT; 1963 } else { 1964 sprintf(s, "vsync: Active High\n"); 1965 mode->sync |= FB_SYNC_VERT_HIGH_ACT; 1966 } 1967 } else if (!strncmp(this_opt, "dpc:", 4)) { 1968 if (simple_strtoul(this_opt+4, NULL, 0) == 0) { 1969 sprintf(s, "double pixel clock: false\n"); 1970 inf->lccr3 &= ~LCCR3_DPC; 1971 } else { 1972 sprintf(s, "double pixel clock: true\n"); 1973 inf->lccr3 |= LCCR3_DPC; 1974 } 1975 } else if (!strncmp(this_opt, "outputen:", 9)) { 1976 if (simple_strtoul(this_opt+9, NULL, 0) == 0) { 1977 sprintf(s, "output enable: active low\n"); 1978 inf->lccr3 = (inf->lccr3 & ~LCCR3_OEP) | LCCR3_OutEnL; 1979 } else { 1980 sprintf(s, "output enable: active high\n"); 1981 inf->lccr3 = (inf->lccr3 & ~LCCR3_OEP) | LCCR3_OutEnH; 1982 } 1983 } else if (!strncmp(this_opt, "pixclockpol:", 12)) { 1984 if (simple_strtoul(this_opt+12, NULL, 0) == 0) { 1985 sprintf(s, "pixel clock polarity: falling edge\n"); 1986 inf->lccr3 = (inf->lccr3 & ~LCCR3_PCP) | LCCR3_PixFlEdg; 1987 } else { 1988 sprintf(s, "pixel clock polarity: rising edge\n"); 1989 inf->lccr3 = (inf->lccr3 & ~LCCR3_PCP) | LCCR3_PixRsEdg; 1990 } 1991 } else if (!strncmp(this_opt, "color", 5)) { 1992 inf->lccr0 = (inf->lccr0 & ~LCCR0_CMS) | LCCR0_Color; 1993 } else if (!strncmp(this_opt, "mono", 4)) { 1994 inf->lccr0 = (inf->lccr0 & ~LCCR0_CMS) | LCCR0_Mono; 1995 } else if (!strncmp(this_opt, "active", 6)) { 1996 inf->lccr0 = (inf->lccr0 & ~LCCR0_PAS) | LCCR0_Act; 1997 } else if (!strncmp(this_opt, "passive", 7)) { 1998 inf->lccr0 = (inf->lccr0 & ~LCCR0_PAS) | LCCR0_Pas; 1999 } else if (!strncmp(this_opt, "single", 6)) { 2000 inf->lccr0 = (inf->lccr0 & ~LCCR0_SDS) | LCCR0_Sngl; 2001 } else if (!strncmp(this_opt, "dual", 4)) { 2002 inf->lccr0 = (inf->lccr0 & ~LCCR0_SDS) | LCCR0_Dual; 2003 } else if (!strncmp(this_opt, "4pix", 4)) { 2004 inf->lccr0 = (inf->lccr0 & ~LCCR0_DPD) | LCCR0_4PixMono; 2005 } else if (!strncmp(this_opt, "8pix", 4)) { 2006 inf->lccr0 = (inf->lccr0 & ~LCCR0_DPD) | LCCR0_8PixMono; 2007 } else { 2008 dev_err(dev, "unknown option: %s\n", this_opt); 2009 return -EINVAL; 2010 } 2011 2012 if (s[0] != '\0') 2013 dev_info(dev, "override %s", s); 2014 2015 return 0; 2016 } 2017 2018 static int pxafb_parse_options(struct device *dev, char *options, 2019 struct pxafb_mach_info *inf) 2020 { 2021 char *this_opt; 2022 int ret; 2023 2024 if (!options || !*options) 2025 return 0; 2026 2027 dev_dbg(dev, "options are \"%s\"\n", options ? options : "null"); 2028 2029 /* could be made table driven or similar?... */ 2030 while ((this_opt = strsep(&options, ",")) != NULL) { 2031 ret = parse_opt(dev, this_opt, inf); 2032 if (ret) 2033 return ret; 2034 } 2035 return 0; 2036 } 2037 2038 static char g_options[256] = ""; 2039 2040 #ifndef MODULE 2041 static int __init pxafb_setup_options(void) 2042 { 2043 char *options = NULL; 2044 2045 if (fb_get_options("pxafb", &options)) 2046 return -ENODEV; 2047 2048 if (options) 2049 strlcpy(g_options, options, sizeof(g_options)); 2050 2051 return 0; 2052 } 2053 #else 2054 #define pxafb_setup_options() (0) 2055 2056 module_param_string(options, g_options, sizeof(g_options), 0); 2057 MODULE_PARM_DESC(options, "LCD parameters (see Documentation/fb/pxafb.txt)"); 2058 #endif 2059 2060 #else 2061 #define pxafb_parse_options(...) (0) 2062 #define pxafb_setup_options() (0) 2063 #endif 2064 2065 #ifdef DEBUG_VAR 2066 /* Check for various illegal bit-combinations. Currently only 2067 * a warning is given. */ 2068 static void pxafb_check_options(struct device *dev, struct pxafb_mach_info *inf) 2069 { 2070 if (inf->lcd_conn) 2071 return; 2072 2073 if (inf->lccr0 & LCCR0_INVALID_CONFIG_MASK) 2074 dev_warn(dev, "machine LCCR0 setting contains " 2075 "illegal bits: %08x\n", 2076 inf->lccr0 & LCCR0_INVALID_CONFIG_MASK); 2077 if (inf->lccr3 & LCCR3_INVALID_CONFIG_MASK) 2078 dev_warn(dev, "machine LCCR3 setting contains " 2079 "illegal bits: %08x\n", 2080 inf->lccr3 & LCCR3_INVALID_CONFIG_MASK); 2081 if (inf->lccr0 & LCCR0_DPD && 2082 ((inf->lccr0 & LCCR0_PAS) != LCCR0_Pas || 2083 (inf->lccr0 & LCCR0_SDS) != LCCR0_Sngl || 2084 (inf->lccr0 & LCCR0_CMS) != LCCR0_Mono)) 2085 dev_warn(dev, "Double Pixel Data (DPD) mode is " 2086 "only valid in passive mono" 2087 " single panel mode\n"); 2088 if ((inf->lccr0 & LCCR0_PAS) == LCCR0_Act && 2089 (inf->lccr0 & LCCR0_SDS) == LCCR0_Dual) 2090 dev_warn(dev, "Dual panel only valid in passive mode\n"); 2091 if ((inf->lccr0 & LCCR0_PAS) == LCCR0_Pas && 2092 (inf->modes->upper_margin || inf->modes->lower_margin)) 2093 dev_warn(dev, "Upper and lower margins must be 0 in " 2094 "passive mode\n"); 2095 } 2096 #else 2097 #define pxafb_check_options(...) do {} while (0) 2098 #endif 2099 2100 #if defined(CONFIG_OF) 2101 static const char * const lcd_types[] = { 2102 "unknown", "mono-stn", "mono-dstn", "color-stn", "color-dstn", 2103 "color-tft", "smart-panel", NULL 2104 }; 2105 2106 static int of_get_pxafb_display(struct device *dev, struct device_node *disp, 2107 struct pxafb_mach_info *info, u32 bus_width) 2108 { 2109 struct display_timings *timings; 2110 struct videomode vm; 2111 int i, ret = -EINVAL; 2112 const char *s; 2113 2114 ret = of_property_read_string(disp, "lcd-type", &s); 2115 if (ret) 2116 s = "color-tft"; 2117 2118 for (i = 0; lcd_types[i]; i++) 2119 if (!strcmp(s, lcd_types[i])) 2120 break; 2121 if (!i || !lcd_types[i]) { 2122 dev_err(dev, "lcd-type %s is unknown\n", s); 2123 return -EINVAL; 2124 } 2125 info->lcd_conn |= LCD_CONN_TYPE(i); 2126 info->lcd_conn |= LCD_CONN_WIDTH(bus_width); 2127 2128 timings = of_get_display_timings(disp); 2129 if (!timings) 2130 return -EINVAL; 2131 2132 ret = -ENOMEM; 2133 info->modes = kmalloc_array(timings->num_timings, 2134 sizeof(info->modes[0]), GFP_KERNEL); 2135 if (!info->modes) 2136 goto out; 2137 info->num_modes = timings->num_timings; 2138 2139 for (i = 0; i < timings->num_timings; i++) { 2140 ret = videomode_from_timings(timings, &vm, i); 2141 if (ret) { 2142 dev_err(dev, "videomode_from_timings %d failed: %d\n", 2143 i, ret); 2144 goto out; 2145 } 2146 if (vm.flags & DISPLAY_FLAGS_PIXDATA_POSEDGE) 2147 info->lcd_conn |= LCD_PCLK_EDGE_RISE; 2148 if (vm.flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE) 2149 info->lcd_conn |= LCD_PCLK_EDGE_FALL; 2150 if (vm.flags & DISPLAY_FLAGS_DE_HIGH) 2151 info->lcd_conn |= LCD_BIAS_ACTIVE_HIGH; 2152 if (vm.flags & DISPLAY_FLAGS_DE_LOW) 2153 info->lcd_conn |= LCD_BIAS_ACTIVE_LOW; 2154 if (vm.flags & DISPLAY_FLAGS_HSYNC_HIGH) 2155 info->modes[i].sync |= FB_SYNC_HOR_HIGH_ACT; 2156 if (vm.flags & DISPLAY_FLAGS_VSYNC_HIGH) 2157 info->modes[i].sync |= FB_SYNC_VERT_HIGH_ACT; 2158 2159 info->modes[i].pixclock = 1000000000UL / (vm.pixelclock / 1000); 2160 info->modes[i].xres = vm.hactive; 2161 info->modes[i].yres = vm.vactive; 2162 info->modes[i].hsync_len = vm.hsync_len; 2163 info->modes[i].left_margin = vm.hback_porch; 2164 info->modes[i].right_margin = vm.hfront_porch; 2165 info->modes[i].vsync_len = vm.vsync_len; 2166 info->modes[i].upper_margin = vm.vback_porch; 2167 info->modes[i].lower_margin = vm.vfront_porch; 2168 } 2169 ret = 0; 2170 2171 out: 2172 display_timings_release(timings); 2173 return ret; 2174 } 2175 2176 static int of_get_pxafb_mode_info(struct device *dev, 2177 struct pxafb_mach_info *info) 2178 { 2179 struct device_node *display, *np; 2180 u32 bus_width; 2181 int ret, i; 2182 2183 np = of_graph_get_next_endpoint(dev->of_node, NULL); 2184 if (!np) { 2185 dev_err(dev, "could not find endpoint\n"); 2186 return -EINVAL; 2187 } 2188 ret = of_property_read_u32(np, "bus-width", &bus_width); 2189 if (ret) { 2190 dev_err(dev, "no bus-width specified: %d\n", ret); 2191 of_node_put(np); 2192 return ret; 2193 } 2194 2195 display = of_graph_get_remote_port_parent(np); 2196 of_node_put(np); 2197 if (!display) { 2198 dev_err(dev, "no display defined\n"); 2199 return -EINVAL; 2200 } 2201 2202 ret = of_get_pxafb_display(dev, display, info, bus_width); 2203 of_node_put(display); 2204 if (ret) 2205 return ret; 2206 2207 for (i = 0; i < info->num_modes; i++) 2208 info->modes[i].bpp = bus_width; 2209 2210 return 0; 2211 } 2212 2213 static struct pxafb_mach_info *of_pxafb_of_mach_info(struct device *dev) 2214 { 2215 int ret; 2216 struct pxafb_mach_info *info; 2217 2218 if (!dev->of_node) 2219 return NULL; 2220 info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL); 2221 if (!info) 2222 return ERR_PTR(-ENOMEM); 2223 ret = of_get_pxafb_mode_info(dev, info); 2224 if (ret) { 2225 kfree(info->modes); 2226 return ERR_PTR(ret); 2227 } 2228 2229 /* 2230 * On purpose, neither lccrX registers nor video memory size can be 2231 * specified through device-tree, they are considered more a debug hack 2232 * available through command line. 2233 */ 2234 return info; 2235 } 2236 #else 2237 static struct pxafb_mach_info *of_pxafb_of_mach_info(struct device *dev) 2238 { 2239 return NULL; 2240 } 2241 #endif 2242 2243 static int pxafb_probe(struct platform_device *dev) 2244 { 2245 struct pxafb_info *fbi; 2246 struct pxafb_mach_info *inf, *pdata; 2247 struct resource *r; 2248 int i, irq, ret; 2249 2250 dev_dbg(&dev->dev, "pxafb_probe\n"); 2251 2252 ret = -ENOMEM; 2253 pdata = dev_get_platdata(&dev->dev); 2254 inf = devm_kmalloc(&dev->dev, sizeof(*inf), GFP_KERNEL); 2255 if (!inf) 2256 goto failed; 2257 2258 if (pdata) { 2259 *inf = *pdata; 2260 inf->modes = 2261 devm_kmalloc_array(&dev->dev, pdata->num_modes, 2262 sizeof(inf->modes[0]), GFP_KERNEL); 2263 if (!inf->modes) 2264 goto failed; 2265 for (i = 0; i < inf->num_modes; i++) 2266 inf->modes[i] = pdata->modes[i]; 2267 } 2268 2269 if (!pdata) 2270 inf = of_pxafb_of_mach_info(&dev->dev); 2271 if (IS_ERR_OR_NULL(inf)) 2272 goto failed; 2273 2274 ret = pxafb_parse_options(&dev->dev, g_options, inf); 2275 if (ret < 0) 2276 goto failed; 2277 2278 pxafb_check_options(&dev->dev, inf); 2279 2280 dev_dbg(&dev->dev, "got a %dx%dx%d LCD\n", 2281 inf->modes->xres, 2282 inf->modes->yres, 2283 inf->modes->bpp); 2284 if (inf->modes->xres == 0 || 2285 inf->modes->yres == 0 || 2286 inf->modes->bpp == 0) { 2287 dev_err(&dev->dev, "Invalid resolution or bit depth\n"); 2288 ret = -EINVAL; 2289 goto failed; 2290 } 2291 2292 fbi = pxafb_init_fbinfo(&dev->dev, inf); 2293 if (!fbi) { 2294 /* only reason for pxafb_init_fbinfo to fail is kmalloc */ 2295 dev_err(&dev->dev, "Failed to initialize framebuffer device\n"); 2296 ret = -ENOMEM; 2297 goto failed; 2298 } 2299 2300 if (cpu_is_pxa3xx() && inf->acceleration_enabled) 2301 fbi->fb.fix.accel = FB_ACCEL_PXA3XX; 2302 2303 fbi->backlight_power = inf->pxafb_backlight_power; 2304 fbi->lcd_power = inf->pxafb_lcd_power; 2305 2306 r = platform_get_resource(dev, IORESOURCE_MEM, 0); 2307 if (r == NULL) { 2308 dev_err(&dev->dev, "no I/O memory resource defined\n"); 2309 ret = -ENODEV; 2310 goto failed_fbi; 2311 } 2312 2313 r = request_mem_region(r->start, resource_size(r), dev->name); 2314 if (r == NULL) { 2315 dev_err(&dev->dev, "failed to request I/O memory\n"); 2316 ret = -EBUSY; 2317 goto failed_fbi; 2318 } 2319 2320 fbi->mmio_base = ioremap(r->start, resource_size(r)); 2321 if (fbi->mmio_base == NULL) { 2322 dev_err(&dev->dev, "failed to map I/O memory\n"); 2323 ret = -EBUSY; 2324 goto failed_free_res; 2325 } 2326 2327 fbi->dma_buff_size = PAGE_ALIGN(sizeof(struct pxafb_dma_buff)); 2328 fbi->dma_buff = dma_alloc_coherent(fbi->dev, fbi->dma_buff_size, 2329 &fbi->dma_buff_phys, GFP_KERNEL); 2330 if (fbi->dma_buff == NULL) { 2331 dev_err(&dev->dev, "failed to allocate memory for DMA\n"); 2332 ret = -ENOMEM; 2333 goto failed_free_io; 2334 } 2335 2336 ret = pxafb_init_video_memory(fbi); 2337 if (ret) { 2338 dev_err(&dev->dev, "Failed to allocate video RAM: %d\n", ret); 2339 ret = -ENOMEM; 2340 goto failed_free_dma; 2341 } 2342 2343 irq = platform_get_irq(dev, 0); 2344 if (irq < 0) { 2345 dev_err(&dev->dev, "no IRQ defined\n"); 2346 ret = -ENODEV; 2347 goto failed_free_mem; 2348 } 2349 2350 ret = request_irq(irq, pxafb_handle_irq, 0, "LCD", fbi); 2351 if (ret) { 2352 dev_err(&dev->dev, "request_irq failed: %d\n", ret); 2353 ret = -EBUSY; 2354 goto failed_free_mem; 2355 } 2356 2357 ret = pxafb_smart_init(fbi); 2358 if (ret) { 2359 dev_err(&dev->dev, "failed to initialize smartpanel\n"); 2360 goto failed_free_irq; 2361 } 2362 2363 /* 2364 * This makes sure that our colour bitfield 2365 * descriptors are correctly initialised. 2366 */ 2367 ret = pxafb_check_var(&fbi->fb.var, &fbi->fb); 2368 if (ret) { 2369 dev_err(&dev->dev, "failed to get suitable mode\n"); 2370 goto failed_free_irq; 2371 } 2372 2373 ret = pxafb_set_par(&fbi->fb); 2374 if (ret) { 2375 dev_err(&dev->dev, "Failed to set parameters\n"); 2376 goto failed_free_irq; 2377 } 2378 2379 platform_set_drvdata(dev, fbi); 2380 2381 ret = register_framebuffer(&fbi->fb); 2382 if (ret < 0) { 2383 dev_err(&dev->dev, 2384 "Failed to register framebuffer device: %d\n", ret); 2385 goto failed_free_cmap; 2386 } 2387 2388 pxafb_overlay_init(fbi); 2389 2390 #ifdef CONFIG_CPU_FREQ 2391 fbi->freq_transition.notifier_call = pxafb_freq_transition; 2392 fbi->freq_policy.notifier_call = pxafb_freq_policy; 2393 cpufreq_register_notifier(&fbi->freq_transition, 2394 CPUFREQ_TRANSITION_NOTIFIER); 2395 cpufreq_register_notifier(&fbi->freq_policy, 2396 CPUFREQ_POLICY_NOTIFIER); 2397 #endif 2398 2399 /* 2400 * Ok, now enable the LCD controller 2401 */ 2402 set_ctrlr_state(fbi, C_ENABLE); 2403 2404 return 0; 2405 2406 failed_free_cmap: 2407 if (fbi->fb.cmap.len) 2408 fb_dealloc_cmap(&fbi->fb.cmap); 2409 failed_free_irq: 2410 free_irq(irq, fbi); 2411 failed_free_mem: 2412 free_pages_exact(fbi->video_mem, fbi->video_mem_size); 2413 failed_free_dma: 2414 dma_free_coherent(&dev->dev, fbi->dma_buff_size, 2415 fbi->dma_buff, fbi->dma_buff_phys); 2416 failed_free_io: 2417 iounmap(fbi->mmio_base); 2418 failed_free_res: 2419 release_mem_region(r->start, resource_size(r)); 2420 failed_fbi: 2421 clk_put(fbi->clk); 2422 kfree(fbi); 2423 failed: 2424 return ret; 2425 } 2426 2427 static int pxafb_remove(struct platform_device *dev) 2428 { 2429 struct pxafb_info *fbi = platform_get_drvdata(dev); 2430 struct resource *r; 2431 int irq; 2432 struct fb_info *info; 2433 2434 if (!fbi) 2435 return 0; 2436 2437 info = &fbi->fb; 2438 2439 pxafb_overlay_exit(fbi); 2440 unregister_framebuffer(info); 2441 2442 pxafb_disable_controller(fbi); 2443 2444 if (fbi->fb.cmap.len) 2445 fb_dealloc_cmap(&fbi->fb.cmap); 2446 2447 irq = platform_get_irq(dev, 0); 2448 free_irq(irq, fbi); 2449 2450 free_pages_exact(fbi->video_mem, fbi->video_mem_size); 2451 2452 dma_free_wc(&dev->dev, fbi->dma_buff_size, fbi->dma_buff, 2453 fbi->dma_buff_phys); 2454 2455 iounmap(fbi->mmio_base); 2456 2457 r = platform_get_resource(dev, IORESOURCE_MEM, 0); 2458 release_mem_region(r->start, resource_size(r)); 2459 2460 clk_put(fbi->clk); 2461 kfree(fbi); 2462 2463 return 0; 2464 } 2465 2466 static const struct of_device_id pxafb_of_dev_id[] = { 2467 { .compatible = "marvell,pxa270-lcdc", }, 2468 { .compatible = "marvell,pxa300-lcdc", }, 2469 { .compatible = "marvell,pxa2xx-lcdc", }, 2470 { /* sentinel */ } 2471 }; 2472 MODULE_DEVICE_TABLE(of, pxafb_of_dev_id); 2473 2474 static struct platform_driver pxafb_driver = { 2475 .probe = pxafb_probe, 2476 .remove = pxafb_remove, 2477 .driver = { 2478 .name = "pxa2xx-fb", 2479 .of_match_table = pxafb_of_dev_id, 2480 #ifdef CONFIG_PM 2481 .pm = &pxafb_pm_ops, 2482 #endif 2483 }, 2484 }; 2485 2486 static int __init pxafb_init(void) 2487 { 2488 if (pxafb_setup_options()) 2489 return -EINVAL; 2490 2491 return platform_driver_register(&pxafb_driver); 2492 } 2493 2494 static void __exit pxafb_exit(void) 2495 { 2496 platform_driver_unregister(&pxafb_driver); 2497 } 2498 2499 module_init(pxafb_init); 2500 module_exit(pxafb_exit); 2501 2502 MODULE_DESCRIPTION("loadable framebuffer driver for PXA"); 2503 MODULE_LICENSE("GPL"); 2504