1 #ifndef __PXA168FB_H__ 2 #define __PXA168FB_H__ 3 4 /* ------------< LCD register >------------ */ 5 /* Video Frame 0&1 start address registers */ 6 #define LCD_SPU_DMA_START_ADDR_Y0 0x00C0 7 #define LCD_SPU_DMA_START_ADDR_U0 0x00C4 8 #define LCD_SPU_DMA_START_ADDR_V0 0x00C8 9 #define LCD_CFG_DMA_START_ADDR_0 0x00CC /* Cmd address */ 10 #define LCD_SPU_DMA_START_ADDR_Y1 0x00D0 11 #define LCD_SPU_DMA_START_ADDR_U1 0x00D4 12 #define LCD_SPU_DMA_START_ADDR_V1 0x00D8 13 #define LCD_CFG_DMA_START_ADDR_1 0x00DC /* Cmd address */ 14 15 /* YC & UV Pitch */ 16 #define LCD_SPU_DMA_PITCH_YC 0x00E0 17 #define SPU_DMA_PITCH_C(c) ((c) << 16) 18 #define SPU_DMA_PITCH_Y(y) (y) 19 #define LCD_SPU_DMA_PITCH_UV 0x00E4 20 #define SPU_DMA_PITCH_V(v) ((v) << 16) 21 #define SPU_DMA_PITCH_U(u) (u) 22 23 /* Video Starting Point on Screen Register */ 24 #define LCD_SPUT_DMA_OVSA_HPXL_VLN 0x00E8 25 #define CFG_DMA_OVSA_VLN(y) ((y) << 16) /* 0~0xfff */ 26 #define CFG_DMA_OVSA_HPXL(x) (x) /* 0~0xfff */ 27 28 /* Video Size Register */ 29 #define LCD_SPU_DMA_HPXL_VLN 0x00EC 30 #define CFG_DMA_VLN(y) ((y) << 16) 31 #define CFG_DMA_HPXL(x) (x) 32 33 /* Video Size After zooming Register */ 34 #define LCD_SPU_DZM_HPXL_VLN 0x00F0 35 #define CFG_DZM_VLN(y) ((y) << 16) 36 #define CFG_DZM_HPXL(x) (x) 37 38 /* Graphic Frame 0&1 Starting Address Register */ 39 #define LCD_CFG_GRA_START_ADDR0 0x00F4 40 #define LCD_CFG_GRA_START_ADDR1 0x00F8 41 42 /* Graphic Frame Pitch */ 43 #define LCD_CFG_GRA_PITCH 0x00FC 44 45 /* Graphic Starting Point on Screen Register */ 46 #define LCD_SPU_GRA_OVSA_HPXL_VLN 0x0100 47 #define CFG_GRA_OVSA_VLN(y) ((y) << 16) 48 #define CFG_GRA_OVSA_HPXL(x) (x) 49 50 /* Graphic Size Register */ 51 #define LCD_SPU_GRA_HPXL_VLN 0x0104 52 #define CFG_GRA_VLN(y) ((y) << 16) 53 #define CFG_GRA_HPXL(x) (x) 54 55 /* Graphic Size after Zooming Register */ 56 #define LCD_SPU_GZM_HPXL_VLN 0x0108 57 #define CFG_GZM_VLN(y) ((y) << 16) 58 #define CFG_GZM_HPXL(x) (x) 59 60 /* HW Cursor Starting Point on Screen Register */ 61 #define LCD_SPU_HWC_OVSA_HPXL_VLN 0x010C 62 #define CFG_HWC_OVSA_VLN(y) ((y) << 16) 63 #define CFG_HWC_OVSA_HPXL(x) (x) 64 65 /* HW Cursor Size */ 66 #define LCD_SPU_HWC_HPXL_VLN 0x0110 67 #define CFG_HWC_VLN(y) ((y) << 16) 68 #define CFG_HWC_HPXL(x) (x) 69 70 /* Total Screen Size Register */ 71 #define LCD_SPUT_V_H_TOTAL 0x0114 72 #define CFG_V_TOTAL(y) ((y) << 16) 73 #define CFG_H_TOTAL(x) (x) 74 75 /* Total Screen Active Size Register */ 76 #define LCD_SPU_V_H_ACTIVE 0x0118 77 #define CFG_V_ACTIVE(y) ((y) << 16) 78 #define CFG_H_ACTIVE(x) (x) 79 80 /* Screen H&V Porch Register */ 81 #define LCD_SPU_H_PORCH 0x011C 82 #define CFG_H_BACK_PORCH(b) ((b) << 16) 83 #define CFG_H_FRONT_PORCH(f) (f) 84 #define LCD_SPU_V_PORCH 0x0120 85 #define CFG_V_BACK_PORCH(b) ((b) << 16) 86 #define CFG_V_FRONT_PORCH(f) (f) 87 88 /* Screen Blank Color Register */ 89 #define LCD_SPU_BLANKCOLOR 0x0124 90 #define CFG_BLANKCOLOR_MASK 0x00FFFFFF 91 #define CFG_BLANKCOLOR_R_MASK 0x000000FF 92 #define CFG_BLANKCOLOR_G_MASK 0x0000FF00 93 #define CFG_BLANKCOLOR_B_MASK 0x00FF0000 94 95 /* HW Cursor Color 1&2 Register */ 96 #define LCD_SPU_ALPHA_COLOR1 0x0128 97 #define CFG_HWC_COLOR1 0x00FFFFFF 98 #define CFG_HWC_COLOR1_R(red) ((red) << 16) 99 #define CFG_HWC_COLOR1_G(green) ((green) << 8) 100 #define CFG_HWC_COLOR1_B(blue) (blue) 101 #define CFG_HWC_COLOR1_R_MASK 0x000000FF 102 #define CFG_HWC_COLOR1_G_MASK 0x0000FF00 103 #define CFG_HWC_COLOR1_B_MASK 0x00FF0000 104 #define LCD_SPU_ALPHA_COLOR2 0x012C 105 #define CFG_HWC_COLOR2 0x00FFFFFF 106 #define CFG_HWC_COLOR2_R_MASK 0x000000FF 107 #define CFG_HWC_COLOR2_G_MASK 0x0000FF00 108 #define CFG_HWC_COLOR2_B_MASK 0x00FF0000 109 110 /* Video YUV Color Key Control */ 111 #define LCD_SPU_COLORKEY_Y 0x0130 112 #define CFG_CKEY_Y2(y2) ((y2) << 24) 113 #define CFG_CKEY_Y2_MASK 0xFF000000 114 #define CFG_CKEY_Y1(y1) ((y1) << 16) 115 #define CFG_CKEY_Y1_MASK 0x00FF0000 116 #define CFG_CKEY_Y(y) ((y) << 8) 117 #define CFG_CKEY_Y_MASK 0x0000FF00 118 #define CFG_ALPHA_Y(y) (y) 119 #define CFG_ALPHA_Y_MASK 0x000000FF 120 #define LCD_SPU_COLORKEY_U 0x0134 121 #define CFG_CKEY_U2(u2) ((u2) << 24) 122 #define CFG_CKEY_U2_MASK 0xFF000000 123 #define CFG_CKEY_U1(u1) ((u1) << 16) 124 #define CFG_CKEY_U1_MASK 0x00FF0000 125 #define CFG_CKEY_U(u) ((u) << 8) 126 #define CFG_CKEY_U_MASK 0x0000FF00 127 #define CFG_ALPHA_U(u) (u) 128 #define CFG_ALPHA_U_MASK 0x000000FF 129 #define LCD_SPU_COLORKEY_V 0x0138 130 #define CFG_CKEY_V2(v2) ((v2) << 24) 131 #define CFG_CKEY_V2_MASK 0xFF000000 132 #define CFG_CKEY_V1(v1) ((v1) << 16) 133 #define CFG_CKEY_V1_MASK 0x00FF0000 134 #define CFG_CKEY_V(v) ((v) << 8) 135 #define CFG_CKEY_V_MASK 0x0000FF00 136 #define CFG_ALPHA_V(v) (v) 137 #define CFG_ALPHA_V_MASK 0x000000FF 138 139 /* SPI Read Data Register */ 140 #define LCD_SPU_SPI_RXDATA 0x0140 141 142 /* Smart Panel Read Data Register */ 143 #define LCD_SPU_ISA_RSDATA 0x0144 144 #define ISA_RXDATA_16BIT_1_DATA_MASK 0x000000FF 145 #define ISA_RXDATA_16BIT_2_DATA_MASK 0x0000FF00 146 #define ISA_RXDATA_16BIT_3_DATA_MASK 0x00FF0000 147 #define ISA_RXDATA_16BIT_4_DATA_MASK 0xFF000000 148 #define ISA_RXDATA_32BIT_1_DATA_MASK 0x00FFFFFF 149 150 /* HWC SRAM Read Data Register */ 151 #define LCD_SPU_HWC_RDDAT 0x0158 152 153 /* Gamma Table SRAM Read Data Register */ 154 #define LCD_SPU_GAMMA_RDDAT 0x015c 155 #define CFG_GAMMA_RDDAT_MASK 0x000000FF 156 157 /* Palette Table SRAM Read Data Register */ 158 #define LCD_SPU_PALETTE_RDDAT 0x0160 159 #define CFG_PALETTE_RDDAT_MASK 0x00FFFFFF 160 161 /* I/O Pads Input Read Only Register */ 162 #define LCD_SPU_IOPAD_IN 0x0178 163 #define CFG_IOPAD_IN_MASK 0x0FFFFFFF 164 165 /* Reserved Read Only Registers */ 166 #define LCD_CFG_RDREG5F 0x017C 167 #define IRE_FRAME_CNT_MASK 0x000000C0 168 #define IPE_FRAME_CNT_MASK 0x00000030 169 #define GRA_FRAME_CNT_MASK 0x0000000C /* Graphic */ 170 #define DMA_FRAME_CNT_MASK 0x00000003 /* Video */ 171 172 /* SPI Control Register. */ 173 #define LCD_SPU_SPI_CTRL 0x0180 174 #define CFG_SCLKCNT(div) ((div) << 24) /* 0xFF~0x2 */ 175 #define CFG_SCLKCNT_MASK 0xFF000000 176 #define CFG_RXBITS(rx) ((rx) << 16) /* 0x1F~0x1 */ 177 #define CFG_RXBITS_MASK 0x00FF0000 178 #define CFG_TXBITS(tx) ((tx) << 8) /* 0x1F~0x1 */ 179 #define CFG_TXBITS_MASK 0x0000FF00 180 #define CFG_CLKINV(clk) ((clk) << 7) 181 #define CFG_CLKINV_MASK 0x00000080 182 #define CFG_KEEPXFER(transfer) ((transfer) << 6) 183 #define CFG_KEEPXFER_MASK 0x00000040 184 #define CFG_RXBITSTO0(rx) ((rx) << 5) 185 #define CFG_RXBITSTO0_MASK 0x00000020 186 #define CFG_TXBITSTO0(tx) ((tx) << 4) 187 #define CFG_TXBITSTO0_MASK 0x00000010 188 #define CFG_SPI_ENA(spi) ((spi) << 3) 189 #define CFG_SPI_ENA_MASK 0x00000008 190 #define CFG_SPI_SEL(spi) ((spi) << 2) 191 #define CFG_SPI_SEL_MASK 0x00000004 192 #define CFG_SPI_3W4WB(wire) ((wire) << 1) 193 #define CFG_SPI_3W4WB_MASK 0x00000002 194 #define CFG_SPI_START(start) (start) 195 #define CFG_SPI_START_MASK 0x00000001 196 197 /* SPI Tx Data Register */ 198 #define LCD_SPU_SPI_TXDATA 0x0184 199 200 /* 201 1. Smart Pannel 8-bit Bus Control Register. 202 2. AHB Slave Path Data Port Register 203 */ 204 #define LCD_SPU_SMPN_CTRL 0x0188 205 206 /* DMA Control 0 Register */ 207 #define LCD_SPU_DMA_CTRL0 0x0190 208 #define CFG_NOBLENDING(nb) ((nb) << 31) 209 #define CFG_NOBLENDING_MASK 0x80000000 210 #define CFG_GAMMA_ENA(gn) ((gn) << 30) 211 #define CFG_GAMMA_ENA_MASK 0x40000000 212 #define CFG_CBSH_ENA(cn) ((cn) << 29) 213 #define CFG_CBSH_ENA_MASK 0x20000000 214 #define CFG_PALETTE_ENA(pn) ((pn) << 28) 215 #define CFG_PALETTE_ENA_MASK 0x10000000 216 #define CFG_ARBFAST_ENA(an) ((an) << 27) 217 #define CFG_ARBFAST_ENA_MASK 0x08000000 218 #define CFG_HWC_1BITMOD(mode) ((mode) << 26) 219 #define CFG_HWC_1BITMOD_MASK 0x04000000 220 #define CFG_HWC_1BITENA(mn) ((mn) << 25) 221 #define CFG_HWC_1BITENA_MASK 0x02000000 222 #define CFG_HWC_ENA(cn) ((cn) << 24) 223 #define CFG_HWC_ENA_MASK 0x01000000 224 #define CFG_DMAFORMAT(dmaformat) ((dmaformat) << 20) 225 #define CFG_DMAFORMAT_MASK 0x00F00000 226 #define CFG_GRAFORMAT(graformat) ((graformat) << 16) 227 #define CFG_GRAFORMAT_MASK 0x000F0000 228 /* for graphic part */ 229 #define CFG_GRA_FTOGGLE(toggle) ((toggle) << 15) 230 #define CFG_GRA_FTOGGLE_MASK 0x00008000 231 #define CFG_GRA_HSMOOTH(smooth) ((smooth) << 14) 232 #define CFG_GRA_HSMOOTH_MASK 0x00004000 233 #define CFG_GRA_TSTMODE(test) ((test) << 13) 234 #define CFG_GRA_TSTMODE_MASK 0x00002000 235 #define CFG_GRA_SWAPRB(swap) ((swap) << 12) 236 #define CFG_GRA_SWAPRB_MASK 0x00001000 237 #define CFG_GRA_SWAPUV(swap) ((swap) << 11) 238 #define CFG_GRA_SWAPUV_MASK 0x00000800 239 #define CFG_GRA_SWAPYU(swap) ((swap) << 10) 240 #define CFG_GRA_SWAPYU_MASK 0x00000400 241 #define CFG_YUV2RGB_GRA(cvrt) ((cvrt) << 9) 242 #define CFG_YUV2RGB_GRA_MASK 0x00000200 243 #define CFG_GRA_ENA(gra) ((gra) << 8) 244 #define CFG_GRA_ENA_MASK 0x00000100 245 /* for video part */ 246 #define CFG_DMA_FTOGGLE(toggle) ((toggle) << 7) 247 #define CFG_DMA_FTOGGLE_MASK 0x00000080 248 #define CFG_DMA_HSMOOTH(smooth) ((smooth) << 6) 249 #define CFG_DMA_HSMOOTH_MASK 0x00000040 250 #define CFG_DMA_TSTMODE(test) ((test) << 5) 251 #define CFG_DMA_TSTMODE_MASK 0x00000020 252 #define CFG_DMA_SWAPRB(swap) ((swap) << 4) 253 #define CFG_DMA_SWAPRB_MASK 0x00000010 254 #define CFG_DMA_SWAPUV(swap) ((swap) << 3) 255 #define CFG_DMA_SWAPUV_MASK 0x00000008 256 #define CFG_DMA_SWAPYU(swap) ((swap) << 2) 257 #define CFG_DMA_SWAPYU_MASK 0x00000004 258 #define CFG_DMA_SWAP_MASK 0x0000001C 259 #define CFG_YUV2RGB_DMA(cvrt) ((cvrt) << 1) 260 #define CFG_YUV2RGB_DMA_MASK 0x00000002 261 #define CFG_DMA_ENA(video) (video) 262 #define CFG_DMA_ENA_MASK 0x00000001 263 264 /* DMA Control 1 Register */ 265 #define LCD_SPU_DMA_CTRL1 0x0194 266 #define CFG_FRAME_TRIG(trig) ((trig) << 31) 267 #define CFG_FRAME_TRIG_MASK 0x80000000 268 #define CFG_VSYNC_TRIG(trig) ((trig) << 28) 269 #define CFG_VSYNC_TRIG_MASK 0x70000000 270 #define CFG_VSYNC_INV(inv) ((inv) << 27) 271 #define CFG_VSYNC_INV_MASK 0x08000000 272 #define CFG_COLOR_KEY_MODE(cmode) ((cmode) << 24) 273 #define CFG_COLOR_KEY_MASK 0x07000000 274 #define CFG_CARRY(carry) ((carry) << 23) 275 #define CFG_CARRY_MASK 0x00800000 276 #define CFG_LNBUF_ENA(lnbuf) ((lnbuf) << 22) 277 #define CFG_LNBUF_ENA_MASK 0x00400000 278 #define CFG_GATED_ENA(gated) ((gated) << 21) 279 #define CFG_GATED_ENA_MASK 0x00200000 280 #define CFG_PWRDN_ENA(power) ((power) << 20) 281 #define CFG_PWRDN_ENA_MASK 0x00100000 282 #define CFG_DSCALE(dscale) ((dscale) << 18) 283 #define CFG_DSCALE_MASK 0x000C0000 284 #define CFG_ALPHA_MODE(amode) ((amode) << 16) 285 #define CFG_ALPHA_MODE_MASK 0x00030000 286 #define CFG_ALPHA(alpha) ((alpha) << 8) 287 #define CFG_ALPHA_MASK 0x0000FF00 288 #define CFG_PXLCMD(pxlcmd) (pxlcmd) 289 #define CFG_PXLCMD_MASK 0x000000FF 290 291 /* SRAM Control Register */ 292 #define LCD_SPU_SRAM_CTRL 0x0198 293 #define CFG_SRAM_INIT_WR_RD(mode) ((mode) << 14) 294 #define CFG_SRAM_INIT_WR_RD_MASK 0x0000C000 295 #define CFG_SRAM_ADDR_LCDID(id) ((id) << 8) 296 #define CFG_SRAM_ADDR_LCDID_MASK 0x00000F00 297 #define CFG_SRAM_ADDR(addr) (addr) 298 #define CFG_SRAM_ADDR_MASK 0x000000FF 299 300 /* SRAM Write Data Register */ 301 #define LCD_SPU_SRAM_WRDAT 0x019C 302 303 /* SRAM RTC/WTC Control Register */ 304 #define LCD_SPU_SRAM_PARA0 0x01A0 305 306 /* SRAM Power Down Control Register */ 307 #define LCD_SPU_SRAM_PARA1 0x01A4 308 #define CFG_CSB_256x32(hwc) ((hwc) << 15) /* HWC */ 309 #define CFG_CSB_256x32_MASK 0x00008000 310 #define CFG_CSB_256x24(palette) ((palette) << 14) /* Palette */ 311 #define CFG_CSB_256x24_MASK 0x00004000 312 #define CFG_CSB_256x8(gamma) ((gamma) << 13) /* Gamma */ 313 #define CFG_CSB_256x8_MASK 0x00002000 314 #define CFG_PDWN256x32(pdwn) ((pdwn) << 7) /* HWC */ 315 #define CFG_PDWN256x32_MASK 0x00000080 316 #define CFG_PDWN256x24(pdwn) ((pdwn) << 6) /* Palette */ 317 #define CFG_PDWN256x24_MASK 0x00000040 318 #define CFG_PDWN256x8(pdwn) ((pdwn) << 5) /* Gamma */ 319 #define CFG_PDWN256x8_MASK 0x00000020 320 #define CFG_PDWN32x32(pdwn) ((pdwn) << 3) 321 #define CFG_PDWN32x32_MASK 0x00000008 322 #define CFG_PDWN16x66(pdwn) ((pdwn) << 2) 323 #define CFG_PDWN16x66_MASK 0x00000004 324 #define CFG_PDWN32x66(pdwn) ((pdwn) << 1) 325 #define CFG_PDWN32x66_MASK 0x00000002 326 #define CFG_PDWN64x66(pdwn) (pdwn) 327 #define CFG_PDWN64x66_MASK 0x00000001 328 329 /* Smart or Dumb Panel Clock Divider */ 330 #define LCD_CFG_SCLK_DIV 0x01A8 331 #define SCLK_SOURCE_SELECT(src) ((src) << 31) 332 #define SCLK_SOURCE_SELECT_MASK 0x80000000 333 #define CLK_FRACDIV(frac) ((frac) << 16) 334 #define CLK_FRACDIV_MASK 0x0FFF0000 335 #define CLK_INT_DIV(div) (div) 336 #define CLK_INT_DIV_MASK 0x0000FFFF 337 338 /* Video Contrast Register */ 339 #define LCD_SPU_CONTRAST 0x01AC 340 #define CFG_BRIGHTNESS(bright) ((bright) << 16) 341 #define CFG_BRIGHTNESS_MASK 0xFFFF0000 342 #define CFG_CONTRAST(contrast) (contrast) 343 #define CFG_CONTRAST_MASK 0x0000FFFF 344 345 /* Video Saturation Register */ 346 #define LCD_SPU_SATURATION 0x01B0 347 #define CFG_C_MULTS(mult) ((mult) << 16) 348 #define CFG_C_MULTS_MASK 0xFFFF0000 349 #define CFG_SATURATION(sat) (sat) 350 #define CFG_SATURATION_MASK 0x0000FFFF 351 352 /* Video Hue Adjust Register */ 353 #define LCD_SPU_CBSH_HUE 0x01B4 354 #define CFG_SIN0(sin0) ((sin0) << 16) 355 #define CFG_SIN0_MASK 0xFFFF0000 356 #define CFG_COS0(con0) (con0) 357 #define CFG_COS0_MASK 0x0000FFFF 358 359 /* Dump LCD Panel Control Register */ 360 #define LCD_SPU_DUMB_CTRL 0x01B8 361 #define CFG_DUMBMODE(mode) ((mode) << 28) 362 #define CFG_DUMBMODE_MASK 0xF0000000 363 #define CFG_LCDGPIO_O(data) ((data) << 20) 364 #define CFG_LCDGPIO_O_MASK 0x0FF00000 365 #define CFG_LCDGPIO_ENA(gpio) ((gpio) << 12) 366 #define CFG_LCDGPIO_ENA_MASK 0x000FF000 367 #define CFG_BIAS_OUT(bias) ((bias) << 8) 368 #define CFG_BIAS_OUT_MASK 0x00000100 369 #define CFG_REVERSE_RGB(rRGB) ((rRGB) << 7) 370 #define CFG_REVERSE_RGB_MASK 0x00000080 371 #define CFG_INV_COMPBLANK(blank) ((blank) << 6) 372 #define CFG_INV_COMPBLANK_MASK 0x00000040 373 #define CFG_INV_COMPSYNC(sync) ((sync) << 5) 374 #define CFG_INV_COMPSYNC_MASK 0x00000020 375 #define CFG_INV_HENA(hena) ((hena) << 4) 376 #define CFG_INV_HENA_MASK 0x00000010 377 #define CFG_INV_VSYNC(vsync) ((vsync) << 3) 378 #define CFG_INV_VSYNC_MASK 0x00000008 379 #define CFG_INV_HSYNC(hsync) ((hsync) << 2) 380 #define CFG_INV_HSYNC_MASK 0x00000004 381 #define CFG_INV_PCLK(pclk) ((pclk) << 1) 382 #define CFG_INV_PCLK_MASK 0x00000002 383 #define CFG_DUMB_ENA(dumb) (dumb) 384 #define CFG_DUMB_ENA_MASK 0x00000001 385 386 /* LCD I/O Pads Control Register */ 387 #define SPU_IOPAD_CONTROL 0x01BC 388 #define CFG_GRA_VM_ENA(vm) ((vm) << 15) /* gfx */ 389 #define CFG_GRA_VM_ENA_MASK 0x00008000 390 #define CFG_DMA_VM_ENA(vm) ((vm) << 13) /* video */ 391 #define CFG_DMA_VM_ENA_MASK 0x00002000 392 #define CFG_CMD_VM_ENA(vm) ((vm) << 13) 393 #define CFG_CMD_VM_ENA_MASK 0x00000800 394 #define CFG_CSC(csc) ((csc) << 8) /* csc */ 395 #define CFG_CSC_MASK 0x00000300 396 #define CFG_AXICTRL(axi) ((axi) << 4) 397 #define CFG_AXICTRL_MASK 0x000000F0 398 #define CFG_IOPADMODE(iopad) (iopad) 399 #define CFG_IOPADMODE_MASK 0x0000000F 400 401 /* LCD Interrupt Control Register */ 402 #define SPU_IRQ_ENA 0x01C0 403 #define DMA_FRAME_IRQ0_ENA(irq) ((irq) << 31) 404 #define DMA_FRAME_IRQ0_ENA_MASK 0x80000000 405 #define DMA_FRAME_IRQ1_ENA(irq) ((irq) << 30) 406 #define DMA_FRAME_IRQ1_ENA_MASK 0x40000000 407 #define DMA_FF_UNDERFLOW_ENA(ff) ((ff) << 29) 408 #define DMA_FF_UNDERFLOW_ENA_MASK 0x20000000 409 #define GRA_FRAME_IRQ0_ENA(irq) ((irq) << 27) 410 #define GRA_FRAME_IRQ0_ENA_MASK 0x08000000 411 #define GRA_FRAME_IRQ1_ENA(irq) ((irq) << 26) 412 #define GRA_FRAME_IRQ1_ENA_MASK 0x04000000 413 #define GRA_FF_UNDERFLOW_ENA(ff) ((ff) << 25) 414 #define GRA_FF_UNDERFLOW_ENA_MASK 0x02000000 415 #define VSYNC_IRQ_ENA(vsync_irq) ((vsync_irq) << 23) 416 #define VSYNC_IRQ_ENA_MASK 0x00800000 417 #define DUMB_FRAMEDONE_ENA(fdone) ((fdone) << 22) 418 #define DUMB_FRAMEDONE_ENA_MASK 0x00400000 419 #define TWC_FRAMEDONE_ENA(fdone) ((fdone) << 21) 420 #define TWC_FRAMEDONE_ENA_MASK 0x00200000 421 #define HWC_FRAMEDONE_ENA(fdone) ((fdone) << 20) 422 #define HWC_FRAMEDONE_ENA_MASK 0x00100000 423 #define SLV_IRQ_ENA(irq) ((irq) << 19) 424 #define SLV_IRQ_ENA_MASK 0x00080000 425 #define SPI_IRQ_ENA(irq) ((irq) << 18) 426 #define SPI_IRQ_ENA_MASK 0x00040000 427 #define PWRDN_IRQ_ENA(irq) ((irq) << 17) 428 #define PWRDN_IRQ_ENA_MASK 0x00020000 429 #define ERR_IRQ_ENA(irq) ((irq) << 16) 430 #define ERR_IRQ_ENA_MASK 0x00010000 431 #define CLEAN_SPU_IRQ_ISR(irq) (irq) 432 #define CLEAN_SPU_IRQ_ISR_MASK 0x0000FFFF 433 434 /* LCD Interrupt Status Register */ 435 #define SPU_IRQ_ISR 0x01C4 436 #define DMA_FRAME_IRQ0(irq) ((irq) << 31) 437 #define DMA_FRAME_IRQ0_MASK 0x80000000 438 #define DMA_FRAME_IRQ1(irq) ((irq) << 30) 439 #define DMA_FRAME_IRQ1_MASK 0x40000000 440 #define DMA_FF_UNDERFLOW(ff) ((ff) << 29) 441 #define DMA_FF_UNDERFLOW_MASK 0x20000000 442 #define GRA_FRAME_IRQ0(irq) ((irq) << 27) 443 #define GRA_FRAME_IRQ0_MASK 0x08000000 444 #define GRA_FRAME_IRQ1(irq) ((irq) << 26) 445 #define GRA_FRAME_IRQ1_MASK 0x04000000 446 #define GRA_FF_UNDERFLOW(ff) ((ff) << 25) 447 #define GRA_FF_UNDERFLOW_MASK 0x02000000 448 #define VSYNC_IRQ(vsync_irq) ((vsync_irq) << 23) 449 #define VSYNC_IRQ_MASK 0x00800000 450 #define DUMB_FRAMEDONE(fdone) ((fdone) << 22) 451 #define DUMB_FRAMEDONE_MASK 0x00400000 452 #define TWC_FRAMEDONE(fdone) ((fdone) << 21) 453 #define TWC_FRAMEDONE_MASK 0x00200000 454 #define HWC_FRAMEDONE(fdone) ((fdone) << 20) 455 #define HWC_FRAMEDONE_MASK 0x00100000 456 #define SLV_IRQ(irq) ((irq) << 19) 457 #define SLV_IRQ_MASK 0x00080000 458 #define SPI_IRQ(irq) ((irq) << 18) 459 #define SPI_IRQ_MASK 0x00040000 460 #define PWRDN_IRQ(irq) ((irq) << 17) 461 #define PWRDN_IRQ_MASK 0x00020000 462 #define ERR_IRQ(irq) ((irq) << 16) 463 #define ERR_IRQ_MASK 0x00010000 464 /* read-only */ 465 #define DMA_FRAME_IRQ0_LEVEL_MASK 0x00008000 466 #define DMA_FRAME_IRQ1_LEVEL_MASK 0x00004000 467 #define DMA_FRAME_CNT_ISR_MASK 0x00003000 468 #define GRA_FRAME_IRQ0_LEVEL_MASK 0x00000800 469 #define GRA_FRAME_IRQ1_LEVEL_MASK 0x00000400 470 #define GRA_FRAME_CNT_ISR_MASK 0x00000300 471 #define VSYNC_IRQ_LEVEL_MASK 0x00000080 472 #define DUMB_FRAMEDONE_LEVEL_MASK 0x00000040 473 #define TWC_FRAMEDONE_LEVEL_MASK 0x00000020 474 #define HWC_FRAMEDONE_LEVEL_MASK 0x00000010 475 #define SLV_FF_EMPTY_MASK 0x00000008 476 #define DMA_FF_ALLEMPTY_MASK 0x00000004 477 #define GRA_FF_ALLEMPTY_MASK 0x00000002 478 #define PWRDN_IRQ_LEVEL_MASK 0x00000001 479 480 481 /* 482 * defined Video Memory Color format for DMA control 0 register 483 * DMA0 bit[23:20] 484 */ 485 #define VMODE_RGB565 0x0 486 #define VMODE_RGB1555 0x1 487 #define VMODE_RGB888PACKED 0x2 488 #define VMODE_RGB888UNPACKED 0x3 489 #define VMODE_RGBA888 0x4 490 #define VMODE_YUV422PACKED 0x5 491 #define VMODE_YUV422PLANAR 0x6 492 #define VMODE_YUV420PLANAR 0x7 493 #define VMODE_SMPNCMD 0x8 494 #define VMODE_PALETTE4BIT 0x9 495 #define VMODE_PALETTE8BIT 0xa 496 #define VMODE_RESERVED 0xb 497 498 /* 499 * defined Graphic Memory Color format for DMA control 0 register 500 * DMA0 bit[19:16] 501 */ 502 #define GMODE_RGB565 0x0 503 #define GMODE_RGB1555 0x1 504 #define GMODE_RGB888PACKED 0x2 505 #define GMODE_RGB888UNPACKED 0x3 506 #define GMODE_RGBA888 0x4 507 #define GMODE_YUV422PACKED 0x5 508 #define GMODE_YUV422PLANAR 0x6 509 #define GMODE_YUV420PLANAR 0x7 510 #define GMODE_SMPNCMD 0x8 511 #define GMODE_PALETTE4BIT 0x9 512 #define GMODE_PALETTE8BIT 0xa 513 #define GMODE_RESERVED 0xb 514 515 /* 516 * define for DMA control 1 register 517 */ 518 #define DMA1_FRAME_TRIG 31 /* bit location */ 519 #define DMA1_VSYNC_MODE 28 520 #define DMA1_VSYNC_INV 27 521 #define DMA1_CKEY 24 522 #define DMA1_CARRY 23 523 #define DMA1_LNBUF_ENA 22 524 #define DMA1_GATED_ENA 21 525 #define DMA1_PWRDN_ENA 20 526 #define DMA1_DSCALE 18 527 #define DMA1_ALPHA_MODE 16 528 #define DMA1_ALPHA 08 529 #define DMA1_PXLCMD 00 530 531 /* 532 * defined for Configure Dumb Mode 533 * DUMB LCD Panel bit[31:28] 534 */ 535 #define DUMB16_RGB565_0 0x0 536 #define DUMB16_RGB565_1 0x1 537 #define DUMB18_RGB666_0 0x2 538 #define DUMB18_RGB666_1 0x3 539 #define DUMB12_RGB444_0 0x4 540 #define DUMB12_RGB444_1 0x5 541 #define DUMB24_RGB888_0 0x6 542 #define DUMB_BLANK 0x7 543 544 /* 545 * defined for Configure I/O Pin Allocation Mode 546 * LCD LCD I/O Pads control register bit[3:0] 547 */ 548 #define IOPAD_DUMB24 0x0 549 #define IOPAD_DUMB18SPI 0x1 550 #define IOPAD_DUMB18GPIO 0x2 551 #define IOPAD_DUMB16SPI 0x3 552 #define IOPAD_DUMB16GPIO 0x4 553 #define IOPAD_DUMB12 0x5 554 #define IOPAD_SMART18SPI 0x6 555 #define IOPAD_SMART16SPI 0x7 556 #define IOPAD_SMART8BOTH 0x8 557 558 #endif /* __PXA168FB_H__ */ 559