1 /*
2 * linux/drivers/video/pm3fb.c -- 3DLabs Permedia3 frame buffer device
3 *
4 * Copyright (C) 2001 Romain Dolbeau <romain@dolbeau.org>.
5 *
6 * Ported to 2.6 kernel on 1 May 2007 by Krzysztof Helt <krzysztof.h1@wp.pl>
7 * based on pm2fb.c
8 *
9 * Based on code written by:
10 * Sven Luther, <luther@dpt-info.u-strasbg.fr>
11 * Alan Hourihane, <alanh@fairlite.demon.co.uk>
12 * Russell King, <rmk@arm.linux.org.uk>
13 * Based on linux/drivers/video/skeletonfb.c:
14 * Copyright (C) 1997 Geert Uytterhoeven
15 * Based on linux/driver/video/pm2fb.c:
16 * Copyright (C) 1998-1999 Ilario Nardinocchi (nardinoc@CS.UniBO.IT)
17 * Copyright (C) 1999 Jakub Jelinek (jakub@redhat.com)
18 *
19 * This file is subject to the terms and conditions of the GNU General Public
20 * License. See the file COPYING in the main directory of this archive for
21 * more details.
22 *
23 */
24
25 #include <linux/aperture.h>
26 #include <linux/module.h>
27 #include <linux/kernel.h>
28 #include <linux/errno.h>
29 #include <linux/string.h>
30 #include <linux/mm.h>
31 #include <linux/slab.h>
32 #include <linux/delay.h>
33 #include <linux/fb.h>
34 #include <linux/init.h>
35 #include <linux/pci.h>
36
37 #include <video/pm3fb.h>
38
39 #if !defined(CONFIG_PCI)
40 #error "Only generic PCI cards supported."
41 #endif
42
43 #undef PM3FB_MASTER_DEBUG
44 #ifdef PM3FB_MASTER_DEBUG
45 #define DPRINTK(a, b...) \
46 printk(KERN_DEBUG "pm3fb: %s: " a, __func__ , ## b)
47 #else
48 #define DPRINTK(a, b...) no_printk(a, ##b)
49 #endif
50
51 #define PM3_PIXMAP_SIZE (2048 * 4)
52
53 /*
54 * Driver data
55 */
56 static int hwcursor = 1;
57 static char *mode_option;
58 static bool noaccel;
59 static bool nomtrr;
60
61 /*
62 * This structure defines the hardware state of the graphics card. Normally
63 * you place this in a header file in linux/include/video. This file usually
64 * also includes register information. That allows other driver subsystems
65 * and userland applications the ability to use the same header file to
66 * avoid duplicate work and easy porting of software.
67 */
68 struct pm3_par {
69 unsigned char __iomem *v_regs;/* virtual address of p_regs */
70 u32 video; /* video flags before blanking */
71 u32 base; /* screen base in 128 bits unit */
72 u32 palette[16];
73 int wc_cookie;
74 };
75
76 /*
77 * Here we define the default structs fb_fix_screeninfo and fb_var_screeninfo
78 * if we don't use modedb. If we do use modedb see pm3fb_init how to use it
79 * to get a fb_var_screeninfo. Otherwise define a default var as well.
80 */
81 static struct fb_fix_screeninfo pm3fb_fix = {
82 .id = "Permedia3",
83 .type = FB_TYPE_PACKED_PIXELS,
84 .visual = FB_VISUAL_PSEUDOCOLOR,
85 .xpanstep = 1,
86 .ypanstep = 1,
87 .ywrapstep = 0,
88 .accel = FB_ACCEL_3DLABS_PERMEDIA3,
89 };
90
91 /*
92 * Utility functions
93 */
94
PM3_READ_REG(struct pm3_par * par,s32 off)95 static inline u32 PM3_READ_REG(struct pm3_par *par, s32 off)
96 {
97 return fb_readl(par->v_regs + off);
98 }
99
PM3_WRITE_REG(struct pm3_par * par,s32 off,u32 v)100 static inline void PM3_WRITE_REG(struct pm3_par *par, s32 off, u32 v)
101 {
102 fb_writel(v, par->v_regs + off);
103 }
104
PM3_WAIT(struct pm3_par * par,u32 n)105 static inline void PM3_WAIT(struct pm3_par *par, u32 n)
106 {
107 while (PM3_READ_REG(par, PM3InFIFOSpace) < n)
108 cpu_relax();
109 }
110
PM3_WRITE_DAC_REG(struct pm3_par * par,unsigned r,u8 v)111 static inline void PM3_WRITE_DAC_REG(struct pm3_par *par, unsigned r, u8 v)
112 {
113 PM3_WAIT(par, 3);
114 PM3_WRITE_REG(par, PM3RD_IndexHigh, (r >> 8) & 0xff);
115 PM3_WRITE_REG(par, PM3RD_IndexLow, r & 0xff);
116 wmb();
117 PM3_WRITE_REG(par, PM3RD_IndexedData, v);
118 wmb();
119 }
120
pm3fb_set_color(struct pm3_par * par,unsigned char regno,unsigned char r,unsigned char g,unsigned char b)121 static inline void pm3fb_set_color(struct pm3_par *par, unsigned char regno,
122 unsigned char r, unsigned char g, unsigned char b)
123 {
124 PM3_WAIT(par, 4);
125 PM3_WRITE_REG(par, PM3RD_PaletteWriteAddress, regno);
126 wmb();
127 PM3_WRITE_REG(par, PM3RD_PaletteData, r);
128 wmb();
129 PM3_WRITE_REG(par, PM3RD_PaletteData, g);
130 wmb();
131 PM3_WRITE_REG(par, PM3RD_PaletteData, b);
132 wmb();
133 }
134
pm3fb_clear_colormap(struct pm3_par * par,unsigned char r,unsigned char g,unsigned char b)135 static void pm3fb_clear_colormap(struct pm3_par *par,
136 unsigned char r, unsigned char g, unsigned char b)
137 {
138 int i;
139
140 for (i = 0; i < 256 ; i++)
141 pm3fb_set_color(par, i, r, g, b);
142
143 }
144
145 /* Calculating various clock parameters */
pm3fb_calculate_clock(unsigned long reqclock,unsigned char * prescale,unsigned char * feedback,unsigned char * postscale)146 static void pm3fb_calculate_clock(unsigned long reqclock,
147 unsigned char *prescale,
148 unsigned char *feedback,
149 unsigned char *postscale)
150 {
151 int f, pre, post;
152 unsigned long freq;
153 long freqerr = 1000;
154 long currerr;
155
156 for (f = 1; f < 256; f++) {
157 for (pre = 1; pre < 256; pre++) {
158 for (post = 0; post < 5; post++) {
159 freq = ((2*PM3_REF_CLOCK * f) >> post) / pre;
160 currerr = (reqclock > freq)
161 ? reqclock - freq
162 : freq - reqclock;
163 if (currerr < freqerr) {
164 freqerr = currerr;
165 *feedback = f;
166 *prescale = pre;
167 *postscale = post;
168 }
169 }
170 }
171 }
172 }
173
pm3fb_depth(const struct fb_var_screeninfo * var)174 static inline int pm3fb_depth(const struct fb_var_screeninfo *var)
175 {
176 if (var->bits_per_pixel == 16)
177 return var->red.length + var->green.length
178 + var->blue.length;
179
180 return var->bits_per_pixel;
181 }
182
pm3fb_shift_bpp(unsigned bpp,int v)183 static inline int pm3fb_shift_bpp(unsigned bpp, int v)
184 {
185 switch (bpp) {
186 case 8:
187 return (v >> 4);
188 case 16:
189 return (v >> 3);
190 case 32:
191 return (v >> 2);
192 }
193 DPRINTK("Unsupported depth %u\n", bpp);
194 return 0;
195 }
196
197 /* acceleration */
pm3fb_sync(struct fb_info * info)198 static int pm3fb_sync(struct fb_info *info)
199 {
200 struct pm3_par *par = info->par;
201
202 PM3_WAIT(par, 2);
203 PM3_WRITE_REG(par, PM3FilterMode, PM3FilterModeSync);
204 PM3_WRITE_REG(par, PM3Sync, 0);
205 mb();
206 do {
207 while ((PM3_READ_REG(par, PM3OutFIFOWords)) == 0)
208 cpu_relax();
209 } while ((PM3_READ_REG(par, PM3OutputFifo)) != PM3Sync_Tag);
210
211 return 0;
212 }
213
pm3fb_init_engine(struct fb_info * info)214 static void pm3fb_init_engine(struct fb_info *info)
215 {
216 struct pm3_par *par = info->par;
217 const u32 width = (info->var.xres_virtual + 7) & ~7;
218
219 PM3_WAIT(par, 50);
220 PM3_WRITE_REG(par, PM3FilterMode, PM3FilterModeSync);
221 PM3_WRITE_REG(par, PM3StatisticMode, 0x0);
222 PM3_WRITE_REG(par, PM3DeltaMode, 0x0);
223 PM3_WRITE_REG(par, PM3RasterizerMode, 0x0);
224 PM3_WRITE_REG(par, PM3ScissorMode, 0x0);
225 PM3_WRITE_REG(par, PM3LineStippleMode, 0x0);
226 PM3_WRITE_REG(par, PM3AreaStippleMode, 0x0);
227 PM3_WRITE_REG(par, PM3GIDMode, 0x0);
228 PM3_WRITE_REG(par, PM3DepthMode, 0x0);
229 PM3_WRITE_REG(par, PM3StencilMode, 0x0);
230 PM3_WRITE_REG(par, PM3StencilData, 0x0);
231 PM3_WRITE_REG(par, PM3ColorDDAMode, 0x0);
232 PM3_WRITE_REG(par, PM3TextureCoordMode, 0x0);
233 PM3_WRITE_REG(par, PM3TextureIndexMode0, 0x0);
234 PM3_WRITE_REG(par, PM3TextureIndexMode1, 0x0);
235 PM3_WRITE_REG(par, PM3TextureReadMode, 0x0);
236 PM3_WRITE_REG(par, PM3LUTMode, 0x0);
237 PM3_WRITE_REG(par, PM3TextureFilterMode, 0x0);
238 PM3_WRITE_REG(par, PM3TextureCompositeMode, 0x0);
239 PM3_WRITE_REG(par, PM3TextureApplicationMode, 0x0);
240 PM3_WRITE_REG(par, PM3TextureCompositeColorMode1, 0x0);
241 PM3_WRITE_REG(par, PM3TextureCompositeAlphaMode1, 0x0);
242 PM3_WRITE_REG(par, PM3TextureCompositeColorMode0, 0x0);
243 PM3_WRITE_REG(par, PM3TextureCompositeAlphaMode0, 0x0);
244 PM3_WRITE_REG(par, PM3FogMode, 0x0);
245 PM3_WRITE_REG(par, PM3ChromaTestMode, 0x0);
246 PM3_WRITE_REG(par, PM3AlphaTestMode, 0x0);
247 PM3_WRITE_REG(par, PM3AntialiasMode, 0x0);
248 PM3_WRITE_REG(par, PM3YUVMode, 0x0);
249 PM3_WRITE_REG(par, PM3AlphaBlendColorMode, 0x0);
250 PM3_WRITE_REG(par, PM3AlphaBlendAlphaMode, 0x0);
251 PM3_WRITE_REG(par, PM3DitherMode, 0x0);
252 PM3_WRITE_REG(par, PM3LogicalOpMode, 0x0);
253 PM3_WRITE_REG(par, PM3RouterMode, 0x0);
254 PM3_WRITE_REG(par, PM3Window, 0x0);
255
256 PM3_WRITE_REG(par, PM3Config2D, 0x0);
257
258 PM3_WRITE_REG(par, PM3SpanColorMask, 0xffffffff);
259
260 PM3_WRITE_REG(par, PM3XBias, 0x0);
261 PM3_WRITE_REG(par, PM3YBias, 0x0);
262 PM3_WRITE_REG(par, PM3DeltaControl, 0x0);
263
264 PM3_WRITE_REG(par, PM3BitMaskPattern, 0xffffffff);
265
266 PM3_WRITE_REG(par, PM3FBDestReadEnables,
267 PM3FBDestReadEnables_E(0xff) |
268 PM3FBDestReadEnables_R(0xff) |
269 PM3FBDestReadEnables_ReferenceAlpha(0xff));
270 PM3_WRITE_REG(par, PM3FBDestReadBufferAddr0, 0x0);
271 PM3_WRITE_REG(par, PM3FBDestReadBufferOffset0, 0x0);
272 PM3_WRITE_REG(par, PM3FBDestReadBufferWidth0,
273 PM3FBDestReadBufferWidth_Width(width));
274
275 PM3_WRITE_REG(par, PM3FBDestReadMode,
276 PM3FBDestReadMode_ReadEnable |
277 PM3FBDestReadMode_Enable0);
278 PM3_WRITE_REG(par, PM3FBSourceReadBufferAddr, 0x0);
279 PM3_WRITE_REG(par, PM3FBSourceReadBufferOffset, 0x0);
280 PM3_WRITE_REG(par, PM3FBSourceReadBufferWidth,
281 PM3FBSourceReadBufferWidth_Width(width));
282 PM3_WRITE_REG(par, PM3FBSourceReadMode,
283 PM3FBSourceReadMode_Blocking |
284 PM3FBSourceReadMode_ReadEnable);
285
286 PM3_WAIT(par, 2);
287 {
288 /* invert bits in bitmask */
289 unsigned long rm = 1 | (3 << 7);
290 switch (info->var.bits_per_pixel) {
291 case 8:
292 PM3_WRITE_REG(par, PM3PixelSize,
293 PM3PixelSize_GLOBAL_8BIT);
294 #ifdef __BIG_ENDIAN
295 rm |= 3 << 15;
296 #endif
297 break;
298 case 16:
299 PM3_WRITE_REG(par, PM3PixelSize,
300 PM3PixelSize_GLOBAL_16BIT);
301 #ifdef __BIG_ENDIAN
302 rm |= 2 << 15;
303 #endif
304 break;
305 case 32:
306 PM3_WRITE_REG(par, PM3PixelSize,
307 PM3PixelSize_GLOBAL_32BIT);
308 break;
309 default:
310 DPRINTK("Unsupported depth %d\n",
311 info->var.bits_per_pixel);
312 break;
313 }
314 PM3_WRITE_REG(par, PM3RasterizerMode, rm);
315 }
316
317 PM3_WAIT(par, 20);
318 PM3_WRITE_REG(par, PM3FBSoftwareWriteMask, 0xffffffff);
319 PM3_WRITE_REG(par, PM3FBHardwareWriteMask, 0xffffffff);
320 PM3_WRITE_REG(par, PM3FBWriteMode,
321 PM3FBWriteMode_WriteEnable |
322 PM3FBWriteMode_OpaqueSpan |
323 PM3FBWriteMode_Enable0);
324 PM3_WRITE_REG(par, PM3FBWriteBufferAddr0, 0x0);
325 PM3_WRITE_REG(par, PM3FBWriteBufferOffset0, 0x0);
326 PM3_WRITE_REG(par, PM3FBWriteBufferWidth0,
327 PM3FBWriteBufferWidth_Width(width));
328
329 PM3_WRITE_REG(par, PM3SizeOfFramebuffer, 0x0);
330 {
331 /* size in lines of FB */
332 unsigned long sofb = info->screen_size /
333 info->fix.line_length;
334 if (sofb > 4095)
335 PM3_WRITE_REG(par, PM3SizeOfFramebuffer, 4095);
336 else
337 PM3_WRITE_REG(par, PM3SizeOfFramebuffer, sofb);
338
339 switch (info->var.bits_per_pixel) {
340 case 8:
341 PM3_WRITE_REG(par, PM3DitherMode,
342 (1 << 10) | (2 << 3));
343 break;
344 case 16:
345 PM3_WRITE_REG(par, PM3DitherMode,
346 (1 << 10) | (1 << 3));
347 break;
348 case 32:
349 PM3_WRITE_REG(par, PM3DitherMode,
350 (1 << 10) | (0 << 3));
351 break;
352 default:
353 DPRINTK("Unsupported depth %d\n",
354 info->var.bits_per_pixel);
355 break;
356 }
357 }
358
359 PM3_WRITE_REG(par, PM3dXDom, 0x0);
360 PM3_WRITE_REG(par, PM3dXSub, 0x0);
361 PM3_WRITE_REG(par, PM3dY, 1 << 16);
362 PM3_WRITE_REG(par, PM3StartXDom, 0x0);
363 PM3_WRITE_REG(par, PM3StartXSub, 0x0);
364 PM3_WRITE_REG(par, PM3StartY, 0x0);
365 PM3_WRITE_REG(par, PM3Count, 0x0);
366
367 /* Disable LocalBuffer. better safe than sorry */
368 PM3_WRITE_REG(par, PM3LBDestReadMode, 0x0);
369 PM3_WRITE_REG(par, PM3LBDestReadEnables, 0x0);
370 PM3_WRITE_REG(par, PM3LBSourceReadMode, 0x0);
371 PM3_WRITE_REG(par, PM3LBWriteMode, 0x0);
372
373 pm3fb_sync(info);
374 }
375
pm3fb_fillrect(struct fb_info * info,const struct fb_fillrect * region)376 static void pm3fb_fillrect(struct fb_info *info,
377 const struct fb_fillrect *region)
378 {
379 struct pm3_par *par = info->par;
380 struct fb_fillrect modded;
381 int vxres, vyres;
382 int rop;
383 u32 color = (info->fix.visual == FB_VISUAL_TRUECOLOR) ?
384 ((u32 *)info->pseudo_palette)[region->color] : region->color;
385
386 if (info->state != FBINFO_STATE_RUNNING)
387 return;
388 if (info->flags & FBINFO_HWACCEL_DISABLED) {
389 cfb_fillrect(info, region);
390 return;
391 }
392 if (region->rop == ROP_COPY )
393 rop = PM3Config2D_ForegroundROP(0x3); /* GXcopy */
394 else
395 rop = PM3Config2D_ForegroundROP(0x6) | /* GXxor */
396 PM3Config2D_FBDestReadEnable;
397
398 vxres = info->var.xres_virtual;
399 vyres = info->var.yres_virtual;
400
401 memcpy(&modded, region, sizeof(struct fb_fillrect));
402
403 if (!modded.width || !modded.height ||
404 modded.dx >= vxres || modded.dy >= vyres)
405 return;
406
407 if (modded.dx + modded.width > vxres)
408 modded.width = vxres - modded.dx;
409 if (modded.dy + modded.height > vyres)
410 modded.height = vyres - modded.dy;
411
412 if (info->var.bits_per_pixel == 8)
413 color |= color << 8;
414 if (info->var.bits_per_pixel <= 16)
415 color |= color << 16;
416
417 PM3_WAIT(par, 4);
418 /* ROP Ox3 is GXcopy */
419 PM3_WRITE_REG(par, PM3Config2D,
420 PM3Config2D_UseConstantSource |
421 PM3Config2D_ForegroundROPEnable |
422 rop |
423 PM3Config2D_FBWriteEnable);
424
425 PM3_WRITE_REG(par, PM3ForegroundColor, color);
426
427 PM3_WRITE_REG(par, PM3RectanglePosition,
428 PM3RectanglePosition_XOffset(modded.dx) |
429 PM3RectanglePosition_YOffset(modded.dy));
430
431 PM3_WRITE_REG(par, PM3Render2D,
432 PM3Render2D_XPositive |
433 PM3Render2D_YPositive |
434 PM3Render2D_Operation_Normal |
435 PM3Render2D_SpanOperation |
436 PM3Render2D_Width(modded.width) |
437 PM3Render2D_Height(modded.height));
438 }
439
pm3fb_copyarea(struct fb_info * info,const struct fb_copyarea * area)440 static void pm3fb_copyarea(struct fb_info *info,
441 const struct fb_copyarea *area)
442 {
443 struct pm3_par *par = info->par;
444 struct fb_copyarea modded;
445 u32 vxres, vyres;
446 int x_align, o_x, o_y;
447
448 if (info->state != FBINFO_STATE_RUNNING)
449 return;
450 if (info->flags & FBINFO_HWACCEL_DISABLED) {
451 cfb_copyarea(info, area);
452 return;
453 }
454
455 memcpy(&modded, area, sizeof(struct fb_copyarea));
456
457 vxres = info->var.xres_virtual;
458 vyres = info->var.yres_virtual;
459
460 if (!modded.width || !modded.height ||
461 modded.sx >= vxres || modded.sy >= vyres ||
462 modded.dx >= vxres || modded.dy >= vyres)
463 return;
464
465 if (modded.sx + modded.width > vxres)
466 modded.width = vxres - modded.sx;
467 if (modded.dx + modded.width > vxres)
468 modded.width = vxres - modded.dx;
469 if (modded.sy + modded.height > vyres)
470 modded.height = vyres - modded.sy;
471 if (modded.dy + modded.height > vyres)
472 modded.height = vyres - modded.dy;
473
474 o_x = modded.sx - modded.dx; /*(sx > dx ) ? (sx - dx) : (dx - sx); */
475 o_y = modded.sy - modded.dy; /*(sy > dy ) ? (sy - dy) : (dy - sy); */
476
477 x_align = (modded.sx & 0x1f);
478
479 PM3_WAIT(par, 6);
480
481 PM3_WRITE_REG(par, PM3Config2D,
482 PM3Config2D_UserScissorEnable |
483 PM3Config2D_ForegroundROPEnable |
484 PM3Config2D_Blocking |
485 PM3Config2D_ForegroundROP(0x3) | /* Ox3 is GXcopy */
486 PM3Config2D_FBWriteEnable);
487
488 PM3_WRITE_REG(par, PM3ScissorMinXY,
489 ((modded.dy & 0x0fff) << 16) | (modded.dx & 0x0fff));
490 PM3_WRITE_REG(par, PM3ScissorMaxXY,
491 (((modded.dy + modded.height) & 0x0fff) << 16) |
492 ((modded.dx + modded.width) & 0x0fff));
493
494 PM3_WRITE_REG(par, PM3FBSourceReadBufferOffset,
495 PM3FBSourceReadBufferOffset_XOffset(o_x) |
496 PM3FBSourceReadBufferOffset_YOffset(o_y));
497
498 PM3_WRITE_REG(par, PM3RectanglePosition,
499 PM3RectanglePosition_XOffset(modded.dx - x_align) |
500 PM3RectanglePosition_YOffset(modded.dy));
501
502 PM3_WRITE_REG(par, PM3Render2D,
503 ((modded.sx > modded.dx) ? PM3Render2D_XPositive : 0) |
504 ((modded.sy > modded.dy) ? PM3Render2D_YPositive : 0) |
505 PM3Render2D_Operation_Normal |
506 PM3Render2D_SpanOperation |
507 PM3Render2D_FBSourceReadEnable |
508 PM3Render2D_Width(modded.width + x_align) |
509 PM3Render2D_Height(modded.height));
510 }
511
pm3fb_imageblit(struct fb_info * info,const struct fb_image * image)512 static void pm3fb_imageblit(struct fb_info *info, const struct fb_image *image)
513 {
514 struct pm3_par *par = info->par;
515 u32 height = image->height;
516 u32 fgx, bgx;
517 const u32 *src = (const u32 *)image->data;
518
519 if (info->state != FBINFO_STATE_RUNNING)
520 return;
521 if (info->flags & FBINFO_HWACCEL_DISABLED) {
522 cfb_imageblit(info, image);
523 return;
524 }
525 switch (info->fix.visual) {
526 case FB_VISUAL_PSEUDOCOLOR:
527 fgx = image->fg_color;
528 bgx = image->bg_color;
529 break;
530 case FB_VISUAL_TRUECOLOR:
531 default:
532 fgx = par->palette[image->fg_color];
533 bgx = par->palette[image->bg_color];
534 break;
535 }
536 if (image->depth != 1) {
537 cfb_imageblit(info, image);
538 return;
539 }
540
541 if (info->var.bits_per_pixel == 8) {
542 fgx |= fgx << 8;
543 bgx |= bgx << 8;
544 }
545 if (info->var.bits_per_pixel <= 16) {
546 fgx |= fgx << 16;
547 bgx |= bgx << 16;
548 }
549
550 PM3_WAIT(par, 7);
551
552 PM3_WRITE_REG(par, PM3ForegroundColor, fgx);
553 PM3_WRITE_REG(par, PM3BackgroundColor, bgx);
554
555 /* ROP Ox3 is GXcopy */
556 PM3_WRITE_REG(par, PM3Config2D,
557 PM3Config2D_UserScissorEnable |
558 PM3Config2D_UseConstantSource |
559 PM3Config2D_ForegroundROPEnable |
560 PM3Config2D_ForegroundROP(0x3) |
561 PM3Config2D_OpaqueSpan |
562 PM3Config2D_FBWriteEnable);
563 PM3_WRITE_REG(par, PM3ScissorMinXY,
564 ((image->dy & 0x0fff) << 16) | (image->dx & 0x0fff));
565 PM3_WRITE_REG(par, PM3ScissorMaxXY,
566 (((image->dy + image->height) & 0x0fff) << 16) |
567 ((image->dx + image->width) & 0x0fff));
568 PM3_WRITE_REG(par, PM3RectanglePosition,
569 PM3RectanglePosition_XOffset(image->dx) |
570 PM3RectanglePosition_YOffset(image->dy));
571 PM3_WRITE_REG(par, PM3Render2D,
572 PM3Render2D_XPositive |
573 PM3Render2D_YPositive |
574 PM3Render2D_Operation_SyncOnBitMask |
575 PM3Render2D_SpanOperation |
576 PM3Render2D_Width(image->width) |
577 PM3Render2D_Height(image->height));
578
579
580 while (height--) {
581 int width = ((image->width + 7) >> 3)
582 + info->pixmap.scan_align - 1;
583 width >>= 2;
584
585 while (width >= PM3_FIFO_SIZE) {
586 int i = PM3_FIFO_SIZE - 1;
587
588 PM3_WAIT(par, PM3_FIFO_SIZE);
589 while (i--) {
590 PM3_WRITE_REG(par, PM3BitMaskPattern, *src);
591 src++;
592 }
593 width -= PM3_FIFO_SIZE - 1;
594 }
595
596 PM3_WAIT(par, width + 1);
597 while (width--) {
598 PM3_WRITE_REG(par, PM3BitMaskPattern, *src);
599 src++;
600 }
601 }
602 }
603 /* end of acceleration functions */
604
605 /*
606 * Hardware Cursor support.
607 */
608 static const u8 cursor_bits_lookup[16] = {
609 0x00, 0x40, 0x10, 0x50, 0x04, 0x44, 0x14, 0x54,
610 0x01, 0x41, 0x11, 0x51, 0x05, 0x45, 0x15, 0x55
611 };
612
pm3fb_cursor(struct fb_info * info,struct fb_cursor * cursor)613 static int pm3fb_cursor(struct fb_info *info, struct fb_cursor *cursor)
614 {
615 struct pm3_par *par = info->par;
616 u8 mode;
617
618 if (!hwcursor)
619 return -EINVAL; /* just to force soft_cursor() call */
620
621 /* Too large of a cursor or wrong bpp :-( */
622 if (cursor->image.width > 64 ||
623 cursor->image.height > 64 ||
624 cursor->image.depth > 1)
625 return -EINVAL;
626
627 mode = PM3RD_CursorMode_TYPE_X;
628 if (cursor->enable)
629 mode |= PM3RD_CursorMode_CURSOR_ENABLE;
630
631 PM3_WRITE_DAC_REG(par, PM3RD_CursorMode, mode);
632
633 /*
634 * If the cursor is not be changed this means either we want the
635 * current cursor state (if enable is set) or we want to query what
636 * we can do with the cursor (if enable is not set)
637 */
638 if (!cursor->set)
639 return 0;
640
641 if (cursor->set & FB_CUR_SETPOS) {
642 int x = cursor->image.dx - info->var.xoffset;
643 int y = cursor->image.dy - info->var.yoffset;
644
645 PM3_WRITE_DAC_REG(par, PM3RD_CursorXLow, x & 0xff);
646 PM3_WRITE_DAC_REG(par, PM3RD_CursorXHigh, (x >> 8) & 0xf);
647 PM3_WRITE_DAC_REG(par, PM3RD_CursorYLow, y & 0xff);
648 PM3_WRITE_DAC_REG(par, PM3RD_CursorYHigh, (y >> 8) & 0xf);
649 }
650
651 if (cursor->set & FB_CUR_SETHOT) {
652 PM3_WRITE_DAC_REG(par, PM3RD_CursorHotSpotX,
653 cursor->hot.x & 0x3f);
654 PM3_WRITE_DAC_REG(par, PM3RD_CursorHotSpotY,
655 cursor->hot.y & 0x3f);
656 }
657
658 if (cursor->set & FB_CUR_SETCMAP) {
659 u32 fg_idx = cursor->image.fg_color;
660 u32 bg_idx = cursor->image.bg_color;
661 struct fb_cmap cmap = info->cmap;
662
663 /* the X11 driver says one should use these color registers */
664 PM3_WRITE_DAC_REG(par, PM3RD_CursorPalette(39),
665 cmap.red[fg_idx] >> 8 );
666 PM3_WRITE_DAC_REG(par, PM3RD_CursorPalette(40),
667 cmap.green[fg_idx] >> 8 );
668 PM3_WRITE_DAC_REG(par, PM3RD_CursorPalette(41),
669 cmap.blue[fg_idx] >> 8 );
670
671 PM3_WRITE_DAC_REG(par, PM3RD_CursorPalette(42),
672 cmap.red[bg_idx] >> 8 );
673 PM3_WRITE_DAC_REG(par, PM3RD_CursorPalette(43),
674 cmap.green[bg_idx] >> 8 );
675 PM3_WRITE_DAC_REG(par, PM3RD_CursorPalette(44),
676 cmap.blue[bg_idx] >> 8 );
677 }
678
679 if (cursor->set & (FB_CUR_SETSHAPE | FB_CUR_SETIMAGE)) {
680 u8 *bitmap = (u8 *)cursor->image.data;
681 u8 *mask = (u8 *)cursor->mask;
682 int i;
683 int pos = PM3RD_CursorPattern(0);
684
685 for (i = 0; i < cursor->image.height; i++) {
686 int j = (cursor->image.width + 7) >> 3;
687 int k = 8 - j;
688
689 for (; j > 0; j--) {
690 u8 data = *bitmap ^ *mask;
691
692 if (cursor->rop == ROP_COPY)
693 data = *mask & *bitmap;
694 /* Upper 4 bits of bitmap data */
695 PM3_WRITE_DAC_REG(par, pos++,
696 cursor_bits_lookup[data >> 4] |
697 (cursor_bits_lookup[*mask >> 4] << 1));
698 /* Lower 4 bits of bitmap */
699 PM3_WRITE_DAC_REG(par, pos++,
700 cursor_bits_lookup[data & 0xf] |
701 (cursor_bits_lookup[*mask & 0xf] << 1));
702 bitmap++;
703 mask++;
704 }
705 for (; k > 0; k--) {
706 PM3_WRITE_DAC_REG(par, pos++, 0);
707 PM3_WRITE_DAC_REG(par, pos++, 0);
708 }
709 }
710 while (pos < PM3RD_CursorPattern(1024))
711 PM3_WRITE_DAC_REG(par, pos++, 0);
712 }
713 return 0;
714 }
715
716 /* write the mode to registers */
pm3fb_write_mode(struct fb_info * info)717 static void pm3fb_write_mode(struct fb_info *info)
718 {
719 struct pm3_par *par = info->par;
720 char tempsync = 0x00;
721 char tempmisc = 0x00;
722 const u32 hsstart = info->var.right_margin;
723 const u32 hsend = hsstart + info->var.hsync_len;
724 const u32 hbend = hsend + info->var.left_margin;
725 const u32 xres = (info->var.xres + 31) & ~31;
726 const u32 htotal = xres + hbend;
727 const u32 vsstart = info->var.lower_margin;
728 const u32 vsend = vsstart + info->var.vsync_len;
729 const u32 vbend = vsend + info->var.upper_margin;
730 const u32 vtotal = info->var.yres + vbend;
731 const u32 width = (info->var.xres_virtual + 7) & ~7;
732 const unsigned bpp = info->var.bits_per_pixel;
733
734 PM3_WAIT(par, 20);
735 PM3_WRITE_REG(par, PM3MemBypassWriteMask, 0xffffffff);
736 PM3_WRITE_REG(par, PM3Aperture0, 0x00000000);
737 PM3_WRITE_REG(par, PM3Aperture1, 0x00000000);
738 PM3_WRITE_REG(par, PM3FIFODis, 0x00000007);
739
740 PM3_WRITE_REG(par, PM3HTotal,
741 pm3fb_shift_bpp(bpp, htotal - 1));
742 PM3_WRITE_REG(par, PM3HsEnd,
743 pm3fb_shift_bpp(bpp, hsend));
744 PM3_WRITE_REG(par, PM3HsStart,
745 pm3fb_shift_bpp(bpp, hsstart));
746 PM3_WRITE_REG(par, PM3HbEnd,
747 pm3fb_shift_bpp(bpp, hbend));
748 PM3_WRITE_REG(par, PM3HgEnd,
749 pm3fb_shift_bpp(bpp, hbend));
750 PM3_WRITE_REG(par, PM3ScreenStride,
751 pm3fb_shift_bpp(bpp, width));
752 PM3_WRITE_REG(par, PM3VTotal, vtotal - 1);
753 PM3_WRITE_REG(par, PM3VsEnd, vsend - 1);
754 PM3_WRITE_REG(par, PM3VsStart, vsstart - 1);
755 PM3_WRITE_REG(par, PM3VbEnd, vbend);
756
757 switch (bpp) {
758 case 8:
759 PM3_WRITE_REG(par, PM3ByAperture1Mode,
760 PM3ByApertureMode_PIXELSIZE_8BIT);
761 PM3_WRITE_REG(par, PM3ByAperture2Mode,
762 PM3ByApertureMode_PIXELSIZE_8BIT);
763 break;
764
765 case 16:
766 #ifndef __BIG_ENDIAN
767 PM3_WRITE_REG(par, PM3ByAperture1Mode,
768 PM3ByApertureMode_PIXELSIZE_16BIT);
769 PM3_WRITE_REG(par, PM3ByAperture2Mode,
770 PM3ByApertureMode_PIXELSIZE_16BIT);
771 #else
772 PM3_WRITE_REG(par, PM3ByAperture1Mode,
773 PM3ByApertureMode_PIXELSIZE_16BIT |
774 PM3ByApertureMode_BYTESWAP_BADC);
775 PM3_WRITE_REG(par, PM3ByAperture2Mode,
776 PM3ByApertureMode_PIXELSIZE_16BIT |
777 PM3ByApertureMode_BYTESWAP_BADC);
778 #endif /* ! __BIG_ENDIAN */
779 break;
780
781 case 32:
782 #ifndef __BIG_ENDIAN
783 PM3_WRITE_REG(par, PM3ByAperture1Mode,
784 PM3ByApertureMode_PIXELSIZE_32BIT);
785 PM3_WRITE_REG(par, PM3ByAperture2Mode,
786 PM3ByApertureMode_PIXELSIZE_32BIT);
787 #else
788 PM3_WRITE_REG(par, PM3ByAperture1Mode,
789 PM3ByApertureMode_PIXELSIZE_32BIT |
790 PM3ByApertureMode_BYTESWAP_DCBA);
791 PM3_WRITE_REG(par, PM3ByAperture2Mode,
792 PM3ByApertureMode_PIXELSIZE_32BIT |
793 PM3ByApertureMode_BYTESWAP_DCBA);
794 #endif /* ! __BIG_ENDIAN */
795 break;
796
797 default:
798 DPRINTK("Unsupported depth %d\n", bpp);
799 break;
800 }
801
802 /*
803 * Oxygen VX1 - it appears that setting PM3VideoControl and
804 * then PM3RD_SyncControl to the same SYNC settings undoes
805 * any net change - they seem to xor together. Only set the
806 * sync options in PM3RD_SyncControl. --rmk
807 */
808 {
809 unsigned int video = par->video;
810
811 video &= ~(PM3VideoControl_HSYNC_MASK |
812 PM3VideoControl_VSYNC_MASK);
813 video |= PM3VideoControl_HSYNC_ACTIVE_HIGH |
814 PM3VideoControl_VSYNC_ACTIVE_HIGH;
815 PM3_WRITE_REG(par, PM3VideoControl, video);
816 }
817 PM3_WRITE_REG(par, PM3VClkCtl,
818 (PM3_READ_REG(par, PM3VClkCtl) & 0xFFFFFFFC));
819 PM3_WRITE_REG(par, PM3ScreenBase, par->base);
820 PM3_WRITE_REG(par, PM3ChipConfig,
821 (PM3_READ_REG(par, PM3ChipConfig) & 0xFFFFFFFD));
822
823 wmb();
824 {
825 unsigned char m; /* ClkPreScale */
826 unsigned char n; /* ClkFeedBackScale */
827 unsigned char p; /* ClkPostScale */
828 unsigned long pixclock = PICOS2KHZ(info->var.pixclock);
829
830 (void)pm3fb_calculate_clock(pixclock, &m, &n, &p);
831
832 DPRINTK("Pixclock: %ld, Pre: %d, Feedback: %d, Post: %d\n",
833 pixclock, (int) m, (int) n, (int) p);
834
835 PM3_WRITE_DAC_REG(par, PM3RD_DClk0PreScale, m);
836 PM3_WRITE_DAC_REG(par, PM3RD_DClk0FeedbackScale, n);
837 PM3_WRITE_DAC_REG(par, PM3RD_DClk0PostScale, p);
838 }
839 /*
840 PM3_WRITE_DAC_REG(par, PM3RD_IndexControl, 0x00);
841 */
842 /*
843 PM3_SLOW_WRITE_REG(par, PM3RD_IndexControl, 0x00);
844 */
845 if ((par->video & PM3VideoControl_HSYNC_MASK) ==
846 PM3VideoControl_HSYNC_ACTIVE_HIGH)
847 tempsync |= PM3RD_SyncControl_HSYNC_ACTIVE_HIGH;
848 if ((par->video & PM3VideoControl_VSYNC_MASK) ==
849 PM3VideoControl_VSYNC_ACTIVE_HIGH)
850 tempsync |= PM3RD_SyncControl_VSYNC_ACTIVE_HIGH;
851
852 PM3_WRITE_DAC_REG(par, PM3RD_SyncControl, tempsync);
853 DPRINTK("PM3RD_SyncControl: %d\n", tempsync);
854
855 PM3_WRITE_DAC_REG(par, PM3RD_DACControl, 0x00);
856
857 switch (pm3fb_depth(&info->var)) {
858 case 8:
859 PM3_WRITE_DAC_REG(par, PM3RD_PixelSize,
860 PM3RD_PixelSize_8_BIT_PIXELS);
861 PM3_WRITE_DAC_REG(par, PM3RD_ColorFormat,
862 PM3RD_ColorFormat_CI8_COLOR |
863 PM3RD_ColorFormat_COLOR_ORDER_BLUE_LOW);
864 tempmisc |= PM3RD_MiscControl_HIGHCOLOR_RES_ENABLE;
865 break;
866 case 12:
867 PM3_WRITE_DAC_REG(par, PM3RD_PixelSize,
868 PM3RD_PixelSize_16_BIT_PIXELS);
869 PM3_WRITE_DAC_REG(par, PM3RD_ColorFormat,
870 PM3RD_ColorFormat_4444_COLOR |
871 PM3RD_ColorFormat_COLOR_ORDER_BLUE_LOW |
872 PM3RD_ColorFormat_LINEAR_COLOR_EXT_ENABLE);
873 tempmisc |= PM3RD_MiscControl_DIRECTCOLOR_ENABLE |
874 PM3RD_MiscControl_HIGHCOLOR_RES_ENABLE;
875 break;
876 case 15:
877 PM3_WRITE_DAC_REG(par, PM3RD_PixelSize,
878 PM3RD_PixelSize_16_BIT_PIXELS);
879 PM3_WRITE_DAC_REG(par, PM3RD_ColorFormat,
880 PM3RD_ColorFormat_5551_FRONT_COLOR |
881 PM3RD_ColorFormat_COLOR_ORDER_BLUE_LOW |
882 PM3RD_ColorFormat_LINEAR_COLOR_EXT_ENABLE);
883 tempmisc |= PM3RD_MiscControl_DIRECTCOLOR_ENABLE |
884 PM3RD_MiscControl_HIGHCOLOR_RES_ENABLE;
885 break;
886 case 16:
887 PM3_WRITE_DAC_REG(par, PM3RD_PixelSize,
888 PM3RD_PixelSize_16_BIT_PIXELS);
889 PM3_WRITE_DAC_REG(par, PM3RD_ColorFormat,
890 PM3RD_ColorFormat_565_FRONT_COLOR |
891 PM3RD_ColorFormat_COLOR_ORDER_BLUE_LOW |
892 PM3RD_ColorFormat_LINEAR_COLOR_EXT_ENABLE);
893 tempmisc |= PM3RD_MiscControl_DIRECTCOLOR_ENABLE |
894 PM3RD_MiscControl_HIGHCOLOR_RES_ENABLE;
895 break;
896 case 32:
897 PM3_WRITE_DAC_REG(par, PM3RD_PixelSize,
898 PM3RD_PixelSize_32_BIT_PIXELS);
899 PM3_WRITE_DAC_REG(par, PM3RD_ColorFormat,
900 PM3RD_ColorFormat_8888_COLOR |
901 PM3RD_ColorFormat_COLOR_ORDER_BLUE_LOW);
902 tempmisc |= PM3RD_MiscControl_DIRECTCOLOR_ENABLE |
903 PM3RD_MiscControl_HIGHCOLOR_RES_ENABLE;
904 break;
905 }
906 PM3_WRITE_DAC_REG(par, PM3RD_MiscControl, tempmisc);
907 }
908
909 /*
910 * hardware independent functions
911 */
pm3fb_check_var(struct fb_var_screeninfo * var,struct fb_info * info)912 static int pm3fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
913 {
914 u32 lpitch;
915 unsigned bpp = var->red.length + var->green.length
916 + var->blue.length + var->transp.length;
917
918 if (bpp != var->bits_per_pixel) {
919 /* set predefined mode for bits_per_pixel settings */
920
921 switch (var->bits_per_pixel) {
922 case 8:
923 var->red.length = 8;
924 var->green.length = 8;
925 var->blue.length = 8;
926 var->red.offset = 0;
927 var->green.offset = 0;
928 var->blue.offset = 0;
929 var->transp.offset = 0;
930 var->transp.length = 0;
931 break;
932 case 16:
933 var->red.length = 5;
934 var->blue.length = 5;
935 var->green.length = 6;
936 var->transp.length = 0;
937 break;
938 case 32:
939 var->red.length = 8;
940 var->green.length = 8;
941 var->blue.length = 8;
942 var->transp.length = 8;
943 break;
944 default:
945 DPRINTK("depth not supported: %u\n",
946 var->bits_per_pixel);
947 return -EINVAL;
948 }
949 }
950 /* it is assumed BGRA order */
951 if (var->bits_per_pixel > 8 ) {
952 var->blue.offset = 0;
953 var->green.offset = var->blue.length;
954 var->red.offset = var->green.offset + var->green.length;
955 var->transp.offset = var->red.offset + var->red.length;
956 }
957 var->height = -1;
958 var->width = -1;
959
960 if (var->xres != var->xres_virtual) {
961 DPRINTK("virtual x resolution != "
962 "physical x resolution not supported\n");
963 return -EINVAL;
964 }
965
966 if (var->yres > var->yres_virtual) {
967 DPRINTK("virtual y resolution < "
968 "physical y resolution not possible\n");
969 return -EINVAL;
970 }
971
972 if (var->xoffset) {
973 DPRINTK("xoffset not supported\n");
974 return -EINVAL;
975 }
976
977 if ((var->vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) {
978 DPRINTK("interlace not supported\n");
979 return -EINVAL;
980 }
981
982 var->xres = (var->xres + 31) & ~31; /* could sometimes be 8 */
983 lpitch = var->xres * ((var->bits_per_pixel + 7) >> 3);
984
985 if (var->xres < 200 || var->xres > 2048) {
986 DPRINTK("width not supported: %u\n", var->xres);
987 return -EINVAL;
988 }
989
990 if (var->yres < 200 || var->yres > 4095) {
991 DPRINTK("height not supported: %u\n", var->yres);
992 return -EINVAL;
993 }
994
995 if (lpitch * var->yres_virtual > info->fix.smem_len) {
996 DPRINTK("no memory for screen (%ux%ux%u)\n",
997 var->xres, var->yres_virtual, var->bits_per_pixel);
998 return -EINVAL;
999 }
1000
1001 if (PICOS2KHZ(var->pixclock) > PM3_MAX_PIXCLOCK) {
1002 DPRINTK("pixclock too high (%ldKHz)\n",
1003 PICOS2KHZ(var->pixclock));
1004 return -EINVAL;
1005 }
1006
1007 var->accel_flags = 0; /* Can't mmap if this is on */
1008
1009 DPRINTK("Checking graphics mode at %dx%d depth %d\n",
1010 var->xres, var->yres, var->bits_per_pixel);
1011 return 0;
1012 }
1013
pm3fb_set_par(struct fb_info * info)1014 static int pm3fb_set_par(struct fb_info *info)
1015 {
1016 struct pm3_par *par = info->par;
1017 const u32 xres = (info->var.xres + 31) & ~31;
1018 const unsigned bpp = info->var.bits_per_pixel;
1019
1020 par->base = pm3fb_shift_bpp(bpp, (info->var.yoffset * xres)
1021 + info->var.xoffset);
1022 par->video = 0;
1023
1024 if (info->var.sync & FB_SYNC_HOR_HIGH_ACT)
1025 par->video |= PM3VideoControl_HSYNC_ACTIVE_HIGH;
1026 else
1027 par->video |= PM3VideoControl_HSYNC_ACTIVE_LOW;
1028
1029 if (info->var.sync & FB_SYNC_VERT_HIGH_ACT)
1030 par->video |= PM3VideoControl_VSYNC_ACTIVE_HIGH;
1031 else
1032 par->video |= PM3VideoControl_VSYNC_ACTIVE_LOW;
1033
1034 if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_DOUBLE)
1035 par->video |= PM3VideoControl_LINE_DOUBLE_ON;
1036
1037 if ((info->var.activate & FB_ACTIVATE_MASK) == FB_ACTIVATE_NOW)
1038 par->video |= PM3VideoControl_ENABLE;
1039 else
1040 DPRINTK("PM3Video disabled\n");
1041
1042 switch (bpp) {
1043 case 8:
1044 par->video |= PM3VideoControl_PIXELSIZE_8BIT;
1045 break;
1046 case 16:
1047 par->video |= PM3VideoControl_PIXELSIZE_16BIT;
1048 break;
1049 case 32:
1050 par->video |= PM3VideoControl_PIXELSIZE_32BIT;
1051 break;
1052 default:
1053 DPRINTK("Unsupported depth\n");
1054 break;
1055 }
1056
1057 info->fix.visual =
1058 (bpp == 8) ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
1059 info->fix.line_length = ((info->var.xres_virtual + 7) >> 3) * bpp;
1060
1061 /* pm3fb_clear_memory(info, 0);*/
1062 pm3fb_clear_colormap(par, 0, 0, 0);
1063 PM3_WRITE_DAC_REG(par, PM3RD_CursorMode, 0);
1064 pm3fb_init_engine(info);
1065 pm3fb_write_mode(info);
1066 return 0;
1067 }
1068
pm3fb_setcolreg(unsigned regno,unsigned red,unsigned green,unsigned blue,unsigned transp,struct fb_info * info)1069 static int pm3fb_setcolreg(unsigned regno, unsigned red, unsigned green,
1070 unsigned blue, unsigned transp,
1071 struct fb_info *info)
1072 {
1073 struct pm3_par *par = info->par;
1074
1075 if (regno >= 256) /* no. of hw registers */
1076 return -EINVAL;
1077
1078 /* grayscale works only partially under directcolor */
1079 /* grayscale = 0.30*R + 0.59*G + 0.11*B */
1080 if (info->var.grayscale)
1081 red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8;
1082
1083 /* Directcolor:
1084 * var->{color}.offset contains start of bitfield
1085 * var->{color}.length contains length of bitfield
1086 * {hardwarespecific} contains width of DAC
1087 * pseudo_palette[X] is programmed to (X << red.offset) |
1088 * (X << green.offset) |
1089 * (X << blue.offset)
1090 * RAMDAC[X] is programmed to (red, green, blue)
1091 * color depth = SUM(var->{color}.length)
1092 *
1093 * Pseudocolor:
1094 * var->{color}.offset is 0
1095 * var->{color}.length contains width of DAC or the number
1096 * of unique colors available (color depth)
1097 * pseudo_palette is not used
1098 * RAMDAC[X] is programmed to (red, green, blue)
1099 * color depth = var->{color}.length
1100 */
1101
1102 /*
1103 * This is the point where the color is converted to something that
1104 * is acceptable by the hardware.
1105 */
1106 #define CNVT_TOHW(val, width) ((((val) << (width)) + 0x7FFF - (val)) >> 16)
1107 red = CNVT_TOHW(red, info->var.red.length);
1108 green = CNVT_TOHW(green, info->var.green.length);
1109 blue = CNVT_TOHW(blue, info->var.blue.length);
1110 transp = CNVT_TOHW(transp, info->var.transp.length);
1111 #undef CNVT_TOHW
1112
1113 if (info->fix.visual == FB_VISUAL_TRUECOLOR ||
1114 info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
1115 u32 v;
1116
1117 if (regno >= 16)
1118 return -EINVAL;
1119
1120 v = (red << info->var.red.offset) |
1121 (green << info->var.green.offset) |
1122 (blue << info->var.blue.offset) |
1123 (transp << info->var.transp.offset);
1124
1125 switch (info->var.bits_per_pixel) {
1126 case 8:
1127 break;
1128 case 16:
1129 case 32:
1130 ((u32 *)(info->pseudo_palette))[regno] = v;
1131 break;
1132 }
1133 return 0;
1134 } else if (info->fix.visual == FB_VISUAL_PSEUDOCOLOR)
1135 pm3fb_set_color(par, regno, red, green, blue);
1136
1137 return 0;
1138 }
1139
pm3fb_pan_display(struct fb_var_screeninfo * var,struct fb_info * info)1140 static int pm3fb_pan_display(struct fb_var_screeninfo *var,
1141 struct fb_info *info)
1142 {
1143 struct pm3_par *par = info->par;
1144 const u32 xres = (info->var.xres + 31) & ~31;
1145
1146 par->base = pm3fb_shift_bpp(info->var.bits_per_pixel,
1147 (var->yoffset * xres)
1148 + var->xoffset);
1149 PM3_WAIT(par, 1);
1150 PM3_WRITE_REG(par, PM3ScreenBase, par->base);
1151 return 0;
1152 }
1153
pm3fb_blank(int blank_mode,struct fb_info * info)1154 static int pm3fb_blank(int blank_mode, struct fb_info *info)
1155 {
1156 struct pm3_par *par = info->par;
1157 u32 video = par->video;
1158
1159 /*
1160 * Oxygen VX1 - it appears that setting PM3VideoControl and
1161 * then PM3RD_SyncControl to the same SYNC settings undoes
1162 * any net change - they seem to xor together. Only set the
1163 * sync options in PM3RD_SyncControl. --rmk
1164 */
1165 video &= ~(PM3VideoControl_HSYNC_MASK |
1166 PM3VideoControl_VSYNC_MASK);
1167 video |= PM3VideoControl_HSYNC_ACTIVE_HIGH |
1168 PM3VideoControl_VSYNC_ACTIVE_HIGH;
1169
1170 switch (blank_mode) {
1171 case FB_BLANK_UNBLANK:
1172 video |= PM3VideoControl_ENABLE;
1173 break;
1174 case FB_BLANK_NORMAL:
1175 video &= ~PM3VideoControl_ENABLE;
1176 break;
1177 case FB_BLANK_HSYNC_SUSPEND:
1178 video &= ~(PM3VideoControl_HSYNC_MASK |
1179 PM3VideoControl_BLANK_ACTIVE_LOW);
1180 break;
1181 case FB_BLANK_VSYNC_SUSPEND:
1182 video &= ~(PM3VideoControl_VSYNC_MASK |
1183 PM3VideoControl_BLANK_ACTIVE_LOW);
1184 break;
1185 case FB_BLANK_POWERDOWN:
1186 video &= ~(PM3VideoControl_HSYNC_MASK |
1187 PM3VideoControl_VSYNC_MASK |
1188 PM3VideoControl_BLANK_ACTIVE_LOW);
1189 break;
1190 default:
1191 DPRINTK("Unsupported blanking %d\n", blank_mode);
1192 return 1;
1193 }
1194
1195 PM3_WAIT(par, 1);
1196 PM3_WRITE_REG(par, PM3VideoControl, video);
1197 return 0;
1198 }
1199
1200 /*
1201 * Frame buffer operations
1202 */
1203
1204 static const struct fb_ops pm3fb_ops = {
1205 .owner = THIS_MODULE,
1206 .fb_check_var = pm3fb_check_var,
1207 .fb_set_par = pm3fb_set_par,
1208 .fb_setcolreg = pm3fb_setcolreg,
1209 .fb_pan_display = pm3fb_pan_display,
1210 .fb_fillrect = pm3fb_fillrect,
1211 .fb_copyarea = pm3fb_copyarea,
1212 .fb_imageblit = pm3fb_imageblit,
1213 .fb_blank = pm3fb_blank,
1214 .fb_sync = pm3fb_sync,
1215 .fb_cursor = pm3fb_cursor,
1216 };
1217
1218 /* ------------------------------------------------------------------------- */
1219
1220 /*
1221 * Initialization
1222 */
1223
1224 /* mmio register are already mapped when this function is called */
1225 /* the pm3fb_fix.smem_start is also set */
pm3fb_size_memory(struct pm3_par * par)1226 static unsigned long pm3fb_size_memory(struct pm3_par *par)
1227 {
1228 unsigned long memsize = 0;
1229 unsigned long tempBypass, i, temp1, temp2;
1230 unsigned char __iomem *screen_mem;
1231
1232 pm3fb_fix.smem_len = 64 * 1024l * 1024; /* request full aperture size */
1233 /* Linear frame buffer - request region and map it. */
1234 if (!request_mem_region(pm3fb_fix.smem_start, pm3fb_fix.smem_len,
1235 "pm3fb smem")) {
1236 printk(KERN_WARNING "pm3fb: Can't reserve smem.\n");
1237 return 0;
1238 }
1239 screen_mem =
1240 ioremap(pm3fb_fix.smem_start, pm3fb_fix.smem_len);
1241 if (!screen_mem) {
1242 printk(KERN_WARNING "pm3fb: Can't ioremap smem area.\n");
1243 release_mem_region(pm3fb_fix.smem_start, pm3fb_fix.smem_len);
1244 return 0;
1245 }
1246
1247 /* TODO: card-specific stuff, *before* accessing *any* FB memory */
1248 /* For Appian Jeronimo 2000 board second head */
1249
1250 tempBypass = PM3_READ_REG(par, PM3MemBypassWriteMask);
1251
1252 DPRINTK("PM3MemBypassWriteMask was: 0x%08lx\n", tempBypass);
1253
1254 PM3_WAIT(par, 1);
1255 PM3_WRITE_REG(par, PM3MemBypassWriteMask, 0xFFFFFFFF);
1256
1257 /* pm3 split up memory, replicates, and do a lot of
1258 * nasty stuff IMHO ;-)
1259 */
1260 for (i = 0; i < 32; i++) {
1261 fb_writel(i * 0x00345678,
1262 (screen_mem + (i * 1048576)));
1263 mb();
1264 temp1 = fb_readl((screen_mem + (i * 1048576)));
1265
1266 /* Let's check for wrapover, write will fail at 16MB boundary */
1267 if (temp1 == (i * 0x00345678))
1268 memsize = i;
1269 else
1270 break;
1271 }
1272
1273 DPRINTK("First detect pass already got %ld MB\n", memsize + 1);
1274
1275 if (memsize + 1 == i) {
1276 for (i = 0; i < 32; i++) {
1277 /* Clear first 32MB ; 0 is 0, no need to byteswap */
1278 writel(0x0000000, (screen_mem + (i * 1048576)));
1279 }
1280 wmb();
1281
1282 for (i = 32; i < 64; i++) {
1283 fb_writel(i * 0x00345678,
1284 (screen_mem + (i * 1048576)));
1285 mb();
1286 temp1 =
1287 fb_readl((screen_mem + (i * 1048576)));
1288 temp2 =
1289 fb_readl((screen_mem + ((i - 32) * 1048576)));
1290 /* different value, different RAM... */
1291 if ((temp1 == (i * 0x00345678)) && (temp2 == 0))
1292 memsize = i;
1293 else
1294 break;
1295 }
1296 }
1297 DPRINTK("Second detect pass got %ld MB\n", memsize + 1);
1298
1299 PM3_WAIT(par, 1);
1300 PM3_WRITE_REG(par, PM3MemBypassWriteMask, tempBypass);
1301
1302 iounmap(screen_mem);
1303 release_mem_region(pm3fb_fix.smem_start, pm3fb_fix.smem_len);
1304 memsize = 1048576 * (memsize + 1);
1305
1306 DPRINTK("Returning 0x%08lx bytes\n", memsize);
1307
1308 return memsize;
1309 }
1310
pm3fb_probe(struct pci_dev * dev,const struct pci_device_id * ent)1311 static int pm3fb_probe(struct pci_dev *dev, const struct pci_device_id *ent)
1312 {
1313 struct fb_info *info;
1314 struct pm3_par *par;
1315 struct device *device = &dev->dev; /* for pci drivers */
1316 int err;
1317 int retval = -ENXIO;
1318
1319 err = aperture_remove_conflicting_pci_devices(dev, "pm3fb");
1320 if (err)
1321 return err;
1322
1323 err = pci_enable_device(dev);
1324 if (err) {
1325 printk(KERN_WARNING "pm3fb: Can't enable PCI dev: %d\n", err);
1326 return err;
1327 }
1328 /*
1329 * Dynamically allocate info and par
1330 */
1331 info = framebuffer_alloc(sizeof(struct pm3_par), device);
1332
1333 if (!info)
1334 return -ENOMEM;
1335 par = info->par;
1336
1337 /*
1338 * Here we set the screen_base to the virtual memory address
1339 * for the framebuffer.
1340 */
1341 pm3fb_fix.mmio_start = pci_resource_start(dev, 0);
1342 pm3fb_fix.mmio_len = PM3_REGS_SIZE;
1343 #if defined(__BIG_ENDIAN)
1344 pm3fb_fix.mmio_start += PM3_REGS_SIZE;
1345 DPRINTK("Adjusting register base for big-endian.\n");
1346 #endif
1347
1348 /* Registers - request region and map it. */
1349 if (!request_mem_region(pm3fb_fix.mmio_start, pm3fb_fix.mmio_len,
1350 "pm3fb regbase")) {
1351 printk(KERN_WARNING "pm3fb: Can't reserve regbase.\n");
1352 goto err_exit_neither;
1353 }
1354 par->v_regs =
1355 ioremap(pm3fb_fix.mmio_start, pm3fb_fix.mmio_len);
1356 if (!par->v_regs) {
1357 printk(KERN_WARNING "pm3fb: Can't remap %s register area.\n",
1358 pm3fb_fix.id);
1359 release_mem_region(pm3fb_fix.mmio_start, pm3fb_fix.mmio_len);
1360 goto err_exit_neither;
1361 }
1362
1363 /* Linear frame buffer - request region and map it. */
1364 pm3fb_fix.smem_start = pci_resource_start(dev, 1);
1365 pm3fb_fix.smem_len = pm3fb_size_memory(par);
1366 if (!pm3fb_fix.smem_len) {
1367 printk(KERN_WARNING "pm3fb: Can't find memory on board.\n");
1368 goto err_exit_mmio;
1369 }
1370 if (!request_mem_region(pm3fb_fix.smem_start, pm3fb_fix.smem_len,
1371 "pm3fb smem")) {
1372 printk(KERN_WARNING "pm3fb: Can't reserve smem.\n");
1373 goto err_exit_mmio;
1374 }
1375 info->screen_base = ioremap_wc(pm3fb_fix.smem_start,
1376 pm3fb_fix.smem_len);
1377 if (!info->screen_base) {
1378 printk(KERN_WARNING "pm3fb: Can't ioremap smem area.\n");
1379 release_mem_region(pm3fb_fix.smem_start, pm3fb_fix.smem_len);
1380 goto err_exit_mmio;
1381 }
1382 info->screen_size = pm3fb_fix.smem_len;
1383
1384 if (!nomtrr)
1385 par->wc_cookie = arch_phys_wc_add(pm3fb_fix.smem_start,
1386 pm3fb_fix.smem_len);
1387 info->fbops = &pm3fb_ops;
1388
1389 par->video = PM3_READ_REG(par, PM3VideoControl);
1390
1391 info->fix = pm3fb_fix;
1392 info->pseudo_palette = par->palette;
1393 info->flags = FBINFO_HWACCEL_XPAN |
1394 FBINFO_HWACCEL_YPAN |
1395 FBINFO_HWACCEL_COPYAREA |
1396 FBINFO_HWACCEL_IMAGEBLIT |
1397 FBINFO_HWACCEL_FILLRECT;
1398
1399 if (noaccel) {
1400 printk(KERN_DEBUG "disabling acceleration\n");
1401 info->flags |= FBINFO_HWACCEL_DISABLED;
1402 }
1403 info->pixmap.addr = kmalloc(PM3_PIXMAP_SIZE, GFP_KERNEL);
1404 if (!info->pixmap.addr) {
1405 retval = -ENOMEM;
1406 goto err_exit_pixmap;
1407 }
1408 info->pixmap.size = PM3_PIXMAP_SIZE;
1409 info->pixmap.buf_align = 4;
1410 info->pixmap.scan_align = 4;
1411 info->pixmap.access_align = 32;
1412 info->pixmap.flags = FB_PIXMAP_SYSTEM;
1413
1414 /*
1415 * This should give a reasonable default video mode. The following is
1416 * done when we can set a video mode.
1417 */
1418 if (!mode_option)
1419 mode_option = "640x480@60";
1420
1421 retval = fb_find_mode(&info->var, info, mode_option, NULL, 0, NULL, 8);
1422
1423 if (!retval || retval == 4) {
1424 retval = -EINVAL;
1425 goto err_exit_both;
1426 }
1427
1428 if (fb_alloc_cmap(&info->cmap, 256, 0) < 0) {
1429 retval = -ENOMEM;
1430 goto err_exit_both;
1431 }
1432
1433 /*
1434 * For drivers that can...
1435 */
1436 pm3fb_check_var(&info->var, info);
1437
1438 if (register_framebuffer(info) < 0) {
1439 retval = -EINVAL;
1440 goto err_exit_all;
1441 }
1442 fb_info(info, "%s frame buffer device\n", info->fix.id);
1443 pci_set_drvdata(dev, info);
1444 return 0;
1445
1446 err_exit_all:
1447 fb_dealloc_cmap(&info->cmap);
1448 err_exit_both:
1449 kfree(info->pixmap.addr);
1450 err_exit_pixmap:
1451 iounmap(info->screen_base);
1452 release_mem_region(pm3fb_fix.smem_start, pm3fb_fix.smem_len);
1453 err_exit_mmio:
1454 iounmap(par->v_regs);
1455 release_mem_region(pm3fb_fix.mmio_start, pm3fb_fix.mmio_len);
1456 err_exit_neither:
1457 framebuffer_release(info);
1458 return retval;
1459 }
1460
1461 /*
1462 * Cleanup
1463 */
pm3fb_remove(struct pci_dev * dev)1464 static void pm3fb_remove(struct pci_dev *dev)
1465 {
1466 struct fb_info *info = pci_get_drvdata(dev);
1467
1468 if (info) {
1469 struct fb_fix_screeninfo *fix = &info->fix;
1470 struct pm3_par *par = info->par;
1471
1472 unregister_framebuffer(info);
1473 fb_dealloc_cmap(&info->cmap);
1474
1475 arch_phys_wc_del(par->wc_cookie);
1476 iounmap(info->screen_base);
1477 release_mem_region(fix->smem_start, fix->smem_len);
1478 iounmap(par->v_regs);
1479 release_mem_region(fix->mmio_start, fix->mmio_len);
1480
1481 kfree(info->pixmap.addr);
1482 framebuffer_release(info);
1483 }
1484 }
1485
1486 static const struct pci_device_id pm3fb_id_table[] = {
1487 { PCI_VENDOR_ID_3DLABS, 0x0a,
1488 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
1489 { 0, }
1490 };
1491
1492 /* For PCI drivers */
1493 static struct pci_driver pm3fb_driver = {
1494 .name = "pm3fb",
1495 .id_table = pm3fb_id_table,
1496 .probe = pm3fb_probe,
1497 .remove = pm3fb_remove,
1498 };
1499
1500 MODULE_DEVICE_TABLE(pci, pm3fb_id_table);
1501
1502 #ifndef MODULE
1503 /*
1504 * Setup
1505 */
1506
1507 /*
1508 * Only necessary if your driver takes special options,
1509 * otherwise we fall back on the generic fb_setup().
1510 */
pm3fb_setup(char * options)1511 static int __init pm3fb_setup(char *options)
1512 {
1513 char *this_opt;
1514
1515 /* Parse user specified options (`video=pm3fb:') */
1516 if (!options || !*options)
1517 return 0;
1518
1519 while ((this_opt = strsep(&options, ",")) != NULL) {
1520 if (!*this_opt)
1521 continue;
1522 else if (!strncmp(this_opt, "noaccel", 7))
1523 noaccel = 1;
1524 else if (!strncmp(this_opt, "hwcursor=", 9))
1525 hwcursor = simple_strtoul(this_opt + 9, NULL, 0);
1526 else if (!strncmp(this_opt, "nomtrr", 6))
1527 nomtrr = 1;
1528 else
1529 mode_option = this_opt;
1530 }
1531 return 0;
1532 }
1533 #endif /* MODULE */
1534
pm3fb_init(void)1535 static int __init pm3fb_init(void)
1536 {
1537 /*
1538 * For kernel boot options (in 'video=pm3fb:<options>' format)
1539 */
1540 #ifndef MODULE
1541 char *option = NULL;
1542 #endif
1543
1544 if (fb_modesetting_disabled("pm3fb"))
1545 return -ENODEV;
1546
1547 #ifndef MODULE
1548 if (fb_get_options("pm3fb", &option))
1549 return -ENODEV;
1550 pm3fb_setup(option);
1551 #endif
1552
1553 return pci_register_driver(&pm3fb_driver);
1554 }
1555
1556 #ifdef MODULE
pm3fb_exit(void)1557 static void __exit pm3fb_exit(void)
1558 {
1559 pci_unregister_driver(&pm3fb_driver);
1560 }
1561
1562 module_exit(pm3fb_exit);
1563 #endif
1564 module_init(pm3fb_init);
1565
1566 module_param(mode_option, charp, 0);
1567 MODULE_PARM_DESC(mode_option, "Initial video mode e.g. '648x480-8@60'");
1568 module_param(noaccel, bool, 0);
1569 MODULE_PARM_DESC(noaccel, "Disable acceleration");
1570 module_param(hwcursor, int, 0644);
1571 MODULE_PARM_DESC(hwcursor, "Enable hardware cursor "
1572 "(1=enable, 0=disable, default=1)");
1573 module_param(nomtrr, bool, 0);
1574 MODULE_PARM_DESC(nomtrr, "Disable MTRR support (0 or 1=disabled) (default=0)");
1575
1576 MODULE_DESCRIPTION("Permedia3 framebuffer device driver");
1577 MODULE_LICENSE("GPL");
1578