1 /* 2 * Permedia2 framebuffer driver. 3 * 4 * 2.5/2.6 driver: 5 * Copyright (c) 2003 Jim Hague (jim.hague@acm.org) 6 * 7 * based on 2.4 driver: 8 * Copyright (c) 1998-2000 Ilario Nardinocchi (nardinoc@CS.UniBO.IT) 9 * Copyright (c) 1999 Jakub Jelinek (jakub@redhat.com) 10 * 11 * and additional input from James Simmon's port of Hannu Mallat's tdfx 12 * driver. 13 * 14 * I have a Creative Graphics Blaster Exxtreme card - pm2fb on x86. I 15 * have no access to other pm2fb implementations. Sparc (and thus 16 * hopefully other big-endian) devices now work, thanks to a lot of 17 * testing work by Ron Murray. I have no access to CVision hardware, 18 * and therefore for now I am omitting the CVision code. 19 * 20 * Multiple boards support has been on the TODO list for ages. 21 * Don't expect this to change. 22 * 23 * This file is subject to the terms and conditions of the GNU General Public 24 * License. See the file COPYING in the main directory of this archive for 25 * more details. 26 * 27 * 28 */ 29 30 #include <linux/module.h> 31 #include <linux/moduleparam.h> 32 #include <linux/kernel.h> 33 #include <linux/errno.h> 34 #include <linux/string.h> 35 #include <linux/mm.h> 36 #include <linux/slab.h> 37 #include <linux/delay.h> 38 #include <linux/fb.h> 39 #include <linux/init.h> 40 #include <linux/pci.h> 41 #include <video/permedia2.h> 42 #include <video/cvisionppc.h> 43 44 #if !defined(__LITTLE_ENDIAN) && !defined(__BIG_ENDIAN) 45 #error "The endianness of the target host has not been defined." 46 #endif 47 48 #if !defined(CONFIG_PCI) 49 #error "Only generic PCI cards supported." 50 #endif 51 52 #undef PM2FB_MASTER_DEBUG 53 #ifdef PM2FB_MASTER_DEBUG 54 #define DPRINTK(a, b...) \ 55 printk(KERN_DEBUG "pm2fb: %s: " a, __func__ , ## b) 56 #else 57 #define DPRINTK(a, b...) no_printk(a, ##b) 58 #endif 59 60 #define PM2_PIXMAP_SIZE (1600 * 4) 61 62 /* 63 * Driver data 64 */ 65 static int hwcursor = 1; 66 static char *mode_option; 67 68 /* 69 * The XFree GLINT driver will (I think to implement hardware cursor 70 * support on TVP4010 and similar where there is no RAMDAC - see 71 * comment in set_video) always request +ve sync regardless of what 72 * the mode requires. This screws me because I have a Sun 73 * fixed-frequency monitor which absolutely has to have -ve sync. So 74 * these flags allow the user to specify that requests for +ve sync 75 * should be silently turned in -ve sync. 76 */ 77 static bool lowhsync; 78 static bool lowvsync; 79 static bool noaccel; 80 static bool nomtrr; 81 82 /* 83 * The hardware state of the graphics card that isn't part of the 84 * screeninfo. 85 */ 86 struct pm2fb_par 87 { 88 pm2type_t type; /* Board type */ 89 unsigned char __iomem *v_regs;/* virtual address of p_regs */ 90 u32 memclock; /* memclock */ 91 u32 video; /* video flags before blanking */ 92 u32 mem_config; /* MemConfig reg at probe */ 93 u32 mem_control; /* MemControl reg at probe */ 94 u32 boot_address; /* BootAddress reg at probe */ 95 u32 palette[16]; 96 int wc_cookie; 97 }; 98 99 /* 100 * Here we define the default structs fb_fix_screeninfo and fb_var_screeninfo 101 * if we don't use modedb. 102 */ 103 static struct fb_fix_screeninfo pm2fb_fix = { 104 .id = "", 105 .type = FB_TYPE_PACKED_PIXELS, 106 .visual = FB_VISUAL_PSEUDOCOLOR, 107 .xpanstep = 1, 108 .ypanstep = 1, 109 .ywrapstep = 0, 110 .accel = FB_ACCEL_3DLABS_PERMEDIA2, 111 }; 112 113 /* 114 * Default video mode. In case the modedb doesn't work. 115 */ 116 static const struct fb_var_screeninfo pm2fb_var = { 117 /* "640x480, 8 bpp @ 60 Hz */ 118 .xres = 640, 119 .yres = 480, 120 .xres_virtual = 640, 121 .yres_virtual = 480, 122 .bits_per_pixel = 8, 123 .red = {0, 8, 0}, 124 .blue = {0, 8, 0}, 125 .green = {0, 8, 0}, 126 .activate = FB_ACTIVATE_NOW, 127 .height = -1, 128 .width = -1, 129 .accel_flags = 0, 130 .pixclock = 39721, 131 .left_margin = 40, 132 .right_margin = 24, 133 .upper_margin = 32, 134 .lower_margin = 11, 135 .hsync_len = 96, 136 .vsync_len = 2, 137 .vmode = FB_VMODE_NONINTERLACED 138 }; 139 140 /* 141 * Utility functions 142 */ 143 144 static inline u32 pm2_RD(struct pm2fb_par *p, s32 off) 145 { 146 return fb_readl(p->v_regs + off); 147 } 148 149 static inline void pm2_WR(struct pm2fb_par *p, s32 off, u32 v) 150 { 151 fb_writel(v, p->v_regs + off); 152 } 153 154 static inline u32 pm2_RDAC_RD(struct pm2fb_par *p, s32 idx) 155 { 156 pm2_WR(p, PM2R_RD_PALETTE_WRITE_ADDRESS, idx); 157 mb(); 158 return pm2_RD(p, PM2R_RD_INDEXED_DATA); 159 } 160 161 static inline u32 pm2v_RDAC_RD(struct pm2fb_par *p, s32 idx) 162 { 163 pm2_WR(p, PM2VR_RD_INDEX_LOW, idx & 0xff); 164 mb(); 165 return pm2_RD(p, PM2VR_RD_INDEXED_DATA); 166 } 167 168 static inline void pm2_RDAC_WR(struct pm2fb_par *p, s32 idx, u32 v) 169 { 170 pm2_WR(p, PM2R_RD_PALETTE_WRITE_ADDRESS, idx); 171 wmb(); 172 pm2_WR(p, PM2R_RD_INDEXED_DATA, v); 173 wmb(); 174 } 175 176 static inline void pm2v_RDAC_WR(struct pm2fb_par *p, s32 idx, u32 v) 177 { 178 pm2_WR(p, PM2VR_RD_INDEX_LOW, idx & 0xff); 179 wmb(); 180 pm2_WR(p, PM2VR_RD_INDEXED_DATA, v); 181 wmb(); 182 } 183 184 #ifdef CONFIG_FB_PM2_FIFO_DISCONNECT 185 #define WAIT_FIFO(p, a) 186 #else 187 static inline void WAIT_FIFO(struct pm2fb_par *p, u32 a) 188 { 189 while (pm2_RD(p, PM2R_IN_FIFO_SPACE) < a) 190 cpu_relax(); 191 } 192 #endif 193 194 /* 195 * partial products for the supported horizontal resolutions. 196 */ 197 #define PACKPP(p0, p1, p2) (((p2) << 6) | ((p1) << 3) | (p0)) 198 static const struct { 199 u16 width; 200 u16 pp; 201 } pp_table[] = { 202 { 32, PACKPP(1, 0, 0) }, { 64, PACKPP(1, 1, 0) }, 203 { 96, PACKPP(1, 1, 1) }, { 128, PACKPP(2, 1, 1) }, 204 { 160, PACKPP(2, 2, 1) }, { 192, PACKPP(2, 2, 2) }, 205 { 224, PACKPP(3, 2, 1) }, { 256, PACKPP(3, 2, 2) }, 206 { 288, PACKPP(3, 3, 1) }, { 320, PACKPP(3, 3, 2) }, 207 { 384, PACKPP(3, 3, 3) }, { 416, PACKPP(4, 3, 1) }, 208 { 448, PACKPP(4, 3, 2) }, { 512, PACKPP(4, 3, 3) }, 209 { 544, PACKPP(4, 4, 1) }, { 576, PACKPP(4, 4, 2) }, 210 { 640, PACKPP(4, 4, 3) }, { 768, PACKPP(4, 4, 4) }, 211 { 800, PACKPP(5, 4, 1) }, { 832, PACKPP(5, 4, 2) }, 212 { 896, PACKPP(5, 4, 3) }, { 1024, PACKPP(5, 4, 4) }, 213 { 1056, PACKPP(5, 5, 1) }, { 1088, PACKPP(5, 5, 2) }, 214 { 1152, PACKPP(5, 5, 3) }, { 1280, PACKPP(5, 5, 4) }, 215 { 1536, PACKPP(5, 5, 5) }, { 1568, PACKPP(6, 5, 1) }, 216 { 1600, PACKPP(6, 5, 2) }, { 1664, PACKPP(6, 5, 3) }, 217 { 1792, PACKPP(6, 5, 4) }, { 2048, PACKPP(6, 5, 5) }, 218 { 0, 0 } }; 219 220 static u32 partprod(u32 xres) 221 { 222 int i; 223 224 for (i = 0; pp_table[i].width && pp_table[i].width != xres; i++) 225 ; 226 if (pp_table[i].width == 0) 227 DPRINTK("invalid width %u\n", xres); 228 return pp_table[i].pp; 229 } 230 231 static u32 to3264(u32 timing, int bpp, int is64) 232 { 233 switch (bpp) { 234 case 24: 235 timing *= 3; 236 fallthrough; 237 case 8: 238 timing >>= 1; 239 fallthrough; 240 case 16: 241 timing >>= 1; 242 fallthrough; 243 case 32: 244 break; 245 } 246 if (is64) 247 timing >>= 1; 248 return timing; 249 } 250 251 static void pm2_mnp(u32 clk, unsigned char *mm, unsigned char *nn, 252 unsigned char *pp) 253 { 254 unsigned char m; 255 unsigned char n; 256 unsigned char p; 257 u32 f; 258 s32 curr; 259 s32 delta = 100000; 260 261 *mm = *nn = *pp = 0; 262 for (n = 2; n < 15; n++) { 263 for (m = 2; m; m++) { 264 f = PM2_REFERENCE_CLOCK * m / n; 265 if (f >= 150000 && f <= 300000) { 266 for (p = 0; p < 5; p++, f >>= 1) { 267 curr = (clk > f) ? clk - f : f - clk; 268 if (curr < delta) { 269 delta = curr; 270 *mm = m; 271 *nn = n; 272 *pp = p; 273 } 274 } 275 } 276 } 277 } 278 } 279 280 static void pm2v_mnp(u32 clk, unsigned char *mm, unsigned char *nn, 281 unsigned char *pp) 282 { 283 unsigned char m; 284 unsigned char n; 285 unsigned char p; 286 u32 f; 287 s32 delta = 1000; 288 289 *mm = *nn = *pp = 0; 290 for (m = 1; m < 128; m++) { 291 for (n = 2 * m + 1; n; n++) { 292 for (p = 0; p < 2; p++) { 293 f = (PM2_REFERENCE_CLOCK >> (p + 1)) * n / m; 294 if (clk > f - delta && clk < f + delta) { 295 delta = (clk > f) ? clk - f : f - clk; 296 *mm = m; 297 *nn = n; 298 *pp = p; 299 } 300 } 301 } 302 } 303 } 304 305 static void clear_palette(struct pm2fb_par *p) 306 { 307 int i = 256; 308 309 WAIT_FIFO(p, 1); 310 pm2_WR(p, PM2R_RD_PALETTE_WRITE_ADDRESS, 0); 311 wmb(); 312 while (i--) { 313 WAIT_FIFO(p, 3); 314 pm2_WR(p, PM2R_RD_PALETTE_DATA, 0); 315 pm2_WR(p, PM2R_RD_PALETTE_DATA, 0); 316 pm2_WR(p, PM2R_RD_PALETTE_DATA, 0); 317 } 318 } 319 320 static void reset_card(struct pm2fb_par *p) 321 { 322 if (p->type == PM2_TYPE_PERMEDIA2V) 323 pm2_WR(p, PM2VR_RD_INDEX_HIGH, 0); 324 pm2_WR(p, PM2R_RESET_STATUS, 0); 325 mb(); 326 while (pm2_RD(p, PM2R_RESET_STATUS) & PM2F_BEING_RESET) 327 cpu_relax(); 328 mb(); 329 #ifdef CONFIG_FB_PM2_FIFO_DISCONNECT 330 DPRINTK("FIFO disconnect enabled\n"); 331 pm2_WR(p, PM2R_FIFO_DISCON, 1); 332 mb(); 333 #endif 334 335 /* Restore stashed memory config information from probe */ 336 WAIT_FIFO(p, 3); 337 pm2_WR(p, PM2R_MEM_CONTROL, p->mem_control); 338 pm2_WR(p, PM2R_BOOT_ADDRESS, p->boot_address); 339 wmb(); 340 pm2_WR(p, PM2R_MEM_CONFIG, p->mem_config); 341 } 342 343 static void reset_config(struct pm2fb_par *p) 344 { 345 WAIT_FIFO(p, 53); 346 pm2_WR(p, PM2R_CHIP_CONFIG, pm2_RD(p, PM2R_CHIP_CONFIG) & 347 ~(PM2F_VGA_ENABLE | PM2F_VGA_FIXED)); 348 pm2_WR(p, PM2R_BYPASS_WRITE_MASK, ~(0L)); 349 pm2_WR(p, PM2R_FRAMEBUFFER_WRITE_MASK, ~(0L)); 350 pm2_WR(p, PM2R_FIFO_CONTROL, 0); 351 pm2_WR(p, PM2R_APERTURE_ONE, 0); 352 pm2_WR(p, PM2R_APERTURE_TWO, 0); 353 pm2_WR(p, PM2R_RASTERIZER_MODE, 0); 354 pm2_WR(p, PM2R_DELTA_MODE, PM2F_DELTA_ORDER_RGB); 355 pm2_WR(p, PM2R_LB_READ_FORMAT, 0); 356 pm2_WR(p, PM2R_LB_WRITE_FORMAT, 0); 357 pm2_WR(p, PM2R_LB_READ_MODE, 0); 358 pm2_WR(p, PM2R_LB_SOURCE_OFFSET, 0); 359 pm2_WR(p, PM2R_FB_SOURCE_OFFSET, 0); 360 pm2_WR(p, PM2R_FB_PIXEL_OFFSET, 0); 361 pm2_WR(p, PM2R_FB_WINDOW_BASE, 0); 362 pm2_WR(p, PM2R_LB_WINDOW_BASE, 0); 363 pm2_WR(p, PM2R_FB_SOFT_WRITE_MASK, ~(0L)); 364 pm2_WR(p, PM2R_FB_HARD_WRITE_MASK, ~(0L)); 365 pm2_WR(p, PM2R_FB_READ_PIXEL, 0); 366 pm2_WR(p, PM2R_DITHER_MODE, 0); 367 pm2_WR(p, PM2R_AREA_STIPPLE_MODE, 0); 368 pm2_WR(p, PM2R_DEPTH_MODE, 0); 369 pm2_WR(p, PM2R_STENCIL_MODE, 0); 370 pm2_WR(p, PM2R_TEXTURE_ADDRESS_MODE, 0); 371 pm2_WR(p, PM2R_TEXTURE_READ_MODE, 0); 372 pm2_WR(p, PM2R_TEXEL_LUT_MODE, 0); 373 pm2_WR(p, PM2R_YUV_MODE, 0); 374 pm2_WR(p, PM2R_COLOR_DDA_MODE, 0); 375 pm2_WR(p, PM2R_TEXTURE_COLOR_MODE, 0); 376 pm2_WR(p, PM2R_FOG_MODE, 0); 377 pm2_WR(p, PM2R_ALPHA_BLEND_MODE, 0); 378 pm2_WR(p, PM2R_LOGICAL_OP_MODE, 0); 379 pm2_WR(p, PM2R_STATISTICS_MODE, 0); 380 pm2_WR(p, PM2R_SCISSOR_MODE, 0); 381 pm2_WR(p, PM2R_FILTER_MODE, PM2F_SYNCHRONIZATION); 382 pm2_WR(p, PM2R_RD_PIXEL_MASK, 0xff); 383 switch (p->type) { 384 case PM2_TYPE_PERMEDIA2: 385 pm2_RDAC_WR(p, PM2I_RD_MODE_CONTROL, 0); /* no overlay */ 386 pm2_RDAC_WR(p, PM2I_RD_CURSOR_CONTROL, 0); 387 pm2_RDAC_WR(p, PM2I_RD_MISC_CONTROL, PM2F_RD_PALETTE_WIDTH_8); 388 pm2_RDAC_WR(p, PM2I_RD_COLOR_KEY_CONTROL, 0); 389 pm2_RDAC_WR(p, PM2I_RD_OVERLAY_KEY, 0); 390 pm2_RDAC_WR(p, PM2I_RD_RED_KEY, 0); 391 pm2_RDAC_WR(p, PM2I_RD_GREEN_KEY, 0); 392 pm2_RDAC_WR(p, PM2I_RD_BLUE_KEY, 0); 393 break; 394 case PM2_TYPE_PERMEDIA2V: 395 pm2v_RDAC_WR(p, PM2VI_RD_MISC_CONTROL, 1); /* 8bit */ 396 break; 397 } 398 } 399 400 static void set_aperture(struct pm2fb_par *p, u32 depth) 401 { 402 /* 403 * The hardware is little-endian. When used in big-endian 404 * hosts, the on-chip aperture settings are used where 405 * possible to translate from host to card byte order. 406 */ 407 WAIT_FIFO(p, 2); 408 #ifdef __LITTLE_ENDIAN 409 pm2_WR(p, PM2R_APERTURE_ONE, PM2F_APERTURE_STANDARD); 410 #else 411 switch (depth) { 412 case 24: /* RGB->BGR */ 413 /* 414 * We can't use the aperture to translate host to 415 * card byte order here, so we switch to BGR mode 416 * in pm2fb_set_par(). 417 */ 418 case 8: /* B->B */ 419 pm2_WR(p, PM2R_APERTURE_ONE, PM2F_APERTURE_STANDARD); 420 break; 421 case 16: /* HL->LH */ 422 pm2_WR(p, PM2R_APERTURE_ONE, PM2F_APERTURE_HALFWORDSWAP); 423 break; 424 case 32: /* RGBA->ABGR */ 425 pm2_WR(p, PM2R_APERTURE_ONE, PM2F_APERTURE_BYTESWAP); 426 break; 427 } 428 #endif 429 430 /* We don't use aperture two, so this may be superflous */ 431 pm2_WR(p, PM2R_APERTURE_TWO, PM2F_APERTURE_STANDARD); 432 } 433 434 static void set_color(struct pm2fb_par *p, unsigned char regno, 435 unsigned char r, unsigned char g, unsigned char b) 436 { 437 WAIT_FIFO(p, 4); 438 pm2_WR(p, PM2R_RD_PALETTE_WRITE_ADDRESS, regno); 439 wmb(); 440 pm2_WR(p, PM2R_RD_PALETTE_DATA, r); 441 wmb(); 442 pm2_WR(p, PM2R_RD_PALETTE_DATA, g); 443 wmb(); 444 pm2_WR(p, PM2R_RD_PALETTE_DATA, b); 445 } 446 447 static void set_memclock(struct pm2fb_par *par, u32 clk) 448 { 449 int i; 450 unsigned char m, n, p; 451 452 switch (par->type) { 453 case PM2_TYPE_PERMEDIA2V: 454 pm2v_mnp(clk/2, &m, &n, &p); 455 WAIT_FIFO(par, 12); 456 pm2_WR(par, PM2VR_RD_INDEX_HIGH, PM2VI_RD_MCLK_CONTROL >> 8); 457 pm2v_RDAC_WR(par, PM2VI_RD_MCLK_CONTROL, 0); 458 pm2v_RDAC_WR(par, PM2VI_RD_MCLK_PRESCALE, m); 459 pm2v_RDAC_WR(par, PM2VI_RD_MCLK_FEEDBACK, n); 460 pm2v_RDAC_WR(par, PM2VI_RD_MCLK_POSTSCALE, p); 461 pm2v_RDAC_WR(par, PM2VI_RD_MCLK_CONTROL, 1); 462 rmb(); 463 for (i = 256; i; i--) 464 if (pm2v_RDAC_RD(par, PM2VI_RD_MCLK_CONTROL) & 2) 465 break; 466 pm2_WR(par, PM2VR_RD_INDEX_HIGH, 0); 467 break; 468 case PM2_TYPE_PERMEDIA2: 469 pm2_mnp(clk, &m, &n, &p); 470 WAIT_FIFO(par, 10); 471 pm2_RDAC_WR(par, PM2I_RD_MEMORY_CLOCK_3, 6); 472 pm2_RDAC_WR(par, PM2I_RD_MEMORY_CLOCK_1, m); 473 pm2_RDAC_WR(par, PM2I_RD_MEMORY_CLOCK_2, n); 474 pm2_RDAC_WR(par, PM2I_RD_MEMORY_CLOCK_3, 8|p); 475 pm2_RDAC_RD(par, PM2I_RD_MEMORY_CLOCK_STATUS); 476 rmb(); 477 for (i = 256; i; i--) 478 if (pm2_RD(par, PM2R_RD_INDEXED_DATA) & PM2F_PLL_LOCKED) 479 break; 480 break; 481 } 482 } 483 484 static void set_pixclock(struct pm2fb_par *par, u32 clk) 485 { 486 int i; 487 unsigned char m, n, p; 488 489 switch (par->type) { 490 case PM2_TYPE_PERMEDIA2: 491 pm2_mnp(clk, &m, &n, &p); 492 WAIT_FIFO(par, 10); 493 pm2_RDAC_WR(par, PM2I_RD_PIXEL_CLOCK_A3, 0); 494 pm2_RDAC_WR(par, PM2I_RD_PIXEL_CLOCK_A1, m); 495 pm2_RDAC_WR(par, PM2I_RD_PIXEL_CLOCK_A2, n); 496 pm2_RDAC_WR(par, PM2I_RD_PIXEL_CLOCK_A3, 8|p); 497 pm2_RDAC_RD(par, PM2I_RD_PIXEL_CLOCK_STATUS); 498 rmb(); 499 for (i = 256; i; i--) 500 if (pm2_RD(par, PM2R_RD_INDEXED_DATA) & PM2F_PLL_LOCKED) 501 break; 502 break; 503 case PM2_TYPE_PERMEDIA2V: 504 pm2v_mnp(clk/2, &m, &n, &p); 505 WAIT_FIFO(par, 8); 506 pm2_WR(par, PM2VR_RD_INDEX_HIGH, PM2VI_RD_CLK0_PRESCALE >> 8); 507 pm2v_RDAC_WR(par, PM2VI_RD_CLK0_PRESCALE, m); 508 pm2v_RDAC_WR(par, PM2VI_RD_CLK0_FEEDBACK, n); 509 pm2v_RDAC_WR(par, PM2VI_RD_CLK0_POSTSCALE, p); 510 pm2_WR(par, PM2VR_RD_INDEX_HIGH, 0); 511 break; 512 } 513 } 514 515 static void set_video(struct pm2fb_par *p, u32 video) 516 { 517 u32 tmp; 518 u32 vsync = video; 519 520 DPRINTK("video = 0x%x\n", video); 521 522 /* 523 * The hardware cursor needs +vsync to recognise vert retrace. 524 * We may not be using the hardware cursor, but the X Glint 525 * driver may well. So always set +hsync/+vsync and then set 526 * the RAMDAC to invert the sync if necessary. 527 */ 528 vsync &= ~(PM2F_HSYNC_MASK | PM2F_VSYNC_MASK); 529 vsync |= PM2F_HSYNC_ACT_HIGH | PM2F_VSYNC_ACT_HIGH; 530 531 WAIT_FIFO(p, 3); 532 pm2_WR(p, PM2R_VIDEO_CONTROL, vsync); 533 534 switch (p->type) { 535 case PM2_TYPE_PERMEDIA2: 536 tmp = PM2F_RD_PALETTE_WIDTH_8; 537 if ((video & PM2F_HSYNC_MASK) == PM2F_HSYNC_ACT_LOW) 538 tmp |= 4; /* invert hsync */ 539 if ((video & PM2F_VSYNC_MASK) == PM2F_VSYNC_ACT_LOW) 540 tmp |= 8; /* invert vsync */ 541 pm2_RDAC_WR(p, PM2I_RD_MISC_CONTROL, tmp); 542 break; 543 case PM2_TYPE_PERMEDIA2V: 544 tmp = 0; 545 if ((video & PM2F_HSYNC_MASK) == PM2F_HSYNC_ACT_LOW) 546 tmp |= 1; /* invert hsync */ 547 if ((video & PM2F_VSYNC_MASK) == PM2F_VSYNC_ACT_LOW) 548 tmp |= 4; /* invert vsync */ 549 pm2v_RDAC_WR(p, PM2VI_RD_SYNC_CONTROL, tmp); 550 break; 551 } 552 } 553 554 /* 555 * pm2fb_check_var - Optional function. Validates a var passed in. 556 * @var: frame buffer variable screen structure 557 * @info: frame buffer structure that represents a single frame buffer 558 * 559 * Checks to see if the hardware supports the state requested by 560 * var passed in. 561 * 562 * Returns negative errno on error, or zero on success. 563 */ 564 static int pm2fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) 565 { 566 u32 lpitch; 567 568 if (var->bits_per_pixel != 8 && var->bits_per_pixel != 16 && 569 var->bits_per_pixel != 24 && var->bits_per_pixel != 32) { 570 DPRINTK("depth not supported: %u\n", var->bits_per_pixel); 571 return -EINVAL; 572 } 573 574 if (var->xres != var->xres_virtual) { 575 DPRINTK("virtual x resolution != " 576 "physical x resolution not supported\n"); 577 return -EINVAL; 578 } 579 580 if (var->yres > var->yres_virtual) { 581 DPRINTK("virtual y resolution < " 582 "physical y resolution not possible\n"); 583 return -EINVAL; 584 } 585 586 /* permedia cannot blit over 2048 */ 587 if (var->yres_virtual > 2047) { 588 var->yres_virtual = 2047; 589 } 590 591 if (var->xoffset) { 592 DPRINTK("xoffset not supported\n"); 593 return -EINVAL; 594 } 595 596 if ((var->vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) { 597 DPRINTK("interlace not supported\n"); 598 return -EINVAL; 599 } 600 601 var->xres = (var->xres + 15) & ~15; /* could sometimes be 8 */ 602 lpitch = var->xres * ((var->bits_per_pixel + 7) >> 3); 603 604 if (var->xres < 320 || var->xres > 1600) { 605 DPRINTK("width not supported: %u\n", var->xres); 606 return -EINVAL; 607 } 608 609 if (var->yres < 200 || var->yres > 1200) { 610 DPRINTK("height not supported: %u\n", var->yres); 611 return -EINVAL; 612 } 613 614 if (lpitch * var->yres_virtual > info->fix.smem_len) { 615 DPRINTK("no memory for screen (%ux%ux%u)\n", 616 var->xres, var->yres_virtual, var->bits_per_pixel); 617 return -EINVAL; 618 } 619 620 if (PICOS2KHZ(var->pixclock) > PM2_MAX_PIXCLOCK) { 621 DPRINTK("pixclock too high (%ldKHz)\n", 622 PICOS2KHZ(var->pixclock)); 623 return -EINVAL; 624 } 625 626 var->transp.offset = 0; 627 var->transp.length = 0; 628 switch (var->bits_per_pixel) { 629 case 8: 630 var->red.length = 8; 631 var->green.length = 8; 632 var->blue.length = 8; 633 break; 634 case 16: 635 var->red.offset = 11; 636 var->red.length = 5; 637 var->green.offset = 5; 638 var->green.length = 6; 639 var->blue.offset = 0; 640 var->blue.length = 5; 641 break; 642 case 32: 643 var->transp.offset = 24; 644 var->transp.length = 8; 645 var->red.offset = 16; 646 var->green.offset = 8; 647 var->blue.offset = 0; 648 var->red.length = 8; 649 var->green.length = 8; 650 var->blue.length = 8; 651 break; 652 case 24: 653 #ifdef __BIG_ENDIAN 654 var->red.offset = 0; 655 var->blue.offset = 16; 656 #else 657 var->red.offset = 16; 658 var->blue.offset = 0; 659 #endif 660 var->green.offset = 8; 661 var->red.length = 8; 662 var->green.length = 8; 663 var->blue.length = 8; 664 break; 665 } 666 var->height = -1; 667 var->width = -1; 668 669 var->accel_flags = 0; /* Can't mmap if this is on */ 670 671 DPRINTK("Checking graphics mode at %dx%d depth %d\n", 672 var->xres, var->yres, var->bits_per_pixel); 673 return 0; 674 } 675 676 /** 677 * pm2fb_set_par - Alters the hardware state. 678 * @info: frame buffer structure that represents a single frame buffer 679 * 680 * Using the fb_var_screeninfo in fb_info we set the resolution of the 681 * this particular framebuffer. 682 */ 683 static int pm2fb_set_par(struct fb_info *info) 684 { 685 struct pm2fb_par *par = info->par; 686 u32 pixclock; 687 u32 width = (info->var.xres_virtual + 7) & ~7; 688 u32 height = info->var.yres_virtual; 689 u32 depth = (info->var.bits_per_pixel + 7) & ~7; 690 u32 hsstart, hsend, hbend, htotal; 691 u32 vsstart, vsend, vbend, vtotal; 692 u32 stride; 693 u32 base; 694 u32 video = 0; 695 u32 clrmode = PM2F_RD_COLOR_MODE_RGB | PM2F_RD_GUI_ACTIVE; 696 u32 txtmap = 0; 697 u32 pixsize = 0; 698 u32 clrformat = 0; 699 u32 misc = 1; /* 8-bit DAC */ 700 u32 xres = (info->var.xres + 31) & ~31; 701 int data64; 702 703 reset_card(par); 704 reset_config(par); 705 clear_palette(par); 706 if (par->memclock) 707 set_memclock(par, par->memclock); 708 709 depth = (depth > 32) ? 32 : depth; 710 data64 = depth > 8 || par->type == PM2_TYPE_PERMEDIA2V; 711 712 pixclock = PICOS2KHZ(info->var.pixclock); 713 if (pixclock > PM2_MAX_PIXCLOCK) { 714 DPRINTK("pixclock too high (%uKHz)\n", pixclock); 715 return -EINVAL; 716 } 717 718 hsstart = to3264(info->var.right_margin, depth, data64); 719 hsend = hsstart + to3264(info->var.hsync_len, depth, data64); 720 hbend = hsend + to3264(info->var.left_margin, depth, data64); 721 htotal = to3264(xres, depth, data64) + hbend - 1; 722 vsstart = (info->var.lower_margin) 723 ? info->var.lower_margin - 1 724 : 0; /* FIXME! */ 725 vsend = info->var.lower_margin + info->var.vsync_len - 1; 726 vbend = info->var.lower_margin + info->var.vsync_len + 727 info->var.upper_margin; 728 vtotal = info->var.yres + vbend - 1; 729 stride = to3264(width, depth, 1); 730 base = to3264(info->var.yoffset * xres + info->var.xoffset, depth, 1); 731 if (data64) 732 video |= PM2F_DATA_64_ENABLE; 733 734 if (info->var.sync & FB_SYNC_HOR_HIGH_ACT) { 735 if (lowhsync) { 736 DPRINTK("ignoring +hsync, using -hsync.\n"); 737 video |= PM2F_HSYNC_ACT_LOW; 738 } else 739 video |= PM2F_HSYNC_ACT_HIGH; 740 } else 741 video |= PM2F_HSYNC_ACT_LOW; 742 743 if (info->var.sync & FB_SYNC_VERT_HIGH_ACT) { 744 if (lowvsync) { 745 DPRINTK("ignoring +vsync, using -vsync.\n"); 746 video |= PM2F_VSYNC_ACT_LOW; 747 } else 748 video |= PM2F_VSYNC_ACT_HIGH; 749 } else 750 video |= PM2F_VSYNC_ACT_LOW; 751 752 if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) { 753 DPRINTK("interlaced not supported\n"); 754 return -EINVAL; 755 } 756 if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_DOUBLE) 757 video |= PM2F_LINE_DOUBLE; 758 if ((info->var.activate & FB_ACTIVATE_MASK) == FB_ACTIVATE_NOW) 759 video |= PM2F_VIDEO_ENABLE; 760 par->video = video; 761 762 info->fix.visual = 763 (depth == 8) ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR; 764 info->fix.line_length = info->var.xres * depth / 8; 765 info->cmap.len = 256; 766 767 /* 768 * Settings calculated. Now write them out. 769 */ 770 if (par->type == PM2_TYPE_PERMEDIA2V) { 771 WAIT_FIFO(par, 1); 772 pm2_WR(par, PM2VR_RD_INDEX_HIGH, 0); 773 } 774 775 set_aperture(par, depth); 776 777 mb(); 778 WAIT_FIFO(par, 19); 779 switch (depth) { 780 case 8: 781 pm2_WR(par, PM2R_FB_READ_PIXEL, 0); 782 clrformat = 0x2e; 783 break; 784 case 16: 785 pm2_WR(par, PM2R_FB_READ_PIXEL, 1); 786 clrmode |= PM2F_RD_TRUECOLOR | PM2F_RD_PIXELFORMAT_RGB565; 787 txtmap = PM2F_TEXTEL_SIZE_16; 788 pixsize = 1; 789 clrformat = 0x70; 790 misc |= 8; 791 break; 792 case 32: 793 pm2_WR(par, PM2R_FB_READ_PIXEL, 2); 794 clrmode |= PM2F_RD_TRUECOLOR | PM2F_RD_PIXELFORMAT_RGBA8888; 795 txtmap = PM2F_TEXTEL_SIZE_32; 796 pixsize = 2; 797 clrformat = 0x20; 798 misc |= 8; 799 break; 800 case 24: 801 pm2_WR(par, PM2R_FB_READ_PIXEL, 4); 802 clrmode |= PM2F_RD_TRUECOLOR | PM2F_RD_PIXELFORMAT_RGB888; 803 txtmap = PM2F_TEXTEL_SIZE_24; 804 pixsize = 4; 805 clrformat = 0x20; 806 misc |= 8; 807 break; 808 } 809 pm2_WR(par, PM2R_FB_WRITE_MODE, PM2F_FB_WRITE_ENABLE); 810 pm2_WR(par, PM2R_FB_READ_MODE, partprod(xres)); 811 pm2_WR(par, PM2R_LB_READ_MODE, partprod(xres)); 812 pm2_WR(par, PM2R_TEXTURE_MAP_FORMAT, txtmap | partprod(xres)); 813 pm2_WR(par, PM2R_H_TOTAL, htotal); 814 pm2_WR(par, PM2R_HS_START, hsstart); 815 pm2_WR(par, PM2R_HS_END, hsend); 816 pm2_WR(par, PM2R_HG_END, hbend); 817 pm2_WR(par, PM2R_HB_END, hbend); 818 pm2_WR(par, PM2R_V_TOTAL, vtotal); 819 pm2_WR(par, PM2R_VS_START, vsstart); 820 pm2_WR(par, PM2R_VS_END, vsend); 821 pm2_WR(par, PM2R_VB_END, vbend); 822 pm2_WR(par, PM2R_SCREEN_STRIDE, stride); 823 wmb(); 824 pm2_WR(par, PM2R_WINDOW_ORIGIN, 0); 825 pm2_WR(par, PM2R_SCREEN_SIZE, (height << 16) | width); 826 pm2_WR(par, PM2R_SCISSOR_MODE, PM2F_SCREEN_SCISSOR_ENABLE); 827 wmb(); 828 pm2_WR(par, PM2R_SCREEN_BASE, base); 829 wmb(); 830 set_video(par, video); 831 WAIT_FIFO(par, 10); 832 switch (par->type) { 833 case PM2_TYPE_PERMEDIA2: 834 pm2_RDAC_WR(par, PM2I_RD_COLOR_MODE, clrmode); 835 pm2_RDAC_WR(par, PM2I_RD_COLOR_KEY_CONTROL, 836 (depth == 8) ? 0 : PM2F_COLOR_KEY_TEST_OFF); 837 break; 838 case PM2_TYPE_PERMEDIA2V: 839 pm2v_RDAC_WR(par, PM2VI_RD_DAC_CONTROL, 0); 840 pm2v_RDAC_WR(par, PM2VI_RD_PIXEL_SIZE, pixsize); 841 pm2v_RDAC_WR(par, PM2VI_RD_COLOR_FORMAT, clrformat); 842 pm2v_RDAC_WR(par, PM2VI_RD_MISC_CONTROL, misc); 843 pm2v_RDAC_WR(par, PM2VI_RD_OVERLAY_KEY, 0); 844 break; 845 } 846 set_pixclock(par, pixclock); 847 DPRINTK("Setting graphics mode at %dx%d depth %d\n", 848 info->var.xres, info->var.yres, info->var.bits_per_pixel); 849 return 0; 850 } 851 852 /** 853 * pm2fb_setcolreg - Sets a color register. 854 * @regno: boolean, 0 copy local, 1 get_user() function 855 * @red: frame buffer colormap structure 856 * @green: The green value which can be up to 16 bits wide 857 * @blue: The blue value which can be up to 16 bits wide. 858 * @transp: If supported the alpha value which can be up to 16 bits wide. 859 * @info: frame buffer info structure 860 * 861 * Set a single color register. The values supplied have a 16 bit 862 * magnitude which needs to be scaled in this function for the hardware. 863 * Pretty much a direct lift from tdfxfb.c. 864 * 865 * Returns negative errno on error, or zero on success. 866 */ 867 static int pm2fb_setcolreg(unsigned regno, unsigned red, unsigned green, 868 unsigned blue, unsigned transp, 869 struct fb_info *info) 870 { 871 struct pm2fb_par *par = info->par; 872 873 if (regno >= info->cmap.len) /* no. of hw registers */ 874 return -EINVAL; 875 /* 876 * Program hardware... do anything you want with transp 877 */ 878 879 /* grayscale works only partially under directcolor */ 880 /* grayscale = 0.30*R + 0.59*G + 0.11*B */ 881 if (info->var.grayscale) 882 red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8; 883 884 /* Directcolor: 885 * var->{color}.offset contains start of bitfield 886 * var->{color}.length contains length of bitfield 887 * {hardwarespecific} contains width of DAC 888 * cmap[X] is programmed to 889 * (X << red.offset) | (X << green.offset) | (X << blue.offset) 890 * RAMDAC[X] is programmed to (red, green, blue) 891 * 892 * Pseudocolor: 893 * uses offset = 0 && length = DAC register width. 894 * var->{color}.offset is 0 895 * var->{color}.length contains width of DAC 896 * cmap is not used 897 * DAC[X] is programmed to (red, green, blue) 898 * Truecolor: 899 * does not use RAMDAC (usually has 3 of them). 900 * var->{color}.offset contains start of bitfield 901 * var->{color}.length contains length of bitfield 902 * cmap is programmed to 903 * (red << red.offset) | (green << green.offset) | 904 * (blue << blue.offset) | (transp << transp.offset) 905 * RAMDAC does not exist 906 */ 907 #define CNVT_TOHW(val, width) ((((val) << (width)) + 0x7FFF -(val)) >> 16) 908 switch (info->fix.visual) { 909 case FB_VISUAL_TRUECOLOR: 910 case FB_VISUAL_PSEUDOCOLOR: 911 red = CNVT_TOHW(red, info->var.red.length); 912 green = CNVT_TOHW(green, info->var.green.length); 913 blue = CNVT_TOHW(blue, info->var.blue.length); 914 transp = CNVT_TOHW(transp, info->var.transp.length); 915 break; 916 case FB_VISUAL_DIRECTCOLOR: 917 /* example here assumes 8 bit DAC. Might be different 918 * for your hardware */ 919 red = CNVT_TOHW(red, 8); 920 green = CNVT_TOHW(green, 8); 921 blue = CNVT_TOHW(blue, 8); 922 /* hey, there is bug in transp handling... */ 923 transp = CNVT_TOHW(transp, 8); 924 break; 925 } 926 #undef CNVT_TOHW 927 /* Truecolor has hardware independent palette */ 928 if (info->fix.visual == FB_VISUAL_TRUECOLOR) { 929 u32 v; 930 931 if (regno >= 16) 932 return -EINVAL; 933 934 v = (red << info->var.red.offset) | 935 (green << info->var.green.offset) | 936 (blue << info->var.blue.offset) | 937 (transp << info->var.transp.offset); 938 939 switch (info->var.bits_per_pixel) { 940 case 8: 941 break; 942 case 16: 943 case 24: 944 case 32: 945 par->palette[regno] = v; 946 break; 947 } 948 return 0; 949 } else if (info->fix.visual == FB_VISUAL_PSEUDOCOLOR) 950 set_color(par, regno, red, green, blue); 951 952 return 0; 953 } 954 955 /** 956 * pm2fb_pan_display - Pans the display. 957 * @var: frame buffer variable screen structure 958 * @info: frame buffer structure that represents a single frame buffer 959 * 960 * Pan (or wrap, depending on the `vmode' field) the display using the 961 * `xoffset' and `yoffset' fields of the `var' structure. 962 * If the values don't fit, return -EINVAL. 963 * 964 * Returns negative errno on error, or zero on success. 965 * 966 */ 967 static int pm2fb_pan_display(struct fb_var_screeninfo *var, 968 struct fb_info *info) 969 { 970 struct pm2fb_par *p = info->par; 971 u32 base; 972 u32 depth = (info->var.bits_per_pixel + 7) & ~7; 973 u32 xres = (info->var.xres + 31) & ~31; 974 975 depth = (depth > 32) ? 32 : depth; 976 base = to3264(var->yoffset * xres + var->xoffset, depth, 1); 977 WAIT_FIFO(p, 1); 978 pm2_WR(p, PM2R_SCREEN_BASE, base); 979 return 0; 980 } 981 982 /** 983 * pm2fb_blank - Blanks the display. 984 * @blank_mode: the blank mode we want. 985 * @info: frame buffer structure that represents a single frame buffer 986 * 987 * Blank the screen if blank_mode != 0, else unblank. Return 0 if 988 * blanking succeeded, != 0 if un-/blanking failed due to e.g. a 989 * video mode which doesn't support it. Implements VESA suspend 990 * and powerdown modes on hardware that supports disabling hsync/vsync: 991 * blank_mode == 2: suspend vsync 992 * blank_mode == 3: suspend hsync 993 * blank_mode == 4: powerdown 994 * 995 * Returns negative errno on error, or zero on success. 996 * 997 */ 998 static int pm2fb_blank(int blank_mode, struct fb_info *info) 999 { 1000 struct pm2fb_par *par = info->par; 1001 u32 video = par->video; 1002 1003 DPRINTK("blank_mode %d\n", blank_mode); 1004 1005 switch (blank_mode) { 1006 case FB_BLANK_UNBLANK: 1007 /* Screen: On */ 1008 video |= PM2F_VIDEO_ENABLE; 1009 break; 1010 case FB_BLANK_NORMAL: 1011 /* Screen: Off */ 1012 video &= ~PM2F_VIDEO_ENABLE; 1013 break; 1014 case FB_BLANK_VSYNC_SUSPEND: 1015 /* VSync: Off */ 1016 video &= ~(PM2F_VSYNC_MASK | PM2F_BLANK_LOW); 1017 break; 1018 case FB_BLANK_HSYNC_SUSPEND: 1019 /* HSync: Off */ 1020 video &= ~(PM2F_HSYNC_MASK | PM2F_BLANK_LOW); 1021 break; 1022 case FB_BLANK_POWERDOWN: 1023 /* HSync: Off, VSync: Off */ 1024 video &= ~(PM2F_VSYNC_MASK | PM2F_HSYNC_MASK | PM2F_BLANK_LOW); 1025 break; 1026 } 1027 set_video(par, video); 1028 return 0; 1029 } 1030 1031 static int pm2fb_sync(struct fb_info *info) 1032 { 1033 struct pm2fb_par *par = info->par; 1034 1035 WAIT_FIFO(par, 1); 1036 pm2_WR(par, PM2R_SYNC, 0); 1037 mb(); 1038 do { 1039 while (pm2_RD(par, PM2R_OUT_FIFO_WORDS) == 0) 1040 cpu_relax(); 1041 } while (pm2_RD(par, PM2R_OUT_FIFO) != PM2TAG(PM2R_SYNC)); 1042 1043 return 0; 1044 } 1045 1046 static void pm2fb_fillrect(struct fb_info *info, 1047 const struct fb_fillrect *region) 1048 { 1049 struct pm2fb_par *par = info->par; 1050 struct fb_fillrect modded; 1051 int vxres, vyres; 1052 u32 color = (info->fix.visual == FB_VISUAL_TRUECOLOR) ? 1053 ((u32 *)info->pseudo_palette)[region->color] : region->color; 1054 1055 if (info->state != FBINFO_STATE_RUNNING) 1056 return; 1057 if ((info->flags & FBINFO_HWACCEL_DISABLED) || 1058 region->rop != ROP_COPY ) { 1059 cfb_fillrect(info, region); 1060 return; 1061 } 1062 1063 vxres = info->var.xres_virtual; 1064 vyres = info->var.yres_virtual; 1065 1066 memcpy(&modded, region, sizeof(struct fb_fillrect)); 1067 1068 if (!modded.width || !modded.height || 1069 modded.dx >= vxres || modded.dy >= vyres) 1070 return; 1071 1072 if (modded.dx + modded.width > vxres) 1073 modded.width = vxres - modded.dx; 1074 if (modded.dy + modded.height > vyres) 1075 modded.height = vyres - modded.dy; 1076 1077 if (info->var.bits_per_pixel == 8) 1078 color |= color << 8; 1079 if (info->var.bits_per_pixel <= 16) 1080 color |= color << 16; 1081 1082 WAIT_FIFO(par, 3); 1083 pm2_WR(par, PM2R_CONFIG, PM2F_CONFIG_FB_WRITE_ENABLE); 1084 pm2_WR(par, PM2R_RECTANGLE_ORIGIN, (modded.dy << 16) | modded.dx); 1085 pm2_WR(par, PM2R_RECTANGLE_SIZE, (modded.height << 16) | modded.width); 1086 if (info->var.bits_per_pixel != 24) { 1087 WAIT_FIFO(par, 2); 1088 pm2_WR(par, PM2R_FB_BLOCK_COLOR, color); 1089 wmb(); 1090 pm2_WR(par, PM2R_RENDER, 1091 PM2F_RENDER_RECTANGLE | PM2F_RENDER_FASTFILL); 1092 } else { 1093 WAIT_FIFO(par, 4); 1094 pm2_WR(par, PM2R_COLOR_DDA_MODE, 1); 1095 pm2_WR(par, PM2R_CONSTANT_COLOR, color); 1096 wmb(); 1097 pm2_WR(par, PM2R_RENDER, 1098 PM2F_RENDER_RECTANGLE | 1099 PM2F_INCREASE_X | PM2F_INCREASE_Y ); 1100 pm2_WR(par, PM2R_COLOR_DDA_MODE, 0); 1101 } 1102 } 1103 1104 static void pm2fb_copyarea(struct fb_info *info, 1105 const struct fb_copyarea *area) 1106 { 1107 struct pm2fb_par *par = info->par; 1108 struct fb_copyarea modded; 1109 u32 vxres, vyres; 1110 1111 if (info->state != FBINFO_STATE_RUNNING) 1112 return; 1113 if (info->flags & FBINFO_HWACCEL_DISABLED) { 1114 cfb_copyarea(info, area); 1115 return; 1116 } 1117 1118 memcpy(&modded, area, sizeof(struct fb_copyarea)); 1119 1120 vxres = info->var.xres_virtual; 1121 vyres = info->var.yres_virtual; 1122 1123 if (!modded.width || !modded.height || 1124 modded.sx >= vxres || modded.sy >= vyres || 1125 modded.dx >= vxres || modded.dy >= vyres) 1126 return; 1127 1128 if (modded.sx + modded.width > vxres) 1129 modded.width = vxres - modded.sx; 1130 if (modded.dx + modded.width > vxres) 1131 modded.width = vxres - modded.dx; 1132 if (modded.sy + modded.height > vyres) 1133 modded.height = vyres - modded.sy; 1134 if (modded.dy + modded.height > vyres) 1135 modded.height = vyres - modded.dy; 1136 1137 WAIT_FIFO(par, 5); 1138 pm2_WR(par, PM2R_CONFIG, PM2F_CONFIG_FB_WRITE_ENABLE | 1139 PM2F_CONFIG_FB_READ_SOURCE_ENABLE); 1140 pm2_WR(par, PM2R_FB_SOURCE_DELTA, 1141 ((modded.sy - modded.dy) & 0xfff) << 16 | 1142 ((modded.sx - modded.dx) & 0xfff)); 1143 pm2_WR(par, PM2R_RECTANGLE_ORIGIN, (modded.dy << 16) | modded.dx); 1144 pm2_WR(par, PM2R_RECTANGLE_SIZE, (modded.height << 16) | modded.width); 1145 wmb(); 1146 pm2_WR(par, PM2R_RENDER, PM2F_RENDER_RECTANGLE | 1147 (modded.dx < modded.sx ? PM2F_INCREASE_X : 0) | 1148 (modded.dy < modded.sy ? PM2F_INCREASE_Y : 0)); 1149 } 1150 1151 static void pm2fb_imageblit(struct fb_info *info, const struct fb_image *image) 1152 { 1153 struct pm2fb_par *par = info->par; 1154 u32 height = image->height; 1155 u32 fgx, bgx; 1156 const u32 *src = (const u32 *)image->data; 1157 u32 xres = (info->var.xres + 31) & ~31; 1158 int raster_mode = 1; /* invert bits */ 1159 1160 #ifdef __LITTLE_ENDIAN 1161 raster_mode |= 3 << 7; /* reverse byte order */ 1162 #endif 1163 1164 if (info->state != FBINFO_STATE_RUNNING) 1165 return; 1166 if (info->flags & FBINFO_HWACCEL_DISABLED || image->depth != 1) { 1167 cfb_imageblit(info, image); 1168 return; 1169 } 1170 switch (info->fix.visual) { 1171 case FB_VISUAL_PSEUDOCOLOR: 1172 fgx = image->fg_color; 1173 bgx = image->bg_color; 1174 break; 1175 case FB_VISUAL_TRUECOLOR: 1176 default: 1177 fgx = par->palette[image->fg_color]; 1178 bgx = par->palette[image->bg_color]; 1179 break; 1180 } 1181 if (info->var.bits_per_pixel == 8) { 1182 fgx |= fgx << 8; 1183 bgx |= bgx << 8; 1184 } 1185 if (info->var.bits_per_pixel <= 16) { 1186 fgx |= fgx << 16; 1187 bgx |= bgx << 16; 1188 } 1189 1190 WAIT_FIFO(par, 13); 1191 pm2_WR(par, PM2R_FB_READ_MODE, partprod(xres)); 1192 pm2_WR(par, PM2R_SCISSOR_MIN_XY, 1193 ((image->dy & 0xfff) << 16) | (image->dx & 0x0fff)); 1194 pm2_WR(par, PM2R_SCISSOR_MAX_XY, 1195 (((image->dy + image->height) & 0x0fff) << 16) | 1196 ((image->dx + image->width) & 0x0fff)); 1197 pm2_WR(par, PM2R_SCISSOR_MODE, 1); 1198 /* GXcopy & UNIT_ENABLE */ 1199 pm2_WR(par, PM2R_LOGICAL_OP_MODE, (0x3 << 1) | 1); 1200 pm2_WR(par, PM2R_RECTANGLE_ORIGIN, 1201 ((image->dy & 0xfff) << 16) | (image->dx & 0x0fff)); 1202 pm2_WR(par, PM2R_RECTANGLE_SIZE, 1203 ((image->height & 0x0fff) << 16) | 1204 ((image->width) & 0x0fff)); 1205 if (info->var.bits_per_pixel == 24) { 1206 pm2_WR(par, PM2R_COLOR_DDA_MODE, 1); 1207 /* clear area */ 1208 pm2_WR(par, PM2R_CONSTANT_COLOR, bgx); 1209 pm2_WR(par, PM2R_RENDER, 1210 PM2F_RENDER_RECTANGLE | 1211 PM2F_INCREASE_X | PM2F_INCREASE_Y); 1212 /* BitMapPackEachScanline */ 1213 pm2_WR(par, PM2R_RASTERIZER_MODE, raster_mode | (1 << 9)); 1214 pm2_WR(par, PM2R_CONSTANT_COLOR, fgx); 1215 pm2_WR(par, PM2R_RENDER, 1216 PM2F_RENDER_RECTANGLE | 1217 PM2F_INCREASE_X | PM2F_INCREASE_Y | 1218 PM2F_RENDER_SYNC_ON_BIT_MASK); 1219 } else { 1220 pm2_WR(par, PM2R_COLOR_DDA_MODE, 0); 1221 /* clear area */ 1222 pm2_WR(par, PM2R_FB_BLOCK_COLOR, bgx); 1223 pm2_WR(par, PM2R_RENDER, 1224 PM2F_RENDER_RECTANGLE | 1225 PM2F_RENDER_FASTFILL | 1226 PM2F_INCREASE_X | PM2F_INCREASE_Y); 1227 pm2_WR(par, PM2R_RASTERIZER_MODE, raster_mode); 1228 pm2_WR(par, PM2R_FB_BLOCK_COLOR, fgx); 1229 pm2_WR(par, PM2R_RENDER, 1230 PM2F_RENDER_RECTANGLE | 1231 PM2F_INCREASE_X | PM2F_INCREASE_Y | 1232 PM2F_RENDER_FASTFILL | 1233 PM2F_RENDER_SYNC_ON_BIT_MASK); 1234 } 1235 1236 while (height--) { 1237 int width = ((image->width + 7) >> 3) 1238 + info->pixmap.scan_align - 1; 1239 width >>= 2; 1240 WAIT_FIFO(par, width); 1241 while (width--) { 1242 pm2_WR(par, PM2R_BIT_MASK_PATTERN, *src); 1243 src++; 1244 } 1245 } 1246 WAIT_FIFO(par, 3); 1247 pm2_WR(par, PM2R_RASTERIZER_MODE, 0); 1248 pm2_WR(par, PM2R_COLOR_DDA_MODE, 0); 1249 pm2_WR(par, PM2R_SCISSOR_MODE, 0); 1250 } 1251 1252 /* 1253 * Hardware cursor support. 1254 */ 1255 static const u8 cursor_bits_lookup[16] = { 1256 0x00, 0x40, 0x10, 0x50, 0x04, 0x44, 0x14, 0x54, 1257 0x01, 0x41, 0x11, 0x51, 0x05, 0x45, 0x15, 0x55 1258 }; 1259 1260 static int pm2vfb_cursor(struct fb_info *info, struct fb_cursor *cursor) 1261 { 1262 struct pm2fb_par *par = info->par; 1263 u8 mode = PM2F_CURSORMODE_TYPE_X; 1264 int x = cursor->image.dx - info->var.xoffset; 1265 int y = cursor->image.dy - info->var.yoffset; 1266 1267 if (cursor->enable) 1268 mode |= PM2F_CURSORMODE_CURSOR_ENABLE; 1269 1270 pm2v_RDAC_WR(par, PM2VI_RD_CURSOR_MODE, mode); 1271 1272 if (!cursor->enable) 1273 x = 2047; /* push it outside display */ 1274 pm2v_RDAC_WR(par, PM2VI_RD_CURSOR_X_LOW, x & 0xff); 1275 pm2v_RDAC_WR(par, PM2VI_RD_CURSOR_X_HIGH, (x >> 8) & 0xf); 1276 pm2v_RDAC_WR(par, PM2VI_RD_CURSOR_Y_LOW, y & 0xff); 1277 pm2v_RDAC_WR(par, PM2VI_RD_CURSOR_Y_HIGH, (y >> 8) & 0xf); 1278 1279 /* 1280 * If the cursor is not be changed this means either we want the 1281 * current cursor state (if enable is set) or we want to query what 1282 * we can do with the cursor (if enable is not set) 1283 */ 1284 if (!cursor->set) 1285 return 0; 1286 1287 if (cursor->set & FB_CUR_SETHOT) { 1288 pm2v_RDAC_WR(par, PM2VI_RD_CURSOR_X_HOT, 1289 cursor->hot.x & 0x3f); 1290 pm2v_RDAC_WR(par, PM2VI_RD_CURSOR_Y_HOT, 1291 cursor->hot.y & 0x3f); 1292 } 1293 1294 if (cursor->set & FB_CUR_SETCMAP) { 1295 u32 fg_idx = cursor->image.fg_color; 1296 u32 bg_idx = cursor->image.bg_color; 1297 struct fb_cmap cmap = info->cmap; 1298 1299 /* the X11 driver says one should use these color registers */ 1300 pm2_WR(par, PM2VR_RD_INDEX_HIGH, PM2VI_RD_CURSOR_PALETTE >> 8); 1301 pm2v_RDAC_WR(par, PM2VI_RD_CURSOR_PALETTE + 0, 1302 cmap.red[bg_idx] >> 8 ); 1303 pm2v_RDAC_WR(par, PM2VI_RD_CURSOR_PALETTE + 1, 1304 cmap.green[bg_idx] >> 8 ); 1305 pm2v_RDAC_WR(par, PM2VI_RD_CURSOR_PALETTE + 2, 1306 cmap.blue[bg_idx] >> 8 ); 1307 1308 pm2v_RDAC_WR(par, PM2VI_RD_CURSOR_PALETTE + 3, 1309 cmap.red[fg_idx] >> 8 ); 1310 pm2v_RDAC_WR(par, PM2VI_RD_CURSOR_PALETTE + 4, 1311 cmap.green[fg_idx] >> 8 ); 1312 pm2v_RDAC_WR(par, PM2VI_RD_CURSOR_PALETTE + 5, 1313 cmap.blue[fg_idx] >> 8 ); 1314 pm2_WR(par, PM2VR_RD_INDEX_HIGH, 0); 1315 } 1316 1317 if (cursor->set & (FB_CUR_SETSHAPE | FB_CUR_SETIMAGE)) { 1318 u8 *bitmap = (u8 *)cursor->image.data; 1319 u8 *mask = (u8 *)cursor->mask; 1320 int i; 1321 int pos = PM2VI_RD_CURSOR_PATTERN; 1322 1323 for (i = 0; i < cursor->image.height; i++) { 1324 int j = (cursor->image.width + 7) >> 3; 1325 int k = 8 - j; 1326 1327 pm2_WR(par, PM2VR_RD_INDEX_HIGH, pos >> 8); 1328 1329 for (; j > 0; j--) { 1330 u8 data = *bitmap ^ *mask; 1331 1332 if (cursor->rop == ROP_COPY) 1333 data = *mask & *bitmap; 1334 /* Upper 4 bits of bitmap data */ 1335 pm2v_RDAC_WR(par, pos++, 1336 cursor_bits_lookup[data >> 4] | 1337 (cursor_bits_lookup[*mask >> 4] << 1)); 1338 /* Lower 4 bits of bitmap */ 1339 pm2v_RDAC_WR(par, pos++, 1340 cursor_bits_lookup[data & 0xf] | 1341 (cursor_bits_lookup[*mask & 0xf] << 1)); 1342 bitmap++; 1343 mask++; 1344 } 1345 for (; k > 0; k--) { 1346 pm2v_RDAC_WR(par, pos++, 0); 1347 pm2v_RDAC_WR(par, pos++, 0); 1348 } 1349 } 1350 1351 while (pos < (1024 + PM2VI_RD_CURSOR_PATTERN)) { 1352 pm2_WR(par, PM2VR_RD_INDEX_HIGH, pos >> 8); 1353 pm2v_RDAC_WR(par, pos++, 0); 1354 } 1355 1356 pm2_WR(par, PM2VR_RD_INDEX_HIGH, 0); 1357 } 1358 return 0; 1359 } 1360 1361 static int pm2fb_cursor(struct fb_info *info, struct fb_cursor *cursor) 1362 { 1363 struct pm2fb_par *par = info->par; 1364 u8 mode; 1365 1366 if (!hwcursor) 1367 return -EINVAL; /* just to force soft_cursor() call */ 1368 1369 /* Too large of a cursor or wrong bpp :-( */ 1370 if (cursor->image.width > 64 || 1371 cursor->image.height > 64 || 1372 cursor->image.depth > 1) 1373 return -EINVAL; 1374 1375 if (par->type == PM2_TYPE_PERMEDIA2V) 1376 return pm2vfb_cursor(info, cursor); 1377 1378 mode = 0x40; 1379 if (cursor->enable) 1380 mode = 0x43; 1381 1382 pm2_RDAC_WR(par, PM2I_RD_CURSOR_CONTROL, mode); 1383 1384 /* 1385 * If the cursor is not be changed this means either we want the 1386 * current cursor state (if enable is set) or we want to query what 1387 * we can do with the cursor (if enable is not set) 1388 */ 1389 if (!cursor->set) 1390 return 0; 1391 1392 if (cursor->set & FB_CUR_SETPOS) { 1393 int x = cursor->image.dx - info->var.xoffset + 63; 1394 int y = cursor->image.dy - info->var.yoffset + 63; 1395 1396 WAIT_FIFO(par, 4); 1397 pm2_WR(par, PM2R_RD_CURSOR_X_LSB, x & 0xff); 1398 pm2_WR(par, PM2R_RD_CURSOR_X_MSB, (x >> 8) & 0x7); 1399 pm2_WR(par, PM2R_RD_CURSOR_Y_LSB, y & 0xff); 1400 pm2_WR(par, PM2R_RD_CURSOR_Y_MSB, (y >> 8) & 0x7); 1401 } 1402 1403 if (cursor->set & FB_CUR_SETCMAP) { 1404 u32 fg_idx = cursor->image.fg_color; 1405 u32 bg_idx = cursor->image.bg_color; 1406 1407 WAIT_FIFO(par, 7); 1408 pm2_WR(par, PM2R_RD_CURSOR_COLOR_ADDRESS, 1); 1409 pm2_WR(par, PM2R_RD_CURSOR_COLOR_DATA, 1410 info->cmap.red[bg_idx] >> 8); 1411 pm2_WR(par, PM2R_RD_CURSOR_COLOR_DATA, 1412 info->cmap.green[bg_idx] >> 8); 1413 pm2_WR(par, PM2R_RD_CURSOR_COLOR_DATA, 1414 info->cmap.blue[bg_idx] >> 8); 1415 1416 pm2_WR(par, PM2R_RD_CURSOR_COLOR_DATA, 1417 info->cmap.red[fg_idx] >> 8); 1418 pm2_WR(par, PM2R_RD_CURSOR_COLOR_DATA, 1419 info->cmap.green[fg_idx] >> 8); 1420 pm2_WR(par, PM2R_RD_CURSOR_COLOR_DATA, 1421 info->cmap.blue[fg_idx] >> 8); 1422 } 1423 1424 if (cursor->set & (FB_CUR_SETSHAPE | FB_CUR_SETIMAGE)) { 1425 u8 *bitmap = (u8 *)cursor->image.data; 1426 u8 *mask = (u8 *)cursor->mask; 1427 int i; 1428 1429 WAIT_FIFO(par, 1); 1430 pm2_WR(par, PM2R_RD_PALETTE_WRITE_ADDRESS, 0); 1431 1432 for (i = 0; i < cursor->image.height; i++) { 1433 int j = (cursor->image.width + 7) >> 3; 1434 int k = 8 - j; 1435 1436 WAIT_FIFO(par, 8); 1437 for (; j > 0; j--) { 1438 u8 data = *bitmap ^ *mask; 1439 1440 if (cursor->rop == ROP_COPY) 1441 data = *mask & *bitmap; 1442 /* bitmap data */ 1443 pm2_WR(par, PM2R_RD_CURSOR_DATA, data); 1444 bitmap++; 1445 mask++; 1446 } 1447 for (; k > 0; k--) 1448 pm2_WR(par, PM2R_RD_CURSOR_DATA, 0); 1449 } 1450 for (; i < 64; i++) { 1451 int j = 8; 1452 WAIT_FIFO(par, 8); 1453 while (j-- > 0) 1454 pm2_WR(par, PM2R_RD_CURSOR_DATA, 0); 1455 } 1456 1457 mask = (u8 *)cursor->mask; 1458 for (i = 0; i < cursor->image.height; i++) { 1459 int j = (cursor->image.width + 7) >> 3; 1460 int k = 8 - j; 1461 1462 WAIT_FIFO(par, 8); 1463 for (; j > 0; j--) { 1464 /* mask */ 1465 pm2_WR(par, PM2R_RD_CURSOR_DATA, *mask); 1466 mask++; 1467 } 1468 for (; k > 0; k--) 1469 pm2_WR(par, PM2R_RD_CURSOR_DATA, 0); 1470 } 1471 for (; i < 64; i++) { 1472 int j = 8; 1473 WAIT_FIFO(par, 8); 1474 while (j-- > 0) 1475 pm2_WR(par, PM2R_RD_CURSOR_DATA, 0); 1476 } 1477 } 1478 return 0; 1479 } 1480 1481 /* ------------ Hardware Independent Functions ------------ */ 1482 1483 /* 1484 * Frame buffer operations 1485 */ 1486 1487 static const struct fb_ops pm2fb_ops = { 1488 .owner = THIS_MODULE, 1489 .fb_check_var = pm2fb_check_var, 1490 .fb_set_par = pm2fb_set_par, 1491 .fb_setcolreg = pm2fb_setcolreg, 1492 .fb_blank = pm2fb_blank, 1493 .fb_pan_display = pm2fb_pan_display, 1494 .fb_fillrect = pm2fb_fillrect, 1495 .fb_copyarea = pm2fb_copyarea, 1496 .fb_imageblit = pm2fb_imageblit, 1497 .fb_sync = pm2fb_sync, 1498 .fb_cursor = pm2fb_cursor, 1499 }; 1500 1501 /* 1502 * PCI stuff 1503 */ 1504 1505 1506 /** 1507 * Device initialisation 1508 * 1509 * Initialise and allocate resource for PCI device. 1510 * 1511 * @pdev: PCI device. 1512 * @id: PCI device ID. 1513 */ 1514 static int pm2fb_probe(struct pci_dev *pdev, const struct pci_device_id *id) 1515 { 1516 struct pm2fb_par *default_par; 1517 struct fb_info *info; 1518 int err; 1519 int retval = -ENXIO; 1520 1521 err = pci_enable_device(pdev); 1522 if (err) { 1523 printk(KERN_WARNING "pm2fb: Can't enable pdev: %d\n", err); 1524 return err; 1525 } 1526 1527 info = framebuffer_alloc(sizeof(struct pm2fb_par), &pdev->dev); 1528 if (!info) 1529 return -ENOMEM; 1530 default_par = info->par; 1531 1532 switch (pdev->device) { 1533 case PCI_DEVICE_ID_TI_TVP4020: 1534 strcpy(pm2fb_fix.id, "TVP4020"); 1535 default_par->type = PM2_TYPE_PERMEDIA2; 1536 break; 1537 case PCI_DEVICE_ID_3DLABS_PERMEDIA2: 1538 strcpy(pm2fb_fix.id, "Permedia2"); 1539 default_par->type = PM2_TYPE_PERMEDIA2; 1540 break; 1541 case PCI_DEVICE_ID_3DLABS_PERMEDIA2V: 1542 strcpy(pm2fb_fix.id, "Permedia2v"); 1543 default_par->type = PM2_TYPE_PERMEDIA2V; 1544 break; 1545 } 1546 1547 pm2fb_fix.mmio_start = pci_resource_start(pdev, 0); 1548 pm2fb_fix.mmio_len = PM2_REGS_SIZE; 1549 1550 #if defined(__BIG_ENDIAN) 1551 /* 1552 * PM2 has a 64k register file, mapped twice in 128k. Lower 1553 * map is little-endian, upper map is big-endian. 1554 */ 1555 pm2fb_fix.mmio_start += PM2_REGS_SIZE; 1556 DPRINTK("Adjusting register base for big-endian.\n"); 1557 #endif 1558 DPRINTK("Register base at 0x%lx\n", pm2fb_fix.mmio_start); 1559 1560 /* Registers - request region and map it. */ 1561 if (!request_mem_region(pm2fb_fix.mmio_start, pm2fb_fix.mmio_len, 1562 "pm2fb regbase")) { 1563 printk(KERN_WARNING "pm2fb: Can't reserve regbase.\n"); 1564 goto err_exit_neither; 1565 } 1566 default_par->v_regs = 1567 ioremap(pm2fb_fix.mmio_start, pm2fb_fix.mmio_len); 1568 if (!default_par->v_regs) { 1569 printk(KERN_WARNING "pm2fb: Can't remap %s register area.\n", 1570 pm2fb_fix.id); 1571 release_mem_region(pm2fb_fix.mmio_start, pm2fb_fix.mmio_len); 1572 goto err_exit_neither; 1573 } 1574 1575 /* Stash away memory register info for use when we reset the board */ 1576 default_par->mem_control = pm2_RD(default_par, PM2R_MEM_CONTROL); 1577 default_par->boot_address = pm2_RD(default_par, PM2R_BOOT_ADDRESS); 1578 default_par->mem_config = pm2_RD(default_par, PM2R_MEM_CONFIG); 1579 DPRINTK("MemControl 0x%x BootAddress 0x%x MemConfig 0x%x\n", 1580 default_par->mem_control, default_par->boot_address, 1581 default_par->mem_config); 1582 1583 if (default_par->mem_control == 0 && 1584 default_par->boot_address == 0x31 && 1585 default_par->mem_config == 0x259fffff) { 1586 default_par->memclock = CVPPC_MEMCLOCK; 1587 default_par->mem_control = 0; 1588 default_par->boot_address = 0x20; 1589 default_par->mem_config = 0xe6002021; 1590 if (pdev->subsystem_vendor == 0x1048 && 1591 pdev->subsystem_device == 0x0a31) { 1592 DPRINTK("subsystem_vendor: %04x, " 1593 "subsystem_device: %04x\n", 1594 pdev->subsystem_vendor, pdev->subsystem_device); 1595 DPRINTK("We have not been initialized by VGA BIOS and " 1596 "are running on an Elsa Winner 2000 Office\n"); 1597 DPRINTK("Initializing card timings manually...\n"); 1598 default_par->memclock = 100000; 1599 } 1600 if (pdev->subsystem_vendor == 0x3d3d && 1601 pdev->subsystem_device == 0x0100) { 1602 DPRINTK("subsystem_vendor: %04x, " 1603 "subsystem_device: %04x\n", 1604 pdev->subsystem_vendor, pdev->subsystem_device); 1605 DPRINTK("We have not been initialized by VGA BIOS and " 1606 "are running on an 3dlabs reference board\n"); 1607 DPRINTK("Initializing card timings manually...\n"); 1608 default_par->memclock = 74894; 1609 } 1610 } 1611 1612 /* Now work out how big lfb is going to be. */ 1613 switch (default_par->mem_config & PM2F_MEM_CONFIG_RAM_MASK) { 1614 case PM2F_MEM_BANKS_1: 1615 pm2fb_fix.smem_len = 0x200000; 1616 break; 1617 case PM2F_MEM_BANKS_2: 1618 pm2fb_fix.smem_len = 0x400000; 1619 break; 1620 case PM2F_MEM_BANKS_3: 1621 pm2fb_fix.smem_len = 0x600000; 1622 break; 1623 case PM2F_MEM_BANKS_4: 1624 pm2fb_fix.smem_len = 0x800000; 1625 break; 1626 } 1627 pm2fb_fix.smem_start = pci_resource_start(pdev, 1); 1628 1629 /* Linear frame buffer - request region and map it. */ 1630 if (!request_mem_region(pm2fb_fix.smem_start, pm2fb_fix.smem_len, 1631 "pm2fb smem")) { 1632 printk(KERN_WARNING "pm2fb: Can't reserve smem.\n"); 1633 goto err_exit_mmio; 1634 } 1635 info->screen_base = 1636 ioremap_wc(pm2fb_fix.smem_start, pm2fb_fix.smem_len); 1637 if (!info->screen_base) { 1638 printk(KERN_WARNING "pm2fb: Can't ioremap smem area.\n"); 1639 release_mem_region(pm2fb_fix.smem_start, pm2fb_fix.smem_len); 1640 goto err_exit_mmio; 1641 } 1642 1643 if (!nomtrr) 1644 default_par->wc_cookie = arch_phys_wc_add(pm2fb_fix.smem_start, 1645 pm2fb_fix.smem_len); 1646 1647 info->fbops = &pm2fb_ops; 1648 info->fix = pm2fb_fix; 1649 info->pseudo_palette = default_par->palette; 1650 info->flags = FBINFO_DEFAULT | 1651 FBINFO_HWACCEL_YPAN | 1652 FBINFO_HWACCEL_COPYAREA | 1653 FBINFO_HWACCEL_IMAGEBLIT | 1654 FBINFO_HWACCEL_FILLRECT; 1655 1656 info->pixmap.addr = kmalloc(PM2_PIXMAP_SIZE, GFP_KERNEL); 1657 if (!info->pixmap.addr) { 1658 retval = -ENOMEM; 1659 goto err_exit_pixmap; 1660 } 1661 info->pixmap.size = PM2_PIXMAP_SIZE; 1662 info->pixmap.buf_align = 4; 1663 info->pixmap.scan_align = 4; 1664 info->pixmap.access_align = 32; 1665 info->pixmap.flags = FB_PIXMAP_SYSTEM; 1666 1667 if (noaccel) { 1668 printk(KERN_DEBUG "disabling acceleration\n"); 1669 info->flags |= FBINFO_HWACCEL_DISABLED; 1670 info->pixmap.scan_align = 1; 1671 } 1672 1673 if (!mode_option) 1674 mode_option = "640x480@60"; 1675 1676 err = fb_find_mode(&info->var, info, mode_option, NULL, 0, NULL, 8); 1677 if (!err || err == 4) 1678 info->var = pm2fb_var; 1679 1680 retval = fb_alloc_cmap(&info->cmap, 256, 0); 1681 if (retval < 0) 1682 goto err_exit_both; 1683 1684 retval = register_framebuffer(info); 1685 if (retval < 0) 1686 goto err_exit_all; 1687 1688 fb_info(info, "%s frame buffer device, memory = %dK\n", 1689 info->fix.id, pm2fb_fix.smem_len / 1024); 1690 1691 /* 1692 * Our driver data 1693 */ 1694 pci_set_drvdata(pdev, info); 1695 1696 return 0; 1697 1698 err_exit_all: 1699 fb_dealloc_cmap(&info->cmap); 1700 err_exit_both: 1701 kfree(info->pixmap.addr); 1702 err_exit_pixmap: 1703 iounmap(info->screen_base); 1704 release_mem_region(pm2fb_fix.smem_start, pm2fb_fix.smem_len); 1705 err_exit_mmio: 1706 iounmap(default_par->v_regs); 1707 release_mem_region(pm2fb_fix.mmio_start, pm2fb_fix.mmio_len); 1708 err_exit_neither: 1709 framebuffer_release(info); 1710 return retval; 1711 } 1712 1713 /** 1714 * Device removal. 1715 * 1716 * Release all device resources. 1717 * 1718 * @pdev: PCI device to clean up. 1719 */ 1720 static void pm2fb_remove(struct pci_dev *pdev) 1721 { 1722 struct fb_info *info = pci_get_drvdata(pdev); 1723 struct fb_fix_screeninfo *fix = &info->fix; 1724 struct pm2fb_par *par = info->par; 1725 1726 unregister_framebuffer(info); 1727 arch_phys_wc_del(par->wc_cookie); 1728 iounmap(info->screen_base); 1729 release_mem_region(fix->smem_start, fix->smem_len); 1730 iounmap(par->v_regs); 1731 release_mem_region(fix->mmio_start, fix->mmio_len); 1732 1733 fb_dealloc_cmap(&info->cmap); 1734 kfree(info->pixmap.addr); 1735 framebuffer_release(info); 1736 } 1737 1738 static const struct pci_device_id pm2fb_id_table[] = { 1739 { PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TVP4020, 1740 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 1741 { PCI_VENDOR_ID_3DLABS, PCI_DEVICE_ID_3DLABS_PERMEDIA2, 1742 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 1743 { PCI_VENDOR_ID_3DLABS, PCI_DEVICE_ID_3DLABS_PERMEDIA2V, 1744 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 1745 { 0, } 1746 }; 1747 1748 static struct pci_driver pm2fb_driver = { 1749 .name = "pm2fb", 1750 .id_table = pm2fb_id_table, 1751 .probe = pm2fb_probe, 1752 .remove = pm2fb_remove, 1753 }; 1754 1755 MODULE_DEVICE_TABLE(pci, pm2fb_id_table); 1756 1757 1758 #ifndef MODULE 1759 /* 1760 * Parse user specified options. 1761 * 1762 * This is, comma-separated options following `video=pm2fb:'. 1763 */ 1764 static int __init pm2fb_setup(char *options) 1765 { 1766 char *this_opt; 1767 1768 if (!options || !*options) 1769 return 0; 1770 1771 while ((this_opt = strsep(&options, ",")) != NULL) { 1772 if (!*this_opt) 1773 continue; 1774 if (!strcmp(this_opt, "lowhsync")) 1775 lowhsync = 1; 1776 else if (!strcmp(this_opt, "lowvsync")) 1777 lowvsync = 1; 1778 else if (!strncmp(this_opt, "hwcursor=", 9)) 1779 hwcursor = simple_strtoul(this_opt + 9, NULL, 0); 1780 else if (!strncmp(this_opt, "nomtrr", 6)) 1781 nomtrr = 1; 1782 else if (!strncmp(this_opt, "noaccel", 7)) 1783 noaccel = 1; 1784 else 1785 mode_option = this_opt; 1786 } 1787 return 0; 1788 } 1789 #endif 1790 1791 1792 static int __init pm2fb_init(void) 1793 { 1794 #ifndef MODULE 1795 char *option = NULL; 1796 1797 if (fb_get_options("pm2fb", &option)) 1798 return -ENODEV; 1799 pm2fb_setup(option); 1800 #endif 1801 1802 return pci_register_driver(&pm2fb_driver); 1803 } 1804 1805 module_init(pm2fb_init); 1806 1807 #ifdef MODULE 1808 /* 1809 * Cleanup 1810 */ 1811 1812 static void __exit pm2fb_exit(void) 1813 { 1814 pci_unregister_driver(&pm2fb_driver); 1815 } 1816 #endif 1817 1818 #ifdef MODULE 1819 module_exit(pm2fb_exit); 1820 1821 module_param(mode_option, charp, 0); 1822 MODULE_PARM_DESC(mode_option, "Initial video mode e.g. '648x480-8@60'"); 1823 module_param_named(mode, mode_option, charp, 0); 1824 MODULE_PARM_DESC(mode, "Initial video mode e.g. '648x480-8@60' (deprecated)"); 1825 module_param(lowhsync, bool, 0); 1826 MODULE_PARM_DESC(lowhsync, "Force horizontal sync low regardless of mode"); 1827 module_param(lowvsync, bool, 0); 1828 MODULE_PARM_DESC(lowvsync, "Force vertical sync low regardless of mode"); 1829 module_param(noaccel, bool, 0); 1830 MODULE_PARM_DESC(noaccel, "Disable acceleration"); 1831 module_param(hwcursor, int, 0644); 1832 MODULE_PARM_DESC(hwcursor, "Enable hardware cursor " 1833 "(1=enable, 0=disable, default=1)"); 1834 module_param(nomtrr, bool, 0); 1835 MODULE_PARM_DESC(nomtrr, "Disable MTRR support (0 or 1=disabled) (default=0)"); 1836 1837 MODULE_AUTHOR("Jim Hague <jim.hague@acm.org>"); 1838 MODULE_DESCRIPTION("Permedia2 framebuffer device driver"); 1839 MODULE_LICENSE("GPL"); 1840 #endif 1841