1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * HDMI PLL 4 * 5 * Copyright (C) 2013 Texas Instruments Incorporated 6 */ 7 8 #define DSS_SUBSYS_NAME "HDMIPLL" 9 10 #include <linux/kernel.h> 11 #include <linux/module.h> 12 #include <linux/err.h> 13 #include <linux/io.h> 14 #include <linux/platform_device.h> 15 #include <linux/clk.h> 16 #include <linux/seq_file.h> 17 18 #include <video/omapfb_dss.h> 19 20 #include "dss.h" 21 #include "hdmi.h" 22 23 void hdmi_pll_dump(struct hdmi_pll_data *pll, struct seq_file *s) 24 { 25 #define DUMPPLL(r) seq_printf(s, "%-35s %08x\n", #r,\ 26 hdmi_read_reg(pll->base, r)) 27 28 DUMPPLL(PLLCTRL_PLL_CONTROL); 29 DUMPPLL(PLLCTRL_PLL_STATUS); 30 DUMPPLL(PLLCTRL_PLL_GO); 31 DUMPPLL(PLLCTRL_CFG1); 32 DUMPPLL(PLLCTRL_CFG2); 33 DUMPPLL(PLLCTRL_CFG3); 34 DUMPPLL(PLLCTRL_SSC_CFG1); 35 DUMPPLL(PLLCTRL_SSC_CFG2); 36 DUMPPLL(PLLCTRL_CFG4); 37 } 38 39 void hdmi_pll_compute(struct hdmi_pll_data *pll, 40 unsigned long target_tmds, struct dss_pll_clock_info *pi) 41 { 42 unsigned long fint, clkdco, clkout; 43 unsigned long target_bitclk, target_clkdco; 44 unsigned long min_dco; 45 unsigned n, m, mf, m2, sd; 46 unsigned long clkin; 47 const struct dss_pll_hw *hw = pll->pll.hw; 48 49 clkin = clk_get_rate(pll->pll.clkin); 50 51 DSSDBG("clkin %lu, target tmds %lu\n", clkin, target_tmds); 52 53 target_bitclk = target_tmds * 10; 54 55 /* Fint */ 56 n = DIV_ROUND_UP(clkin, hw->fint_max); 57 fint = clkin / n; 58 59 /* adjust m2 so that the clkdco will be high enough */ 60 min_dco = roundup(hw->clkdco_min, fint); 61 m2 = DIV_ROUND_UP(min_dco, target_bitclk); 62 if (m2 == 0) 63 m2 = 1; 64 65 target_clkdco = target_bitclk * m2; 66 m = target_clkdco / fint; 67 68 clkdco = fint * m; 69 70 /* adjust clkdco with fractional mf */ 71 if (WARN_ON(target_clkdco - clkdco > fint)) 72 mf = 0; 73 else 74 mf = (u32)div_u64(262144ull * (target_clkdco - clkdco), fint); 75 76 if (mf > 0) 77 clkdco += (u32)div_u64((u64)mf * fint, 262144); 78 79 clkout = clkdco / m2; 80 81 /* sigma-delta */ 82 sd = DIV_ROUND_UP(fint * m, 250000000); 83 84 DSSDBG("N = %u, M = %u, M.f = %u, M2 = %u, SD = %u\n", 85 n, m, mf, m2, sd); 86 DSSDBG("Fint %lu, clkdco %lu, clkout %lu\n", fint, clkdco, clkout); 87 88 pi->n = n; 89 pi->m = m; 90 pi->mf = mf; 91 pi->mX[0] = m2; 92 pi->sd = sd; 93 94 pi->fint = fint; 95 pi->clkdco = clkdco; 96 pi->clkout[0] = clkout; 97 } 98 99 static int hdmi_pll_enable(struct dss_pll *dsspll) 100 { 101 struct hdmi_pll_data *pll = container_of(dsspll, struct hdmi_pll_data, pll); 102 struct hdmi_wp_data *wp = pll->wp; 103 u16 r = 0; 104 105 dss_ctrl_pll_enable(DSS_PLL_HDMI, true); 106 107 return hdmi_wp_set_pll_pwr(wp, HDMI_PLLPWRCMD_BOTHON_ALLCLKS); 108 } 109 110 static void hdmi_pll_disable(struct dss_pll *dsspll) 111 { 112 struct hdmi_pll_data *pll = container_of(dsspll, struct hdmi_pll_data, pll); 113 struct hdmi_wp_data *wp = pll->wp; 114 115 hdmi_wp_set_pll_pwr(wp, HDMI_PLLPWRCMD_ALLOFF); 116 117 dss_ctrl_pll_enable(DSS_PLL_HDMI, false); 118 } 119 120 static const struct dss_pll_ops dsi_pll_ops = { 121 .enable = hdmi_pll_enable, 122 .disable = hdmi_pll_disable, 123 .set_config = dss_pll_write_config_type_b, 124 }; 125 126 static const struct dss_pll_hw dss_omap4_hdmi_pll_hw = { 127 .n_max = 255, 128 .m_min = 20, 129 .m_max = 4095, 130 .mX_max = 127, 131 .fint_min = 500000, 132 .fint_max = 2500000, 133 134 .clkdco_min = 500000000, 135 .clkdco_low = 1000000000, 136 .clkdco_max = 2000000000, 137 138 .n_msb = 8, 139 .n_lsb = 1, 140 .m_msb = 20, 141 .m_lsb = 9, 142 143 .mX_msb[0] = 24, 144 .mX_lsb[0] = 18, 145 146 .has_selfreqdco = true, 147 }; 148 149 static const struct dss_pll_hw dss_omap5_hdmi_pll_hw = { 150 .n_max = 255, 151 .m_min = 20, 152 .m_max = 2045, 153 .mX_max = 127, 154 .fint_min = 620000, 155 .fint_max = 2500000, 156 157 .clkdco_min = 750000000, 158 .clkdco_low = 1500000000, 159 .clkdco_max = 2500000000UL, 160 161 .n_msb = 8, 162 .n_lsb = 1, 163 .m_msb = 20, 164 .m_lsb = 9, 165 166 .mX_msb[0] = 24, 167 .mX_lsb[0] = 18, 168 169 .has_selfreqdco = true, 170 .has_refsel = true, 171 }; 172 173 static int dsi_init_pll_data(struct platform_device *pdev, struct hdmi_pll_data *hpll) 174 { 175 struct dss_pll *pll = &hpll->pll; 176 struct clk *clk; 177 int r; 178 179 clk = devm_clk_get(&pdev->dev, "sys_clk"); 180 if (IS_ERR(clk)) { 181 DSSERR("can't get sys_clk\n"); 182 return PTR_ERR(clk); 183 } 184 185 pll->name = "hdmi"; 186 pll->id = DSS_PLL_HDMI; 187 pll->base = hpll->base; 188 pll->clkin = clk; 189 190 switch (omapdss_get_version()) { 191 case OMAPDSS_VER_OMAP4430_ES1: 192 case OMAPDSS_VER_OMAP4430_ES2: 193 case OMAPDSS_VER_OMAP4: 194 pll->hw = &dss_omap4_hdmi_pll_hw; 195 break; 196 197 case OMAPDSS_VER_OMAP5: 198 case OMAPDSS_VER_DRA7xx: 199 pll->hw = &dss_omap5_hdmi_pll_hw; 200 break; 201 202 default: 203 return -ENODEV; 204 } 205 206 pll->ops = &dsi_pll_ops; 207 208 r = dss_pll_register(pll); 209 if (r) 210 return r; 211 212 return 0; 213 } 214 215 int hdmi_pll_init(struct platform_device *pdev, struct hdmi_pll_data *pll, 216 struct hdmi_wp_data *wp) 217 { 218 int r; 219 struct resource *res; 220 221 pll->wp = wp; 222 223 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pll"); 224 if (!res) { 225 DSSERR("can't get PLL mem resource\n"); 226 return -EINVAL; 227 } 228 229 pll->base = devm_ioremap_resource(&pdev->dev, res); 230 if (IS_ERR(pll->base)) { 231 DSSERR("can't ioremap PLLCTRL\n"); 232 return PTR_ERR(pll->base); 233 } 234 235 r = dsi_init_pll_data(pdev, pll); 236 if (r) { 237 DSSERR("failed to init HDMI PLL\n"); 238 return r; 239 } 240 241 return 0; 242 } 243 244 void hdmi_pll_uninit(struct hdmi_pll_data *hpll) 245 { 246 struct dss_pll *pll = &hpll->pll; 247 248 dss_pll_unregister(pll); 249 } 250