1 /* 2 * OMAP5 HDMI CORE IP driver library 3 * 4 * Copyright (C) 2014 Texas Instruments Incorporated 5 * 6 * Authors: 7 * Yong Zhi 8 * Mythri pk 9 * Archit Taneja <archit@ti.com> 10 * Tomi Valkeinen <tomi.valkeinen@ti.com> 11 * 12 * This program is free software; you can redistribute it and/or modify it 13 * under the terms of the GNU General Public License version 2 as published by 14 * the Free Software Foundation. 15 * 16 * This program is distributed in the hope that it will be useful, but WITHOUT 17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 19 * more details. 20 * 21 * You should have received a copy of the GNU General Public License along with 22 * this program. If not, see <http://www.gnu.org/licenses/>. 23 */ 24 25 #include <linux/kernel.h> 26 #include <linux/module.h> 27 #include <linux/err.h> 28 #include <linux/io.h> 29 #include <linux/delay.h> 30 #include <linux/string.h> 31 #include <linux/seq_file.h> 32 #include <drm/drm_edid.h> 33 #include <sound/asound.h> 34 #include <sound/asoundef.h> 35 36 #include "hdmi5_core.h" 37 38 /* only 24 bit color depth used for now */ 39 static const struct csc_table csc_table_deepcolor[] = { 40 /* HDMI_DEEP_COLOR_24BIT */ 41 [0] = { 7036, 0, 0, 32, 0, 7036, 0, 32, 0, 0, 7036, 32, }, 42 /* HDMI_DEEP_COLOR_30BIT */ 43 [1] = { 7015, 0, 0, 128, 0, 7015, 0, 128, 0, 0, 7015, 128, }, 44 /* HDMI_DEEP_COLOR_36BIT */ 45 [2] = { 7010, 0, 0, 512, 0, 7010, 0, 512, 0, 0, 7010, 512, }, 46 /* FULL RANGE */ 47 [3] = { 8192, 0, 0, 0, 0, 8192, 0, 0, 0, 0, 8192, 0, }, 48 }; 49 50 static void hdmi_core_ddc_init(struct hdmi_core_data *core) 51 { 52 void __iomem *base = core->base; 53 const unsigned long long iclk = 266000000; /* DSS L3 ICLK */ 54 const unsigned ss_scl_high = 4600; /* ns */ 55 const unsigned ss_scl_low = 5400; /* ns */ 56 const unsigned fs_scl_high = 600; /* ns */ 57 const unsigned fs_scl_low = 1300; /* ns */ 58 const unsigned sda_hold = 1000; /* ns */ 59 const unsigned sfr_div = 10; 60 unsigned long long sfr; 61 unsigned v; 62 63 sfr = iclk / sfr_div; /* SFR_DIV */ 64 sfr /= 1000; /* SFR clock in kHz */ 65 66 /* Reset */ 67 REG_FLD_MOD(base, HDMI_CORE_I2CM_SOFTRSTZ, 0, 0, 0); 68 if (hdmi_wait_for_bit_change(base, HDMI_CORE_I2CM_SOFTRSTZ, 69 0, 0, 1) != 1) 70 DSSERR("HDMI I2CM reset failed\n"); 71 72 /* Standard (0) or Fast (1) Mode */ 73 REG_FLD_MOD(base, HDMI_CORE_I2CM_DIV, 0, 3, 3); 74 75 /* Standard Mode SCL High counter */ 76 v = DIV_ROUND_UP_ULL(ss_scl_high * sfr, 1000000); 77 REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_HCNT_1_ADDR, 78 (v >> 8) & 0xff, 7, 0); 79 REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_HCNT_0_ADDR, 80 v & 0xff, 7, 0); 81 82 /* Standard Mode SCL Low counter */ 83 v = DIV_ROUND_UP_ULL(ss_scl_low * sfr, 1000000); 84 REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_LCNT_1_ADDR, 85 (v >> 8) & 0xff, 7, 0); 86 REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_LCNT_0_ADDR, 87 v & 0xff, 7, 0); 88 89 /* Fast Mode SCL High Counter */ 90 v = DIV_ROUND_UP_ULL(fs_scl_high * sfr, 1000000); 91 REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_HCNT_1_ADDR, 92 (v >> 8) & 0xff, 7, 0); 93 REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_HCNT_0_ADDR, 94 v & 0xff, 7, 0); 95 96 /* Fast Mode SCL Low Counter */ 97 v = DIV_ROUND_UP_ULL(fs_scl_low * sfr, 1000000); 98 REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_LCNT_1_ADDR, 99 (v >> 8) & 0xff, 7, 0); 100 REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_LCNT_0_ADDR, 101 v & 0xff, 7, 0); 102 103 /* SDA Hold Time */ 104 v = DIV_ROUND_UP_ULL(sda_hold * sfr, 1000000); 105 REG_FLD_MOD(base, HDMI_CORE_I2CM_SDA_HOLD_ADDR, v & 0xff, 7, 0); 106 107 REG_FLD_MOD(base, HDMI_CORE_I2CM_SLAVE, 0x50, 6, 0); 108 REG_FLD_MOD(base, HDMI_CORE_I2CM_SEGADDR, 0x30, 6, 0); 109 110 /* NACK_POL to high */ 111 REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 7, 7); 112 113 /* NACK_MASK to unmasked */ 114 REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x0, 6, 6); 115 116 /* ARBITRATION_POL to high */ 117 REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 3, 3); 118 119 /* ARBITRATION_MASK to unmasked */ 120 REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x0, 2, 2); 121 122 /* DONE_POL to high */ 123 REG_FLD_MOD(base, HDMI_CORE_I2CM_INT, 0x1, 3, 3); 124 125 /* DONE_MASK to unmasked */ 126 REG_FLD_MOD(base, HDMI_CORE_I2CM_INT, 0x0, 2, 2); 127 } 128 129 static void hdmi_core_ddc_uninit(struct hdmi_core_data *core) 130 { 131 void __iomem *base = core->base; 132 133 /* Mask I2C interrupts */ 134 REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 6, 6); 135 REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 2, 2); 136 REG_FLD_MOD(base, HDMI_CORE_I2CM_INT, 0x1, 2, 2); 137 } 138 139 static int hdmi_core_ddc_edid(struct hdmi_core_data *core, u8 *pedid, u8 ext) 140 { 141 void __iomem *base = core->base; 142 u8 cur_addr; 143 char checksum = 0; 144 const int retries = 1000; 145 u8 seg_ptr = ext / 2; 146 u8 edidbase = ((ext % 2) * 0x80); 147 148 REG_FLD_MOD(base, HDMI_CORE_I2CM_SEGPTR, seg_ptr, 7, 0); 149 150 /* 151 * TODO: We use polling here, although we probably should use proper 152 * interrupts. 153 */ 154 for (cur_addr = 0; cur_addr < 128; ++cur_addr) { 155 int i; 156 157 /* clear ERROR and DONE */ 158 REG_FLD_MOD(base, HDMI_CORE_IH_I2CM_STAT0, 0x3, 1, 0); 159 160 REG_FLD_MOD(base, HDMI_CORE_I2CM_ADDRESS, 161 edidbase + cur_addr, 7, 0); 162 163 if (seg_ptr) 164 REG_FLD_MOD(base, HDMI_CORE_I2CM_OPERATION, 1, 1, 1); 165 else 166 REG_FLD_MOD(base, HDMI_CORE_I2CM_OPERATION, 1, 0, 0); 167 168 for (i = 0; i < retries; ++i) { 169 u32 stat; 170 171 stat = REG_GET(base, HDMI_CORE_IH_I2CM_STAT0, 1, 0); 172 173 /* I2CM_ERROR */ 174 if (stat & 1) { 175 DSSERR("HDMI I2C Master Error\n"); 176 return -EIO; 177 } 178 179 /* I2CM_DONE */ 180 if (stat & (1 << 1)) 181 break; 182 183 usleep_range(250, 1000); 184 } 185 186 if (i == retries) { 187 DSSERR("HDMI I2C timeout reading EDID\n"); 188 return -EIO; 189 } 190 191 pedid[cur_addr] = REG_GET(base, HDMI_CORE_I2CM_DATAI, 7, 0); 192 checksum += pedid[cur_addr]; 193 } 194 195 return 0; 196 197 } 198 199 int hdmi5_read_edid(struct hdmi_core_data *core, u8 *edid, int len) 200 { 201 int r, n, i; 202 int max_ext_blocks = (len / 128) - 1; 203 204 if (len < 128) 205 return -EINVAL; 206 207 hdmi_core_ddc_init(core); 208 209 r = hdmi_core_ddc_edid(core, edid, 0); 210 if (r) 211 goto out; 212 213 n = edid[0x7e]; 214 215 if (n > max_ext_blocks) 216 n = max_ext_blocks; 217 218 for (i = 1; i <= n; i++) { 219 r = hdmi_core_ddc_edid(core, edid + i * EDID_LENGTH, i); 220 if (r) 221 goto out; 222 } 223 224 out: 225 hdmi_core_ddc_uninit(core); 226 227 return r ? r : len; 228 } 229 230 void hdmi5_core_dump(struct hdmi_core_data *core, struct seq_file *s) 231 { 232 233 #define DUMPCORE(r) seq_printf(s, "%-35s %08x\n", #r,\ 234 hdmi_read_reg(core->base, r)) 235 236 DUMPCORE(HDMI_CORE_FC_INVIDCONF); 237 DUMPCORE(HDMI_CORE_FC_INHACTIV0); 238 DUMPCORE(HDMI_CORE_FC_INHACTIV1); 239 DUMPCORE(HDMI_CORE_FC_INHBLANK0); 240 DUMPCORE(HDMI_CORE_FC_INHBLANK1); 241 DUMPCORE(HDMI_CORE_FC_INVACTIV0); 242 DUMPCORE(HDMI_CORE_FC_INVACTIV1); 243 DUMPCORE(HDMI_CORE_FC_INVBLANK); 244 DUMPCORE(HDMI_CORE_FC_HSYNCINDELAY0); 245 DUMPCORE(HDMI_CORE_FC_HSYNCINDELAY1); 246 DUMPCORE(HDMI_CORE_FC_HSYNCINWIDTH0); 247 DUMPCORE(HDMI_CORE_FC_HSYNCINWIDTH1); 248 DUMPCORE(HDMI_CORE_FC_VSYNCINDELAY); 249 DUMPCORE(HDMI_CORE_FC_VSYNCINWIDTH); 250 DUMPCORE(HDMI_CORE_FC_CTRLDUR); 251 DUMPCORE(HDMI_CORE_FC_EXCTRLDUR); 252 DUMPCORE(HDMI_CORE_FC_EXCTRLSPAC); 253 DUMPCORE(HDMI_CORE_FC_CH0PREAM); 254 DUMPCORE(HDMI_CORE_FC_CH1PREAM); 255 DUMPCORE(HDMI_CORE_FC_CH2PREAM); 256 DUMPCORE(HDMI_CORE_FC_AVICONF0); 257 DUMPCORE(HDMI_CORE_FC_AVICONF1); 258 DUMPCORE(HDMI_CORE_FC_AVICONF2); 259 DUMPCORE(HDMI_CORE_FC_AVIVID); 260 DUMPCORE(HDMI_CORE_FC_PRCONF); 261 262 DUMPCORE(HDMI_CORE_MC_CLKDIS); 263 DUMPCORE(HDMI_CORE_MC_SWRSTZREQ); 264 DUMPCORE(HDMI_CORE_MC_FLOWCTRL); 265 DUMPCORE(HDMI_CORE_MC_PHYRSTZ); 266 DUMPCORE(HDMI_CORE_MC_LOCKONCLOCK); 267 268 DUMPCORE(HDMI_CORE_I2CM_SLAVE); 269 DUMPCORE(HDMI_CORE_I2CM_ADDRESS); 270 DUMPCORE(HDMI_CORE_I2CM_DATAO); 271 DUMPCORE(HDMI_CORE_I2CM_DATAI); 272 DUMPCORE(HDMI_CORE_I2CM_OPERATION); 273 DUMPCORE(HDMI_CORE_I2CM_INT); 274 DUMPCORE(HDMI_CORE_I2CM_CTLINT); 275 DUMPCORE(HDMI_CORE_I2CM_DIV); 276 DUMPCORE(HDMI_CORE_I2CM_SEGADDR); 277 DUMPCORE(HDMI_CORE_I2CM_SOFTRSTZ); 278 DUMPCORE(HDMI_CORE_I2CM_SEGPTR); 279 DUMPCORE(HDMI_CORE_I2CM_SS_SCL_HCNT_1_ADDR); 280 DUMPCORE(HDMI_CORE_I2CM_SS_SCL_HCNT_0_ADDR); 281 DUMPCORE(HDMI_CORE_I2CM_SS_SCL_LCNT_1_ADDR); 282 DUMPCORE(HDMI_CORE_I2CM_SS_SCL_LCNT_0_ADDR); 283 DUMPCORE(HDMI_CORE_I2CM_FS_SCL_HCNT_1_ADDR); 284 DUMPCORE(HDMI_CORE_I2CM_FS_SCL_HCNT_0_ADDR); 285 DUMPCORE(HDMI_CORE_I2CM_FS_SCL_LCNT_1_ADDR); 286 DUMPCORE(HDMI_CORE_I2CM_FS_SCL_LCNT_0_ADDR); 287 DUMPCORE(HDMI_CORE_I2CM_SDA_HOLD_ADDR); 288 } 289 290 static void hdmi_core_init(struct hdmi_core_vid_config *video_cfg, 291 struct hdmi_config *cfg) 292 { 293 DSSDBG("hdmi_core_init\n"); 294 295 /* video core */ 296 video_cfg->data_enable_pol = 1; /* It is always 1*/ 297 video_cfg->v_fc_config.timings.hsync_level = cfg->timings.hsync_level; 298 video_cfg->v_fc_config.timings.x_res = cfg->timings.x_res; 299 video_cfg->v_fc_config.timings.hsw = cfg->timings.hsw - 1; 300 video_cfg->v_fc_config.timings.hbp = cfg->timings.hbp; 301 video_cfg->v_fc_config.timings.hfp = cfg->timings.hfp; 302 video_cfg->hblank = cfg->timings.hfp + 303 cfg->timings.hbp + cfg->timings.hsw - 1; 304 video_cfg->v_fc_config.timings.vsync_level = cfg->timings.vsync_level; 305 video_cfg->v_fc_config.timings.y_res = cfg->timings.y_res; 306 video_cfg->v_fc_config.timings.vsw = cfg->timings.vsw; 307 video_cfg->v_fc_config.timings.vfp = cfg->timings.vfp; 308 video_cfg->v_fc_config.timings.vbp = cfg->timings.vbp; 309 video_cfg->vblank_osc = 0; /* Always 0 - need to confirm */ 310 video_cfg->vblank = cfg->timings.vsw + 311 cfg->timings.vfp + cfg->timings.vbp; 312 video_cfg->v_fc_config.hdmi_dvi_mode = cfg->hdmi_dvi_mode; 313 video_cfg->v_fc_config.timings.interlace = cfg->timings.interlace; 314 } 315 316 /* DSS_HDMI_CORE_VIDEO_CONFIG */ 317 static void hdmi_core_video_config(struct hdmi_core_data *core, 318 struct hdmi_core_vid_config *cfg) 319 { 320 void __iomem *base = core->base; 321 unsigned char r = 0; 322 bool vsync_pol, hsync_pol; 323 324 vsync_pol = 325 cfg->v_fc_config.timings.vsync_level == OMAPDSS_SIG_ACTIVE_HIGH; 326 hsync_pol = 327 cfg->v_fc_config.timings.hsync_level == OMAPDSS_SIG_ACTIVE_HIGH; 328 329 /* Set hsync, vsync and data-enable polarity */ 330 r = hdmi_read_reg(base, HDMI_CORE_FC_INVIDCONF); 331 r = FLD_MOD(r, vsync_pol, 6, 6); 332 r = FLD_MOD(r, hsync_pol, 5, 5); 333 r = FLD_MOD(r, cfg->data_enable_pol, 4, 4); 334 r = FLD_MOD(r, cfg->vblank_osc, 1, 1); 335 r = FLD_MOD(r, cfg->v_fc_config.timings.interlace, 0, 0); 336 hdmi_write_reg(base, HDMI_CORE_FC_INVIDCONF, r); 337 338 /* set x resolution */ 339 REG_FLD_MOD(base, HDMI_CORE_FC_INHACTIV1, 340 cfg->v_fc_config.timings.x_res >> 8, 4, 0); 341 REG_FLD_MOD(base, HDMI_CORE_FC_INHACTIV0, 342 cfg->v_fc_config.timings.x_res & 0xFF, 7, 0); 343 344 /* set y resolution */ 345 REG_FLD_MOD(base, HDMI_CORE_FC_INVACTIV1, 346 cfg->v_fc_config.timings.y_res >> 8, 4, 0); 347 REG_FLD_MOD(base, HDMI_CORE_FC_INVACTIV0, 348 cfg->v_fc_config.timings.y_res & 0xFF, 7, 0); 349 350 /* set horizontal blanking pixels */ 351 REG_FLD_MOD(base, HDMI_CORE_FC_INHBLANK1, cfg->hblank >> 8, 4, 0); 352 REG_FLD_MOD(base, HDMI_CORE_FC_INHBLANK0, cfg->hblank & 0xFF, 7, 0); 353 354 /* set vertial blanking pixels */ 355 REG_FLD_MOD(base, HDMI_CORE_FC_INVBLANK, cfg->vblank, 7, 0); 356 357 /* set horizontal sync offset */ 358 REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINDELAY1, 359 cfg->v_fc_config.timings.hfp >> 8, 4, 0); 360 REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINDELAY0, 361 cfg->v_fc_config.timings.hfp & 0xFF, 7, 0); 362 363 /* set vertical sync offset */ 364 REG_FLD_MOD(base, HDMI_CORE_FC_VSYNCINDELAY, 365 cfg->v_fc_config.timings.vfp, 7, 0); 366 367 /* set horizontal sync pulse width */ 368 REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINWIDTH1, 369 (cfg->v_fc_config.timings.hsw >> 8), 1, 0); 370 REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINWIDTH0, 371 cfg->v_fc_config.timings.hsw & 0xFF, 7, 0); 372 373 /* set vertical sync pulse width */ 374 REG_FLD_MOD(base, HDMI_CORE_FC_VSYNCINWIDTH, 375 cfg->v_fc_config.timings.vsw, 5, 0); 376 377 /* select DVI mode */ 378 REG_FLD_MOD(base, HDMI_CORE_FC_INVIDCONF, 379 cfg->v_fc_config.hdmi_dvi_mode, 3, 3); 380 } 381 382 static void hdmi_core_config_video_packetizer(struct hdmi_core_data *core) 383 { 384 void __iomem *base = core->base; 385 int clr_depth = 0; /* 24 bit color depth */ 386 387 /* COLOR_DEPTH */ 388 REG_FLD_MOD(base, HDMI_CORE_VP_PR_CD, clr_depth, 7, 4); 389 /* BYPASS_EN */ 390 REG_FLD_MOD(base, HDMI_CORE_VP_CONF, clr_depth ? 0 : 1, 6, 6); 391 /* PP_EN */ 392 REG_FLD_MOD(base, HDMI_CORE_VP_CONF, clr_depth ? 1 : 0, 5, 5); 393 /* YCC422_EN */ 394 REG_FLD_MOD(base, HDMI_CORE_VP_CONF, 0, 3, 3); 395 /* PP_STUFFING */ 396 REG_FLD_MOD(base, HDMI_CORE_VP_STUFF, clr_depth ? 1 : 0, 1, 1); 397 /* YCC422_STUFFING */ 398 REG_FLD_MOD(base, HDMI_CORE_VP_STUFF, 1, 2, 2); 399 /* OUTPUT_SELECTOR */ 400 REG_FLD_MOD(base, HDMI_CORE_VP_CONF, clr_depth ? 0 : 2, 1, 0); 401 } 402 403 static void hdmi_core_config_csc(struct hdmi_core_data *core) 404 { 405 int clr_depth = 0; /* 24 bit color depth */ 406 407 /* CSC_COLORDEPTH */ 408 REG_FLD_MOD(core->base, HDMI_CORE_CSC_SCALE, clr_depth, 7, 4); 409 } 410 411 static void hdmi_core_config_video_sampler(struct hdmi_core_data *core) 412 { 413 int video_mapping = 1; /* for 24 bit color depth */ 414 415 /* VIDEO_MAPPING */ 416 REG_FLD_MOD(core->base, HDMI_CORE_TX_INVID0, video_mapping, 4, 0); 417 } 418 419 static void hdmi_core_write_avi_infoframe(struct hdmi_core_data *core, 420 struct hdmi_avi_infoframe *frame) 421 { 422 void __iomem *base = core->base; 423 u8 data[HDMI_INFOFRAME_SIZE(AVI)]; 424 u8 *ptr; 425 unsigned y, a, b, s; 426 unsigned c, m, r; 427 unsigned itc, ec, q, sc; 428 unsigned vic; 429 unsigned yq, cn, pr; 430 431 hdmi_avi_infoframe_pack(frame, data, sizeof(data)); 432 433 print_hex_dump_debug("AVI: ", DUMP_PREFIX_NONE, 16, 1, data, 434 HDMI_INFOFRAME_SIZE(AVI), false); 435 436 ptr = data + HDMI_INFOFRAME_HEADER_SIZE; 437 438 y = (ptr[0] >> 5) & 0x3; 439 a = (ptr[0] >> 4) & 0x1; 440 b = (ptr[0] >> 2) & 0x3; 441 s = (ptr[0] >> 0) & 0x3; 442 443 c = (ptr[1] >> 6) & 0x3; 444 m = (ptr[1] >> 4) & 0x3; 445 r = (ptr[1] >> 0) & 0xf; 446 447 itc = (ptr[2] >> 7) & 0x1; 448 ec = (ptr[2] >> 4) & 0x7; 449 q = (ptr[2] >> 2) & 0x3; 450 sc = (ptr[2] >> 0) & 0x3; 451 452 vic = ptr[3]; 453 454 yq = (ptr[4] >> 6) & 0x3; 455 cn = (ptr[4] >> 4) & 0x3; 456 pr = (ptr[4] >> 0) & 0xf; 457 458 hdmi_write_reg(base, HDMI_CORE_FC_AVICONF0, 459 (a << 6) | (s << 4) | (b << 2) | (y << 0)); 460 461 hdmi_write_reg(base, HDMI_CORE_FC_AVICONF1, 462 (c << 6) | (m << 4) | (r << 0)); 463 464 hdmi_write_reg(base, HDMI_CORE_FC_AVICONF2, 465 (itc << 7) | (ec << 4) | (q << 2) | (sc << 0)); 466 467 hdmi_write_reg(base, HDMI_CORE_FC_AVIVID, vic); 468 469 hdmi_write_reg(base, HDMI_CORE_FC_AVICONF3, 470 (yq << 2) | (cn << 0)); 471 472 REG_FLD_MOD(base, HDMI_CORE_FC_PRCONF, pr, 3, 0); 473 } 474 475 static void hdmi_core_csc_config(struct hdmi_core_data *core, 476 struct csc_table csc_coeff) 477 { 478 void __iomem *base = core->base; 479 480 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A1_MSB, csc_coeff.a1 >> 8 , 6, 0); 481 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A1_LSB, csc_coeff.a1, 7, 0); 482 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A2_MSB, csc_coeff.a2 >> 8, 6, 0); 483 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A2_LSB, csc_coeff.a2, 7, 0); 484 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A3_MSB, csc_coeff.a3 >> 8, 6, 0); 485 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A3_LSB, csc_coeff.a3, 7, 0); 486 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A4_MSB, csc_coeff.a4 >> 8, 6, 0); 487 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A4_LSB, csc_coeff.a4, 7, 0); 488 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B1_MSB, csc_coeff.b1 >> 8, 6, 0); 489 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B1_LSB, csc_coeff.b1, 7, 0); 490 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B2_MSB, csc_coeff.b2 >> 8, 6, 0); 491 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B2_LSB, csc_coeff.b2, 7, 0); 492 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B3_MSB, csc_coeff.b3 >> 8, 6, 0); 493 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B3_LSB, csc_coeff.b3, 7, 0); 494 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B4_MSB, csc_coeff.b4 >> 8, 6, 0); 495 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B4_LSB, csc_coeff.b4, 7, 0); 496 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C1_MSB, csc_coeff.c1 >> 8, 6, 0); 497 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C1_LSB, csc_coeff.c1, 7, 0); 498 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C2_MSB, csc_coeff.c2 >> 8, 6, 0); 499 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C2_LSB, csc_coeff.c2, 7, 0); 500 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C3_MSB, csc_coeff.c3 >> 8, 6, 0); 501 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C3_LSB, csc_coeff.c3, 7, 0); 502 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C4_MSB, csc_coeff.c4 >> 8, 6, 0); 503 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C4_LSB, csc_coeff.c4, 7, 0); 504 505 REG_FLD_MOD(base, HDMI_CORE_MC_FLOWCTRL, 0x1, 0, 0); 506 } 507 508 static void hdmi_core_configure_range(struct hdmi_core_data *core) 509 { 510 struct csc_table csc_coeff = { 0 }; 511 512 /* support limited range with 24 bit color depth for now */ 513 csc_coeff = csc_table_deepcolor[0]; 514 515 hdmi_core_csc_config(core, csc_coeff); 516 } 517 518 static void hdmi_core_enable_video_path(struct hdmi_core_data *core) 519 { 520 void __iomem *base = core->base; 521 522 DSSDBG("hdmi_core_enable_video_path\n"); 523 524 REG_FLD_MOD(base, HDMI_CORE_FC_CTRLDUR, 0x0C, 7, 0); 525 REG_FLD_MOD(base, HDMI_CORE_FC_EXCTRLDUR, 0x20, 7, 0); 526 REG_FLD_MOD(base, HDMI_CORE_FC_EXCTRLSPAC, 0x01, 7, 0); 527 REG_FLD_MOD(base, HDMI_CORE_FC_CH0PREAM, 0x0B, 7, 0); 528 REG_FLD_MOD(base, HDMI_CORE_FC_CH1PREAM, 0x16, 5, 0); 529 REG_FLD_MOD(base, HDMI_CORE_FC_CH2PREAM, 0x21, 5, 0); 530 REG_FLD_MOD(base, HDMI_CORE_MC_CLKDIS, 0x00, 0, 0); 531 REG_FLD_MOD(base, HDMI_CORE_MC_CLKDIS, 0x00, 1, 1); 532 } 533 534 static void hdmi_core_mask_interrupts(struct hdmi_core_data *core) 535 { 536 void __iomem *base = core->base; 537 538 /* Master IRQ mask */ 539 REG_FLD_MOD(base, HDMI_CORE_IH_MUTE, 0x3, 1, 0); 540 541 /* Mask all the interrupts in HDMI core */ 542 543 REG_FLD_MOD(base, HDMI_CORE_VP_MASK, 0xff, 7, 0); 544 REG_FLD_MOD(base, HDMI_CORE_FC_MASK0, 0xe7, 7, 0); 545 REG_FLD_MOD(base, HDMI_CORE_FC_MASK1, 0xfb, 7, 0); 546 REG_FLD_MOD(base, HDMI_CORE_FC_MASK2, 0x3, 1, 0); 547 548 REG_FLD_MOD(base, HDMI_CORE_AUD_INT, 0x3, 3, 2); 549 REG_FLD_MOD(base, HDMI_CORE_AUD_GP_MASK, 0x3, 1, 0); 550 551 REG_FLD_MOD(base, HDMI_CORE_CEC_MASK, 0x7f, 6, 0); 552 553 REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 6, 6); 554 REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 2, 2); 555 REG_FLD_MOD(base, HDMI_CORE_I2CM_INT, 0x1, 2, 2); 556 557 REG_FLD_MOD(base, HDMI_CORE_PHY_MASK0, 0xf3, 7, 0); 558 559 REG_FLD_MOD(base, HDMI_CORE_IH_PHY_STAT0, 0xff, 7, 0); 560 561 /* Clear all the current interrupt bits */ 562 563 REG_FLD_MOD(base, HDMI_CORE_IH_VP_STAT0, 0xff, 7, 0); 564 REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT0, 0xe7, 7, 0); 565 REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT1, 0xfb, 7, 0); 566 REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT2, 0x3, 1, 0); 567 568 REG_FLD_MOD(base, HDMI_CORE_IH_AS_STAT0, 0x7, 2, 0); 569 570 REG_FLD_MOD(base, HDMI_CORE_IH_CEC_STAT0, 0x7f, 6, 0); 571 572 REG_FLD_MOD(base, HDMI_CORE_IH_I2CM_STAT0, 0x3, 1, 0); 573 574 REG_FLD_MOD(base, HDMI_CORE_IH_PHY_STAT0, 0xff, 7, 0); 575 } 576 577 static void hdmi_core_enable_interrupts(struct hdmi_core_data *core) 578 { 579 /* Unmute interrupts */ 580 REG_FLD_MOD(core->base, HDMI_CORE_IH_MUTE, 0x0, 1, 0); 581 } 582 583 int hdmi5_core_handle_irqs(struct hdmi_core_data *core) 584 { 585 void __iomem *base = core->base; 586 587 REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT0, 0xff, 7, 0); 588 REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT1, 0xff, 7, 0); 589 REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT2, 0xff, 7, 0); 590 REG_FLD_MOD(base, HDMI_CORE_IH_AS_STAT0, 0xff, 7, 0); 591 REG_FLD_MOD(base, HDMI_CORE_IH_PHY_STAT0, 0xff, 7, 0); 592 REG_FLD_MOD(base, HDMI_CORE_IH_I2CM_STAT0, 0xff, 7, 0); 593 REG_FLD_MOD(base, HDMI_CORE_IH_CEC_STAT0, 0xff, 7, 0); 594 REG_FLD_MOD(base, HDMI_CORE_IH_VP_STAT0, 0xff, 7, 0); 595 REG_FLD_MOD(base, HDMI_CORE_IH_I2CMPHY_STAT0, 0xff, 7, 0); 596 597 return 0; 598 } 599 600 void hdmi5_configure(struct hdmi_core_data *core, struct hdmi_wp_data *wp, 601 struct hdmi_config *cfg) 602 { 603 struct omap_video_timings video_timing; 604 struct hdmi_video_format video_format; 605 struct hdmi_core_vid_config v_core_cfg; 606 607 hdmi_core_mask_interrupts(core); 608 609 hdmi_core_init(&v_core_cfg, cfg); 610 611 hdmi_wp_init_vid_fmt_timings(&video_format, &video_timing, cfg); 612 613 hdmi_wp_video_config_timing(wp, &video_timing); 614 615 /* video config */ 616 video_format.packing_mode = HDMI_PACK_24b_RGB_YUV444_YUV422; 617 618 hdmi_wp_video_config_format(wp, &video_format); 619 620 hdmi_wp_video_config_interface(wp, &video_timing); 621 622 /* support limited range with 24 bit color depth for now */ 623 hdmi_core_configure_range(core); 624 cfg->infoframe.quantization_range = HDMI_QUANTIZATION_RANGE_LIMITED; 625 626 /* 627 * configure core video part, set software reset in the core 628 */ 629 v_core_cfg.packet_mode = HDMI_PACKETMODE24BITPERPIXEL; 630 631 hdmi_core_video_config(core, &v_core_cfg); 632 633 hdmi_core_config_video_packetizer(core); 634 hdmi_core_config_csc(core); 635 hdmi_core_config_video_sampler(core); 636 637 if (cfg->hdmi_dvi_mode == HDMI_HDMI) 638 hdmi_core_write_avi_infoframe(core, &cfg->infoframe); 639 640 hdmi_core_enable_video_path(core); 641 642 hdmi_core_enable_interrupts(core); 643 } 644 645 static void hdmi5_core_audio_config(struct hdmi_core_data *core, 646 struct hdmi_core_audio_config *cfg) 647 { 648 void __iomem *base = core->base; 649 u8 val; 650 651 /* Mute audio before configuring */ 652 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCONF, 0xf, 7, 4); 653 654 /* Set the N parameter */ 655 REG_FLD_MOD(base, HDMI_CORE_AUD_N1, cfg->n, 7, 0); 656 REG_FLD_MOD(base, HDMI_CORE_AUD_N2, cfg->n >> 8, 7, 0); 657 REG_FLD_MOD(base, HDMI_CORE_AUD_N3, cfg->n >> 16, 3, 0); 658 659 /* 660 * CTS manual mode. Automatic mode is not supported when using audio 661 * parallel interface. 662 */ 663 REG_FLD_MOD(base, HDMI_CORE_AUD_CTS3, 1, 4, 4); 664 REG_FLD_MOD(base, HDMI_CORE_AUD_CTS1, cfg->cts, 7, 0); 665 REG_FLD_MOD(base, HDMI_CORE_AUD_CTS2, cfg->cts >> 8, 7, 0); 666 REG_FLD_MOD(base, HDMI_CORE_AUD_CTS3, cfg->cts >> 16, 3, 0); 667 668 /* Layout of Audio Sample Packets: 2-channel or multichannels */ 669 if (cfg->layout == HDMI_AUDIO_LAYOUT_2CH) 670 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCONF, 0, 0, 0); 671 else 672 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCONF, 1, 0, 0); 673 674 /* Configure IEC-609580 Validity bits */ 675 /* Channel 0 is valid */ 676 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, 0, 0, 0); 677 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, 0, 4, 4); 678 679 if (cfg->layout == HDMI_AUDIO_LAYOUT_2CH) 680 val = 1; 681 else 682 val = 0; 683 684 /* Channels 1, 2 setting */ 685 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 1, 1); 686 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 5, 5); 687 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 2, 2); 688 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 6, 6); 689 /* Channel 3 setting */ 690 if (cfg->layout == HDMI_AUDIO_LAYOUT_6CH) 691 val = 1; 692 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 3, 3); 693 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 7, 7); 694 695 /* Configure IEC-60958 User bits */ 696 /* TODO: should be set by user. */ 697 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSU, 0, 7, 0); 698 699 /* Configure IEC-60958 Channel Status word */ 700 /* CGMSA */ 701 val = cfg->iec60958_cfg->status[5] & IEC958_AES5_CON_CGMSA; 702 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(0), val, 5, 4); 703 704 /* Copyright */ 705 val = (cfg->iec60958_cfg->status[0] & 706 IEC958_AES0_CON_NOT_COPYRIGHT) >> 2; 707 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(0), val, 0, 0); 708 709 /* Category */ 710 hdmi_write_reg(base, HDMI_CORE_FC_AUDSCHNLS(1), 711 cfg->iec60958_cfg->status[1]); 712 713 /* PCM audio mode */ 714 val = (cfg->iec60958_cfg->status[0] & IEC958_AES0_CON_MODE) >> 6; 715 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(2), val, 6, 4); 716 717 /* Source number */ 718 val = cfg->iec60958_cfg->status[2] & IEC958_AES2_CON_SOURCE; 719 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(2), val, 3, 0); 720 721 /* Channel number right 0 */ 722 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(3), 2, 3, 0); 723 /* Channel number right 1*/ 724 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(3), 4, 7, 4); 725 /* Channel number right 2 */ 726 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(4), 6, 3, 0); 727 /* Channel number right 3*/ 728 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(4), 8, 7, 4); 729 /* Channel number left 0 */ 730 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(5), 1, 3, 0); 731 /* Channel number left 1*/ 732 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(5), 3, 7, 4); 733 /* Channel number left 2 */ 734 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(6), 5, 3, 0); 735 /* Channel number left 3*/ 736 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(6), 7, 7, 4); 737 738 /* Clock accuracy and sample rate */ 739 hdmi_write_reg(base, HDMI_CORE_FC_AUDSCHNLS(7), 740 cfg->iec60958_cfg->status[3]); 741 742 /* Original sample rate and word length */ 743 hdmi_write_reg(base, HDMI_CORE_FC_AUDSCHNLS(8), 744 cfg->iec60958_cfg->status[4]); 745 746 /* Enable FIFO empty and full interrupts */ 747 REG_FLD_MOD(base, HDMI_CORE_AUD_INT, 3, 3, 2); 748 749 /* Configure GPA */ 750 /* select HBR/SPDIF interfaces */ 751 if (cfg->layout == HDMI_AUDIO_LAYOUT_2CH) { 752 /* select HBR/SPDIF interfaces */ 753 REG_FLD_MOD(base, HDMI_CORE_AUD_CONF0, 0, 5, 5); 754 /* enable two channels in GPA */ 755 REG_FLD_MOD(base, HDMI_CORE_AUD_GP_CONF1, 3, 7, 0); 756 } else if (cfg->layout == HDMI_AUDIO_LAYOUT_6CH) { 757 /* select HBR/SPDIF interfaces */ 758 REG_FLD_MOD(base, HDMI_CORE_AUD_CONF0, 0, 5, 5); 759 /* enable six channels in GPA */ 760 REG_FLD_MOD(base, HDMI_CORE_AUD_GP_CONF1, 0x3F, 7, 0); 761 } else { 762 /* select HBR/SPDIF interfaces */ 763 REG_FLD_MOD(base, HDMI_CORE_AUD_CONF0, 0, 5, 5); 764 /* enable eight channels in GPA */ 765 REG_FLD_MOD(base, HDMI_CORE_AUD_GP_CONF1, 0xFF, 7, 0); 766 } 767 768 /* disable HBR */ 769 REG_FLD_MOD(base, HDMI_CORE_AUD_GP_CONF2, 0, 0, 0); 770 /* enable PCUV */ 771 REG_FLD_MOD(base, HDMI_CORE_AUD_GP_CONF2, 1, 1, 1); 772 /* enable GPA FIFO full and empty mask */ 773 REG_FLD_MOD(base, HDMI_CORE_AUD_GP_MASK, 3, 1, 0); 774 /* set polarity of GPA FIFO empty interrupts */ 775 REG_FLD_MOD(base, HDMI_CORE_AUD_GP_POL, 1, 0, 0); 776 777 /* unmute audio */ 778 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCONF, 0, 7, 4); 779 } 780 781 static void hdmi5_core_audio_infoframe_cfg(struct hdmi_core_data *core, 782 struct snd_cea_861_aud_if *info_aud) 783 { 784 void __iomem *base = core->base; 785 786 /* channel count and coding type fields in AUDICONF0 are swapped */ 787 hdmi_write_reg(base, HDMI_CORE_FC_AUDICONF0, 788 (info_aud->db1_ct_cc & CEA861_AUDIO_INFOFRAME_DB1CC) << 4 | 789 (info_aud->db1_ct_cc & CEA861_AUDIO_INFOFRAME_DB1CT) >> 4); 790 791 hdmi_write_reg(base, HDMI_CORE_FC_AUDICONF1, info_aud->db2_sf_ss); 792 hdmi_write_reg(base, HDMI_CORE_FC_AUDICONF2, info_aud->db4_ca); 793 hdmi_write_reg(base, HDMI_CORE_FC_AUDICONF3, 794 (info_aud->db5_dminh_lsv & CEA861_AUDIO_INFOFRAME_DB5_DM_INH) >> 3 | 795 (info_aud->db5_dminh_lsv & CEA861_AUDIO_INFOFRAME_DB5_LSV)); 796 } 797 798 int hdmi5_audio_config(struct hdmi_core_data *core, struct hdmi_wp_data *wp, 799 struct omap_dss_audio *audio, u32 pclk) 800 { 801 struct hdmi_audio_format audio_format; 802 struct hdmi_audio_dma audio_dma; 803 struct hdmi_core_audio_config core_cfg; 804 int err, n, cts, channel_count; 805 unsigned int fs_nr; 806 bool word_length_16b = false; 807 808 if (!audio || !audio->iec || !audio->cea || !core) 809 return -EINVAL; 810 811 core_cfg.iec60958_cfg = audio->iec; 812 813 if (!(audio->iec->status[4] & IEC958_AES4_CON_MAX_WORDLEN_24) && 814 (audio->iec->status[4] & IEC958_AES4_CON_WORDLEN_20_16)) 815 word_length_16b = true; 816 817 /* only 16-bit word length supported atm */ 818 if (!word_length_16b) 819 return -EINVAL; 820 821 switch (audio->iec->status[3] & IEC958_AES3_CON_FS) { 822 case IEC958_AES3_CON_FS_32000: 823 fs_nr = 32000; 824 break; 825 case IEC958_AES3_CON_FS_44100: 826 fs_nr = 44100; 827 break; 828 case IEC958_AES3_CON_FS_48000: 829 fs_nr = 48000; 830 break; 831 case IEC958_AES3_CON_FS_88200: 832 fs_nr = 88200; 833 break; 834 case IEC958_AES3_CON_FS_96000: 835 fs_nr = 96000; 836 break; 837 case IEC958_AES3_CON_FS_176400: 838 fs_nr = 176400; 839 break; 840 case IEC958_AES3_CON_FS_192000: 841 fs_nr = 192000; 842 break; 843 default: 844 return -EINVAL; 845 } 846 847 err = hdmi_compute_acr(pclk, fs_nr, &n, &cts); 848 core_cfg.n = n; 849 core_cfg.cts = cts; 850 851 /* Audio channels settings */ 852 channel_count = (audio->cea->db1_ct_cc & CEA861_AUDIO_INFOFRAME_DB1CC) 853 + 1; 854 855 if (channel_count == 2) 856 core_cfg.layout = HDMI_AUDIO_LAYOUT_2CH; 857 else if (channel_count == 6) 858 core_cfg.layout = HDMI_AUDIO_LAYOUT_6CH; 859 else 860 core_cfg.layout = HDMI_AUDIO_LAYOUT_8CH; 861 862 /* DMA settings */ 863 if (word_length_16b) 864 audio_dma.transfer_size = 0x10; 865 else 866 audio_dma.transfer_size = 0x20; 867 audio_dma.block_size = 0xC0; 868 audio_dma.mode = HDMI_AUDIO_TRANSF_DMA; 869 audio_dma.fifo_threshold = 0x20; /* in number of samples */ 870 871 /* audio FIFO format settings for 16-bit samples*/ 872 audio_format.samples_per_word = HDMI_AUDIO_ONEWORD_TWOSAMPLES; 873 audio_format.sample_size = HDMI_AUDIO_SAMPLE_16BITS; 874 audio_format.justification = HDMI_AUDIO_JUSTIFY_LEFT; 875 audio_format.sample_order = HDMI_AUDIO_SAMPLE_LEFT_FIRST; 876 877 /* only LPCM atm */ 878 audio_format.type = HDMI_AUDIO_TYPE_LPCM; 879 880 /* only allowed option */ 881 audio_format.sample_order = HDMI_AUDIO_SAMPLE_LEFT_FIRST; 882 883 /* disable start/stop signals of IEC 60958 blocks */ 884 audio_format.en_sig_blk_strt_end = HDMI_AUDIO_BLOCK_SIG_STARTEND_ON; 885 886 /* configure DMA and audio FIFO format*/ 887 hdmi_wp_audio_config_dma(wp, &audio_dma); 888 hdmi_wp_audio_config_format(wp, &audio_format); 889 890 /* configure the core */ 891 hdmi5_core_audio_config(core, &core_cfg); 892 893 /* configure CEA 861 audio infoframe */ 894 hdmi5_core_audio_infoframe_cfg(core, audio->cea); 895 896 return 0; 897 } 898 899 int hdmi5_core_init(struct platform_device *pdev, struct hdmi_core_data *core) 900 { 901 struct resource *res; 902 903 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "core"); 904 if (!res) { 905 DSSERR("can't get CORE IORESOURCE_MEM HDMI\n"); 906 return -EINVAL; 907 } 908 909 core->base = devm_ioremap_resource(&pdev->dev, res); 910 if (IS_ERR(core->base)) { 911 DSSERR("can't ioremap HDMI core\n"); 912 return PTR_ERR(core->base); 913 } 914 915 return 0; 916 } 917