1f76ee892STomi Valkeinen /* 2f76ee892STomi Valkeinen * linux/drivers/video/omap2/dss/dss_features.h 3f76ee892STomi Valkeinen * 4f76ee892STomi Valkeinen * Copyright (C) 2010 Texas Instruments 5f76ee892STomi Valkeinen * Author: Archit Taneja <archit@ti.com> 6f76ee892STomi Valkeinen * 7f76ee892STomi Valkeinen * This program is free software; you can redistribute it and/or modify it 8f76ee892STomi Valkeinen * under the terms of the GNU General Public License version 2 as published by 9f76ee892STomi Valkeinen * the Free Software Foundation. 10f76ee892STomi Valkeinen * 11f76ee892STomi Valkeinen * This program is distributed in the hope that it will be useful, but WITHOUT 12f76ee892STomi Valkeinen * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13f76ee892STomi Valkeinen * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14f76ee892STomi Valkeinen * more details. 15f76ee892STomi Valkeinen * 16f76ee892STomi Valkeinen * You should have received a copy of the GNU General Public License along with 17f76ee892STomi Valkeinen * this program. If not, see <http://www.gnu.org/licenses/>. 18f76ee892STomi Valkeinen */ 19f76ee892STomi Valkeinen 20f76ee892STomi Valkeinen #ifndef __OMAP2_DSS_FEATURES_H 21f76ee892STomi Valkeinen #define __OMAP2_DSS_FEATURES_H 22f76ee892STomi Valkeinen 23f76ee892STomi Valkeinen #define MAX_DSS_MANAGERS 4 24f76ee892STomi Valkeinen #define MAX_DSS_OVERLAYS 4 25f76ee892STomi Valkeinen #define MAX_DSS_LCD_MANAGERS 3 26f76ee892STomi Valkeinen #define MAX_NUM_DSI 2 27f76ee892STomi Valkeinen 28f76ee892STomi Valkeinen /* DSS has feature id */ 29f76ee892STomi Valkeinen enum dss_feat_id { 30f76ee892STomi Valkeinen FEAT_LCDENABLEPOL, 31f76ee892STomi Valkeinen FEAT_LCDENABLESIGNAL, 32f76ee892STomi Valkeinen FEAT_PCKFREEENABLE, 33f76ee892STomi Valkeinen FEAT_FUNCGATED, 34f76ee892STomi Valkeinen FEAT_MGR_LCD2, 35f76ee892STomi Valkeinen FEAT_MGR_LCD3, 36f76ee892STomi Valkeinen FEAT_LINEBUFFERSPLIT, 37f76ee892STomi Valkeinen FEAT_ROWREPEATENABLE, 38f76ee892STomi Valkeinen FEAT_RESIZECONF, 39f76ee892STomi Valkeinen /* Independent core clk divider */ 40f76ee892STomi Valkeinen FEAT_CORE_CLK_DIV, 41f76ee892STomi Valkeinen FEAT_LCD_CLK_SRC, 42f76ee892STomi Valkeinen /* DSI-PLL power command 0x3 is not working */ 43f76ee892STomi Valkeinen FEAT_DSI_PLL_PWR_BUG, 44f76ee892STomi Valkeinen FEAT_DSI_DCS_CMD_CONFIG_VC, 45f76ee892STomi Valkeinen FEAT_DSI_VC_OCP_WIDTH, 46f76ee892STomi Valkeinen FEAT_DSI_REVERSE_TXCLKESC, 47f76ee892STomi Valkeinen FEAT_DSI_GNQ, 48f76ee892STomi Valkeinen FEAT_DPI_USES_VDDS_DSI, 49f76ee892STomi Valkeinen FEAT_HDMI_CTS_SWMODE, 50f76ee892STomi Valkeinen FEAT_HDMI_AUDIO_USE_MCLK, 51f76ee892STomi Valkeinen FEAT_HANDLE_UV_SEPARATE, 52f76ee892STomi Valkeinen FEAT_ATTR2, 53f76ee892STomi Valkeinen FEAT_VENC_REQUIRES_TV_DAC_CLK, 54f76ee892STomi Valkeinen FEAT_CPR, 55f76ee892STomi Valkeinen FEAT_PRELOAD, 56f76ee892STomi Valkeinen FEAT_FIR_COEF_V, 57f76ee892STomi Valkeinen FEAT_ALPHA_FIXED_ZORDER, 58f76ee892STomi Valkeinen FEAT_ALPHA_FREE_ZORDER, 59f76ee892STomi Valkeinen FEAT_FIFO_MERGE, 60f76ee892STomi Valkeinen /* An unknown HW bug causing the normal FIFO thresholds not to work */ 61f76ee892STomi Valkeinen FEAT_OMAP3_DSI_FIFO_BUG, 62f76ee892STomi Valkeinen FEAT_BURST_2D, 63f76ee892STomi Valkeinen FEAT_DSI_PHY_DCC, 64f76ee892STomi Valkeinen FEAT_MFLAG, 65f76ee892STomi Valkeinen }; 66f76ee892STomi Valkeinen 67f76ee892STomi Valkeinen /* DSS register field id */ 68f76ee892STomi Valkeinen enum dss_feat_reg_field { 69f76ee892STomi Valkeinen FEAT_REG_FIRHINC, 70f76ee892STomi Valkeinen FEAT_REG_FIRVINC, 71f76ee892STomi Valkeinen FEAT_REG_FIFOHIGHTHRESHOLD, 72f76ee892STomi Valkeinen FEAT_REG_FIFOLOWTHRESHOLD, 73f76ee892STomi Valkeinen FEAT_REG_FIFOSIZE, 74f76ee892STomi Valkeinen FEAT_REG_HORIZONTALACCU, 75f76ee892STomi Valkeinen FEAT_REG_VERTICALACCU, 76f76ee892STomi Valkeinen FEAT_REG_DISPC_CLK_SWITCH, 77f76ee892STomi Valkeinen }; 78f76ee892STomi Valkeinen 79f76ee892STomi Valkeinen enum dss_range_param { 80f76ee892STomi Valkeinen FEAT_PARAM_DSS_FCK, 81f76ee892STomi Valkeinen FEAT_PARAM_DSS_PCD, 82f76ee892STomi Valkeinen FEAT_PARAM_DSIPLL_LPDIV, 83f76ee892STomi Valkeinen FEAT_PARAM_DSI_FCK, 84f76ee892STomi Valkeinen FEAT_PARAM_DOWNSCALE, 85f76ee892STomi Valkeinen FEAT_PARAM_LINEWIDTH, 86f76ee892STomi Valkeinen }; 87f76ee892STomi Valkeinen 88f76ee892STomi Valkeinen /* DSS Feature Functions */ 89f76ee892STomi Valkeinen unsigned long dss_feat_get_param_min(enum dss_range_param param); 90f76ee892STomi Valkeinen unsigned long dss_feat_get_param_max(enum dss_range_param param); 91f76ee892STomi Valkeinen enum omap_overlay_caps dss_feat_get_overlay_caps(enum omap_plane plane); 92f76ee892STomi Valkeinen bool dss_feat_color_mode_supported(enum omap_plane plane, 93f76ee892STomi Valkeinen enum omap_color_mode color_mode); 94f76ee892STomi Valkeinen const char *dss_feat_get_clk_source_name(enum omap_dss_clk_source id); 95f76ee892STomi Valkeinen 96f76ee892STomi Valkeinen u32 dss_feat_get_buffer_size_unit(void); /* in bytes */ 97f76ee892STomi Valkeinen u32 dss_feat_get_burst_size_unit(void); /* in bytes */ 98f76ee892STomi Valkeinen 99f76ee892STomi Valkeinen bool dss_feat_rotation_type_supported(enum omap_dss_rotation_type rot_type); 100f76ee892STomi Valkeinen 101f76ee892STomi Valkeinen bool dss_has_feature(enum dss_feat_id id); 102f76ee892STomi Valkeinen void dss_feat_get_reg_field(enum dss_feat_reg_field id, u8 *start, u8 *end); 103f76ee892STomi Valkeinen void dss_features_init(enum omapdss_version version); 104f76ee892STomi Valkeinen 105f76ee892STomi Valkeinen enum omap_display_type dss_feat_get_supported_displays(enum omap_channel channel); 106f76ee892STomi Valkeinen enum omap_dss_output_id dss_feat_get_supported_outputs(enum omap_channel channel); 107f76ee892STomi Valkeinen 108f76ee892STomi Valkeinen #endif 109