1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * linux/drivers/video/omap2/dss/dsi.c
4  *
5  * Copyright (C) 2009 Nokia Corporation
6  * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
7  */
8 
9 #define DSS_SUBSYS_NAME "DSI"
10 
11 #include <linux/kernel.h>
12 #include <linux/io.h>
13 #include <linux/clk.h>
14 #include <linux/device.h>
15 #include <linux/err.h>
16 #include <linux/interrupt.h>
17 #include <linux/delay.h>
18 #include <linux/mutex.h>
19 #include <linux/module.h>
20 #include <linux/semaphore.h>
21 #include <linux/seq_file.h>
22 #include <linux/platform_device.h>
23 #include <linux/regulator/consumer.h>
24 #include <linux/wait.h>
25 #include <linux/workqueue.h>
26 #include <linux/sched.h>
27 #include <linux/slab.h>
28 #include <linux/debugfs.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/of.h>
31 #include <linux/of_platform.h>
32 #include <linux/component.h>
33 
34 #include <video/omapfb_dss.h>
35 #include <video/mipi_display.h>
36 
37 #include "dss.h"
38 #include "dss_features.h"
39 
40 #define DSI_CATCH_MISSING_TE
41 
42 struct dsi_reg { u16 module; u16 idx; };
43 
44 #define DSI_REG(mod, idx)		((const struct dsi_reg) { mod, idx })
45 
46 /* DSI Protocol Engine */
47 
48 #define DSI_PROTO			0
49 #define DSI_PROTO_SZ			0x200
50 
51 #define DSI_REVISION			DSI_REG(DSI_PROTO, 0x0000)
52 #define DSI_SYSCONFIG			DSI_REG(DSI_PROTO, 0x0010)
53 #define DSI_SYSSTATUS			DSI_REG(DSI_PROTO, 0x0014)
54 #define DSI_IRQSTATUS			DSI_REG(DSI_PROTO, 0x0018)
55 #define DSI_IRQENABLE			DSI_REG(DSI_PROTO, 0x001C)
56 #define DSI_CTRL			DSI_REG(DSI_PROTO, 0x0040)
57 #define DSI_GNQ				DSI_REG(DSI_PROTO, 0x0044)
58 #define DSI_COMPLEXIO_CFG1		DSI_REG(DSI_PROTO, 0x0048)
59 #define DSI_COMPLEXIO_IRQ_STATUS	DSI_REG(DSI_PROTO, 0x004C)
60 #define DSI_COMPLEXIO_IRQ_ENABLE	DSI_REG(DSI_PROTO, 0x0050)
61 #define DSI_CLK_CTRL			DSI_REG(DSI_PROTO, 0x0054)
62 #define DSI_TIMING1			DSI_REG(DSI_PROTO, 0x0058)
63 #define DSI_TIMING2			DSI_REG(DSI_PROTO, 0x005C)
64 #define DSI_VM_TIMING1			DSI_REG(DSI_PROTO, 0x0060)
65 #define DSI_VM_TIMING2			DSI_REG(DSI_PROTO, 0x0064)
66 #define DSI_VM_TIMING3			DSI_REG(DSI_PROTO, 0x0068)
67 #define DSI_CLK_TIMING			DSI_REG(DSI_PROTO, 0x006C)
68 #define DSI_TX_FIFO_VC_SIZE		DSI_REG(DSI_PROTO, 0x0070)
69 #define DSI_RX_FIFO_VC_SIZE		DSI_REG(DSI_PROTO, 0x0074)
70 #define DSI_COMPLEXIO_CFG2		DSI_REG(DSI_PROTO, 0x0078)
71 #define DSI_RX_FIFO_VC_FULLNESS		DSI_REG(DSI_PROTO, 0x007C)
72 #define DSI_VM_TIMING4			DSI_REG(DSI_PROTO, 0x0080)
73 #define DSI_TX_FIFO_VC_EMPTINESS	DSI_REG(DSI_PROTO, 0x0084)
74 #define DSI_VM_TIMING5			DSI_REG(DSI_PROTO, 0x0088)
75 #define DSI_VM_TIMING6			DSI_REG(DSI_PROTO, 0x008C)
76 #define DSI_VM_TIMING7			DSI_REG(DSI_PROTO, 0x0090)
77 #define DSI_STOPCLK_TIMING		DSI_REG(DSI_PROTO, 0x0094)
78 #define DSI_VC_CTRL(n)			DSI_REG(DSI_PROTO, 0x0100 + (n * 0x20))
79 #define DSI_VC_TE(n)			DSI_REG(DSI_PROTO, 0x0104 + (n * 0x20))
80 #define DSI_VC_LONG_PACKET_HEADER(n)	DSI_REG(DSI_PROTO, 0x0108 + (n * 0x20))
81 #define DSI_VC_LONG_PACKET_PAYLOAD(n)	DSI_REG(DSI_PROTO, 0x010C + (n * 0x20))
82 #define DSI_VC_SHORT_PACKET_HEADER(n)	DSI_REG(DSI_PROTO, 0x0110 + (n * 0x20))
83 #define DSI_VC_IRQSTATUS(n)		DSI_REG(DSI_PROTO, 0x0118 + (n * 0x20))
84 #define DSI_VC_IRQENABLE(n)		DSI_REG(DSI_PROTO, 0x011C + (n * 0x20))
85 
86 /* DSIPHY_SCP */
87 
88 #define DSI_PHY				1
89 #define DSI_PHY_OFFSET			0x200
90 #define DSI_PHY_SZ			0x40
91 
92 #define DSI_DSIPHY_CFG0			DSI_REG(DSI_PHY, 0x0000)
93 #define DSI_DSIPHY_CFG1			DSI_REG(DSI_PHY, 0x0004)
94 #define DSI_DSIPHY_CFG2			DSI_REG(DSI_PHY, 0x0008)
95 #define DSI_DSIPHY_CFG5			DSI_REG(DSI_PHY, 0x0014)
96 #define DSI_DSIPHY_CFG10		DSI_REG(DSI_PHY, 0x0028)
97 
98 /* DSI_PLL_CTRL_SCP */
99 
100 #define DSI_PLL				2
101 #define DSI_PLL_OFFSET			0x300
102 #define DSI_PLL_SZ			0x20
103 
104 #define DSI_PLL_CONTROL			DSI_REG(DSI_PLL, 0x0000)
105 #define DSI_PLL_STATUS			DSI_REG(DSI_PLL, 0x0004)
106 #define DSI_PLL_GO			DSI_REG(DSI_PLL, 0x0008)
107 #define DSI_PLL_CONFIGURATION1		DSI_REG(DSI_PLL, 0x000C)
108 #define DSI_PLL_CONFIGURATION2		DSI_REG(DSI_PLL, 0x0010)
109 
110 #define REG_GET(dsidev, idx, start, end) \
111 	FLD_GET(dsi_read_reg(dsidev, idx), start, end)
112 
113 #define REG_FLD_MOD(dsidev, idx, val, start, end) \
114 	dsi_write_reg(dsidev, idx, FLD_MOD(dsi_read_reg(dsidev, idx), val, start, end))
115 
116 /* Global interrupts */
117 #define DSI_IRQ_VC0		(1 << 0)
118 #define DSI_IRQ_VC1		(1 << 1)
119 #define DSI_IRQ_VC2		(1 << 2)
120 #define DSI_IRQ_VC3		(1 << 3)
121 #define DSI_IRQ_WAKEUP		(1 << 4)
122 #define DSI_IRQ_RESYNC		(1 << 5)
123 #define DSI_IRQ_PLL_LOCK	(1 << 7)
124 #define DSI_IRQ_PLL_UNLOCK	(1 << 8)
125 #define DSI_IRQ_PLL_RECALL	(1 << 9)
126 #define DSI_IRQ_COMPLEXIO_ERR	(1 << 10)
127 #define DSI_IRQ_HS_TX_TIMEOUT	(1 << 14)
128 #define DSI_IRQ_LP_RX_TIMEOUT	(1 << 15)
129 #define DSI_IRQ_TE_TRIGGER	(1 << 16)
130 #define DSI_IRQ_ACK_TRIGGER	(1 << 17)
131 #define DSI_IRQ_SYNC_LOST	(1 << 18)
132 #define DSI_IRQ_LDO_POWER_GOOD	(1 << 19)
133 #define DSI_IRQ_TA_TIMEOUT	(1 << 20)
134 #define DSI_IRQ_ERROR_MASK \
135 	(DSI_IRQ_HS_TX_TIMEOUT | DSI_IRQ_LP_RX_TIMEOUT | DSI_IRQ_SYNC_LOST | \
136 	DSI_IRQ_TA_TIMEOUT)
137 #define DSI_IRQ_CHANNEL_MASK	0xf
138 
139 /* Virtual channel interrupts */
140 #define DSI_VC_IRQ_CS		(1 << 0)
141 #define DSI_VC_IRQ_ECC_CORR	(1 << 1)
142 #define DSI_VC_IRQ_PACKET_SENT	(1 << 2)
143 #define DSI_VC_IRQ_FIFO_TX_OVF	(1 << 3)
144 #define DSI_VC_IRQ_FIFO_RX_OVF	(1 << 4)
145 #define DSI_VC_IRQ_BTA		(1 << 5)
146 #define DSI_VC_IRQ_ECC_NO_CORR	(1 << 6)
147 #define DSI_VC_IRQ_FIFO_TX_UDF	(1 << 7)
148 #define DSI_VC_IRQ_PP_BUSY_CHANGE (1 << 8)
149 #define DSI_VC_IRQ_ERROR_MASK \
150 	(DSI_VC_IRQ_CS | DSI_VC_IRQ_ECC_CORR | DSI_VC_IRQ_FIFO_TX_OVF | \
151 	DSI_VC_IRQ_FIFO_RX_OVF | DSI_VC_IRQ_ECC_NO_CORR | \
152 	DSI_VC_IRQ_FIFO_TX_UDF)
153 
154 /* ComplexIO interrupts */
155 #define DSI_CIO_IRQ_ERRSYNCESC1		(1 << 0)
156 #define DSI_CIO_IRQ_ERRSYNCESC2		(1 << 1)
157 #define DSI_CIO_IRQ_ERRSYNCESC3		(1 << 2)
158 #define DSI_CIO_IRQ_ERRSYNCESC4		(1 << 3)
159 #define DSI_CIO_IRQ_ERRSYNCESC5		(1 << 4)
160 #define DSI_CIO_IRQ_ERRESC1		(1 << 5)
161 #define DSI_CIO_IRQ_ERRESC2		(1 << 6)
162 #define DSI_CIO_IRQ_ERRESC3		(1 << 7)
163 #define DSI_CIO_IRQ_ERRESC4		(1 << 8)
164 #define DSI_CIO_IRQ_ERRESC5		(1 << 9)
165 #define DSI_CIO_IRQ_ERRCONTROL1		(1 << 10)
166 #define DSI_CIO_IRQ_ERRCONTROL2		(1 << 11)
167 #define DSI_CIO_IRQ_ERRCONTROL3		(1 << 12)
168 #define DSI_CIO_IRQ_ERRCONTROL4		(1 << 13)
169 #define DSI_CIO_IRQ_ERRCONTROL5		(1 << 14)
170 #define DSI_CIO_IRQ_STATEULPS1		(1 << 15)
171 #define DSI_CIO_IRQ_STATEULPS2		(1 << 16)
172 #define DSI_CIO_IRQ_STATEULPS3		(1 << 17)
173 #define DSI_CIO_IRQ_STATEULPS4		(1 << 18)
174 #define DSI_CIO_IRQ_STATEULPS5		(1 << 19)
175 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_1	(1 << 20)
176 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_1	(1 << 21)
177 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_2	(1 << 22)
178 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_2	(1 << 23)
179 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_3	(1 << 24)
180 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_3	(1 << 25)
181 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_4	(1 << 26)
182 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_4	(1 << 27)
183 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_5	(1 << 28)
184 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_5	(1 << 29)
185 #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL0	(1 << 30)
186 #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL1	(1 << 31)
187 #define DSI_CIO_IRQ_ERROR_MASK \
188 	(DSI_CIO_IRQ_ERRSYNCESC1 | DSI_CIO_IRQ_ERRSYNCESC2 | \
189 	 DSI_CIO_IRQ_ERRSYNCESC3 | DSI_CIO_IRQ_ERRSYNCESC4 | \
190 	 DSI_CIO_IRQ_ERRSYNCESC5 | \
191 	 DSI_CIO_IRQ_ERRESC1 | DSI_CIO_IRQ_ERRESC2 | \
192 	 DSI_CIO_IRQ_ERRESC3 | DSI_CIO_IRQ_ERRESC4 | \
193 	 DSI_CIO_IRQ_ERRESC5 | \
194 	 DSI_CIO_IRQ_ERRCONTROL1 | DSI_CIO_IRQ_ERRCONTROL2 | \
195 	 DSI_CIO_IRQ_ERRCONTROL3 | DSI_CIO_IRQ_ERRCONTROL4 | \
196 	 DSI_CIO_IRQ_ERRCONTROL5 | \
197 	 DSI_CIO_IRQ_ERRCONTENTIONLP0_1 | DSI_CIO_IRQ_ERRCONTENTIONLP1_1 | \
198 	 DSI_CIO_IRQ_ERRCONTENTIONLP0_2 | DSI_CIO_IRQ_ERRCONTENTIONLP1_2 | \
199 	 DSI_CIO_IRQ_ERRCONTENTIONLP0_3 | DSI_CIO_IRQ_ERRCONTENTIONLP1_3 | \
200 	 DSI_CIO_IRQ_ERRCONTENTIONLP0_4 | DSI_CIO_IRQ_ERRCONTENTIONLP1_4 | \
201 	 DSI_CIO_IRQ_ERRCONTENTIONLP0_5 | DSI_CIO_IRQ_ERRCONTENTIONLP1_5)
202 
203 typedef void (*omap_dsi_isr_t) (void *arg, u32 mask);
204 
205 static int dsi_display_init_dispc(struct platform_device *dsidev,
206 	struct omap_overlay_manager *mgr);
207 static void dsi_display_uninit_dispc(struct platform_device *dsidev,
208 	struct omap_overlay_manager *mgr);
209 
210 static int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel);
211 
212 /* DSI PLL HSDIV indices */
213 #define HSDIV_DISPC	0
214 #define HSDIV_DSI	1
215 
216 #define DSI_MAX_NR_ISRS                2
217 #define DSI_MAX_NR_LANES	5
218 
219 enum dsi_lane_function {
220 	DSI_LANE_UNUSED	= 0,
221 	DSI_LANE_CLK,
222 	DSI_LANE_DATA1,
223 	DSI_LANE_DATA2,
224 	DSI_LANE_DATA3,
225 	DSI_LANE_DATA4,
226 };
227 
228 struct dsi_lane_config {
229 	enum dsi_lane_function function;
230 	u8 polarity;
231 };
232 
233 struct dsi_isr_data {
234 	omap_dsi_isr_t	isr;
235 	void		*arg;
236 	u32		mask;
237 };
238 
239 enum fifo_size {
240 	DSI_FIFO_SIZE_0		= 0,
241 	DSI_FIFO_SIZE_32	= 1,
242 	DSI_FIFO_SIZE_64	= 2,
243 	DSI_FIFO_SIZE_96	= 3,
244 	DSI_FIFO_SIZE_128	= 4,
245 };
246 
247 enum dsi_vc_source {
248 	DSI_VC_SOURCE_L4 = 0,
249 	DSI_VC_SOURCE_VP,
250 };
251 
252 struct dsi_irq_stats {
253 	unsigned long last_reset;
254 	unsigned irq_count;
255 	unsigned dsi_irqs[32];
256 	unsigned vc_irqs[4][32];
257 	unsigned cio_irqs[32];
258 };
259 
260 struct dsi_isr_tables {
261 	struct dsi_isr_data isr_table[DSI_MAX_NR_ISRS];
262 	struct dsi_isr_data isr_table_vc[4][DSI_MAX_NR_ISRS];
263 	struct dsi_isr_data isr_table_cio[DSI_MAX_NR_ISRS];
264 };
265 
266 struct dsi_clk_calc_ctx {
267 	struct platform_device *dsidev;
268 	struct dss_pll *pll;
269 
270 	/* inputs */
271 
272 	const struct omap_dss_dsi_config *config;
273 
274 	unsigned long req_pck_min, req_pck_nom, req_pck_max;
275 
276 	/* outputs */
277 
278 	struct dss_pll_clock_info dsi_cinfo;
279 	struct dispc_clock_info dispc_cinfo;
280 
281 	struct omap_video_timings dispc_vm;
282 	struct omap_dss_dsi_videomode_timings dsi_vm;
283 };
284 
285 struct dsi_lp_clock_info {
286 	unsigned long lp_clk;
287 	u16 lp_clk_div;
288 };
289 
290 struct dsi_data {
291 	struct platform_device *pdev;
292 	void __iomem *proto_base;
293 	void __iomem *phy_base;
294 	void __iomem *pll_base;
295 
296 	int module_id;
297 
298 	int irq;
299 
300 	bool is_enabled;
301 
302 	struct clk *dss_clk;
303 
304 	struct dispc_clock_info user_dispc_cinfo;
305 	struct dss_pll_clock_info user_dsi_cinfo;
306 
307 	struct dsi_lp_clock_info user_lp_cinfo;
308 	struct dsi_lp_clock_info current_lp_cinfo;
309 
310 	struct dss_pll pll;
311 
312 	bool vdds_dsi_enabled;
313 	struct regulator *vdds_dsi_reg;
314 
315 	struct {
316 		enum dsi_vc_source source;
317 		struct omap_dss_device *dssdev;
318 		enum fifo_size tx_fifo_size;
319 		enum fifo_size rx_fifo_size;
320 		int vc_id;
321 	} vc[4];
322 
323 	struct mutex lock;
324 	struct semaphore bus_lock;
325 
326 	spinlock_t irq_lock;
327 	struct dsi_isr_tables isr_tables;
328 	/* space for a copy used by the interrupt handler */
329 	struct dsi_isr_tables isr_tables_copy;
330 
331 	int update_channel;
332 #ifdef DSI_PERF_MEASURE
333 	unsigned update_bytes;
334 #endif
335 
336 	bool te_enabled;
337 	bool ulps_enabled;
338 
339 	void (*framedone_callback)(int, void *);
340 	void *framedone_data;
341 
342 	struct delayed_work framedone_timeout_work;
343 
344 #ifdef DSI_CATCH_MISSING_TE
345 	struct timer_list te_timer;
346 #endif
347 
348 	unsigned long cache_req_pck;
349 	unsigned long cache_clk_freq;
350 	struct dss_pll_clock_info cache_cinfo;
351 
352 	u32		errors;
353 	spinlock_t	errors_lock;
354 #ifdef DSI_PERF_MEASURE
355 	ktime_t perf_setup_time;
356 	ktime_t perf_start_time;
357 #endif
358 	int debug_read;
359 	int debug_write;
360 
361 #ifdef CONFIG_FB_OMAP2_DSS_COLLECT_IRQ_STATS
362 	spinlock_t irq_stats_lock;
363 	struct dsi_irq_stats irq_stats;
364 #endif
365 
366 	unsigned num_lanes_supported;
367 	unsigned line_buffer_size;
368 
369 	struct dsi_lane_config lanes[DSI_MAX_NR_LANES];
370 	unsigned num_lanes_used;
371 
372 	unsigned scp_clk_refcount;
373 
374 	struct dss_lcd_mgr_config mgr_config;
375 	struct omap_video_timings timings;
376 	enum omap_dss_dsi_pixel_format pix_fmt;
377 	enum omap_dss_dsi_mode mode;
378 	struct omap_dss_dsi_videomode_timings vm_timings;
379 
380 	struct omap_dss_device output;
381 };
382 
383 struct dsi_packet_sent_handler_data {
384 	struct platform_device *dsidev;
385 	struct completion *completion;
386 };
387 
388 struct dsi_module_id_data {
389 	u32 address;
390 	int id;
391 };
392 
393 static const struct of_device_id dsi_of_match[];
394 
395 #ifdef DSI_PERF_MEASURE
396 static bool dsi_perf;
397 module_param(dsi_perf, bool, 0644);
398 #endif
399 
400 static inline struct dsi_data *dsi_get_dsidrv_data(struct platform_device *dsidev)
401 {
402 	return platform_get_drvdata(dsidev);
403 }
404 
405 static inline struct platform_device *dsi_get_dsidev_from_dssdev(struct omap_dss_device *dssdev)
406 {
407 	return to_platform_device(dssdev->dev);
408 }
409 
410 static struct platform_device *dsi_get_dsidev_from_id(int module)
411 {
412 	struct omap_dss_device *out;
413 	enum omap_dss_output_id	id;
414 
415 	switch (module) {
416 	case 0:
417 		id = OMAP_DSS_OUTPUT_DSI1;
418 		break;
419 	case 1:
420 		id = OMAP_DSS_OUTPUT_DSI2;
421 		break;
422 	default:
423 		return NULL;
424 	}
425 
426 	out = omap_dss_get_output(id);
427 
428 	return out ? to_platform_device(out->dev) : NULL;
429 }
430 
431 static inline void dsi_write_reg(struct platform_device *dsidev,
432 		const struct dsi_reg idx, u32 val)
433 {
434 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
435 	void __iomem *base;
436 
437 	switch(idx.module) {
438 		case DSI_PROTO: base = dsi->proto_base; break;
439 		case DSI_PHY: base = dsi->phy_base; break;
440 		case DSI_PLL: base = dsi->pll_base; break;
441 		default: return;
442 	}
443 
444 	__raw_writel(val, base + idx.idx);
445 }
446 
447 static inline u32 dsi_read_reg(struct platform_device *dsidev,
448 		const struct dsi_reg idx)
449 {
450 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
451 	void __iomem *base;
452 
453 	switch(idx.module) {
454 		case DSI_PROTO: base = dsi->proto_base; break;
455 		case DSI_PHY: base = dsi->phy_base; break;
456 		case DSI_PLL: base = dsi->pll_base; break;
457 		default: return 0;
458 	}
459 
460 	return __raw_readl(base + idx.idx);
461 }
462 
463 static void dsi_bus_lock(struct omap_dss_device *dssdev)
464 {
465 	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
466 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
467 
468 	down(&dsi->bus_lock);
469 }
470 
471 static void dsi_bus_unlock(struct omap_dss_device *dssdev)
472 {
473 	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
474 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
475 
476 	up(&dsi->bus_lock);
477 }
478 
479 static bool dsi_bus_is_locked(struct platform_device *dsidev)
480 {
481 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
482 
483 	return dsi->bus_lock.count == 0;
484 }
485 
486 static void dsi_completion_handler(void *data, u32 mask)
487 {
488 	complete((struct completion *)data);
489 }
490 
491 static inline int wait_for_bit_change(struct platform_device *dsidev,
492 		const struct dsi_reg idx, int bitnum, int value)
493 {
494 	unsigned long timeout;
495 	ktime_t wait;
496 	int t;
497 
498 	/* first busyloop to see if the bit changes right away */
499 	t = 100;
500 	while (t-- > 0) {
501 		if (REG_GET(dsidev, idx, bitnum, bitnum) == value)
502 			return value;
503 	}
504 
505 	/* then loop for 500ms, sleeping for 1ms in between */
506 	timeout = jiffies + msecs_to_jiffies(500);
507 	while (time_before(jiffies, timeout)) {
508 		if (REG_GET(dsidev, idx, bitnum, bitnum) == value)
509 			return value;
510 
511 		wait = ns_to_ktime(1000 * 1000);
512 		set_current_state(TASK_UNINTERRUPTIBLE);
513 		schedule_hrtimeout(&wait, HRTIMER_MODE_REL);
514 	}
515 
516 	return !value;
517 }
518 
519 u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt)
520 {
521 	switch (fmt) {
522 	case OMAP_DSS_DSI_FMT_RGB888:
523 	case OMAP_DSS_DSI_FMT_RGB666:
524 		return 24;
525 	case OMAP_DSS_DSI_FMT_RGB666_PACKED:
526 		return 18;
527 	case OMAP_DSS_DSI_FMT_RGB565:
528 		return 16;
529 	default:
530 		BUG();
531 		return 0;
532 	}
533 }
534 
535 #ifdef DSI_PERF_MEASURE
536 static void dsi_perf_mark_setup(struct platform_device *dsidev)
537 {
538 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
539 	dsi->perf_setup_time = ktime_get();
540 }
541 
542 static void dsi_perf_mark_start(struct platform_device *dsidev)
543 {
544 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
545 	dsi->perf_start_time = ktime_get();
546 }
547 
548 static void dsi_perf_show(struct platform_device *dsidev, const char *name)
549 {
550 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
551 	ktime_t t, setup_time, trans_time;
552 	u32 total_bytes;
553 	u32 setup_us, trans_us, total_us;
554 
555 	if (!dsi_perf)
556 		return;
557 
558 	t = ktime_get();
559 
560 	setup_time = ktime_sub(dsi->perf_start_time, dsi->perf_setup_time);
561 	setup_us = (u32)ktime_to_us(setup_time);
562 	if (setup_us == 0)
563 		setup_us = 1;
564 
565 	trans_time = ktime_sub(t, dsi->perf_start_time);
566 	trans_us = (u32)ktime_to_us(trans_time);
567 	if (trans_us == 0)
568 		trans_us = 1;
569 
570 	total_us = setup_us + trans_us;
571 
572 	total_bytes = dsi->update_bytes;
573 
574 	printk(KERN_INFO "DSI(%s): %u us + %u us = %u us (%uHz), "
575 			"%u bytes, %u kbytes/sec\n",
576 			name,
577 			setup_us,
578 			trans_us,
579 			total_us,
580 			1000*1000 / total_us,
581 			total_bytes,
582 			total_bytes * 1000 / total_us);
583 }
584 #else
585 static inline void dsi_perf_mark_setup(struct platform_device *dsidev)
586 {
587 }
588 
589 static inline void dsi_perf_mark_start(struct platform_device *dsidev)
590 {
591 }
592 
593 static inline void dsi_perf_show(struct platform_device *dsidev,
594 		const char *name)
595 {
596 }
597 #endif
598 
599 static int verbose_irq;
600 
601 static void print_irq_status(u32 status)
602 {
603 	if (status == 0)
604 		return;
605 
606 	if (!verbose_irq && (status & ~DSI_IRQ_CHANNEL_MASK) == 0)
607 		return;
608 
609 #define PIS(x) (status & DSI_IRQ_##x) ? (#x " ") : ""
610 
611 	pr_debug("DSI IRQ: 0x%x: %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n",
612 		status,
613 		verbose_irq ? PIS(VC0) : "",
614 		verbose_irq ? PIS(VC1) : "",
615 		verbose_irq ? PIS(VC2) : "",
616 		verbose_irq ? PIS(VC3) : "",
617 		PIS(WAKEUP),
618 		PIS(RESYNC),
619 		PIS(PLL_LOCK),
620 		PIS(PLL_UNLOCK),
621 		PIS(PLL_RECALL),
622 		PIS(COMPLEXIO_ERR),
623 		PIS(HS_TX_TIMEOUT),
624 		PIS(LP_RX_TIMEOUT),
625 		PIS(TE_TRIGGER),
626 		PIS(ACK_TRIGGER),
627 		PIS(SYNC_LOST),
628 		PIS(LDO_POWER_GOOD),
629 		PIS(TA_TIMEOUT));
630 #undef PIS
631 }
632 
633 static void print_irq_status_vc(int channel, u32 status)
634 {
635 	if (status == 0)
636 		return;
637 
638 	if (!verbose_irq && (status & ~DSI_VC_IRQ_PACKET_SENT) == 0)
639 		return;
640 
641 #define PIS(x) (status & DSI_VC_IRQ_##x) ? (#x " ") : ""
642 
643 	pr_debug("DSI VC(%d) IRQ 0x%x: %s%s%s%s%s%s%s%s%s\n",
644 		channel,
645 		status,
646 		PIS(CS),
647 		PIS(ECC_CORR),
648 		PIS(ECC_NO_CORR),
649 		verbose_irq ? PIS(PACKET_SENT) : "",
650 		PIS(BTA),
651 		PIS(FIFO_TX_OVF),
652 		PIS(FIFO_RX_OVF),
653 		PIS(FIFO_TX_UDF),
654 		PIS(PP_BUSY_CHANGE));
655 #undef PIS
656 }
657 
658 static void print_irq_status_cio(u32 status)
659 {
660 	if (status == 0)
661 		return;
662 
663 #define PIS(x) (status & DSI_CIO_IRQ_##x) ? (#x " ") : ""
664 
665 	pr_debug("DSI CIO IRQ 0x%x: %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n",
666 		status,
667 		PIS(ERRSYNCESC1),
668 		PIS(ERRSYNCESC2),
669 		PIS(ERRSYNCESC3),
670 		PIS(ERRESC1),
671 		PIS(ERRESC2),
672 		PIS(ERRESC3),
673 		PIS(ERRCONTROL1),
674 		PIS(ERRCONTROL2),
675 		PIS(ERRCONTROL3),
676 		PIS(STATEULPS1),
677 		PIS(STATEULPS2),
678 		PIS(STATEULPS3),
679 		PIS(ERRCONTENTIONLP0_1),
680 		PIS(ERRCONTENTIONLP1_1),
681 		PIS(ERRCONTENTIONLP0_2),
682 		PIS(ERRCONTENTIONLP1_2),
683 		PIS(ERRCONTENTIONLP0_3),
684 		PIS(ERRCONTENTIONLP1_3),
685 		PIS(ULPSACTIVENOT_ALL0),
686 		PIS(ULPSACTIVENOT_ALL1));
687 #undef PIS
688 }
689 
690 #ifdef CONFIG_FB_OMAP2_DSS_COLLECT_IRQ_STATS
691 static void dsi_collect_irq_stats(struct platform_device *dsidev, u32 irqstatus,
692 		u32 *vcstatus, u32 ciostatus)
693 {
694 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
695 	int i;
696 
697 	spin_lock(&dsi->irq_stats_lock);
698 
699 	dsi->irq_stats.irq_count++;
700 	dss_collect_irq_stats(irqstatus, dsi->irq_stats.dsi_irqs);
701 
702 	for (i = 0; i < 4; ++i)
703 		dss_collect_irq_stats(vcstatus[i], dsi->irq_stats.vc_irqs[i]);
704 
705 	dss_collect_irq_stats(ciostatus, dsi->irq_stats.cio_irqs);
706 
707 	spin_unlock(&dsi->irq_stats_lock);
708 }
709 #else
710 #define dsi_collect_irq_stats(dsidev, irqstatus, vcstatus, ciostatus)
711 #endif
712 
713 static int debug_irq;
714 
715 static void dsi_handle_irq_errors(struct platform_device *dsidev, u32 irqstatus,
716 		u32 *vcstatus, u32 ciostatus)
717 {
718 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
719 	int i;
720 
721 	if (irqstatus & DSI_IRQ_ERROR_MASK) {
722 		DSSERR("DSI error, irqstatus %x\n", irqstatus);
723 		print_irq_status(irqstatus);
724 		spin_lock(&dsi->errors_lock);
725 		dsi->errors |= irqstatus & DSI_IRQ_ERROR_MASK;
726 		spin_unlock(&dsi->errors_lock);
727 	} else if (debug_irq) {
728 		print_irq_status(irqstatus);
729 	}
730 
731 	for (i = 0; i < 4; ++i) {
732 		if (vcstatus[i] & DSI_VC_IRQ_ERROR_MASK) {
733 			DSSERR("DSI VC(%d) error, vc irqstatus %x\n",
734 				       i, vcstatus[i]);
735 			print_irq_status_vc(i, vcstatus[i]);
736 		} else if (debug_irq) {
737 			print_irq_status_vc(i, vcstatus[i]);
738 		}
739 	}
740 
741 	if (ciostatus & DSI_CIO_IRQ_ERROR_MASK) {
742 		DSSERR("DSI CIO error, cio irqstatus %x\n", ciostatus);
743 		print_irq_status_cio(ciostatus);
744 	} else if (debug_irq) {
745 		print_irq_status_cio(ciostatus);
746 	}
747 }
748 
749 static void dsi_call_isrs(struct dsi_isr_data *isr_array,
750 		unsigned isr_array_size, u32 irqstatus)
751 {
752 	struct dsi_isr_data *isr_data;
753 	int i;
754 
755 	for (i = 0; i < isr_array_size; i++) {
756 		isr_data = &isr_array[i];
757 		if (isr_data->isr && isr_data->mask & irqstatus)
758 			isr_data->isr(isr_data->arg, irqstatus);
759 	}
760 }
761 
762 static void dsi_handle_isrs(struct dsi_isr_tables *isr_tables,
763 		u32 irqstatus, u32 *vcstatus, u32 ciostatus)
764 {
765 	int i;
766 
767 	dsi_call_isrs(isr_tables->isr_table,
768 			ARRAY_SIZE(isr_tables->isr_table),
769 			irqstatus);
770 
771 	for (i = 0; i < 4; ++i) {
772 		if (vcstatus[i] == 0)
773 			continue;
774 		dsi_call_isrs(isr_tables->isr_table_vc[i],
775 				ARRAY_SIZE(isr_tables->isr_table_vc[i]),
776 				vcstatus[i]);
777 	}
778 
779 	if (ciostatus != 0)
780 		dsi_call_isrs(isr_tables->isr_table_cio,
781 				ARRAY_SIZE(isr_tables->isr_table_cio),
782 				ciostatus);
783 }
784 
785 static irqreturn_t omap_dsi_irq_handler(int irq, void *arg)
786 {
787 	struct platform_device *dsidev;
788 	struct dsi_data *dsi;
789 	u32 irqstatus, vcstatus[4], ciostatus;
790 	int i;
791 
792 	dsidev = (struct platform_device *) arg;
793 	dsi = dsi_get_dsidrv_data(dsidev);
794 
795 	if (!dsi->is_enabled)
796 		return IRQ_NONE;
797 
798 	spin_lock(&dsi->irq_lock);
799 
800 	irqstatus = dsi_read_reg(dsidev, DSI_IRQSTATUS);
801 
802 	/* IRQ is not for us */
803 	if (!irqstatus) {
804 		spin_unlock(&dsi->irq_lock);
805 		return IRQ_NONE;
806 	}
807 
808 	dsi_write_reg(dsidev, DSI_IRQSTATUS, irqstatus & ~DSI_IRQ_CHANNEL_MASK);
809 	/* flush posted write */
810 	dsi_read_reg(dsidev, DSI_IRQSTATUS);
811 
812 	for (i = 0; i < 4; ++i) {
813 		if ((irqstatus & (1 << i)) == 0) {
814 			vcstatus[i] = 0;
815 			continue;
816 		}
817 
818 		vcstatus[i] = dsi_read_reg(dsidev, DSI_VC_IRQSTATUS(i));
819 
820 		dsi_write_reg(dsidev, DSI_VC_IRQSTATUS(i), vcstatus[i]);
821 		/* flush posted write */
822 		dsi_read_reg(dsidev, DSI_VC_IRQSTATUS(i));
823 	}
824 
825 	if (irqstatus & DSI_IRQ_COMPLEXIO_ERR) {
826 		ciostatus = dsi_read_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS);
827 
828 		dsi_write_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS, ciostatus);
829 		/* flush posted write */
830 		dsi_read_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS);
831 	} else {
832 		ciostatus = 0;
833 	}
834 
835 #ifdef DSI_CATCH_MISSING_TE
836 	if (irqstatus & DSI_IRQ_TE_TRIGGER)
837 		del_timer(&dsi->te_timer);
838 #endif
839 
840 	/* make a copy and unlock, so that isrs can unregister
841 	 * themselves */
842 	memcpy(&dsi->isr_tables_copy, &dsi->isr_tables,
843 		sizeof(dsi->isr_tables));
844 
845 	spin_unlock(&dsi->irq_lock);
846 
847 	dsi_handle_isrs(&dsi->isr_tables_copy, irqstatus, vcstatus, ciostatus);
848 
849 	dsi_handle_irq_errors(dsidev, irqstatus, vcstatus, ciostatus);
850 
851 	dsi_collect_irq_stats(dsidev, irqstatus, vcstatus, ciostatus);
852 
853 	return IRQ_HANDLED;
854 }
855 
856 /* dsi->irq_lock has to be locked by the caller */
857 static void _omap_dsi_configure_irqs(struct platform_device *dsidev,
858 		struct dsi_isr_data *isr_array,
859 		unsigned isr_array_size, u32 default_mask,
860 		const struct dsi_reg enable_reg,
861 		const struct dsi_reg status_reg)
862 {
863 	struct dsi_isr_data *isr_data;
864 	u32 mask;
865 	u32 old_mask;
866 	int i;
867 
868 	mask = default_mask;
869 
870 	for (i = 0; i < isr_array_size; i++) {
871 		isr_data = &isr_array[i];
872 
873 		if (isr_data->isr == NULL)
874 			continue;
875 
876 		mask |= isr_data->mask;
877 	}
878 
879 	old_mask = dsi_read_reg(dsidev, enable_reg);
880 	/* clear the irqstatus for newly enabled irqs */
881 	dsi_write_reg(dsidev, status_reg, (mask ^ old_mask) & mask);
882 	dsi_write_reg(dsidev, enable_reg, mask);
883 
884 	/* flush posted writes */
885 	dsi_read_reg(dsidev, enable_reg);
886 	dsi_read_reg(dsidev, status_reg);
887 }
888 
889 /* dsi->irq_lock has to be locked by the caller */
890 static void _omap_dsi_set_irqs(struct platform_device *dsidev)
891 {
892 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
893 	u32 mask = DSI_IRQ_ERROR_MASK;
894 #ifdef DSI_CATCH_MISSING_TE
895 	mask |= DSI_IRQ_TE_TRIGGER;
896 #endif
897 	_omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table,
898 			ARRAY_SIZE(dsi->isr_tables.isr_table), mask,
899 			DSI_IRQENABLE, DSI_IRQSTATUS);
900 }
901 
902 /* dsi->irq_lock has to be locked by the caller */
903 static void _omap_dsi_set_irqs_vc(struct platform_device *dsidev, int vc)
904 {
905 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
906 
907 	_omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table_vc[vc],
908 			ARRAY_SIZE(dsi->isr_tables.isr_table_vc[vc]),
909 			DSI_VC_IRQ_ERROR_MASK,
910 			DSI_VC_IRQENABLE(vc), DSI_VC_IRQSTATUS(vc));
911 }
912 
913 /* dsi->irq_lock has to be locked by the caller */
914 static void _omap_dsi_set_irqs_cio(struct platform_device *dsidev)
915 {
916 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
917 
918 	_omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table_cio,
919 			ARRAY_SIZE(dsi->isr_tables.isr_table_cio),
920 			DSI_CIO_IRQ_ERROR_MASK,
921 			DSI_COMPLEXIO_IRQ_ENABLE, DSI_COMPLEXIO_IRQ_STATUS);
922 }
923 
924 static void _dsi_initialize_irq(struct platform_device *dsidev)
925 {
926 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
927 	unsigned long flags;
928 	int vc;
929 
930 	spin_lock_irqsave(&dsi->irq_lock, flags);
931 
932 	memset(&dsi->isr_tables, 0, sizeof(dsi->isr_tables));
933 
934 	_omap_dsi_set_irqs(dsidev);
935 	for (vc = 0; vc < 4; ++vc)
936 		_omap_dsi_set_irqs_vc(dsidev, vc);
937 	_omap_dsi_set_irqs_cio(dsidev);
938 
939 	spin_unlock_irqrestore(&dsi->irq_lock, flags);
940 }
941 
942 static int _dsi_register_isr(omap_dsi_isr_t isr, void *arg, u32 mask,
943 		struct dsi_isr_data *isr_array, unsigned isr_array_size)
944 {
945 	struct dsi_isr_data *isr_data;
946 	int free_idx;
947 	int i;
948 
949 	BUG_ON(isr == NULL);
950 
951 	/* check for duplicate entry and find a free slot */
952 	free_idx = -1;
953 	for (i = 0; i < isr_array_size; i++) {
954 		isr_data = &isr_array[i];
955 
956 		if (isr_data->isr == isr && isr_data->arg == arg &&
957 				isr_data->mask == mask) {
958 			return -EINVAL;
959 		}
960 
961 		if (isr_data->isr == NULL && free_idx == -1)
962 			free_idx = i;
963 	}
964 
965 	if (free_idx == -1)
966 		return -EBUSY;
967 
968 	isr_data = &isr_array[free_idx];
969 	isr_data->isr = isr;
970 	isr_data->arg = arg;
971 	isr_data->mask = mask;
972 
973 	return 0;
974 }
975 
976 static int _dsi_unregister_isr(omap_dsi_isr_t isr, void *arg, u32 mask,
977 		struct dsi_isr_data *isr_array, unsigned isr_array_size)
978 {
979 	struct dsi_isr_data *isr_data;
980 	int i;
981 
982 	for (i = 0; i < isr_array_size; i++) {
983 		isr_data = &isr_array[i];
984 		if (isr_data->isr != isr || isr_data->arg != arg ||
985 				isr_data->mask != mask)
986 			continue;
987 
988 		isr_data->isr = NULL;
989 		isr_data->arg = NULL;
990 		isr_data->mask = 0;
991 
992 		return 0;
993 	}
994 
995 	return -EINVAL;
996 }
997 
998 static int dsi_register_isr(struct platform_device *dsidev, omap_dsi_isr_t isr,
999 		void *arg, u32 mask)
1000 {
1001 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1002 	unsigned long flags;
1003 	int r;
1004 
1005 	spin_lock_irqsave(&dsi->irq_lock, flags);
1006 
1007 	r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table,
1008 			ARRAY_SIZE(dsi->isr_tables.isr_table));
1009 
1010 	if (r == 0)
1011 		_omap_dsi_set_irqs(dsidev);
1012 
1013 	spin_unlock_irqrestore(&dsi->irq_lock, flags);
1014 
1015 	return r;
1016 }
1017 
1018 static int dsi_unregister_isr(struct platform_device *dsidev,
1019 		omap_dsi_isr_t isr, void *arg, u32 mask)
1020 {
1021 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1022 	unsigned long flags;
1023 	int r;
1024 
1025 	spin_lock_irqsave(&dsi->irq_lock, flags);
1026 
1027 	r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table,
1028 			ARRAY_SIZE(dsi->isr_tables.isr_table));
1029 
1030 	if (r == 0)
1031 		_omap_dsi_set_irqs(dsidev);
1032 
1033 	spin_unlock_irqrestore(&dsi->irq_lock, flags);
1034 
1035 	return r;
1036 }
1037 
1038 static int dsi_register_isr_vc(struct platform_device *dsidev, int channel,
1039 		omap_dsi_isr_t isr, void *arg, u32 mask)
1040 {
1041 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1042 	unsigned long flags;
1043 	int r;
1044 
1045 	spin_lock_irqsave(&dsi->irq_lock, flags);
1046 
1047 	r = _dsi_register_isr(isr, arg, mask,
1048 			dsi->isr_tables.isr_table_vc[channel],
1049 			ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel]));
1050 
1051 	if (r == 0)
1052 		_omap_dsi_set_irqs_vc(dsidev, channel);
1053 
1054 	spin_unlock_irqrestore(&dsi->irq_lock, flags);
1055 
1056 	return r;
1057 }
1058 
1059 static int dsi_unregister_isr_vc(struct platform_device *dsidev, int channel,
1060 		omap_dsi_isr_t isr, void *arg, u32 mask)
1061 {
1062 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1063 	unsigned long flags;
1064 	int r;
1065 
1066 	spin_lock_irqsave(&dsi->irq_lock, flags);
1067 
1068 	r = _dsi_unregister_isr(isr, arg, mask,
1069 			dsi->isr_tables.isr_table_vc[channel],
1070 			ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel]));
1071 
1072 	if (r == 0)
1073 		_omap_dsi_set_irqs_vc(dsidev, channel);
1074 
1075 	spin_unlock_irqrestore(&dsi->irq_lock, flags);
1076 
1077 	return r;
1078 }
1079 
1080 static int dsi_register_isr_cio(struct platform_device *dsidev,
1081 		omap_dsi_isr_t isr, void *arg, u32 mask)
1082 {
1083 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1084 	unsigned long flags;
1085 	int r;
1086 
1087 	spin_lock_irqsave(&dsi->irq_lock, flags);
1088 
1089 	r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio,
1090 			ARRAY_SIZE(dsi->isr_tables.isr_table_cio));
1091 
1092 	if (r == 0)
1093 		_omap_dsi_set_irqs_cio(dsidev);
1094 
1095 	spin_unlock_irqrestore(&dsi->irq_lock, flags);
1096 
1097 	return r;
1098 }
1099 
1100 static int dsi_unregister_isr_cio(struct platform_device *dsidev,
1101 		omap_dsi_isr_t isr, void *arg, u32 mask)
1102 {
1103 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1104 	unsigned long flags;
1105 	int r;
1106 
1107 	spin_lock_irqsave(&dsi->irq_lock, flags);
1108 
1109 	r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio,
1110 			ARRAY_SIZE(dsi->isr_tables.isr_table_cio));
1111 
1112 	if (r == 0)
1113 		_omap_dsi_set_irqs_cio(dsidev);
1114 
1115 	spin_unlock_irqrestore(&dsi->irq_lock, flags);
1116 
1117 	return r;
1118 }
1119 
1120 static u32 dsi_get_errors(struct platform_device *dsidev)
1121 {
1122 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1123 	unsigned long flags;
1124 	u32 e;
1125 	spin_lock_irqsave(&dsi->errors_lock, flags);
1126 	e = dsi->errors;
1127 	dsi->errors = 0;
1128 	spin_unlock_irqrestore(&dsi->errors_lock, flags);
1129 	return e;
1130 }
1131 
1132 static int dsi_runtime_get(struct platform_device *dsidev)
1133 {
1134 	int r;
1135 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1136 
1137 	DSSDBG("dsi_runtime_get\n");
1138 
1139 	r = pm_runtime_resume_and_get(&dsi->pdev->dev);
1140 	if (WARN_ON(r < 0))
1141 		return r;
1142 	return 0;
1143 }
1144 
1145 static void dsi_runtime_put(struct platform_device *dsidev)
1146 {
1147 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1148 	int r;
1149 
1150 	DSSDBG("dsi_runtime_put\n");
1151 
1152 	r = pm_runtime_put_sync(&dsi->pdev->dev);
1153 	WARN_ON(r < 0 && r != -ENOSYS);
1154 }
1155 
1156 static int dsi_regulator_init(struct platform_device *dsidev)
1157 {
1158 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1159 	struct regulator *vdds_dsi;
1160 
1161 	if (dsi->vdds_dsi_reg != NULL)
1162 		return 0;
1163 
1164 	vdds_dsi = devm_regulator_get(&dsi->pdev->dev, "vdd");
1165 
1166 	if (IS_ERR(vdds_dsi)) {
1167 		if (PTR_ERR(vdds_dsi) != -EPROBE_DEFER)
1168 			DSSERR("can't get DSI VDD regulator\n");
1169 		return PTR_ERR(vdds_dsi);
1170 	}
1171 
1172 	dsi->vdds_dsi_reg = vdds_dsi;
1173 
1174 	return 0;
1175 }
1176 
1177 static void _dsi_print_reset_status(struct platform_device *dsidev)
1178 {
1179 	int b0, b1, b2;
1180 
1181 	/* A dummy read using the SCP interface to any DSIPHY register is
1182 	 * required after DSIPHY reset to complete the reset of the DSI complex
1183 	 * I/O. */
1184 	dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
1185 
1186 	if (dss_has_feature(FEAT_DSI_REVERSE_TXCLKESC)) {
1187 		b0 = 28;
1188 		b1 = 27;
1189 		b2 = 26;
1190 	} else {
1191 		b0 = 24;
1192 		b1 = 25;
1193 		b2 = 26;
1194 	}
1195 
1196 #define DSI_FLD_GET(fld, start, end)\
1197 	FLD_GET(dsi_read_reg(dsidev, DSI_##fld), start, end)
1198 
1199 	pr_debug("DSI resets: PLL (%d) CIO (%d) PHY (%x%x%x, %d, %d, %d)\n",
1200 		DSI_FLD_GET(PLL_STATUS, 0, 0),
1201 		DSI_FLD_GET(COMPLEXIO_CFG1, 29, 29),
1202 		DSI_FLD_GET(DSIPHY_CFG5, b0, b0),
1203 		DSI_FLD_GET(DSIPHY_CFG5, b1, b1),
1204 		DSI_FLD_GET(DSIPHY_CFG5, b2, b2),
1205 		DSI_FLD_GET(DSIPHY_CFG5, 29, 29),
1206 		DSI_FLD_GET(DSIPHY_CFG5, 30, 30),
1207 		DSI_FLD_GET(DSIPHY_CFG5, 31, 31));
1208 
1209 #undef DSI_FLD_GET
1210 }
1211 
1212 static inline int dsi_if_enable(struct platform_device *dsidev, bool enable)
1213 {
1214 	DSSDBG("dsi_if_enable(%d)\n", enable);
1215 
1216 	enable = enable ? 1 : 0;
1217 	REG_FLD_MOD(dsidev, DSI_CTRL, enable, 0, 0); /* IF_EN */
1218 
1219 	if (wait_for_bit_change(dsidev, DSI_CTRL, 0, enable) != enable) {
1220 			DSSERR("Failed to set dsi_if_enable to %d\n", enable);
1221 			return -EIO;
1222 	}
1223 
1224 	return 0;
1225 }
1226 
1227 static unsigned long dsi_get_pll_hsdiv_dispc_rate(struct platform_device *dsidev)
1228 {
1229 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1230 
1231 	return dsi->pll.cinfo.clkout[HSDIV_DISPC];
1232 }
1233 
1234 static unsigned long dsi_get_pll_hsdiv_dsi_rate(struct platform_device *dsidev)
1235 {
1236 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1237 
1238 	return dsi->pll.cinfo.clkout[HSDIV_DSI];
1239 }
1240 
1241 static unsigned long dsi_get_txbyteclkhs(struct platform_device *dsidev)
1242 {
1243 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1244 
1245 	return dsi->pll.cinfo.clkdco / 16;
1246 }
1247 
1248 static unsigned long dsi_fclk_rate(struct platform_device *dsidev)
1249 {
1250 	unsigned long r;
1251 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1252 
1253 	if (dss_get_dsi_clk_source(dsi->module_id) == OMAP_DSS_CLK_SRC_FCK) {
1254 		/* DSI FCLK source is DSS_CLK_FCK */
1255 		r = clk_get_rate(dsi->dss_clk);
1256 	} else {
1257 		/* DSI FCLK source is dsi_pll_hsdiv_dsi_clk */
1258 		r = dsi_get_pll_hsdiv_dsi_rate(dsidev);
1259 	}
1260 
1261 	return r;
1262 }
1263 
1264 static int dsi_lp_clock_calc(unsigned long dsi_fclk,
1265 		unsigned long lp_clk_min, unsigned long lp_clk_max,
1266 		struct dsi_lp_clock_info *lp_cinfo)
1267 {
1268 	unsigned lp_clk_div;
1269 	unsigned long lp_clk;
1270 
1271 	lp_clk_div = DIV_ROUND_UP(dsi_fclk, lp_clk_max * 2);
1272 	lp_clk = dsi_fclk / 2 / lp_clk_div;
1273 
1274 	if (lp_clk < lp_clk_min || lp_clk > lp_clk_max)
1275 		return -EINVAL;
1276 
1277 	lp_cinfo->lp_clk_div = lp_clk_div;
1278 	lp_cinfo->lp_clk = lp_clk;
1279 
1280 	return 0;
1281 }
1282 
1283 static int dsi_set_lp_clk_divisor(struct platform_device *dsidev)
1284 {
1285 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1286 	unsigned long dsi_fclk;
1287 	unsigned lp_clk_div;
1288 	unsigned long lp_clk;
1289 	unsigned lpdiv_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_LPDIV);
1290 
1291 
1292 	lp_clk_div = dsi->user_lp_cinfo.lp_clk_div;
1293 
1294 	if (lp_clk_div == 0 || lp_clk_div > lpdiv_max)
1295 		return -EINVAL;
1296 
1297 	dsi_fclk = dsi_fclk_rate(dsidev);
1298 
1299 	lp_clk = dsi_fclk / 2 / lp_clk_div;
1300 
1301 	DSSDBG("LP_CLK_DIV %u, LP_CLK %lu\n", lp_clk_div, lp_clk);
1302 	dsi->current_lp_cinfo.lp_clk = lp_clk;
1303 	dsi->current_lp_cinfo.lp_clk_div = lp_clk_div;
1304 
1305 	/* LP_CLK_DIVISOR */
1306 	REG_FLD_MOD(dsidev, DSI_CLK_CTRL, lp_clk_div, 12, 0);
1307 
1308 	/* LP_RX_SYNCHRO_ENABLE */
1309 	REG_FLD_MOD(dsidev, DSI_CLK_CTRL, dsi_fclk > 30000000 ? 1 : 0, 21, 21);
1310 
1311 	return 0;
1312 }
1313 
1314 static void dsi_enable_scp_clk(struct platform_device *dsidev)
1315 {
1316 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1317 
1318 	if (dsi->scp_clk_refcount++ == 0)
1319 		REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 14, 14); /* CIO_CLK_ICG */
1320 }
1321 
1322 static void dsi_disable_scp_clk(struct platform_device *dsidev)
1323 {
1324 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1325 
1326 	WARN_ON(dsi->scp_clk_refcount == 0);
1327 	if (--dsi->scp_clk_refcount == 0)
1328 		REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 14, 14); /* CIO_CLK_ICG */
1329 }
1330 
1331 enum dsi_pll_power_state {
1332 	DSI_PLL_POWER_OFF	= 0x0,
1333 	DSI_PLL_POWER_ON_HSCLK	= 0x1,
1334 	DSI_PLL_POWER_ON_ALL	= 0x2,
1335 	DSI_PLL_POWER_ON_DIV	= 0x3,
1336 };
1337 
1338 static int dsi_pll_power(struct platform_device *dsidev,
1339 		enum dsi_pll_power_state state)
1340 {
1341 	int t = 0;
1342 
1343 	/* DSI-PLL power command 0x3 is not working */
1344 	if (dss_has_feature(FEAT_DSI_PLL_PWR_BUG) &&
1345 			state == DSI_PLL_POWER_ON_DIV)
1346 		state = DSI_PLL_POWER_ON_ALL;
1347 
1348 	/* PLL_PWR_CMD */
1349 	REG_FLD_MOD(dsidev, DSI_CLK_CTRL, state, 31, 30);
1350 
1351 	/* PLL_PWR_STATUS */
1352 	while (FLD_GET(dsi_read_reg(dsidev, DSI_CLK_CTRL), 29, 28) != state) {
1353 		if (++t > 1000) {
1354 			DSSERR("Failed to set DSI PLL power mode to %d\n",
1355 					state);
1356 			return -ENODEV;
1357 		}
1358 		udelay(1);
1359 	}
1360 
1361 	return 0;
1362 }
1363 
1364 
1365 static void dsi_pll_calc_dsi_fck(struct dss_pll_clock_info *cinfo)
1366 {
1367 	unsigned long max_dsi_fck;
1368 
1369 	max_dsi_fck = dss_feat_get_param_max(FEAT_PARAM_DSI_FCK);
1370 
1371 	cinfo->mX[HSDIV_DSI] = DIV_ROUND_UP(cinfo->clkdco, max_dsi_fck);
1372 	cinfo->clkout[HSDIV_DSI] = cinfo->clkdco / cinfo->mX[HSDIV_DSI];
1373 }
1374 
1375 static int dsi_pll_enable(struct dss_pll *pll)
1376 {
1377 	struct dsi_data *dsi = container_of(pll, struct dsi_data, pll);
1378 	struct platform_device *dsidev = dsi->pdev;
1379 	int r = 0;
1380 
1381 	DSSDBG("PLL init\n");
1382 
1383 	r = dsi_regulator_init(dsidev);
1384 	if (r)
1385 		return r;
1386 
1387 	r = dsi_runtime_get(dsidev);
1388 	if (r)
1389 		return r;
1390 
1391 	/*
1392 	 * Note: SCP CLK is not required on OMAP3, but it is required on OMAP4.
1393 	 */
1394 	dsi_enable_scp_clk(dsidev);
1395 
1396 	if (!dsi->vdds_dsi_enabled) {
1397 		r = regulator_enable(dsi->vdds_dsi_reg);
1398 		if (r)
1399 			goto err0;
1400 		dsi->vdds_dsi_enabled = true;
1401 	}
1402 
1403 	/* XXX PLL does not come out of reset without this... */
1404 	dispc_pck_free_enable(1);
1405 
1406 	if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 0, 1) != 1) {
1407 		DSSERR("PLL not coming out of reset.\n");
1408 		r = -ENODEV;
1409 		dispc_pck_free_enable(0);
1410 		goto err1;
1411 	}
1412 
1413 	/* XXX ... but if left on, we get problems when planes do not
1414 	 * fill the whole display. No idea about this */
1415 	dispc_pck_free_enable(0);
1416 
1417 	r = dsi_pll_power(dsidev, DSI_PLL_POWER_ON_ALL);
1418 
1419 	if (r)
1420 		goto err1;
1421 
1422 	DSSDBG("PLL init done\n");
1423 
1424 	return 0;
1425 err1:
1426 	if (dsi->vdds_dsi_enabled) {
1427 		regulator_disable(dsi->vdds_dsi_reg);
1428 		dsi->vdds_dsi_enabled = false;
1429 	}
1430 err0:
1431 	dsi_disable_scp_clk(dsidev);
1432 	dsi_runtime_put(dsidev);
1433 	return r;
1434 }
1435 
1436 static void dsi_pll_uninit(struct platform_device *dsidev, bool disconnect_lanes)
1437 {
1438 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1439 
1440 	dsi_pll_power(dsidev, DSI_PLL_POWER_OFF);
1441 	if (disconnect_lanes) {
1442 		WARN_ON(!dsi->vdds_dsi_enabled);
1443 		regulator_disable(dsi->vdds_dsi_reg);
1444 		dsi->vdds_dsi_enabled = false;
1445 	}
1446 
1447 	dsi_disable_scp_clk(dsidev);
1448 	dsi_runtime_put(dsidev);
1449 
1450 	DSSDBG("PLL uninit done\n");
1451 }
1452 
1453 static void dsi_pll_disable(struct dss_pll *pll)
1454 {
1455 	struct dsi_data *dsi = container_of(pll, struct dsi_data, pll);
1456 	struct platform_device *dsidev = dsi->pdev;
1457 
1458 	dsi_pll_uninit(dsidev, true);
1459 }
1460 
1461 static void dsi_dump_dsidev_clocks(struct platform_device *dsidev,
1462 		struct seq_file *s)
1463 {
1464 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1465 	struct dss_pll_clock_info *cinfo = &dsi->pll.cinfo;
1466 	enum omap_dss_clk_source dispc_clk_src, dsi_clk_src;
1467 	int dsi_module = dsi->module_id;
1468 	struct dss_pll *pll = &dsi->pll;
1469 
1470 	dispc_clk_src = dss_get_dispc_clk_source();
1471 	dsi_clk_src = dss_get_dsi_clk_source(dsi_module);
1472 
1473 	if (dsi_runtime_get(dsidev))
1474 		return;
1475 
1476 	seq_printf(s,	"- DSI%d PLL -\n", dsi_module + 1);
1477 
1478 	seq_printf(s,	"dsi pll clkin\t%lu\n", clk_get_rate(pll->clkin));
1479 
1480 	seq_printf(s,	"Fint\t\t%-16lun %u\n", cinfo->fint, cinfo->n);
1481 
1482 	seq_printf(s,	"CLKIN4DDR\t%-16lum %u\n",
1483 			cinfo->clkdco, cinfo->m);
1484 
1485 	seq_printf(s,	"DSI_PLL_HSDIV_DISPC (%s)\t%-16lum_dispc %u\t(%s)\n",
1486 			dss_feat_get_clk_source_name(dsi_module == 0 ?
1487 				OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC :
1488 				OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC),
1489 			cinfo->clkout[HSDIV_DISPC],
1490 			cinfo->mX[HSDIV_DISPC],
1491 			dispc_clk_src == OMAP_DSS_CLK_SRC_FCK ?
1492 			"off" : "on");
1493 
1494 	seq_printf(s,	"DSI_PLL_HSDIV_DSI (%s)\t%-16lum_dsi %u\t(%s)\n",
1495 			dss_feat_get_clk_source_name(dsi_module == 0 ?
1496 				OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI :
1497 				OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI),
1498 			cinfo->clkout[HSDIV_DSI],
1499 			cinfo->mX[HSDIV_DSI],
1500 			dsi_clk_src == OMAP_DSS_CLK_SRC_FCK ?
1501 			"off" : "on");
1502 
1503 	seq_printf(s,	"- DSI%d -\n", dsi_module + 1);
1504 
1505 	seq_printf(s,	"dsi fclk source = %s (%s)\n",
1506 			dss_get_generic_clk_source_name(dsi_clk_src),
1507 			dss_feat_get_clk_source_name(dsi_clk_src));
1508 
1509 	seq_printf(s,	"DSI_FCLK\t%lu\n", dsi_fclk_rate(dsidev));
1510 
1511 	seq_printf(s,	"DDR_CLK\t\t%lu\n",
1512 			cinfo->clkdco / 4);
1513 
1514 	seq_printf(s,	"TxByteClkHS\t%lu\n", dsi_get_txbyteclkhs(dsidev));
1515 
1516 	seq_printf(s,	"LP_CLK\t\t%lu\n", dsi->current_lp_cinfo.lp_clk);
1517 
1518 	dsi_runtime_put(dsidev);
1519 }
1520 
1521 void dsi_dump_clocks(struct seq_file *s)
1522 {
1523 	struct platform_device *dsidev;
1524 	int i;
1525 
1526 	for  (i = 0; i < MAX_NUM_DSI; i++) {
1527 		dsidev = dsi_get_dsidev_from_id(i);
1528 		if (dsidev)
1529 			dsi_dump_dsidev_clocks(dsidev, s);
1530 	}
1531 }
1532 
1533 #ifdef CONFIG_FB_OMAP2_DSS_COLLECT_IRQ_STATS
1534 static void dsi_dump_dsidev_irqs(struct platform_device *dsidev,
1535 		struct seq_file *s)
1536 {
1537 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1538 	unsigned long flags;
1539 	struct dsi_irq_stats *stats;
1540 
1541 	stats = kzalloc(sizeof(*stats), GFP_KERNEL);
1542 	if (!stats) {
1543 		seq_printf(s, "out of memory\n");
1544 		return;
1545 	}
1546 
1547 	spin_lock_irqsave(&dsi->irq_stats_lock, flags);
1548 
1549 	*stats = dsi->irq_stats;
1550 	memset(&dsi->irq_stats, 0, sizeof(dsi->irq_stats));
1551 	dsi->irq_stats.last_reset = jiffies;
1552 
1553 	spin_unlock_irqrestore(&dsi->irq_stats_lock, flags);
1554 
1555 	seq_printf(s, "period %u ms\n",
1556 			jiffies_to_msecs(jiffies - stats->last_reset));
1557 
1558 	seq_printf(s, "irqs %d\n", stats->irq_count);
1559 #define PIS(x) \
1560 	seq_printf(s, "%-20s %10d\n", #x, stats->dsi_irqs[ffs(DSI_IRQ_##x)-1])
1561 
1562 	seq_printf(s, "-- DSI%d interrupts --\n", dsi->module_id + 1);
1563 	PIS(VC0);
1564 	PIS(VC1);
1565 	PIS(VC2);
1566 	PIS(VC3);
1567 	PIS(WAKEUP);
1568 	PIS(RESYNC);
1569 	PIS(PLL_LOCK);
1570 	PIS(PLL_UNLOCK);
1571 	PIS(PLL_RECALL);
1572 	PIS(COMPLEXIO_ERR);
1573 	PIS(HS_TX_TIMEOUT);
1574 	PIS(LP_RX_TIMEOUT);
1575 	PIS(TE_TRIGGER);
1576 	PIS(ACK_TRIGGER);
1577 	PIS(SYNC_LOST);
1578 	PIS(LDO_POWER_GOOD);
1579 	PIS(TA_TIMEOUT);
1580 #undef PIS
1581 
1582 #define PIS(x) \
1583 	seq_printf(s, "%-20s %10d %10d %10d %10d\n", #x, \
1584 			stats->vc_irqs[0][ffs(DSI_VC_IRQ_##x)-1], \
1585 			stats->vc_irqs[1][ffs(DSI_VC_IRQ_##x)-1], \
1586 			stats->vc_irqs[2][ffs(DSI_VC_IRQ_##x)-1], \
1587 			stats->vc_irqs[3][ffs(DSI_VC_IRQ_##x)-1]);
1588 
1589 	seq_printf(s, "-- VC interrupts --\n");
1590 	PIS(CS);
1591 	PIS(ECC_CORR);
1592 	PIS(PACKET_SENT);
1593 	PIS(FIFO_TX_OVF);
1594 	PIS(FIFO_RX_OVF);
1595 	PIS(BTA);
1596 	PIS(ECC_NO_CORR);
1597 	PIS(FIFO_TX_UDF);
1598 	PIS(PP_BUSY_CHANGE);
1599 #undef PIS
1600 
1601 #define PIS(x) \
1602 	seq_printf(s, "%-20s %10d\n", #x, \
1603 			stats->cio_irqs[ffs(DSI_CIO_IRQ_##x)-1]);
1604 
1605 	seq_printf(s, "-- CIO interrupts --\n");
1606 	PIS(ERRSYNCESC1);
1607 	PIS(ERRSYNCESC2);
1608 	PIS(ERRSYNCESC3);
1609 	PIS(ERRESC1);
1610 	PIS(ERRESC2);
1611 	PIS(ERRESC3);
1612 	PIS(ERRCONTROL1);
1613 	PIS(ERRCONTROL2);
1614 	PIS(ERRCONTROL3);
1615 	PIS(STATEULPS1);
1616 	PIS(STATEULPS2);
1617 	PIS(STATEULPS3);
1618 	PIS(ERRCONTENTIONLP0_1);
1619 	PIS(ERRCONTENTIONLP1_1);
1620 	PIS(ERRCONTENTIONLP0_2);
1621 	PIS(ERRCONTENTIONLP1_2);
1622 	PIS(ERRCONTENTIONLP0_3);
1623 	PIS(ERRCONTENTIONLP1_3);
1624 	PIS(ULPSACTIVENOT_ALL0);
1625 	PIS(ULPSACTIVENOT_ALL1);
1626 #undef PIS
1627 
1628 	kfree(stats);
1629 }
1630 
1631 static void dsi1_dump_irqs(struct seq_file *s)
1632 {
1633 	struct platform_device *dsidev = dsi_get_dsidev_from_id(0);
1634 
1635 	dsi_dump_dsidev_irqs(dsidev, s);
1636 }
1637 
1638 static void dsi2_dump_irqs(struct seq_file *s)
1639 {
1640 	struct platform_device *dsidev = dsi_get_dsidev_from_id(1);
1641 
1642 	dsi_dump_dsidev_irqs(dsidev, s);
1643 }
1644 #endif
1645 
1646 static void dsi_dump_dsidev_regs(struct platform_device *dsidev,
1647 		struct seq_file *s)
1648 {
1649 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(dsidev, r))
1650 
1651 	if (dsi_runtime_get(dsidev))
1652 		return;
1653 	dsi_enable_scp_clk(dsidev);
1654 
1655 	DUMPREG(DSI_REVISION);
1656 	DUMPREG(DSI_SYSCONFIG);
1657 	DUMPREG(DSI_SYSSTATUS);
1658 	DUMPREG(DSI_IRQSTATUS);
1659 	DUMPREG(DSI_IRQENABLE);
1660 	DUMPREG(DSI_CTRL);
1661 	DUMPREG(DSI_COMPLEXIO_CFG1);
1662 	DUMPREG(DSI_COMPLEXIO_IRQ_STATUS);
1663 	DUMPREG(DSI_COMPLEXIO_IRQ_ENABLE);
1664 	DUMPREG(DSI_CLK_CTRL);
1665 	DUMPREG(DSI_TIMING1);
1666 	DUMPREG(DSI_TIMING2);
1667 	DUMPREG(DSI_VM_TIMING1);
1668 	DUMPREG(DSI_VM_TIMING2);
1669 	DUMPREG(DSI_VM_TIMING3);
1670 	DUMPREG(DSI_CLK_TIMING);
1671 	DUMPREG(DSI_TX_FIFO_VC_SIZE);
1672 	DUMPREG(DSI_RX_FIFO_VC_SIZE);
1673 	DUMPREG(DSI_COMPLEXIO_CFG2);
1674 	DUMPREG(DSI_RX_FIFO_VC_FULLNESS);
1675 	DUMPREG(DSI_VM_TIMING4);
1676 	DUMPREG(DSI_TX_FIFO_VC_EMPTINESS);
1677 	DUMPREG(DSI_VM_TIMING5);
1678 	DUMPREG(DSI_VM_TIMING6);
1679 	DUMPREG(DSI_VM_TIMING7);
1680 	DUMPREG(DSI_STOPCLK_TIMING);
1681 
1682 	DUMPREG(DSI_VC_CTRL(0));
1683 	DUMPREG(DSI_VC_TE(0));
1684 	DUMPREG(DSI_VC_LONG_PACKET_HEADER(0));
1685 	DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(0));
1686 	DUMPREG(DSI_VC_SHORT_PACKET_HEADER(0));
1687 	DUMPREG(DSI_VC_IRQSTATUS(0));
1688 	DUMPREG(DSI_VC_IRQENABLE(0));
1689 
1690 	DUMPREG(DSI_VC_CTRL(1));
1691 	DUMPREG(DSI_VC_TE(1));
1692 	DUMPREG(DSI_VC_LONG_PACKET_HEADER(1));
1693 	DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(1));
1694 	DUMPREG(DSI_VC_SHORT_PACKET_HEADER(1));
1695 	DUMPREG(DSI_VC_IRQSTATUS(1));
1696 	DUMPREG(DSI_VC_IRQENABLE(1));
1697 
1698 	DUMPREG(DSI_VC_CTRL(2));
1699 	DUMPREG(DSI_VC_TE(2));
1700 	DUMPREG(DSI_VC_LONG_PACKET_HEADER(2));
1701 	DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(2));
1702 	DUMPREG(DSI_VC_SHORT_PACKET_HEADER(2));
1703 	DUMPREG(DSI_VC_IRQSTATUS(2));
1704 	DUMPREG(DSI_VC_IRQENABLE(2));
1705 
1706 	DUMPREG(DSI_VC_CTRL(3));
1707 	DUMPREG(DSI_VC_TE(3));
1708 	DUMPREG(DSI_VC_LONG_PACKET_HEADER(3));
1709 	DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(3));
1710 	DUMPREG(DSI_VC_SHORT_PACKET_HEADER(3));
1711 	DUMPREG(DSI_VC_IRQSTATUS(3));
1712 	DUMPREG(DSI_VC_IRQENABLE(3));
1713 
1714 	DUMPREG(DSI_DSIPHY_CFG0);
1715 	DUMPREG(DSI_DSIPHY_CFG1);
1716 	DUMPREG(DSI_DSIPHY_CFG2);
1717 	DUMPREG(DSI_DSIPHY_CFG5);
1718 
1719 	DUMPREG(DSI_PLL_CONTROL);
1720 	DUMPREG(DSI_PLL_STATUS);
1721 	DUMPREG(DSI_PLL_GO);
1722 	DUMPREG(DSI_PLL_CONFIGURATION1);
1723 	DUMPREG(DSI_PLL_CONFIGURATION2);
1724 
1725 	dsi_disable_scp_clk(dsidev);
1726 	dsi_runtime_put(dsidev);
1727 #undef DUMPREG
1728 }
1729 
1730 static void dsi1_dump_regs(struct seq_file *s)
1731 {
1732 	struct platform_device *dsidev = dsi_get_dsidev_from_id(0);
1733 
1734 	dsi_dump_dsidev_regs(dsidev, s);
1735 }
1736 
1737 static void dsi2_dump_regs(struct seq_file *s)
1738 {
1739 	struct platform_device *dsidev = dsi_get_dsidev_from_id(1);
1740 
1741 	dsi_dump_dsidev_regs(dsidev, s);
1742 }
1743 
1744 enum dsi_cio_power_state {
1745 	DSI_COMPLEXIO_POWER_OFF		= 0x0,
1746 	DSI_COMPLEXIO_POWER_ON		= 0x1,
1747 	DSI_COMPLEXIO_POWER_ULPS	= 0x2,
1748 };
1749 
1750 static int dsi_cio_power(struct platform_device *dsidev,
1751 		enum dsi_cio_power_state state)
1752 {
1753 	int t = 0;
1754 
1755 	/* PWR_CMD */
1756 	REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG1, state, 28, 27);
1757 
1758 	/* PWR_STATUS */
1759 	while (FLD_GET(dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1),
1760 			26, 25) != state) {
1761 		if (++t > 1000) {
1762 			DSSERR("failed to set complexio power state to "
1763 					"%d\n", state);
1764 			return -ENODEV;
1765 		}
1766 		udelay(1);
1767 	}
1768 
1769 	return 0;
1770 }
1771 
1772 static unsigned dsi_get_line_buf_size(struct platform_device *dsidev)
1773 {
1774 	int val;
1775 
1776 	/* line buffer on OMAP3 is 1024 x 24bits */
1777 	/* XXX: for some reason using full buffer size causes
1778 	 * considerable TX slowdown with update sizes that fill the
1779 	 * whole buffer */
1780 	if (!dss_has_feature(FEAT_DSI_GNQ))
1781 		return 1023 * 3;
1782 
1783 	val = REG_GET(dsidev, DSI_GNQ, 14, 12); /* VP1_LINE_BUFFER_SIZE */
1784 
1785 	switch (val) {
1786 	case 1:
1787 		return 512 * 3;		/* 512x24 bits */
1788 	case 2:
1789 		return 682 * 3;		/* 682x24 bits */
1790 	case 3:
1791 		return 853 * 3;		/* 853x24 bits */
1792 	case 4:
1793 		return 1024 * 3;	/* 1024x24 bits */
1794 	case 5:
1795 		return 1194 * 3;	/* 1194x24 bits */
1796 	case 6:
1797 		return 1365 * 3;	/* 1365x24 bits */
1798 	case 7:
1799 		return 1920 * 3;	/* 1920x24 bits */
1800 	default:
1801 		BUG();
1802 		return 0;
1803 	}
1804 }
1805 
1806 static int dsi_set_lane_config(struct platform_device *dsidev)
1807 {
1808 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1809 	static const u8 offsets[] = { 0, 4, 8, 12, 16 };
1810 	static const enum dsi_lane_function functions[] = {
1811 		DSI_LANE_CLK,
1812 		DSI_LANE_DATA1,
1813 		DSI_LANE_DATA2,
1814 		DSI_LANE_DATA3,
1815 		DSI_LANE_DATA4,
1816 	};
1817 	u32 r;
1818 	int i;
1819 
1820 	r = dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1);
1821 
1822 	for (i = 0; i < dsi->num_lanes_used; ++i) {
1823 		unsigned offset = offsets[i];
1824 		unsigned polarity, lane_number;
1825 		unsigned t;
1826 
1827 		for (t = 0; t < dsi->num_lanes_supported; ++t)
1828 			if (dsi->lanes[t].function == functions[i])
1829 				break;
1830 
1831 		if (t == dsi->num_lanes_supported)
1832 			return -EINVAL;
1833 
1834 		lane_number = t;
1835 		polarity = dsi->lanes[t].polarity;
1836 
1837 		r = FLD_MOD(r, lane_number + 1, offset + 2, offset);
1838 		r = FLD_MOD(r, polarity, offset + 3, offset + 3);
1839 	}
1840 
1841 	/* clear the unused lanes */
1842 	for (; i < dsi->num_lanes_supported; ++i) {
1843 		unsigned offset = offsets[i];
1844 
1845 		r = FLD_MOD(r, 0, offset + 2, offset);
1846 		r = FLD_MOD(r, 0, offset + 3, offset + 3);
1847 	}
1848 
1849 	dsi_write_reg(dsidev, DSI_COMPLEXIO_CFG1, r);
1850 
1851 	return 0;
1852 }
1853 
1854 static inline unsigned ns2ddr(struct platform_device *dsidev, unsigned ns)
1855 {
1856 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1857 
1858 	/* convert time in ns to ddr ticks, rounding up */
1859 	unsigned long ddr_clk = dsi->pll.cinfo.clkdco / 4;
1860 	return (ns * (ddr_clk / 1000 / 1000) + 999) / 1000;
1861 }
1862 
1863 static inline unsigned ddr2ns(struct platform_device *dsidev, unsigned ddr)
1864 {
1865 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1866 
1867 	unsigned long ddr_clk = dsi->pll.cinfo.clkdco / 4;
1868 	return ddr * 1000 * 1000 / (ddr_clk / 1000);
1869 }
1870 
1871 static void dsi_cio_timings(struct platform_device *dsidev)
1872 {
1873 	u32 r;
1874 	u32 ths_prepare, ths_prepare_ths_zero, ths_trail, ths_exit;
1875 	u32 tlpx_half, tclk_trail, tclk_zero;
1876 	u32 tclk_prepare;
1877 
1878 	/* calculate timings */
1879 
1880 	/* 1 * DDR_CLK = 2 * UI */
1881 
1882 	/* min 40ns + 4*UI	max 85ns + 6*UI */
1883 	ths_prepare = ns2ddr(dsidev, 70) + 2;
1884 
1885 	/* min 145ns + 10*UI */
1886 	ths_prepare_ths_zero = ns2ddr(dsidev, 175) + 2;
1887 
1888 	/* min max(8*UI, 60ns+4*UI) */
1889 	ths_trail = ns2ddr(dsidev, 60) + 5;
1890 
1891 	/* min 100ns */
1892 	ths_exit = ns2ddr(dsidev, 145);
1893 
1894 	/* tlpx min 50n */
1895 	tlpx_half = ns2ddr(dsidev, 25);
1896 
1897 	/* min 60ns */
1898 	tclk_trail = ns2ddr(dsidev, 60) + 2;
1899 
1900 	/* min 38ns, max 95ns */
1901 	tclk_prepare = ns2ddr(dsidev, 65);
1902 
1903 	/* min tclk-prepare + tclk-zero = 300ns */
1904 	tclk_zero = ns2ddr(dsidev, 260);
1905 
1906 	DSSDBG("ths_prepare %u (%uns), ths_prepare_ths_zero %u (%uns)\n",
1907 		ths_prepare, ddr2ns(dsidev, ths_prepare),
1908 		ths_prepare_ths_zero, ddr2ns(dsidev, ths_prepare_ths_zero));
1909 	DSSDBG("ths_trail %u (%uns), ths_exit %u (%uns)\n",
1910 			ths_trail, ddr2ns(dsidev, ths_trail),
1911 			ths_exit, ddr2ns(dsidev, ths_exit));
1912 
1913 	DSSDBG("tlpx_half %u (%uns), tclk_trail %u (%uns), "
1914 			"tclk_zero %u (%uns)\n",
1915 			tlpx_half, ddr2ns(dsidev, tlpx_half),
1916 			tclk_trail, ddr2ns(dsidev, tclk_trail),
1917 			tclk_zero, ddr2ns(dsidev, tclk_zero));
1918 	DSSDBG("tclk_prepare %u (%uns)\n",
1919 			tclk_prepare, ddr2ns(dsidev, tclk_prepare));
1920 
1921 	/* program timings */
1922 
1923 	r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0);
1924 	r = FLD_MOD(r, ths_prepare, 31, 24);
1925 	r = FLD_MOD(r, ths_prepare_ths_zero, 23, 16);
1926 	r = FLD_MOD(r, ths_trail, 15, 8);
1927 	r = FLD_MOD(r, ths_exit, 7, 0);
1928 	dsi_write_reg(dsidev, DSI_DSIPHY_CFG0, r);
1929 
1930 	r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1);
1931 	r = FLD_MOD(r, tlpx_half, 20, 16);
1932 	r = FLD_MOD(r, tclk_trail, 15, 8);
1933 	r = FLD_MOD(r, tclk_zero, 7, 0);
1934 
1935 	if (dss_has_feature(FEAT_DSI_PHY_DCC)) {
1936 		r = FLD_MOD(r, 0, 21, 21);	/* DCCEN = disable */
1937 		r = FLD_MOD(r, 1, 22, 22);	/* CLKINP_DIVBY2EN = enable */
1938 		r = FLD_MOD(r, 1, 23, 23);	/* CLKINP_SEL = enable */
1939 	}
1940 
1941 	dsi_write_reg(dsidev, DSI_DSIPHY_CFG1, r);
1942 
1943 	r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG2);
1944 	r = FLD_MOD(r, tclk_prepare, 7, 0);
1945 	dsi_write_reg(dsidev, DSI_DSIPHY_CFG2, r);
1946 }
1947 
1948 /* lane masks have lane 0 at lsb. mask_p for positive lines, n for negative */
1949 static void dsi_cio_enable_lane_override(struct platform_device *dsidev,
1950 		unsigned mask_p, unsigned mask_n)
1951 {
1952 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1953 	int i;
1954 	u32 l;
1955 	u8 lptxscp_start = dsi->num_lanes_supported == 3 ? 22 : 26;
1956 
1957 	l = 0;
1958 
1959 	for (i = 0; i < dsi->num_lanes_supported; ++i) {
1960 		unsigned p = dsi->lanes[i].polarity;
1961 
1962 		if (mask_p & (1 << i))
1963 			l |= 1 << (i * 2 + (p ? 0 : 1));
1964 
1965 		if (mask_n & (1 << i))
1966 			l |= 1 << (i * 2 + (p ? 1 : 0));
1967 	}
1968 
1969 	/*
1970 	 * Bits in REGLPTXSCPDAT4TO0DXDY:
1971 	 * 17: DY0 18: DX0
1972 	 * 19: DY1 20: DX1
1973 	 * 21: DY2 22: DX2
1974 	 * 23: DY3 24: DX3
1975 	 * 25: DY4 26: DX4
1976 	 */
1977 
1978 	/* Set the lane override configuration */
1979 
1980 	/* REGLPTXSCPDAT4TO0DXDY */
1981 	REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, l, lptxscp_start, 17);
1982 
1983 	/* Enable lane override */
1984 
1985 	/* ENLPTXSCPDAT */
1986 	REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 1, 27, 27);
1987 }
1988 
1989 static void dsi_cio_disable_lane_override(struct platform_device *dsidev)
1990 {
1991 	/* Disable lane override */
1992 	REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 0, 27, 27); /* ENLPTXSCPDAT */
1993 	/* Reset the lane override configuration */
1994 	/* REGLPTXSCPDAT4TO0DXDY */
1995 	REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 0, 22, 17);
1996 }
1997 
1998 static int dsi_cio_wait_tx_clk_esc_reset(struct platform_device *dsidev)
1999 {
2000 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2001 	int t, i;
2002 	bool in_use[DSI_MAX_NR_LANES];
2003 	static const u8 offsets_old[] = { 28, 27, 26 };
2004 	static const u8 offsets_new[] = { 24, 25, 26, 27, 28 };
2005 	const u8 *offsets;
2006 
2007 	if (dss_has_feature(FEAT_DSI_REVERSE_TXCLKESC))
2008 		offsets = offsets_old;
2009 	else
2010 		offsets = offsets_new;
2011 
2012 	for (i = 0; i < dsi->num_lanes_supported; ++i)
2013 		in_use[i] = dsi->lanes[i].function != DSI_LANE_UNUSED;
2014 
2015 	t = 100000;
2016 	while (true) {
2017 		u32 l;
2018 		int ok;
2019 
2020 		l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
2021 
2022 		ok = 0;
2023 		for (i = 0; i < dsi->num_lanes_supported; ++i) {
2024 			if (!in_use[i] || (l & (1 << offsets[i])))
2025 				ok++;
2026 		}
2027 
2028 		if (ok == dsi->num_lanes_supported)
2029 			break;
2030 
2031 		if (--t == 0) {
2032 			for (i = 0; i < dsi->num_lanes_supported; ++i) {
2033 				if (!in_use[i] || (l & (1 << offsets[i])))
2034 					continue;
2035 
2036 				DSSERR("CIO TXCLKESC%d domain not coming " \
2037 						"out of reset\n", i);
2038 			}
2039 			return -EIO;
2040 		}
2041 	}
2042 
2043 	return 0;
2044 }
2045 
2046 /* return bitmask of enabled lanes, lane0 being the lsb */
2047 static unsigned dsi_get_lane_mask(struct platform_device *dsidev)
2048 {
2049 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2050 	unsigned mask = 0;
2051 	int i;
2052 
2053 	for (i = 0; i < dsi->num_lanes_supported; ++i) {
2054 		if (dsi->lanes[i].function != DSI_LANE_UNUSED)
2055 			mask |= 1 << i;
2056 	}
2057 
2058 	return mask;
2059 }
2060 
2061 static int dsi_cio_init(struct platform_device *dsidev)
2062 {
2063 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2064 	int r;
2065 	u32 l;
2066 
2067 	DSSDBG("DSI CIO init starts");
2068 
2069 	r = dss_dsi_enable_pads(dsi->module_id, dsi_get_lane_mask(dsidev));
2070 	if (r)
2071 		return r;
2072 
2073 	dsi_enable_scp_clk(dsidev);
2074 
2075 	/* A dummy read using the SCP interface to any DSIPHY register is
2076 	 * required after DSIPHY reset to complete the reset of the DSI complex
2077 	 * I/O. */
2078 	dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
2079 
2080 	if (wait_for_bit_change(dsidev, DSI_DSIPHY_CFG5, 30, 1) != 1) {
2081 		DSSERR("CIO SCP Clock domain not coming out of reset.\n");
2082 		r = -EIO;
2083 		goto err_scp_clk_dom;
2084 	}
2085 
2086 	r = dsi_set_lane_config(dsidev);
2087 	if (r)
2088 		goto err_scp_clk_dom;
2089 
2090 	/* set TX STOP MODE timer to maximum for this operation */
2091 	l = dsi_read_reg(dsidev, DSI_TIMING1);
2092 	l = FLD_MOD(l, 1, 15, 15);	/* FORCE_TX_STOP_MODE_IO */
2093 	l = FLD_MOD(l, 1, 14, 14);	/* STOP_STATE_X16_IO */
2094 	l = FLD_MOD(l, 1, 13, 13);	/* STOP_STATE_X4_IO */
2095 	l = FLD_MOD(l, 0x1fff, 12, 0);	/* STOP_STATE_COUNTER_IO */
2096 	dsi_write_reg(dsidev, DSI_TIMING1, l);
2097 
2098 	if (dsi->ulps_enabled) {
2099 		unsigned mask_p;
2100 		int i;
2101 
2102 		DSSDBG("manual ulps exit\n");
2103 
2104 		/* ULPS is exited by Mark-1 state for 1ms, followed by
2105 		 * stop state. DSS HW cannot do this via the normal
2106 		 * ULPS exit sequence, as after reset the DSS HW thinks
2107 		 * that we are not in ULPS mode, and refuses to send the
2108 		 * sequence. So we need to send the ULPS exit sequence
2109 		 * manually by setting positive lines high and negative lines
2110 		 * low for 1ms.
2111 		 */
2112 
2113 		mask_p = 0;
2114 
2115 		for (i = 0; i < dsi->num_lanes_supported; ++i) {
2116 			if (dsi->lanes[i].function == DSI_LANE_UNUSED)
2117 				continue;
2118 			mask_p |= 1 << i;
2119 		}
2120 
2121 		dsi_cio_enable_lane_override(dsidev, mask_p, 0);
2122 	}
2123 
2124 	r = dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_ON);
2125 	if (r)
2126 		goto err_cio_pwr;
2127 
2128 	if (wait_for_bit_change(dsidev, DSI_COMPLEXIO_CFG1, 29, 1) != 1) {
2129 		DSSERR("CIO PWR clock domain not coming out of reset.\n");
2130 		r = -ENODEV;
2131 		goto err_cio_pwr_dom;
2132 	}
2133 
2134 	dsi_if_enable(dsidev, true);
2135 	dsi_if_enable(dsidev, false);
2136 	REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 20, 20); /* LP_CLK_ENABLE */
2137 
2138 	r = dsi_cio_wait_tx_clk_esc_reset(dsidev);
2139 	if (r)
2140 		goto err_tx_clk_esc_rst;
2141 
2142 	if (dsi->ulps_enabled) {
2143 		/* Keep Mark-1 state for 1ms (as per DSI spec) */
2144 		ktime_t wait = ns_to_ktime(1000 * 1000);
2145 		set_current_state(TASK_UNINTERRUPTIBLE);
2146 		schedule_hrtimeout(&wait, HRTIMER_MODE_REL);
2147 
2148 		/* Disable the override. The lanes should be set to Mark-11
2149 		 * state by the HW */
2150 		dsi_cio_disable_lane_override(dsidev);
2151 	}
2152 
2153 	/* FORCE_TX_STOP_MODE_IO */
2154 	REG_FLD_MOD(dsidev, DSI_TIMING1, 0, 15, 15);
2155 
2156 	dsi_cio_timings(dsidev);
2157 
2158 	if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
2159 		/* DDR_CLK_ALWAYS_ON */
2160 		REG_FLD_MOD(dsidev, DSI_CLK_CTRL,
2161 			dsi->vm_timings.ddr_clk_always_on, 13, 13);
2162 	}
2163 
2164 	dsi->ulps_enabled = false;
2165 
2166 	DSSDBG("CIO init done\n");
2167 
2168 	return 0;
2169 
2170 err_tx_clk_esc_rst:
2171 	REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 20, 20); /* LP_CLK_ENABLE */
2172 err_cio_pwr_dom:
2173 	dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_OFF);
2174 err_cio_pwr:
2175 	if (dsi->ulps_enabled)
2176 		dsi_cio_disable_lane_override(dsidev);
2177 err_scp_clk_dom:
2178 	dsi_disable_scp_clk(dsidev);
2179 	dss_dsi_disable_pads(dsi->module_id, dsi_get_lane_mask(dsidev));
2180 	return r;
2181 }
2182 
2183 static void dsi_cio_uninit(struct platform_device *dsidev)
2184 {
2185 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2186 
2187 	/* DDR_CLK_ALWAYS_ON */
2188 	REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 13, 13);
2189 
2190 	dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_OFF);
2191 	dsi_disable_scp_clk(dsidev);
2192 	dss_dsi_disable_pads(dsi->module_id, dsi_get_lane_mask(dsidev));
2193 }
2194 
2195 static void dsi_config_tx_fifo(struct platform_device *dsidev,
2196 		enum fifo_size size1, enum fifo_size size2,
2197 		enum fifo_size size3, enum fifo_size size4)
2198 {
2199 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2200 	u32 r = 0;
2201 	int add = 0;
2202 	int i;
2203 
2204 	dsi->vc[0].tx_fifo_size = size1;
2205 	dsi->vc[1].tx_fifo_size = size2;
2206 	dsi->vc[2].tx_fifo_size = size3;
2207 	dsi->vc[3].tx_fifo_size = size4;
2208 
2209 	for (i = 0; i < 4; i++) {
2210 		u8 v;
2211 		int size = dsi->vc[i].tx_fifo_size;
2212 
2213 		if (add + size > 4) {
2214 			DSSERR("Illegal FIFO configuration\n");
2215 			BUG();
2216 			return;
2217 		}
2218 
2219 		v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
2220 		r |= v << (8 * i);
2221 		/*DSSDBG("TX FIFO vc %d: size %d, add %d\n", i, size, add); */
2222 		add += size;
2223 	}
2224 
2225 	dsi_write_reg(dsidev, DSI_TX_FIFO_VC_SIZE, r);
2226 }
2227 
2228 static void dsi_config_rx_fifo(struct platform_device *dsidev,
2229 		enum fifo_size size1, enum fifo_size size2,
2230 		enum fifo_size size3, enum fifo_size size4)
2231 {
2232 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2233 	u32 r = 0;
2234 	int add = 0;
2235 	int i;
2236 
2237 	dsi->vc[0].rx_fifo_size = size1;
2238 	dsi->vc[1].rx_fifo_size = size2;
2239 	dsi->vc[2].rx_fifo_size = size3;
2240 	dsi->vc[3].rx_fifo_size = size4;
2241 
2242 	for (i = 0; i < 4; i++) {
2243 		u8 v;
2244 		int size = dsi->vc[i].rx_fifo_size;
2245 
2246 		if (add + size > 4) {
2247 			DSSERR("Illegal FIFO configuration\n");
2248 			BUG();
2249 			return;
2250 		}
2251 
2252 		v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
2253 		r |= v << (8 * i);
2254 		/*DSSDBG("RX FIFO vc %d: size %d, add %d\n", i, size, add); */
2255 		add += size;
2256 	}
2257 
2258 	dsi_write_reg(dsidev, DSI_RX_FIFO_VC_SIZE, r);
2259 }
2260 
2261 static int dsi_force_tx_stop_mode_io(struct platform_device *dsidev)
2262 {
2263 	u32 r;
2264 
2265 	r = dsi_read_reg(dsidev, DSI_TIMING1);
2266 	r = FLD_MOD(r, 1, 15, 15);	/* FORCE_TX_STOP_MODE_IO */
2267 	dsi_write_reg(dsidev, DSI_TIMING1, r);
2268 
2269 	if (wait_for_bit_change(dsidev, DSI_TIMING1, 15, 0) != 0) {
2270 		DSSERR("TX_STOP bit not going down\n");
2271 		return -EIO;
2272 	}
2273 
2274 	return 0;
2275 }
2276 
2277 static bool dsi_vc_is_enabled(struct platform_device *dsidev, int channel)
2278 {
2279 	return REG_GET(dsidev, DSI_VC_CTRL(channel), 0, 0);
2280 }
2281 
2282 static void dsi_packet_sent_handler_vp(void *data, u32 mask)
2283 {
2284 	struct dsi_packet_sent_handler_data *vp_data =
2285 		(struct dsi_packet_sent_handler_data *) data;
2286 	struct dsi_data *dsi = dsi_get_dsidrv_data(vp_data->dsidev);
2287 	const int channel = dsi->update_channel;
2288 	u8 bit = dsi->te_enabled ? 30 : 31;
2289 
2290 	if (REG_GET(vp_data->dsidev, DSI_VC_TE(channel), bit, bit) == 0)
2291 		complete(vp_data->completion);
2292 }
2293 
2294 static int dsi_sync_vc_vp(struct platform_device *dsidev, int channel)
2295 {
2296 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2297 	DECLARE_COMPLETION_ONSTACK(completion);
2298 	struct dsi_packet_sent_handler_data vp_data = {
2299 		.dsidev = dsidev,
2300 		.completion = &completion
2301 	};
2302 	int r = 0;
2303 	u8 bit;
2304 
2305 	bit = dsi->te_enabled ? 30 : 31;
2306 
2307 	r = dsi_register_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp,
2308 		&vp_data, DSI_VC_IRQ_PACKET_SENT);
2309 	if (r)
2310 		goto err0;
2311 
2312 	/* Wait for completion only if TE_EN/TE_START is still set */
2313 	if (REG_GET(dsidev, DSI_VC_TE(channel), bit, bit)) {
2314 		if (wait_for_completion_timeout(&completion,
2315 				msecs_to_jiffies(10)) == 0) {
2316 			DSSERR("Failed to complete previous frame transfer\n");
2317 			r = -EIO;
2318 			goto err1;
2319 		}
2320 	}
2321 
2322 	dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp,
2323 		&vp_data, DSI_VC_IRQ_PACKET_SENT);
2324 
2325 	return 0;
2326 err1:
2327 	dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp,
2328 		&vp_data, DSI_VC_IRQ_PACKET_SENT);
2329 err0:
2330 	return r;
2331 }
2332 
2333 static void dsi_packet_sent_handler_l4(void *data, u32 mask)
2334 {
2335 	struct dsi_packet_sent_handler_data *l4_data =
2336 		(struct dsi_packet_sent_handler_data *) data;
2337 	struct dsi_data *dsi = dsi_get_dsidrv_data(l4_data->dsidev);
2338 	const int channel = dsi->update_channel;
2339 
2340 	if (REG_GET(l4_data->dsidev, DSI_VC_CTRL(channel), 5, 5) == 0)
2341 		complete(l4_data->completion);
2342 }
2343 
2344 static int dsi_sync_vc_l4(struct platform_device *dsidev, int channel)
2345 {
2346 	DECLARE_COMPLETION_ONSTACK(completion);
2347 	struct dsi_packet_sent_handler_data l4_data = {
2348 		.dsidev = dsidev,
2349 		.completion = &completion
2350 	};
2351 	int r = 0;
2352 
2353 	r = dsi_register_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4,
2354 		&l4_data, DSI_VC_IRQ_PACKET_SENT);
2355 	if (r)
2356 		goto err0;
2357 
2358 	/* Wait for completion only if TX_FIFO_NOT_EMPTY is still set */
2359 	if (REG_GET(dsidev, DSI_VC_CTRL(channel), 5, 5)) {
2360 		if (wait_for_completion_timeout(&completion,
2361 				msecs_to_jiffies(10)) == 0) {
2362 			DSSERR("Failed to complete previous l4 transfer\n");
2363 			r = -EIO;
2364 			goto err1;
2365 		}
2366 	}
2367 
2368 	dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4,
2369 		&l4_data, DSI_VC_IRQ_PACKET_SENT);
2370 
2371 	return 0;
2372 err1:
2373 	dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4,
2374 		&l4_data, DSI_VC_IRQ_PACKET_SENT);
2375 err0:
2376 	return r;
2377 }
2378 
2379 static int dsi_sync_vc(struct platform_device *dsidev, int channel)
2380 {
2381 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2382 
2383 	WARN_ON(!dsi_bus_is_locked(dsidev));
2384 
2385 	if (!dsi_vc_is_enabled(dsidev, channel))
2386 		return 0;
2387 
2388 	switch (dsi->vc[channel].source) {
2389 	case DSI_VC_SOURCE_VP:
2390 		return dsi_sync_vc_vp(dsidev, channel);
2391 	case DSI_VC_SOURCE_L4:
2392 		return dsi_sync_vc_l4(dsidev, channel);
2393 	default:
2394 		BUG();
2395 		return -EINVAL;
2396 	}
2397 }
2398 
2399 static int dsi_vc_enable(struct platform_device *dsidev, int channel,
2400 		bool enable)
2401 {
2402 	DSSDBG("dsi_vc_enable channel %d, enable %d\n",
2403 			channel, enable);
2404 
2405 	enable = enable ? 1 : 0;
2406 
2407 	REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 0, 0);
2408 
2409 	if (wait_for_bit_change(dsidev, DSI_VC_CTRL(channel),
2410 		0, enable) != enable) {
2411 			DSSERR("Failed to set dsi_vc_enable to %d\n", enable);
2412 			return -EIO;
2413 	}
2414 
2415 	return 0;
2416 }
2417 
2418 static void dsi_vc_initial_config(struct platform_device *dsidev, int channel)
2419 {
2420 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2421 	u32 r;
2422 
2423 	DSSDBG("Initial config of virtual channel %d", channel);
2424 
2425 	r = dsi_read_reg(dsidev, DSI_VC_CTRL(channel));
2426 
2427 	if (FLD_GET(r, 15, 15)) /* VC_BUSY */
2428 		DSSERR("VC(%d) busy when trying to configure it!\n",
2429 				channel);
2430 
2431 	r = FLD_MOD(r, 0, 1, 1); /* SOURCE, 0 = L4 */
2432 	r = FLD_MOD(r, 0, 2, 2); /* BTA_SHORT_EN  */
2433 	r = FLD_MOD(r, 0, 3, 3); /* BTA_LONG_EN */
2434 	r = FLD_MOD(r, 0, 4, 4); /* MODE, 0 = command */
2435 	r = FLD_MOD(r, 1, 7, 7); /* CS_TX_EN */
2436 	r = FLD_MOD(r, 1, 8, 8); /* ECC_TX_EN */
2437 	r = FLD_MOD(r, 0, 9, 9); /* MODE_SPEED, high speed on/off */
2438 	if (dss_has_feature(FEAT_DSI_VC_OCP_WIDTH))
2439 		r = FLD_MOD(r, 3, 11, 10);	/* OCP_WIDTH = 32 bit */
2440 
2441 	r = FLD_MOD(r, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */
2442 	r = FLD_MOD(r, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */
2443 
2444 	dsi_write_reg(dsidev, DSI_VC_CTRL(channel), r);
2445 
2446 	dsi->vc[channel].source = DSI_VC_SOURCE_L4;
2447 }
2448 
2449 static int dsi_vc_config_source(struct platform_device *dsidev, int channel,
2450 		enum dsi_vc_source source)
2451 {
2452 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2453 
2454 	if (dsi->vc[channel].source == source)
2455 		return 0;
2456 
2457 	DSSDBG("Source config of virtual channel %d", channel);
2458 
2459 	dsi_sync_vc(dsidev, channel);
2460 
2461 	dsi_vc_enable(dsidev, channel, 0);
2462 
2463 	/* VC_BUSY */
2464 	if (wait_for_bit_change(dsidev, DSI_VC_CTRL(channel), 15, 0) != 0) {
2465 		DSSERR("vc(%d) busy when trying to config for VP\n", channel);
2466 		return -EIO;
2467 	}
2468 
2469 	/* SOURCE, 0 = L4, 1 = video port */
2470 	REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), source, 1, 1);
2471 
2472 	/* DCS_CMD_ENABLE */
2473 	if (dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC)) {
2474 		bool enable = source == DSI_VC_SOURCE_VP;
2475 		REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 30, 30);
2476 	}
2477 
2478 	dsi_vc_enable(dsidev, channel, 1);
2479 
2480 	dsi->vc[channel].source = source;
2481 
2482 	return 0;
2483 }
2484 
2485 static void dsi_vc_enable_hs(struct omap_dss_device *dssdev, int channel,
2486 		bool enable)
2487 {
2488 	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2489 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2490 
2491 	DSSDBG("dsi_vc_enable_hs(%d, %d)\n", channel, enable);
2492 
2493 	WARN_ON(!dsi_bus_is_locked(dsidev));
2494 
2495 	dsi_vc_enable(dsidev, channel, 0);
2496 	dsi_if_enable(dsidev, 0);
2497 
2498 	REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 9, 9);
2499 
2500 	dsi_vc_enable(dsidev, channel, 1);
2501 	dsi_if_enable(dsidev, 1);
2502 
2503 	dsi_force_tx_stop_mode_io(dsidev);
2504 
2505 	/* start the DDR clock by sending a NULL packet */
2506 	if (dsi->vm_timings.ddr_clk_always_on && enable)
2507 		dsi_vc_send_null(dssdev, channel);
2508 }
2509 
2510 static void dsi_vc_flush_long_data(struct platform_device *dsidev, int channel)
2511 {
2512 	while (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
2513 		u32 val;
2514 		val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));
2515 		DSSDBG("\t\tb1 %#02x b2 %#02x b3 %#02x b4 %#02x\n",
2516 				(val >> 0) & 0xff,
2517 				(val >> 8) & 0xff,
2518 				(val >> 16) & 0xff,
2519 				(val >> 24) & 0xff);
2520 	}
2521 }
2522 
2523 static void dsi_show_rx_ack_with_err(u16 err)
2524 {
2525 	DSSERR("\tACK with ERROR (%#x):\n", err);
2526 	if (err & (1 << 0))
2527 		DSSERR("\t\tSoT Error\n");
2528 	if (err & (1 << 1))
2529 		DSSERR("\t\tSoT Sync Error\n");
2530 	if (err & (1 << 2))
2531 		DSSERR("\t\tEoT Sync Error\n");
2532 	if (err & (1 << 3))
2533 		DSSERR("\t\tEscape Mode Entry Command Error\n");
2534 	if (err & (1 << 4))
2535 		DSSERR("\t\tLP Transmit Sync Error\n");
2536 	if (err & (1 << 5))
2537 		DSSERR("\t\tHS Receive Timeout Error\n");
2538 	if (err & (1 << 6))
2539 		DSSERR("\t\tFalse Control Error\n");
2540 	if (err & (1 << 7))
2541 		DSSERR("\t\t(reserved7)\n");
2542 	if (err & (1 << 8))
2543 		DSSERR("\t\tECC Error, single-bit (corrected)\n");
2544 	if (err & (1 << 9))
2545 		DSSERR("\t\tECC Error, multi-bit (not corrected)\n");
2546 	if (err & (1 << 10))
2547 		DSSERR("\t\tChecksum Error\n");
2548 	if (err & (1 << 11))
2549 		DSSERR("\t\tData type not recognized\n");
2550 	if (err & (1 << 12))
2551 		DSSERR("\t\tInvalid VC ID\n");
2552 	if (err & (1 << 13))
2553 		DSSERR("\t\tInvalid Transmission Length\n");
2554 	if (err & (1 << 14))
2555 		DSSERR("\t\t(reserved14)\n");
2556 	if (err & (1 << 15))
2557 		DSSERR("\t\tDSI Protocol Violation\n");
2558 }
2559 
2560 static u16 dsi_vc_flush_receive_data(struct platform_device *dsidev,
2561 		int channel)
2562 {
2563 	/* RX_FIFO_NOT_EMPTY */
2564 	while (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
2565 		u32 val;
2566 		u8 dt;
2567 		val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));
2568 		DSSERR("\trawval %#08x\n", val);
2569 		dt = FLD_GET(val, 5, 0);
2570 		if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) {
2571 			u16 err = FLD_GET(val, 23, 8);
2572 			dsi_show_rx_ack_with_err(err);
2573 		} else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE) {
2574 			DSSERR("\tDCS short response, 1 byte: %#x\n",
2575 					FLD_GET(val, 23, 8));
2576 		} else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE) {
2577 			DSSERR("\tDCS short response, 2 byte: %#x\n",
2578 					FLD_GET(val, 23, 8));
2579 		} else if (dt == MIPI_DSI_RX_DCS_LONG_READ_RESPONSE) {
2580 			DSSERR("\tDCS long response, len %d\n",
2581 					FLD_GET(val, 23, 8));
2582 			dsi_vc_flush_long_data(dsidev, channel);
2583 		} else {
2584 			DSSERR("\tunknown datatype 0x%02x\n", dt);
2585 		}
2586 	}
2587 	return 0;
2588 }
2589 
2590 static int dsi_vc_send_bta(struct platform_device *dsidev, int channel)
2591 {
2592 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2593 
2594 	if (dsi->debug_write || dsi->debug_read)
2595 		DSSDBG("dsi_vc_send_bta %d\n", channel);
2596 
2597 	WARN_ON(!dsi_bus_is_locked(dsidev));
2598 
2599 	/* RX_FIFO_NOT_EMPTY */
2600 	if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
2601 		DSSERR("rx fifo not empty when sending BTA, dumping data:\n");
2602 		dsi_vc_flush_receive_data(dsidev, channel);
2603 	}
2604 
2605 	REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 1, 6, 6); /* BTA_EN */
2606 
2607 	/* flush posted write */
2608 	dsi_read_reg(dsidev, DSI_VC_CTRL(channel));
2609 
2610 	return 0;
2611 }
2612 
2613 static int dsi_vc_send_bta_sync(struct omap_dss_device *dssdev, int channel)
2614 {
2615 	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2616 	DECLARE_COMPLETION_ONSTACK(completion);
2617 	int r = 0;
2618 	u32 err;
2619 
2620 	r = dsi_register_isr_vc(dsidev, channel, dsi_completion_handler,
2621 			&completion, DSI_VC_IRQ_BTA);
2622 	if (r)
2623 		goto err0;
2624 
2625 	r = dsi_register_isr(dsidev, dsi_completion_handler, &completion,
2626 			DSI_IRQ_ERROR_MASK);
2627 	if (r)
2628 		goto err1;
2629 
2630 	r = dsi_vc_send_bta(dsidev, channel);
2631 	if (r)
2632 		goto err2;
2633 
2634 	if (wait_for_completion_timeout(&completion,
2635 				msecs_to_jiffies(500)) == 0) {
2636 		DSSERR("Failed to receive BTA\n");
2637 		r = -EIO;
2638 		goto err2;
2639 	}
2640 
2641 	err = dsi_get_errors(dsidev);
2642 	if (err) {
2643 		DSSERR("Error while sending BTA: %x\n", err);
2644 		r = -EIO;
2645 		goto err2;
2646 	}
2647 err2:
2648 	dsi_unregister_isr(dsidev, dsi_completion_handler, &completion,
2649 			DSI_IRQ_ERROR_MASK);
2650 err1:
2651 	dsi_unregister_isr_vc(dsidev, channel, dsi_completion_handler,
2652 			&completion, DSI_VC_IRQ_BTA);
2653 err0:
2654 	return r;
2655 }
2656 
2657 static inline void dsi_vc_write_long_header(struct platform_device *dsidev,
2658 		int channel, u8 data_type, u16 len, u8 ecc)
2659 {
2660 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2661 	u32 val;
2662 	u8 data_id;
2663 
2664 	WARN_ON(!dsi_bus_is_locked(dsidev));
2665 
2666 	data_id = data_type | dsi->vc[channel].vc_id << 6;
2667 
2668 	val = FLD_VAL(data_id, 7, 0) | FLD_VAL(len, 23, 8) |
2669 		FLD_VAL(ecc, 31, 24);
2670 
2671 	dsi_write_reg(dsidev, DSI_VC_LONG_PACKET_HEADER(channel), val);
2672 }
2673 
2674 static inline void dsi_vc_write_long_payload(struct platform_device *dsidev,
2675 		int channel, u8 b1, u8 b2, u8 b3, u8 b4)
2676 {
2677 	u32 val;
2678 
2679 	val = b4 << 24 | b3 << 16 | b2 << 8  | b1 << 0;
2680 
2681 /*	DSSDBG("\twriting %02x, %02x, %02x, %02x (%#010x)\n",
2682 			b1, b2, b3, b4, val); */
2683 
2684 	dsi_write_reg(dsidev, DSI_VC_LONG_PACKET_PAYLOAD(channel), val);
2685 }
2686 
2687 static int dsi_vc_send_long(struct platform_device *dsidev, int channel,
2688 		u8 data_type, u8 *data, u16 len, u8 ecc)
2689 {
2690 	/*u32 val; */
2691 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2692 	int i;
2693 	u8 *p;
2694 	int r = 0;
2695 	u8 b1, b2, b3, b4;
2696 
2697 	if (dsi->debug_write)
2698 		DSSDBG("dsi_vc_send_long, %d bytes\n", len);
2699 
2700 	/* len + header */
2701 	if (dsi->vc[channel].tx_fifo_size * 32 * 4 < len + 4) {
2702 		DSSERR("unable to send long packet: packet too long.\n");
2703 		return -EINVAL;
2704 	}
2705 
2706 	dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_L4);
2707 
2708 	dsi_vc_write_long_header(dsidev, channel, data_type, len, ecc);
2709 
2710 	p = data;
2711 	for (i = 0; i < len >> 2; i++) {
2712 		if (dsi->debug_write)
2713 			DSSDBG("\tsending full packet %d\n", i);
2714 
2715 		b1 = *p++;
2716 		b2 = *p++;
2717 		b3 = *p++;
2718 		b4 = *p++;
2719 
2720 		dsi_vc_write_long_payload(dsidev, channel, b1, b2, b3, b4);
2721 	}
2722 
2723 	i = len % 4;
2724 	if (i) {
2725 		b1 = 0; b2 = 0; b3 = 0;
2726 
2727 		if (dsi->debug_write)
2728 			DSSDBG("\tsending remainder bytes %d\n", i);
2729 
2730 		switch (i) {
2731 		case 3:
2732 			b1 = *p++;
2733 			b2 = *p++;
2734 			b3 = *p++;
2735 			break;
2736 		case 2:
2737 			b1 = *p++;
2738 			b2 = *p++;
2739 			break;
2740 		case 1:
2741 			b1 = *p++;
2742 			break;
2743 		}
2744 
2745 		dsi_vc_write_long_payload(dsidev, channel, b1, b2, b3, 0);
2746 	}
2747 
2748 	return r;
2749 }
2750 
2751 static int dsi_vc_send_short(struct platform_device *dsidev, int channel,
2752 		u8 data_type, u16 data, u8 ecc)
2753 {
2754 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2755 	u32 r;
2756 	u8 data_id;
2757 
2758 	WARN_ON(!dsi_bus_is_locked(dsidev));
2759 
2760 	if (dsi->debug_write)
2761 		DSSDBG("dsi_vc_send_short(ch%d, dt %#x, b1 %#x, b2 %#x)\n",
2762 				channel,
2763 				data_type, data & 0xff, (data >> 8) & 0xff);
2764 
2765 	dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_L4);
2766 
2767 	if (FLD_GET(dsi_read_reg(dsidev, DSI_VC_CTRL(channel)), 16, 16)) {
2768 		DSSERR("ERROR FIFO FULL, aborting transfer\n");
2769 		return -EINVAL;
2770 	}
2771 
2772 	data_id = data_type | dsi->vc[channel].vc_id << 6;
2773 
2774 	r = (data_id << 0) | (data << 8) | (ecc << 24);
2775 
2776 	dsi_write_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel), r);
2777 
2778 	return 0;
2779 }
2780 
2781 static int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel)
2782 {
2783 	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2784 
2785 	return dsi_vc_send_long(dsidev, channel, MIPI_DSI_NULL_PACKET, NULL,
2786 		0, 0);
2787 }
2788 
2789 static int dsi_vc_write_nosync_common(struct platform_device *dsidev,
2790 		int channel, u8 *data, int len, enum dss_dsi_content_type type)
2791 {
2792 	int r;
2793 
2794 	if (len == 0) {
2795 		BUG_ON(type == DSS_DSI_CONTENT_DCS);
2796 		r = dsi_vc_send_short(dsidev, channel,
2797 				MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM, 0, 0);
2798 	} else if (len == 1) {
2799 		r = dsi_vc_send_short(dsidev, channel,
2800 				type == DSS_DSI_CONTENT_GENERIC ?
2801 				MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM :
2802 				MIPI_DSI_DCS_SHORT_WRITE, data[0], 0);
2803 	} else if (len == 2) {
2804 		r = dsi_vc_send_short(dsidev, channel,
2805 				type == DSS_DSI_CONTENT_GENERIC ?
2806 				MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM :
2807 				MIPI_DSI_DCS_SHORT_WRITE_PARAM,
2808 				data[0] | (data[1] << 8), 0);
2809 	} else {
2810 		r = dsi_vc_send_long(dsidev, channel,
2811 				type == DSS_DSI_CONTENT_GENERIC ?
2812 				MIPI_DSI_GENERIC_LONG_WRITE :
2813 				MIPI_DSI_DCS_LONG_WRITE, data, len, 0);
2814 	}
2815 
2816 	return r;
2817 }
2818 
2819 static int dsi_vc_dcs_write_nosync(struct omap_dss_device *dssdev, int channel,
2820 		u8 *data, int len)
2821 {
2822 	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2823 
2824 	return dsi_vc_write_nosync_common(dsidev, channel, data, len,
2825 			DSS_DSI_CONTENT_DCS);
2826 }
2827 
2828 static int dsi_vc_generic_write_nosync(struct omap_dss_device *dssdev, int channel,
2829 		u8 *data, int len)
2830 {
2831 	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2832 
2833 	return dsi_vc_write_nosync_common(dsidev, channel, data, len,
2834 			DSS_DSI_CONTENT_GENERIC);
2835 }
2836 
2837 static int dsi_vc_write_common(struct omap_dss_device *dssdev, int channel,
2838 		u8 *data, int len, enum dss_dsi_content_type type)
2839 {
2840 	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2841 	int r;
2842 
2843 	r = dsi_vc_write_nosync_common(dsidev, channel, data, len, type);
2844 	if (r)
2845 		goto err;
2846 
2847 	r = dsi_vc_send_bta_sync(dssdev, channel);
2848 	if (r)
2849 		goto err;
2850 
2851 	/* RX_FIFO_NOT_EMPTY */
2852 	if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
2853 		DSSERR("rx fifo not empty after write, dumping data:\n");
2854 		dsi_vc_flush_receive_data(dsidev, channel);
2855 		r = -EIO;
2856 		goto err;
2857 	}
2858 
2859 	return 0;
2860 err:
2861 	DSSERR("dsi_vc_write_common(ch %d, cmd 0x%02x, len %d) failed\n",
2862 			channel, data[0], len);
2863 	return r;
2864 }
2865 
2866 static int dsi_vc_dcs_write(struct omap_dss_device *dssdev, int channel, u8 *data,
2867 		int len)
2868 {
2869 	return dsi_vc_write_common(dssdev, channel, data, len,
2870 			DSS_DSI_CONTENT_DCS);
2871 }
2872 
2873 static int dsi_vc_generic_write(struct omap_dss_device *dssdev, int channel, u8 *data,
2874 		int len)
2875 {
2876 	return dsi_vc_write_common(dssdev, channel, data, len,
2877 			DSS_DSI_CONTENT_GENERIC);
2878 }
2879 
2880 static int dsi_vc_dcs_send_read_request(struct platform_device *dsidev,
2881 		int channel, u8 dcs_cmd)
2882 {
2883 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2884 	int r;
2885 
2886 	if (dsi->debug_read)
2887 		DSSDBG("dsi_vc_dcs_send_read_request(ch%d, dcs_cmd %x)\n",
2888 			channel, dcs_cmd);
2889 
2890 	r = dsi_vc_send_short(dsidev, channel, MIPI_DSI_DCS_READ, dcs_cmd, 0);
2891 	if (r) {
2892 		DSSERR("dsi_vc_dcs_send_read_request(ch %d, cmd 0x%02x)"
2893 			" failed\n", channel, dcs_cmd);
2894 		return r;
2895 	}
2896 
2897 	return 0;
2898 }
2899 
2900 static int dsi_vc_generic_send_read_request(struct platform_device *dsidev,
2901 		int channel, u8 *reqdata, int reqlen)
2902 {
2903 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2904 	u16 data;
2905 	u8 data_type;
2906 	int r;
2907 
2908 	if (dsi->debug_read)
2909 		DSSDBG("dsi_vc_generic_send_read_request(ch %d, reqlen %d)\n",
2910 			channel, reqlen);
2911 
2912 	if (reqlen == 0) {
2913 		data_type = MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM;
2914 		data = 0;
2915 	} else if (reqlen == 1) {
2916 		data_type = MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM;
2917 		data = reqdata[0];
2918 	} else if (reqlen == 2) {
2919 		data_type = MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM;
2920 		data = reqdata[0] | (reqdata[1] << 8);
2921 	} else {
2922 		BUG();
2923 		return -EINVAL;
2924 	}
2925 
2926 	r = dsi_vc_send_short(dsidev, channel, data_type, data, 0);
2927 	if (r) {
2928 		DSSERR("dsi_vc_generic_send_read_request(ch %d, reqlen %d)"
2929 			" failed\n", channel, reqlen);
2930 		return r;
2931 	}
2932 
2933 	return 0;
2934 }
2935 
2936 static int dsi_vc_read_rx_fifo(struct platform_device *dsidev, int channel,
2937 		u8 *buf, int buflen, enum dss_dsi_content_type type)
2938 {
2939 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2940 	u32 val;
2941 	u8 dt;
2942 	int r;
2943 
2944 	/* RX_FIFO_NOT_EMPTY */
2945 	if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20) == 0) {
2946 		DSSERR("RX fifo empty when trying to read.\n");
2947 		r = -EIO;
2948 		goto err;
2949 	}
2950 
2951 	val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));
2952 	if (dsi->debug_read)
2953 		DSSDBG("\theader: %08x\n", val);
2954 	dt = FLD_GET(val, 5, 0);
2955 	if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) {
2956 		u16 err = FLD_GET(val, 23, 8);
2957 		dsi_show_rx_ack_with_err(err);
2958 		r = -EIO;
2959 		goto err;
2960 
2961 	} else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
2962 			MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE :
2963 			MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE)) {
2964 		u8 data = FLD_GET(val, 15, 8);
2965 		if (dsi->debug_read)
2966 			DSSDBG("\t%s short response, 1 byte: %02x\n",
2967 				type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
2968 				"DCS", data);
2969 
2970 		if (buflen < 1) {
2971 			r = -EIO;
2972 			goto err;
2973 		}
2974 
2975 		buf[0] = data;
2976 
2977 		return 1;
2978 	} else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
2979 			MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE :
2980 			MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE)) {
2981 		u16 data = FLD_GET(val, 23, 8);
2982 		if (dsi->debug_read)
2983 			DSSDBG("\t%s short response, 2 byte: %04x\n",
2984 				type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
2985 				"DCS", data);
2986 
2987 		if (buflen < 2) {
2988 			r = -EIO;
2989 			goto err;
2990 		}
2991 
2992 		buf[0] = data & 0xff;
2993 		buf[1] = (data >> 8) & 0xff;
2994 
2995 		return 2;
2996 	} else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
2997 			MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE :
2998 			MIPI_DSI_RX_DCS_LONG_READ_RESPONSE)) {
2999 		int w;
3000 		int len = FLD_GET(val, 23, 8);
3001 		if (dsi->debug_read)
3002 			DSSDBG("\t%s long response, len %d\n",
3003 				type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
3004 				"DCS", len);
3005 
3006 		if (len > buflen) {
3007 			r = -EIO;
3008 			goto err;
3009 		}
3010 
3011 		/* two byte checksum ends the packet, not included in len */
3012 		for (w = 0; w < len + 2;) {
3013 			int b;
3014 			val = dsi_read_reg(dsidev,
3015 				DSI_VC_SHORT_PACKET_HEADER(channel));
3016 			if (dsi->debug_read)
3017 				DSSDBG("\t\t%02x %02x %02x %02x\n",
3018 						(val >> 0) & 0xff,
3019 						(val >> 8) & 0xff,
3020 						(val >> 16) & 0xff,
3021 						(val >> 24) & 0xff);
3022 
3023 			for (b = 0; b < 4; ++b) {
3024 				if (w < len)
3025 					buf[w] = (val >> (b * 8)) & 0xff;
3026 				/* we discard the 2 byte checksum */
3027 				++w;
3028 			}
3029 		}
3030 
3031 		return len;
3032 	} else {
3033 		DSSERR("\tunknown datatype 0x%02x\n", dt);
3034 		r = -EIO;
3035 		goto err;
3036 	}
3037 
3038 err:
3039 	DSSERR("dsi_vc_read_rx_fifo(ch %d type %s) failed\n", channel,
3040 		type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" : "DCS");
3041 
3042 	return r;
3043 }
3044 
3045 static int dsi_vc_dcs_read(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
3046 		u8 *buf, int buflen)
3047 {
3048 	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3049 	int r;
3050 
3051 	r = dsi_vc_dcs_send_read_request(dsidev, channel, dcs_cmd);
3052 	if (r)
3053 		goto err;
3054 
3055 	r = dsi_vc_send_bta_sync(dssdev, channel);
3056 	if (r)
3057 		goto err;
3058 
3059 	r = dsi_vc_read_rx_fifo(dsidev, channel, buf, buflen,
3060 		DSS_DSI_CONTENT_DCS);
3061 	if (r < 0)
3062 		goto err;
3063 
3064 	if (r != buflen) {
3065 		r = -EIO;
3066 		goto err;
3067 	}
3068 
3069 	return 0;
3070 err:
3071 	DSSERR("dsi_vc_dcs_read(ch %d, cmd 0x%02x) failed\n", channel, dcs_cmd);
3072 	return r;
3073 }
3074 
3075 static int dsi_vc_generic_read(struct omap_dss_device *dssdev, int channel,
3076 		u8 *reqdata, int reqlen, u8 *buf, int buflen)
3077 {
3078 	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3079 	int r;
3080 
3081 	r = dsi_vc_generic_send_read_request(dsidev, channel, reqdata, reqlen);
3082 	if (r)
3083 		return r;
3084 
3085 	r = dsi_vc_send_bta_sync(dssdev, channel);
3086 	if (r)
3087 		return r;
3088 
3089 	r = dsi_vc_read_rx_fifo(dsidev, channel, buf, buflen,
3090 		DSS_DSI_CONTENT_GENERIC);
3091 	if (r < 0)
3092 		return r;
3093 
3094 	if (r != buflen) {
3095 		r = -EIO;
3096 		return r;
3097 	}
3098 
3099 	return 0;
3100 }
3101 
3102 static int dsi_vc_set_max_rx_packet_size(struct omap_dss_device *dssdev, int channel,
3103 		u16 len)
3104 {
3105 	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3106 
3107 	return dsi_vc_send_short(dsidev, channel,
3108 			MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE, len, 0);
3109 }
3110 
3111 static int dsi_enter_ulps(struct platform_device *dsidev)
3112 {
3113 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3114 	DECLARE_COMPLETION_ONSTACK(completion);
3115 	int r, i;
3116 	unsigned mask;
3117 
3118 	DSSDBG("Entering ULPS");
3119 
3120 	WARN_ON(!dsi_bus_is_locked(dsidev));
3121 
3122 	WARN_ON(dsi->ulps_enabled);
3123 
3124 	if (dsi->ulps_enabled)
3125 		return 0;
3126 
3127 	/* DDR_CLK_ALWAYS_ON */
3128 	if (REG_GET(dsidev, DSI_CLK_CTRL, 13, 13)) {
3129 		dsi_if_enable(dsidev, 0);
3130 		REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 13, 13);
3131 		dsi_if_enable(dsidev, 1);
3132 	}
3133 
3134 	dsi_sync_vc(dsidev, 0);
3135 	dsi_sync_vc(dsidev, 1);
3136 	dsi_sync_vc(dsidev, 2);
3137 	dsi_sync_vc(dsidev, 3);
3138 
3139 	dsi_force_tx_stop_mode_io(dsidev);
3140 
3141 	dsi_vc_enable(dsidev, 0, false);
3142 	dsi_vc_enable(dsidev, 1, false);
3143 	dsi_vc_enable(dsidev, 2, false);
3144 	dsi_vc_enable(dsidev, 3, false);
3145 
3146 	if (REG_GET(dsidev, DSI_COMPLEXIO_CFG2, 16, 16)) {	/* HS_BUSY */
3147 		DSSERR("HS busy when enabling ULPS\n");
3148 		return -EIO;
3149 	}
3150 
3151 	if (REG_GET(dsidev, DSI_COMPLEXIO_CFG2, 17, 17)) {	/* LP_BUSY */
3152 		DSSERR("LP busy when enabling ULPS\n");
3153 		return -EIO;
3154 	}
3155 
3156 	r = dsi_register_isr_cio(dsidev, dsi_completion_handler, &completion,
3157 			DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
3158 	if (r)
3159 		return r;
3160 
3161 	mask = 0;
3162 
3163 	for (i = 0; i < dsi->num_lanes_supported; ++i) {
3164 		if (dsi->lanes[i].function == DSI_LANE_UNUSED)
3165 			continue;
3166 		mask |= 1 << i;
3167 	}
3168 	/* Assert TxRequestEsc for data lanes and TxUlpsClk for clk lane */
3169 	/* LANEx_ULPS_SIG2 */
3170 	REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG2, mask, 9, 5);
3171 
3172 	/* flush posted write and wait for SCP interface to finish the write */
3173 	dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG2);
3174 
3175 	if (wait_for_completion_timeout(&completion,
3176 				msecs_to_jiffies(1000)) == 0) {
3177 		DSSERR("ULPS enable timeout\n");
3178 		r = -EIO;
3179 		goto err;
3180 	}
3181 
3182 	dsi_unregister_isr_cio(dsidev, dsi_completion_handler, &completion,
3183 			DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
3184 
3185 	/* Reset LANEx_ULPS_SIG2 */
3186 	REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG2, 0, 9, 5);
3187 
3188 	/* flush posted write and wait for SCP interface to finish the write */
3189 	dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG2);
3190 
3191 	dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_ULPS);
3192 
3193 	dsi_if_enable(dsidev, false);
3194 
3195 	dsi->ulps_enabled = true;
3196 
3197 	return 0;
3198 
3199 err:
3200 	dsi_unregister_isr_cio(dsidev, dsi_completion_handler, &completion,
3201 			DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
3202 	return r;
3203 }
3204 
3205 static void dsi_set_lp_rx_timeout(struct platform_device *dsidev,
3206 		unsigned ticks, bool x4, bool x16)
3207 {
3208 	unsigned long fck;
3209 	unsigned long total_ticks;
3210 	u32 r;
3211 
3212 	BUG_ON(ticks > 0x1fff);
3213 
3214 	/* ticks in DSI_FCK */
3215 	fck = dsi_fclk_rate(dsidev);
3216 
3217 	r = dsi_read_reg(dsidev, DSI_TIMING2);
3218 	r = FLD_MOD(r, 1, 15, 15);	/* LP_RX_TO */
3219 	r = FLD_MOD(r, x16 ? 1 : 0, 14, 14);	/* LP_RX_TO_X16 */
3220 	r = FLD_MOD(r, x4 ? 1 : 0, 13, 13);	/* LP_RX_TO_X4 */
3221 	r = FLD_MOD(r, ticks, 12, 0);	/* LP_RX_COUNTER */
3222 	dsi_write_reg(dsidev, DSI_TIMING2, r);
3223 
3224 	total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
3225 
3226 	DSSDBG("LP_RX_TO %lu ticks (%#x%s%s) = %lu ns\n",
3227 			total_ticks,
3228 			ticks, x4 ? " x4" : "", x16 ? " x16" : "",
3229 			(total_ticks * 1000) / (fck / 1000 / 1000));
3230 }
3231 
3232 static void dsi_set_ta_timeout(struct platform_device *dsidev, unsigned ticks,
3233 		bool x8, bool x16)
3234 {
3235 	unsigned long fck;
3236 	unsigned long total_ticks;
3237 	u32 r;
3238 
3239 	BUG_ON(ticks > 0x1fff);
3240 
3241 	/* ticks in DSI_FCK */
3242 	fck = dsi_fclk_rate(dsidev);
3243 
3244 	r = dsi_read_reg(dsidev, DSI_TIMING1);
3245 	r = FLD_MOD(r, 1, 31, 31);	/* TA_TO */
3246 	r = FLD_MOD(r, x16 ? 1 : 0, 30, 30);	/* TA_TO_X16 */
3247 	r = FLD_MOD(r, x8 ? 1 : 0, 29, 29);	/* TA_TO_X8 */
3248 	r = FLD_MOD(r, ticks, 28, 16);	/* TA_TO_COUNTER */
3249 	dsi_write_reg(dsidev, DSI_TIMING1, r);
3250 
3251 	total_ticks = ticks * (x16 ? 16 : 1) * (x8 ? 8 : 1);
3252 
3253 	DSSDBG("TA_TO %lu ticks (%#x%s%s) = %lu ns\n",
3254 			total_ticks,
3255 			ticks, x8 ? " x8" : "", x16 ? " x16" : "",
3256 			(total_ticks * 1000) / (fck / 1000 / 1000));
3257 }
3258 
3259 static void dsi_set_stop_state_counter(struct platform_device *dsidev,
3260 		unsigned ticks, bool x4, bool x16)
3261 {
3262 	unsigned long fck;
3263 	unsigned long total_ticks;
3264 	u32 r;
3265 
3266 	BUG_ON(ticks > 0x1fff);
3267 
3268 	/* ticks in DSI_FCK */
3269 	fck = dsi_fclk_rate(dsidev);
3270 
3271 	r = dsi_read_reg(dsidev, DSI_TIMING1);
3272 	r = FLD_MOD(r, 1, 15, 15);	/* FORCE_TX_STOP_MODE_IO */
3273 	r = FLD_MOD(r, x16 ? 1 : 0, 14, 14);	/* STOP_STATE_X16_IO */
3274 	r = FLD_MOD(r, x4 ? 1 : 0, 13, 13);	/* STOP_STATE_X4_IO */
3275 	r = FLD_MOD(r, ticks, 12, 0);	/* STOP_STATE_COUNTER_IO */
3276 	dsi_write_reg(dsidev, DSI_TIMING1, r);
3277 
3278 	total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
3279 
3280 	DSSDBG("STOP_STATE_COUNTER %lu ticks (%#x%s%s) = %lu ns\n",
3281 			total_ticks,
3282 			ticks, x4 ? " x4" : "", x16 ? " x16" : "",
3283 			(total_ticks * 1000) / (fck / 1000 / 1000));
3284 }
3285 
3286 static void dsi_set_hs_tx_timeout(struct platform_device *dsidev,
3287 		unsigned ticks, bool x4, bool x16)
3288 {
3289 	unsigned long fck;
3290 	unsigned long total_ticks;
3291 	u32 r;
3292 
3293 	BUG_ON(ticks > 0x1fff);
3294 
3295 	/* ticks in TxByteClkHS */
3296 	fck = dsi_get_txbyteclkhs(dsidev);
3297 
3298 	r = dsi_read_reg(dsidev, DSI_TIMING2);
3299 	r = FLD_MOD(r, 1, 31, 31);	/* HS_TX_TO */
3300 	r = FLD_MOD(r, x16 ? 1 : 0, 30, 30);	/* HS_TX_TO_X16 */
3301 	r = FLD_MOD(r, x4 ? 1 : 0, 29, 29);	/* HS_TX_TO_X8 (4 really) */
3302 	r = FLD_MOD(r, ticks, 28, 16);	/* HS_TX_TO_COUNTER */
3303 	dsi_write_reg(dsidev, DSI_TIMING2, r);
3304 
3305 	total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
3306 
3307 	DSSDBG("HS_TX_TO %lu ticks (%#x%s%s) = %lu ns\n",
3308 			total_ticks,
3309 			ticks, x4 ? " x4" : "", x16 ? " x16" : "",
3310 			(total_ticks * 1000) / (fck / 1000 / 1000));
3311 }
3312 
3313 static void dsi_config_vp_num_line_buffers(struct platform_device *dsidev)
3314 {
3315 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3316 	int num_line_buffers;
3317 
3318 	if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
3319 		int bpp = dsi_get_pixel_size(dsi->pix_fmt);
3320 		struct omap_video_timings *timings = &dsi->timings;
3321 		/*
3322 		 * Don't use line buffers if width is greater than the video
3323 		 * port's line buffer size
3324 		 */
3325 		if (dsi->line_buffer_size <= timings->x_res * bpp / 8)
3326 			num_line_buffers = 0;
3327 		else
3328 			num_line_buffers = 2;
3329 	} else {
3330 		/* Use maximum number of line buffers in command mode */
3331 		num_line_buffers = 2;
3332 	}
3333 
3334 	/* LINE_BUFFER */
3335 	REG_FLD_MOD(dsidev, DSI_CTRL, num_line_buffers, 13, 12);
3336 }
3337 
3338 static void dsi_config_vp_sync_events(struct platform_device *dsidev)
3339 {
3340 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3341 	bool sync_end;
3342 	u32 r;
3343 
3344 	if (dsi->vm_timings.trans_mode == OMAP_DSS_DSI_PULSE_MODE)
3345 		sync_end = true;
3346 	else
3347 		sync_end = false;
3348 
3349 	r = dsi_read_reg(dsidev, DSI_CTRL);
3350 	r = FLD_MOD(r, 1, 9, 9);		/* VP_DE_POL */
3351 	r = FLD_MOD(r, 1, 10, 10);		/* VP_HSYNC_POL */
3352 	r = FLD_MOD(r, 1, 11, 11);		/* VP_VSYNC_POL */
3353 	r = FLD_MOD(r, 1, 15, 15);		/* VP_VSYNC_START */
3354 	r = FLD_MOD(r, sync_end, 16, 16);	/* VP_VSYNC_END */
3355 	r = FLD_MOD(r, 1, 17, 17);		/* VP_HSYNC_START */
3356 	r = FLD_MOD(r, sync_end, 18, 18);	/* VP_HSYNC_END */
3357 	dsi_write_reg(dsidev, DSI_CTRL, r);
3358 }
3359 
3360 static void dsi_config_blanking_modes(struct platform_device *dsidev)
3361 {
3362 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3363 	int blanking_mode = dsi->vm_timings.blanking_mode;
3364 	int hfp_blanking_mode = dsi->vm_timings.hfp_blanking_mode;
3365 	int hbp_blanking_mode = dsi->vm_timings.hbp_blanking_mode;
3366 	int hsa_blanking_mode = dsi->vm_timings.hsa_blanking_mode;
3367 	u32 r;
3368 
3369 	/*
3370 	 * 0 = TX FIFO packets sent or LPS in corresponding blanking periods
3371 	 * 1 = Long blanking packets are sent in corresponding blanking periods
3372 	 */
3373 	r = dsi_read_reg(dsidev, DSI_CTRL);
3374 	r = FLD_MOD(r, blanking_mode, 20, 20);		/* BLANKING_MODE */
3375 	r = FLD_MOD(r, hfp_blanking_mode, 21, 21);	/* HFP_BLANKING */
3376 	r = FLD_MOD(r, hbp_blanking_mode, 22, 22);	/* HBP_BLANKING */
3377 	r = FLD_MOD(r, hsa_blanking_mode, 23, 23);	/* HSA_BLANKING */
3378 	dsi_write_reg(dsidev, DSI_CTRL, r);
3379 }
3380 
3381 /*
3382  * According to section 'HS Command Mode Interleaving' in OMAP TRM, Scenario 3
3383  * results in maximum transition time for data and clock lanes to enter and
3384  * exit HS mode. Hence, this is the scenario where the least amount of command
3385  * mode data can be interleaved. We program the minimum amount of TXBYTECLKHS
3386  * clock cycles that can be used to interleave command mode data in HS so that
3387  * all scenarios are satisfied.
3388  */
3389 static int dsi_compute_interleave_hs(int blank, bool ddr_alwon, int enter_hs,
3390 		int exit_hs, int exiths_clk, int ddr_pre, int ddr_post)
3391 {
3392 	int transition;
3393 
3394 	/*
3395 	 * If DDR_CLK_ALWAYS_ON is set, we need to consider HS mode transition
3396 	 * time of data lanes only, if it isn't set, we need to consider HS
3397 	 * transition time of both data and clock lanes. HS transition time
3398 	 * of Scenario 3 is considered.
3399 	 */
3400 	if (ddr_alwon) {
3401 		transition = enter_hs + exit_hs + max(enter_hs, 2) + 1;
3402 	} else {
3403 		int trans1, trans2;
3404 		trans1 = ddr_pre + enter_hs + exit_hs + max(enter_hs, 2) + 1;
3405 		trans2 = ddr_pre + enter_hs + exiths_clk + ddr_post + ddr_pre +
3406 				enter_hs + 1;
3407 		transition = max(trans1, trans2);
3408 	}
3409 
3410 	return blank > transition ? blank - transition : 0;
3411 }
3412 
3413 /*
3414  * According to section 'LP Command Mode Interleaving' in OMAP TRM, Scenario 1
3415  * results in maximum transition time for data lanes to enter and exit LP mode.
3416  * Hence, this is the scenario where the least amount of command mode data can
3417  * be interleaved. We program the minimum amount of bytes that can be
3418  * interleaved in LP so that all scenarios are satisfied.
3419  */
3420 static int dsi_compute_interleave_lp(int blank, int enter_hs, int exit_hs,
3421 		int lp_clk_div, int tdsi_fclk)
3422 {
3423 	int trans_lp;	/* time required for a LP transition, in TXBYTECLKHS */
3424 	int tlp_avail;	/* time left for interleaving commands, in CLKIN4DDR */
3425 	int ttxclkesc;	/* period of LP transmit escape clock, in CLKIN4DDR */
3426 	int thsbyte_clk = 16;	/* Period of TXBYTECLKHS clock, in CLKIN4DDR */
3427 	int lp_inter;	/* cmd mode data that can be interleaved, in bytes */
3428 
3429 	/* maximum LP transition time according to Scenario 1 */
3430 	trans_lp = exit_hs + max(enter_hs, 2) + 1;
3431 
3432 	/* CLKIN4DDR = 16 * TXBYTECLKHS */
3433 	tlp_avail = thsbyte_clk * (blank - trans_lp);
3434 
3435 	ttxclkesc = tdsi_fclk * lp_clk_div;
3436 
3437 	lp_inter = ((tlp_avail - 8 * thsbyte_clk - 5 * tdsi_fclk) / ttxclkesc -
3438 			26) / 16;
3439 
3440 	return max(lp_inter, 0);
3441 }
3442 
3443 static void dsi_config_cmd_mode_interleaving(struct platform_device *dsidev)
3444 {
3445 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3446 	int blanking_mode;
3447 	int hfp_blanking_mode, hbp_blanking_mode, hsa_blanking_mode;
3448 	int hsa, hfp, hbp, width_bytes, bllp, lp_clk_div;
3449 	int ddr_clk_pre, ddr_clk_post, enter_hs_mode_lat, exit_hs_mode_lat;
3450 	int tclk_trail, ths_exit, exiths_clk;
3451 	bool ddr_alwon;
3452 	struct omap_video_timings *timings = &dsi->timings;
3453 	int bpp = dsi_get_pixel_size(dsi->pix_fmt);
3454 	int ndl = dsi->num_lanes_used - 1;
3455 	int dsi_fclk_hsdiv = dsi->user_dsi_cinfo.mX[HSDIV_DSI] + 1;
3456 	int hsa_interleave_hs = 0, hsa_interleave_lp = 0;
3457 	int hfp_interleave_hs = 0, hfp_interleave_lp = 0;
3458 	int hbp_interleave_hs = 0, hbp_interleave_lp = 0;
3459 	int bl_interleave_hs = 0, bl_interleave_lp = 0;
3460 	u32 r;
3461 
3462 	r = dsi_read_reg(dsidev, DSI_CTRL);
3463 	blanking_mode = FLD_GET(r, 20, 20);
3464 	hfp_blanking_mode = FLD_GET(r, 21, 21);
3465 	hbp_blanking_mode = FLD_GET(r, 22, 22);
3466 	hsa_blanking_mode = FLD_GET(r, 23, 23);
3467 
3468 	r = dsi_read_reg(dsidev, DSI_VM_TIMING1);
3469 	hbp = FLD_GET(r, 11, 0);
3470 	hfp = FLD_GET(r, 23, 12);
3471 	hsa = FLD_GET(r, 31, 24);
3472 
3473 	r = dsi_read_reg(dsidev, DSI_CLK_TIMING);
3474 	ddr_clk_post = FLD_GET(r, 7, 0);
3475 	ddr_clk_pre = FLD_GET(r, 15, 8);
3476 
3477 	r = dsi_read_reg(dsidev, DSI_VM_TIMING7);
3478 	exit_hs_mode_lat = FLD_GET(r, 15, 0);
3479 	enter_hs_mode_lat = FLD_GET(r, 31, 16);
3480 
3481 	r = dsi_read_reg(dsidev, DSI_CLK_CTRL);
3482 	lp_clk_div = FLD_GET(r, 12, 0);
3483 	ddr_alwon = FLD_GET(r, 13, 13);
3484 
3485 	r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0);
3486 	ths_exit = FLD_GET(r, 7, 0);
3487 
3488 	r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1);
3489 	tclk_trail = FLD_GET(r, 15, 8);
3490 
3491 	exiths_clk = ths_exit + tclk_trail;
3492 
3493 	width_bytes = DIV_ROUND_UP(timings->x_res * bpp, 8);
3494 	bllp = hbp + hfp + hsa + DIV_ROUND_UP(width_bytes + 6, ndl);
3495 
3496 	if (!hsa_blanking_mode) {
3497 		hsa_interleave_hs = dsi_compute_interleave_hs(hsa, ddr_alwon,
3498 					enter_hs_mode_lat, exit_hs_mode_lat,
3499 					exiths_clk, ddr_clk_pre, ddr_clk_post);
3500 		hsa_interleave_lp = dsi_compute_interleave_lp(hsa,
3501 					enter_hs_mode_lat, exit_hs_mode_lat,
3502 					lp_clk_div, dsi_fclk_hsdiv);
3503 	}
3504 
3505 	if (!hfp_blanking_mode) {
3506 		hfp_interleave_hs = dsi_compute_interleave_hs(hfp, ddr_alwon,
3507 					enter_hs_mode_lat, exit_hs_mode_lat,
3508 					exiths_clk, ddr_clk_pre, ddr_clk_post);
3509 		hfp_interleave_lp = dsi_compute_interleave_lp(hfp,
3510 					enter_hs_mode_lat, exit_hs_mode_lat,
3511 					lp_clk_div, dsi_fclk_hsdiv);
3512 	}
3513 
3514 	if (!hbp_blanking_mode) {
3515 		hbp_interleave_hs = dsi_compute_interleave_hs(hbp, ddr_alwon,
3516 					enter_hs_mode_lat, exit_hs_mode_lat,
3517 					exiths_clk, ddr_clk_pre, ddr_clk_post);
3518 
3519 		hbp_interleave_lp = dsi_compute_interleave_lp(hbp,
3520 					enter_hs_mode_lat, exit_hs_mode_lat,
3521 					lp_clk_div, dsi_fclk_hsdiv);
3522 	}
3523 
3524 	if (!blanking_mode) {
3525 		bl_interleave_hs = dsi_compute_interleave_hs(bllp, ddr_alwon,
3526 					enter_hs_mode_lat, exit_hs_mode_lat,
3527 					exiths_clk, ddr_clk_pre, ddr_clk_post);
3528 
3529 		bl_interleave_lp = dsi_compute_interleave_lp(bllp,
3530 					enter_hs_mode_lat, exit_hs_mode_lat,
3531 					lp_clk_div, dsi_fclk_hsdiv);
3532 	}
3533 
3534 	DSSDBG("DSI HS interleaving(TXBYTECLKHS) HSA %d, HFP %d, HBP %d, BLLP %d\n",
3535 		hsa_interleave_hs, hfp_interleave_hs, hbp_interleave_hs,
3536 		bl_interleave_hs);
3537 
3538 	DSSDBG("DSI LP interleaving(bytes) HSA %d, HFP %d, HBP %d, BLLP %d\n",
3539 		hsa_interleave_lp, hfp_interleave_lp, hbp_interleave_lp,
3540 		bl_interleave_lp);
3541 
3542 	r = dsi_read_reg(dsidev, DSI_VM_TIMING4);
3543 	r = FLD_MOD(r, hsa_interleave_hs, 23, 16);
3544 	r = FLD_MOD(r, hfp_interleave_hs, 15, 8);
3545 	r = FLD_MOD(r, hbp_interleave_hs, 7, 0);
3546 	dsi_write_reg(dsidev, DSI_VM_TIMING4, r);
3547 
3548 	r = dsi_read_reg(dsidev, DSI_VM_TIMING5);
3549 	r = FLD_MOD(r, hsa_interleave_lp, 23, 16);
3550 	r = FLD_MOD(r, hfp_interleave_lp, 15, 8);
3551 	r = FLD_MOD(r, hbp_interleave_lp, 7, 0);
3552 	dsi_write_reg(dsidev, DSI_VM_TIMING5, r);
3553 
3554 	r = dsi_read_reg(dsidev, DSI_VM_TIMING6);
3555 	r = FLD_MOD(r, bl_interleave_hs, 31, 15);
3556 	r = FLD_MOD(r, bl_interleave_lp, 16, 0);
3557 	dsi_write_reg(dsidev, DSI_VM_TIMING6, r);
3558 }
3559 
3560 static int dsi_proto_config(struct platform_device *dsidev)
3561 {
3562 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3563 	u32 r;
3564 	int buswidth = 0;
3565 
3566 	dsi_config_tx_fifo(dsidev, DSI_FIFO_SIZE_32,
3567 			DSI_FIFO_SIZE_32,
3568 			DSI_FIFO_SIZE_32,
3569 			DSI_FIFO_SIZE_32);
3570 
3571 	dsi_config_rx_fifo(dsidev, DSI_FIFO_SIZE_32,
3572 			DSI_FIFO_SIZE_32,
3573 			DSI_FIFO_SIZE_32,
3574 			DSI_FIFO_SIZE_32);
3575 
3576 	/* XXX what values for the timeouts? */
3577 	dsi_set_stop_state_counter(dsidev, 0x1000, false, false);
3578 	dsi_set_ta_timeout(dsidev, 0x1fff, true, true);
3579 	dsi_set_lp_rx_timeout(dsidev, 0x1fff, true, true);
3580 	dsi_set_hs_tx_timeout(dsidev, 0x1fff, true, true);
3581 
3582 	switch (dsi_get_pixel_size(dsi->pix_fmt)) {
3583 	case 16:
3584 		buswidth = 0;
3585 		break;
3586 	case 18:
3587 		buswidth = 1;
3588 		break;
3589 	case 24:
3590 		buswidth = 2;
3591 		break;
3592 	default:
3593 		BUG();
3594 		return -EINVAL;
3595 	}
3596 
3597 	r = dsi_read_reg(dsidev, DSI_CTRL);
3598 	r = FLD_MOD(r, 1, 1, 1);	/* CS_RX_EN */
3599 	r = FLD_MOD(r, 1, 2, 2);	/* ECC_RX_EN */
3600 	r = FLD_MOD(r, 1, 3, 3);	/* TX_FIFO_ARBITRATION */
3601 	r = FLD_MOD(r, 1, 4, 4);	/* VP_CLK_RATIO, always 1, see errata*/
3602 	r = FLD_MOD(r, buswidth, 7, 6); /* VP_DATA_BUS_WIDTH */
3603 	r = FLD_MOD(r, 0, 8, 8);	/* VP_CLK_POL */
3604 	r = FLD_MOD(r, 1, 14, 14);	/* TRIGGER_RESET_MODE */
3605 	r = FLD_MOD(r, 1, 19, 19);	/* EOT_ENABLE */
3606 	if (!dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC)) {
3607 		r = FLD_MOD(r, 1, 24, 24);	/* DCS_CMD_ENABLE */
3608 		/* DCS_CMD_CODE, 1=start, 0=continue */
3609 		r = FLD_MOD(r, 0, 25, 25);
3610 	}
3611 
3612 	dsi_write_reg(dsidev, DSI_CTRL, r);
3613 
3614 	dsi_config_vp_num_line_buffers(dsidev);
3615 
3616 	if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
3617 		dsi_config_vp_sync_events(dsidev);
3618 		dsi_config_blanking_modes(dsidev);
3619 		dsi_config_cmd_mode_interleaving(dsidev);
3620 	}
3621 
3622 	dsi_vc_initial_config(dsidev, 0);
3623 	dsi_vc_initial_config(dsidev, 1);
3624 	dsi_vc_initial_config(dsidev, 2);
3625 	dsi_vc_initial_config(dsidev, 3);
3626 
3627 	return 0;
3628 }
3629 
3630 static void dsi_proto_timings(struct platform_device *dsidev)
3631 {
3632 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3633 	unsigned tlpx, tclk_zero, tclk_prepare;
3634 	unsigned tclk_pre, tclk_post;
3635 	unsigned ths_prepare, ths_prepare_ths_zero, ths_zero;
3636 	unsigned ths_trail, ths_exit;
3637 	unsigned ddr_clk_pre, ddr_clk_post;
3638 	unsigned enter_hs_mode_lat, exit_hs_mode_lat;
3639 	unsigned ths_eot;
3640 	int ndl = dsi->num_lanes_used - 1;
3641 	u32 r;
3642 
3643 	r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0);
3644 	ths_prepare = FLD_GET(r, 31, 24);
3645 	ths_prepare_ths_zero = FLD_GET(r, 23, 16);
3646 	ths_zero = ths_prepare_ths_zero - ths_prepare;
3647 	ths_trail = FLD_GET(r, 15, 8);
3648 	ths_exit = FLD_GET(r, 7, 0);
3649 
3650 	r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1);
3651 	tlpx = FLD_GET(r, 20, 16) * 2;
3652 	tclk_zero = FLD_GET(r, 7, 0);
3653 
3654 	r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG2);
3655 	tclk_prepare = FLD_GET(r, 7, 0);
3656 
3657 	/* min 8*UI */
3658 	tclk_pre = 20;
3659 	/* min 60ns + 52*UI */
3660 	tclk_post = ns2ddr(dsidev, 60) + 26;
3661 
3662 	ths_eot = DIV_ROUND_UP(4, ndl);
3663 
3664 	ddr_clk_pre = DIV_ROUND_UP(tclk_pre + tlpx + tclk_zero + tclk_prepare,
3665 			4);
3666 	ddr_clk_post = DIV_ROUND_UP(tclk_post + ths_trail, 4) + ths_eot;
3667 
3668 	BUG_ON(ddr_clk_pre == 0 || ddr_clk_pre > 255);
3669 	BUG_ON(ddr_clk_post == 0 || ddr_clk_post > 255);
3670 
3671 	r = dsi_read_reg(dsidev, DSI_CLK_TIMING);
3672 	r = FLD_MOD(r, ddr_clk_pre, 15, 8);
3673 	r = FLD_MOD(r, ddr_clk_post, 7, 0);
3674 	dsi_write_reg(dsidev, DSI_CLK_TIMING, r);
3675 
3676 	DSSDBG("ddr_clk_pre %u, ddr_clk_post %u\n",
3677 			ddr_clk_pre,
3678 			ddr_clk_post);
3679 
3680 	enter_hs_mode_lat = 1 + DIV_ROUND_UP(tlpx, 4) +
3681 		DIV_ROUND_UP(ths_prepare, 4) +
3682 		DIV_ROUND_UP(ths_zero + 3, 4);
3683 
3684 	exit_hs_mode_lat = DIV_ROUND_UP(ths_trail + ths_exit, 4) + 1 + ths_eot;
3685 
3686 	r = FLD_VAL(enter_hs_mode_lat, 31, 16) |
3687 		FLD_VAL(exit_hs_mode_lat, 15, 0);
3688 	dsi_write_reg(dsidev, DSI_VM_TIMING7, r);
3689 
3690 	DSSDBG("enter_hs_mode_lat %u, exit_hs_mode_lat %u\n",
3691 			enter_hs_mode_lat, exit_hs_mode_lat);
3692 
3693 	 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
3694 		/* TODO: Implement a video mode check_timings function */
3695 		int hsa = dsi->vm_timings.hsa;
3696 		int hfp = dsi->vm_timings.hfp;
3697 		int hbp = dsi->vm_timings.hbp;
3698 		int vsa = dsi->vm_timings.vsa;
3699 		int vfp = dsi->vm_timings.vfp;
3700 		int vbp = dsi->vm_timings.vbp;
3701 		int window_sync = dsi->vm_timings.window_sync;
3702 		bool hsync_end;
3703 		struct omap_video_timings *timings = &dsi->timings;
3704 		int bpp = dsi_get_pixel_size(dsi->pix_fmt);
3705 		int tl, t_he, width_bytes;
3706 
3707 		hsync_end = dsi->vm_timings.trans_mode == OMAP_DSS_DSI_PULSE_MODE;
3708 		t_he = hsync_end ?
3709 			((hsa == 0 && ndl == 3) ? 1 : DIV_ROUND_UP(4, ndl)) : 0;
3710 
3711 		width_bytes = DIV_ROUND_UP(timings->x_res * bpp, 8);
3712 
3713 		/* TL = t_HS + HSA + t_HE + HFP + ceil((WC + 6) / NDL) + HBP */
3714 		tl = DIV_ROUND_UP(4, ndl) + (hsync_end ? hsa : 0) + t_he + hfp +
3715 			DIV_ROUND_UP(width_bytes + 6, ndl) + hbp;
3716 
3717 		DSSDBG("HBP: %d, HFP: %d, HSA: %d, TL: %d TXBYTECLKHS\n", hbp,
3718 			hfp, hsync_end ? hsa : 0, tl);
3719 		DSSDBG("VBP: %d, VFP: %d, VSA: %d, VACT: %d lines\n", vbp, vfp,
3720 			vsa, timings->y_res);
3721 
3722 		r = dsi_read_reg(dsidev, DSI_VM_TIMING1);
3723 		r = FLD_MOD(r, hbp, 11, 0);	/* HBP */
3724 		r = FLD_MOD(r, hfp, 23, 12);	/* HFP */
3725 		r = FLD_MOD(r, hsync_end ? hsa : 0, 31, 24);	/* HSA */
3726 		dsi_write_reg(dsidev, DSI_VM_TIMING1, r);
3727 
3728 		r = dsi_read_reg(dsidev, DSI_VM_TIMING2);
3729 		r = FLD_MOD(r, vbp, 7, 0);	/* VBP */
3730 		r = FLD_MOD(r, vfp, 15, 8);	/* VFP */
3731 		r = FLD_MOD(r, vsa, 23, 16);	/* VSA */
3732 		r = FLD_MOD(r, window_sync, 27, 24);	/* WINDOW_SYNC */
3733 		dsi_write_reg(dsidev, DSI_VM_TIMING2, r);
3734 
3735 		r = dsi_read_reg(dsidev, DSI_VM_TIMING3);
3736 		r = FLD_MOD(r, timings->y_res, 14, 0);	/* VACT */
3737 		r = FLD_MOD(r, tl, 31, 16);		/* TL */
3738 		dsi_write_reg(dsidev, DSI_VM_TIMING3, r);
3739 	}
3740 }
3741 
3742 static int dsi_configure_pins(struct omap_dss_device *dssdev,
3743 		const struct omap_dsi_pin_config *pin_cfg)
3744 {
3745 	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3746 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3747 	int num_pins;
3748 	const int *pins;
3749 	struct dsi_lane_config lanes[DSI_MAX_NR_LANES];
3750 	int num_lanes;
3751 	int i;
3752 
3753 	static const enum dsi_lane_function functions[] = {
3754 		DSI_LANE_CLK,
3755 		DSI_LANE_DATA1,
3756 		DSI_LANE_DATA2,
3757 		DSI_LANE_DATA3,
3758 		DSI_LANE_DATA4,
3759 	};
3760 
3761 	num_pins = pin_cfg->num_pins;
3762 	pins = pin_cfg->pins;
3763 
3764 	if (num_pins < 4 || num_pins > dsi->num_lanes_supported * 2
3765 			|| num_pins % 2 != 0)
3766 		return -EINVAL;
3767 
3768 	for (i = 0; i < DSI_MAX_NR_LANES; ++i)
3769 		lanes[i].function = DSI_LANE_UNUSED;
3770 
3771 	num_lanes = 0;
3772 
3773 	for (i = 0; i < num_pins; i += 2) {
3774 		u8 lane, pol;
3775 		int dx, dy;
3776 
3777 		dx = pins[i];
3778 		dy = pins[i + 1];
3779 
3780 		if (dx < 0 || dx >= dsi->num_lanes_supported * 2)
3781 			return -EINVAL;
3782 
3783 		if (dy < 0 || dy >= dsi->num_lanes_supported * 2)
3784 			return -EINVAL;
3785 
3786 		if (dx & 1) {
3787 			if (dy != dx - 1)
3788 				return -EINVAL;
3789 			pol = 1;
3790 		} else {
3791 			if (dy != dx + 1)
3792 				return -EINVAL;
3793 			pol = 0;
3794 		}
3795 
3796 		lane = dx / 2;
3797 
3798 		lanes[lane].function = functions[i / 2];
3799 		lanes[lane].polarity = pol;
3800 		num_lanes++;
3801 	}
3802 
3803 	memcpy(dsi->lanes, lanes, sizeof(dsi->lanes));
3804 	dsi->num_lanes_used = num_lanes;
3805 
3806 	return 0;
3807 }
3808 
3809 static int dsi_enable_video_output(struct omap_dss_device *dssdev, int channel)
3810 {
3811 	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3812 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3813 	struct omap_overlay_manager *mgr = dsi->output.manager;
3814 	int bpp = dsi_get_pixel_size(dsi->pix_fmt);
3815 	struct omap_dss_device *out = &dsi->output;
3816 	u8 data_type;
3817 	u16 word_count;
3818 	int r;
3819 
3820 	if (out->manager == NULL) {
3821 		DSSERR("failed to enable display: no output/manager\n");
3822 		return -ENODEV;
3823 	}
3824 
3825 	r = dsi_display_init_dispc(dsidev, mgr);
3826 	if (r)
3827 		goto err_init_dispc;
3828 
3829 	if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
3830 		switch (dsi->pix_fmt) {
3831 		case OMAP_DSS_DSI_FMT_RGB888:
3832 			data_type = MIPI_DSI_PACKED_PIXEL_STREAM_24;
3833 			break;
3834 		case OMAP_DSS_DSI_FMT_RGB666:
3835 			data_type = MIPI_DSI_PIXEL_STREAM_3BYTE_18;
3836 			break;
3837 		case OMAP_DSS_DSI_FMT_RGB666_PACKED:
3838 			data_type = MIPI_DSI_PACKED_PIXEL_STREAM_18;
3839 			break;
3840 		case OMAP_DSS_DSI_FMT_RGB565:
3841 			data_type = MIPI_DSI_PACKED_PIXEL_STREAM_16;
3842 			break;
3843 		default:
3844 			r = -EINVAL;
3845 			goto err_pix_fmt;
3846 		}
3847 
3848 		dsi_if_enable(dsidev, false);
3849 		dsi_vc_enable(dsidev, channel, false);
3850 
3851 		/* MODE, 1 = video mode */
3852 		REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 1, 4, 4);
3853 
3854 		word_count = DIV_ROUND_UP(dsi->timings.x_res * bpp, 8);
3855 
3856 		dsi_vc_write_long_header(dsidev, channel, data_type,
3857 				word_count, 0);
3858 
3859 		dsi_vc_enable(dsidev, channel, true);
3860 		dsi_if_enable(dsidev, true);
3861 	}
3862 
3863 	r = dss_mgr_enable(mgr);
3864 	if (r)
3865 		goto err_mgr_enable;
3866 
3867 	return 0;
3868 
3869 err_mgr_enable:
3870 	if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
3871 		dsi_if_enable(dsidev, false);
3872 		dsi_vc_enable(dsidev, channel, false);
3873 	}
3874 err_pix_fmt:
3875 	dsi_display_uninit_dispc(dsidev, mgr);
3876 err_init_dispc:
3877 	return r;
3878 }
3879 
3880 static void dsi_disable_video_output(struct omap_dss_device *dssdev, int channel)
3881 {
3882 	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3883 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3884 	struct omap_overlay_manager *mgr = dsi->output.manager;
3885 
3886 	if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
3887 		dsi_if_enable(dsidev, false);
3888 		dsi_vc_enable(dsidev, channel, false);
3889 
3890 		/* MODE, 0 = command mode */
3891 		REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 0, 4, 4);
3892 
3893 		dsi_vc_enable(dsidev, channel, true);
3894 		dsi_if_enable(dsidev, true);
3895 	}
3896 
3897 	dss_mgr_disable(mgr);
3898 
3899 	dsi_display_uninit_dispc(dsidev, mgr);
3900 }
3901 
3902 static void dsi_update_screen_dispc(struct platform_device *dsidev)
3903 {
3904 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3905 	struct omap_overlay_manager *mgr = dsi->output.manager;
3906 	unsigned bytespp;
3907 	unsigned bytespl;
3908 	unsigned bytespf;
3909 	unsigned total_len;
3910 	unsigned packet_payload;
3911 	unsigned packet_len;
3912 	u32 l;
3913 	int r;
3914 	const unsigned channel = dsi->update_channel;
3915 	const unsigned line_buf_size = dsi->line_buffer_size;
3916 	u16 w = dsi->timings.x_res;
3917 	u16 h = dsi->timings.y_res;
3918 
3919 	DSSDBG("dsi_update_screen_dispc(%dx%d)\n", w, h);
3920 
3921 	dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_VP);
3922 
3923 	bytespp	= dsi_get_pixel_size(dsi->pix_fmt) / 8;
3924 	bytespl = w * bytespp;
3925 	bytespf = bytespl * h;
3926 
3927 	/* NOTE: packet_payload has to be equal to N * bytespl, where N is
3928 	 * number of lines in a packet.  See errata about VP_CLK_RATIO */
3929 
3930 	if (bytespf < line_buf_size)
3931 		packet_payload = bytespf;
3932 	else
3933 		packet_payload = (line_buf_size) / bytespl * bytespl;
3934 
3935 	packet_len = packet_payload + 1;	/* 1 byte for DCS cmd */
3936 	total_len = (bytespf / packet_payload) * packet_len;
3937 
3938 	if (bytespf % packet_payload)
3939 		total_len += (bytespf % packet_payload) + 1;
3940 
3941 	l = FLD_VAL(total_len, 23, 0); /* TE_SIZE */
3942 	dsi_write_reg(dsidev, DSI_VC_TE(channel), l);
3943 
3944 	dsi_vc_write_long_header(dsidev, channel, MIPI_DSI_DCS_LONG_WRITE,
3945 		packet_len, 0);
3946 
3947 	if (dsi->te_enabled)
3948 		l = FLD_MOD(l, 1, 30, 30); /* TE_EN */
3949 	else
3950 		l = FLD_MOD(l, 1, 31, 31); /* TE_START */
3951 	dsi_write_reg(dsidev, DSI_VC_TE(channel), l);
3952 
3953 	/* We put SIDLEMODE to no-idle for the duration of the transfer,
3954 	 * because DSS interrupts are not capable of waking up the CPU and the
3955 	 * framedone interrupt could be delayed for quite a long time. I think
3956 	 * the same goes for any DSS interrupts, but for some reason I have not
3957 	 * seen the problem anywhere else than here.
3958 	 */
3959 	dispc_disable_sidle();
3960 
3961 	dsi_perf_mark_start(dsidev);
3962 
3963 	r = schedule_delayed_work(&dsi->framedone_timeout_work,
3964 		msecs_to_jiffies(250));
3965 	BUG_ON(r == 0);
3966 
3967 	dss_mgr_set_timings(mgr, &dsi->timings);
3968 
3969 	dss_mgr_start_update(mgr);
3970 
3971 	if (dsi->te_enabled) {
3972 		/* disable LP_RX_TO, so that we can receive TE.  Time to wait
3973 		 * for TE is longer than the timer allows */
3974 		REG_FLD_MOD(dsidev, DSI_TIMING2, 0, 15, 15); /* LP_RX_TO */
3975 
3976 		dsi_vc_send_bta(dsidev, channel);
3977 
3978 #ifdef DSI_CATCH_MISSING_TE
3979 		mod_timer(&dsi->te_timer, jiffies + msecs_to_jiffies(250));
3980 #endif
3981 	}
3982 }
3983 
3984 #ifdef DSI_CATCH_MISSING_TE
3985 static void dsi_te_timeout(struct timer_list *unused)
3986 {
3987 	DSSERR("TE not received for 250ms!\n");
3988 }
3989 #endif
3990 
3991 static void dsi_handle_framedone(struct platform_device *dsidev, int error)
3992 {
3993 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3994 
3995 	/* SIDLEMODE back to smart-idle */
3996 	dispc_enable_sidle();
3997 
3998 	if (dsi->te_enabled) {
3999 		/* enable LP_RX_TO again after the TE */
4000 		REG_FLD_MOD(dsidev, DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */
4001 	}
4002 
4003 	dsi->framedone_callback(error, dsi->framedone_data);
4004 
4005 	if (!error)
4006 		dsi_perf_show(dsidev, "DISPC");
4007 }
4008 
4009 static void dsi_framedone_timeout_work_callback(struct work_struct *work)
4010 {
4011 	struct dsi_data *dsi = container_of(work, struct dsi_data,
4012 			framedone_timeout_work.work);
4013 	/* XXX While extremely unlikely, we could get FRAMEDONE interrupt after
4014 	 * 250ms which would conflict with this timeout work. What should be
4015 	 * done is first cancel the transfer on the HW, and then cancel the
4016 	 * possibly scheduled framedone work. However, cancelling the transfer
4017 	 * on the HW is buggy, and would probably require resetting the whole
4018 	 * DSI */
4019 
4020 	DSSERR("Framedone not received for 250ms!\n");
4021 
4022 	dsi_handle_framedone(dsi->pdev, -ETIMEDOUT);
4023 }
4024 
4025 static void dsi_framedone_irq_callback(void *data)
4026 {
4027 	struct platform_device *dsidev = (struct platform_device *) data;
4028 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4029 
4030 	/* Note: We get FRAMEDONE when DISPC has finished sending pixels and
4031 	 * turns itself off. However, DSI still has the pixels in its buffers,
4032 	 * and is sending the data.
4033 	 */
4034 
4035 	cancel_delayed_work(&dsi->framedone_timeout_work);
4036 
4037 	dsi_handle_framedone(dsidev, 0);
4038 }
4039 
4040 static int dsi_update(struct omap_dss_device *dssdev, int channel,
4041 		void (*callback)(int, void *), void *data)
4042 {
4043 	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4044 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4045 
4046 	dsi_perf_mark_setup(dsidev);
4047 
4048 	dsi->update_channel = channel;
4049 
4050 	dsi->framedone_callback = callback;
4051 	dsi->framedone_data = data;
4052 
4053 #ifdef DSI_PERF_MEASURE
4054 	dsi->update_bytes = dsi->timings.x_res * dsi->timings.y_res *
4055 		dsi_get_pixel_size(dsi->pix_fmt) / 8;
4056 #endif
4057 	dsi_update_screen_dispc(dsidev);
4058 
4059 	return 0;
4060 }
4061 
4062 /* Display funcs */
4063 
4064 static int dsi_configure_dispc_clocks(struct platform_device *dsidev)
4065 {
4066 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4067 	struct dispc_clock_info dispc_cinfo;
4068 	int r;
4069 	unsigned long fck;
4070 
4071 	fck = dsi_get_pll_hsdiv_dispc_rate(dsidev);
4072 
4073 	dispc_cinfo.lck_div = dsi->user_dispc_cinfo.lck_div;
4074 	dispc_cinfo.pck_div = dsi->user_dispc_cinfo.pck_div;
4075 
4076 	r = dispc_calc_clock_rates(fck, &dispc_cinfo);
4077 	if (r) {
4078 		DSSERR("Failed to calc dispc clocks\n");
4079 		return r;
4080 	}
4081 
4082 	dsi->mgr_config.clock_info = dispc_cinfo;
4083 
4084 	return 0;
4085 }
4086 
4087 static int dsi_display_init_dispc(struct platform_device *dsidev,
4088 		struct omap_overlay_manager *mgr)
4089 {
4090 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4091 	int r;
4092 
4093 	dss_select_lcd_clk_source(mgr->id, dsi->module_id == 0 ?
4094 			OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC :
4095 			OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC);
4096 
4097 	if (dsi->mode == OMAP_DSS_DSI_CMD_MODE) {
4098 		r = dss_mgr_register_framedone_handler(mgr,
4099 				dsi_framedone_irq_callback, dsidev);
4100 		if (r) {
4101 			DSSERR("can't register FRAMEDONE handler\n");
4102 			goto err;
4103 		}
4104 
4105 		dsi->mgr_config.stallmode = true;
4106 		dsi->mgr_config.fifohandcheck = true;
4107 	} else {
4108 		dsi->mgr_config.stallmode = false;
4109 		dsi->mgr_config.fifohandcheck = false;
4110 	}
4111 
4112 	/*
4113 	 * override interlace, logic level and edge related parameters in
4114 	 * omap_video_timings with default values
4115 	 */
4116 	dsi->timings.interlace = false;
4117 	dsi->timings.hsync_level = OMAPDSS_SIG_ACTIVE_HIGH;
4118 	dsi->timings.vsync_level = OMAPDSS_SIG_ACTIVE_HIGH;
4119 	dsi->timings.data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE;
4120 	dsi->timings.de_level = OMAPDSS_SIG_ACTIVE_HIGH;
4121 	dsi->timings.sync_pclk_edge = OMAPDSS_DRIVE_SIG_FALLING_EDGE;
4122 
4123 	dss_mgr_set_timings(mgr, &dsi->timings);
4124 
4125 	r = dsi_configure_dispc_clocks(dsidev);
4126 	if (r)
4127 		goto err1;
4128 
4129 	dsi->mgr_config.io_pad_mode = DSS_IO_PAD_MODE_BYPASS;
4130 	dsi->mgr_config.video_port_width =
4131 			dsi_get_pixel_size(dsi->pix_fmt);
4132 	dsi->mgr_config.lcden_sig_polarity = 0;
4133 
4134 	dss_mgr_set_lcd_config(mgr, &dsi->mgr_config);
4135 
4136 	return 0;
4137 err1:
4138 	if (dsi->mode == OMAP_DSS_DSI_CMD_MODE)
4139 		dss_mgr_unregister_framedone_handler(mgr,
4140 				dsi_framedone_irq_callback, dsidev);
4141 err:
4142 	dss_select_lcd_clk_source(mgr->id, OMAP_DSS_CLK_SRC_FCK);
4143 	return r;
4144 }
4145 
4146 static void dsi_display_uninit_dispc(struct platform_device *dsidev,
4147 		struct omap_overlay_manager *mgr)
4148 {
4149 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4150 
4151 	if (dsi->mode == OMAP_DSS_DSI_CMD_MODE)
4152 		dss_mgr_unregister_framedone_handler(mgr,
4153 				dsi_framedone_irq_callback, dsidev);
4154 
4155 	dss_select_lcd_clk_source(mgr->id, OMAP_DSS_CLK_SRC_FCK);
4156 }
4157 
4158 static int dsi_configure_dsi_clocks(struct platform_device *dsidev)
4159 {
4160 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4161 	struct dss_pll_clock_info cinfo;
4162 	int r;
4163 
4164 	cinfo = dsi->user_dsi_cinfo;
4165 
4166 	r = dss_pll_set_config(&dsi->pll, &cinfo);
4167 	if (r) {
4168 		DSSERR("Failed to set dsi clocks\n");
4169 		return r;
4170 	}
4171 
4172 	return 0;
4173 }
4174 
4175 static int dsi_display_init_dsi(struct platform_device *dsidev)
4176 {
4177 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4178 	int r;
4179 
4180 	r = dss_pll_enable(&dsi->pll);
4181 	if (r)
4182 		goto err0;
4183 
4184 	r = dsi_configure_dsi_clocks(dsidev);
4185 	if (r)
4186 		goto err1;
4187 
4188 	dss_select_dsi_clk_source(dsi->module_id, dsi->module_id == 0 ?
4189 			OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI :
4190 			OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI);
4191 
4192 	DSSDBG("PLL OK\n");
4193 
4194 	r = dsi_cio_init(dsidev);
4195 	if (r)
4196 		goto err2;
4197 
4198 	_dsi_print_reset_status(dsidev);
4199 
4200 	dsi_proto_timings(dsidev);
4201 	dsi_set_lp_clk_divisor(dsidev);
4202 
4203 	if (1)
4204 		_dsi_print_reset_status(dsidev);
4205 
4206 	r = dsi_proto_config(dsidev);
4207 	if (r)
4208 		goto err3;
4209 
4210 	/* enable interface */
4211 	dsi_vc_enable(dsidev, 0, 1);
4212 	dsi_vc_enable(dsidev, 1, 1);
4213 	dsi_vc_enable(dsidev, 2, 1);
4214 	dsi_vc_enable(dsidev, 3, 1);
4215 	dsi_if_enable(dsidev, 1);
4216 	dsi_force_tx_stop_mode_io(dsidev);
4217 
4218 	return 0;
4219 err3:
4220 	dsi_cio_uninit(dsidev);
4221 err2:
4222 	dss_select_dsi_clk_source(dsi->module_id, OMAP_DSS_CLK_SRC_FCK);
4223 err1:
4224 	dss_pll_disable(&dsi->pll);
4225 err0:
4226 	return r;
4227 }
4228 
4229 static void dsi_display_uninit_dsi(struct platform_device *dsidev,
4230 		bool disconnect_lanes, bool enter_ulps)
4231 {
4232 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4233 
4234 	if (enter_ulps && !dsi->ulps_enabled)
4235 		dsi_enter_ulps(dsidev);
4236 
4237 	/* disable interface */
4238 	dsi_if_enable(dsidev, 0);
4239 	dsi_vc_enable(dsidev, 0, 0);
4240 	dsi_vc_enable(dsidev, 1, 0);
4241 	dsi_vc_enable(dsidev, 2, 0);
4242 	dsi_vc_enable(dsidev, 3, 0);
4243 
4244 	dss_select_dsi_clk_source(dsi->module_id, OMAP_DSS_CLK_SRC_FCK);
4245 	dsi_cio_uninit(dsidev);
4246 	dsi_pll_uninit(dsidev, disconnect_lanes);
4247 }
4248 
4249 static int dsi_display_enable(struct omap_dss_device *dssdev)
4250 {
4251 	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4252 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4253 	int r = 0;
4254 
4255 	DSSDBG("dsi_display_enable\n");
4256 
4257 	WARN_ON(!dsi_bus_is_locked(dsidev));
4258 
4259 	mutex_lock(&dsi->lock);
4260 
4261 	r = dsi_runtime_get(dsidev);
4262 	if (r)
4263 		goto err_get_dsi;
4264 
4265 	_dsi_initialize_irq(dsidev);
4266 
4267 	r = dsi_display_init_dsi(dsidev);
4268 	if (r)
4269 		goto err_init_dsi;
4270 
4271 	mutex_unlock(&dsi->lock);
4272 
4273 	return 0;
4274 
4275 err_init_dsi:
4276 	dsi_runtime_put(dsidev);
4277 err_get_dsi:
4278 	mutex_unlock(&dsi->lock);
4279 	DSSDBG("dsi_display_enable FAILED\n");
4280 	return r;
4281 }
4282 
4283 static void dsi_display_disable(struct omap_dss_device *dssdev,
4284 		bool disconnect_lanes, bool enter_ulps)
4285 {
4286 	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4287 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4288 
4289 	DSSDBG("dsi_display_disable\n");
4290 
4291 	WARN_ON(!dsi_bus_is_locked(dsidev));
4292 
4293 	mutex_lock(&dsi->lock);
4294 
4295 	dsi_sync_vc(dsidev, 0);
4296 	dsi_sync_vc(dsidev, 1);
4297 	dsi_sync_vc(dsidev, 2);
4298 	dsi_sync_vc(dsidev, 3);
4299 
4300 	dsi_display_uninit_dsi(dsidev, disconnect_lanes, enter_ulps);
4301 
4302 	dsi_runtime_put(dsidev);
4303 
4304 	mutex_unlock(&dsi->lock);
4305 }
4306 
4307 static int dsi_enable_te(struct omap_dss_device *dssdev, bool enable)
4308 {
4309 	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4310 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4311 
4312 	dsi->te_enabled = enable;
4313 	return 0;
4314 }
4315 
4316 #ifdef PRINT_VERBOSE_VM_TIMINGS
4317 static void print_dsi_vm(const char *str,
4318 		const struct omap_dss_dsi_videomode_timings *t)
4319 {
4320 	unsigned long byteclk = t->hsclk / 4;
4321 	int bl, wc, pps, tot;
4322 
4323 	wc = DIV_ROUND_UP(t->hact * t->bitspp, 8);
4324 	pps = DIV_ROUND_UP(wc + 6, t->ndl); /* pixel packet size */
4325 	bl = t->hss + t->hsa + t->hse + t->hbp + t->hfp;
4326 	tot = bl + pps;
4327 
4328 #define TO_DSI_T(x) ((u32)div64_u64((u64)x * 1000000000llu, byteclk))
4329 
4330 	pr_debug("%s bck %lu, %u/%u/%u/%u/%u/%u = %u+%u = %u, "
4331 			"%u/%u/%u/%u/%u/%u = %u + %u = %u\n",
4332 			str,
4333 			byteclk,
4334 			t->hss, t->hsa, t->hse, t->hbp, pps, t->hfp,
4335 			bl, pps, tot,
4336 			TO_DSI_T(t->hss),
4337 			TO_DSI_T(t->hsa),
4338 			TO_DSI_T(t->hse),
4339 			TO_DSI_T(t->hbp),
4340 			TO_DSI_T(pps),
4341 			TO_DSI_T(t->hfp),
4342 
4343 			TO_DSI_T(bl),
4344 			TO_DSI_T(pps),
4345 
4346 			TO_DSI_T(tot));
4347 #undef TO_DSI_T
4348 }
4349 
4350 static void print_dispc_vm(const char *str, const struct omap_video_timings *t)
4351 {
4352 	unsigned long pck = t->pixelclock;
4353 	int hact, bl, tot;
4354 
4355 	hact = t->x_res;
4356 	bl = t->hsw + t->hbp + t->hfp;
4357 	tot = hact + bl;
4358 
4359 #define TO_DISPC_T(x) ((u32)div64_u64((u64)x * 1000000000llu, pck))
4360 
4361 	pr_debug("%s pck %lu, %u/%u/%u/%u = %u+%u = %u, "
4362 			"%u/%u/%u/%u = %u + %u = %u\n",
4363 			str,
4364 			pck,
4365 			t->hsw, t->hbp, hact, t->hfp,
4366 			bl, hact, tot,
4367 			TO_DISPC_T(t->hsw),
4368 			TO_DISPC_T(t->hbp),
4369 			TO_DISPC_T(hact),
4370 			TO_DISPC_T(t->hfp),
4371 			TO_DISPC_T(bl),
4372 			TO_DISPC_T(hact),
4373 			TO_DISPC_T(tot));
4374 #undef TO_DISPC_T
4375 }
4376 
4377 /* note: this is not quite accurate */
4378 static void print_dsi_dispc_vm(const char *str,
4379 		const struct omap_dss_dsi_videomode_timings *t)
4380 {
4381 	struct omap_video_timings vm = { 0 };
4382 	unsigned long byteclk = t->hsclk / 4;
4383 	unsigned long pck;
4384 	u64 dsi_tput;
4385 	int dsi_hact, dsi_htot;
4386 
4387 	dsi_tput = (u64)byteclk * t->ndl * 8;
4388 	pck = (u32)div64_u64(dsi_tput, t->bitspp);
4389 	dsi_hact = DIV_ROUND_UP(DIV_ROUND_UP(t->hact * t->bitspp, 8) + 6, t->ndl);
4390 	dsi_htot = t->hss + t->hsa + t->hse + t->hbp + dsi_hact + t->hfp;
4391 
4392 	vm.pixelclock = pck;
4393 	vm.hsw = div64_u64((u64)(t->hsa + t->hse) * pck, byteclk);
4394 	vm.hbp = div64_u64((u64)t->hbp * pck, byteclk);
4395 	vm.hfp = div64_u64((u64)t->hfp * pck, byteclk);
4396 	vm.x_res = t->hact;
4397 
4398 	print_dispc_vm(str, &vm);
4399 }
4400 #endif /* PRINT_VERBOSE_VM_TIMINGS */
4401 
4402 static bool dsi_cm_calc_dispc_cb(int lckd, int pckd, unsigned long lck,
4403 		unsigned long pck, void *data)
4404 {
4405 	struct dsi_clk_calc_ctx *ctx = data;
4406 	struct omap_video_timings *t = &ctx->dispc_vm;
4407 
4408 	ctx->dispc_cinfo.lck_div = lckd;
4409 	ctx->dispc_cinfo.pck_div = pckd;
4410 	ctx->dispc_cinfo.lck = lck;
4411 	ctx->dispc_cinfo.pck = pck;
4412 
4413 	*t = *ctx->config->timings;
4414 	t->pixelclock = pck;
4415 	t->x_res = ctx->config->timings->x_res;
4416 	t->y_res = ctx->config->timings->y_res;
4417 	t->hsw = t->hfp = t->hbp = t->vsw = 1;
4418 	t->vfp = t->vbp = 0;
4419 
4420 	return true;
4421 }
4422 
4423 static bool dsi_cm_calc_hsdiv_cb(int m_dispc, unsigned long dispc,
4424 		void *data)
4425 {
4426 	struct dsi_clk_calc_ctx *ctx = data;
4427 
4428 	ctx->dsi_cinfo.mX[HSDIV_DISPC] = m_dispc;
4429 	ctx->dsi_cinfo.clkout[HSDIV_DISPC] = dispc;
4430 
4431 	return dispc_div_calc(dispc, ctx->req_pck_min, ctx->req_pck_max,
4432 			dsi_cm_calc_dispc_cb, ctx);
4433 }
4434 
4435 static bool dsi_cm_calc_pll_cb(int n, int m, unsigned long fint,
4436 		unsigned long clkdco, void *data)
4437 {
4438 	struct dsi_clk_calc_ctx *ctx = data;
4439 
4440 	ctx->dsi_cinfo.n = n;
4441 	ctx->dsi_cinfo.m = m;
4442 	ctx->dsi_cinfo.fint = fint;
4443 	ctx->dsi_cinfo.clkdco = clkdco;
4444 
4445 	return dss_pll_hsdiv_calc(ctx->pll, clkdco, ctx->req_pck_min,
4446 			dss_feat_get_param_max(FEAT_PARAM_DSS_FCK),
4447 			dsi_cm_calc_hsdiv_cb, ctx);
4448 }
4449 
4450 static bool dsi_cm_calc(struct dsi_data *dsi,
4451 		const struct omap_dss_dsi_config *cfg,
4452 		struct dsi_clk_calc_ctx *ctx)
4453 {
4454 	unsigned long clkin;
4455 	int bitspp, ndl;
4456 	unsigned long pll_min, pll_max;
4457 	unsigned long pck, txbyteclk;
4458 
4459 	clkin = clk_get_rate(dsi->pll.clkin);
4460 	bitspp = dsi_get_pixel_size(cfg->pixel_format);
4461 	ndl = dsi->num_lanes_used - 1;
4462 
4463 	/*
4464 	 * Here we should calculate minimum txbyteclk to be able to send the
4465 	 * frame in time, and also to handle TE. That's not very simple, though,
4466 	 * especially as we go to LP between each pixel packet due to HW
4467 	 * "feature". So let's just estimate very roughly and multiply by 1.5.
4468 	 */
4469 	pck = cfg->timings->pixelclock;
4470 	pck = pck * 3 / 2;
4471 	txbyteclk = pck * bitspp / 8 / ndl;
4472 
4473 	memset(ctx, 0, sizeof(*ctx));
4474 	ctx->dsidev = dsi->pdev;
4475 	ctx->pll = &dsi->pll;
4476 	ctx->config = cfg;
4477 	ctx->req_pck_min = pck;
4478 	ctx->req_pck_nom = pck;
4479 	ctx->req_pck_max = pck * 3 / 2;
4480 
4481 	pll_min = max(cfg->hs_clk_min * 4, txbyteclk * 4 * 4);
4482 	pll_max = cfg->hs_clk_max * 4;
4483 
4484 	return dss_pll_calc(ctx->pll, clkin,
4485 			pll_min, pll_max,
4486 			dsi_cm_calc_pll_cb, ctx);
4487 }
4488 
4489 static bool dsi_vm_calc_blanking(struct dsi_clk_calc_ctx *ctx)
4490 {
4491 	struct dsi_data *dsi = dsi_get_dsidrv_data(ctx->dsidev);
4492 	const struct omap_dss_dsi_config *cfg = ctx->config;
4493 	int bitspp = dsi_get_pixel_size(cfg->pixel_format);
4494 	int ndl = dsi->num_lanes_used - 1;
4495 	unsigned long hsclk = ctx->dsi_cinfo.clkdco / 4;
4496 	unsigned long byteclk = hsclk / 4;
4497 
4498 	unsigned long dispc_pck, req_pck_min, req_pck_nom, req_pck_max;
4499 	int xres;
4500 	int panel_htot, panel_hbl; /* pixels */
4501 	int dispc_htot, dispc_hbl; /* pixels */
4502 	int dsi_htot, dsi_hact, dsi_hbl, hss, hse; /* byteclks */
4503 	int hfp, hsa, hbp;
4504 	const struct omap_video_timings *req_vm;
4505 	struct omap_video_timings *dispc_vm;
4506 	struct omap_dss_dsi_videomode_timings *dsi_vm;
4507 	u64 dsi_tput, dispc_tput;
4508 
4509 	dsi_tput = (u64)byteclk * ndl * 8;
4510 
4511 	req_vm = cfg->timings;
4512 	req_pck_min = ctx->req_pck_min;
4513 	req_pck_max = ctx->req_pck_max;
4514 	req_pck_nom = ctx->req_pck_nom;
4515 
4516 	dispc_pck = ctx->dispc_cinfo.pck;
4517 	dispc_tput = (u64)dispc_pck * bitspp;
4518 
4519 	xres = req_vm->x_res;
4520 
4521 	panel_hbl = req_vm->hfp + req_vm->hbp + req_vm->hsw;
4522 	panel_htot = xres + panel_hbl;
4523 
4524 	dsi_hact = DIV_ROUND_UP(DIV_ROUND_UP(xres * bitspp, 8) + 6, ndl);
4525 
4526 	/*
4527 	 * When there are no line buffers, DISPC and DSI must have the
4528 	 * same tput. Otherwise DISPC tput needs to be higher than DSI's.
4529 	 */
4530 	if (dsi->line_buffer_size < xres * bitspp / 8) {
4531 		if (dispc_tput != dsi_tput)
4532 			return false;
4533 	} else {
4534 		if (dispc_tput < dsi_tput)
4535 			return false;
4536 	}
4537 
4538 	/* DSI tput must be over the min requirement */
4539 	if (dsi_tput < (u64)bitspp * req_pck_min)
4540 		return false;
4541 
4542 	/* When non-burst mode, DSI tput must be below max requirement. */
4543 	if (cfg->trans_mode != OMAP_DSS_DSI_BURST_MODE) {
4544 		if (dsi_tput > (u64)bitspp * req_pck_max)
4545 			return false;
4546 	}
4547 
4548 	hss = DIV_ROUND_UP(4, ndl);
4549 
4550 	if (cfg->trans_mode == OMAP_DSS_DSI_PULSE_MODE) {
4551 		if (ndl == 3 && req_vm->hsw == 0)
4552 			hse = 1;
4553 		else
4554 			hse = DIV_ROUND_UP(4, ndl);
4555 	} else {
4556 		hse = 0;
4557 	}
4558 
4559 	/* DSI htot to match the panel's nominal pck */
4560 	dsi_htot = div64_u64((u64)panel_htot * byteclk, req_pck_nom);
4561 
4562 	/* fail if there would be no time for blanking */
4563 	if (dsi_htot < hss + hse + dsi_hact)
4564 		return false;
4565 
4566 	/* total DSI blanking needed to achieve panel's TL */
4567 	dsi_hbl = dsi_htot - dsi_hact;
4568 
4569 	/* DISPC htot to match the DSI TL */
4570 	dispc_htot = div64_u64((u64)dsi_htot * dispc_pck, byteclk);
4571 
4572 	/* verify that the DSI and DISPC TLs are the same */
4573 	if ((u64)dsi_htot * dispc_pck != (u64)dispc_htot * byteclk)
4574 		return false;
4575 
4576 	dispc_hbl = dispc_htot - xres;
4577 
4578 	/* setup DSI videomode */
4579 
4580 	dsi_vm = &ctx->dsi_vm;
4581 	memset(dsi_vm, 0, sizeof(*dsi_vm));
4582 
4583 	dsi_vm->hsclk = hsclk;
4584 
4585 	dsi_vm->ndl = ndl;
4586 	dsi_vm->bitspp = bitspp;
4587 
4588 	if (cfg->trans_mode != OMAP_DSS_DSI_PULSE_MODE) {
4589 		hsa = 0;
4590 	} else if (ndl == 3 && req_vm->hsw == 0) {
4591 		hsa = 0;
4592 	} else {
4593 		hsa = div64_u64((u64)req_vm->hsw * byteclk, req_pck_nom);
4594 		hsa = max(hsa - hse, 1);
4595 	}
4596 
4597 	hbp = div64_u64((u64)req_vm->hbp * byteclk, req_pck_nom);
4598 	hbp = max(hbp, 1);
4599 
4600 	hfp = dsi_hbl - (hss + hsa + hse + hbp);
4601 	if (hfp < 1) {
4602 		int t;
4603 		/* we need to take cycles from hbp */
4604 
4605 		t = 1 - hfp;
4606 		hbp = max(hbp - t, 1);
4607 		hfp = dsi_hbl - (hss + hsa + hse + hbp);
4608 
4609 		if (hfp < 1 && hsa > 0) {
4610 			/* we need to take cycles from hsa */
4611 			t = 1 - hfp;
4612 			hsa = max(hsa - t, 1);
4613 			hfp = dsi_hbl - (hss + hsa + hse + hbp);
4614 		}
4615 	}
4616 
4617 	if (hfp < 1)
4618 		return false;
4619 
4620 	dsi_vm->hss = hss;
4621 	dsi_vm->hsa = hsa;
4622 	dsi_vm->hse = hse;
4623 	dsi_vm->hbp = hbp;
4624 	dsi_vm->hact = xres;
4625 	dsi_vm->hfp = hfp;
4626 
4627 	dsi_vm->vsa = req_vm->vsw;
4628 	dsi_vm->vbp = req_vm->vbp;
4629 	dsi_vm->vact = req_vm->y_res;
4630 	dsi_vm->vfp = req_vm->vfp;
4631 
4632 	dsi_vm->trans_mode = cfg->trans_mode;
4633 
4634 	dsi_vm->blanking_mode = 0;
4635 	dsi_vm->hsa_blanking_mode = 1;
4636 	dsi_vm->hfp_blanking_mode = 1;
4637 	dsi_vm->hbp_blanking_mode = 1;
4638 
4639 	dsi_vm->ddr_clk_always_on = cfg->ddr_clk_always_on;
4640 	dsi_vm->window_sync = 4;
4641 
4642 	/* setup DISPC videomode */
4643 
4644 	dispc_vm = &ctx->dispc_vm;
4645 	*dispc_vm = *req_vm;
4646 	dispc_vm->pixelclock = dispc_pck;
4647 
4648 	if (cfg->trans_mode == OMAP_DSS_DSI_PULSE_MODE) {
4649 		hsa = div64_u64((u64)req_vm->hsw * dispc_pck,
4650 				req_pck_nom);
4651 		hsa = max(hsa, 1);
4652 	} else {
4653 		hsa = 1;
4654 	}
4655 
4656 	hbp = div64_u64((u64)req_vm->hbp * dispc_pck, req_pck_nom);
4657 	hbp = max(hbp, 1);
4658 
4659 	hfp = dispc_hbl - hsa - hbp;
4660 	if (hfp < 1) {
4661 		int t;
4662 		/* we need to take cycles from hbp */
4663 
4664 		t = 1 - hfp;
4665 		hbp = max(hbp - t, 1);
4666 		hfp = dispc_hbl - hsa - hbp;
4667 
4668 		if (hfp < 1) {
4669 			/* we need to take cycles from hsa */
4670 			t = 1 - hfp;
4671 			hsa = max(hsa - t, 1);
4672 			hfp = dispc_hbl - hsa - hbp;
4673 		}
4674 	}
4675 
4676 	if (hfp < 1)
4677 		return false;
4678 
4679 	dispc_vm->hfp = hfp;
4680 	dispc_vm->hsw = hsa;
4681 	dispc_vm->hbp = hbp;
4682 
4683 	return true;
4684 }
4685 
4686 
4687 static bool dsi_vm_calc_dispc_cb(int lckd, int pckd, unsigned long lck,
4688 		unsigned long pck, void *data)
4689 {
4690 	struct dsi_clk_calc_ctx *ctx = data;
4691 
4692 	ctx->dispc_cinfo.lck_div = lckd;
4693 	ctx->dispc_cinfo.pck_div = pckd;
4694 	ctx->dispc_cinfo.lck = lck;
4695 	ctx->dispc_cinfo.pck = pck;
4696 
4697 	if (dsi_vm_calc_blanking(ctx) == false)
4698 		return false;
4699 
4700 #ifdef PRINT_VERBOSE_VM_TIMINGS
4701 	print_dispc_vm("dispc", &ctx->dispc_vm);
4702 	print_dsi_vm("dsi  ", &ctx->dsi_vm);
4703 	print_dispc_vm("req  ", ctx->config->timings);
4704 	print_dsi_dispc_vm("act  ", &ctx->dsi_vm);
4705 #endif
4706 
4707 	return true;
4708 }
4709 
4710 static bool dsi_vm_calc_hsdiv_cb(int m_dispc, unsigned long dispc,
4711 		void *data)
4712 {
4713 	struct dsi_clk_calc_ctx *ctx = data;
4714 	unsigned long pck_max;
4715 
4716 	ctx->dsi_cinfo.mX[HSDIV_DISPC] = m_dispc;
4717 	ctx->dsi_cinfo.clkout[HSDIV_DISPC] = dispc;
4718 
4719 	/*
4720 	 * In burst mode we can let the dispc pck be arbitrarily high, but it
4721 	 * limits our scaling abilities. So for now, don't aim too high.
4722 	 */
4723 
4724 	if (ctx->config->trans_mode == OMAP_DSS_DSI_BURST_MODE)
4725 		pck_max = ctx->req_pck_max + 10000000;
4726 	else
4727 		pck_max = ctx->req_pck_max;
4728 
4729 	return dispc_div_calc(dispc, ctx->req_pck_min, pck_max,
4730 			dsi_vm_calc_dispc_cb, ctx);
4731 }
4732 
4733 static bool dsi_vm_calc_pll_cb(int n, int m, unsigned long fint,
4734 		unsigned long clkdco, void *data)
4735 {
4736 	struct dsi_clk_calc_ctx *ctx = data;
4737 
4738 	ctx->dsi_cinfo.n = n;
4739 	ctx->dsi_cinfo.m = m;
4740 	ctx->dsi_cinfo.fint = fint;
4741 	ctx->dsi_cinfo.clkdco = clkdco;
4742 
4743 	return dss_pll_hsdiv_calc(ctx->pll, clkdco, ctx->req_pck_min,
4744 			dss_feat_get_param_max(FEAT_PARAM_DSS_FCK),
4745 			dsi_vm_calc_hsdiv_cb, ctx);
4746 }
4747 
4748 static bool dsi_vm_calc(struct dsi_data *dsi,
4749 		const struct omap_dss_dsi_config *cfg,
4750 		struct dsi_clk_calc_ctx *ctx)
4751 {
4752 	const struct omap_video_timings *t = cfg->timings;
4753 	unsigned long clkin;
4754 	unsigned long pll_min;
4755 	unsigned long pll_max;
4756 	int ndl = dsi->num_lanes_used - 1;
4757 	int bitspp = dsi_get_pixel_size(cfg->pixel_format);
4758 	unsigned long byteclk_min;
4759 
4760 	clkin = clk_get_rate(dsi->pll.clkin);
4761 
4762 	memset(ctx, 0, sizeof(*ctx));
4763 	ctx->dsidev = dsi->pdev;
4764 	ctx->pll = &dsi->pll;
4765 	ctx->config = cfg;
4766 
4767 	/* these limits should come from the panel driver */
4768 	ctx->req_pck_min = t->pixelclock - 1000;
4769 	ctx->req_pck_nom = t->pixelclock;
4770 	ctx->req_pck_max = t->pixelclock + 1000;
4771 
4772 	byteclk_min = div64_u64((u64)ctx->req_pck_min * bitspp, ndl * 8);
4773 	pll_min = max(cfg->hs_clk_min * 4, byteclk_min * 4 * 4);
4774 
4775 	if (cfg->trans_mode == OMAP_DSS_DSI_BURST_MODE) {
4776 		pll_max = cfg->hs_clk_max * 4;
4777 	} else {
4778 		unsigned long byteclk_max;
4779 		byteclk_max = div64_u64((u64)ctx->req_pck_max * bitspp,
4780 				ndl * 8);
4781 
4782 		pll_max = byteclk_max * 4 * 4;
4783 	}
4784 
4785 	return dss_pll_calc(ctx->pll, clkin,
4786 			pll_min, pll_max,
4787 			dsi_vm_calc_pll_cb, ctx);
4788 }
4789 
4790 static int dsi_set_config(struct omap_dss_device *dssdev,
4791 		const struct omap_dss_dsi_config *config)
4792 {
4793 	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4794 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4795 	struct dsi_clk_calc_ctx ctx;
4796 	bool ok;
4797 	int r;
4798 
4799 	mutex_lock(&dsi->lock);
4800 
4801 	dsi->pix_fmt = config->pixel_format;
4802 	dsi->mode = config->mode;
4803 
4804 	if (config->mode == OMAP_DSS_DSI_VIDEO_MODE)
4805 		ok = dsi_vm_calc(dsi, config, &ctx);
4806 	else
4807 		ok = dsi_cm_calc(dsi, config, &ctx);
4808 
4809 	if (!ok) {
4810 		DSSERR("failed to find suitable DSI clock settings\n");
4811 		r = -EINVAL;
4812 		goto err;
4813 	}
4814 
4815 	dsi_pll_calc_dsi_fck(&ctx.dsi_cinfo);
4816 
4817 	r = dsi_lp_clock_calc(ctx.dsi_cinfo.clkout[HSDIV_DSI],
4818 		config->lp_clk_min, config->lp_clk_max, &dsi->user_lp_cinfo);
4819 	if (r) {
4820 		DSSERR("failed to find suitable DSI LP clock settings\n");
4821 		goto err;
4822 	}
4823 
4824 	dsi->user_dsi_cinfo = ctx.dsi_cinfo;
4825 	dsi->user_dispc_cinfo = ctx.dispc_cinfo;
4826 
4827 	dsi->timings = ctx.dispc_vm;
4828 	dsi->vm_timings = ctx.dsi_vm;
4829 
4830 	mutex_unlock(&dsi->lock);
4831 
4832 	return 0;
4833 err:
4834 	mutex_unlock(&dsi->lock);
4835 
4836 	return r;
4837 }
4838 
4839 /*
4840  * Return a hardcoded channel for the DSI output. This should work for
4841  * current use cases, but this can be later expanded to either resolve
4842  * the channel in some more dynamic manner, or get the channel as a user
4843  * parameter.
4844  */
4845 static enum omap_channel dsi_get_channel(int module_id)
4846 {
4847 	switch (omapdss_get_version()) {
4848 	case OMAPDSS_VER_OMAP24xx:
4849 	case OMAPDSS_VER_AM43xx:
4850 		DSSWARN("DSI not supported\n");
4851 		return OMAP_DSS_CHANNEL_LCD;
4852 
4853 	case OMAPDSS_VER_OMAP34xx_ES1:
4854 	case OMAPDSS_VER_OMAP34xx_ES3:
4855 	case OMAPDSS_VER_OMAP3630:
4856 	case OMAPDSS_VER_AM35xx:
4857 		return OMAP_DSS_CHANNEL_LCD;
4858 
4859 	case OMAPDSS_VER_OMAP4430_ES1:
4860 	case OMAPDSS_VER_OMAP4430_ES2:
4861 	case OMAPDSS_VER_OMAP4:
4862 		switch (module_id) {
4863 		case 0:
4864 			return OMAP_DSS_CHANNEL_LCD;
4865 		case 1:
4866 			return OMAP_DSS_CHANNEL_LCD2;
4867 		default:
4868 			DSSWARN("unsupported module id\n");
4869 			return OMAP_DSS_CHANNEL_LCD;
4870 		}
4871 
4872 	case OMAPDSS_VER_OMAP5:
4873 		switch (module_id) {
4874 		case 0:
4875 			return OMAP_DSS_CHANNEL_LCD;
4876 		case 1:
4877 			return OMAP_DSS_CHANNEL_LCD3;
4878 		default:
4879 			DSSWARN("unsupported module id\n");
4880 			return OMAP_DSS_CHANNEL_LCD;
4881 		}
4882 
4883 	default:
4884 		DSSWARN("unsupported DSS version\n");
4885 		return OMAP_DSS_CHANNEL_LCD;
4886 	}
4887 }
4888 
4889 static int dsi_request_vc(struct omap_dss_device *dssdev, int *channel)
4890 {
4891 	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4892 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4893 	int i;
4894 
4895 	for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) {
4896 		if (!dsi->vc[i].dssdev) {
4897 			dsi->vc[i].dssdev = dssdev;
4898 			*channel = i;
4899 			return 0;
4900 		}
4901 	}
4902 
4903 	DSSERR("cannot get VC for display %s", dssdev->name);
4904 	return -ENOSPC;
4905 }
4906 
4907 static int dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id)
4908 {
4909 	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4910 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4911 
4912 	if (vc_id < 0 || vc_id > 3) {
4913 		DSSERR("VC ID out of range\n");
4914 		return -EINVAL;
4915 	}
4916 
4917 	if (channel < 0 || channel > 3) {
4918 		DSSERR("Virtual Channel out of range\n");
4919 		return -EINVAL;
4920 	}
4921 
4922 	if (dsi->vc[channel].dssdev != dssdev) {
4923 		DSSERR("Virtual Channel not allocated to display %s\n",
4924 			dssdev->name);
4925 		return -EINVAL;
4926 	}
4927 
4928 	dsi->vc[channel].vc_id = vc_id;
4929 
4930 	return 0;
4931 }
4932 
4933 static void dsi_release_vc(struct omap_dss_device *dssdev, int channel)
4934 {
4935 	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4936 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4937 
4938 	if ((channel >= 0 && channel <= 3) &&
4939 		dsi->vc[channel].dssdev == dssdev) {
4940 		dsi->vc[channel].dssdev = NULL;
4941 		dsi->vc[channel].vc_id = 0;
4942 	}
4943 }
4944 
4945 
4946 static int dsi_get_clocks(struct platform_device *dsidev)
4947 {
4948 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4949 	struct clk *clk;
4950 
4951 	clk = devm_clk_get(&dsidev->dev, "fck");
4952 	if (IS_ERR(clk)) {
4953 		DSSERR("can't get fck\n");
4954 		return PTR_ERR(clk);
4955 	}
4956 
4957 	dsi->dss_clk = clk;
4958 
4959 	return 0;
4960 }
4961 
4962 static int dsi_connect(struct omap_dss_device *dssdev,
4963 		struct omap_dss_device *dst)
4964 {
4965 	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4966 	struct omap_overlay_manager *mgr;
4967 	int r;
4968 
4969 	r = dsi_regulator_init(dsidev);
4970 	if (r)
4971 		return r;
4972 
4973 	mgr = omap_dss_get_overlay_manager(dssdev->dispc_channel);
4974 	if (!mgr)
4975 		return -ENODEV;
4976 
4977 	r = dss_mgr_connect(mgr, dssdev);
4978 	if (r)
4979 		return r;
4980 
4981 	r = omapdss_output_set_device(dssdev, dst);
4982 	if (r) {
4983 		DSSERR("failed to connect output to new device: %s\n",
4984 				dssdev->name);
4985 		dss_mgr_disconnect(mgr, dssdev);
4986 		return r;
4987 	}
4988 
4989 	return 0;
4990 }
4991 
4992 static void dsi_disconnect(struct omap_dss_device *dssdev,
4993 		struct omap_dss_device *dst)
4994 {
4995 	WARN_ON(dst != dssdev->dst);
4996 
4997 	if (dst != dssdev->dst)
4998 		return;
4999 
5000 	omapdss_output_unset_device(dssdev);
5001 
5002 	if (dssdev->manager)
5003 		dss_mgr_disconnect(dssdev->manager, dssdev);
5004 }
5005 
5006 static const struct omapdss_dsi_ops dsi_ops = {
5007 	.connect = dsi_connect,
5008 	.disconnect = dsi_disconnect,
5009 
5010 	.bus_lock = dsi_bus_lock,
5011 	.bus_unlock = dsi_bus_unlock,
5012 
5013 	.enable = dsi_display_enable,
5014 	.disable = dsi_display_disable,
5015 
5016 	.enable_hs = dsi_vc_enable_hs,
5017 
5018 	.configure_pins = dsi_configure_pins,
5019 	.set_config = dsi_set_config,
5020 
5021 	.enable_video_output = dsi_enable_video_output,
5022 	.disable_video_output = dsi_disable_video_output,
5023 
5024 	.update = dsi_update,
5025 
5026 	.enable_te = dsi_enable_te,
5027 
5028 	.request_vc = dsi_request_vc,
5029 	.set_vc_id = dsi_set_vc_id,
5030 	.release_vc = dsi_release_vc,
5031 
5032 	.dcs_write = dsi_vc_dcs_write,
5033 	.dcs_write_nosync = dsi_vc_dcs_write_nosync,
5034 	.dcs_read = dsi_vc_dcs_read,
5035 
5036 	.gen_write = dsi_vc_generic_write,
5037 	.gen_write_nosync = dsi_vc_generic_write_nosync,
5038 	.gen_read = dsi_vc_generic_read,
5039 
5040 	.bta_sync = dsi_vc_send_bta_sync,
5041 
5042 	.set_max_rx_packet_size = dsi_vc_set_max_rx_packet_size,
5043 };
5044 
5045 static void dsi_init_output(struct platform_device *dsidev)
5046 {
5047 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5048 	struct omap_dss_device *out = &dsi->output;
5049 
5050 	out->dev = &dsidev->dev;
5051 	out->id = dsi->module_id == 0 ?
5052 			OMAP_DSS_OUTPUT_DSI1 : OMAP_DSS_OUTPUT_DSI2;
5053 
5054 	out->output_type = OMAP_DISPLAY_TYPE_DSI;
5055 	out->name = dsi->module_id == 0 ? "dsi.0" : "dsi.1";
5056 	out->dispc_channel = dsi_get_channel(dsi->module_id);
5057 	out->ops.dsi = &dsi_ops;
5058 	out->owner = THIS_MODULE;
5059 
5060 	omapdss_register_output(out);
5061 }
5062 
5063 static void dsi_uninit_output(struct platform_device *dsidev)
5064 {
5065 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5066 	struct omap_dss_device *out = &dsi->output;
5067 
5068 	omapdss_unregister_output(out);
5069 }
5070 
5071 static int dsi_probe_of(struct platform_device *pdev)
5072 {
5073 	struct device_node *node = pdev->dev.of_node;
5074 	struct dsi_data *dsi = dsi_get_dsidrv_data(pdev);
5075 	struct property *prop;
5076 	u32 lane_arr[10];
5077 	int len, num_pins;
5078 	int r, i;
5079 	struct device_node *ep;
5080 	struct omap_dsi_pin_config pin_cfg;
5081 
5082 	ep = omapdss_of_get_first_endpoint(node);
5083 	if (!ep)
5084 		return 0;
5085 
5086 	prop = of_find_property(ep, "lanes", &len);
5087 	if (prop == NULL) {
5088 		dev_err(&pdev->dev, "failed to find lane data\n");
5089 		r = -EINVAL;
5090 		goto err;
5091 	}
5092 
5093 	num_pins = len / sizeof(u32);
5094 
5095 	if (num_pins < 4 || num_pins % 2 != 0 ||
5096 		num_pins > dsi->num_lanes_supported * 2) {
5097 		dev_err(&pdev->dev, "bad number of lanes\n");
5098 		r = -EINVAL;
5099 		goto err;
5100 	}
5101 
5102 	r = of_property_read_u32_array(ep, "lanes", lane_arr, num_pins);
5103 	if (r) {
5104 		dev_err(&pdev->dev, "failed to read lane data\n");
5105 		goto err;
5106 	}
5107 
5108 	pin_cfg.num_pins = num_pins;
5109 	for (i = 0; i < num_pins; ++i)
5110 		pin_cfg.pins[i] = (int)lane_arr[i];
5111 
5112 	r = dsi_configure_pins(&dsi->output, &pin_cfg);
5113 	if (r) {
5114 		dev_err(&pdev->dev, "failed to configure pins");
5115 		goto err;
5116 	}
5117 
5118 	of_node_put(ep);
5119 
5120 	return 0;
5121 
5122 err:
5123 	of_node_put(ep);
5124 	return r;
5125 }
5126 
5127 static const struct dss_pll_ops dsi_pll_ops = {
5128 	.enable = dsi_pll_enable,
5129 	.disable = dsi_pll_disable,
5130 	.set_config = dss_pll_write_config_type_a,
5131 };
5132 
5133 static const struct dss_pll_hw dss_omap3_dsi_pll_hw = {
5134 	.n_max = (1 << 7) - 1,
5135 	.m_max = (1 << 11) - 1,
5136 	.mX_max = (1 << 4) - 1,
5137 	.fint_min = 750000,
5138 	.fint_max = 2100000,
5139 	.clkdco_low = 1000000000,
5140 	.clkdco_max = 1800000000,
5141 
5142 	.n_msb = 7,
5143 	.n_lsb = 1,
5144 	.m_msb = 18,
5145 	.m_lsb = 8,
5146 
5147 	.mX_msb[0] = 22,
5148 	.mX_lsb[0] = 19,
5149 	.mX_msb[1] = 26,
5150 	.mX_lsb[1] = 23,
5151 
5152 	.has_stopmode = true,
5153 	.has_freqsel = true,
5154 	.has_selfreqdco = false,
5155 	.has_refsel = false,
5156 };
5157 
5158 static const struct dss_pll_hw dss_omap4_dsi_pll_hw = {
5159 	.n_max = (1 << 8) - 1,
5160 	.m_max = (1 << 12) - 1,
5161 	.mX_max = (1 << 5) - 1,
5162 	.fint_min = 500000,
5163 	.fint_max = 2500000,
5164 	.clkdco_low = 1000000000,
5165 	.clkdco_max = 1800000000,
5166 
5167 	.n_msb = 8,
5168 	.n_lsb = 1,
5169 	.m_msb = 20,
5170 	.m_lsb = 9,
5171 
5172 	.mX_msb[0] = 25,
5173 	.mX_lsb[0] = 21,
5174 	.mX_msb[1] = 30,
5175 	.mX_lsb[1] = 26,
5176 
5177 	.has_stopmode = true,
5178 	.has_freqsel = false,
5179 	.has_selfreqdco = false,
5180 	.has_refsel = false,
5181 };
5182 
5183 static const struct dss_pll_hw dss_omap5_dsi_pll_hw = {
5184 	.n_max = (1 << 8) - 1,
5185 	.m_max = (1 << 12) - 1,
5186 	.mX_max = (1 << 5) - 1,
5187 	.fint_min = 150000,
5188 	.fint_max = 52000000,
5189 	.clkdco_low = 1000000000,
5190 	.clkdco_max = 1800000000,
5191 
5192 	.n_msb = 8,
5193 	.n_lsb = 1,
5194 	.m_msb = 20,
5195 	.m_lsb = 9,
5196 
5197 	.mX_msb[0] = 25,
5198 	.mX_lsb[0] = 21,
5199 	.mX_msb[1] = 30,
5200 	.mX_lsb[1] = 26,
5201 
5202 	.has_stopmode = true,
5203 	.has_freqsel = false,
5204 	.has_selfreqdco = true,
5205 	.has_refsel = true,
5206 };
5207 
5208 static int dsi_init_pll_data(struct platform_device *dsidev)
5209 {
5210 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5211 	struct dss_pll *pll = &dsi->pll;
5212 	struct clk *clk;
5213 	int r;
5214 
5215 	clk = devm_clk_get(&dsidev->dev, "sys_clk");
5216 	if (IS_ERR(clk)) {
5217 		DSSERR("can't get sys_clk\n");
5218 		return PTR_ERR(clk);
5219 	}
5220 
5221 	pll->name = dsi->module_id == 0 ? "dsi0" : "dsi1";
5222 	pll->id = dsi->module_id == 0 ? DSS_PLL_DSI1 : DSS_PLL_DSI2;
5223 	pll->clkin = clk;
5224 	pll->base = dsi->pll_base;
5225 
5226 	switch (omapdss_get_version()) {
5227 	case OMAPDSS_VER_OMAP34xx_ES1:
5228 	case OMAPDSS_VER_OMAP34xx_ES3:
5229 	case OMAPDSS_VER_OMAP3630:
5230 	case OMAPDSS_VER_AM35xx:
5231 		pll->hw = &dss_omap3_dsi_pll_hw;
5232 		break;
5233 
5234 	case OMAPDSS_VER_OMAP4430_ES1:
5235 	case OMAPDSS_VER_OMAP4430_ES2:
5236 	case OMAPDSS_VER_OMAP4:
5237 		pll->hw = &dss_omap4_dsi_pll_hw;
5238 		break;
5239 
5240 	case OMAPDSS_VER_OMAP5:
5241 		pll->hw = &dss_omap5_dsi_pll_hw;
5242 		break;
5243 
5244 	default:
5245 		return -ENODEV;
5246 	}
5247 
5248 	pll->ops = &dsi_pll_ops;
5249 
5250 	r = dss_pll_register(pll);
5251 	if (r)
5252 		return r;
5253 
5254 	return 0;
5255 }
5256 
5257 /* DSI1 HW IP initialisation */
5258 static int dsi_bind(struct device *dev, struct device *master, void *data)
5259 {
5260 	struct platform_device *dsidev = to_platform_device(dev);
5261 	u32 rev;
5262 	int r, i;
5263 	struct dsi_data *dsi;
5264 	struct resource *dsi_mem;
5265 	struct resource *res;
5266 	struct resource temp_res;
5267 
5268 	dsi = devm_kzalloc(&dsidev->dev, sizeof(*dsi), GFP_KERNEL);
5269 	if (!dsi)
5270 		return -ENOMEM;
5271 
5272 	dsi->pdev = dsidev;
5273 	platform_set_drvdata(dsidev, dsi);
5274 
5275 	spin_lock_init(&dsi->irq_lock);
5276 	spin_lock_init(&dsi->errors_lock);
5277 	dsi->errors = 0;
5278 
5279 #ifdef CONFIG_FB_OMAP2_DSS_COLLECT_IRQ_STATS
5280 	spin_lock_init(&dsi->irq_stats_lock);
5281 	dsi->irq_stats.last_reset = jiffies;
5282 #endif
5283 
5284 	mutex_init(&dsi->lock);
5285 	sema_init(&dsi->bus_lock, 1);
5286 
5287 	INIT_DEFERRABLE_WORK(&dsi->framedone_timeout_work,
5288 			     dsi_framedone_timeout_work_callback);
5289 
5290 #ifdef DSI_CATCH_MISSING_TE
5291 	timer_setup(&dsi->te_timer, dsi_te_timeout, 0);
5292 #endif
5293 
5294 	res = platform_get_resource_byname(dsidev, IORESOURCE_MEM, "proto");
5295 	if (!res) {
5296 		res = platform_get_resource(dsidev, IORESOURCE_MEM, 0);
5297 		if (!res) {
5298 			DSSERR("can't get IORESOURCE_MEM DSI\n");
5299 			return -EINVAL;
5300 		}
5301 
5302 		temp_res.start = res->start;
5303 		temp_res.end = temp_res.start + DSI_PROTO_SZ - 1;
5304 		res = &temp_res;
5305 	}
5306 
5307 	dsi_mem = res;
5308 
5309 	dsi->proto_base = devm_ioremap(&dsidev->dev, res->start,
5310 		resource_size(res));
5311 	if (!dsi->proto_base) {
5312 		DSSERR("can't ioremap DSI protocol engine\n");
5313 		return -ENOMEM;
5314 	}
5315 
5316 	res = platform_get_resource_byname(dsidev, IORESOURCE_MEM, "phy");
5317 	if (!res) {
5318 		res = platform_get_resource(dsidev, IORESOURCE_MEM, 0);
5319 		if (!res) {
5320 			DSSERR("can't get IORESOURCE_MEM DSI\n");
5321 			return -EINVAL;
5322 		}
5323 
5324 		temp_res.start = res->start + DSI_PHY_OFFSET;
5325 		temp_res.end = temp_res.start + DSI_PHY_SZ - 1;
5326 		res = &temp_res;
5327 	}
5328 
5329 	dsi->phy_base = devm_ioremap(&dsidev->dev, res->start,
5330 		resource_size(res));
5331 	if (!dsi->phy_base) {
5332 		DSSERR("can't ioremap DSI PHY\n");
5333 		return -ENOMEM;
5334 	}
5335 
5336 	res = platform_get_resource_byname(dsidev, IORESOURCE_MEM, "pll");
5337 	if (!res) {
5338 		res = platform_get_resource(dsidev, IORESOURCE_MEM, 0);
5339 		if (!res) {
5340 			DSSERR("can't get IORESOURCE_MEM DSI\n");
5341 			return -EINVAL;
5342 		}
5343 
5344 		temp_res.start = res->start + DSI_PLL_OFFSET;
5345 		temp_res.end = temp_res.start + DSI_PLL_SZ - 1;
5346 		res = &temp_res;
5347 	}
5348 
5349 	dsi->pll_base = devm_ioremap(&dsidev->dev, res->start,
5350 		resource_size(res));
5351 	if (!dsi->pll_base) {
5352 		DSSERR("can't ioremap DSI PLL\n");
5353 		return -ENOMEM;
5354 	}
5355 
5356 	dsi->irq = platform_get_irq(dsi->pdev, 0);
5357 	if (dsi->irq < 0) {
5358 		DSSERR("platform_get_irq failed\n");
5359 		return -ENODEV;
5360 	}
5361 
5362 	r = devm_request_irq(&dsidev->dev, dsi->irq, omap_dsi_irq_handler,
5363 			     IRQF_SHARED, dev_name(&dsidev->dev), dsi->pdev);
5364 	if (r < 0) {
5365 		DSSERR("request_irq failed\n");
5366 		return r;
5367 	}
5368 
5369 	if (dsidev->dev.of_node) {
5370 		const struct of_device_id *match;
5371 		const struct dsi_module_id_data *d;
5372 
5373 		match = of_match_node(dsi_of_match, dsidev->dev.of_node);
5374 		if (!match) {
5375 			DSSERR("unsupported DSI module\n");
5376 			return -ENODEV;
5377 		}
5378 
5379 		d = match->data;
5380 
5381 		while (d->address != 0 && d->address != dsi_mem->start)
5382 			d++;
5383 
5384 		if (d->address == 0) {
5385 			DSSERR("unsupported DSI module\n");
5386 			return -ENODEV;
5387 		}
5388 
5389 		dsi->module_id = d->id;
5390 	} else {
5391 		dsi->module_id = dsidev->id;
5392 	}
5393 
5394 	/* DSI VCs initialization */
5395 	for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) {
5396 		dsi->vc[i].source = DSI_VC_SOURCE_L4;
5397 		dsi->vc[i].dssdev = NULL;
5398 		dsi->vc[i].vc_id = 0;
5399 	}
5400 
5401 	r = dsi_get_clocks(dsidev);
5402 	if (r)
5403 		return r;
5404 
5405 	dsi_init_pll_data(dsidev);
5406 
5407 	pm_runtime_enable(&dsidev->dev);
5408 
5409 	r = dsi_runtime_get(dsidev);
5410 	if (r)
5411 		goto err_runtime_get;
5412 
5413 	rev = dsi_read_reg(dsidev, DSI_REVISION);
5414 	dev_dbg(&dsidev->dev, "OMAP DSI rev %d.%d\n",
5415 	       FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
5416 
5417 	/* DSI on OMAP3 doesn't have register DSI_GNQ, set number
5418 	 * of data to 3 by default */
5419 	if (dss_has_feature(FEAT_DSI_GNQ))
5420 		/* NB_DATA_LANES */
5421 		dsi->num_lanes_supported = 1 + REG_GET(dsidev, DSI_GNQ, 11, 9);
5422 	else
5423 		dsi->num_lanes_supported = 3;
5424 
5425 	dsi->line_buffer_size = dsi_get_line_buf_size(dsidev);
5426 
5427 	dsi_init_output(dsidev);
5428 
5429 	if (dsidev->dev.of_node) {
5430 		r = dsi_probe_of(dsidev);
5431 		if (r) {
5432 			DSSERR("Invalid DSI DT data\n");
5433 			goto err_probe_of;
5434 		}
5435 
5436 		r = of_platform_populate(dsidev->dev.of_node, NULL, NULL,
5437 			&dsidev->dev);
5438 		if (r)
5439 			DSSERR("Failed to populate DSI child devices: %d\n", r);
5440 	}
5441 
5442 	dsi_runtime_put(dsidev);
5443 
5444 	if (dsi->module_id == 0)
5445 		dss_debugfs_create_file("dsi1_regs", dsi1_dump_regs);
5446 	else if (dsi->module_id == 1)
5447 		dss_debugfs_create_file("dsi2_regs", dsi2_dump_regs);
5448 
5449 #ifdef CONFIG_FB_OMAP2_DSS_COLLECT_IRQ_STATS
5450 	if (dsi->module_id == 0)
5451 		dss_debugfs_create_file("dsi1_irqs", dsi1_dump_irqs);
5452 	else if (dsi->module_id == 1)
5453 		dss_debugfs_create_file("dsi2_irqs", dsi2_dump_irqs);
5454 #endif
5455 
5456 	return 0;
5457 
5458 err_probe_of:
5459 	dsi_uninit_output(dsidev);
5460 	dsi_runtime_put(dsidev);
5461 
5462 err_runtime_get:
5463 	pm_runtime_disable(&dsidev->dev);
5464 	return r;
5465 }
5466 
5467 static void dsi_unbind(struct device *dev, struct device *master, void *data)
5468 {
5469 	struct platform_device *dsidev = to_platform_device(dev);
5470 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5471 
5472 	of_platform_depopulate(&dsidev->dev);
5473 
5474 	WARN_ON(dsi->scp_clk_refcount > 0);
5475 
5476 	dss_pll_unregister(&dsi->pll);
5477 
5478 	dsi_uninit_output(dsidev);
5479 
5480 	pm_runtime_disable(&dsidev->dev);
5481 
5482 	if (dsi->vdds_dsi_reg != NULL && dsi->vdds_dsi_enabled) {
5483 		regulator_disable(dsi->vdds_dsi_reg);
5484 		dsi->vdds_dsi_enabled = false;
5485 	}
5486 }
5487 
5488 static const struct component_ops dsi_component_ops = {
5489 	.bind	= dsi_bind,
5490 	.unbind	= dsi_unbind,
5491 };
5492 
5493 static int dsi_probe(struct platform_device *pdev)
5494 {
5495 	return component_add(&pdev->dev, &dsi_component_ops);
5496 }
5497 
5498 static int dsi_remove(struct platform_device *pdev)
5499 {
5500 	component_del(&pdev->dev, &dsi_component_ops);
5501 	return 0;
5502 }
5503 
5504 static int dsi_runtime_suspend(struct device *dev)
5505 {
5506 	struct platform_device *pdev = to_platform_device(dev);
5507 	struct dsi_data *dsi = dsi_get_dsidrv_data(pdev);
5508 
5509 	dsi->is_enabled = false;
5510 	/* ensure the irq handler sees the is_enabled value */
5511 	smp_wmb();
5512 	/* wait for current handler to finish before turning the DSI off */
5513 	synchronize_irq(dsi->irq);
5514 
5515 	dispc_runtime_put();
5516 
5517 	return 0;
5518 }
5519 
5520 static int dsi_runtime_resume(struct device *dev)
5521 {
5522 	struct platform_device *pdev = to_platform_device(dev);
5523 	struct dsi_data *dsi = dsi_get_dsidrv_data(pdev);
5524 	int r;
5525 
5526 	r = dispc_runtime_get();
5527 	if (r)
5528 		return r;
5529 
5530 	dsi->is_enabled = true;
5531 	/* ensure the irq handler sees the is_enabled value */
5532 	smp_wmb();
5533 
5534 	return 0;
5535 }
5536 
5537 static const struct dev_pm_ops dsi_pm_ops = {
5538 	.runtime_suspend = dsi_runtime_suspend,
5539 	.runtime_resume = dsi_runtime_resume,
5540 };
5541 
5542 static const struct dsi_module_id_data dsi_of_data_omap3[] = {
5543 	{ .address = 0x4804fc00, .id = 0, },
5544 	{ },
5545 };
5546 
5547 static const struct dsi_module_id_data dsi_of_data_omap4[] = {
5548 	{ .address = 0x58004000, .id = 0, },
5549 	{ .address = 0x58005000, .id = 1, },
5550 	{ },
5551 };
5552 
5553 static const struct dsi_module_id_data dsi_of_data_omap5[] = {
5554 	{ .address = 0x58004000, .id = 0, },
5555 	{ .address = 0x58009000, .id = 1, },
5556 	{ },
5557 };
5558 
5559 static const struct of_device_id dsi_of_match[] = {
5560 	{ .compatible = "ti,omap3-dsi", .data = dsi_of_data_omap3, },
5561 	{ .compatible = "ti,omap4-dsi", .data = dsi_of_data_omap4, },
5562 	{ .compatible = "ti,omap5-dsi", .data = dsi_of_data_omap5, },
5563 	{},
5564 };
5565 
5566 static struct platform_driver omap_dsihw_driver = {
5567 	.probe		= dsi_probe,
5568 	.remove		= dsi_remove,
5569 	.driver         = {
5570 		.name   = "omapdss_dsi",
5571 		.pm	= &dsi_pm_ops,
5572 		.of_match_table = dsi_of_match,
5573 		.suppress_bind_attrs = true,
5574 	},
5575 };
5576 
5577 int __init dsi_init_platform_driver(void)
5578 {
5579 	return platform_driver_register(&omap_dsihw_driver);
5580 }
5581 
5582 void dsi_uninit_platform_driver(void)
5583 {
5584 	platform_driver_unregister(&omap_dsihw_driver);
5585 }
5586