1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * linux/drivers/video/omap2/dss/dsi.c
4  *
5  * Copyright (C) 2009 Nokia Corporation
6  * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
7  */
8 
9 #define DSS_SUBSYS_NAME "DSI"
10 
11 #include <linux/kernel.h>
12 #include <linux/io.h>
13 #include <linux/clk.h>
14 #include <linux/device.h>
15 #include <linux/err.h>
16 #include <linux/interrupt.h>
17 #include <linux/delay.h>
18 #include <linux/mutex.h>
19 #include <linux/module.h>
20 #include <linux/semaphore.h>
21 #include <linux/seq_file.h>
22 #include <linux/platform_device.h>
23 #include <linux/regulator/consumer.h>
24 #include <linux/wait.h>
25 #include <linux/workqueue.h>
26 #include <linux/sched.h>
27 #include <linux/slab.h>
28 #include <linux/debugfs.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/of.h>
31 #include <linux/of_platform.h>
32 #include <linux/component.h>
33 
34 #include <video/omapfb_dss.h>
35 #include <video/mipi_display.h>
36 
37 #include "dss.h"
38 #include "dss_features.h"
39 
40 #define DSI_CATCH_MISSING_TE
41 
42 struct dsi_reg { u16 module; u16 idx; };
43 
44 #define DSI_REG(mod, idx)		((const struct dsi_reg) { mod, idx })
45 
46 /* DSI Protocol Engine */
47 
48 #define DSI_PROTO			0
49 #define DSI_PROTO_SZ			0x200
50 
51 #define DSI_REVISION			DSI_REG(DSI_PROTO, 0x0000)
52 #define DSI_SYSCONFIG			DSI_REG(DSI_PROTO, 0x0010)
53 #define DSI_SYSSTATUS			DSI_REG(DSI_PROTO, 0x0014)
54 #define DSI_IRQSTATUS			DSI_REG(DSI_PROTO, 0x0018)
55 #define DSI_IRQENABLE			DSI_REG(DSI_PROTO, 0x001C)
56 #define DSI_CTRL			DSI_REG(DSI_PROTO, 0x0040)
57 #define DSI_GNQ				DSI_REG(DSI_PROTO, 0x0044)
58 #define DSI_COMPLEXIO_CFG1		DSI_REG(DSI_PROTO, 0x0048)
59 #define DSI_COMPLEXIO_IRQ_STATUS	DSI_REG(DSI_PROTO, 0x004C)
60 #define DSI_COMPLEXIO_IRQ_ENABLE	DSI_REG(DSI_PROTO, 0x0050)
61 #define DSI_CLK_CTRL			DSI_REG(DSI_PROTO, 0x0054)
62 #define DSI_TIMING1			DSI_REG(DSI_PROTO, 0x0058)
63 #define DSI_TIMING2			DSI_REG(DSI_PROTO, 0x005C)
64 #define DSI_VM_TIMING1			DSI_REG(DSI_PROTO, 0x0060)
65 #define DSI_VM_TIMING2			DSI_REG(DSI_PROTO, 0x0064)
66 #define DSI_VM_TIMING3			DSI_REG(DSI_PROTO, 0x0068)
67 #define DSI_CLK_TIMING			DSI_REG(DSI_PROTO, 0x006C)
68 #define DSI_TX_FIFO_VC_SIZE		DSI_REG(DSI_PROTO, 0x0070)
69 #define DSI_RX_FIFO_VC_SIZE		DSI_REG(DSI_PROTO, 0x0074)
70 #define DSI_COMPLEXIO_CFG2		DSI_REG(DSI_PROTO, 0x0078)
71 #define DSI_RX_FIFO_VC_FULLNESS		DSI_REG(DSI_PROTO, 0x007C)
72 #define DSI_VM_TIMING4			DSI_REG(DSI_PROTO, 0x0080)
73 #define DSI_TX_FIFO_VC_EMPTINESS	DSI_REG(DSI_PROTO, 0x0084)
74 #define DSI_VM_TIMING5			DSI_REG(DSI_PROTO, 0x0088)
75 #define DSI_VM_TIMING6			DSI_REG(DSI_PROTO, 0x008C)
76 #define DSI_VM_TIMING7			DSI_REG(DSI_PROTO, 0x0090)
77 #define DSI_STOPCLK_TIMING		DSI_REG(DSI_PROTO, 0x0094)
78 #define DSI_VC_CTRL(n)			DSI_REG(DSI_PROTO, 0x0100 + (n * 0x20))
79 #define DSI_VC_TE(n)			DSI_REG(DSI_PROTO, 0x0104 + (n * 0x20))
80 #define DSI_VC_LONG_PACKET_HEADER(n)	DSI_REG(DSI_PROTO, 0x0108 + (n * 0x20))
81 #define DSI_VC_LONG_PACKET_PAYLOAD(n)	DSI_REG(DSI_PROTO, 0x010C + (n * 0x20))
82 #define DSI_VC_SHORT_PACKET_HEADER(n)	DSI_REG(DSI_PROTO, 0x0110 + (n * 0x20))
83 #define DSI_VC_IRQSTATUS(n)		DSI_REG(DSI_PROTO, 0x0118 + (n * 0x20))
84 #define DSI_VC_IRQENABLE(n)		DSI_REG(DSI_PROTO, 0x011C + (n * 0x20))
85 
86 /* DSIPHY_SCP */
87 
88 #define DSI_PHY				1
89 #define DSI_PHY_OFFSET			0x200
90 #define DSI_PHY_SZ			0x40
91 
92 #define DSI_DSIPHY_CFG0			DSI_REG(DSI_PHY, 0x0000)
93 #define DSI_DSIPHY_CFG1			DSI_REG(DSI_PHY, 0x0004)
94 #define DSI_DSIPHY_CFG2			DSI_REG(DSI_PHY, 0x0008)
95 #define DSI_DSIPHY_CFG5			DSI_REG(DSI_PHY, 0x0014)
96 #define DSI_DSIPHY_CFG10		DSI_REG(DSI_PHY, 0x0028)
97 
98 /* DSI_PLL_CTRL_SCP */
99 
100 #define DSI_PLL				2
101 #define DSI_PLL_OFFSET			0x300
102 #define DSI_PLL_SZ			0x20
103 
104 #define DSI_PLL_CONTROL			DSI_REG(DSI_PLL, 0x0000)
105 #define DSI_PLL_STATUS			DSI_REG(DSI_PLL, 0x0004)
106 #define DSI_PLL_GO			DSI_REG(DSI_PLL, 0x0008)
107 #define DSI_PLL_CONFIGURATION1		DSI_REG(DSI_PLL, 0x000C)
108 #define DSI_PLL_CONFIGURATION2		DSI_REG(DSI_PLL, 0x0010)
109 
110 #define REG_GET(dsidev, idx, start, end) \
111 	FLD_GET(dsi_read_reg(dsidev, idx), start, end)
112 
113 #define REG_FLD_MOD(dsidev, idx, val, start, end) \
114 	dsi_write_reg(dsidev, idx, FLD_MOD(dsi_read_reg(dsidev, idx), val, start, end))
115 
116 /* Global interrupts */
117 #define DSI_IRQ_VC0		(1 << 0)
118 #define DSI_IRQ_VC1		(1 << 1)
119 #define DSI_IRQ_VC2		(1 << 2)
120 #define DSI_IRQ_VC3		(1 << 3)
121 #define DSI_IRQ_WAKEUP		(1 << 4)
122 #define DSI_IRQ_RESYNC		(1 << 5)
123 #define DSI_IRQ_PLL_LOCK	(1 << 7)
124 #define DSI_IRQ_PLL_UNLOCK	(1 << 8)
125 #define DSI_IRQ_PLL_RECALL	(1 << 9)
126 #define DSI_IRQ_COMPLEXIO_ERR	(1 << 10)
127 #define DSI_IRQ_HS_TX_TIMEOUT	(1 << 14)
128 #define DSI_IRQ_LP_RX_TIMEOUT	(1 << 15)
129 #define DSI_IRQ_TE_TRIGGER	(1 << 16)
130 #define DSI_IRQ_ACK_TRIGGER	(1 << 17)
131 #define DSI_IRQ_SYNC_LOST	(1 << 18)
132 #define DSI_IRQ_LDO_POWER_GOOD	(1 << 19)
133 #define DSI_IRQ_TA_TIMEOUT	(1 << 20)
134 #define DSI_IRQ_ERROR_MASK \
135 	(DSI_IRQ_HS_TX_TIMEOUT | DSI_IRQ_LP_RX_TIMEOUT | DSI_IRQ_SYNC_LOST | \
136 	DSI_IRQ_TA_TIMEOUT)
137 #define DSI_IRQ_CHANNEL_MASK	0xf
138 
139 /* Virtual channel interrupts */
140 #define DSI_VC_IRQ_CS		(1 << 0)
141 #define DSI_VC_IRQ_ECC_CORR	(1 << 1)
142 #define DSI_VC_IRQ_PACKET_SENT	(1 << 2)
143 #define DSI_VC_IRQ_FIFO_TX_OVF	(1 << 3)
144 #define DSI_VC_IRQ_FIFO_RX_OVF	(1 << 4)
145 #define DSI_VC_IRQ_BTA		(1 << 5)
146 #define DSI_VC_IRQ_ECC_NO_CORR	(1 << 6)
147 #define DSI_VC_IRQ_FIFO_TX_UDF	(1 << 7)
148 #define DSI_VC_IRQ_PP_BUSY_CHANGE (1 << 8)
149 #define DSI_VC_IRQ_ERROR_MASK \
150 	(DSI_VC_IRQ_CS | DSI_VC_IRQ_ECC_CORR | DSI_VC_IRQ_FIFO_TX_OVF | \
151 	DSI_VC_IRQ_FIFO_RX_OVF | DSI_VC_IRQ_ECC_NO_CORR | \
152 	DSI_VC_IRQ_FIFO_TX_UDF)
153 
154 /* ComplexIO interrupts */
155 #define DSI_CIO_IRQ_ERRSYNCESC1		(1 << 0)
156 #define DSI_CIO_IRQ_ERRSYNCESC2		(1 << 1)
157 #define DSI_CIO_IRQ_ERRSYNCESC3		(1 << 2)
158 #define DSI_CIO_IRQ_ERRSYNCESC4		(1 << 3)
159 #define DSI_CIO_IRQ_ERRSYNCESC5		(1 << 4)
160 #define DSI_CIO_IRQ_ERRESC1		(1 << 5)
161 #define DSI_CIO_IRQ_ERRESC2		(1 << 6)
162 #define DSI_CIO_IRQ_ERRESC3		(1 << 7)
163 #define DSI_CIO_IRQ_ERRESC4		(1 << 8)
164 #define DSI_CIO_IRQ_ERRESC5		(1 << 9)
165 #define DSI_CIO_IRQ_ERRCONTROL1		(1 << 10)
166 #define DSI_CIO_IRQ_ERRCONTROL2		(1 << 11)
167 #define DSI_CIO_IRQ_ERRCONTROL3		(1 << 12)
168 #define DSI_CIO_IRQ_ERRCONTROL4		(1 << 13)
169 #define DSI_CIO_IRQ_ERRCONTROL5		(1 << 14)
170 #define DSI_CIO_IRQ_STATEULPS1		(1 << 15)
171 #define DSI_CIO_IRQ_STATEULPS2		(1 << 16)
172 #define DSI_CIO_IRQ_STATEULPS3		(1 << 17)
173 #define DSI_CIO_IRQ_STATEULPS4		(1 << 18)
174 #define DSI_CIO_IRQ_STATEULPS5		(1 << 19)
175 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_1	(1 << 20)
176 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_1	(1 << 21)
177 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_2	(1 << 22)
178 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_2	(1 << 23)
179 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_3	(1 << 24)
180 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_3	(1 << 25)
181 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_4	(1 << 26)
182 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_4	(1 << 27)
183 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_5	(1 << 28)
184 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_5	(1 << 29)
185 #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL0	(1 << 30)
186 #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL1	(1 << 31)
187 #define DSI_CIO_IRQ_ERROR_MASK \
188 	(DSI_CIO_IRQ_ERRSYNCESC1 | DSI_CIO_IRQ_ERRSYNCESC2 | \
189 	 DSI_CIO_IRQ_ERRSYNCESC3 | DSI_CIO_IRQ_ERRSYNCESC4 | \
190 	 DSI_CIO_IRQ_ERRSYNCESC5 | \
191 	 DSI_CIO_IRQ_ERRESC1 | DSI_CIO_IRQ_ERRESC2 | \
192 	 DSI_CIO_IRQ_ERRESC3 | DSI_CIO_IRQ_ERRESC4 | \
193 	 DSI_CIO_IRQ_ERRESC5 | \
194 	 DSI_CIO_IRQ_ERRCONTROL1 | DSI_CIO_IRQ_ERRCONTROL2 | \
195 	 DSI_CIO_IRQ_ERRCONTROL3 | DSI_CIO_IRQ_ERRCONTROL4 | \
196 	 DSI_CIO_IRQ_ERRCONTROL5 | \
197 	 DSI_CIO_IRQ_ERRCONTENTIONLP0_1 | DSI_CIO_IRQ_ERRCONTENTIONLP1_1 | \
198 	 DSI_CIO_IRQ_ERRCONTENTIONLP0_2 | DSI_CIO_IRQ_ERRCONTENTIONLP1_2 | \
199 	 DSI_CIO_IRQ_ERRCONTENTIONLP0_3 | DSI_CIO_IRQ_ERRCONTENTIONLP1_3 | \
200 	 DSI_CIO_IRQ_ERRCONTENTIONLP0_4 | DSI_CIO_IRQ_ERRCONTENTIONLP1_4 | \
201 	 DSI_CIO_IRQ_ERRCONTENTIONLP0_5 | DSI_CIO_IRQ_ERRCONTENTIONLP1_5)
202 
203 typedef void (*omap_dsi_isr_t) (void *arg, u32 mask);
204 
205 static int dsi_display_init_dispc(struct platform_device *dsidev,
206 	struct omap_overlay_manager *mgr);
207 static void dsi_display_uninit_dispc(struct platform_device *dsidev,
208 	struct omap_overlay_manager *mgr);
209 
210 static int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel);
211 
212 /* DSI PLL HSDIV indices */
213 #define HSDIV_DISPC	0
214 #define HSDIV_DSI	1
215 
216 #define DSI_MAX_NR_ISRS                2
217 #define DSI_MAX_NR_LANES	5
218 
219 enum dsi_lane_function {
220 	DSI_LANE_UNUSED	= 0,
221 	DSI_LANE_CLK,
222 	DSI_LANE_DATA1,
223 	DSI_LANE_DATA2,
224 	DSI_LANE_DATA3,
225 	DSI_LANE_DATA4,
226 };
227 
228 struct dsi_lane_config {
229 	enum dsi_lane_function function;
230 	u8 polarity;
231 };
232 
233 struct dsi_isr_data {
234 	omap_dsi_isr_t	isr;
235 	void		*arg;
236 	u32		mask;
237 };
238 
239 enum fifo_size {
240 	DSI_FIFO_SIZE_0		= 0,
241 	DSI_FIFO_SIZE_32	= 1,
242 	DSI_FIFO_SIZE_64	= 2,
243 	DSI_FIFO_SIZE_96	= 3,
244 	DSI_FIFO_SIZE_128	= 4,
245 };
246 
247 enum dsi_vc_source {
248 	DSI_VC_SOURCE_L4 = 0,
249 	DSI_VC_SOURCE_VP,
250 };
251 
252 struct dsi_irq_stats {
253 	unsigned long last_reset;
254 	unsigned irq_count;
255 	unsigned dsi_irqs[32];
256 	unsigned vc_irqs[4][32];
257 	unsigned cio_irqs[32];
258 };
259 
260 struct dsi_isr_tables {
261 	struct dsi_isr_data isr_table[DSI_MAX_NR_ISRS];
262 	struct dsi_isr_data isr_table_vc[4][DSI_MAX_NR_ISRS];
263 	struct dsi_isr_data isr_table_cio[DSI_MAX_NR_ISRS];
264 };
265 
266 struct dsi_clk_calc_ctx {
267 	struct platform_device *dsidev;
268 	struct dss_pll *pll;
269 
270 	/* inputs */
271 
272 	const struct omap_dss_dsi_config *config;
273 
274 	unsigned long req_pck_min, req_pck_nom, req_pck_max;
275 
276 	/* outputs */
277 
278 	struct dss_pll_clock_info dsi_cinfo;
279 	struct dispc_clock_info dispc_cinfo;
280 
281 	struct omap_video_timings dispc_vm;
282 	struct omap_dss_dsi_videomode_timings dsi_vm;
283 };
284 
285 struct dsi_lp_clock_info {
286 	unsigned long lp_clk;
287 	u16 lp_clk_div;
288 };
289 
290 struct dsi_data {
291 	struct platform_device *pdev;
292 	void __iomem *proto_base;
293 	void __iomem *phy_base;
294 	void __iomem *pll_base;
295 
296 	int module_id;
297 
298 	int irq;
299 
300 	bool is_enabled;
301 
302 	struct clk *dss_clk;
303 
304 	struct dispc_clock_info user_dispc_cinfo;
305 	struct dss_pll_clock_info user_dsi_cinfo;
306 
307 	struct dsi_lp_clock_info user_lp_cinfo;
308 	struct dsi_lp_clock_info current_lp_cinfo;
309 
310 	struct dss_pll pll;
311 
312 	bool vdds_dsi_enabled;
313 	struct regulator *vdds_dsi_reg;
314 
315 	struct {
316 		enum dsi_vc_source source;
317 		struct omap_dss_device *dssdev;
318 		enum fifo_size tx_fifo_size;
319 		enum fifo_size rx_fifo_size;
320 		int vc_id;
321 	} vc[4];
322 
323 	struct mutex lock;
324 	struct semaphore bus_lock;
325 
326 	spinlock_t irq_lock;
327 	struct dsi_isr_tables isr_tables;
328 	/* space for a copy used by the interrupt handler */
329 	struct dsi_isr_tables isr_tables_copy;
330 
331 	int update_channel;
332 #ifdef DSI_PERF_MEASURE
333 	unsigned update_bytes;
334 #endif
335 
336 	bool te_enabled;
337 	bool ulps_enabled;
338 
339 	void (*framedone_callback)(int, void *);
340 	void *framedone_data;
341 
342 	struct delayed_work framedone_timeout_work;
343 
344 #ifdef DSI_CATCH_MISSING_TE
345 	struct timer_list te_timer;
346 #endif
347 
348 	unsigned long cache_req_pck;
349 	unsigned long cache_clk_freq;
350 	struct dss_pll_clock_info cache_cinfo;
351 
352 	u32		errors;
353 	spinlock_t	errors_lock;
354 #ifdef DSI_PERF_MEASURE
355 	ktime_t perf_setup_time;
356 	ktime_t perf_start_time;
357 #endif
358 	int debug_read;
359 	int debug_write;
360 
361 #ifdef CONFIG_FB_OMAP2_DSS_COLLECT_IRQ_STATS
362 	spinlock_t irq_stats_lock;
363 	struct dsi_irq_stats irq_stats;
364 #endif
365 
366 	unsigned num_lanes_supported;
367 	unsigned line_buffer_size;
368 
369 	struct dsi_lane_config lanes[DSI_MAX_NR_LANES];
370 	unsigned num_lanes_used;
371 
372 	unsigned scp_clk_refcount;
373 
374 	struct dss_lcd_mgr_config mgr_config;
375 	struct omap_video_timings timings;
376 	enum omap_dss_dsi_pixel_format pix_fmt;
377 	enum omap_dss_dsi_mode mode;
378 	struct omap_dss_dsi_videomode_timings vm_timings;
379 
380 	struct omap_dss_device output;
381 };
382 
383 struct dsi_packet_sent_handler_data {
384 	struct platform_device *dsidev;
385 	struct completion *completion;
386 };
387 
388 struct dsi_module_id_data {
389 	u32 address;
390 	int id;
391 };
392 
393 static const struct of_device_id dsi_of_match[];
394 
395 #ifdef DSI_PERF_MEASURE
396 static bool dsi_perf;
397 module_param(dsi_perf, bool, 0644);
398 #endif
399 
400 static inline struct dsi_data *dsi_get_dsidrv_data(struct platform_device *dsidev)
401 {
402 	return platform_get_drvdata(dsidev);
403 }
404 
405 static inline struct platform_device *dsi_get_dsidev_from_dssdev(struct omap_dss_device *dssdev)
406 {
407 	return to_platform_device(dssdev->dev);
408 }
409 
410 static struct platform_device *dsi_get_dsidev_from_id(int module)
411 {
412 	struct omap_dss_device *out;
413 	enum omap_dss_output_id	id;
414 
415 	switch (module) {
416 	case 0:
417 		id = OMAP_DSS_OUTPUT_DSI1;
418 		break;
419 	case 1:
420 		id = OMAP_DSS_OUTPUT_DSI2;
421 		break;
422 	default:
423 		return NULL;
424 	}
425 
426 	out = omap_dss_get_output(id);
427 
428 	return out ? to_platform_device(out->dev) : NULL;
429 }
430 
431 static inline void dsi_write_reg(struct platform_device *dsidev,
432 		const struct dsi_reg idx, u32 val)
433 {
434 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
435 	void __iomem *base;
436 
437 	switch(idx.module) {
438 		case DSI_PROTO: base = dsi->proto_base; break;
439 		case DSI_PHY: base = dsi->phy_base; break;
440 		case DSI_PLL: base = dsi->pll_base; break;
441 		default: return;
442 	}
443 
444 	__raw_writel(val, base + idx.idx);
445 }
446 
447 static inline u32 dsi_read_reg(struct platform_device *dsidev,
448 		const struct dsi_reg idx)
449 {
450 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
451 	void __iomem *base;
452 
453 	switch(idx.module) {
454 		case DSI_PROTO: base = dsi->proto_base; break;
455 		case DSI_PHY: base = dsi->phy_base; break;
456 		case DSI_PLL: base = dsi->pll_base; break;
457 		default: return 0;
458 	}
459 
460 	return __raw_readl(base + idx.idx);
461 }
462 
463 static void dsi_bus_lock(struct omap_dss_device *dssdev)
464 {
465 	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
466 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
467 
468 	down(&dsi->bus_lock);
469 }
470 
471 static void dsi_bus_unlock(struct omap_dss_device *dssdev)
472 {
473 	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
474 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
475 
476 	up(&dsi->bus_lock);
477 }
478 
479 static bool dsi_bus_is_locked(struct platform_device *dsidev)
480 {
481 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
482 
483 	return dsi->bus_lock.count == 0;
484 }
485 
486 static void dsi_completion_handler(void *data, u32 mask)
487 {
488 	complete((struct completion *)data);
489 }
490 
491 static inline int wait_for_bit_change(struct platform_device *dsidev,
492 		const struct dsi_reg idx, int bitnum, int value)
493 {
494 	unsigned long timeout;
495 	ktime_t wait;
496 	int t;
497 
498 	/* first busyloop to see if the bit changes right away */
499 	t = 100;
500 	while (t-- > 0) {
501 		if (REG_GET(dsidev, idx, bitnum, bitnum) == value)
502 			return value;
503 	}
504 
505 	/* then loop for 500ms, sleeping for 1ms in between */
506 	timeout = jiffies + msecs_to_jiffies(500);
507 	while (time_before(jiffies, timeout)) {
508 		if (REG_GET(dsidev, idx, bitnum, bitnum) == value)
509 			return value;
510 
511 		wait = ns_to_ktime(1000 * 1000);
512 		set_current_state(TASK_UNINTERRUPTIBLE);
513 		schedule_hrtimeout(&wait, HRTIMER_MODE_REL);
514 	}
515 
516 	return !value;
517 }
518 
519 u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt)
520 {
521 	switch (fmt) {
522 	case OMAP_DSS_DSI_FMT_RGB888:
523 	case OMAP_DSS_DSI_FMT_RGB666:
524 		return 24;
525 	case OMAP_DSS_DSI_FMT_RGB666_PACKED:
526 		return 18;
527 	case OMAP_DSS_DSI_FMT_RGB565:
528 		return 16;
529 	default:
530 		BUG();
531 		return 0;
532 	}
533 }
534 
535 #ifdef DSI_PERF_MEASURE
536 static void dsi_perf_mark_setup(struct platform_device *dsidev)
537 {
538 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
539 	dsi->perf_setup_time = ktime_get();
540 }
541 
542 static void dsi_perf_mark_start(struct platform_device *dsidev)
543 {
544 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
545 	dsi->perf_start_time = ktime_get();
546 }
547 
548 static void dsi_perf_show(struct platform_device *dsidev, const char *name)
549 {
550 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
551 	ktime_t t, setup_time, trans_time;
552 	u32 total_bytes;
553 	u32 setup_us, trans_us, total_us;
554 
555 	if (!dsi_perf)
556 		return;
557 
558 	t = ktime_get();
559 
560 	setup_time = ktime_sub(dsi->perf_start_time, dsi->perf_setup_time);
561 	setup_us = (u32)ktime_to_us(setup_time);
562 	if (setup_us == 0)
563 		setup_us = 1;
564 
565 	trans_time = ktime_sub(t, dsi->perf_start_time);
566 	trans_us = (u32)ktime_to_us(trans_time);
567 	if (trans_us == 0)
568 		trans_us = 1;
569 
570 	total_us = setup_us + trans_us;
571 
572 	total_bytes = dsi->update_bytes;
573 
574 	printk(KERN_INFO "DSI(%s): %u us + %u us = %u us (%uHz), "
575 			"%u bytes, %u kbytes/sec\n",
576 			name,
577 			setup_us,
578 			trans_us,
579 			total_us,
580 			1000*1000 / total_us,
581 			total_bytes,
582 			total_bytes * 1000 / total_us);
583 }
584 #else
585 static inline void dsi_perf_mark_setup(struct platform_device *dsidev)
586 {
587 }
588 
589 static inline void dsi_perf_mark_start(struct platform_device *dsidev)
590 {
591 }
592 
593 static inline void dsi_perf_show(struct platform_device *dsidev,
594 		const char *name)
595 {
596 }
597 #endif
598 
599 static int verbose_irq;
600 
601 static void print_irq_status(u32 status)
602 {
603 	if (status == 0)
604 		return;
605 
606 	if (!verbose_irq && (status & ~DSI_IRQ_CHANNEL_MASK) == 0)
607 		return;
608 
609 #define PIS(x) (status & DSI_IRQ_##x) ? (#x " ") : ""
610 
611 	pr_debug("DSI IRQ: 0x%x: %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n",
612 		status,
613 		verbose_irq ? PIS(VC0) : "",
614 		verbose_irq ? PIS(VC1) : "",
615 		verbose_irq ? PIS(VC2) : "",
616 		verbose_irq ? PIS(VC3) : "",
617 		PIS(WAKEUP),
618 		PIS(RESYNC),
619 		PIS(PLL_LOCK),
620 		PIS(PLL_UNLOCK),
621 		PIS(PLL_RECALL),
622 		PIS(COMPLEXIO_ERR),
623 		PIS(HS_TX_TIMEOUT),
624 		PIS(LP_RX_TIMEOUT),
625 		PIS(TE_TRIGGER),
626 		PIS(ACK_TRIGGER),
627 		PIS(SYNC_LOST),
628 		PIS(LDO_POWER_GOOD),
629 		PIS(TA_TIMEOUT));
630 #undef PIS
631 }
632 
633 static void print_irq_status_vc(int channel, u32 status)
634 {
635 	if (status == 0)
636 		return;
637 
638 	if (!verbose_irq && (status & ~DSI_VC_IRQ_PACKET_SENT) == 0)
639 		return;
640 
641 #define PIS(x) (status & DSI_VC_IRQ_##x) ? (#x " ") : ""
642 
643 	pr_debug("DSI VC(%d) IRQ 0x%x: %s%s%s%s%s%s%s%s%s\n",
644 		channel,
645 		status,
646 		PIS(CS),
647 		PIS(ECC_CORR),
648 		PIS(ECC_NO_CORR),
649 		verbose_irq ? PIS(PACKET_SENT) : "",
650 		PIS(BTA),
651 		PIS(FIFO_TX_OVF),
652 		PIS(FIFO_RX_OVF),
653 		PIS(FIFO_TX_UDF),
654 		PIS(PP_BUSY_CHANGE));
655 #undef PIS
656 }
657 
658 static void print_irq_status_cio(u32 status)
659 {
660 	if (status == 0)
661 		return;
662 
663 #define PIS(x) (status & DSI_CIO_IRQ_##x) ? (#x " ") : ""
664 
665 	pr_debug("DSI CIO IRQ 0x%x: %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n",
666 		status,
667 		PIS(ERRSYNCESC1),
668 		PIS(ERRSYNCESC2),
669 		PIS(ERRSYNCESC3),
670 		PIS(ERRESC1),
671 		PIS(ERRESC2),
672 		PIS(ERRESC3),
673 		PIS(ERRCONTROL1),
674 		PIS(ERRCONTROL2),
675 		PIS(ERRCONTROL3),
676 		PIS(STATEULPS1),
677 		PIS(STATEULPS2),
678 		PIS(STATEULPS3),
679 		PIS(ERRCONTENTIONLP0_1),
680 		PIS(ERRCONTENTIONLP1_1),
681 		PIS(ERRCONTENTIONLP0_2),
682 		PIS(ERRCONTENTIONLP1_2),
683 		PIS(ERRCONTENTIONLP0_3),
684 		PIS(ERRCONTENTIONLP1_3),
685 		PIS(ULPSACTIVENOT_ALL0),
686 		PIS(ULPSACTIVENOT_ALL1));
687 #undef PIS
688 }
689 
690 #ifdef CONFIG_FB_OMAP2_DSS_COLLECT_IRQ_STATS
691 static void dsi_collect_irq_stats(struct platform_device *dsidev, u32 irqstatus,
692 		u32 *vcstatus, u32 ciostatus)
693 {
694 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
695 	int i;
696 
697 	spin_lock(&dsi->irq_stats_lock);
698 
699 	dsi->irq_stats.irq_count++;
700 	dss_collect_irq_stats(irqstatus, dsi->irq_stats.dsi_irqs);
701 
702 	for (i = 0; i < 4; ++i)
703 		dss_collect_irq_stats(vcstatus[i], dsi->irq_stats.vc_irqs[i]);
704 
705 	dss_collect_irq_stats(ciostatus, dsi->irq_stats.cio_irqs);
706 
707 	spin_unlock(&dsi->irq_stats_lock);
708 }
709 #else
710 #define dsi_collect_irq_stats(dsidev, irqstatus, vcstatus, ciostatus)
711 #endif
712 
713 static int debug_irq;
714 
715 static void dsi_handle_irq_errors(struct platform_device *dsidev, u32 irqstatus,
716 		u32 *vcstatus, u32 ciostatus)
717 {
718 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
719 	int i;
720 
721 	if (irqstatus & DSI_IRQ_ERROR_MASK) {
722 		DSSERR("DSI error, irqstatus %x\n", irqstatus);
723 		print_irq_status(irqstatus);
724 		spin_lock(&dsi->errors_lock);
725 		dsi->errors |= irqstatus & DSI_IRQ_ERROR_MASK;
726 		spin_unlock(&dsi->errors_lock);
727 	} else if (debug_irq) {
728 		print_irq_status(irqstatus);
729 	}
730 
731 	for (i = 0; i < 4; ++i) {
732 		if (vcstatus[i] & DSI_VC_IRQ_ERROR_MASK) {
733 			DSSERR("DSI VC(%d) error, vc irqstatus %x\n",
734 				       i, vcstatus[i]);
735 			print_irq_status_vc(i, vcstatus[i]);
736 		} else if (debug_irq) {
737 			print_irq_status_vc(i, vcstatus[i]);
738 		}
739 	}
740 
741 	if (ciostatus & DSI_CIO_IRQ_ERROR_MASK) {
742 		DSSERR("DSI CIO error, cio irqstatus %x\n", ciostatus);
743 		print_irq_status_cio(ciostatus);
744 	} else if (debug_irq) {
745 		print_irq_status_cio(ciostatus);
746 	}
747 }
748 
749 static void dsi_call_isrs(struct dsi_isr_data *isr_array,
750 		unsigned isr_array_size, u32 irqstatus)
751 {
752 	struct dsi_isr_data *isr_data;
753 	int i;
754 
755 	for (i = 0; i < isr_array_size; i++) {
756 		isr_data = &isr_array[i];
757 		if (isr_data->isr && isr_data->mask & irqstatus)
758 			isr_data->isr(isr_data->arg, irqstatus);
759 	}
760 }
761 
762 static void dsi_handle_isrs(struct dsi_isr_tables *isr_tables,
763 		u32 irqstatus, u32 *vcstatus, u32 ciostatus)
764 {
765 	int i;
766 
767 	dsi_call_isrs(isr_tables->isr_table,
768 			ARRAY_SIZE(isr_tables->isr_table),
769 			irqstatus);
770 
771 	for (i = 0; i < 4; ++i) {
772 		if (vcstatus[i] == 0)
773 			continue;
774 		dsi_call_isrs(isr_tables->isr_table_vc[i],
775 				ARRAY_SIZE(isr_tables->isr_table_vc[i]),
776 				vcstatus[i]);
777 	}
778 
779 	if (ciostatus != 0)
780 		dsi_call_isrs(isr_tables->isr_table_cio,
781 				ARRAY_SIZE(isr_tables->isr_table_cio),
782 				ciostatus);
783 }
784 
785 static irqreturn_t omap_dsi_irq_handler(int irq, void *arg)
786 {
787 	struct platform_device *dsidev;
788 	struct dsi_data *dsi;
789 	u32 irqstatus, vcstatus[4], ciostatus;
790 	int i;
791 
792 	dsidev = (struct platform_device *) arg;
793 	dsi = dsi_get_dsidrv_data(dsidev);
794 
795 	if (!dsi->is_enabled)
796 		return IRQ_NONE;
797 
798 	spin_lock(&dsi->irq_lock);
799 
800 	irqstatus = dsi_read_reg(dsidev, DSI_IRQSTATUS);
801 
802 	/* IRQ is not for us */
803 	if (!irqstatus) {
804 		spin_unlock(&dsi->irq_lock);
805 		return IRQ_NONE;
806 	}
807 
808 	dsi_write_reg(dsidev, DSI_IRQSTATUS, irqstatus & ~DSI_IRQ_CHANNEL_MASK);
809 	/* flush posted write */
810 	dsi_read_reg(dsidev, DSI_IRQSTATUS);
811 
812 	for (i = 0; i < 4; ++i) {
813 		if ((irqstatus & (1 << i)) == 0) {
814 			vcstatus[i] = 0;
815 			continue;
816 		}
817 
818 		vcstatus[i] = dsi_read_reg(dsidev, DSI_VC_IRQSTATUS(i));
819 
820 		dsi_write_reg(dsidev, DSI_VC_IRQSTATUS(i), vcstatus[i]);
821 		/* flush posted write */
822 		dsi_read_reg(dsidev, DSI_VC_IRQSTATUS(i));
823 	}
824 
825 	if (irqstatus & DSI_IRQ_COMPLEXIO_ERR) {
826 		ciostatus = dsi_read_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS);
827 
828 		dsi_write_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS, ciostatus);
829 		/* flush posted write */
830 		dsi_read_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS);
831 	} else {
832 		ciostatus = 0;
833 	}
834 
835 #ifdef DSI_CATCH_MISSING_TE
836 	if (irqstatus & DSI_IRQ_TE_TRIGGER)
837 		del_timer(&dsi->te_timer);
838 #endif
839 
840 	/* make a copy and unlock, so that isrs can unregister
841 	 * themselves */
842 	memcpy(&dsi->isr_tables_copy, &dsi->isr_tables,
843 		sizeof(dsi->isr_tables));
844 
845 	spin_unlock(&dsi->irq_lock);
846 
847 	dsi_handle_isrs(&dsi->isr_tables_copy, irqstatus, vcstatus, ciostatus);
848 
849 	dsi_handle_irq_errors(dsidev, irqstatus, vcstatus, ciostatus);
850 
851 	dsi_collect_irq_stats(dsidev, irqstatus, vcstatus, ciostatus);
852 
853 	return IRQ_HANDLED;
854 }
855 
856 /* dsi->irq_lock has to be locked by the caller */
857 static void _omap_dsi_configure_irqs(struct platform_device *dsidev,
858 		struct dsi_isr_data *isr_array,
859 		unsigned isr_array_size, u32 default_mask,
860 		const struct dsi_reg enable_reg,
861 		const struct dsi_reg status_reg)
862 {
863 	struct dsi_isr_data *isr_data;
864 	u32 mask;
865 	u32 old_mask;
866 	int i;
867 
868 	mask = default_mask;
869 
870 	for (i = 0; i < isr_array_size; i++) {
871 		isr_data = &isr_array[i];
872 
873 		if (isr_data->isr == NULL)
874 			continue;
875 
876 		mask |= isr_data->mask;
877 	}
878 
879 	old_mask = dsi_read_reg(dsidev, enable_reg);
880 	/* clear the irqstatus for newly enabled irqs */
881 	dsi_write_reg(dsidev, status_reg, (mask ^ old_mask) & mask);
882 	dsi_write_reg(dsidev, enable_reg, mask);
883 
884 	/* flush posted writes */
885 	dsi_read_reg(dsidev, enable_reg);
886 	dsi_read_reg(dsidev, status_reg);
887 }
888 
889 /* dsi->irq_lock has to be locked by the caller */
890 static void _omap_dsi_set_irqs(struct platform_device *dsidev)
891 {
892 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
893 	u32 mask = DSI_IRQ_ERROR_MASK;
894 #ifdef DSI_CATCH_MISSING_TE
895 	mask |= DSI_IRQ_TE_TRIGGER;
896 #endif
897 	_omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table,
898 			ARRAY_SIZE(dsi->isr_tables.isr_table), mask,
899 			DSI_IRQENABLE, DSI_IRQSTATUS);
900 }
901 
902 /* dsi->irq_lock has to be locked by the caller */
903 static void _omap_dsi_set_irqs_vc(struct platform_device *dsidev, int vc)
904 {
905 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
906 
907 	_omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table_vc[vc],
908 			ARRAY_SIZE(dsi->isr_tables.isr_table_vc[vc]),
909 			DSI_VC_IRQ_ERROR_MASK,
910 			DSI_VC_IRQENABLE(vc), DSI_VC_IRQSTATUS(vc));
911 }
912 
913 /* dsi->irq_lock has to be locked by the caller */
914 static void _omap_dsi_set_irqs_cio(struct platform_device *dsidev)
915 {
916 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
917 
918 	_omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table_cio,
919 			ARRAY_SIZE(dsi->isr_tables.isr_table_cio),
920 			DSI_CIO_IRQ_ERROR_MASK,
921 			DSI_COMPLEXIO_IRQ_ENABLE, DSI_COMPLEXIO_IRQ_STATUS);
922 }
923 
924 static void _dsi_initialize_irq(struct platform_device *dsidev)
925 {
926 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
927 	unsigned long flags;
928 	int vc;
929 
930 	spin_lock_irqsave(&dsi->irq_lock, flags);
931 
932 	memset(&dsi->isr_tables, 0, sizeof(dsi->isr_tables));
933 
934 	_omap_dsi_set_irqs(dsidev);
935 	for (vc = 0; vc < 4; ++vc)
936 		_omap_dsi_set_irqs_vc(dsidev, vc);
937 	_omap_dsi_set_irqs_cio(dsidev);
938 
939 	spin_unlock_irqrestore(&dsi->irq_lock, flags);
940 }
941 
942 static int _dsi_register_isr(omap_dsi_isr_t isr, void *arg, u32 mask,
943 		struct dsi_isr_data *isr_array, unsigned isr_array_size)
944 {
945 	struct dsi_isr_data *isr_data;
946 	int free_idx;
947 	int i;
948 
949 	BUG_ON(isr == NULL);
950 
951 	/* check for duplicate entry and find a free slot */
952 	free_idx = -1;
953 	for (i = 0; i < isr_array_size; i++) {
954 		isr_data = &isr_array[i];
955 
956 		if (isr_data->isr == isr && isr_data->arg == arg &&
957 				isr_data->mask == mask) {
958 			return -EINVAL;
959 		}
960 
961 		if (isr_data->isr == NULL && free_idx == -1)
962 			free_idx = i;
963 	}
964 
965 	if (free_idx == -1)
966 		return -EBUSY;
967 
968 	isr_data = &isr_array[free_idx];
969 	isr_data->isr = isr;
970 	isr_data->arg = arg;
971 	isr_data->mask = mask;
972 
973 	return 0;
974 }
975 
976 static int _dsi_unregister_isr(omap_dsi_isr_t isr, void *arg, u32 mask,
977 		struct dsi_isr_data *isr_array, unsigned isr_array_size)
978 {
979 	struct dsi_isr_data *isr_data;
980 	int i;
981 
982 	for (i = 0; i < isr_array_size; i++) {
983 		isr_data = &isr_array[i];
984 		if (isr_data->isr != isr || isr_data->arg != arg ||
985 				isr_data->mask != mask)
986 			continue;
987 
988 		isr_data->isr = NULL;
989 		isr_data->arg = NULL;
990 		isr_data->mask = 0;
991 
992 		return 0;
993 	}
994 
995 	return -EINVAL;
996 }
997 
998 static int dsi_register_isr(struct platform_device *dsidev, omap_dsi_isr_t isr,
999 		void *arg, u32 mask)
1000 {
1001 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1002 	unsigned long flags;
1003 	int r;
1004 
1005 	spin_lock_irqsave(&dsi->irq_lock, flags);
1006 
1007 	r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table,
1008 			ARRAY_SIZE(dsi->isr_tables.isr_table));
1009 
1010 	if (r == 0)
1011 		_omap_dsi_set_irqs(dsidev);
1012 
1013 	spin_unlock_irqrestore(&dsi->irq_lock, flags);
1014 
1015 	return r;
1016 }
1017 
1018 static int dsi_unregister_isr(struct platform_device *dsidev,
1019 		omap_dsi_isr_t isr, void *arg, u32 mask)
1020 {
1021 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1022 	unsigned long flags;
1023 	int r;
1024 
1025 	spin_lock_irqsave(&dsi->irq_lock, flags);
1026 
1027 	r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table,
1028 			ARRAY_SIZE(dsi->isr_tables.isr_table));
1029 
1030 	if (r == 0)
1031 		_omap_dsi_set_irqs(dsidev);
1032 
1033 	spin_unlock_irqrestore(&dsi->irq_lock, flags);
1034 
1035 	return r;
1036 }
1037 
1038 static int dsi_register_isr_vc(struct platform_device *dsidev, int channel,
1039 		omap_dsi_isr_t isr, void *arg, u32 mask)
1040 {
1041 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1042 	unsigned long flags;
1043 	int r;
1044 
1045 	spin_lock_irqsave(&dsi->irq_lock, flags);
1046 
1047 	r = _dsi_register_isr(isr, arg, mask,
1048 			dsi->isr_tables.isr_table_vc[channel],
1049 			ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel]));
1050 
1051 	if (r == 0)
1052 		_omap_dsi_set_irqs_vc(dsidev, channel);
1053 
1054 	spin_unlock_irqrestore(&dsi->irq_lock, flags);
1055 
1056 	return r;
1057 }
1058 
1059 static int dsi_unregister_isr_vc(struct platform_device *dsidev, int channel,
1060 		omap_dsi_isr_t isr, void *arg, u32 mask)
1061 {
1062 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1063 	unsigned long flags;
1064 	int r;
1065 
1066 	spin_lock_irqsave(&dsi->irq_lock, flags);
1067 
1068 	r = _dsi_unregister_isr(isr, arg, mask,
1069 			dsi->isr_tables.isr_table_vc[channel],
1070 			ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel]));
1071 
1072 	if (r == 0)
1073 		_omap_dsi_set_irqs_vc(dsidev, channel);
1074 
1075 	spin_unlock_irqrestore(&dsi->irq_lock, flags);
1076 
1077 	return r;
1078 }
1079 
1080 static int dsi_register_isr_cio(struct platform_device *dsidev,
1081 		omap_dsi_isr_t isr, void *arg, u32 mask)
1082 {
1083 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1084 	unsigned long flags;
1085 	int r;
1086 
1087 	spin_lock_irqsave(&dsi->irq_lock, flags);
1088 
1089 	r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio,
1090 			ARRAY_SIZE(dsi->isr_tables.isr_table_cio));
1091 
1092 	if (r == 0)
1093 		_omap_dsi_set_irqs_cio(dsidev);
1094 
1095 	spin_unlock_irqrestore(&dsi->irq_lock, flags);
1096 
1097 	return r;
1098 }
1099 
1100 static int dsi_unregister_isr_cio(struct platform_device *dsidev,
1101 		omap_dsi_isr_t isr, void *arg, u32 mask)
1102 {
1103 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1104 	unsigned long flags;
1105 	int r;
1106 
1107 	spin_lock_irqsave(&dsi->irq_lock, flags);
1108 
1109 	r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio,
1110 			ARRAY_SIZE(dsi->isr_tables.isr_table_cio));
1111 
1112 	if (r == 0)
1113 		_omap_dsi_set_irqs_cio(dsidev);
1114 
1115 	spin_unlock_irqrestore(&dsi->irq_lock, flags);
1116 
1117 	return r;
1118 }
1119 
1120 static u32 dsi_get_errors(struct platform_device *dsidev)
1121 {
1122 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1123 	unsigned long flags;
1124 	u32 e;
1125 	spin_lock_irqsave(&dsi->errors_lock, flags);
1126 	e = dsi->errors;
1127 	dsi->errors = 0;
1128 	spin_unlock_irqrestore(&dsi->errors_lock, flags);
1129 	return e;
1130 }
1131 
1132 static int dsi_runtime_get(struct platform_device *dsidev)
1133 {
1134 	int r;
1135 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1136 
1137 	DSSDBG("dsi_runtime_get\n");
1138 
1139 	r = pm_runtime_get_sync(&dsi->pdev->dev);
1140 	if (WARN_ON(r < 0)) {
1141 		pm_runtime_put_sync(&dsi->pdev->dev);
1142 		return r;
1143 	}
1144 	return 0;
1145 }
1146 
1147 static void dsi_runtime_put(struct platform_device *dsidev)
1148 {
1149 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1150 	int r;
1151 
1152 	DSSDBG("dsi_runtime_put\n");
1153 
1154 	r = pm_runtime_put_sync(&dsi->pdev->dev);
1155 	WARN_ON(r < 0 && r != -ENOSYS);
1156 }
1157 
1158 static int dsi_regulator_init(struct platform_device *dsidev)
1159 {
1160 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1161 	struct regulator *vdds_dsi;
1162 
1163 	if (dsi->vdds_dsi_reg != NULL)
1164 		return 0;
1165 
1166 	vdds_dsi = devm_regulator_get(&dsi->pdev->dev, "vdd");
1167 
1168 	if (IS_ERR(vdds_dsi)) {
1169 		if (PTR_ERR(vdds_dsi) != -EPROBE_DEFER)
1170 			DSSERR("can't get DSI VDD regulator\n");
1171 		return PTR_ERR(vdds_dsi);
1172 	}
1173 
1174 	dsi->vdds_dsi_reg = vdds_dsi;
1175 
1176 	return 0;
1177 }
1178 
1179 static void _dsi_print_reset_status(struct platform_device *dsidev)
1180 {
1181 	int b0, b1, b2;
1182 
1183 	/* A dummy read using the SCP interface to any DSIPHY register is
1184 	 * required after DSIPHY reset to complete the reset of the DSI complex
1185 	 * I/O. */
1186 	dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
1187 
1188 	if (dss_has_feature(FEAT_DSI_REVERSE_TXCLKESC)) {
1189 		b0 = 28;
1190 		b1 = 27;
1191 		b2 = 26;
1192 	} else {
1193 		b0 = 24;
1194 		b1 = 25;
1195 		b2 = 26;
1196 	}
1197 
1198 #define DSI_FLD_GET(fld, start, end)\
1199 	FLD_GET(dsi_read_reg(dsidev, DSI_##fld), start, end)
1200 
1201 	pr_debug("DSI resets: PLL (%d) CIO (%d) PHY (%x%x%x, %d, %d, %d)\n",
1202 		DSI_FLD_GET(PLL_STATUS, 0, 0),
1203 		DSI_FLD_GET(COMPLEXIO_CFG1, 29, 29),
1204 		DSI_FLD_GET(DSIPHY_CFG5, b0, b0),
1205 		DSI_FLD_GET(DSIPHY_CFG5, b1, b1),
1206 		DSI_FLD_GET(DSIPHY_CFG5, b2, b2),
1207 		DSI_FLD_GET(DSIPHY_CFG5, 29, 29),
1208 		DSI_FLD_GET(DSIPHY_CFG5, 30, 30),
1209 		DSI_FLD_GET(DSIPHY_CFG5, 31, 31));
1210 
1211 #undef DSI_FLD_GET
1212 }
1213 
1214 static inline int dsi_if_enable(struct platform_device *dsidev, bool enable)
1215 {
1216 	DSSDBG("dsi_if_enable(%d)\n", enable);
1217 
1218 	enable = enable ? 1 : 0;
1219 	REG_FLD_MOD(dsidev, DSI_CTRL, enable, 0, 0); /* IF_EN */
1220 
1221 	if (wait_for_bit_change(dsidev, DSI_CTRL, 0, enable) != enable) {
1222 			DSSERR("Failed to set dsi_if_enable to %d\n", enable);
1223 			return -EIO;
1224 	}
1225 
1226 	return 0;
1227 }
1228 
1229 static unsigned long dsi_get_pll_hsdiv_dispc_rate(struct platform_device *dsidev)
1230 {
1231 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1232 
1233 	return dsi->pll.cinfo.clkout[HSDIV_DISPC];
1234 }
1235 
1236 static unsigned long dsi_get_pll_hsdiv_dsi_rate(struct platform_device *dsidev)
1237 {
1238 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1239 
1240 	return dsi->pll.cinfo.clkout[HSDIV_DSI];
1241 }
1242 
1243 static unsigned long dsi_get_txbyteclkhs(struct platform_device *dsidev)
1244 {
1245 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1246 
1247 	return dsi->pll.cinfo.clkdco / 16;
1248 }
1249 
1250 static unsigned long dsi_fclk_rate(struct platform_device *dsidev)
1251 {
1252 	unsigned long r;
1253 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1254 
1255 	if (dss_get_dsi_clk_source(dsi->module_id) == OMAP_DSS_CLK_SRC_FCK) {
1256 		/* DSI FCLK source is DSS_CLK_FCK */
1257 		r = clk_get_rate(dsi->dss_clk);
1258 	} else {
1259 		/* DSI FCLK source is dsi_pll_hsdiv_dsi_clk */
1260 		r = dsi_get_pll_hsdiv_dsi_rate(dsidev);
1261 	}
1262 
1263 	return r;
1264 }
1265 
1266 static int dsi_lp_clock_calc(unsigned long dsi_fclk,
1267 		unsigned long lp_clk_min, unsigned long lp_clk_max,
1268 		struct dsi_lp_clock_info *lp_cinfo)
1269 {
1270 	unsigned lp_clk_div;
1271 	unsigned long lp_clk;
1272 
1273 	lp_clk_div = DIV_ROUND_UP(dsi_fclk, lp_clk_max * 2);
1274 	lp_clk = dsi_fclk / 2 / lp_clk_div;
1275 
1276 	if (lp_clk < lp_clk_min || lp_clk > lp_clk_max)
1277 		return -EINVAL;
1278 
1279 	lp_cinfo->lp_clk_div = lp_clk_div;
1280 	lp_cinfo->lp_clk = lp_clk;
1281 
1282 	return 0;
1283 }
1284 
1285 static int dsi_set_lp_clk_divisor(struct platform_device *dsidev)
1286 {
1287 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1288 	unsigned long dsi_fclk;
1289 	unsigned lp_clk_div;
1290 	unsigned long lp_clk;
1291 	unsigned lpdiv_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_LPDIV);
1292 
1293 
1294 	lp_clk_div = dsi->user_lp_cinfo.lp_clk_div;
1295 
1296 	if (lp_clk_div == 0 || lp_clk_div > lpdiv_max)
1297 		return -EINVAL;
1298 
1299 	dsi_fclk = dsi_fclk_rate(dsidev);
1300 
1301 	lp_clk = dsi_fclk / 2 / lp_clk_div;
1302 
1303 	DSSDBG("LP_CLK_DIV %u, LP_CLK %lu\n", lp_clk_div, lp_clk);
1304 	dsi->current_lp_cinfo.lp_clk = lp_clk;
1305 	dsi->current_lp_cinfo.lp_clk_div = lp_clk_div;
1306 
1307 	/* LP_CLK_DIVISOR */
1308 	REG_FLD_MOD(dsidev, DSI_CLK_CTRL, lp_clk_div, 12, 0);
1309 
1310 	/* LP_RX_SYNCHRO_ENABLE */
1311 	REG_FLD_MOD(dsidev, DSI_CLK_CTRL, dsi_fclk > 30000000 ? 1 : 0, 21, 21);
1312 
1313 	return 0;
1314 }
1315 
1316 static void dsi_enable_scp_clk(struct platform_device *dsidev)
1317 {
1318 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1319 
1320 	if (dsi->scp_clk_refcount++ == 0)
1321 		REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 14, 14); /* CIO_CLK_ICG */
1322 }
1323 
1324 static void dsi_disable_scp_clk(struct platform_device *dsidev)
1325 {
1326 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1327 
1328 	WARN_ON(dsi->scp_clk_refcount == 0);
1329 	if (--dsi->scp_clk_refcount == 0)
1330 		REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 14, 14); /* CIO_CLK_ICG */
1331 }
1332 
1333 enum dsi_pll_power_state {
1334 	DSI_PLL_POWER_OFF	= 0x0,
1335 	DSI_PLL_POWER_ON_HSCLK	= 0x1,
1336 	DSI_PLL_POWER_ON_ALL	= 0x2,
1337 	DSI_PLL_POWER_ON_DIV	= 0x3,
1338 };
1339 
1340 static int dsi_pll_power(struct platform_device *dsidev,
1341 		enum dsi_pll_power_state state)
1342 {
1343 	int t = 0;
1344 
1345 	/* DSI-PLL power command 0x3 is not working */
1346 	if (dss_has_feature(FEAT_DSI_PLL_PWR_BUG) &&
1347 			state == DSI_PLL_POWER_ON_DIV)
1348 		state = DSI_PLL_POWER_ON_ALL;
1349 
1350 	/* PLL_PWR_CMD */
1351 	REG_FLD_MOD(dsidev, DSI_CLK_CTRL, state, 31, 30);
1352 
1353 	/* PLL_PWR_STATUS */
1354 	while (FLD_GET(dsi_read_reg(dsidev, DSI_CLK_CTRL), 29, 28) != state) {
1355 		if (++t > 1000) {
1356 			DSSERR("Failed to set DSI PLL power mode to %d\n",
1357 					state);
1358 			return -ENODEV;
1359 		}
1360 		udelay(1);
1361 	}
1362 
1363 	return 0;
1364 }
1365 
1366 
1367 static void dsi_pll_calc_dsi_fck(struct dss_pll_clock_info *cinfo)
1368 {
1369 	unsigned long max_dsi_fck;
1370 
1371 	max_dsi_fck = dss_feat_get_param_max(FEAT_PARAM_DSI_FCK);
1372 
1373 	cinfo->mX[HSDIV_DSI] = DIV_ROUND_UP(cinfo->clkdco, max_dsi_fck);
1374 	cinfo->clkout[HSDIV_DSI] = cinfo->clkdco / cinfo->mX[HSDIV_DSI];
1375 }
1376 
1377 static int dsi_pll_enable(struct dss_pll *pll)
1378 {
1379 	struct dsi_data *dsi = container_of(pll, struct dsi_data, pll);
1380 	struct platform_device *dsidev = dsi->pdev;
1381 	int r = 0;
1382 
1383 	DSSDBG("PLL init\n");
1384 
1385 	r = dsi_regulator_init(dsidev);
1386 	if (r)
1387 		return r;
1388 
1389 	r = dsi_runtime_get(dsidev);
1390 	if (r)
1391 		return r;
1392 
1393 	/*
1394 	 * Note: SCP CLK is not required on OMAP3, but it is required on OMAP4.
1395 	 */
1396 	dsi_enable_scp_clk(dsidev);
1397 
1398 	if (!dsi->vdds_dsi_enabled) {
1399 		r = regulator_enable(dsi->vdds_dsi_reg);
1400 		if (r)
1401 			goto err0;
1402 		dsi->vdds_dsi_enabled = true;
1403 	}
1404 
1405 	/* XXX PLL does not come out of reset without this... */
1406 	dispc_pck_free_enable(1);
1407 
1408 	if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 0, 1) != 1) {
1409 		DSSERR("PLL not coming out of reset.\n");
1410 		r = -ENODEV;
1411 		dispc_pck_free_enable(0);
1412 		goto err1;
1413 	}
1414 
1415 	/* XXX ... but if left on, we get problems when planes do not
1416 	 * fill the whole display. No idea about this */
1417 	dispc_pck_free_enable(0);
1418 
1419 	r = dsi_pll_power(dsidev, DSI_PLL_POWER_ON_ALL);
1420 
1421 	if (r)
1422 		goto err1;
1423 
1424 	DSSDBG("PLL init done\n");
1425 
1426 	return 0;
1427 err1:
1428 	if (dsi->vdds_dsi_enabled) {
1429 		regulator_disable(dsi->vdds_dsi_reg);
1430 		dsi->vdds_dsi_enabled = false;
1431 	}
1432 err0:
1433 	dsi_disable_scp_clk(dsidev);
1434 	dsi_runtime_put(dsidev);
1435 	return r;
1436 }
1437 
1438 static void dsi_pll_uninit(struct platform_device *dsidev, bool disconnect_lanes)
1439 {
1440 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1441 
1442 	dsi_pll_power(dsidev, DSI_PLL_POWER_OFF);
1443 	if (disconnect_lanes) {
1444 		WARN_ON(!dsi->vdds_dsi_enabled);
1445 		regulator_disable(dsi->vdds_dsi_reg);
1446 		dsi->vdds_dsi_enabled = false;
1447 	}
1448 
1449 	dsi_disable_scp_clk(dsidev);
1450 	dsi_runtime_put(dsidev);
1451 
1452 	DSSDBG("PLL uninit done\n");
1453 }
1454 
1455 static void dsi_pll_disable(struct dss_pll *pll)
1456 {
1457 	struct dsi_data *dsi = container_of(pll, struct dsi_data, pll);
1458 	struct platform_device *dsidev = dsi->pdev;
1459 
1460 	dsi_pll_uninit(dsidev, true);
1461 }
1462 
1463 static void dsi_dump_dsidev_clocks(struct platform_device *dsidev,
1464 		struct seq_file *s)
1465 {
1466 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1467 	struct dss_pll_clock_info *cinfo = &dsi->pll.cinfo;
1468 	enum omap_dss_clk_source dispc_clk_src, dsi_clk_src;
1469 	int dsi_module = dsi->module_id;
1470 	struct dss_pll *pll = &dsi->pll;
1471 
1472 	dispc_clk_src = dss_get_dispc_clk_source();
1473 	dsi_clk_src = dss_get_dsi_clk_source(dsi_module);
1474 
1475 	if (dsi_runtime_get(dsidev))
1476 		return;
1477 
1478 	seq_printf(s,	"- DSI%d PLL -\n", dsi_module + 1);
1479 
1480 	seq_printf(s,	"dsi pll clkin\t%lu\n", clk_get_rate(pll->clkin));
1481 
1482 	seq_printf(s,	"Fint\t\t%-16lun %u\n", cinfo->fint, cinfo->n);
1483 
1484 	seq_printf(s,	"CLKIN4DDR\t%-16lum %u\n",
1485 			cinfo->clkdco, cinfo->m);
1486 
1487 	seq_printf(s,	"DSI_PLL_HSDIV_DISPC (%s)\t%-16lum_dispc %u\t(%s)\n",
1488 			dss_feat_get_clk_source_name(dsi_module == 0 ?
1489 				OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC :
1490 				OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC),
1491 			cinfo->clkout[HSDIV_DISPC],
1492 			cinfo->mX[HSDIV_DISPC],
1493 			dispc_clk_src == OMAP_DSS_CLK_SRC_FCK ?
1494 			"off" : "on");
1495 
1496 	seq_printf(s,	"DSI_PLL_HSDIV_DSI (%s)\t%-16lum_dsi %u\t(%s)\n",
1497 			dss_feat_get_clk_source_name(dsi_module == 0 ?
1498 				OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI :
1499 				OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI),
1500 			cinfo->clkout[HSDIV_DSI],
1501 			cinfo->mX[HSDIV_DSI],
1502 			dsi_clk_src == OMAP_DSS_CLK_SRC_FCK ?
1503 			"off" : "on");
1504 
1505 	seq_printf(s,	"- DSI%d -\n", dsi_module + 1);
1506 
1507 	seq_printf(s,	"dsi fclk source = %s (%s)\n",
1508 			dss_get_generic_clk_source_name(dsi_clk_src),
1509 			dss_feat_get_clk_source_name(dsi_clk_src));
1510 
1511 	seq_printf(s,	"DSI_FCLK\t%lu\n", dsi_fclk_rate(dsidev));
1512 
1513 	seq_printf(s,	"DDR_CLK\t\t%lu\n",
1514 			cinfo->clkdco / 4);
1515 
1516 	seq_printf(s,	"TxByteClkHS\t%lu\n", dsi_get_txbyteclkhs(dsidev));
1517 
1518 	seq_printf(s,	"LP_CLK\t\t%lu\n", dsi->current_lp_cinfo.lp_clk);
1519 
1520 	dsi_runtime_put(dsidev);
1521 }
1522 
1523 void dsi_dump_clocks(struct seq_file *s)
1524 {
1525 	struct platform_device *dsidev;
1526 	int i;
1527 
1528 	for  (i = 0; i < MAX_NUM_DSI; i++) {
1529 		dsidev = dsi_get_dsidev_from_id(i);
1530 		if (dsidev)
1531 			dsi_dump_dsidev_clocks(dsidev, s);
1532 	}
1533 }
1534 
1535 #ifdef CONFIG_FB_OMAP2_DSS_COLLECT_IRQ_STATS
1536 static void dsi_dump_dsidev_irqs(struct platform_device *dsidev,
1537 		struct seq_file *s)
1538 {
1539 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1540 	unsigned long flags;
1541 	struct dsi_irq_stats stats;
1542 
1543 	spin_lock_irqsave(&dsi->irq_stats_lock, flags);
1544 
1545 	stats = dsi->irq_stats;
1546 	memset(&dsi->irq_stats, 0, sizeof(dsi->irq_stats));
1547 	dsi->irq_stats.last_reset = jiffies;
1548 
1549 	spin_unlock_irqrestore(&dsi->irq_stats_lock, flags);
1550 
1551 	seq_printf(s, "period %u ms\n",
1552 			jiffies_to_msecs(jiffies - stats.last_reset));
1553 
1554 	seq_printf(s, "irqs %d\n", stats.irq_count);
1555 #define PIS(x) \
1556 	seq_printf(s, "%-20s %10d\n", #x, stats.dsi_irqs[ffs(DSI_IRQ_##x)-1])
1557 
1558 	seq_printf(s, "-- DSI%d interrupts --\n", dsi->module_id + 1);
1559 	PIS(VC0);
1560 	PIS(VC1);
1561 	PIS(VC2);
1562 	PIS(VC3);
1563 	PIS(WAKEUP);
1564 	PIS(RESYNC);
1565 	PIS(PLL_LOCK);
1566 	PIS(PLL_UNLOCK);
1567 	PIS(PLL_RECALL);
1568 	PIS(COMPLEXIO_ERR);
1569 	PIS(HS_TX_TIMEOUT);
1570 	PIS(LP_RX_TIMEOUT);
1571 	PIS(TE_TRIGGER);
1572 	PIS(ACK_TRIGGER);
1573 	PIS(SYNC_LOST);
1574 	PIS(LDO_POWER_GOOD);
1575 	PIS(TA_TIMEOUT);
1576 #undef PIS
1577 
1578 #define PIS(x) \
1579 	seq_printf(s, "%-20s %10d %10d %10d %10d\n", #x, \
1580 			stats.vc_irqs[0][ffs(DSI_VC_IRQ_##x)-1], \
1581 			stats.vc_irqs[1][ffs(DSI_VC_IRQ_##x)-1], \
1582 			stats.vc_irqs[2][ffs(DSI_VC_IRQ_##x)-1], \
1583 			stats.vc_irqs[3][ffs(DSI_VC_IRQ_##x)-1]);
1584 
1585 	seq_printf(s, "-- VC interrupts --\n");
1586 	PIS(CS);
1587 	PIS(ECC_CORR);
1588 	PIS(PACKET_SENT);
1589 	PIS(FIFO_TX_OVF);
1590 	PIS(FIFO_RX_OVF);
1591 	PIS(BTA);
1592 	PIS(ECC_NO_CORR);
1593 	PIS(FIFO_TX_UDF);
1594 	PIS(PP_BUSY_CHANGE);
1595 #undef PIS
1596 
1597 #define PIS(x) \
1598 	seq_printf(s, "%-20s %10d\n", #x, \
1599 			stats.cio_irqs[ffs(DSI_CIO_IRQ_##x)-1]);
1600 
1601 	seq_printf(s, "-- CIO interrupts --\n");
1602 	PIS(ERRSYNCESC1);
1603 	PIS(ERRSYNCESC2);
1604 	PIS(ERRSYNCESC3);
1605 	PIS(ERRESC1);
1606 	PIS(ERRESC2);
1607 	PIS(ERRESC3);
1608 	PIS(ERRCONTROL1);
1609 	PIS(ERRCONTROL2);
1610 	PIS(ERRCONTROL3);
1611 	PIS(STATEULPS1);
1612 	PIS(STATEULPS2);
1613 	PIS(STATEULPS3);
1614 	PIS(ERRCONTENTIONLP0_1);
1615 	PIS(ERRCONTENTIONLP1_1);
1616 	PIS(ERRCONTENTIONLP0_2);
1617 	PIS(ERRCONTENTIONLP1_2);
1618 	PIS(ERRCONTENTIONLP0_3);
1619 	PIS(ERRCONTENTIONLP1_3);
1620 	PIS(ULPSACTIVENOT_ALL0);
1621 	PIS(ULPSACTIVENOT_ALL1);
1622 #undef PIS
1623 }
1624 
1625 static void dsi1_dump_irqs(struct seq_file *s)
1626 {
1627 	struct platform_device *dsidev = dsi_get_dsidev_from_id(0);
1628 
1629 	dsi_dump_dsidev_irqs(dsidev, s);
1630 }
1631 
1632 static void dsi2_dump_irqs(struct seq_file *s)
1633 {
1634 	struct platform_device *dsidev = dsi_get_dsidev_from_id(1);
1635 
1636 	dsi_dump_dsidev_irqs(dsidev, s);
1637 }
1638 #endif
1639 
1640 static void dsi_dump_dsidev_regs(struct platform_device *dsidev,
1641 		struct seq_file *s)
1642 {
1643 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(dsidev, r))
1644 
1645 	if (dsi_runtime_get(dsidev))
1646 		return;
1647 	dsi_enable_scp_clk(dsidev);
1648 
1649 	DUMPREG(DSI_REVISION);
1650 	DUMPREG(DSI_SYSCONFIG);
1651 	DUMPREG(DSI_SYSSTATUS);
1652 	DUMPREG(DSI_IRQSTATUS);
1653 	DUMPREG(DSI_IRQENABLE);
1654 	DUMPREG(DSI_CTRL);
1655 	DUMPREG(DSI_COMPLEXIO_CFG1);
1656 	DUMPREG(DSI_COMPLEXIO_IRQ_STATUS);
1657 	DUMPREG(DSI_COMPLEXIO_IRQ_ENABLE);
1658 	DUMPREG(DSI_CLK_CTRL);
1659 	DUMPREG(DSI_TIMING1);
1660 	DUMPREG(DSI_TIMING2);
1661 	DUMPREG(DSI_VM_TIMING1);
1662 	DUMPREG(DSI_VM_TIMING2);
1663 	DUMPREG(DSI_VM_TIMING3);
1664 	DUMPREG(DSI_CLK_TIMING);
1665 	DUMPREG(DSI_TX_FIFO_VC_SIZE);
1666 	DUMPREG(DSI_RX_FIFO_VC_SIZE);
1667 	DUMPREG(DSI_COMPLEXIO_CFG2);
1668 	DUMPREG(DSI_RX_FIFO_VC_FULLNESS);
1669 	DUMPREG(DSI_VM_TIMING4);
1670 	DUMPREG(DSI_TX_FIFO_VC_EMPTINESS);
1671 	DUMPREG(DSI_VM_TIMING5);
1672 	DUMPREG(DSI_VM_TIMING6);
1673 	DUMPREG(DSI_VM_TIMING7);
1674 	DUMPREG(DSI_STOPCLK_TIMING);
1675 
1676 	DUMPREG(DSI_VC_CTRL(0));
1677 	DUMPREG(DSI_VC_TE(0));
1678 	DUMPREG(DSI_VC_LONG_PACKET_HEADER(0));
1679 	DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(0));
1680 	DUMPREG(DSI_VC_SHORT_PACKET_HEADER(0));
1681 	DUMPREG(DSI_VC_IRQSTATUS(0));
1682 	DUMPREG(DSI_VC_IRQENABLE(0));
1683 
1684 	DUMPREG(DSI_VC_CTRL(1));
1685 	DUMPREG(DSI_VC_TE(1));
1686 	DUMPREG(DSI_VC_LONG_PACKET_HEADER(1));
1687 	DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(1));
1688 	DUMPREG(DSI_VC_SHORT_PACKET_HEADER(1));
1689 	DUMPREG(DSI_VC_IRQSTATUS(1));
1690 	DUMPREG(DSI_VC_IRQENABLE(1));
1691 
1692 	DUMPREG(DSI_VC_CTRL(2));
1693 	DUMPREG(DSI_VC_TE(2));
1694 	DUMPREG(DSI_VC_LONG_PACKET_HEADER(2));
1695 	DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(2));
1696 	DUMPREG(DSI_VC_SHORT_PACKET_HEADER(2));
1697 	DUMPREG(DSI_VC_IRQSTATUS(2));
1698 	DUMPREG(DSI_VC_IRQENABLE(2));
1699 
1700 	DUMPREG(DSI_VC_CTRL(3));
1701 	DUMPREG(DSI_VC_TE(3));
1702 	DUMPREG(DSI_VC_LONG_PACKET_HEADER(3));
1703 	DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(3));
1704 	DUMPREG(DSI_VC_SHORT_PACKET_HEADER(3));
1705 	DUMPREG(DSI_VC_IRQSTATUS(3));
1706 	DUMPREG(DSI_VC_IRQENABLE(3));
1707 
1708 	DUMPREG(DSI_DSIPHY_CFG0);
1709 	DUMPREG(DSI_DSIPHY_CFG1);
1710 	DUMPREG(DSI_DSIPHY_CFG2);
1711 	DUMPREG(DSI_DSIPHY_CFG5);
1712 
1713 	DUMPREG(DSI_PLL_CONTROL);
1714 	DUMPREG(DSI_PLL_STATUS);
1715 	DUMPREG(DSI_PLL_GO);
1716 	DUMPREG(DSI_PLL_CONFIGURATION1);
1717 	DUMPREG(DSI_PLL_CONFIGURATION2);
1718 
1719 	dsi_disable_scp_clk(dsidev);
1720 	dsi_runtime_put(dsidev);
1721 #undef DUMPREG
1722 }
1723 
1724 static void dsi1_dump_regs(struct seq_file *s)
1725 {
1726 	struct platform_device *dsidev = dsi_get_dsidev_from_id(0);
1727 
1728 	dsi_dump_dsidev_regs(dsidev, s);
1729 }
1730 
1731 static void dsi2_dump_regs(struct seq_file *s)
1732 {
1733 	struct platform_device *dsidev = dsi_get_dsidev_from_id(1);
1734 
1735 	dsi_dump_dsidev_regs(dsidev, s);
1736 }
1737 
1738 enum dsi_cio_power_state {
1739 	DSI_COMPLEXIO_POWER_OFF		= 0x0,
1740 	DSI_COMPLEXIO_POWER_ON		= 0x1,
1741 	DSI_COMPLEXIO_POWER_ULPS	= 0x2,
1742 };
1743 
1744 static int dsi_cio_power(struct platform_device *dsidev,
1745 		enum dsi_cio_power_state state)
1746 {
1747 	int t = 0;
1748 
1749 	/* PWR_CMD */
1750 	REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG1, state, 28, 27);
1751 
1752 	/* PWR_STATUS */
1753 	while (FLD_GET(dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1),
1754 			26, 25) != state) {
1755 		if (++t > 1000) {
1756 			DSSERR("failed to set complexio power state to "
1757 					"%d\n", state);
1758 			return -ENODEV;
1759 		}
1760 		udelay(1);
1761 	}
1762 
1763 	return 0;
1764 }
1765 
1766 static unsigned dsi_get_line_buf_size(struct platform_device *dsidev)
1767 {
1768 	int val;
1769 
1770 	/* line buffer on OMAP3 is 1024 x 24bits */
1771 	/* XXX: for some reason using full buffer size causes
1772 	 * considerable TX slowdown with update sizes that fill the
1773 	 * whole buffer */
1774 	if (!dss_has_feature(FEAT_DSI_GNQ))
1775 		return 1023 * 3;
1776 
1777 	val = REG_GET(dsidev, DSI_GNQ, 14, 12); /* VP1_LINE_BUFFER_SIZE */
1778 
1779 	switch (val) {
1780 	case 1:
1781 		return 512 * 3;		/* 512x24 bits */
1782 	case 2:
1783 		return 682 * 3;		/* 682x24 bits */
1784 	case 3:
1785 		return 853 * 3;		/* 853x24 bits */
1786 	case 4:
1787 		return 1024 * 3;	/* 1024x24 bits */
1788 	case 5:
1789 		return 1194 * 3;	/* 1194x24 bits */
1790 	case 6:
1791 		return 1365 * 3;	/* 1365x24 bits */
1792 	case 7:
1793 		return 1920 * 3;	/* 1920x24 bits */
1794 	default:
1795 		BUG();
1796 		return 0;
1797 	}
1798 }
1799 
1800 static int dsi_set_lane_config(struct platform_device *dsidev)
1801 {
1802 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1803 	static const u8 offsets[] = { 0, 4, 8, 12, 16 };
1804 	static const enum dsi_lane_function functions[] = {
1805 		DSI_LANE_CLK,
1806 		DSI_LANE_DATA1,
1807 		DSI_LANE_DATA2,
1808 		DSI_LANE_DATA3,
1809 		DSI_LANE_DATA4,
1810 	};
1811 	u32 r;
1812 	int i;
1813 
1814 	r = dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1);
1815 
1816 	for (i = 0; i < dsi->num_lanes_used; ++i) {
1817 		unsigned offset = offsets[i];
1818 		unsigned polarity, lane_number;
1819 		unsigned t;
1820 
1821 		for (t = 0; t < dsi->num_lanes_supported; ++t)
1822 			if (dsi->lanes[t].function == functions[i])
1823 				break;
1824 
1825 		if (t == dsi->num_lanes_supported)
1826 			return -EINVAL;
1827 
1828 		lane_number = t;
1829 		polarity = dsi->lanes[t].polarity;
1830 
1831 		r = FLD_MOD(r, lane_number + 1, offset + 2, offset);
1832 		r = FLD_MOD(r, polarity, offset + 3, offset + 3);
1833 	}
1834 
1835 	/* clear the unused lanes */
1836 	for (; i < dsi->num_lanes_supported; ++i) {
1837 		unsigned offset = offsets[i];
1838 
1839 		r = FLD_MOD(r, 0, offset + 2, offset);
1840 		r = FLD_MOD(r, 0, offset + 3, offset + 3);
1841 	}
1842 
1843 	dsi_write_reg(dsidev, DSI_COMPLEXIO_CFG1, r);
1844 
1845 	return 0;
1846 }
1847 
1848 static inline unsigned ns2ddr(struct platform_device *dsidev, unsigned ns)
1849 {
1850 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1851 
1852 	/* convert time in ns to ddr ticks, rounding up */
1853 	unsigned long ddr_clk = dsi->pll.cinfo.clkdco / 4;
1854 	return (ns * (ddr_clk / 1000 / 1000) + 999) / 1000;
1855 }
1856 
1857 static inline unsigned ddr2ns(struct platform_device *dsidev, unsigned ddr)
1858 {
1859 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1860 
1861 	unsigned long ddr_clk = dsi->pll.cinfo.clkdco / 4;
1862 	return ddr * 1000 * 1000 / (ddr_clk / 1000);
1863 }
1864 
1865 static void dsi_cio_timings(struct platform_device *dsidev)
1866 {
1867 	u32 r;
1868 	u32 ths_prepare, ths_prepare_ths_zero, ths_trail, ths_exit;
1869 	u32 tlpx_half, tclk_trail, tclk_zero;
1870 	u32 tclk_prepare;
1871 
1872 	/* calculate timings */
1873 
1874 	/* 1 * DDR_CLK = 2 * UI */
1875 
1876 	/* min 40ns + 4*UI	max 85ns + 6*UI */
1877 	ths_prepare = ns2ddr(dsidev, 70) + 2;
1878 
1879 	/* min 145ns + 10*UI */
1880 	ths_prepare_ths_zero = ns2ddr(dsidev, 175) + 2;
1881 
1882 	/* min max(8*UI, 60ns+4*UI) */
1883 	ths_trail = ns2ddr(dsidev, 60) + 5;
1884 
1885 	/* min 100ns */
1886 	ths_exit = ns2ddr(dsidev, 145);
1887 
1888 	/* tlpx min 50n */
1889 	tlpx_half = ns2ddr(dsidev, 25);
1890 
1891 	/* min 60ns */
1892 	tclk_trail = ns2ddr(dsidev, 60) + 2;
1893 
1894 	/* min 38ns, max 95ns */
1895 	tclk_prepare = ns2ddr(dsidev, 65);
1896 
1897 	/* min tclk-prepare + tclk-zero = 300ns */
1898 	tclk_zero = ns2ddr(dsidev, 260);
1899 
1900 	DSSDBG("ths_prepare %u (%uns), ths_prepare_ths_zero %u (%uns)\n",
1901 		ths_prepare, ddr2ns(dsidev, ths_prepare),
1902 		ths_prepare_ths_zero, ddr2ns(dsidev, ths_prepare_ths_zero));
1903 	DSSDBG("ths_trail %u (%uns), ths_exit %u (%uns)\n",
1904 			ths_trail, ddr2ns(dsidev, ths_trail),
1905 			ths_exit, ddr2ns(dsidev, ths_exit));
1906 
1907 	DSSDBG("tlpx_half %u (%uns), tclk_trail %u (%uns), "
1908 			"tclk_zero %u (%uns)\n",
1909 			tlpx_half, ddr2ns(dsidev, tlpx_half),
1910 			tclk_trail, ddr2ns(dsidev, tclk_trail),
1911 			tclk_zero, ddr2ns(dsidev, tclk_zero));
1912 	DSSDBG("tclk_prepare %u (%uns)\n",
1913 			tclk_prepare, ddr2ns(dsidev, tclk_prepare));
1914 
1915 	/* program timings */
1916 
1917 	r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0);
1918 	r = FLD_MOD(r, ths_prepare, 31, 24);
1919 	r = FLD_MOD(r, ths_prepare_ths_zero, 23, 16);
1920 	r = FLD_MOD(r, ths_trail, 15, 8);
1921 	r = FLD_MOD(r, ths_exit, 7, 0);
1922 	dsi_write_reg(dsidev, DSI_DSIPHY_CFG0, r);
1923 
1924 	r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1);
1925 	r = FLD_MOD(r, tlpx_half, 20, 16);
1926 	r = FLD_MOD(r, tclk_trail, 15, 8);
1927 	r = FLD_MOD(r, tclk_zero, 7, 0);
1928 
1929 	if (dss_has_feature(FEAT_DSI_PHY_DCC)) {
1930 		r = FLD_MOD(r, 0, 21, 21);	/* DCCEN = disable */
1931 		r = FLD_MOD(r, 1, 22, 22);	/* CLKINP_DIVBY2EN = enable */
1932 		r = FLD_MOD(r, 1, 23, 23);	/* CLKINP_SEL = enable */
1933 	}
1934 
1935 	dsi_write_reg(dsidev, DSI_DSIPHY_CFG1, r);
1936 
1937 	r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG2);
1938 	r = FLD_MOD(r, tclk_prepare, 7, 0);
1939 	dsi_write_reg(dsidev, DSI_DSIPHY_CFG2, r);
1940 }
1941 
1942 /* lane masks have lane 0 at lsb. mask_p for positive lines, n for negative */
1943 static void dsi_cio_enable_lane_override(struct platform_device *dsidev,
1944 		unsigned mask_p, unsigned mask_n)
1945 {
1946 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1947 	int i;
1948 	u32 l;
1949 	u8 lptxscp_start = dsi->num_lanes_supported == 3 ? 22 : 26;
1950 
1951 	l = 0;
1952 
1953 	for (i = 0; i < dsi->num_lanes_supported; ++i) {
1954 		unsigned p = dsi->lanes[i].polarity;
1955 
1956 		if (mask_p & (1 << i))
1957 			l |= 1 << (i * 2 + (p ? 0 : 1));
1958 
1959 		if (mask_n & (1 << i))
1960 			l |= 1 << (i * 2 + (p ? 1 : 0));
1961 	}
1962 
1963 	/*
1964 	 * Bits in REGLPTXSCPDAT4TO0DXDY:
1965 	 * 17: DY0 18: DX0
1966 	 * 19: DY1 20: DX1
1967 	 * 21: DY2 22: DX2
1968 	 * 23: DY3 24: DX3
1969 	 * 25: DY4 26: DX4
1970 	 */
1971 
1972 	/* Set the lane override configuration */
1973 
1974 	/* REGLPTXSCPDAT4TO0DXDY */
1975 	REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, l, lptxscp_start, 17);
1976 
1977 	/* Enable lane override */
1978 
1979 	/* ENLPTXSCPDAT */
1980 	REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 1, 27, 27);
1981 }
1982 
1983 static void dsi_cio_disable_lane_override(struct platform_device *dsidev)
1984 {
1985 	/* Disable lane override */
1986 	REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 0, 27, 27); /* ENLPTXSCPDAT */
1987 	/* Reset the lane override configuration */
1988 	/* REGLPTXSCPDAT4TO0DXDY */
1989 	REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 0, 22, 17);
1990 }
1991 
1992 static int dsi_cio_wait_tx_clk_esc_reset(struct platform_device *dsidev)
1993 {
1994 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1995 	int t, i;
1996 	bool in_use[DSI_MAX_NR_LANES];
1997 	static const u8 offsets_old[] = { 28, 27, 26 };
1998 	static const u8 offsets_new[] = { 24, 25, 26, 27, 28 };
1999 	const u8 *offsets;
2000 
2001 	if (dss_has_feature(FEAT_DSI_REVERSE_TXCLKESC))
2002 		offsets = offsets_old;
2003 	else
2004 		offsets = offsets_new;
2005 
2006 	for (i = 0; i < dsi->num_lanes_supported; ++i)
2007 		in_use[i] = dsi->lanes[i].function != DSI_LANE_UNUSED;
2008 
2009 	t = 100000;
2010 	while (true) {
2011 		u32 l;
2012 		int ok;
2013 
2014 		l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
2015 
2016 		ok = 0;
2017 		for (i = 0; i < dsi->num_lanes_supported; ++i) {
2018 			if (!in_use[i] || (l & (1 << offsets[i])))
2019 				ok++;
2020 		}
2021 
2022 		if (ok == dsi->num_lanes_supported)
2023 			break;
2024 
2025 		if (--t == 0) {
2026 			for (i = 0; i < dsi->num_lanes_supported; ++i) {
2027 				if (!in_use[i] || (l & (1 << offsets[i])))
2028 					continue;
2029 
2030 				DSSERR("CIO TXCLKESC%d domain not coming " \
2031 						"out of reset\n", i);
2032 			}
2033 			return -EIO;
2034 		}
2035 	}
2036 
2037 	return 0;
2038 }
2039 
2040 /* return bitmask of enabled lanes, lane0 being the lsb */
2041 static unsigned dsi_get_lane_mask(struct platform_device *dsidev)
2042 {
2043 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2044 	unsigned mask = 0;
2045 	int i;
2046 
2047 	for (i = 0; i < dsi->num_lanes_supported; ++i) {
2048 		if (dsi->lanes[i].function != DSI_LANE_UNUSED)
2049 			mask |= 1 << i;
2050 	}
2051 
2052 	return mask;
2053 }
2054 
2055 static int dsi_cio_init(struct platform_device *dsidev)
2056 {
2057 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2058 	int r;
2059 	u32 l;
2060 
2061 	DSSDBG("DSI CIO init starts");
2062 
2063 	r = dss_dsi_enable_pads(dsi->module_id, dsi_get_lane_mask(dsidev));
2064 	if (r)
2065 		return r;
2066 
2067 	dsi_enable_scp_clk(dsidev);
2068 
2069 	/* A dummy read using the SCP interface to any DSIPHY register is
2070 	 * required after DSIPHY reset to complete the reset of the DSI complex
2071 	 * I/O. */
2072 	dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
2073 
2074 	if (wait_for_bit_change(dsidev, DSI_DSIPHY_CFG5, 30, 1) != 1) {
2075 		DSSERR("CIO SCP Clock domain not coming out of reset.\n");
2076 		r = -EIO;
2077 		goto err_scp_clk_dom;
2078 	}
2079 
2080 	r = dsi_set_lane_config(dsidev);
2081 	if (r)
2082 		goto err_scp_clk_dom;
2083 
2084 	/* set TX STOP MODE timer to maximum for this operation */
2085 	l = dsi_read_reg(dsidev, DSI_TIMING1);
2086 	l = FLD_MOD(l, 1, 15, 15);	/* FORCE_TX_STOP_MODE_IO */
2087 	l = FLD_MOD(l, 1, 14, 14);	/* STOP_STATE_X16_IO */
2088 	l = FLD_MOD(l, 1, 13, 13);	/* STOP_STATE_X4_IO */
2089 	l = FLD_MOD(l, 0x1fff, 12, 0);	/* STOP_STATE_COUNTER_IO */
2090 	dsi_write_reg(dsidev, DSI_TIMING1, l);
2091 
2092 	if (dsi->ulps_enabled) {
2093 		unsigned mask_p;
2094 		int i;
2095 
2096 		DSSDBG("manual ulps exit\n");
2097 
2098 		/* ULPS is exited by Mark-1 state for 1ms, followed by
2099 		 * stop state. DSS HW cannot do this via the normal
2100 		 * ULPS exit sequence, as after reset the DSS HW thinks
2101 		 * that we are not in ULPS mode, and refuses to send the
2102 		 * sequence. So we need to send the ULPS exit sequence
2103 		 * manually by setting positive lines high and negative lines
2104 		 * low for 1ms.
2105 		 */
2106 
2107 		mask_p = 0;
2108 
2109 		for (i = 0; i < dsi->num_lanes_supported; ++i) {
2110 			if (dsi->lanes[i].function == DSI_LANE_UNUSED)
2111 				continue;
2112 			mask_p |= 1 << i;
2113 		}
2114 
2115 		dsi_cio_enable_lane_override(dsidev, mask_p, 0);
2116 	}
2117 
2118 	r = dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_ON);
2119 	if (r)
2120 		goto err_cio_pwr;
2121 
2122 	if (wait_for_bit_change(dsidev, DSI_COMPLEXIO_CFG1, 29, 1) != 1) {
2123 		DSSERR("CIO PWR clock domain not coming out of reset.\n");
2124 		r = -ENODEV;
2125 		goto err_cio_pwr_dom;
2126 	}
2127 
2128 	dsi_if_enable(dsidev, true);
2129 	dsi_if_enable(dsidev, false);
2130 	REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 20, 20); /* LP_CLK_ENABLE */
2131 
2132 	r = dsi_cio_wait_tx_clk_esc_reset(dsidev);
2133 	if (r)
2134 		goto err_tx_clk_esc_rst;
2135 
2136 	if (dsi->ulps_enabled) {
2137 		/* Keep Mark-1 state for 1ms (as per DSI spec) */
2138 		ktime_t wait = ns_to_ktime(1000 * 1000);
2139 		set_current_state(TASK_UNINTERRUPTIBLE);
2140 		schedule_hrtimeout(&wait, HRTIMER_MODE_REL);
2141 
2142 		/* Disable the override. The lanes should be set to Mark-11
2143 		 * state by the HW */
2144 		dsi_cio_disable_lane_override(dsidev);
2145 	}
2146 
2147 	/* FORCE_TX_STOP_MODE_IO */
2148 	REG_FLD_MOD(dsidev, DSI_TIMING1, 0, 15, 15);
2149 
2150 	dsi_cio_timings(dsidev);
2151 
2152 	if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
2153 		/* DDR_CLK_ALWAYS_ON */
2154 		REG_FLD_MOD(dsidev, DSI_CLK_CTRL,
2155 			dsi->vm_timings.ddr_clk_always_on, 13, 13);
2156 	}
2157 
2158 	dsi->ulps_enabled = false;
2159 
2160 	DSSDBG("CIO init done\n");
2161 
2162 	return 0;
2163 
2164 err_tx_clk_esc_rst:
2165 	REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 20, 20); /* LP_CLK_ENABLE */
2166 err_cio_pwr_dom:
2167 	dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_OFF);
2168 err_cio_pwr:
2169 	if (dsi->ulps_enabled)
2170 		dsi_cio_disable_lane_override(dsidev);
2171 err_scp_clk_dom:
2172 	dsi_disable_scp_clk(dsidev);
2173 	dss_dsi_disable_pads(dsi->module_id, dsi_get_lane_mask(dsidev));
2174 	return r;
2175 }
2176 
2177 static void dsi_cio_uninit(struct platform_device *dsidev)
2178 {
2179 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2180 
2181 	/* DDR_CLK_ALWAYS_ON */
2182 	REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 13, 13);
2183 
2184 	dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_OFF);
2185 	dsi_disable_scp_clk(dsidev);
2186 	dss_dsi_disable_pads(dsi->module_id, dsi_get_lane_mask(dsidev));
2187 }
2188 
2189 static void dsi_config_tx_fifo(struct platform_device *dsidev,
2190 		enum fifo_size size1, enum fifo_size size2,
2191 		enum fifo_size size3, enum fifo_size size4)
2192 {
2193 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2194 	u32 r = 0;
2195 	int add = 0;
2196 	int i;
2197 
2198 	dsi->vc[0].tx_fifo_size = size1;
2199 	dsi->vc[1].tx_fifo_size = size2;
2200 	dsi->vc[2].tx_fifo_size = size3;
2201 	dsi->vc[3].tx_fifo_size = size4;
2202 
2203 	for (i = 0; i < 4; i++) {
2204 		u8 v;
2205 		int size = dsi->vc[i].tx_fifo_size;
2206 
2207 		if (add + size > 4) {
2208 			DSSERR("Illegal FIFO configuration\n");
2209 			BUG();
2210 			return;
2211 		}
2212 
2213 		v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
2214 		r |= v << (8 * i);
2215 		/*DSSDBG("TX FIFO vc %d: size %d, add %d\n", i, size, add); */
2216 		add += size;
2217 	}
2218 
2219 	dsi_write_reg(dsidev, DSI_TX_FIFO_VC_SIZE, r);
2220 }
2221 
2222 static void dsi_config_rx_fifo(struct platform_device *dsidev,
2223 		enum fifo_size size1, enum fifo_size size2,
2224 		enum fifo_size size3, enum fifo_size size4)
2225 {
2226 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2227 	u32 r = 0;
2228 	int add = 0;
2229 	int i;
2230 
2231 	dsi->vc[0].rx_fifo_size = size1;
2232 	dsi->vc[1].rx_fifo_size = size2;
2233 	dsi->vc[2].rx_fifo_size = size3;
2234 	dsi->vc[3].rx_fifo_size = size4;
2235 
2236 	for (i = 0; i < 4; i++) {
2237 		u8 v;
2238 		int size = dsi->vc[i].rx_fifo_size;
2239 
2240 		if (add + size > 4) {
2241 			DSSERR("Illegal FIFO configuration\n");
2242 			BUG();
2243 			return;
2244 		}
2245 
2246 		v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
2247 		r |= v << (8 * i);
2248 		/*DSSDBG("RX FIFO vc %d: size %d, add %d\n", i, size, add); */
2249 		add += size;
2250 	}
2251 
2252 	dsi_write_reg(dsidev, DSI_RX_FIFO_VC_SIZE, r);
2253 }
2254 
2255 static int dsi_force_tx_stop_mode_io(struct platform_device *dsidev)
2256 {
2257 	u32 r;
2258 
2259 	r = dsi_read_reg(dsidev, DSI_TIMING1);
2260 	r = FLD_MOD(r, 1, 15, 15);	/* FORCE_TX_STOP_MODE_IO */
2261 	dsi_write_reg(dsidev, DSI_TIMING1, r);
2262 
2263 	if (wait_for_bit_change(dsidev, DSI_TIMING1, 15, 0) != 0) {
2264 		DSSERR("TX_STOP bit not going down\n");
2265 		return -EIO;
2266 	}
2267 
2268 	return 0;
2269 }
2270 
2271 static bool dsi_vc_is_enabled(struct platform_device *dsidev, int channel)
2272 {
2273 	return REG_GET(dsidev, DSI_VC_CTRL(channel), 0, 0);
2274 }
2275 
2276 static void dsi_packet_sent_handler_vp(void *data, u32 mask)
2277 {
2278 	struct dsi_packet_sent_handler_data *vp_data =
2279 		(struct dsi_packet_sent_handler_data *) data;
2280 	struct dsi_data *dsi = dsi_get_dsidrv_data(vp_data->dsidev);
2281 	const int channel = dsi->update_channel;
2282 	u8 bit = dsi->te_enabled ? 30 : 31;
2283 
2284 	if (REG_GET(vp_data->dsidev, DSI_VC_TE(channel), bit, bit) == 0)
2285 		complete(vp_data->completion);
2286 }
2287 
2288 static int dsi_sync_vc_vp(struct platform_device *dsidev, int channel)
2289 {
2290 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2291 	DECLARE_COMPLETION_ONSTACK(completion);
2292 	struct dsi_packet_sent_handler_data vp_data = {
2293 		.dsidev = dsidev,
2294 		.completion = &completion
2295 	};
2296 	int r = 0;
2297 	u8 bit;
2298 
2299 	bit = dsi->te_enabled ? 30 : 31;
2300 
2301 	r = dsi_register_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp,
2302 		&vp_data, DSI_VC_IRQ_PACKET_SENT);
2303 	if (r)
2304 		goto err0;
2305 
2306 	/* Wait for completion only if TE_EN/TE_START is still set */
2307 	if (REG_GET(dsidev, DSI_VC_TE(channel), bit, bit)) {
2308 		if (wait_for_completion_timeout(&completion,
2309 				msecs_to_jiffies(10)) == 0) {
2310 			DSSERR("Failed to complete previous frame transfer\n");
2311 			r = -EIO;
2312 			goto err1;
2313 		}
2314 	}
2315 
2316 	dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp,
2317 		&vp_data, DSI_VC_IRQ_PACKET_SENT);
2318 
2319 	return 0;
2320 err1:
2321 	dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp,
2322 		&vp_data, DSI_VC_IRQ_PACKET_SENT);
2323 err0:
2324 	return r;
2325 }
2326 
2327 static void dsi_packet_sent_handler_l4(void *data, u32 mask)
2328 {
2329 	struct dsi_packet_sent_handler_data *l4_data =
2330 		(struct dsi_packet_sent_handler_data *) data;
2331 	struct dsi_data *dsi = dsi_get_dsidrv_data(l4_data->dsidev);
2332 	const int channel = dsi->update_channel;
2333 
2334 	if (REG_GET(l4_data->dsidev, DSI_VC_CTRL(channel), 5, 5) == 0)
2335 		complete(l4_data->completion);
2336 }
2337 
2338 static int dsi_sync_vc_l4(struct platform_device *dsidev, int channel)
2339 {
2340 	DECLARE_COMPLETION_ONSTACK(completion);
2341 	struct dsi_packet_sent_handler_data l4_data = {
2342 		.dsidev = dsidev,
2343 		.completion = &completion
2344 	};
2345 	int r = 0;
2346 
2347 	r = dsi_register_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4,
2348 		&l4_data, DSI_VC_IRQ_PACKET_SENT);
2349 	if (r)
2350 		goto err0;
2351 
2352 	/* Wait for completion only if TX_FIFO_NOT_EMPTY is still set */
2353 	if (REG_GET(dsidev, DSI_VC_CTRL(channel), 5, 5)) {
2354 		if (wait_for_completion_timeout(&completion,
2355 				msecs_to_jiffies(10)) == 0) {
2356 			DSSERR("Failed to complete previous l4 transfer\n");
2357 			r = -EIO;
2358 			goto err1;
2359 		}
2360 	}
2361 
2362 	dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4,
2363 		&l4_data, DSI_VC_IRQ_PACKET_SENT);
2364 
2365 	return 0;
2366 err1:
2367 	dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4,
2368 		&l4_data, DSI_VC_IRQ_PACKET_SENT);
2369 err0:
2370 	return r;
2371 }
2372 
2373 static int dsi_sync_vc(struct platform_device *dsidev, int channel)
2374 {
2375 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2376 
2377 	WARN_ON(!dsi_bus_is_locked(dsidev));
2378 
2379 	if (!dsi_vc_is_enabled(dsidev, channel))
2380 		return 0;
2381 
2382 	switch (dsi->vc[channel].source) {
2383 	case DSI_VC_SOURCE_VP:
2384 		return dsi_sync_vc_vp(dsidev, channel);
2385 	case DSI_VC_SOURCE_L4:
2386 		return dsi_sync_vc_l4(dsidev, channel);
2387 	default:
2388 		BUG();
2389 		return -EINVAL;
2390 	}
2391 }
2392 
2393 static int dsi_vc_enable(struct platform_device *dsidev, int channel,
2394 		bool enable)
2395 {
2396 	DSSDBG("dsi_vc_enable channel %d, enable %d\n",
2397 			channel, enable);
2398 
2399 	enable = enable ? 1 : 0;
2400 
2401 	REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 0, 0);
2402 
2403 	if (wait_for_bit_change(dsidev, DSI_VC_CTRL(channel),
2404 		0, enable) != enable) {
2405 			DSSERR("Failed to set dsi_vc_enable to %d\n", enable);
2406 			return -EIO;
2407 	}
2408 
2409 	return 0;
2410 }
2411 
2412 static void dsi_vc_initial_config(struct platform_device *dsidev, int channel)
2413 {
2414 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2415 	u32 r;
2416 
2417 	DSSDBG("Initial config of virtual channel %d", channel);
2418 
2419 	r = dsi_read_reg(dsidev, DSI_VC_CTRL(channel));
2420 
2421 	if (FLD_GET(r, 15, 15)) /* VC_BUSY */
2422 		DSSERR("VC(%d) busy when trying to configure it!\n",
2423 				channel);
2424 
2425 	r = FLD_MOD(r, 0, 1, 1); /* SOURCE, 0 = L4 */
2426 	r = FLD_MOD(r, 0, 2, 2); /* BTA_SHORT_EN  */
2427 	r = FLD_MOD(r, 0, 3, 3); /* BTA_LONG_EN */
2428 	r = FLD_MOD(r, 0, 4, 4); /* MODE, 0 = command */
2429 	r = FLD_MOD(r, 1, 7, 7); /* CS_TX_EN */
2430 	r = FLD_MOD(r, 1, 8, 8); /* ECC_TX_EN */
2431 	r = FLD_MOD(r, 0, 9, 9); /* MODE_SPEED, high speed on/off */
2432 	if (dss_has_feature(FEAT_DSI_VC_OCP_WIDTH))
2433 		r = FLD_MOD(r, 3, 11, 10);	/* OCP_WIDTH = 32 bit */
2434 
2435 	r = FLD_MOD(r, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */
2436 	r = FLD_MOD(r, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */
2437 
2438 	dsi_write_reg(dsidev, DSI_VC_CTRL(channel), r);
2439 
2440 	dsi->vc[channel].source = DSI_VC_SOURCE_L4;
2441 }
2442 
2443 static int dsi_vc_config_source(struct platform_device *dsidev, int channel,
2444 		enum dsi_vc_source source)
2445 {
2446 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2447 
2448 	if (dsi->vc[channel].source == source)
2449 		return 0;
2450 
2451 	DSSDBG("Source config of virtual channel %d", channel);
2452 
2453 	dsi_sync_vc(dsidev, channel);
2454 
2455 	dsi_vc_enable(dsidev, channel, 0);
2456 
2457 	/* VC_BUSY */
2458 	if (wait_for_bit_change(dsidev, DSI_VC_CTRL(channel), 15, 0) != 0) {
2459 		DSSERR("vc(%d) busy when trying to config for VP\n", channel);
2460 		return -EIO;
2461 	}
2462 
2463 	/* SOURCE, 0 = L4, 1 = video port */
2464 	REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), source, 1, 1);
2465 
2466 	/* DCS_CMD_ENABLE */
2467 	if (dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC)) {
2468 		bool enable = source == DSI_VC_SOURCE_VP;
2469 		REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 30, 30);
2470 	}
2471 
2472 	dsi_vc_enable(dsidev, channel, 1);
2473 
2474 	dsi->vc[channel].source = source;
2475 
2476 	return 0;
2477 }
2478 
2479 static void dsi_vc_enable_hs(struct omap_dss_device *dssdev, int channel,
2480 		bool enable)
2481 {
2482 	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2483 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2484 
2485 	DSSDBG("dsi_vc_enable_hs(%d, %d)\n", channel, enable);
2486 
2487 	WARN_ON(!dsi_bus_is_locked(dsidev));
2488 
2489 	dsi_vc_enable(dsidev, channel, 0);
2490 	dsi_if_enable(dsidev, 0);
2491 
2492 	REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 9, 9);
2493 
2494 	dsi_vc_enable(dsidev, channel, 1);
2495 	dsi_if_enable(dsidev, 1);
2496 
2497 	dsi_force_tx_stop_mode_io(dsidev);
2498 
2499 	/* start the DDR clock by sending a NULL packet */
2500 	if (dsi->vm_timings.ddr_clk_always_on && enable)
2501 		dsi_vc_send_null(dssdev, channel);
2502 }
2503 
2504 static void dsi_vc_flush_long_data(struct platform_device *dsidev, int channel)
2505 {
2506 	while (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
2507 		u32 val;
2508 		val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));
2509 		DSSDBG("\t\tb1 %#02x b2 %#02x b3 %#02x b4 %#02x\n",
2510 				(val >> 0) & 0xff,
2511 				(val >> 8) & 0xff,
2512 				(val >> 16) & 0xff,
2513 				(val >> 24) & 0xff);
2514 	}
2515 }
2516 
2517 static void dsi_show_rx_ack_with_err(u16 err)
2518 {
2519 	DSSERR("\tACK with ERROR (%#x):\n", err);
2520 	if (err & (1 << 0))
2521 		DSSERR("\t\tSoT Error\n");
2522 	if (err & (1 << 1))
2523 		DSSERR("\t\tSoT Sync Error\n");
2524 	if (err & (1 << 2))
2525 		DSSERR("\t\tEoT Sync Error\n");
2526 	if (err & (1 << 3))
2527 		DSSERR("\t\tEscape Mode Entry Command Error\n");
2528 	if (err & (1 << 4))
2529 		DSSERR("\t\tLP Transmit Sync Error\n");
2530 	if (err & (1 << 5))
2531 		DSSERR("\t\tHS Receive Timeout Error\n");
2532 	if (err & (1 << 6))
2533 		DSSERR("\t\tFalse Control Error\n");
2534 	if (err & (1 << 7))
2535 		DSSERR("\t\t(reserved7)\n");
2536 	if (err & (1 << 8))
2537 		DSSERR("\t\tECC Error, single-bit (corrected)\n");
2538 	if (err & (1 << 9))
2539 		DSSERR("\t\tECC Error, multi-bit (not corrected)\n");
2540 	if (err & (1 << 10))
2541 		DSSERR("\t\tChecksum Error\n");
2542 	if (err & (1 << 11))
2543 		DSSERR("\t\tData type not recognized\n");
2544 	if (err & (1 << 12))
2545 		DSSERR("\t\tInvalid VC ID\n");
2546 	if (err & (1 << 13))
2547 		DSSERR("\t\tInvalid Transmission Length\n");
2548 	if (err & (1 << 14))
2549 		DSSERR("\t\t(reserved14)\n");
2550 	if (err & (1 << 15))
2551 		DSSERR("\t\tDSI Protocol Violation\n");
2552 }
2553 
2554 static u16 dsi_vc_flush_receive_data(struct platform_device *dsidev,
2555 		int channel)
2556 {
2557 	/* RX_FIFO_NOT_EMPTY */
2558 	while (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
2559 		u32 val;
2560 		u8 dt;
2561 		val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));
2562 		DSSERR("\trawval %#08x\n", val);
2563 		dt = FLD_GET(val, 5, 0);
2564 		if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) {
2565 			u16 err = FLD_GET(val, 23, 8);
2566 			dsi_show_rx_ack_with_err(err);
2567 		} else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE) {
2568 			DSSERR("\tDCS short response, 1 byte: %#x\n",
2569 					FLD_GET(val, 23, 8));
2570 		} else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE) {
2571 			DSSERR("\tDCS short response, 2 byte: %#x\n",
2572 					FLD_GET(val, 23, 8));
2573 		} else if (dt == MIPI_DSI_RX_DCS_LONG_READ_RESPONSE) {
2574 			DSSERR("\tDCS long response, len %d\n",
2575 					FLD_GET(val, 23, 8));
2576 			dsi_vc_flush_long_data(dsidev, channel);
2577 		} else {
2578 			DSSERR("\tunknown datatype 0x%02x\n", dt);
2579 		}
2580 	}
2581 	return 0;
2582 }
2583 
2584 static int dsi_vc_send_bta(struct platform_device *dsidev, int channel)
2585 {
2586 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2587 
2588 	if (dsi->debug_write || dsi->debug_read)
2589 		DSSDBG("dsi_vc_send_bta %d\n", channel);
2590 
2591 	WARN_ON(!dsi_bus_is_locked(dsidev));
2592 
2593 	/* RX_FIFO_NOT_EMPTY */
2594 	if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
2595 		DSSERR("rx fifo not empty when sending BTA, dumping data:\n");
2596 		dsi_vc_flush_receive_data(dsidev, channel);
2597 	}
2598 
2599 	REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 1, 6, 6); /* BTA_EN */
2600 
2601 	/* flush posted write */
2602 	dsi_read_reg(dsidev, DSI_VC_CTRL(channel));
2603 
2604 	return 0;
2605 }
2606 
2607 static int dsi_vc_send_bta_sync(struct omap_dss_device *dssdev, int channel)
2608 {
2609 	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2610 	DECLARE_COMPLETION_ONSTACK(completion);
2611 	int r = 0;
2612 	u32 err;
2613 
2614 	r = dsi_register_isr_vc(dsidev, channel, dsi_completion_handler,
2615 			&completion, DSI_VC_IRQ_BTA);
2616 	if (r)
2617 		goto err0;
2618 
2619 	r = dsi_register_isr(dsidev, dsi_completion_handler, &completion,
2620 			DSI_IRQ_ERROR_MASK);
2621 	if (r)
2622 		goto err1;
2623 
2624 	r = dsi_vc_send_bta(dsidev, channel);
2625 	if (r)
2626 		goto err2;
2627 
2628 	if (wait_for_completion_timeout(&completion,
2629 				msecs_to_jiffies(500)) == 0) {
2630 		DSSERR("Failed to receive BTA\n");
2631 		r = -EIO;
2632 		goto err2;
2633 	}
2634 
2635 	err = dsi_get_errors(dsidev);
2636 	if (err) {
2637 		DSSERR("Error while sending BTA: %x\n", err);
2638 		r = -EIO;
2639 		goto err2;
2640 	}
2641 err2:
2642 	dsi_unregister_isr(dsidev, dsi_completion_handler, &completion,
2643 			DSI_IRQ_ERROR_MASK);
2644 err1:
2645 	dsi_unregister_isr_vc(dsidev, channel, dsi_completion_handler,
2646 			&completion, DSI_VC_IRQ_BTA);
2647 err0:
2648 	return r;
2649 }
2650 
2651 static inline void dsi_vc_write_long_header(struct platform_device *dsidev,
2652 		int channel, u8 data_type, u16 len, u8 ecc)
2653 {
2654 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2655 	u32 val;
2656 	u8 data_id;
2657 
2658 	WARN_ON(!dsi_bus_is_locked(dsidev));
2659 
2660 	data_id = data_type | dsi->vc[channel].vc_id << 6;
2661 
2662 	val = FLD_VAL(data_id, 7, 0) | FLD_VAL(len, 23, 8) |
2663 		FLD_VAL(ecc, 31, 24);
2664 
2665 	dsi_write_reg(dsidev, DSI_VC_LONG_PACKET_HEADER(channel), val);
2666 }
2667 
2668 static inline void dsi_vc_write_long_payload(struct platform_device *dsidev,
2669 		int channel, u8 b1, u8 b2, u8 b3, u8 b4)
2670 {
2671 	u32 val;
2672 
2673 	val = b4 << 24 | b3 << 16 | b2 << 8  | b1 << 0;
2674 
2675 /*	DSSDBG("\twriting %02x, %02x, %02x, %02x (%#010x)\n",
2676 			b1, b2, b3, b4, val); */
2677 
2678 	dsi_write_reg(dsidev, DSI_VC_LONG_PACKET_PAYLOAD(channel), val);
2679 }
2680 
2681 static int dsi_vc_send_long(struct platform_device *dsidev, int channel,
2682 		u8 data_type, u8 *data, u16 len, u8 ecc)
2683 {
2684 	/*u32 val; */
2685 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2686 	int i;
2687 	u8 *p;
2688 	int r = 0;
2689 	u8 b1, b2, b3, b4;
2690 
2691 	if (dsi->debug_write)
2692 		DSSDBG("dsi_vc_send_long, %d bytes\n", len);
2693 
2694 	/* len + header */
2695 	if (dsi->vc[channel].tx_fifo_size * 32 * 4 < len + 4) {
2696 		DSSERR("unable to send long packet: packet too long.\n");
2697 		return -EINVAL;
2698 	}
2699 
2700 	dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_L4);
2701 
2702 	dsi_vc_write_long_header(dsidev, channel, data_type, len, ecc);
2703 
2704 	p = data;
2705 	for (i = 0; i < len >> 2; i++) {
2706 		if (dsi->debug_write)
2707 			DSSDBG("\tsending full packet %d\n", i);
2708 
2709 		b1 = *p++;
2710 		b2 = *p++;
2711 		b3 = *p++;
2712 		b4 = *p++;
2713 
2714 		dsi_vc_write_long_payload(dsidev, channel, b1, b2, b3, b4);
2715 	}
2716 
2717 	i = len % 4;
2718 	if (i) {
2719 		b1 = 0; b2 = 0; b3 = 0;
2720 
2721 		if (dsi->debug_write)
2722 			DSSDBG("\tsending remainder bytes %d\n", i);
2723 
2724 		switch (i) {
2725 		case 3:
2726 			b1 = *p++;
2727 			b2 = *p++;
2728 			b3 = *p++;
2729 			break;
2730 		case 2:
2731 			b1 = *p++;
2732 			b2 = *p++;
2733 			break;
2734 		case 1:
2735 			b1 = *p++;
2736 			break;
2737 		}
2738 
2739 		dsi_vc_write_long_payload(dsidev, channel, b1, b2, b3, 0);
2740 	}
2741 
2742 	return r;
2743 }
2744 
2745 static int dsi_vc_send_short(struct platform_device *dsidev, int channel,
2746 		u8 data_type, u16 data, u8 ecc)
2747 {
2748 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2749 	u32 r;
2750 	u8 data_id;
2751 
2752 	WARN_ON(!dsi_bus_is_locked(dsidev));
2753 
2754 	if (dsi->debug_write)
2755 		DSSDBG("dsi_vc_send_short(ch%d, dt %#x, b1 %#x, b2 %#x)\n",
2756 				channel,
2757 				data_type, data & 0xff, (data >> 8) & 0xff);
2758 
2759 	dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_L4);
2760 
2761 	if (FLD_GET(dsi_read_reg(dsidev, DSI_VC_CTRL(channel)), 16, 16)) {
2762 		DSSERR("ERROR FIFO FULL, aborting transfer\n");
2763 		return -EINVAL;
2764 	}
2765 
2766 	data_id = data_type | dsi->vc[channel].vc_id << 6;
2767 
2768 	r = (data_id << 0) | (data << 8) | (ecc << 24);
2769 
2770 	dsi_write_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel), r);
2771 
2772 	return 0;
2773 }
2774 
2775 static int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel)
2776 {
2777 	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2778 
2779 	return dsi_vc_send_long(dsidev, channel, MIPI_DSI_NULL_PACKET, NULL,
2780 		0, 0);
2781 }
2782 
2783 static int dsi_vc_write_nosync_common(struct platform_device *dsidev,
2784 		int channel, u8 *data, int len, enum dss_dsi_content_type type)
2785 {
2786 	int r;
2787 
2788 	if (len == 0) {
2789 		BUG_ON(type == DSS_DSI_CONTENT_DCS);
2790 		r = dsi_vc_send_short(dsidev, channel,
2791 				MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM, 0, 0);
2792 	} else if (len == 1) {
2793 		r = dsi_vc_send_short(dsidev, channel,
2794 				type == DSS_DSI_CONTENT_GENERIC ?
2795 				MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM :
2796 				MIPI_DSI_DCS_SHORT_WRITE, data[0], 0);
2797 	} else if (len == 2) {
2798 		r = dsi_vc_send_short(dsidev, channel,
2799 				type == DSS_DSI_CONTENT_GENERIC ?
2800 				MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM :
2801 				MIPI_DSI_DCS_SHORT_WRITE_PARAM,
2802 				data[0] | (data[1] << 8), 0);
2803 	} else {
2804 		r = dsi_vc_send_long(dsidev, channel,
2805 				type == DSS_DSI_CONTENT_GENERIC ?
2806 				MIPI_DSI_GENERIC_LONG_WRITE :
2807 				MIPI_DSI_DCS_LONG_WRITE, data, len, 0);
2808 	}
2809 
2810 	return r;
2811 }
2812 
2813 static int dsi_vc_dcs_write_nosync(struct omap_dss_device *dssdev, int channel,
2814 		u8 *data, int len)
2815 {
2816 	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2817 
2818 	return dsi_vc_write_nosync_common(dsidev, channel, data, len,
2819 			DSS_DSI_CONTENT_DCS);
2820 }
2821 
2822 static int dsi_vc_generic_write_nosync(struct omap_dss_device *dssdev, int channel,
2823 		u8 *data, int len)
2824 {
2825 	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2826 
2827 	return dsi_vc_write_nosync_common(dsidev, channel, data, len,
2828 			DSS_DSI_CONTENT_GENERIC);
2829 }
2830 
2831 static int dsi_vc_write_common(struct omap_dss_device *dssdev, int channel,
2832 		u8 *data, int len, enum dss_dsi_content_type type)
2833 {
2834 	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2835 	int r;
2836 
2837 	r = dsi_vc_write_nosync_common(dsidev, channel, data, len, type);
2838 	if (r)
2839 		goto err;
2840 
2841 	r = dsi_vc_send_bta_sync(dssdev, channel);
2842 	if (r)
2843 		goto err;
2844 
2845 	/* RX_FIFO_NOT_EMPTY */
2846 	if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
2847 		DSSERR("rx fifo not empty after write, dumping data:\n");
2848 		dsi_vc_flush_receive_data(dsidev, channel);
2849 		r = -EIO;
2850 		goto err;
2851 	}
2852 
2853 	return 0;
2854 err:
2855 	DSSERR("dsi_vc_write_common(ch %d, cmd 0x%02x, len %d) failed\n",
2856 			channel, data[0], len);
2857 	return r;
2858 }
2859 
2860 static int dsi_vc_dcs_write(struct omap_dss_device *dssdev, int channel, u8 *data,
2861 		int len)
2862 {
2863 	return dsi_vc_write_common(dssdev, channel, data, len,
2864 			DSS_DSI_CONTENT_DCS);
2865 }
2866 
2867 static int dsi_vc_generic_write(struct omap_dss_device *dssdev, int channel, u8 *data,
2868 		int len)
2869 {
2870 	return dsi_vc_write_common(dssdev, channel, data, len,
2871 			DSS_DSI_CONTENT_GENERIC);
2872 }
2873 
2874 static int dsi_vc_dcs_send_read_request(struct platform_device *dsidev,
2875 		int channel, u8 dcs_cmd)
2876 {
2877 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2878 	int r;
2879 
2880 	if (dsi->debug_read)
2881 		DSSDBG("dsi_vc_dcs_send_read_request(ch%d, dcs_cmd %x)\n",
2882 			channel, dcs_cmd);
2883 
2884 	r = dsi_vc_send_short(dsidev, channel, MIPI_DSI_DCS_READ, dcs_cmd, 0);
2885 	if (r) {
2886 		DSSERR("dsi_vc_dcs_send_read_request(ch %d, cmd 0x%02x)"
2887 			" failed\n", channel, dcs_cmd);
2888 		return r;
2889 	}
2890 
2891 	return 0;
2892 }
2893 
2894 static int dsi_vc_generic_send_read_request(struct platform_device *dsidev,
2895 		int channel, u8 *reqdata, int reqlen)
2896 {
2897 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2898 	u16 data;
2899 	u8 data_type;
2900 	int r;
2901 
2902 	if (dsi->debug_read)
2903 		DSSDBG("dsi_vc_generic_send_read_request(ch %d, reqlen %d)\n",
2904 			channel, reqlen);
2905 
2906 	if (reqlen == 0) {
2907 		data_type = MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM;
2908 		data = 0;
2909 	} else if (reqlen == 1) {
2910 		data_type = MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM;
2911 		data = reqdata[0];
2912 	} else if (reqlen == 2) {
2913 		data_type = MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM;
2914 		data = reqdata[0] | (reqdata[1] << 8);
2915 	} else {
2916 		BUG();
2917 		return -EINVAL;
2918 	}
2919 
2920 	r = dsi_vc_send_short(dsidev, channel, data_type, data, 0);
2921 	if (r) {
2922 		DSSERR("dsi_vc_generic_send_read_request(ch %d, reqlen %d)"
2923 			" failed\n", channel, reqlen);
2924 		return r;
2925 	}
2926 
2927 	return 0;
2928 }
2929 
2930 static int dsi_vc_read_rx_fifo(struct platform_device *dsidev, int channel,
2931 		u8 *buf, int buflen, enum dss_dsi_content_type type)
2932 {
2933 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2934 	u32 val;
2935 	u8 dt;
2936 	int r;
2937 
2938 	/* RX_FIFO_NOT_EMPTY */
2939 	if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20) == 0) {
2940 		DSSERR("RX fifo empty when trying to read.\n");
2941 		r = -EIO;
2942 		goto err;
2943 	}
2944 
2945 	val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));
2946 	if (dsi->debug_read)
2947 		DSSDBG("\theader: %08x\n", val);
2948 	dt = FLD_GET(val, 5, 0);
2949 	if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) {
2950 		u16 err = FLD_GET(val, 23, 8);
2951 		dsi_show_rx_ack_with_err(err);
2952 		r = -EIO;
2953 		goto err;
2954 
2955 	} else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
2956 			MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE :
2957 			MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE)) {
2958 		u8 data = FLD_GET(val, 15, 8);
2959 		if (dsi->debug_read)
2960 			DSSDBG("\t%s short response, 1 byte: %02x\n",
2961 				type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
2962 				"DCS", data);
2963 
2964 		if (buflen < 1) {
2965 			r = -EIO;
2966 			goto err;
2967 		}
2968 
2969 		buf[0] = data;
2970 
2971 		return 1;
2972 	} else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
2973 			MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE :
2974 			MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE)) {
2975 		u16 data = FLD_GET(val, 23, 8);
2976 		if (dsi->debug_read)
2977 			DSSDBG("\t%s short response, 2 byte: %04x\n",
2978 				type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
2979 				"DCS", data);
2980 
2981 		if (buflen < 2) {
2982 			r = -EIO;
2983 			goto err;
2984 		}
2985 
2986 		buf[0] = data & 0xff;
2987 		buf[1] = (data >> 8) & 0xff;
2988 
2989 		return 2;
2990 	} else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
2991 			MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE :
2992 			MIPI_DSI_RX_DCS_LONG_READ_RESPONSE)) {
2993 		int w;
2994 		int len = FLD_GET(val, 23, 8);
2995 		if (dsi->debug_read)
2996 			DSSDBG("\t%s long response, len %d\n",
2997 				type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
2998 				"DCS", len);
2999 
3000 		if (len > buflen) {
3001 			r = -EIO;
3002 			goto err;
3003 		}
3004 
3005 		/* two byte checksum ends the packet, not included in len */
3006 		for (w = 0; w < len + 2;) {
3007 			int b;
3008 			val = dsi_read_reg(dsidev,
3009 				DSI_VC_SHORT_PACKET_HEADER(channel));
3010 			if (dsi->debug_read)
3011 				DSSDBG("\t\t%02x %02x %02x %02x\n",
3012 						(val >> 0) & 0xff,
3013 						(val >> 8) & 0xff,
3014 						(val >> 16) & 0xff,
3015 						(val >> 24) & 0xff);
3016 
3017 			for (b = 0; b < 4; ++b) {
3018 				if (w < len)
3019 					buf[w] = (val >> (b * 8)) & 0xff;
3020 				/* we discard the 2 byte checksum */
3021 				++w;
3022 			}
3023 		}
3024 
3025 		return len;
3026 	} else {
3027 		DSSERR("\tunknown datatype 0x%02x\n", dt);
3028 		r = -EIO;
3029 		goto err;
3030 	}
3031 
3032 err:
3033 	DSSERR("dsi_vc_read_rx_fifo(ch %d type %s) failed\n", channel,
3034 		type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" : "DCS");
3035 
3036 	return r;
3037 }
3038 
3039 static int dsi_vc_dcs_read(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
3040 		u8 *buf, int buflen)
3041 {
3042 	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3043 	int r;
3044 
3045 	r = dsi_vc_dcs_send_read_request(dsidev, channel, dcs_cmd);
3046 	if (r)
3047 		goto err;
3048 
3049 	r = dsi_vc_send_bta_sync(dssdev, channel);
3050 	if (r)
3051 		goto err;
3052 
3053 	r = dsi_vc_read_rx_fifo(dsidev, channel, buf, buflen,
3054 		DSS_DSI_CONTENT_DCS);
3055 	if (r < 0)
3056 		goto err;
3057 
3058 	if (r != buflen) {
3059 		r = -EIO;
3060 		goto err;
3061 	}
3062 
3063 	return 0;
3064 err:
3065 	DSSERR("dsi_vc_dcs_read(ch %d, cmd 0x%02x) failed\n", channel, dcs_cmd);
3066 	return r;
3067 }
3068 
3069 static int dsi_vc_generic_read(struct omap_dss_device *dssdev, int channel,
3070 		u8 *reqdata, int reqlen, u8 *buf, int buflen)
3071 {
3072 	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3073 	int r;
3074 
3075 	r = dsi_vc_generic_send_read_request(dsidev, channel, reqdata, reqlen);
3076 	if (r)
3077 		return r;
3078 
3079 	r = dsi_vc_send_bta_sync(dssdev, channel);
3080 	if (r)
3081 		return r;
3082 
3083 	r = dsi_vc_read_rx_fifo(dsidev, channel, buf, buflen,
3084 		DSS_DSI_CONTENT_GENERIC);
3085 	if (r < 0)
3086 		return r;
3087 
3088 	if (r != buflen) {
3089 		r = -EIO;
3090 		return r;
3091 	}
3092 
3093 	return 0;
3094 }
3095 
3096 static int dsi_vc_set_max_rx_packet_size(struct omap_dss_device *dssdev, int channel,
3097 		u16 len)
3098 {
3099 	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3100 
3101 	return dsi_vc_send_short(dsidev, channel,
3102 			MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE, len, 0);
3103 }
3104 
3105 static int dsi_enter_ulps(struct platform_device *dsidev)
3106 {
3107 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3108 	DECLARE_COMPLETION_ONSTACK(completion);
3109 	int r, i;
3110 	unsigned mask;
3111 
3112 	DSSDBG("Entering ULPS");
3113 
3114 	WARN_ON(!dsi_bus_is_locked(dsidev));
3115 
3116 	WARN_ON(dsi->ulps_enabled);
3117 
3118 	if (dsi->ulps_enabled)
3119 		return 0;
3120 
3121 	/* DDR_CLK_ALWAYS_ON */
3122 	if (REG_GET(dsidev, DSI_CLK_CTRL, 13, 13)) {
3123 		dsi_if_enable(dsidev, 0);
3124 		REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 13, 13);
3125 		dsi_if_enable(dsidev, 1);
3126 	}
3127 
3128 	dsi_sync_vc(dsidev, 0);
3129 	dsi_sync_vc(dsidev, 1);
3130 	dsi_sync_vc(dsidev, 2);
3131 	dsi_sync_vc(dsidev, 3);
3132 
3133 	dsi_force_tx_stop_mode_io(dsidev);
3134 
3135 	dsi_vc_enable(dsidev, 0, false);
3136 	dsi_vc_enable(dsidev, 1, false);
3137 	dsi_vc_enable(dsidev, 2, false);
3138 	dsi_vc_enable(dsidev, 3, false);
3139 
3140 	if (REG_GET(dsidev, DSI_COMPLEXIO_CFG2, 16, 16)) {	/* HS_BUSY */
3141 		DSSERR("HS busy when enabling ULPS\n");
3142 		return -EIO;
3143 	}
3144 
3145 	if (REG_GET(dsidev, DSI_COMPLEXIO_CFG2, 17, 17)) {	/* LP_BUSY */
3146 		DSSERR("LP busy when enabling ULPS\n");
3147 		return -EIO;
3148 	}
3149 
3150 	r = dsi_register_isr_cio(dsidev, dsi_completion_handler, &completion,
3151 			DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
3152 	if (r)
3153 		return r;
3154 
3155 	mask = 0;
3156 
3157 	for (i = 0; i < dsi->num_lanes_supported; ++i) {
3158 		if (dsi->lanes[i].function == DSI_LANE_UNUSED)
3159 			continue;
3160 		mask |= 1 << i;
3161 	}
3162 	/* Assert TxRequestEsc for data lanes and TxUlpsClk for clk lane */
3163 	/* LANEx_ULPS_SIG2 */
3164 	REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG2, mask, 9, 5);
3165 
3166 	/* flush posted write and wait for SCP interface to finish the write */
3167 	dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG2);
3168 
3169 	if (wait_for_completion_timeout(&completion,
3170 				msecs_to_jiffies(1000)) == 0) {
3171 		DSSERR("ULPS enable timeout\n");
3172 		r = -EIO;
3173 		goto err;
3174 	}
3175 
3176 	dsi_unregister_isr_cio(dsidev, dsi_completion_handler, &completion,
3177 			DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
3178 
3179 	/* Reset LANEx_ULPS_SIG2 */
3180 	REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG2, 0, 9, 5);
3181 
3182 	/* flush posted write and wait for SCP interface to finish the write */
3183 	dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG2);
3184 
3185 	dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_ULPS);
3186 
3187 	dsi_if_enable(dsidev, false);
3188 
3189 	dsi->ulps_enabled = true;
3190 
3191 	return 0;
3192 
3193 err:
3194 	dsi_unregister_isr_cio(dsidev, dsi_completion_handler, &completion,
3195 			DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
3196 	return r;
3197 }
3198 
3199 static void dsi_set_lp_rx_timeout(struct platform_device *dsidev,
3200 		unsigned ticks, bool x4, bool x16)
3201 {
3202 	unsigned long fck;
3203 	unsigned long total_ticks;
3204 	u32 r;
3205 
3206 	BUG_ON(ticks > 0x1fff);
3207 
3208 	/* ticks in DSI_FCK */
3209 	fck = dsi_fclk_rate(dsidev);
3210 
3211 	r = dsi_read_reg(dsidev, DSI_TIMING2);
3212 	r = FLD_MOD(r, 1, 15, 15);	/* LP_RX_TO */
3213 	r = FLD_MOD(r, x16 ? 1 : 0, 14, 14);	/* LP_RX_TO_X16 */
3214 	r = FLD_MOD(r, x4 ? 1 : 0, 13, 13);	/* LP_RX_TO_X4 */
3215 	r = FLD_MOD(r, ticks, 12, 0);	/* LP_RX_COUNTER */
3216 	dsi_write_reg(dsidev, DSI_TIMING2, r);
3217 
3218 	total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
3219 
3220 	DSSDBG("LP_RX_TO %lu ticks (%#x%s%s) = %lu ns\n",
3221 			total_ticks,
3222 			ticks, x4 ? " x4" : "", x16 ? " x16" : "",
3223 			(total_ticks * 1000) / (fck / 1000 / 1000));
3224 }
3225 
3226 static void dsi_set_ta_timeout(struct platform_device *dsidev, unsigned ticks,
3227 		bool x8, bool x16)
3228 {
3229 	unsigned long fck;
3230 	unsigned long total_ticks;
3231 	u32 r;
3232 
3233 	BUG_ON(ticks > 0x1fff);
3234 
3235 	/* ticks in DSI_FCK */
3236 	fck = dsi_fclk_rate(dsidev);
3237 
3238 	r = dsi_read_reg(dsidev, DSI_TIMING1);
3239 	r = FLD_MOD(r, 1, 31, 31);	/* TA_TO */
3240 	r = FLD_MOD(r, x16 ? 1 : 0, 30, 30);	/* TA_TO_X16 */
3241 	r = FLD_MOD(r, x8 ? 1 : 0, 29, 29);	/* TA_TO_X8 */
3242 	r = FLD_MOD(r, ticks, 28, 16);	/* TA_TO_COUNTER */
3243 	dsi_write_reg(dsidev, DSI_TIMING1, r);
3244 
3245 	total_ticks = ticks * (x16 ? 16 : 1) * (x8 ? 8 : 1);
3246 
3247 	DSSDBG("TA_TO %lu ticks (%#x%s%s) = %lu ns\n",
3248 			total_ticks,
3249 			ticks, x8 ? " x8" : "", x16 ? " x16" : "",
3250 			(total_ticks * 1000) / (fck / 1000 / 1000));
3251 }
3252 
3253 static void dsi_set_stop_state_counter(struct platform_device *dsidev,
3254 		unsigned ticks, bool x4, bool x16)
3255 {
3256 	unsigned long fck;
3257 	unsigned long total_ticks;
3258 	u32 r;
3259 
3260 	BUG_ON(ticks > 0x1fff);
3261 
3262 	/* ticks in DSI_FCK */
3263 	fck = dsi_fclk_rate(dsidev);
3264 
3265 	r = dsi_read_reg(dsidev, DSI_TIMING1);
3266 	r = FLD_MOD(r, 1, 15, 15);	/* FORCE_TX_STOP_MODE_IO */
3267 	r = FLD_MOD(r, x16 ? 1 : 0, 14, 14);	/* STOP_STATE_X16_IO */
3268 	r = FLD_MOD(r, x4 ? 1 : 0, 13, 13);	/* STOP_STATE_X4_IO */
3269 	r = FLD_MOD(r, ticks, 12, 0);	/* STOP_STATE_COUNTER_IO */
3270 	dsi_write_reg(dsidev, DSI_TIMING1, r);
3271 
3272 	total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
3273 
3274 	DSSDBG("STOP_STATE_COUNTER %lu ticks (%#x%s%s) = %lu ns\n",
3275 			total_ticks,
3276 			ticks, x4 ? " x4" : "", x16 ? " x16" : "",
3277 			(total_ticks * 1000) / (fck / 1000 / 1000));
3278 }
3279 
3280 static void dsi_set_hs_tx_timeout(struct platform_device *dsidev,
3281 		unsigned ticks, bool x4, bool x16)
3282 {
3283 	unsigned long fck;
3284 	unsigned long total_ticks;
3285 	u32 r;
3286 
3287 	BUG_ON(ticks > 0x1fff);
3288 
3289 	/* ticks in TxByteClkHS */
3290 	fck = dsi_get_txbyteclkhs(dsidev);
3291 
3292 	r = dsi_read_reg(dsidev, DSI_TIMING2);
3293 	r = FLD_MOD(r, 1, 31, 31);	/* HS_TX_TO */
3294 	r = FLD_MOD(r, x16 ? 1 : 0, 30, 30);	/* HS_TX_TO_X16 */
3295 	r = FLD_MOD(r, x4 ? 1 : 0, 29, 29);	/* HS_TX_TO_X8 (4 really) */
3296 	r = FLD_MOD(r, ticks, 28, 16);	/* HS_TX_TO_COUNTER */
3297 	dsi_write_reg(dsidev, DSI_TIMING2, r);
3298 
3299 	total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
3300 
3301 	DSSDBG("HS_TX_TO %lu ticks (%#x%s%s) = %lu ns\n",
3302 			total_ticks,
3303 			ticks, x4 ? " x4" : "", x16 ? " x16" : "",
3304 			(total_ticks * 1000) / (fck / 1000 / 1000));
3305 }
3306 
3307 static void dsi_config_vp_num_line_buffers(struct platform_device *dsidev)
3308 {
3309 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3310 	int num_line_buffers;
3311 
3312 	if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
3313 		int bpp = dsi_get_pixel_size(dsi->pix_fmt);
3314 		struct omap_video_timings *timings = &dsi->timings;
3315 		/*
3316 		 * Don't use line buffers if width is greater than the video
3317 		 * port's line buffer size
3318 		 */
3319 		if (dsi->line_buffer_size <= timings->x_res * bpp / 8)
3320 			num_line_buffers = 0;
3321 		else
3322 			num_line_buffers = 2;
3323 	} else {
3324 		/* Use maximum number of line buffers in command mode */
3325 		num_line_buffers = 2;
3326 	}
3327 
3328 	/* LINE_BUFFER */
3329 	REG_FLD_MOD(dsidev, DSI_CTRL, num_line_buffers, 13, 12);
3330 }
3331 
3332 static void dsi_config_vp_sync_events(struct platform_device *dsidev)
3333 {
3334 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3335 	bool sync_end;
3336 	u32 r;
3337 
3338 	if (dsi->vm_timings.trans_mode == OMAP_DSS_DSI_PULSE_MODE)
3339 		sync_end = true;
3340 	else
3341 		sync_end = false;
3342 
3343 	r = dsi_read_reg(dsidev, DSI_CTRL);
3344 	r = FLD_MOD(r, 1, 9, 9);		/* VP_DE_POL */
3345 	r = FLD_MOD(r, 1, 10, 10);		/* VP_HSYNC_POL */
3346 	r = FLD_MOD(r, 1, 11, 11);		/* VP_VSYNC_POL */
3347 	r = FLD_MOD(r, 1, 15, 15);		/* VP_VSYNC_START */
3348 	r = FLD_MOD(r, sync_end, 16, 16);	/* VP_VSYNC_END */
3349 	r = FLD_MOD(r, 1, 17, 17);		/* VP_HSYNC_START */
3350 	r = FLD_MOD(r, sync_end, 18, 18);	/* VP_HSYNC_END */
3351 	dsi_write_reg(dsidev, DSI_CTRL, r);
3352 }
3353 
3354 static void dsi_config_blanking_modes(struct platform_device *dsidev)
3355 {
3356 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3357 	int blanking_mode = dsi->vm_timings.blanking_mode;
3358 	int hfp_blanking_mode = dsi->vm_timings.hfp_blanking_mode;
3359 	int hbp_blanking_mode = dsi->vm_timings.hbp_blanking_mode;
3360 	int hsa_blanking_mode = dsi->vm_timings.hsa_blanking_mode;
3361 	u32 r;
3362 
3363 	/*
3364 	 * 0 = TX FIFO packets sent or LPS in corresponding blanking periods
3365 	 * 1 = Long blanking packets are sent in corresponding blanking periods
3366 	 */
3367 	r = dsi_read_reg(dsidev, DSI_CTRL);
3368 	r = FLD_MOD(r, blanking_mode, 20, 20);		/* BLANKING_MODE */
3369 	r = FLD_MOD(r, hfp_blanking_mode, 21, 21);	/* HFP_BLANKING */
3370 	r = FLD_MOD(r, hbp_blanking_mode, 22, 22);	/* HBP_BLANKING */
3371 	r = FLD_MOD(r, hsa_blanking_mode, 23, 23);	/* HSA_BLANKING */
3372 	dsi_write_reg(dsidev, DSI_CTRL, r);
3373 }
3374 
3375 /*
3376  * According to section 'HS Command Mode Interleaving' in OMAP TRM, Scenario 3
3377  * results in maximum transition time for data and clock lanes to enter and
3378  * exit HS mode. Hence, this is the scenario where the least amount of command
3379  * mode data can be interleaved. We program the minimum amount of TXBYTECLKHS
3380  * clock cycles that can be used to interleave command mode data in HS so that
3381  * all scenarios are satisfied.
3382  */
3383 static int dsi_compute_interleave_hs(int blank, bool ddr_alwon, int enter_hs,
3384 		int exit_hs, int exiths_clk, int ddr_pre, int ddr_post)
3385 {
3386 	int transition;
3387 
3388 	/*
3389 	 * If DDR_CLK_ALWAYS_ON is set, we need to consider HS mode transition
3390 	 * time of data lanes only, if it isn't set, we need to consider HS
3391 	 * transition time of both data and clock lanes. HS transition time
3392 	 * of Scenario 3 is considered.
3393 	 */
3394 	if (ddr_alwon) {
3395 		transition = enter_hs + exit_hs + max(enter_hs, 2) + 1;
3396 	} else {
3397 		int trans1, trans2;
3398 		trans1 = ddr_pre + enter_hs + exit_hs + max(enter_hs, 2) + 1;
3399 		trans2 = ddr_pre + enter_hs + exiths_clk + ddr_post + ddr_pre +
3400 				enter_hs + 1;
3401 		transition = max(trans1, trans2);
3402 	}
3403 
3404 	return blank > transition ? blank - transition : 0;
3405 }
3406 
3407 /*
3408  * According to section 'LP Command Mode Interleaving' in OMAP TRM, Scenario 1
3409  * results in maximum transition time for data lanes to enter and exit LP mode.
3410  * Hence, this is the scenario where the least amount of command mode data can
3411  * be interleaved. We program the minimum amount of bytes that can be
3412  * interleaved in LP so that all scenarios are satisfied.
3413  */
3414 static int dsi_compute_interleave_lp(int blank, int enter_hs, int exit_hs,
3415 		int lp_clk_div, int tdsi_fclk)
3416 {
3417 	int trans_lp;	/* time required for a LP transition, in TXBYTECLKHS */
3418 	int tlp_avail;	/* time left for interleaving commands, in CLKIN4DDR */
3419 	int ttxclkesc;	/* period of LP transmit escape clock, in CLKIN4DDR */
3420 	int thsbyte_clk = 16;	/* Period of TXBYTECLKHS clock, in CLKIN4DDR */
3421 	int lp_inter;	/* cmd mode data that can be interleaved, in bytes */
3422 
3423 	/* maximum LP transition time according to Scenario 1 */
3424 	trans_lp = exit_hs + max(enter_hs, 2) + 1;
3425 
3426 	/* CLKIN4DDR = 16 * TXBYTECLKHS */
3427 	tlp_avail = thsbyte_clk * (blank - trans_lp);
3428 
3429 	ttxclkesc = tdsi_fclk * lp_clk_div;
3430 
3431 	lp_inter = ((tlp_avail - 8 * thsbyte_clk - 5 * tdsi_fclk) / ttxclkesc -
3432 			26) / 16;
3433 
3434 	return max(lp_inter, 0);
3435 }
3436 
3437 static void dsi_config_cmd_mode_interleaving(struct platform_device *dsidev)
3438 {
3439 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3440 	int blanking_mode;
3441 	int hfp_blanking_mode, hbp_blanking_mode, hsa_blanking_mode;
3442 	int hsa, hfp, hbp, width_bytes, bllp, lp_clk_div;
3443 	int ddr_clk_pre, ddr_clk_post, enter_hs_mode_lat, exit_hs_mode_lat;
3444 	int tclk_trail, ths_exit, exiths_clk;
3445 	bool ddr_alwon;
3446 	struct omap_video_timings *timings = &dsi->timings;
3447 	int bpp = dsi_get_pixel_size(dsi->pix_fmt);
3448 	int ndl = dsi->num_lanes_used - 1;
3449 	int dsi_fclk_hsdiv = dsi->user_dsi_cinfo.mX[HSDIV_DSI] + 1;
3450 	int hsa_interleave_hs = 0, hsa_interleave_lp = 0;
3451 	int hfp_interleave_hs = 0, hfp_interleave_lp = 0;
3452 	int hbp_interleave_hs = 0, hbp_interleave_lp = 0;
3453 	int bl_interleave_hs = 0, bl_interleave_lp = 0;
3454 	u32 r;
3455 
3456 	r = dsi_read_reg(dsidev, DSI_CTRL);
3457 	blanking_mode = FLD_GET(r, 20, 20);
3458 	hfp_blanking_mode = FLD_GET(r, 21, 21);
3459 	hbp_blanking_mode = FLD_GET(r, 22, 22);
3460 	hsa_blanking_mode = FLD_GET(r, 23, 23);
3461 
3462 	r = dsi_read_reg(dsidev, DSI_VM_TIMING1);
3463 	hbp = FLD_GET(r, 11, 0);
3464 	hfp = FLD_GET(r, 23, 12);
3465 	hsa = FLD_GET(r, 31, 24);
3466 
3467 	r = dsi_read_reg(dsidev, DSI_CLK_TIMING);
3468 	ddr_clk_post = FLD_GET(r, 7, 0);
3469 	ddr_clk_pre = FLD_GET(r, 15, 8);
3470 
3471 	r = dsi_read_reg(dsidev, DSI_VM_TIMING7);
3472 	exit_hs_mode_lat = FLD_GET(r, 15, 0);
3473 	enter_hs_mode_lat = FLD_GET(r, 31, 16);
3474 
3475 	r = dsi_read_reg(dsidev, DSI_CLK_CTRL);
3476 	lp_clk_div = FLD_GET(r, 12, 0);
3477 	ddr_alwon = FLD_GET(r, 13, 13);
3478 
3479 	r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0);
3480 	ths_exit = FLD_GET(r, 7, 0);
3481 
3482 	r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1);
3483 	tclk_trail = FLD_GET(r, 15, 8);
3484 
3485 	exiths_clk = ths_exit + tclk_trail;
3486 
3487 	width_bytes = DIV_ROUND_UP(timings->x_res * bpp, 8);
3488 	bllp = hbp + hfp + hsa + DIV_ROUND_UP(width_bytes + 6, ndl);
3489 
3490 	if (!hsa_blanking_mode) {
3491 		hsa_interleave_hs = dsi_compute_interleave_hs(hsa, ddr_alwon,
3492 					enter_hs_mode_lat, exit_hs_mode_lat,
3493 					exiths_clk, ddr_clk_pre, ddr_clk_post);
3494 		hsa_interleave_lp = dsi_compute_interleave_lp(hsa,
3495 					enter_hs_mode_lat, exit_hs_mode_lat,
3496 					lp_clk_div, dsi_fclk_hsdiv);
3497 	}
3498 
3499 	if (!hfp_blanking_mode) {
3500 		hfp_interleave_hs = dsi_compute_interleave_hs(hfp, ddr_alwon,
3501 					enter_hs_mode_lat, exit_hs_mode_lat,
3502 					exiths_clk, ddr_clk_pre, ddr_clk_post);
3503 		hfp_interleave_lp = dsi_compute_interleave_lp(hfp,
3504 					enter_hs_mode_lat, exit_hs_mode_lat,
3505 					lp_clk_div, dsi_fclk_hsdiv);
3506 	}
3507 
3508 	if (!hbp_blanking_mode) {
3509 		hbp_interleave_hs = dsi_compute_interleave_hs(hbp, ddr_alwon,
3510 					enter_hs_mode_lat, exit_hs_mode_lat,
3511 					exiths_clk, ddr_clk_pre, ddr_clk_post);
3512 
3513 		hbp_interleave_lp = dsi_compute_interleave_lp(hbp,
3514 					enter_hs_mode_lat, exit_hs_mode_lat,
3515 					lp_clk_div, dsi_fclk_hsdiv);
3516 	}
3517 
3518 	if (!blanking_mode) {
3519 		bl_interleave_hs = dsi_compute_interleave_hs(bllp, ddr_alwon,
3520 					enter_hs_mode_lat, exit_hs_mode_lat,
3521 					exiths_clk, ddr_clk_pre, ddr_clk_post);
3522 
3523 		bl_interleave_lp = dsi_compute_interleave_lp(bllp,
3524 					enter_hs_mode_lat, exit_hs_mode_lat,
3525 					lp_clk_div, dsi_fclk_hsdiv);
3526 	}
3527 
3528 	DSSDBG("DSI HS interleaving(TXBYTECLKHS) HSA %d, HFP %d, HBP %d, BLLP %d\n",
3529 		hsa_interleave_hs, hfp_interleave_hs, hbp_interleave_hs,
3530 		bl_interleave_hs);
3531 
3532 	DSSDBG("DSI LP interleaving(bytes) HSA %d, HFP %d, HBP %d, BLLP %d\n",
3533 		hsa_interleave_lp, hfp_interleave_lp, hbp_interleave_lp,
3534 		bl_interleave_lp);
3535 
3536 	r = dsi_read_reg(dsidev, DSI_VM_TIMING4);
3537 	r = FLD_MOD(r, hsa_interleave_hs, 23, 16);
3538 	r = FLD_MOD(r, hfp_interleave_hs, 15, 8);
3539 	r = FLD_MOD(r, hbp_interleave_hs, 7, 0);
3540 	dsi_write_reg(dsidev, DSI_VM_TIMING4, r);
3541 
3542 	r = dsi_read_reg(dsidev, DSI_VM_TIMING5);
3543 	r = FLD_MOD(r, hsa_interleave_lp, 23, 16);
3544 	r = FLD_MOD(r, hfp_interleave_lp, 15, 8);
3545 	r = FLD_MOD(r, hbp_interleave_lp, 7, 0);
3546 	dsi_write_reg(dsidev, DSI_VM_TIMING5, r);
3547 
3548 	r = dsi_read_reg(dsidev, DSI_VM_TIMING6);
3549 	r = FLD_MOD(r, bl_interleave_hs, 31, 15);
3550 	r = FLD_MOD(r, bl_interleave_lp, 16, 0);
3551 	dsi_write_reg(dsidev, DSI_VM_TIMING6, r);
3552 }
3553 
3554 static int dsi_proto_config(struct platform_device *dsidev)
3555 {
3556 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3557 	u32 r;
3558 	int buswidth = 0;
3559 
3560 	dsi_config_tx_fifo(dsidev, DSI_FIFO_SIZE_32,
3561 			DSI_FIFO_SIZE_32,
3562 			DSI_FIFO_SIZE_32,
3563 			DSI_FIFO_SIZE_32);
3564 
3565 	dsi_config_rx_fifo(dsidev, DSI_FIFO_SIZE_32,
3566 			DSI_FIFO_SIZE_32,
3567 			DSI_FIFO_SIZE_32,
3568 			DSI_FIFO_SIZE_32);
3569 
3570 	/* XXX what values for the timeouts? */
3571 	dsi_set_stop_state_counter(dsidev, 0x1000, false, false);
3572 	dsi_set_ta_timeout(dsidev, 0x1fff, true, true);
3573 	dsi_set_lp_rx_timeout(dsidev, 0x1fff, true, true);
3574 	dsi_set_hs_tx_timeout(dsidev, 0x1fff, true, true);
3575 
3576 	switch (dsi_get_pixel_size(dsi->pix_fmt)) {
3577 	case 16:
3578 		buswidth = 0;
3579 		break;
3580 	case 18:
3581 		buswidth = 1;
3582 		break;
3583 	case 24:
3584 		buswidth = 2;
3585 		break;
3586 	default:
3587 		BUG();
3588 		return -EINVAL;
3589 	}
3590 
3591 	r = dsi_read_reg(dsidev, DSI_CTRL);
3592 	r = FLD_MOD(r, 1, 1, 1);	/* CS_RX_EN */
3593 	r = FLD_MOD(r, 1, 2, 2);	/* ECC_RX_EN */
3594 	r = FLD_MOD(r, 1, 3, 3);	/* TX_FIFO_ARBITRATION */
3595 	r = FLD_MOD(r, 1, 4, 4);	/* VP_CLK_RATIO, always 1, see errata*/
3596 	r = FLD_MOD(r, buswidth, 7, 6); /* VP_DATA_BUS_WIDTH */
3597 	r = FLD_MOD(r, 0, 8, 8);	/* VP_CLK_POL */
3598 	r = FLD_MOD(r, 1, 14, 14);	/* TRIGGER_RESET_MODE */
3599 	r = FLD_MOD(r, 1, 19, 19);	/* EOT_ENABLE */
3600 	if (!dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC)) {
3601 		r = FLD_MOD(r, 1, 24, 24);	/* DCS_CMD_ENABLE */
3602 		/* DCS_CMD_CODE, 1=start, 0=continue */
3603 		r = FLD_MOD(r, 0, 25, 25);
3604 	}
3605 
3606 	dsi_write_reg(dsidev, DSI_CTRL, r);
3607 
3608 	dsi_config_vp_num_line_buffers(dsidev);
3609 
3610 	if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
3611 		dsi_config_vp_sync_events(dsidev);
3612 		dsi_config_blanking_modes(dsidev);
3613 		dsi_config_cmd_mode_interleaving(dsidev);
3614 	}
3615 
3616 	dsi_vc_initial_config(dsidev, 0);
3617 	dsi_vc_initial_config(dsidev, 1);
3618 	dsi_vc_initial_config(dsidev, 2);
3619 	dsi_vc_initial_config(dsidev, 3);
3620 
3621 	return 0;
3622 }
3623 
3624 static void dsi_proto_timings(struct platform_device *dsidev)
3625 {
3626 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3627 	unsigned tlpx, tclk_zero, tclk_prepare;
3628 	unsigned tclk_pre, tclk_post;
3629 	unsigned ths_prepare, ths_prepare_ths_zero, ths_zero;
3630 	unsigned ths_trail, ths_exit;
3631 	unsigned ddr_clk_pre, ddr_clk_post;
3632 	unsigned enter_hs_mode_lat, exit_hs_mode_lat;
3633 	unsigned ths_eot;
3634 	int ndl = dsi->num_lanes_used - 1;
3635 	u32 r;
3636 
3637 	r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0);
3638 	ths_prepare = FLD_GET(r, 31, 24);
3639 	ths_prepare_ths_zero = FLD_GET(r, 23, 16);
3640 	ths_zero = ths_prepare_ths_zero - ths_prepare;
3641 	ths_trail = FLD_GET(r, 15, 8);
3642 	ths_exit = FLD_GET(r, 7, 0);
3643 
3644 	r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1);
3645 	tlpx = FLD_GET(r, 20, 16) * 2;
3646 	tclk_zero = FLD_GET(r, 7, 0);
3647 
3648 	r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG2);
3649 	tclk_prepare = FLD_GET(r, 7, 0);
3650 
3651 	/* min 8*UI */
3652 	tclk_pre = 20;
3653 	/* min 60ns + 52*UI */
3654 	tclk_post = ns2ddr(dsidev, 60) + 26;
3655 
3656 	ths_eot = DIV_ROUND_UP(4, ndl);
3657 
3658 	ddr_clk_pre = DIV_ROUND_UP(tclk_pre + tlpx + tclk_zero + tclk_prepare,
3659 			4);
3660 	ddr_clk_post = DIV_ROUND_UP(tclk_post + ths_trail, 4) + ths_eot;
3661 
3662 	BUG_ON(ddr_clk_pre == 0 || ddr_clk_pre > 255);
3663 	BUG_ON(ddr_clk_post == 0 || ddr_clk_post > 255);
3664 
3665 	r = dsi_read_reg(dsidev, DSI_CLK_TIMING);
3666 	r = FLD_MOD(r, ddr_clk_pre, 15, 8);
3667 	r = FLD_MOD(r, ddr_clk_post, 7, 0);
3668 	dsi_write_reg(dsidev, DSI_CLK_TIMING, r);
3669 
3670 	DSSDBG("ddr_clk_pre %u, ddr_clk_post %u\n",
3671 			ddr_clk_pre,
3672 			ddr_clk_post);
3673 
3674 	enter_hs_mode_lat = 1 + DIV_ROUND_UP(tlpx, 4) +
3675 		DIV_ROUND_UP(ths_prepare, 4) +
3676 		DIV_ROUND_UP(ths_zero + 3, 4);
3677 
3678 	exit_hs_mode_lat = DIV_ROUND_UP(ths_trail + ths_exit, 4) + 1 + ths_eot;
3679 
3680 	r = FLD_VAL(enter_hs_mode_lat, 31, 16) |
3681 		FLD_VAL(exit_hs_mode_lat, 15, 0);
3682 	dsi_write_reg(dsidev, DSI_VM_TIMING7, r);
3683 
3684 	DSSDBG("enter_hs_mode_lat %u, exit_hs_mode_lat %u\n",
3685 			enter_hs_mode_lat, exit_hs_mode_lat);
3686 
3687 	 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
3688 		/* TODO: Implement a video mode check_timings function */
3689 		int hsa = dsi->vm_timings.hsa;
3690 		int hfp = dsi->vm_timings.hfp;
3691 		int hbp = dsi->vm_timings.hbp;
3692 		int vsa = dsi->vm_timings.vsa;
3693 		int vfp = dsi->vm_timings.vfp;
3694 		int vbp = dsi->vm_timings.vbp;
3695 		int window_sync = dsi->vm_timings.window_sync;
3696 		bool hsync_end;
3697 		struct omap_video_timings *timings = &dsi->timings;
3698 		int bpp = dsi_get_pixel_size(dsi->pix_fmt);
3699 		int tl, t_he, width_bytes;
3700 
3701 		hsync_end = dsi->vm_timings.trans_mode == OMAP_DSS_DSI_PULSE_MODE;
3702 		t_he = hsync_end ?
3703 			((hsa == 0 && ndl == 3) ? 1 : DIV_ROUND_UP(4, ndl)) : 0;
3704 
3705 		width_bytes = DIV_ROUND_UP(timings->x_res * bpp, 8);
3706 
3707 		/* TL = t_HS + HSA + t_HE + HFP + ceil((WC + 6) / NDL) + HBP */
3708 		tl = DIV_ROUND_UP(4, ndl) + (hsync_end ? hsa : 0) + t_he + hfp +
3709 			DIV_ROUND_UP(width_bytes + 6, ndl) + hbp;
3710 
3711 		DSSDBG("HBP: %d, HFP: %d, HSA: %d, TL: %d TXBYTECLKHS\n", hbp,
3712 			hfp, hsync_end ? hsa : 0, tl);
3713 		DSSDBG("VBP: %d, VFP: %d, VSA: %d, VACT: %d lines\n", vbp, vfp,
3714 			vsa, timings->y_res);
3715 
3716 		r = dsi_read_reg(dsidev, DSI_VM_TIMING1);
3717 		r = FLD_MOD(r, hbp, 11, 0);	/* HBP */
3718 		r = FLD_MOD(r, hfp, 23, 12);	/* HFP */
3719 		r = FLD_MOD(r, hsync_end ? hsa : 0, 31, 24);	/* HSA */
3720 		dsi_write_reg(dsidev, DSI_VM_TIMING1, r);
3721 
3722 		r = dsi_read_reg(dsidev, DSI_VM_TIMING2);
3723 		r = FLD_MOD(r, vbp, 7, 0);	/* VBP */
3724 		r = FLD_MOD(r, vfp, 15, 8);	/* VFP */
3725 		r = FLD_MOD(r, vsa, 23, 16);	/* VSA */
3726 		r = FLD_MOD(r, window_sync, 27, 24);	/* WINDOW_SYNC */
3727 		dsi_write_reg(dsidev, DSI_VM_TIMING2, r);
3728 
3729 		r = dsi_read_reg(dsidev, DSI_VM_TIMING3);
3730 		r = FLD_MOD(r, timings->y_res, 14, 0);	/* VACT */
3731 		r = FLD_MOD(r, tl, 31, 16);		/* TL */
3732 		dsi_write_reg(dsidev, DSI_VM_TIMING3, r);
3733 	}
3734 }
3735 
3736 static int dsi_configure_pins(struct omap_dss_device *dssdev,
3737 		const struct omap_dsi_pin_config *pin_cfg)
3738 {
3739 	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3740 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3741 	int num_pins;
3742 	const int *pins;
3743 	struct dsi_lane_config lanes[DSI_MAX_NR_LANES];
3744 	int num_lanes;
3745 	int i;
3746 
3747 	static const enum dsi_lane_function functions[] = {
3748 		DSI_LANE_CLK,
3749 		DSI_LANE_DATA1,
3750 		DSI_LANE_DATA2,
3751 		DSI_LANE_DATA3,
3752 		DSI_LANE_DATA4,
3753 	};
3754 
3755 	num_pins = pin_cfg->num_pins;
3756 	pins = pin_cfg->pins;
3757 
3758 	if (num_pins < 4 || num_pins > dsi->num_lanes_supported * 2
3759 			|| num_pins % 2 != 0)
3760 		return -EINVAL;
3761 
3762 	for (i = 0; i < DSI_MAX_NR_LANES; ++i)
3763 		lanes[i].function = DSI_LANE_UNUSED;
3764 
3765 	num_lanes = 0;
3766 
3767 	for (i = 0; i < num_pins; i += 2) {
3768 		u8 lane, pol;
3769 		int dx, dy;
3770 
3771 		dx = pins[i];
3772 		dy = pins[i + 1];
3773 
3774 		if (dx < 0 || dx >= dsi->num_lanes_supported * 2)
3775 			return -EINVAL;
3776 
3777 		if (dy < 0 || dy >= dsi->num_lanes_supported * 2)
3778 			return -EINVAL;
3779 
3780 		if (dx & 1) {
3781 			if (dy != dx - 1)
3782 				return -EINVAL;
3783 			pol = 1;
3784 		} else {
3785 			if (dy != dx + 1)
3786 				return -EINVAL;
3787 			pol = 0;
3788 		}
3789 
3790 		lane = dx / 2;
3791 
3792 		lanes[lane].function = functions[i / 2];
3793 		lanes[lane].polarity = pol;
3794 		num_lanes++;
3795 	}
3796 
3797 	memcpy(dsi->lanes, lanes, sizeof(dsi->lanes));
3798 	dsi->num_lanes_used = num_lanes;
3799 
3800 	return 0;
3801 }
3802 
3803 static int dsi_enable_video_output(struct omap_dss_device *dssdev, int channel)
3804 {
3805 	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3806 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3807 	struct omap_overlay_manager *mgr = dsi->output.manager;
3808 	int bpp = dsi_get_pixel_size(dsi->pix_fmt);
3809 	struct omap_dss_device *out = &dsi->output;
3810 	u8 data_type;
3811 	u16 word_count;
3812 	int r;
3813 
3814 	if (out->manager == NULL) {
3815 		DSSERR("failed to enable display: no output/manager\n");
3816 		return -ENODEV;
3817 	}
3818 
3819 	r = dsi_display_init_dispc(dsidev, mgr);
3820 	if (r)
3821 		goto err_init_dispc;
3822 
3823 	if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
3824 		switch (dsi->pix_fmt) {
3825 		case OMAP_DSS_DSI_FMT_RGB888:
3826 			data_type = MIPI_DSI_PACKED_PIXEL_STREAM_24;
3827 			break;
3828 		case OMAP_DSS_DSI_FMT_RGB666:
3829 			data_type = MIPI_DSI_PIXEL_STREAM_3BYTE_18;
3830 			break;
3831 		case OMAP_DSS_DSI_FMT_RGB666_PACKED:
3832 			data_type = MIPI_DSI_PACKED_PIXEL_STREAM_18;
3833 			break;
3834 		case OMAP_DSS_DSI_FMT_RGB565:
3835 			data_type = MIPI_DSI_PACKED_PIXEL_STREAM_16;
3836 			break;
3837 		default:
3838 			r = -EINVAL;
3839 			goto err_pix_fmt;
3840 		}
3841 
3842 		dsi_if_enable(dsidev, false);
3843 		dsi_vc_enable(dsidev, channel, false);
3844 
3845 		/* MODE, 1 = video mode */
3846 		REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 1, 4, 4);
3847 
3848 		word_count = DIV_ROUND_UP(dsi->timings.x_res * bpp, 8);
3849 
3850 		dsi_vc_write_long_header(dsidev, channel, data_type,
3851 				word_count, 0);
3852 
3853 		dsi_vc_enable(dsidev, channel, true);
3854 		dsi_if_enable(dsidev, true);
3855 	}
3856 
3857 	r = dss_mgr_enable(mgr);
3858 	if (r)
3859 		goto err_mgr_enable;
3860 
3861 	return 0;
3862 
3863 err_mgr_enable:
3864 	if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
3865 		dsi_if_enable(dsidev, false);
3866 		dsi_vc_enable(dsidev, channel, false);
3867 	}
3868 err_pix_fmt:
3869 	dsi_display_uninit_dispc(dsidev, mgr);
3870 err_init_dispc:
3871 	return r;
3872 }
3873 
3874 static void dsi_disable_video_output(struct omap_dss_device *dssdev, int channel)
3875 {
3876 	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3877 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3878 	struct omap_overlay_manager *mgr = dsi->output.manager;
3879 
3880 	if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
3881 		dsi_if_enable(dsidev, false);
3882 		dsi_vc_enable(dsidev, channel, false);
3883 
3884 		/* MODE, 0 = command mode */
3885 		REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 0, 4, 4);
3886 
3887 		dsi_vc_enable(dsidev, channel, true);
3888 		dsi_if_enable(dsidev, true);
3889 	}
3890 
3891 	dss_mgr_disable(mgr);
3892 
3893 	dsi_display_uninit_dispc(dsidev, mgr);
3894 }
3895 
3896 static void dsi_update_screen_dispc(struct platform_device *dsidev)
3897 {
3898 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3899 	struct omap_overlay_manager *mgr = dsi->output.manager;
3900 	unsigned bytespp;
3901 	unsigned bytespl;
3902 	unsigned bytespf;
3903 	unsigned total_len;
3904 	unsigned packet_payload;
3905 	unsigned packet_len;
3906 	u32 l;
3907 	int r;
3908 	const unsigned channel = dsi->update_channel;
3909 	const unsigned line_buf_size = dsi->line_buffer_size;
3910 	u16 w = dsi->timings.x_res;
3911 	u16 h = dsi->timings.y_res;
3912 
3913 	DSSDBG("dsi_update_screen_dispc(%dx%d)\n", w, h);
3914 
3915 	dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_VP);
3916 
3917 	bytespp	= dsi_get_pixel_size(dsi->pix_fmt) / 8;
3918 	bytespl = w * bytespp;
3919 	bytespf = bytespl * h;
3920 
3921 	/* NOTE: packet_payload has to be equal to N * bytespl, where N is
3922 	 * number of lines in a packet.  See errata about VP_CLK_RATIO */
3923 
3924 	if (bytespf < line_buf_size)
3925 		packet_payload = bytespf;
3926 	else
3927 		packet_payload = (line_buf_size) / bytespl * bytespl;
3928 
3929 	packet_len = packet_payload + 1;	/* 1 byte for DCS cmd */
3930 	total_len = (bytespf / packet_payload) * packet_len;
3931 
3932 	if (bytespf % packet_payload)
3933 		total_len += (bytespf % packet_payload) + 1;
3934 
3935 	l = FLD_VAL(total_len, 23, 0); /* TE_SIZE */
3936 	dsi_write_reg(dsidev, DSI_VC_TE(channel), l);
3937 
3938 	dsi_vc_write_long_header(dsidev, channel, MIPI_DSI_DCS_LONG_WRITE,
3939 		packet_len, 0);
3940 
3941 	if (dsi->te_enabled)
3942 		l = FLD_MOD(l, 1, 30, 30); /* TE_EN */
3943 	else
3944 		l = FLD_MOD(l, 1, 31, 31); /* TE_START */
3945 	dsi_write_reg(dsidev, DSI_VC_TE(channel), l);
3946 
3947 	/* We put SIDLEMODE to no-idle for the duration of the transfer,
3948 	 * because DSS interrupts are not capable of waking up the CPU and the
3949 	 * framedone interrupt could be delayed for quite a long time. I think
3950 	 * the same goes for any DSS interrupts, but for some reason I have not
3951 	 * seen the problem anywhere else than here.
3952 	 */
3953 	dispc_disable_sidle();
3954 
3955 	dsi_perf_mark_start(dsidev);
3956 
3957 	r = schedule_delayed_work(&dsi->framedone_timeout_work,
3958 		msecs_to_jiffies(250));
3959 	BUG_ON(r == 0);
3960 
3961 	dss_mgr_set_timings(mgr, &dsi->timings);
3962 
3963 	dss_mgr_start_update(mgr);
3964 
3965 	if (dsi->te_enabled) {
3966 		/* disable LP_RX_TO, so that we can receive TE.  Time to wait
3967 		 * for TE is longer than the timer allows */
3968 		REG_FLD_MOD(dsidev, DSI_TIMING2, 0, 15, 15); /* LP_RX_TO */
3969 
3970 		dsi_vc_send_bta(dsidev, channel);
3971 
3972 #ifdef DSI_CATCH_MISSING_TE
3973 		mod_timer(&dsi->te_timer, jiffies + msecs_to_jiffies(250));
3974 #endif
3975 	}
3976 }
3977 
3978 #ifdef DSI_CATCH_MISSING_TE
3979 static void dsi_te_timeout(struct timer_list *unused)
3980 {
3981 	DSSERR("TE not received for 250ms!\n");
3982 }
3983 #endif
3984 
3985 static void dsi_handle_framedone(struct platform_device *dsidev, int error)
3986 {
3987 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3988 
3989 	/* SIDLEMODE back to smart-idle */
3990 	dispc_enable_sidle();
3991 
3992 	if (dsi->te_enabled) {
3993 		/* enable LP_RX_TO again after the TE */
3994 		REG_FLD_MOD(dsidev, DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */
3995 	}
3996 
3997 	dsi->framedone_callback(error, dsi->framedone_data);
3998 
3999 	if (!error)
4000 		dsi_perf_show(dsidev, "DISPC");
4001 }
4002 
4003 static void dsi_framedone_timeout_work_callback(struct work_struct *work)
4004 {
4005 	struct dsi_data *dsi = container_of(work, struct dsi_data,
4006 			framedone_timeout_work.work);
4007 	/* XXX While extremely unlikely, we could get FRAMEDONE interrupt after
4008 	 * 250ms which would conflict with this timeout work. What should be
4009 	 * done is first cancel the transfer on the HW, and then cancel the
4010 	 * possibly scheduled framedone work. However, cancelling the transfer
4011 	 * on the HW is buggy, and would probably require resetting the whole
4012 	 * DSI */
4013 
4014 	DSSERR("Framedone not received for 250ms!\n");
4015 
4016 	dsi_handle_framedone(dsi->pdev, -ETIMEDOUT);
4017 }
4018 
4019 static void dsi_framedone_irq_callback(void *data)
4020 {
4021 	struct platform_device *dsidev = (struct platform_device *) data;
4022 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4023 
4024 	/* Note: We get FRAMEDONE when DISPC has finished sending pixels and
4025 	 * turns itself off. However, DSI still has the pixels in its buffers,
4026 	 * and is sending the data.
4027 	 */
4028 
4029 	cancel_delayed_work(&dsi->framedone_timeout_work);
4030 
4031 	dsi_handle_framedone(dsidev, 0);
4032 }
4033 
4034 static int dsi_update(struct omap_dss_device *dssdev, int channel,
4035 		void (*callback)(int, void *), void *data)
4036 {
4037 	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4038 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4039 
4040 	dsi_perf_mark_setup(dsidev);
4041 
4042 	dsi->update_channel = channel;
4043 
4044 	dsi->framedone_callback = callback;
4045 	dsi->framedone_data = data;
4046 
4047 #ifdef DSI_PERF_MEASURE
4048 	dsi->update_bytes = dsi->timings.x_res * dsi->timings.y_res *
4049 		dsi_get_pixel_size(dsi->pix_fmt) / 8;
4050 #endif
4051 	dsi_update_screen_dispc(dsidev);
4052 
4053 	return 0;
4054 }
4055 
4056 /* Display funcs */
4057 
4058 static int dsi_configure_dispc_clocks(struct platform_device *dsidev)
4059 {
4060 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4061 	struct dispc_clock_info dispc_cinfo;
4062 	int r;
4063 	unsigned long fck;
4064 
4065 	fck = dsi_get_pll_hsdiv_dispc_rate(dsidev);
4066 
4067 	dispc_cinfo.lck_div = dsi->user_dispc_cinfo.lck_div;
4068 	dispc_cinfo.pck_div = dsi->user_dispc_cinfo.pck_div;
4069 
4070 	r = dispc_calc_clock_rates(fck, &dispc_cinfo);
4071 	if (r) {
4072 		DSSERR("Failed to calc dispc clocks\n");
4073 		return r;
4074 	}
4075 
4076 	dsi->mgr_config.clock_info = dispc_cinfo;
4077 
4078 	return 0;
4079 }
4080 
4081 static int dsi_display_init_dispc(struct platform_device *dsidev,
4082 		struct omap_overlay_manager *mgr)
4083 {
4084 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4085 	int r;
4086 
4087 	dss_select_lcd_clk_source(mgr->id, dsi->module_id == 0 ?
4088 			OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC :
4089 			OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC);
4090 
4091 	if (dsi->mode == OMAP_DSS_DSI_CMD_MODE) {
4092 		r = dss_mgr_register_framedone_handler(mgr,
4093 				dsi_framedone_irq_callback, dsidev);
4094 		if (r) {
4095 			DSSERR("can't register FRAMEDONE handler\n");
4096 			goto err;
4097 		}
4098 
4099 		dsi->mgr_config.stallmode = true;
4100 		dsi->mgr_config.fifohandcheck = true;
4101 	} else {
4102 		dsi->mgr_config.stallmode = false;
4103 		dsi->mgr_config.fifohandcheck = false;
4104 	}
4105 
4106 	/*
4107 	 * override interlace, logic level and edge related parameters in
4108 	 * omap_video_timings with default values
4109 	 */
4110 	dsi->timings.interlace = false;
4111 	dsi->timings.hsync_level = OMAPDSS_SIG_ACTIVE_HIGH;
4112 	dsi->timings.vsync_level = OMAPDSS_SIG_ACTIVE_HIGH;
4113 	dsi->timings.data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE;
4114 	dsi->timings.de_level = OMAPDSS_SIG_ACTIVE_HIGH;
4115 	dsi->timings.sync_pclk_edge = OMAPDSS_DRIVE_SIG_FALLING_EDGE;
4116 
4117 	dss_mgr_set_timings(mgr, &dsi->timings);
4118 
4119 	r = dsi_configure_dispc_clocks(dsidev);
4120 	if (r)
4121 		goto err1;
4122 
4123 	dsi->mgr_config.io_pad_mode = DSS_IO_PAD_MODE_BYPASS;
4124 	dsi->mgr_config.video_port_width =
4125 			dsi_get_pixel_size(dsi->pix_fmt);
4126 	dsi->mgr_config.lcden_sig_polarity = 0;
4127 
4128 	dss_mgr_set_lcd_config(mgr, &dsi->mgr_config);
4129 
4130 	return 0;
4131 err1:
4132 	if (dsi->mode == OMAP_DSS_DSI_CMD_MODE)
4133 		dss_mgr_unregister_framedone_handler(mgr,
4134 				dsi_framedone_irq_callback, dsidev);
4135 err:
4136 	dss_select_lcd_clk_source(mgr->id, OMAP_DSS_CLK_SRC_FCK);
4137 	return r;
4138 }
4139 
4140 static void dsi_display_uninit_dispc(struct platform_device *dsidev,
4141 		struct omap_overlay_manager *mgr)
4142 {
4143 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4144 
4145 	if (dsi->mode == OMAP_DSS_DSI_CMD_MODE)
4146 		dss_mgr_unregister_framedone_handler(mgr,
4147 				dsi_framedone_irq_callback, dsidev);
4148 
4149 	dss_select_lcd_clk_source(mgr->id, OMAP_DSS_CLK_SRC_FCK);
4150 }
4151 
4152 static int dsi_configure_dsi_clocks(struct platform_device *dsidev)
4153 {
4154 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4155 	struct dss_pll_clock_info cinfo;
4156 	int r;
4157 
4158 	cinfo = dsi->user_dsi_cinfo;
4159 
4160 	r = dss_pll_set_config(&dsi->pll, &cinfo);
4161 	if (r) {
4162 		DSSERR("Failed to set dsi clocks\n");
4163 		return r;
4164 	}
4165 
4166 	return 0;
4167 }
4168 
4169 static int dsi_display_init_dsi(struct platform_device *dsidev)
4170 {
4171 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4172 	int r;
4173 
4174 	r = dss_pll_enable(&dsi->pll);
4175 	if (r)
4176 		goto err0;
4177 
4178 	r = dsi_configure_dsi_clocks(dsidev);
4179 	if (r)
4180 		goto err1;
4181 
4182 	dss_select_dsi_clk_source(dsi->module_id, dsi->module_id == 0 ?
4183 			OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI :
4184 			OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI);
4185 
4186 	DSSDBG("PLL OK\n");
4187 
4188 	r = dsi_cio_init(dsidev);
4189 	if (r)
4190 		goto err2;
4191 
4192 	_dsi_print_reset_status(dsidev);
4193 
4194 	dsi_proto_timings(dsidev);
4195 	dsi_set_lp_clk_divisor(dsidev);
4196 
4197 	if (1)
4198 		_dsi_print_reset_status(dsidev);
4199 
4200 	r = dsi_proto_config(dsidev);
4201 	if (r)
4202 		goto err3;
4203 
4204 	/* enable interface */
4205 	dsi_vc_enable(dsidev, 0, 1);
4206 	dsi_vc_enable(dsidev, 1, 1);
4207 	dsi_vc_enable(dsidev, 2, 1);
4208 	dsi_vc_enable(dsidev, 3, 1);
4209 	dsi_if_enable(dsidev, 1);
4210 	dsi_force_tx_stop_mode_io(dsidev);
4211 
4212 	return 0;
4213 err3:
4214 	dsi_cio_uninit(dsidev);
4215 err2:
4216 	dss_select_dsi_clk_source(dsi->module_id, OMAP_DSS_CLK_SRC_FCK);
4217 err1:
4218 	dss_pll_disable(&dsi->pll);
4219 err0:
4220 	return r;
4221 }
4222 
4223 static void dsi_display_uninit_dsi(struct platform_device *dsidev,
4224 		bool disconnect_lanes, bool enter_ulps)
4225 {
4226 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4227 
4228 	if (enter_ulps && !dsi->ulps_enabled)
4229 		dsi_enter_ulps(dsidev);
4230 
4231 	/* disable interface */
4232 	dsi_if_enable(dsidev, 0);
4233 	dsi_vc_enable(dsidev, 0, 0);
4234 	dsi_vc_enable(dsidev, 1, 0);
4235 	dsi_vc_enable(dsidev, 2, 0);
4236 	dsi_vc_enable(dsidev, 3, 0);
4237 
4238 	dss_select_dsi_clk_source(dsi->module_id, OMAP_DSS_CLK_SRC_FCK);
4239 	dsi_cio_uninit(dsidev);
4240 	dsi_pll_uninit(dsidev, disconnect_lanes);
4241 }
4242 
4243 static int dsi_display_enable(struct omap_dss_device *dssdev)
4244 {
4245 	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4246 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4247 	int r = 0;
4248 
4249 	DSSDBG("dsi_display_enable\n");
4250 
4251 	WARN_ON(!dsi_bus_is_locked(dsidev));
4252 
4253 	mutex_lock(&dsi->lock);
4254 
4255 	r = dsi_runtime_get(dsidev);
4256 	if (r)
4257 		goto err_get_dsi;
4258 
4259 	_dsi_initialize_irq(dsidev);
4260 
4261 	r = dsi_display_init_dsi(dsidev);
4262 	if (r)
4263 		goto err_init_dsi;
4264 
4265 	mutex_unlock(&dsi->lock);
4266 
4267 	return 0;
4268 
4269 err_init_dsi:
4270 	dsi_runtime_put(dsidev);
4271 err_get_dsi:
4272 	mutex_unlock(&dsi->lock);
4273 	DSSDBG("dsi_display_enable FAILED\n");
4274 	return r;
4275 }
4276 
4277 static void dsi_display_disable(struct omap_dss_device *dssdev,
4278 		bool disconnect_lanes, bool enter_ulps)
4279 {
4280 	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4281 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4282 
4283 	DSSDBG("dsi_display_disable\n");
4284 
4285 	WARN_ON(!dsi_bus_is_locked(dsidev));
4286 
4287 	mutex_lock(&dsi->lock);
4288 
4289 	dsi_sync_vc(dsidev, 0);
4290 	dsi_sync_vc(dsidev, 1);
4291 	dsi_sync_vc(dsidev, 2);
4292 	dsi_sync_vc(dsidev, 3);
4293 
4294 	dsi_display_uninit_dsi(dsidev, disconnect_lanes, enter_ulps);
4295 
4296 	dsi_runtime_put(dsidev);
4297 
4298 	mutex_unlock(&dsi->lock);
4299 }
4300 
4301 static int dsi_enable_te(struct omap_dss_device *dssdev, bool enable)
4302 {
4303 	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4304 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4305 
4306 	dsi->te_enabled = enable;
4307 	return 0;
4308 }
4309 
4310 #ifdef PRINT_VERBOSE_VM_TIMINGS
4311 static void print_dsi_vm(const char *str,
4312 		const struct omap_dss_dsi_videomode_timings *t)
4313 {
4314 	unsigned long byteclk = t->hsclk / 4;
4315 	int bl, wc, pps, tot;
4316 
4317 	wc = DIV_ROUND_UP(t->hact * t->bitspp, 8);
4318 	pps = DIV_ROUND_UP(wc + 6, t->ndl); /* pixel packet size */
4319 	bl = t->hss + t->hsa + t->hse + t->hbp + t->hfp;
4320 	tot = bl + pps;
4321 
4322 #define TO_DSI_T(x) ((u32)div64_u64((u64)x * 1000000000llu, byteclk))
4323 
4324 	pr_debug("%s bck %lu, %u/%u/%u/%u/%u/%u = %u+%u = %u, "
4325 			"%u/%u/%u/%u/%u/%u = %u + %u = %u\n",
4326 			str,
4327 			byteclk,
4328 			t->hss, t->hsa, t->hse, t->hbp, pps, t->hfp,
4329 			bl, pps, tot,
4330 			TO_DSI_T(t->hss),
4331 			TO_DSI_T(t->hsa),
4332 			TO_DSI_T(t->hse),
4333 			TO_DSI_T(t->hbp),
4334 			TO_DSI_T(pps),
4335 			TO_DSI_T(t->hfp),
4336 
4337 			TO_DSI_T(bl),
4338 			TO_DSI_T(pps),
4339 
4340 			TO_DSI_T(tot));
4341 #undef TO_DSI_T
4342 }
4343 
4344 static void print_dispc_vm(const char *str, const struct omap_video_timings *t)
4345 {
4346 	unsigned long pck = t->pixelclock;
4347 	int hact, bl, tot;
4348 
4349 	hact = t->x_res;
4350 	bl = t->hsw + t->hbp + t->hfp;
4351 	tot = hact + bl;
4352 
4353 #define TO_DISPC_T(x) ((u32)div64_u64((u64)x * 1000000000llu, pck))
4354 
4355 	pr_debug("%s pck %lu, %u/%u/%u/%u = %u+%u = %u, "
4356 			"%u/%u/%u/%u = %u + %u = %u\n",
4357 			str,
4358 			pck,
4359 			t->hsw, t->hbp, hact, t->hfp,
4360 			bl, hact, tot,
4361 			TO_DISPC_T(t->hsw),
4362 			TO_DISPC_T(t->hbp),
4363 			TO_DISPC_T(hact),
4364 			TO_DISPC_T(t->hfp),
4365 			TO_DISPC_T(bl),
4366 			TO_DISPC_T(hact),
4367 			TO_DISPC_T(tot));
4368 #undef TO_DISPC_T
4369 }
4370 
4371 /* note: this is not quite accurate */
4372 static void print_dsi_dispc_vm(const char *str,
4373 		const struct omap_dss_dsi_videomode_timings *t)
4374 {
4375 	struct omap_video_timings vm = { 0 };
4376 	unsigned long byteclk = t->hsclk / 4;
4377 	unsigned long pck;
4378 	u64 dsi_tput;
4379 	int dsi_hact, dsi_htot;
4380 
4381 	dsi_tput = (u64)byteclk * t->ndl * 8;
4382 	pck = (u32)div64_u64(dsi_tput, t->bitspp);
4383 	dsi_hact = DIV_ROUND_UP(DIV_ROUND_UP(t->hact * t->bitspp, 8) + 6, t->ndl);
4384 	dsi_htot = t->hss + t->hsa + t->hse + t->hbp + dsi_hact + t->hfp;
4385 
4386 	vm.pixelclock = pck;
4387 	vm.hsw = div64_u64((u64)(t->hsa + t->hse) * pck, byteclk);
4388 	vm.hbp = div64_u64((u64)t->hbp * pck, byteclk);
4389 	vm.hfp = div64_u64((u64)t->hfp * pck, byteclk);
4390 	vm.x_res = t->hact;
4391 
4392 	print_dispc_vm(str, &vm);
4393 }
4394 #endif /* PRINT_VERBOSE_VM_TIMINGS */
4395 
4396 static bool dsi_cm_calc_dispc_cb(int lckd, int pckd, unsigned long lck,
4397 		unsigned long pck, void *data)
4398 {
4399 	struct dsi_clk_calc_ctx *ctx = data;
4400 	struct omap_video_timings *t = &ctx->dispc_vm;
4401 
4402 	ctx->dispc_cinfo.lck_div = lckd;
4403 	ctx->dispc_cinfo.pck_div = pckd;
4404 	ctx->dispc_cinfo.lck = lck;
4405 	ctx->dispc_cinfo.pck = pck;
4406 
4407 	*t = *ctx->config->timings;
4408 	t->pixelclock = pck;
4409 	t->x_res = ctx->config->timings->x_res;
4410 	t->y_res = ctx->config->timings->y_res;
4411 	t->hsw = t->hfp = t->hbp = t->vsw = 1;
4412 	t->vfp = t->vbp = 0;
4413 
4414 	return true;
4415 }
4416 
4417 static bool dsi_cm_calc_hsdiv_cb(int m_dispc, unsigned long dispc,
4418 		void *data)
4419 {
4420 	struct dsi_clk_calc_ctx *ctx = data;
4421 
4422 	ctx->dsi_cinfo.mX[HSDIV_DISPC] = m_dispc;
4423 	ctx->dsi_cinfo.clkout[HSDIV_DISPC] = dispc;
4424 
4425 	return dispc_div_calc(dispc, ctx->req_pck_min, ctx->req_pck_max,
4426 			dsi_cm_calc_dispc_cb, ctx);
4427 }
4428 
4429 static bool dsi_cm_calc_pll_cb(int n, int m, unsigned long fint,
4430 		unsigned long clkdco, void *data)
4431 {
4432 	struct dsi_clk_calc_ctx *ctx = data;
4433 
4434 	ctx->dsi_cinfo.n = n;
4435 	ctx->dsi_cinfo.m = m;
4436 	ctx->dsi_cinfo.fint = fint;
4437 	ctx->dsi_cinfo.clkdco = clkdco;
4438 
4439 	return dss_pll_hsdiv_calc(ctx->pll, clkdco, ctx->req_pck_min,
4440 			dss_feat_get_param_max(FEAT_PARAM_DSS_FCK),
4441 			dsi_cm_calc_hsdiv_cb, ctx);
4442 }
4443 
4444 static bool dsi_cm_calc(struct dsi_data *dsi,
4445 		const struct omap_dss_dsi_config *cfg,
4446 		struct dsi_clk_calc_ctx *ctx)
4447 {
4448 	unsigned long clkin;
4449 	int bitspp, ndl;
4450 	unsigned long pll_min, pll_max;
4451 	unsigned long pck, txbyteclk;
4452 
4453 	clkin = clk_get_rate(dsi->pll.clkin);
4454 	bitspp = dsi_get_pixel_size(cfg->pixel_format);
4455 	ndl = dsi->num_lanes_used - 1;
4456 
4457 	/*
4458 	 * Here we should calculate minimum txbyteclk to be able to send the
4459 	 * frame in time, and also to handle TE. That's not very simple, though,
4460 	 * especially as we go to LP between each pixel packet due to HW
4461 	 * "feature". So let's just estimate very roughly and multiply by 1.5.
4462 	 */
4463 	pck = cfg->timings->pixelclock;
4464 	pck = pck * 3 / 2;
4465 	txbyteclk = pck * bitspp / 8 / ndl;
4466 
4467 	memset(ctx, 0, sizeof(*ctx));
4468 	ctx->dsidev = dsi->pdev;
4469 	ctx->pll = &dsi->pll;
4470 	ctx->config = cfg;
4471 	ctx->req_pck_min = pck;
4472 	ctx->req_pck_nom = pck;
4473 	ctx->req_pck_max = pck * 3 / 2;
4474 
4475 	pll_min = max(cfg->hs_clk_min * 4, txbyteclk * 4 * 4);
4476 	pll_max = cfg->hs_clk_max * 4;
4477 
4478 	return dss_pll_calc(ctx->pll, clkin,
4479 			pll_min, pll_max,
4480 			dsi_cm_calc_pll_cb, ctx);
4481 }
4482 
4483 static bool dsi_vm_calc_blanking(struct dsi_clk_calc_ctx *ctx)
4484 {
4485 	struct dsi_data *dsi = dsi_get_dsidrv_data(ctx->dsidev);
4486 	const struct omap_dss_dsi_config *cfg = ctx->config;
4487 	int bitspp = dsi_get_pixel_size(cfg->pixel_format);
4488 	int ndl = dsi->num_lanes_used - 1;
4489 	unsigned long hsclk = ctx->dsi_cinfo.clkdco / 4;
4490 	unsigned long byteclk = hsclk / 4;
4491 
4492 	unsigned long dispc_pck, req_pck_min, req_pck_nom, req_pck_max;
4493 	int xres;
4494 	int panel_htot, panel_hbl; /* pixels */
4495 	int dispc_htot, dispc_hbl; /* pixels */
4496 	int dsi_htot, dsi_hact, dsi_hbl, hss, hse; /* byteclks */
4497 	int hfp, hsa, hbp;
4498 	const struct omap_video_timings *req_vm;
4499 	struct omap_video_timings *dispc_vm;
4500 	struct omap_dss_dsi_videomode_timings *dsi_vm;
4501 	u64 dsi_tput, dispc_tput;
4502 
4503 	dsi_tput = (u64)byteclk * ndl * 8;
4504 
4505 	req_vm = cfg->timings;
4506 	req_pck_min = ctx->req_pck_min;
4507 	req_pck_max = ctx->req_pck_max;
4508 	req_pck_nom = ctx->req_pck_nom;
4509 
4510 	dispc_pck = ctx->dispc_cinfo.pck;
4511 	dispc_tput = (u64)dispc_pck * bitspp;
4512 
4513 	xres = req_vm->x_res;
4514 
4515 	panel_hbl = req_vm->hfp + req_vm->hbp + req_vm->hsw;
4516 	panel_htot = xres + panel_hbl;
4517 
4518 	dsi_hact = DIV_ROUND_UP(DIV_ROUND_UP(xres * bitspp, 8) + 6, ndl);
4519 
4520 	/*
4521 	 * When there are no line buffers, DISPC and DSI must have the
4522 	 * same tput. Otherwise DISPC tput needs to be higher than DSI's.
4523 	 */
4524 	if (dsi->line_buffer_size < xres * bitspp / 8) {
4525 		if (dispc_tput != dsi_tput)
4526 			return false;
4527 	} else {
4528 		if (dispc_tput < dsi_tput)
4529 			return false;
4530 	}
4531 
4532 	/* DSI tput must be over the min requirement */
4533 	if (dsi_tput < (u64)bitspp * req_pck_min)
4534 		return false;
4535 
4536 	/* When non-burst mode, DSI tput must be below max requirement. */
4537 	if (cfg->trans_mode != OMAP_DSS_DSI_BURST_MODE) {
4538 		if (dsi_tput > (u64)bitspp * req_pck_max)
4539 			return false;
4540 	}
4541 
4542 	hss = DIV_ROUND_UP(4, ndl);
4543 
4544 	if (cfg->trans_mode == OMAP_DSS_DSI_PULSE_MODE) {
4545 		if (ndl == 3 && req_vm->hsw == 0)
4546 			hse = 1;
4547 		else
4548 			hse = DIV_ROUND_UP(4, ndl);
4549 	} else {
4550 		hse = 0;
4551 	}
4552 
4553 	/* DSI htot to match the panel's nominal pck */
4554 	dsi_htot = div64_u64((u64)panel_htot * byteclk, req_pck_nom);
4555 
4556 	/* fail if there would be no time for blanking */
4557 	if (dsi_htot < hss + hse + dsi_hact)
4558 		return false;
4559 
4560 	/* total DSI blanking needed to achieve panel's TL */
4561 	dsi_hbl = dsi_htot - dsi_hact;
4562 
4563 	/* DISPC htot to match the DSI TL */
4564 	dispc_htot = div64_u64((u64)dsi_htot * dispc_pck, byteclk);
4565 
4566 	/* verify that the DSI and DISPC TLs are the same */
4567 	if ((u64)dsi_htot * dispc_pck != (u64)dispc_htot * byteclk)
4568 		return false;
4569 
4570 	dispc_hbl = dispc_htot - xres;
4571 
4572 	/* setup DSI videomode */
4573 
4574 	dsi_vm = &ctx->dsi_vm;
4575 	memset(dsi_vm, 0, sizeof(*dsi_vm));
4576 
4577 	dsi_vm->hsclk = hsclk;
4578 
4579 	dsi_vm->ndl = ndl;
4580 	dsi_vm->bitspp = bitspp;
4581 
4582 	if (cfg->trans_mode != OMAP_DSS_DSI_PULSE_MODE) {
4583 		hsa = 0;
4584 	} else if (ndl == 3 && req_vm->hsw == 0) {
4585 		hsa = 0;
4586 	} else {
4587 		hsa = div64_u64((u64)req_vm->hsw * byteclk, req_pck_nom);
4588 		hsa = max(hsa - hse, 1);
4589 	}
4590 
4591 	hbp = div64_u64((u64)req_vm->hbp * byteclk, req_pck_nom);
4592 	hbp = max(hbp, 1);
4593 
4594 	hfp = dsi_hbl - (hss + hsa + hse + hbp);
4595 	if (hfp < 1) {
4596 		int t;
4597 		/* we need to take cycles from hbp */
4598 
4599 		t = 1 - hfp;
4600 		hbp = max(hbp - t, 1);
4601 		hfp = dsi_hbl - (hss + hsa + hse + hbp);
4602 
4603 		if (hfp < 1 && hsa > 0) {
4604 			/* we need to take cycles from hsa */
4605 			t = 1 - hfp;
4606 			hsa = max(hsa - t, 1);
4607 			hfp = dsi_hbl - (hss + hsa + hse + hbp);
4608 		}
4609 	}
4610 
4611 	if (hfp < 1)
4612 		return false;
4613 
4614 	dsi_vm->hss = hss;
4615 	dsi_vm->hsa = hsa;
4616 	dsi_vm->hse = hse;
4617 	dsi_vm->hbp = hbp;
4618 	dsi_vm->hact = xres;
4619 	dsi_vm->hfp = hfp;
4620 
4621 	dsi_vm->vsa = req_vm->vsw;
4622 	dsi_vm->vbp = req_vm->vbp;
4623 	dsi_vm->vact = req_vm->y_res;
4624 	dsi_vm->vfp = req_vm->vfp;
4625 
4626 	dsi_vm->trans_mode = cfg->trans_mode;
4627 
4628 	dsi_vm->blanking_mode = 0;
4629 	dsi_vm->hsa_blanking_mode = 1;
4630 	dsi_vm->hfp_blanking_mode = 1;
4631 	dsi_vm->hbp_blanking_mode = 1;
4632 
4633 	dsi_vm->ddr_clk_always_on = cfg->ddr_clk_always_on;
4634 	dsi_vm->window_sync = 4;
4635 
4636 	/* setup DISPC videomode */
4637 
4638 	dispc_vm = &ctx->dispc_vm;
4639 	*dispc_vm = *req_vm;
4640 	dispc_vm->pixelclock = dispc_pck;
4641 
4642 	if (cfg->trans_mode == OMAP_DSS_DSI_PULSE_MODE) {
4643 		hsa = div64_u64((u64)req_vm->hsw * dispc_pck,
4644 				req_pck_nom);
4645 		hsa = max(hsa, 1);
4646 	} else {
4647 		hsa = 1;
4648 	}
4649 
4650 	hbp = div64_u64((u64)req_vm->hbp * dispc_pck, req_pck_nom);
4651 	hbp = max(hbp, 1);
4652 
4653 	hfp = dispc_hbl - hsa - hbp;
4654 	if (hfp < 1) {
4655 		int t;
4656 		/* we need to take cycles from hbp */
4657 
4658 		t = 1 - hfp;
4659 		hbp = max(hbp - t, 1);
4660 		hfp = dispc_hbl - hsa - hbp;
4661 
4662 		if (hfp < 1) {
4663 			/* we need to take cycles from hsa */
4664 			t = 1 - hfp;
4665 			hsa = max(hsa - t, 1);
4666 			hfp = dispc_hbl - hsa - hbp;
4667 		}
4668 	}
4669 
4670 	if (hfp < 1)
4671 		return false;
4672 
4673 	dispc_vm->hfp = hfp;
4674 	dispc_vm->hsw = hsa;
4675 	dispc_vm->hbp = hbp;
4676 
4677 	return true;
4678 }
4679 
4680 
4681 static bool dsi_vm_calc_dispc_cb(int lckd, int pckd, unsigned long lck,
4682 		unsigned long pck, void *data)
4683 {
4684 	struct dsi_clk_calc_ctx *ctx = data;
4685 
4686 	ctx->dispc_cinfo.lck_div = lckd;
4687 	ctx->dispc_cinfo.pck_div = pckd;
4688 	ctx->dispc_cinfo.lck = lck;
4689 	ctx->dispc_cinfo.pck = pck;
4690 
4691 	if (dsi_vm_calc_blanking(ctx) == false)
4692 		return false;
4693 
4694 #ifdef PRINT_VERBOSE_VM_TIMINGS
4695 	print_dispc_vm("dispc", &ctx->dispc_vm);
4696 	print_dsi_vm("dsi  ", &ctx->dsi_vm);
4697 	print_dispc_vm("req  ", ctx->config->timings);
4698 	print_dsi_dispc_vm("act  ", &ctx->dsi_vm);
4699 #endif
4700 
4701 	return true;
4702 }
4703 
4704 static bool dsi_vm_calc_hsdiv_cb(int m_dispc, unsigned long dispc,
4705 		void *data)
4706 {
4707 	struct dsi_clk_calc_ctx *ctx = data;
4708 	unsigned long pck_max;
4709 
4710 	ctx->dsi_cinfo.mX[HSDIV_DISPC] = m_dispc;
4711 	ctx->dsi_cinfo.clkout[HSDIV_DISPC] = dispc;
4712 
4713 	/*
4714 	 * In burst mode we can let the dispc pck be arbitrarily high, but it
4715 	 * limits our scaling abilities. So for now, don't aim too high.
4716 	 */
4717 
4718 	if (ctx->config->trans_mode == OMAP_DSS_DSI_BURST_MODE)
4719 		pck_max = ctx->req_pck_max + 10000000;
4720 	else
4721 		pck_max = ctx->req_pck_max;
4722 
4723 	return dispc_div_calc(dispc, ctx->req_pck_min, pck_max,
4724 			dsi_vm_calc_dispc_cb, ctx);
4725 }
4726 
4727 static bool dsi_vm_calc_pll_cb(int n, int m, unsigned long fint,
4728 		unsigned long clkdco, void *data)
4729 {
4730 	struct dsi_clk_calc_ctx *ctx = data;
4731 
4732 	ctx->dsi_cinfo.n = n;
4733 	ctx->dsi_cinfo.m = m;
4734 	ctx->dsi_cinfo.fint = fint;
4735 	ctx->dsi_cinfo.clkdco = clkdco;
4736 
4737 	return dss_pll_hsdiv_calc(ctx->pll, clkdco, ctx->req_pck_min,
4738 			dss_feat_get_param_max(FEAT_PARAM_DSS_FCK),
4739 			dsi_vm_calc_hsdiv_cb, ctx);
4740 }
4741 
4742 static bool dsi_vm_calc(struct dsi_data *dsi,
4743 		const struct omap_dss_dsi_config *cfg,
4744 		struct dsi_clk_calc_ctx *ctx)
4745 {
4746 	const struct omap_video_timings *t = cfg->timings;
4747 	unsigned long clkin;
4748 	unsigned long pll_min;
4749 	unsigned long pll_max;
4750 	int ndl = dsi->num_lanes_used - 1;
4751 	int bitspp = dsi_get_pixel_size(cfg->pixel_format);
4752 	unsigned long byteclk_min;
4753 
4754 	clkin = clk_get_rate(dsi->pll.clkin);
4755 
4756 	memset(ctx, 0, sizeof(*ctx));
4757 	ctx->dsidev = dsi->pdev;
4758 	ctx->pll = &dsi->pll;
4759 	ctx->config = cfg;
4760 
4761 	/* these limits should come from the panel driver */
4762 	ctx->req_pck_min = t->pixelclock - 1000;
4763 	ctx->req_pck_nom = t->pixelclock;
4764 	ctx->req_pck_max = t->pixelclock + 1000;
4765 
4766 	byteclk_min = div64_u64((u64)ctx->req_pck_min * bitspp, ndl * 8);
4767 	pll_min = max(cfg->hs_clk_min * 4, byteclk_min * 4 * 4);
4768 
4769 	if (cfg->trans_mode == OMAP_DSS_DSI_BURST_MODE) {
4770 		pll_max = cfg->hs_clk_max * 4;
4771 	} else {
4772 		unsigned long byteclk_max;
4773 		byteclk_max = div64_u64((u64)ctx->req_pck_max * bitspp,
4774 				ndl * 8);
4775 
4776 		pll_max = byteclk_max * 4 * 4;
4777 	}
4778 
4779 	return dss_pll_calc(ctx->pll, clkin,
4780 			pll_min, pll_max,
4781 			dsi_vm_calc_pll_cb, ctx);
4782 }
4783 
4784 static int dsi_set_config(struct omap_dss_device *dssdev,
4785 		const struct omap_dss_dsi_config *config)
4786 {
4787 	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4788 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4789 	struct dsi_clk_calc_ctx ctx;
4790 	bool ok;
4791 	int r;
4792 
4793 	mutex_lock(&dsi->lock);
4794 
4795 	dsi->pix_fmt = config->pixel_format;
4796 	dsi->mode = config->mode;
4797 
4798 	if (config->mode == OMAP_DSS_DSI_VIDEO_MODE)
4799 		ok = dsi_vm_calc(dsi, config, &ctx);
4800 	else
4801 		ok = dsi_cm_calc(dsi, config, &ctx);
4802 
4803 	if (!ok) {
4804 		DSSERR("failed to find suitable DSI clock settings\n");
4805 		r = -EINVAL;
4806 		goto err;
4807 	}
4808 
4809 	dsi_pll_calc_dsi_fck(&ctx.dsi_cinfo);
4810 
4811 	r = dsi_lp_clock_calc(ctx.dsi_cinfo.clkout[HSDIV_DSI],
4812 		config->lp_clk_min, config->lp_clk_max, &dsi->user_lp_cinfo);
4813 	if (r) {
4814 		DSSERR("failed to find suitable DSI LP clock settings\n");
4815 		goto err;
4816 	}
4817 
4818 	dsi->user_dsi_cinfo = ctx.dsi_cinfo;
4819 	dsi->user_dispc_cinfo = ctx.dispc_cinfo;
4820 
4821 	dsi->timings = ctx.dispc_vm;
4822 	dsi->vm_timings = ctx.dsi_vm;
4823 
4824 	mutex_unlock(&dsi->lock);
4825 
4826 	return 0;
4827 err:
4828 	mutex_unlock(&dsi->lock);
4829 
4830 	return r;
4831 }
4832 
4833 /*
4834  * Return a hardcoded channel for the DSI output. This should work for
4835  * current use cases, but this can be later expanded to either resolve
4836  * the channel in some more dynamic manner, or get the channel as a user
4837  * parameter.
4838  */
4839 static enum omap_channel dsi_get_channel(int module_id)
4840 {
4841 	switch (omapdss_get_version()) {
4842 	case OMAPDSS_VER_OMAP24xx:
4843 	case OMAPDSS_VER_AM43xx:
4844 		DSSWARN("DSI not supported\n");
4845 		return OMAP_DSS_CHANNEL_LCD;
4846 
4847 	case OMAPDSS_VER_OMAP34xx_ES1:
4848 	case OMAPDSS_VER_OMAP34xx_ES3:
4849 	case OMAPDSS_VER_OMAP3630:
4850 	case OMAPDSS_VER_AM35xx:
4851 		return OMAP_DSS_CHANNEL_LCD;
4852 
4853 	case OMAPDSS_VER_OMAP4430_ES1:
4854 	case OMAPDSS_VER_OMAP4430_ES2:
4855 	case OMAPDSS_VER_OMAP4:
4856 		switch (module_id) {
4857 		case 0:
4858 			return OMAP_DSS_CHANNEL_LCD;
4859 		case 1:
4860 			return OMAP_DSS_CHANNEL_LCD2;
4861 		default:
4862 			DSSWARN("unsupported module id\n");
4863 			return OMAP_DSS_CHANNEL_LCD;
4864 		}
4865 
4866 	case OMAPDSS_VER_OMAP5:
4867 		switch (module_id) {
4868 		case 0:
4869 			return OMAP_DSS_CHANNEL_LCD;
4870 		case 1:
4871 			return OMAP_DSS_CHANNEL_LCD3;
4872 		default:
4873 			DSSWARN("unsupported module id\n");
4874 			return OMAP_DSS_CHANNEL_LCD;
4875 		}
4876 
4877 	default:
4878 		DSSWARN("unsupported DSS version\n");
4879 		return OMAP_DSS_CHANNEL_LCD;
4880 	}
4881 }
4882 
4883 static int dsi_request_vc(struct omap_dss_device *dssdev, int *channel)
4884 {
4885 	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4886 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4887 	int i;
4888 
4889 	for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) {
4890 		if (!dsi->vc[i].dssdev) {
4891 			dsi->vc[i].dssdev = dssdev;
4892 			*channel = i;
4893 			return 0;
4894 		}
4895 	}
4896 
4897 	DSSERR("cannot get VC for display %s", dssdev->name);
4898 	return -ENOSPC;
4899 }
4900 
4901 static int dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id)
4902 {
4903 	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4904 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4905 
4906 	if (vc_id < 0 || vc_id > 3) {
4907 		DSSERR("VC ID out of range\n");
4908 		return -EINVAL;
4909 	}
4910 
4911 	if (channel < 0 || channel > 3) {
4912 		DSSERR("Virtual Channel out of range\n");
4913 		return -EINVAL;
4914 	}
4915 
4916 	if (dsi->vc[channel].dssdev != dssdev) {
4917 		DSSERR("Virtual Channel not allocated to display %s\n",
4918 			dssdev->name);
4919 		return -EINVAL;
4920 	}
4921 
4922 	dsi->vc[channel].vc_id = vc_id;
4923 
4924 	return 0;
4925 }
4926 
4927 static void dsi_release_vc(struct omap_dss_device *dssdev, int channel)
4928 {
4929 	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4930 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4931 
4932 	if ((channel >= 0 && channel <= 3) &&
4933 		dsi->vc[channel].dssdev == dssdev) {
4934 		dsi->vc[channel].dssdev = NULL;
4935 		dsi->vc[channel].vc_id = 0;
4936 	}
4937 }
4938 
4939 
4940 static int dsi_get_clocks(struct platform_device *dsidev)
4941 {
4942 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4943 	struct clk *clk;
4944 
4945 	clk = devm_clk_get(&dsidev->dev, "fck");
4946 	if (IS_ERR(clk)) {
4947 		DSSERR("can't get fck\n");
4948 		return PTR_ERR(clk);
4949 	}
4950 
4951 	dsi->dss_clk = clk;
4952 
4953 	return 0;
4954 }
4955 
4956 static int dsi_connect(struct omap_dss_device *dssdev,
4957 		struct omap_dss_device *dst)
4958 {
4959 	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4960 	struct omap_overlay_manager *mgr;
4961 	int r;
4962 
4963 	r = dsi_regulator_init(dsidev);
4964 	if (r)
4965 		return r;
4966 
4967 	mgr = omap_dss_get_overlay_manager(dssdev->dispc_channel);
4968 	if (!mgr)
4969 		return -ENODEV;
4970 
4971 	r = dss_mgr_connect(mgr, dssdev);
4972 	if (r)
4973 		return r;
4974 
4975 	r = omapdss_output_set_device(dssdev, dst);
4976 	if (r) {
4977 		DSSERR("failed to connect output to new device: %s\n",
4978 				dssdev->name);
4979 		dss_mgr_disconnect(mgr, dssdev);
4980 		return r;
4981 	}
4982 
4983 	return 0;
4984 }
4985 
4986 static void dsi_disconnect(struct omap_dss_device *dssdev,
4987 		struct omap_dss_device *dst)
4988 {
4989 	WARN_ON(dst != dssdev->dst);
4990 
4991 	if (dst != dssdev->dst)
4992 		return;
4993 
4994 	omapdss_output_unset_device(dssdev);
4995 
4996 	if (dssdev->manager)
4997 		dss_mgr_disconnect(dssdev->manager, dssdev);
4998 }
4999 
5000 static const struct omapdss_dsi_ops dsi_ops = {
5001 	.connect = dsi_connect,
5002 	.disconnect = dsi_disconnect,
5003 
5004 	.bus_lock = dsi_bus_lock,
5005 	.bus_unlock = dsi_bus_unlock,
5006 
5007 	.enable = dsi_display_enable,
5008 	.disable = dsi_display_disable,
5009 
5010 	.enable_hs = dsi_vc_enable_hs,
5011 
5012 	.configure_pins = dsi_configure_pins,
5013 	.set_config = dsi_set_config,
5014 
5015 	.enable_video_output = dsi_enable_video_output,
5016 	.disable_video_output = dsi_disable_video_output,
5017 
5018 	.update = dsi_update,
5019 
5020 	.enable_te = dsi_enable_te,
5021 
5022 	.request_vc = dsi_request_vc,
5023 	.set_vc_id = dsi_set_vc_id,
5024 	.release_vc = dsi_release_vc,
5025 
5026 	.dcs_write = dsi_vc_dcs_write,
5027 	.dcs_write_nosync = dsi_vc_dcs_write_nosync,
5028 	.dcs_read = dsi_vc_dcs_read,
5029 
5030 	.gen_write = dsi_vc_generic_write,
5031 	.gen_write_nosync = dsi_vc_generic_write_nosync,
5032 	.gen_read = dsi_vc_generic_read,
5033 
5034 	.bta_sync = dsi_vc_send_bta_sync,
5035 
5036 	.set_max_rx_packet_size = dsi_vc_set_max_rx_packet_size,
5037 };
5038 
5039 static void dsi_init_output(struct platform_device *dsidev)
5040 {
5041 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5042 	struct omap_dss_device *out = &dsi->output;
5043 
5044 	out->dev = &dsidev->dev;
5045 	out->id = dsi->module_id == 0 ?
5046 			OMAP_DSS_OUTPUT_DSI1 : OMAP_DSS_OUTPUT_DSI2;
5047 
5048 	out->output_type = OMAP_DISPLAY_TYPE_DSI;
5049 	out->name = dsi->module_id == 0 ? "dsi.0" : "dsi.1";
5050 	out->dispc_channel = dsi_get_channel(dsi->module_id);
5051 	out->ops.dsi = &dsi_ops;
5052 	out->owner = THIS_MODULE;
5053 
5054 	omapdss_register_output(out);
5055 }
5056 
5057 static void dsi_uninit_output(struct platform_device *dsidev)
5058 {
5059 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5060 	struct omap_dss_device *out = &dsi->output;
5061 
5062 	omapdss_unregister_output(out);
5063 }
5064 
5065 static int dsi_probe_of(struct platform_device *pdev)
5066 {
5067 	struct device_node *node = pdev->dev.of_node;
5068 	struct dsi_data *dsi = dsi_get_dsidrv_data(pdev);
5069 	struct property *prop;
5070 	u32 lane_arr[10];
5071 	int len, num_pins;
5072 	int r, i;
5073 	struct device_node *ep;
5074 	struct omap_dsi_pin_config pin_cfg;
5075 
5076 	ep = omapdss_of_get_first_endpoint(node);
5077 	if (!ep)
5078 		return 0;
5079 
5080 	prop = of_find_property(ep, "lanes", &len);
5081 	if (prop == NULL) {
5082 		dev_err(&pdev->dev, "failed to find lane data\n");
5083 		r = -EINVAL;
5084 		goto err;
5085 	}
5086 
5087 	num_pins = len / sizeof(u32);
5088 
5089 	if (num_pins < 4 || num_pins % 2 != 0 ||
5090 		num_pins > dsi->num_lanes_supported * 2) {
5091 		dev_err(&pdev->dev, "bad number of lanes\n");
5092 		r = -EINVAL;
5093 		goto err;
5094 	}
5095 
5096 	r = of_property_read_u32_array(ep, "lanes", lane_arr, num_pins);
5097 	if (r) {
5098 		dev_err(&pdev->dev, "failed to read lane data\n");
5099 		goto err;
5100 	}
5101 
5102 	pin_cfg.num_pins = num_pins;
5103 	for (i = 0; i < num_pins; ++i)
5104 		pin_cfg.pins[i] = (int)lane_arr[i];
5105 
5106 	r = dsi_configure_pins(&dsi->output, &pin_cfg);
5107 	if (r) {
5108 		dev_err(&pdev->dev, "failed to configure pins");
5109 		goto err;
5110 	}
5111 
5112 	of_node_put(ep);
5113 
5114 	return 0;
5115 
5116 err:
5117 	of_node_put(ep);
5118 	return r;
5119 }
5120 
5121 static const struct dss_pll_ops dsi_pll_ops = {
5122 	.enable = dsi_pll_enable,
5123 	.disable = dsi_pll_disable,
5124 	.set_config = dss_pll_write_config_type_a,
5125 };
5126 
5127 static const struct dss_pll_hw dss_omap3_dsi_pll_hw = {
5128 	.n_max = (1 << 7) - 1,
5129 	.m_max = (1 << 11) - 1,
5130 	.mX_max = (1 << 4) - 1,
5131 	.fint_min = 750000,
5132 	.fint_max = 2100000,
5133 	.clkdco_low = 1000000000,
5134 	.clkdco_max = 1800000000,
5135 
5136 	.n_msb = 7,
5137 	.n_lsb = 1,
5138 	.m_msb = 18,
5139 	.m_lsb = 8,
5140 
5141 	.mX_msb[0] = 22,
5142 	.mX_lsb[0] = 19,
5143 	.mX_msb[1] = 26,
5144 	.mX_lsb[1] = 23,
5145 
5146 	.has_stopmode = true,
5147 	.has_freqsel = true,
5148 	.has_selfreqdco = false,
5149 	.has_refsel = false,
5150 };
5151 
5152 static const struct dss_pll_hw dss_omap4_dsi_pll_hw = {
5153 	.n_max = (1 << 8) - 1,
5154 	.m_max = (1 << 12) - 1,
5155 	.mX_max = (1 << 5) - 1,
5156 	.fint_min = 500000,
5157 	.fint_max = 2500000,
5158 	.clkdco_low = 1000000000,
5159 	.clkdco_max = 1800000000,
5160 
5161 	.n_msb = 8,
5162 	.n_lsb = 1,
5163 	.m_msb = 20,
5164 	.m_lsb = 9,
5165 
5166 	.mX_msb[0] = 25,
5167 	.mX_lsb[0] = 21,
5168 	.mX_msb[1] = 30,
5169 	.mX_lsb[1] = 26,
5170 
5171 	.has_stopmode = true,
5172 	.has_freqsel = false,
5173 	.has_selfreqdco = false,
5174 	.has_refsel = false,
5175 };
5176 
5177 static const struct dss_pll_hw dss_omap5_dsi_pll_hw = {
5178 	.n_max = (1 << 8) - 1,
5179 	.m_max = (1 << 12) - 1,
5180 	.mX_max = (1 << 5) - 1,
5181 	.fint_min = 150000,
5182 	.fint_max = 52000000,
5183 	.clkdco_low = 1000000000,
5184 	.clkdco_max = 1800000000,
5185 
5186 	.n_msb = 8,
5187 	.n_lsb = 1,
5188 	.m_msb = 20,
5189 	.m_lsb = 9,
5190 
5191 	.mX_msb[0] = 25,
5192 	.mX_lsb[0] = 21,
5193 	.mX_msb[1] = 30,
5194 	.mX_lsb[1] = 26,
5195 
5196 	.has_stopmode = true,
5197 	.has_freqsel = false,
5198 	.has_selfreqdco = true,
5199 	.has_refsel = true,
5200 };
5201 
5202 static int dsi_init_pll_data(struct platform_device *dsidev)
5203 {
5204 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5205 	struct dss_pll *pll = &dsi->pll;
5206 	struct clk *clk;
5207 	int r;
5208 
5209 	clk = devm_clk_get(&dsidev->dev, "sys_clk");
5210 	if (IS_ERR(clk)) {
5211 		DSSERR("can't get sys_clk\n");
5212 		return PTR_ERR(clk);
5213 	}
5214 
5215 	pll->name = dsi->module_id == 0 ? "dsi0" : "dsi1";
5216 	pll->id = dsi->module_id == 0 ? DSS_PLL_DSI1 : DSS_PLL_DSI2;
5217 	pll->clkin = clk;
5218 	pll->base = dsi->pll_base;
5219 
5220 	switch (omapdss_get_version()) {
5221 	case OMAPDSS_VER_OMAP34xx_ES1:
5222 	case OMAPDSS_VER_OMAP34xx_ES3:
5223 	case OMAPDSS_VER_OMAP3630:
5224 	case OMAPDSS_VER_AM35xx:
5225 		pll->hw = &dss_omap3_dsi_pll_hw;
5226 		break;
5227 
5228 	case OMAPDSS_VER_OMAP4430_ES1:
5229 	case OMAPDSS_VER_OMAP4430_ES2:
5230 	case OMAPDSS_VER_OMAP4:
5231 		pll->hw = &dss_omap4_dsi_pll_hw;
5232 		break;
5233 
5234 	case OMAPDSS_VER_OMAP5:
5235 		pll->hw = &dss_omap5_dsi_pll_hw;
5236 		break;
5237 
5238 	default:
5239 		return -ENODEV;
5240 	}
5241 
5242 	pll->ops = &dsi_pll_ops;
5243 
5244 	r = dss_pll_register(pll);
5245 	if (r)
5246 		return r;
5247 
5248 	return 0;
5249 }
5250 
5251 /* DSI1 HW IP initialisation */
5252 static int dsi_bind(struct device *dev, struct device *master, void *data)
5253 {
5254 	struct platform_device *dsidev = to_platform_device(dev);
5255 	u32 rev;
5256 	int r, i;
5257 	struct dsi_data *dsi;
5258 	struct resource *dsi_mem;
5259 	struct resource *res;
5260 	struct resource temp_res;
5261 
5262 	dsi = devm_kzalloc(&dsidev->dev, sizeof(*dsi), GFP_KERNEL);
5263 	if (!dsi)
5264 		return -ENOMEM;
5265 
5266 	dsi->pdev = dsidev;
5267 	platform_set_drvdata(dsidev, dsi);
5268 
5269 	spin_lock_init(&dsi->irq_lock);
5270 	spin_lock_init(&dsi->errors_lock);
5271 	dsi->errors = 0;
5272 
5273 #ifdef CONFIG_FB_OMAP2_DSS_COLLECT_IRQ_STATS
5274 	spin_lock_init(&dsi->irq_stats_lock);
5275 	dsi->irq_stats.last_reset = jiffies;
5276 #endif
5277 
5278 	mutex_init(&dsi->lock);
5279 	sema_init(&dsi->bus_lock, 1);
5280 
5281 	INIT_DEFERRABLE_WORK(&dsi->framedone_timeout_work,
5282 			     dsi_framedone_timeout_work_callback);
5283 
5284 #ifdef DSI_CATCH_MISSING_TE
5285 	timer_setup(&dsi->te_timer, dsi_te_timeout, 0);
5286 #endif
5287 
5288 	res = platform_get_resource_byname(dsidev, IORESOURCE_MEM, "proto");
5289 	if (!res) {
5290 		res = platform_get_resource(dsidev, IORESOURCE_MEM, 0);
5291 		if (!res) {
5292 			DSSERR("can't get IORESOURCE_MEM DSI\n");
5293 			return -EINVAL;
5294 		}
5295 
5296 		temp_res.start = res->start;
5297 		temp_res.end = temp_res.start + DSI_PROTO_SZ - 1;
5298 		res = &temp_res;
5299 	}
5300 
5301 	dsi_mem = res;
5302 
5303 	dsi->proto_base = devm_ioremap(&dsidev->dev, res->start,
5304 		resource_size(res));
5305 	if (!dsi->proto_base) {
5306 		DSSERR("can't ioremap DSI protocol engine\n");
5307 		return -ENOMEM;
5308 	}
5309 
5310 	res = platform_get_resource_byname(dsidev, IORESOURCE_MEM, "phy");
5311 	if (!res) {
5312 		res = platform_get_resource(dsidev, IORESOURCE_MEM, 0);
5313 		if (!res) {
5314 			DSSERR("can't get IORESOURCE_MEM DSI\n");
5315 			return -EINVAL;
5316 		}
5317 
5318 		temp_res.start = res->start + DSI_PHY_OFFSET;
5319 		temp_res.end = temp_res.start + DSI_PHY_SZ - 1;
5320 		res = &temp_res;
5321 	}
5322 
5323 	dsi->phy_base = devm_ioremap(&dsidev->dev, res->start,
5324 		resource_size(res));
5325 	if (!dsi->phy_base) {
5326 		DSSERR("can't ioremap DSI PHY\n");
5327 		return -ENOMEM;
5328 	}
5329 
5330 	res = platform_get_resource_byname(dsidev, IORESOURCE_MEM, "pll");
5331 	if (!res) {
5332 		res = platform_get_resource(dsidev, IORESOURCE_MEM, 0);
5333 		if (!res) {
5334 			DSSERR("can't get IORESOURCE_MEM DSI\n");
5335 			return -EINVAL;
5336 		}
5337 
5338 		temp_res.start = res->start + DSI_PLL_OFFSET;
5339 		temp_res.end = temp_res.start + DSI_PLL_SZ - 1;
5340 		res = &temp_res;
5341 	}
5342 
5343 	dsi->pll_base = devm_ioremap(&dsidev->dev, res->start,
5344 		resource_size(res));
5345 	if (!dsi->pll_base) {
5346 		DSSERR("can't ioremap DSI PLL\n");
5347 		return -ENOMEM;
5348 	}
5349 
5350 	dsi->irq = platform_get_irq(dsi->pdev, 0);
5351 	if (dsi->irq < 0) {
5352 		DSSERR("platform_get_irq failed\n");
5353 		return -ENODEV;
5354 	}
5355 
5356 	r = devm_request_irq(&dsidev->dev, dsi->irq, omap_dsi_irq_handler,
5357 			     IRQF_SHARED, dev_name(&dsidev->dev), dsi->pdev);
5358 	if (r < 0) {
5359 		DSSERR("request_irq failed\n");
5360 		return r;
5361 	}
5362 
5363 	if (dsidev->dev.of_node) {
5364 		const struct of_device_id *match;
5365 		const struct dsi_module_id_data *d;
5366 
5367 		match = of_match_node(dsi_of_match, dsidev->dev.of_node);
5368 		if (!match) {
5369 			DSSERR("unsupported DSI module\n");
5370 			return -ENODEV;
5371 		}
5372 
5373 		d = match->data;
5374 
5375 		while (d->address != 0 && d->address != dsi_mem->start)
5376 			d++;
5377 
5378 		if (d->address == 0) {
5379 			DSSERR("unsupported DSI module\n");
5380 			return -ENODEV;
5381 		}
5382 
5383 		dsi->module_id = d->id;
5384 	} else {
5385 		dsi->module_id = dsidev->id;
5386 	}
5387 
5388 	/* DSI VCs initialization */
5389 	for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) {
5390 		dsi->vc[i].source = DSI_VC_SOURCE_L4;
5391 		dsi->vc[i].dssdev = NULL;
5392 		dsi->vc[i].vc_id = 0;
5393 	}
5394 
5395 	r = dsi_get_clocks(dsidev);
5396 	if (r)
5397 		return r;
5398 
5399 	dsi_init_pll_data(dsidev);
5400 
5401 	pm_runtime_enable(&dsidev->dev);
5402 
5403 	r = dsi_runtime_get(dsidev);
5404 	if (r)
5405 		goto err_runtime_get;
5406 
5407 	rev = dsi_read_reg(dsidev, DSI_REVISION);
5408 	dev_dbg(&dsidev->dev, "OMAP DSI rev %d.%d\n",
5409 	       FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
5410 
5411 	/* DSI on OMAP3 doesn't have register DSI_GNQ, set number
5412 	 * of data to 3 by default */
5413 	if (dss_has_feature(FEAT_DSI_GNQ))
5414 		/* NB_DATA_LANES */
5415 		dsi->num_lanes_supported = 1 + REG_GET(dsidev, DSI_GNQ, 11, 9);
5416 	else
5417 		dsi->num_lanes_supported = 3;
5418 
5419 	dsi->line_buffer_size = dsi_get_line_buf_size(dsidev);
5420 
5421 	dsi_init_output(dsidev);
5422 
5423 	if (dsidev->dev.of_node) {
5424 		r = dsi_probe_of(dsidev);
5425 		if (r) {
5426 			DSSERR("Invalid DSI DT data\n");
5427 			goto err_probe_of;
5428 		}
5429 
5430 		r = of_platform_populate(dsidev->dev.of_node, NULL, NULL,
5431 			&dsidev->dev);
5432 		if (r)
5433 			DSSERR("Failed to populate DSI child devices: %d\n", r);
5434 	}
5435 
5436 	dsi_runtime_put(dsidev);
5437 
5438 	if (dsi->module_id == 0)
5439 		dss_debugfs_create_file("dsi1_regs", dsi1_dump_regs);
5440 	else if (dsi->module_id == 1)
5441 		dss_debugfs_create_file("dsi2_regs", dsi2_dump_regs);
5442 
5443 #ifdef CONFIG_FB_OMAP2_DSS_COLLECT_IRQ_STATS
5444 	if (dsi->module_id == 0)
5445 		dss_debugfs_create_file("dsi1_irqs", dsi1_dump_irqs);
5446 	else if (dsi->module_id == 1)
5447 		dss_debugfs_create_file("dsi2_irqs", dsi2_dump_irqs);
5448 #endif
5449 
5450 	return 0;
5451 
5452 err_probe_of:
5453 	dsi_uninit_output(dsidev);
5454 	dsi_runtime_put(dsidev);
5455 
5456 err_runtime_get:
5457 	pm_runtime_disable(&dsidev->dev);
5458 	return r;
5459 }
5460 
5461 static void dsi_unbind(struct device *dev, struct device *master, void *data)
5462 {
5463 	struct platform_device *dsidev = to_platform_device(dev);
5464 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5465 
5466 	of_platform_depopulate(&dsidev->dev);
5467 
5468 	WARN_ON(dsi->scp_clk_refcount > 0);
5469 
5470 	dss_pll_unregister(&dsi->pll);
5471 
5472 	dsi_uninit_output(dsidev);
5473 
5474 	pm_runtime_disable(&dsidev->dev);
5475 
5476 	if (dsi->vdds_dsi_reg != NULL && dsi->vdds_dsi_enabled) {
5477 		regulator_disable(dsi->vdds_dsi_reg);
5478 		dsi->vdds_dsi_enabled = false;
5479 	}
5480 }
5481 
5482 static const struct component_ops dsi_component_ops = {
5483 	.bind	= dsi_bind,
5484 	.unbind	= dsi_unbind,
5485 };
5486 
5487 static int dsi_probe(struct platform_device *pdev)
5488 {
5489 	return component_add(&pdev->dev, &dsi_component_ops);
5490 }
5491 
5492 static int dsi_remove(struct platform_device *pdev)
5493 {
5494 	component_del(&pdev->dev, &dsi_component_ops);
5495 	return 0;
5496 }
5497 
5498 static int dsi_runtime_suspend(struct device *dev)
5499 {
5500 	struct platform_device *pdev = to_platform_device(dev);
5501 	struct dsi_data *dsi = dsi_get_dsidrv_data(pdev);
5502 
5503 	dsi->is_enabled = false;
5504 	/* ensure the irq handler sees the is_enabled value */
5505 	smp_wmb();
5506 	/* wait for current handler to finish before turning the DSI off */
5507 	synchronize_irq(dsi->irq);
5508 
5509 	dispc_runtime_put();
5510 
5511 	return 0;
5512 }
5513 
5514 static int dsi_runtime_resume(struct device *dev)
5515 {
5516 	struct platform_device *pdev = to_platform_device(dev);
5517 	struct dsi_data *dsi = dsi_get_dsidrv_data(pdev);
5518 	int r;
5519 
5520 	r = dispc_runtime_get();
5521 	if (r)
5522 		return r;
5523 
5524 	dsi->is_enabled = true;
5525 	/* ensure the irq handler sees the is_enabled value */
5526 	smp_wmb();
5527 
5528 	return 0;
5529 }
5530 
5531 static const struct dev_pm_ops dsi_pm_ops = {
5532 	.runtime_suspend = dsi_runtime_suspend,
5533 	.runtime_resume = dsi_runtime_resume,
5534 };
5535 
5536 static const struct dsi_module_id_data dsi_of_data_omap3[] = {
5537 	{ .address = 0x4804fc00, .id = 0, },
5538 	{ },
5539 };
5540 
5541 static const struct dsi_module_id_data dsi_of_data_omap4[] = {
5542 	{ .address = 0x58004000, .id = 0, },
5543 	{ .address = 0x58005000, .id = 1, },
5544 	{ },
5545 };
5546 
5547 static const struct dsi_module_id_data dsi_of_data_omap5[] = {
5548 	{ .address = 0x58004000, .id = 0, },
5549 	{ .address = 0x58009000, .id = 1, },
5550 	{ },
5551 };
5552 
5553 static const struct of_device_id dsi_of_match[] = {
5554 	{ .compatible = "ti,omap3-dsi", .data = dsi_of_data_omap3, },
5555 	{ .compatible = "ti,omap4-dsi", .data = dsi_of_data_omap4, },
5556 	{ .compatible = "ti,omap5-dsi", .data = dsi_of_data_omap5, },
5557 	{},
5558 };
5559 
5560 static struct platform_driver omap_dsihw_driver = {
5561 	.probe		= dsi_probe,
5562 	.remove		= dsi_remove,
5563 	.driver         = {
5564 		.name   = "omapdss_dsi",
5565 		.pm	= &dsi_pm_ops,
5566 		.of_match_table = dsi_of_match,
5567 		.suppress_bind_attrs = true,
5568 	},
5569 };
5570 
5571 int __init dsi_init_platform_driver(void)
5572 {
5573 	return platform_driver_register(&omap_dsihw_driver);
5574 }
5575 
5576 void dsi_uninit_platform_driver(void)
5577 {
5578 	platform_driver_unregister(&omap_dsihw_driver);
5579 }
5580