1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * linux/drivers/video/omap2/dss/dsi.c 4 * 5 * Copyright (C) 2009 Nokia Corporation 6 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> 7 */ 8 9 #define DSS_SUBSYS_NAME "DSI" 10 11 #include <linux/kernel.h> 12 #include <linux/io.h> 13 #include <linux/clk.h> 14 #include <linux/device.h> 15 #include <linux/err.h> 16 #include <linux/interrupt.h> 17 #include <linux/delay.h> 18 #include <linux/mutex.h> 19 #include <linux/module.h> 20 #include <linux/semaphore.h> 21 #include <linux/seq_file.h> 22 #include <linux/platform_device.h> 23 #include <linux/regulator/consumer.h> 24 #include <linux/wait.h> 25 #include <linux/workqueue.h> 26 #include <linux/sched.h> 27 #include <linux/slab.h> 28 #include <linux/debugfs.h> 29 #include <linux/pm_runtime.h> 30 #include <linux/of.h> 31 #include <linux/of_platform.h> 32 #include <linux/component.h> 33 34 #include <video/omapfb_dss.h> 35 #include <video/mipi_display.h> 36 37 #include "dss.h" 38 #include "dss_features.h" 39 40 #define DSI_CATCH_MISSING_TE 41 42 struct dsi_reg { u16 module; u16 idx; }; 43 44 #define DSI_REG(mod, idx) ((const struct dsi_reg) { mod, idx }) 45 46 /* DSI Protocol Engine */ 47 48 #define DSI_PROTO 0 49 #define DSI_PROTO_SZ 0x200 50 51 #define DSI_REVISION DSI_REG(DSI_PROTO, 0x0000) 52 #define DSI_SYSCONFIG DSI_REG(DSI_PROTO, 0x0010) 53 #define DSI_SYSSTATUS DSI_REG(DSI_PROTO, 0x0014) 54 #define DSI_IRQSTATUS DSI_REG(DSI_PROTO, 0x0018) 55 #define DSI_IRQENABLE DSI_REG(DSI_PROTO, 0x001C) 56 #define DSI_CTRL DSI_REG(DSI_PROTO, 0x0040) 57 #define DSI_GNQ DSI_REG(DSI_PROTO, 0x0044) 58 #define DSI_COMPLEXIO_CFG1 DSI_REG(DSI_PROTO, 0x0048) 59 #define DSI_COMPLEXIO_IRQ_STATUS DSI_REG(DSI_PROTO, 0x004C) 60 #define DSI_COMPLEXIO_IRQ_ENABLE DSI_REG(DSI_PROTO, 0x0050) 61 #define DSI_CLK_CTRL DSI_REG(DSI_PROTO, 0x0054) 62 #define DSI_TIMING1 DSI_REG(DSI_PROTO, 0x0058) 63 #define DSI_TIMING2 DSI_REG(DSI_PROTO, 0x005C) 64 #define DSI_VM_TIMING1 DSI_REG(DSI_PROTO, 0x0060) 65 #define DSI_VM_TIMING2 DSI_REG(DSI_PROTO, 0x0064) 66 #define DSI_VM_TIMING3 DSI_REG(DSI_PROTO, 0x0068) 67 #define DSI_CLK_TIMING DSI_REG(DSI_PROTO, 0x006C) 68 #define DSI_TX_FIFO_VC_SIZE DSI_REG(DSI_PROTO, 0x0070) 69 #define DSI_RX_FIFO_VC_SIZE DSI_REG(DSI_PROTO, 0x0074) 70 #define DSI_COMPLEXIO_CFG2 DSI_REG(DSI_PROTO, 0x0078) 71 #define DSI_RX_FIFO_VC_FULLNESS DSI_REG(DSI_PROTO, 0x007C) 72 #define DSI_VM_TIMING4 DSI_REG(DSI_PROTO, 0x0080) 73 #define DSI_TX_FIFO_VC_EMPTINESS DSI_REG(DSI_PROTO, 0x0084) 74 #define DSI_VM_TIMING5 DSI_REG(DSI_PROTO, 0x0088) 75 #define DSI_VM_TIMING6 DSI_REG(DSI_PROTO, 0x008C) 76 #define DSI_VM_TIMING7 DSI_REG(DSI_PROTO, 0x0090) 77 #define DSI_STOPCLK_TIMING DSI_REG(DSI_PROTO, 0x0094) 78 #define DSI_VC_CTRL(n) DSI_REG(DSI_PROTO, 0x0100 + (n * 0x20)) 79 #define DSI_VC_TE(n) DSI_REG(DSI_PROTO, 0x0104 + (n * 0x20)) 80 #define DSI_VC_LONG_PACKET_HEADER(n) DSI_REG(DSI_PROTO, 0x0108 + (n * 0x20)) 81 #define DSI_VC_LONG_PACKET_PAYLOAD(n) DSI_REG(DSI_PROTO, 0x010C + (n * 0x20)) 82 #define DSI_VC_SHORT_PACKET_HEADER(n) DSI_REG(DSI_PROTO, 0x0110 + (n * 0x20)) 83 #define DSI_VC_IRQSTATUS(n) DSI_REG(DSI_PROTO, 0x0118 + (n * 0x20)) 84 #define DSI_VC_IRQENABLE(n) DSI_REG(DSI_PROTO, 0x011C + (n * 0x20)) 85 86 /* DSIPHY_SCP */ 87 88 #define DSI_PHY 1 89 #define DSI_PHY_OFFSET 0x200 90 #define DSI_PHY_SZ 0x40 91 92 #define DSI_DSIPHY_CFG0 DSI_REG(DSI_PHY, 0x0000) 93 #define DSI_DSIPHY_CFG1 DSI_REG(DSI_PHY, 0x0004) 94 #define DSI_DSIPHY_CFG2 DSI_REG(DSI_PHY, 0x0008) 95 #define DSI_DSIPHY_CFG5 DSI_REG(DSI_PHY, 0x0014) 96 #define DSI_DSIPHY_CFG10 DSI_REG(DSI_PHY, 0x0028) 97 98 /* DSI_PLL_CTRL_SCP */ 99 100 #define DSI_PLL 2 101 #define DSI_PLL_OFFSET 0x300 102 #define DSI_PLL_SZ 0x20 103 104 #define DSI_PLL_CONTROL DSI_REG(DSI_PLL, 0x0000) 105 #define DSI_PLL_STATUS DSI_REG(DSI_PLL, 0x0004) 106 #define DSI_PLL_GO DSI_REG(DSI_PLL, 0x0008) 107 #define DSI_PLL_CONFIGURATION1 DSI_REG(DSI_PLL, 0x000C) 108 #define DSI_PLL_CONFIGURATION2 DSI_REG(DSI_PLL, 0x0010) 109 110 #define REG_GET(dsidev, idx, start, end) \ 111 FLD_GET(dsi_read_reg(dsidev, idx), start, end) 112 113 #define REG_FLD_MOD(dsidev, idx, val, start, end) \ 114 dsi_write_reg(dsidev, idx, FLD_MOD(dsi_read_reg(dsidev, idx), val, start, end)) 115 116 /* Global interrupts */ 117 #define DSI_IRQ_VC0 (1 << 0) 118 #define DSI_IRQ_VC1 (1 << 1) 119 #define DSI_IRQ_VC2 (1 << 2) 120 #define DSI_IRQ_VC3 (1 << 3) 121 #define DSI_IRQ_WAKEUP (1 << 4) 122 #define DSI_IRQ_RESYNC (1 << 5) 123 #define DSI_IRQ_PLL_LOCK (1 << 7) 124 #define DSI_IRQ_PLL_UNLOCK (1 << 8) 125 #define DSI_IRQ_PLL_RECALL (1 << 9) 126 #define DSI_IRQ_COMPLEXIO_ERR (1 << 10) 127 #define DSI_IRQ_HS_TX_TIMEOUT (1 << 14) 128 #define DSI_IRQ_LP_RX_TIMEOUT (1 << 15) 129 #define DSI_IRQ_TE_TRIGGER (1 << 16) 130 #define DSI_IRQ_ACK_TRIGGER (1 << 17) 131 #define DSI_IRQ_SYNC_LOST (1 << 18) 132 #define DSI_IRQ_LDO_POWER_GOOD (1 << 19) 133 #define DSI_IRQ_TA_TIMEOUT (1 << 20) 134 #define DSI_IRQ_ERROR_MASK \ 135 (DSI_IRQ_HS_TX_TIMEOUT | DSI_IRQ_LP_RX_TIMEOUT | DSI_IRQ_SYNC_LOST | \ 136 DSI_IRQ_TA_TIMEOUT) 137 #define DSI_IRQ_CHANNEL_MASK 0xf 138 139 /* Virtual channel interrupts */ 140 #define DSI_VC_IRQ_CS (1 << 0) 141 #define DSI_VC_IRQ_ECC_CORR (1 << 1) 142 #define DSI_VC_IRQ_PACKET_SENT (1 << 2) 143 #define DSI_VC_IRQ_FIFO_TX_OVF (1 << 3) 144 #define DSI_VC_IRQ_FIFO_RX_OVF (1 << 4) 145 #define DSI_VC_IRQ_BTA (1 << 5) 146 #define DSI_VC_IRQ_ECC_NO_CORR (1 << 6) 147 #define DSI_VC_IRQ_FIFO_TX_UDF (1 << 7) 148 #define DSI_VC_IRQ_PP_BUSY_CHANGE (1 << 8) 149 #define DSI_VC_IRQ_ERROR_MASK \ 150 (DSI_VC_IRQ_CS | DSI_VC_IRQ_ECC_CORR | DSI_VC_IRQ_FIFO_TX_OVF | \ 151 DSI_VC_IRQ_FIFO_RX_OVF | DSI_VC_IRQ_ECC_NO_CORR | \ 152 DSI_VC_IRQ_FIFO_TX_UDF) 153 154 /* ComplexIO interrupts */ 155 #define DSI_CIO_IRQ_ERRSYNCESC1 (1 << 0) 156 #define DSI_CIO_IRQ_ERRSYNCESC2 (1 << 1) 157 #define DSI_CIO_IRQ_ERRSYNCESC3 (1 << 2) 158 #define DSI_CIO_IRQ_ERRSYNCESC4 (1 << 3) 159 #define DSI_CIO_IRQ_ERRSYNCESC5 (1 << 4) 160 #define DSI_CIO_IRQ_ERRESC1 (1 << 5) 161 #define DSI_CIO_IRQ_ERRESC2 (1 << 6) 162 #define DSI_CIO_IRQ_ERRESC3 (1 << 7) 163 #define DSI_CIO_IRQ_ERRESC4 (1 << 8) 164 #define DSI_CIO_IRQ_ERRESC5 (1 << 9) 165 #define DSI_CIO_IRQ_ERRCONTROL1 (1 << 10) 166 #define DSI_CIO_IRQ_ERRCONTROL2 (1 << 11) 167 #define DSI_CIO_IRQ_ERRCONTROL3 (1 << 12) 168 #define DSI_CIO_IRQ_ERRCONTROL4 (1 << 13) 169 #define DSI_CIO_IRQ_ERRCONTROL5 (1 << 14) 170 #define DSI_CIO_IRQ_STATEULPS1 (1 << 15) 171 #define DSI_CIO_IRQ_STATEULPS2 (1 << 16) 172 #define DSI_CIO_IRQ_STATEULPS3 (1 << 17) 173 #define DSI_CIO_IRQ_STATEULPS4 (1 << 18) 174 #define DSI_CIO_IRQ_STATEULPS5 (1 << 19) 175 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_1 (1 << 20) 176 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_1 (1 << 21) 177 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_2 (1 << 22) 178 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_2 (1 << 23) 179 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_3 (1 << 24) 180 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_3 (1 << 25) 181 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_4 (1 << 26) 182 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_4 (1 << 27) 183 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_5 (1 << 28) 184 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_5 (1 << 29) 185 #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL0 (1 << 30) 186 #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL1 (1 << 31) 187 #define DSI_CIO_IRQ_ERROR_MASK \ 188 (DSI_CIO_IRQ_ERRSYNCESC1 | DSI_CIO_IRQ_ERRSYNCESC2 | \ 189 DSI_CIO_IRQ_ERRSYNCESC3 | DSI_CIO_IRQ_ERRSYNCESC4 | \ 190 DSI_CIO_IRQ_ERRSYNCESC5 | \ 191 DSI_CIO_IRQ_ERRESC1 | DSI_CIO_IRQ_ERRESC2 | \ 192 DSI_CIO_IRQ_ERRESC3 | DSI_CIO_IRQ_ERRESC4 | \ 193 DSI_CIO_IRQ_ERRESC5 | \ 194 DSI_CIO_IRQ_ERRCONTROL1 | DSI_CIO_IRQ_ERRCONTROL2 | \ 195 DSI_CIO_IRQ_ERRCONTROL3 | DSI_CIO_IRQ_ERRCONTROL4 | \ 196 DSI_CIO_IRQ_ERRCONTROL5 | \ 197 DSI_CIO_IRQ_ERRCONTENTIONLP0_1 | DSI_CIO_IRQ_ERRCONTENTIONLP1_1 | \ 198 DSI_CIO_IRQ_ERRCONTENTIONLP0_2 | DSI_CIO_IRQ_ERRCONTENTIONLP1_2 | \ 199 DSI_CIO_IRQ_ERRCONTENTIONLP0_3 | DSI_CIO_IRQ_ERRCONTENTIONLP1_3 | \ 200 DSI_CIO_IRQ_ERRCONTENTIONLP0_4 | DSI_CIO_IRQ_ERRCONTENTIONLP1_4 | \ 201 DSI_CIO_IRQ_ERRCONTENTIONLP0_5 | DSI_CIO_IRQ_ERRCONTENTIONLP1_5) 202 203 typedef void (*omap_dsi_isr_t) (void *arg, u32 mask); 204 205 static int dsi_display_init_dispc(struct platform_device *dsidev, 206 struct omap_overlay_manager *mgr); 207 static void dsi_display_uninit_dispc(struct platform_device *dsidev, 208 struct omap_overlay_manager *mgr); 209 210 static int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel); 211 212 /* DSI PLL HSDIV indices */ 213 #define HSDIV_DISPC 0 214 #define HSDIV_DSI 1 215 216 #define DSI_MAX_NR_ISRS 2 217 #define DSI_MAX_NR_LANES 5 218 219 enum dsi_lane_function { 220 DSI_LANE_UNUSED = 0, 221 DSI_LANE_CLK, 222 DSI_LANE_DATA1, 223 DSI_LANE_DATA2, 224 DSI_LANE_DATA3, 225 DSI_LANE_DATA4, 226 }; 227 228 struct dsi_lane_config { 229 enum dsi_lane_function function; 230 u8 polarity; 231 }; 232 233 struct dsi_isr_data { 234 omap_dsi_isr_t isr; 235 void *arg; 236 u32 mask; 237 }; 238 239 enum fifo_size { 240 DSI_FIFO_SIZE_0 = 0, 241 DSI_FIFO_SIZE_32 = 1, 242 DSI_FIFO_SIZE_64 = 2, 243 DSI_FIFO_SIZE_96 = 3, 244 DSI_FIFO_SIZE_128 = 4, 245 }; 246 247 enum dsi_vc_source { 248 DSI_VC_SOURCE_L4 = 0, 249 DSI_VC_SOURCE_VP, 250 }; 251 252 struct dsi_irq_stats { 253 unsigned long last_reset; 254 unsigned irq_count; 255 unsigned dsi_irqs[32]; 256 unsigned vc_irqs[4][32]; 257 unsigned cio_irqs[32]; 258 }; 259 260 struct dsi_isr_tables { 261 struct dsi_isr_data isr_table[DSI_MAX_NR_ISRS]; 262 struct dsi_isr_data isr_table_vc[4][DSI_MAX_NR_ISRS]; 263 struct dsi_isr_data isr_table_cio[DSI_MAX_NR_ISRS]; 264 }; 265 266 struct dsi_clk_calc_ctx { 267 struct platform_device *dsidev; 268 struct dss_pll *pll; 269 270 /* inputs */ 271 272 const struct omap_dss_dsi_config *config; 273 274 unsigned long req_pck_min, req_pck_nom, req_pck_max; 275 276 /* outputs */ 277 278 struct dss_pll_clock_info dsi_cinfo; 279 struct dispc_clock_info dispc_cinfo; 280 281 struct omap_video_timings dispc_vm; 282 struct omap_dss_dsi_videomode_timings dsi_vm; 283 }; 284 285 struct dsi_lp_clock_info { 286 unsigned long lp_clk; 287 u16 lp_clk_div; 288 }; 289 290 struct dsi_data { 291 struct platform_device *pdev; 292 void __iomem *proto_base; 293 void __iomem *phy_base; 294 void __iomem *pll_base; 295 296 int module_id; 297 298 int irq; 299 300 bool is_enabled; 301 302 struct clk *dss_clk; 303 304 struct dispc_clock_info user_dispc_cinfo; 305 struct dss_pll_clock_info user_dsi_cinfo; 306 307 struct dsi_lp_clock_info user_lp_cinfo; 308 struct dsi_lp_clock_info current_lp_cinfo; 309 310 struct dss_pll pll; 311 312 bool vdds_dsi_enabled; 313 struct regulator *vdds_dsi_reg; 314 315 struct { 316 enum dsi_vc_source source; 317 struct omap_dss_device *dssdev; 318 enum fifo_size tx_fifo_size; 319 enum fifo_size rx_fifo_size; 320 int vc_id; 321 } vc[4]; 322 323 struct mutex lock; 324 struct semaphore bus_lock; 325 326 spinlock_t irq_lock; 327 struct dsi_isr_tables isr_tables; 328 /* space for a copy used by the interrupt handler */ 329 struct dsi_isr_tables isr_tables_copy; 330 331 int update_channel; 332 #ifdef DSI_PERF_MEASURE 333 unsigned update_bytes; 334 #endif 335 336 bool te_enabled; 337 bool ulps_enabled; 338 339 void (*framedone_callback)(int, void *); 340 void *framedone_data; 341 342 struct delayed_work framedone_timeout_work; 343 344 #ifdef DSI_CATCH_MISSING_TE 345 struct timer_list te_timer; 346 #endif 347 348 unsigned long cache_req_pck; 349 unsigned long cache_clk_freq; 350 struct dss_pll_clock_info cache_cinfo; 351 352 u32 errors; 353 spinlock_t errors_lock; 354 #ifdef DSI_PERF_MEASURE 355 ktime_t perf_setup_time; 356 ktime_t perf_start_time; 357 #endif 358 int debug_read; 359 int debug_write; 360 361 #ifdef CONFIG_FB_OMAP2_DSS_COLLECT_IRQ_STATS 362 spinlock_t irq_stats_lock; 363 struct dsi_irq_stats irq_stats; 364 #endif 365 366 unsigned num_lanes_supported; 367 unsigned line_buffer_size; 368 369 struct dsi_lane_config lanes[DSI_MAX_NR_LANES]; 370 unsigned num_lanes_used; 371 372 unsigned scp_clk_refcount; 373 374 struct dss_lcd_mgr_config mgr_config; 375 struct omap_video_timings timings; 376 enum omap_dss_dsi_pixel_format pix_fmt; 377 enum omap_dss_dsi_mode mode; 378 struct omap_dss_dsi_videomode_timings vm_timings; 379 380 struct omap_dss_device output; 381 }; 382 383 struct dsi_packet_sent_handler_data { 384 struct platform_device *dsidev; 385 struct completion *completion; 386 }; 387 388 struct dsi_module_id_data { 389 u32 address; 390 int id; 391 }; 392 393 static const struct of_device_id dsi_of_match[]; 394 395 #ifdef DSI_PERF_MEASURE 396 static bool dsi_perf; 397 module_param(dsi_perf, bool, 0644); 398 #endif 399 400 static inline struct dsi_data *dsi_get_dsidrv_data(struct platform_device *dsidev) 401 { 402 return platform_get_drvdata(dsidev); 403 } 404 405 static inline struct platform_device *dsi_get_dsidev_from_dssdev(struct omap_dss_device *dssdev) 406 { 407 return to_platform_device(dssdev->dev); 408 } 409 410 static struct platform_device *dsi_get_dsidev_from_id(int module) 411 { 412 struct omap_dss_device *out; 413 enum omap_dss_output_id id; 414 415 switch (module) { 416 case 0: 417 id = OMAP_DSS_OUTPUT_DSI1; 418 break; 419 case 1: 420 id = OMAP_DSS_OUTPUT_DSI2; 421 break; 422 default: 423 return NULL; 424 } 425 426 out = omap_dss_get_output(id); 427 428 return out ? to_platform_device(out->dev) : NULL; 429 } 430 431 static inline void dsi_write_reg(struct platform_device *dsidev, 432 const struct dsi_reg idx, u32 val) 433 { 434 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 435 void __iomem *base; 436 437 switch(idx.module) { 438 case DSI_PROTO: base = dsi->proto_base; break; 439 case DSI_PHY: base = dsi->phy_base; break; 440 case DSI_PLL: base = dsi->pll_base; break; 441 default: return; 442 } 443 444 __raw_writel(val, base + idx.idx); 445 } 446 447 static inline u32 dsi_read_reg(struct platform_device *dsidev, 448 const struct dsi_reg idx) 449 { 450 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 451 void __iomem *base; 452 453 switch(idx.module) { 454 case DSI_PROTO: base = dsi->proto_base; break; 455 case DSI_PHY: base = dsi->phy_base; break; 456 case DSI_PLL: base = dsi->pll_base; break; 457 default: return 0; 458 } 459 460 return __raw_readl(base + idx.idx); 461 } 462 463 static void dsi_bus_lock(struct omap_dss_device *dssdev) 464 { 465 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 466 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 467 468 down(&dsi->bus_lock); 469 } 470 471 static void dsi_bus_unlock(struct omap_dss_device *dssdev) 472 { 473 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 474 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 475 476 up(&dsi->bus_lock); 477 } 478 479 static bool dsi_bus_is_locked(struct platform_device *dsidev) 480 { 481 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 482 483 return dsi->bus_lock.count == 0; 484 } 485 486 static void dsi_completion_handler(void *data, u32 mask) 487 { 488 complete((struct completion *)data); 489 } 490 491 static inline int wait_for_bit_change(struct platform_device *dsidev, 492 const struct dsi_reg idx, int bitnum, int value) 493 { 494 unsigned long timeout; 495 ktime_t wait; 496 int t; 497 498 /* first busyloop to see if the bit changes right away */ 499 t = 100; 500 while (t-- > 0) { 501 if (REG_GET(dsidev, idx, bitnum, bitnum) == value) 502 return value; 503 } 504 505 /* then loop for 500ms, sleeping for 1ms in between */ 506 timeout = jiffies + msecs_to_jiffies(500); 507 while (time_before(jiffies, timeout)) { 508 if (REG_GET(dsidev, idx, bitnum, bitnum) == value) 509 return value; 510 511 wait = ns_to_ktime(1000 * 1000); 512 set_current_state(TASK_UNINTERRUPTIBLE); 513 schedule_hrtimeout(&wait, HRTIMER_MODE_REL); 514 } 515 516 return !value; 517 } 518 519 u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt) 520 { 521 switch (fmt) { 522 case OMAP_DSS_DSI_FMT_RGB888: 523 case OMAP_DSS_DSI_FMT_RGB666: 524 return 24; 525 case OMAP_DSS_DSI_FMT_RGB666_PACKED: 526 return 18; 527 case OMAP_DSS_DSI_FMT_RGB565: 528 return 16; 529 default: 530 BUG(); 531 return 0; 532 } 533 } 534 535 #ifdef DSI_PERF_MEASURE 536 static void dsi_perf_mark_setup(struct platform_device *dsidev) 537 { 538 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 539 dsi->perf_setup_time = ktime_get(); 540 } 541 542 static void dsi_perf_mark_start(struct platform_device *dsidev) 543 { 544 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 545 dsi->perf_start_time = ktime_get(); 546 } 547 548 static void dsi_perf_show(struct platform_device *dsidev, const char *name) 549 { 550 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 551 ktime_t t, setup_time, trans_time; 552 u32 total_bytes; 553 u32 setup_us, trans_us, total_us; 554 555 if (!dsi_perf) 556 return; 557 558 t = ktime_get(); 559 560 setup_time = ktime_sub(dsi->perf_start_time, dsi->perf_setup_time); 561 setup_us = (u32)ktime_to_us(setup_time); 562 if (setup_us == 0) 563 setup_us = 1; 564 565 trans_time = ktime_sub(t, dsi->perf_start_time); 566 trans_us = (u32)ktime_to_us(trans_time); 567 if (trans_us == 0) 568 trans_us = 1; 569 570 total_us = setup_us + trans_us; 571 572 total_bytes = dsi->update_bytes; 573 574 printk(KERN_INFO "DSI(%s): %u us + %u us = %u us (%uHz), " 575 "%u bytes, %u kbytes/sec\n", 576 name, 577 setup_us, 578 trans_us, 579 total_us, 580 1000*1000 / total_us, 581 total_bytes, 582 total_bytes * 1000 / total_us); 583 } 584 #else 585 static inline void dsi_perf_mark_setup(struct platform_device *dsidev) 586 { 587 } 588 589 static inline void dsi_perf_mark_start(struct platform_device *dsidev) 590 { 591 } 592 593 static inline void dsi_perf_show(struct platform_device *dsidev, 594 const char *name) 595 { 596 } 597 #endif 598 599 static int verbose_irq; 600 601 static void print_irq_status(u32 status) 602 { 603 if (status == 0) 604 return; 605 606 if (!verbose_irq && (status & ~DSI_IRQ_CHANNEL_MASK) == 0) 607 return; 608 609 #define PIS(x) (status & DSI_IRQ_##x) ? (#x " ") : "" 610 611 pr_debug("DSI IRQ: 0x%x: %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", 612 status, 613 verbose_irq ? PIS(VC0) : "", 614 verbose_irq ? PIS(VC1) : "", 615 verbose_irq ? PIS(VC2) : "", 616 verbose_irq ? PIS(VC3) : "", 617 PIS(WAKEUP), 618 PIS(RESYNC), 619 PIS(PLL_LOCK), 620 PIS(PLL_UNLOCK), 621 PIS(PLL_RECALL), 622 PIS(COMPLEXIO_ERR), 623 PIS(HS_TX_TIMEOUT), 624 PIS(LP_RX_TIMEOUT), 625 PIS(TE_TRIGGER), 626 PIS(ACK_TRIGGER), 627 PIS(SYNC_LOST), 628 PIS(LDO_POWER_GOOD), 629 PIS(TA_TIMEOUT)); 630 #undef PIS 631 } 632 633 static void print_irq_status_vc(int channel, u32 status) 634 { 635 if (status == 0) 636 return; 637 638 if (!verbose_irq && (status & ~DSI_VC_IRQ_PACKET_SENT) == 0) 639 return; 640 641 #define PIS(x) (status & DSI_VC_IRQ_##x) ? (#x " ") : "" 642 643 pr_debug("DSI VC(%d) IRQ 0x%x: %s%s%s%s%s%s%s%s%s\n", 644 channel, 645 status, 646 PIS(CS), 647 PIS(ECC_CORR), 648 PIS(ECC_NO_CORR), 649 verbose_irq ? PIS(PACKET_SENT) : "", 650 PIS(BTA), 651 PIS(FIFO_TX_OVF), 652 PIS(FIFO_RX_OVF), 653 PIS(FIFO_TX_UDF), 654 PIS(PP_BUSY_CHANGE)); 655 #undef PIS 656 } 657 658 static void print_irq_status_cio(u32 status) 659 { 660 if (status == 0) 661 return; 662 663 #define PIS(x) (status & DSI_CIO_IRQ_##x) ? (#x " ") : "" 664 665 pr_debug("DSI CIO IRQ 0x%x: %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", 666 status, 667 PIS(ERRSYNCESC1), 668 PIS(ERRSYNCESC2), 669 PIS(ERRSYNCESC3), 670 PIS(ERRESC1), 671 PIS(ERRESC2), 672 PIS(ERRESC3), 673 PIS(ERRCONTROL1), 674 PIS(ERRCONTROL2), 675 PIS(ERRCONTROL3), 676 PIS(STATEULPS1), 677 PIS(STATEULPS2), 678 PIS(STATEULPS3), 679 PIS(ERRCONTENTIONLP0_1), 680 PIS(ERRCONTENTIONLP1_1), 681 PIS(ERRCONTENTIONLP0_2), 682 PIS(ERRCONTENTIONLP1_2), 683 PIS(ERRCONTENTIONLP0_3), 684 PIS(ERRCONTENTIONLP1_3), 685 PIS(ULPSACTIVENOT_ALL0), 686 PIS(ULPSACTIVENOT_ALL1)); 687 #undef PIS 688 } 689 690 #ifdef CONFIG_FB_OMAP2_DSS_COLLECT_IRQ_STATS 691 static void dsi_collect_irq_stats(struct platform_device *dsidev, u32 irqstatus, 692 u32 *vcstatus, u32 ciostatus) 693 { 694 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 695 int i; 696 697 spin_lock(&dsi->irq_stats_lock); 698 699 dsi->irq_stats.irq_count++; 700 dss_collect_irq_stats(irqstatus, dsi->irq_stats.dsi_irqs); 701 702 for (i = 0; i < 4; ++i) 703 dss_collect_irq_stats(vcstatus[i], dsi->irq_stats.vc_irqs[i]); 704 705 dss_collect_irq_stats(ciostatus, dsi->irq_stats.cio_irqs); 706 707 spin_unlock(&dsi->irq_stats_lock); 708 } 709 #else 710 #define dsi_collect_irq_stats(dsidev, irqstatus, vcstatus, ciostatus) 711 #endif 712 713 static int debug_irq; 714 715 static void dsi_handle_irq_errors(struct platform_device *dsidev, u32 irqstatus, 716 u32 *vcstatus, u32 ciostatus) 717 { 718 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 719 int i; 720 721 if (irqstatus & DSI_IRQ_ERROR_MASK) { 722 DSSERR("DSI error, irqstatus %x\n", irqstatus); 723 print_irq_status(irqstatus); 724 spin_lock(&dsi->errors_lock); 725 dsi->errors |= irqstatus & DSI_IRQ_ERROR_MASK; 726 spin_unlock(&dsi->errors_lock); 727 } else if (debug_irq) { 728 print_irq_status(irqstatus); 729 } 730 731 for (i = 0; i < 4; ++i) { 732 if (vcstatus[i] & DSI_VC_IRQ_ERROR_MASK) { 733 DSSERR("DSI VC(%d) error, vc irqstatus %x\n", 734 i, vcstatus[i]); 735 print_irq_status_vc(i, vcstatus[i]); 736 } else if (debug_irq) { 737 print_irq_status_vc(i, vcstatus[i]); 738 } 739 } 740 741 if (ciostatus & DSI_CIO_IRQ_ERROR_MASK) { 742 DSSERR("DSI CIO error, cio irqstatus %x\n", ciostatus); 743 print_irq_status_cio(ciostatus); 744 } else if (debug_irq) { 745 print_irq_status_cio(ciostatus); 746 } 747 } 748 749 static void dsi_call_isrs(struct dsi_isr_data *isr_array, 750 unsigned isr_array_size, u32 irqstatus) 751 { 752 struct dsi_isr_data *isr_data; 753 int i; 754 755 for (i = 0; i < isr_array_size; i++) { 756 isr_data = &isr_array[i]; 757 if (isr_data->isr && isr_data->mask & irqstatus) 758 isr_data->isr(isr_data->arg, irqstatus); 759 } 760 } 761 762 static void dsi_handle_isrs(struct dsi_isr_tables *isr_tables, 763 u32 irqstatus, u32 *vcstatus, u32 ciostatus) 764 { 765 int i; 766 767 dsi_call_isrs(isr_tables->isr_table, 768 ARRAY_SIZE(isr_tables->isr_table), 769 irqstatus); 770 771 for (i = 0; i < 4; ++i) { 772 if (vcstatus[i] == 0) 773 continue; 774 dsi_call_isrs(isr_tables->isr_table_vc[i], 775 ARRAY_SIZE(isr_tables->isr_table_vc[i]), 776 vcstatus[i]); 777 } 778 779 if (ciostatus != 0) 780 dsi_call_isrs(isr_tables->isr_table_cio, 781 ARRAY_SIZE(isr_tables->isr_table_cio), 782 ciostatus); 783 } 784 785 static irqreturn_t omap_dsi_irq_handler(int irq, void *arg) 786 { 787 struct platform_device *dsidev; 788 struct dsi_data *dsi; 789 u32 irqstatus, vcstatus[4], ciostatus; 790 int i; 791 792 dsidev = (struct platform_device *) arg; 793 dsi = dsi_get_dsidrv_data(dsidev); 794 795 if (!dsi->is_enabled) 796 return IRQ_NONE; 797 798 spin_lock(&dsi->irq_lock); 799 800 irqstatus = dsi_read_reg(dsidev, DSI_IRQSTATUS); 801 802 /* IRQ is not for us */ 803 if (!irqstatus) { 804 spin_unlock(&dsi->irq_lock); 805 return IRQ_NONE; 806 } 807 808 dsi_write_reg(dsidev, DSI_IRQSTATUS, irqstatus & ~DSI_IRQ_CHANNEL_MASK); 809 /* flush posted write */ 810 dsi_read_reg(dsidev, DSI_IRQSTATUS); 811 812 for (i = 0; i < 4; ++i) { 813 if ((irqstatus & (1 << i)) == 0) { 814 vcstatus[i] = 0; 815 continue; 816 } 817 818 vcstatus[i] = dsi_read_reg(dsidev, DSI_VC_IRQSTATUS(i)); 819 820 dsi_write_reg(dsidev, DSI_VC_IRQSTATUS(i), vcstatus[i]); 821 /* flush posted write */ 822 dsi_read_reg(dsidev, DSI_VC_IRQSTATUS(i)); 823 } 824 825 if (irqstatus & DSI_IRQ_COMPLEXIO_ERR) { 826 ciostatus = dsi_read_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS); 827 828 dsi_write_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS, ciostatus); 829 /* flush posted write */ 830 dsi_read_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS); 831 } else { 832 ciostatus = 0; 833 } 834 835 #ifdef DSI_CATCH_MISSING_TE 836 if (irqstatus & DSI_IRQ_TE_TRIGGER) 837 del_timer(&dsi->te_timer); 838 #endif 839 840 /* make a copy and unlock, so that isrs can unregister 841 * themselves */ 842 memcpy(&dsi->isr_tables_copy, &dsi->isr_tables, 843 sizeof(dsi->isr_tables)); 844 845 spin_unlock(&dsi->irq_lock); 846 847 dsi_handle_isrs(&dsi->isr_tables_copy, irqstatus, vcstatus, ciostatus); 848 849 dsi_handle_irq_errors(dsidev, irqstatus, vcstatus, ciostatus); 850 851 dsi_collect_irq_stats(dsidev, irqstatus, vcstatus, ciostatus); 852 853 return IRQ_HANDLED; 854 } 855 856 /* dsi->irq_lock has to be locked by the caller */ 857 static void _omap_dsi_configure_irqs(struct platform_device *dsidev, 858 struct dsi_isr_data *isr_array, 859 unsigned isr_array_size, u32 default_mask, 860 const struct dsi_reg enable_reg, 861 const struct dsi_reg status_reg) 862 { 863 struct dsi_isr_data *isr_data; 864 u32 mask; 865 u32 old_mask; 866 int i; 867 868 mask = default_mask; 869 870 for (i = 0; i < isr_array_size; i++) { 871 isr_data = &isr_array[i]; 872 873 if (isr_data->isr == NULL) 874 continue; 875 876 mask |= isr_data->mask; 877 } 878 879 old_mask = dsi_read_reg(dsidev, enable_reg); 880 /* clear the irqstatus for newly enabled irqs */ 881 dsi_write_reg(dsidev, status_reg, (mask ^ old_mask) & mask); 882 dsi_write_reg(dsidev, enable_reg, mask); 883 884 /* flush posted writes */ 885 dsi_read_reg(dsidev, enable_reg); 886 dsi_read_reg(dsidev, status_reg); 887 } 888 889 /* dsi->irq_lock has to be locked by the caller */ 890 static void _omap_dsi_set_irqs(struct platform_device *dsidev) 891 { 892 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 893 u32 mask = DSI_IRQ_ERROR_MASK; 894 #ifdef DSI_CATCH_MISSING_TE 895 mask |= DSI_IRQ_TE_TRIGGER; 896 #endif 897 _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table, 898 ARRAY_SIZE(dsi->isr_tables.isr_table), mask, 899 DSI_IRQENABLE, DSI_IRQSTATUS); 900 } 901 902 /* dsi->irq_lock has to be locked by the caller */ 903 static void _omap_dsi_set_irqs_vc(struct platform_device *dsidev, int vc) 904 { 905 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 906 907 _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table_vc[vc], 908 ARRAY_SIZE(dsi->isr_tables.isr_table_vc[vc]), 909 DSI_VC_IRQ_ERROR_MASK, 910 DSI_VC_IRQENABLE(vc), DSI_VC_IRQSTATUS(vc)); 911 } 912 913 /* dsi->irq_lock has to be locked by the caller */ 914 static void _omap_dsi_set_irqs_cio(struct platform_device *dsidev) 915 { 916 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 917 918 _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table_cio, 919 ARRAY_SIZE(dsi->isr_tables.isr_table_cio), 920 DSI_CIO_IRQ_ERROR_MASK, 921 DSI_COMPLEXIO_IRQ_ENABLE, DSI_COMPLEXIO_IRQ_STATUS); 922 } 923 924 static void _dsi_initialize_irq(struct platform_device *dsidev) 925 { 926 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 927 unsigned long flags; 928 int vc; 929 930 spin_lock_irqsave(&dsi->irq_lock, flags); 931 932 memset(&dsi->isr_tables, 0, sizeof(dsi->isr_tables)); 933 934 _omap_dsi_set_irqs(dsidev); 935 for (vc = 0; vc < 4; ++vc) 936 _omap_dsi_set_irqs_vc(dsidev, vc); 937 _omap_dsi_set_irqs_cio(dsidev); 938 939 spin_unlock_irqrestore(&dsi->irq_lock, flags); 940 } 941 942 static int _dsi_register_isr(omap_dsi_isr_t isr, void *arg, u32 mask, 943 struct dsi_isr_data *isr_array, unsigned isr_array_size) 944 { 945 struct dsi_isr_data *isr_data; 946 int free_idx; 947 int i; 948 949 BUG_ON(isr == NULL); 950 951 /* check for duplicate entry and find a free slot */ 952 free_idx = -1; 953 for (i = 0; i < isr_array_size; i++) { 954 isr_data = &isr_array[i]; 955 956 if (isr_data->isr == isr && isr_data->arg == arg && 957 isr_data->mask == mask) { 958 return -EINVAL; 959 } 960 961 if (isr_data->isr == NULL && free_idx == -1) 962 free_idx = i; 963 } 964 965 if (free_idx == -1) 966 return -EBUSY; 967 968 isr_data = &isr_array[free_idx]; 969 isr_data->isr = isr; 970 isr_data->arg = arg; 971 isr_data->mask = mask; 972 973 return 0; 974 } 975 976 static int _dsi_unregister_isr(omap_dsi_isr_t isr, void *arg, u32 mask, 977 struct dsi_isr_data *isr_array, unsigned isr_array_size) 978 { 979 struct dsi_isr_data *isr_data; 980 int i; 981 982 for (i = 0; i < isr_array_size; i++) { 983 isr_data = &isr_array[i]; 984 if (isr_data->isr != isr || isr_data->arg != arg || 985 isr_data->mask != mask) 986 continue; 987 988 isr_data->isr = NULL; 989 isr_data->arg = NULL; 990 isr_data->mask = 0; 991 992 return 0; 993 } 994 995 return -EINVAL; 996 } 997 998 static int dsi_register_isr(struct platform_device *dsidev, omap_dsi_isr_t isr, 999 void *arg, u32 mask) 1000 { 1001 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1002 unsigned long flags; 1003 int r; 1004 1005 spin_lock_irqsave(&dsi->irq_lock, flags); 1006 1007 r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table, 1008 ARRAY_SIZE(dsi->isr_tables.isr_table)); 1009 1010 if (r == 0) 1011 _omap_dsi_set_irqs(dsidev); 1012 1013 spin_unlock_irqrestore(&dsi->irq_lock, flags); 1014 1015 return r; 1016 } 1017 1018 static int dsi_unregister_isr(struct platform_device *dsidev, 1019 omap_dsi_isr_t isr, void *arg, u32 mask) 1020 { 1021 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1022 unsigned long flags; 1023 int r; 1024 1025 spin_lock_irqsave(&dsi->irq_lock, flags); 1026 1027 r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table, 1028 ARRAY_SIZE(dsi->isr_tables.isr_table)); 1029 1030 if (r == 0) 1031 _omap_dsi_set_irqs(dsidev); 1032 1033 spin_unlock_irqrestore(&dsi->irq_lock, flags); 1034 1035 return r; 1036 } 1037 1038 static int dsi_register_isr_vc(struct platform_device *dsidev, int channel, 1039 omap_dsi_isr_t isr, void *arg, u32 mask) 1040 { 1041 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1042 unsigned long flags; 1043 int r; 1044 1045 spin_lock_irqsave(&dsi->irq_lock, flags); 1046 1047 r = _dsi_register_isr(isr, arg, mask, 1048 dsi->isr_tables.isr_table_vc[channel], 1049 ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel])); 1050 1051 if (r == 0) 1052 _omap_dsi_set_irqs_vc(dsidev, channel); 1053 1054 spin_unlock_irqrestore(&dsi->irq_lock, flags); 1055 1056 return r; 1057 } 1058 1059 static int dsi_unregister_isr_vc(struct platform_device *dsidev, int channel, 1060 omap_dsi_isr_t isr, void *arg, u32 mask) 1061 { 1062 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1063 unsigned long flags; 1064 int r; 1065 1066 spin_lock_irqsave(&dsi->irq_lock, flags); 1067 1068 r = _dsi_unregister_isr(isr, arg, mask, 1069 dsi->isr_tables.isr_table_vc[channel], 1070 ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel])); 1071 1072 if (r == 0) 1073 _omap_dsi_set_irqs_vc(dsidev, channel); 1074 1075 spin_unlock_irqrestore(&dsi->irq_lock, flags); 1076 1077 return r; 1078 } 1079 1080 static int dsi_register_isr_cio(struct platform_device *dsidev, 1081 omap_dsi_isr_t isr, void *arg, u32 mask) 1082 { 1083 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1084 unsigned long flags; 1085 int r; 1086 1087 spin_lock_irqsave(&dsi->irq_lock, flags); 1088 1089 r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio, 1090 ARRAY_SIZE(dsi->isr_tables.isr_table_cio)); 1091 1092 if (r == 0) 1093 _omap_dsi_set_irqs_cio(dsidev); 1094 1095 spin_unlock_irqrestore(&dsi->irq_lock, flags); 1096 1097 return r; 1098 } 1099 1100 static int dsi_unregister_isr_cio(struct platform_device *dsidev, 1101 omap_dsi_isr_t isr, void *arg, u32 mask) 1102 { 1103 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1104 unsigned long flags; 1105 int r; 1106 1107 spin_lock_irqsave(&dsi->irq_lock, flags); 1108 1109 r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio, 1110 ARRAY_SIZE(dsi->isr_tables.isr_table_cio)); 1111 1112 if (r == 0) 1113 _omap_dsi_set_irqs_cio(dsidev); 1114 1115 spin_unlock_irqrestore(&dsi->irq_lock, flags); 1116 1117 return r; 1118 } 1119 1120 static u32 dsi_get_errors(struct platform_device *dsidev) 1121 { 1122 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1123 unsigned long flags; 1124 u32 e; 1125 spin_lock_irqsave(&dsi->errors_lock, flags); 1126 e = dsi->errors; 1127 dsi->errors = 0; 1128 spin_unlock_irqrestore(&dsi->errors_lock, flags); 1129 return e; 1130 } 1131 1132 static int dsi_runtime_get(struct platform_device *dsidev) 1133 { 1134 int r; 1135 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1136 1137 DSSDBG("dsi_runtime_get\n"); 1138 1139 r = pm_runtime_get_sync(&dsi->pdev->dev); 1140 if (WARN_ON(r < 0)) { 1141 pm_runtime_put_sync(&dsi->pdev->dev); 1142 return r; 1143 } 1144 return 0; 1145 } 1146 1147 static void dsi_runtime_put(struct platform_device *dsidev) 1148 { 1149 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1150 int r; 1151 1152 DSSDBG("dsi_runtime_put\n"); 1153 1154 r = pm_runtime_put_sync(&dsi->pdev->dev); 1155 WARN_ON(r < 0 && r != -ENOSYS); 1156 } 1157 1158 static int dsi_regulator_init(struct platform_device *dsidev) 1159 { 1160 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1161 struct regulator *vdds_dsi; 1162 1163 if (dsi->vdds_dsi_reg != NULL) 1164 return 0; 1165 1166 vdds_dsi = devm_regulator_get(&dsi->pdev->dev, "vdd"); 1167 1168 if (IS_ERR(vdds_dsi)) { 1169 if (PTR_ERR(vdds_dsi) != -EPROBE_DEFER) 1170 DSSERR("can't get DSI VDD regulator\n"); 1171 return PTR_ERR(vdds_dsi); 1172 } 1173 1174 dsi->vdds_dsi_reg = vdds_dsi; 1175 1176 return 0; 1177 } 1178 1179 static void _dsi_print_reset_status(struct platform_device *dsidev) 1180 { 1181 int b0, b1, b2; 1182 1183 /* A dummy read using the SCP interface to any DSIPHY register is 1184 * required after DSIPHY reset to complete the reset of the DSI complex 1185 * I/O. */ 1186 dsi_read_reg(dsidev, DSI_DSIPHY_CFG5); 1187 1188 if (dss_has_feature(FEAT_DSI_REVERSE_TXCLKESC)) { 1189 b0 = 28; 1190 b1 = 27; 1191 b2 = 26; 1192 } else { 1193 b0 = 24; 1194 b1 = 25; 1195 b2 = 26; 1196 } 1197 1198 #define DSI_FLD_GET(fld, start, end)\ 1199 FLD_GET(dsi_read_reg(dsidev, DSI_##fld), start, end) 1200 1201 pr_debug("DSI resets: PLL (%d) CIO (%d) PHY (%x%x%x, %d, %d, %d)\n", 1202 DSI_FLD_GET(PLL_STATUS, 0, 0), 1203 DSI_FLD_GET(COMPLEXIO_CFG1, 29, 29), 1204 DSI_FLD_GET(DSIPHY_CFG5, b0, b0), 1205 DSI_FLD_GET(DSIPHY_CFG5, b1, b1), 1206 DSI_FLD_GET(DSIPHY_CFG5, b2, b2), 1207 DSI_FLD_GET(DSIPHY_CFG5, 29, 29), 1208 DSI_FLD_GET(DSIPHY_CFG5, 30, 30), 1209 DSI_FLD_GET(DSIPHY_CFG5, 31, 31)); 1210 1211 #undef DSI_FLD_GET 1212 } 1213 1214 static inline int dsi_if_enable(struct platform_device *dsidev, bool enable) 1215 { 1216 DSSDBG("dsi_if_enable(%d)\n", enable); 1217 1218 enable = enable ? 1 : 0; 1219 REG_FLD_MOD(dsidev, DSI_CTRL, enable, 0, 0); /* IF_EN */ 1220 1221 if (wait_for_bit_change(dsidev, DSI_CTRL, 0, enable) != enable) { 1222 DSSERR("Failed to set dsi_if_enable to %d\n", enable); 1223 return -EIO; 1224 } 1225 1226 return 0; 1227 } 1228 1229 static unsigned long dsi_get_pll_hsdiv_dispc_rate(struct platform_device *dsidev) 1230 { 1231 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1232 1233 return dsi->pll.cinfo.clkout[HSDIV_DISPC]; 1234 } 1235 1236 static unsigned long dsi_get_pll_hsdiv_dsi_rate(struct platform_device *dsidev) 1237 { 1238 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1239 1240 return dsi->pll.cinfo.clkout[HSDIV_DSI]; 1241 } 1242 1243 static unsigned long dsi_get_txbyteclkhs(struct platform_device *dsidev) 1244 { 1245 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1246 1247 return dsi->pll.cinfo.clkdco / 16; 1248 } 1249 1250 static unsigned long dsi_fclk_rate(struct platform_device *dsidev) 1251 { 1252 unsigned long r; 1253 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1254 1255 if (dss_get_dsi_clk_source(dsi->module_id) == OMAP_DSS_CLK_SRC_FCK) { 1256 /* DSI FCLK source is DSS_CLK_FCK */ 1257 r = clk_get_rate(dsi->dss_clk); 1258 } else { 1259 /* DSI FCLK source is dsi_pll_hsdiv_dsi_clk */ 1260 r = dsi_get_pll_hsdiv_dsi_rate(dsidev); 1261 } 1262 1263 return r; 1264 } 1265 1266 static int dsi_lp_clock_calc(unsigned long dsi_fclk, 1267 unsigned long lp_clk_min, unsigned long lp_clk_max, 1268 struct dsi_lp_clock_info *lp_cinfo) 1269 { 1270 unsigned lp_clk_div; 1271 unsigned long lp_clk; 1272 1273 lp_clk_div = DIV_ROUND_UP(dsi_fclk, lp_clk_max * 2); 1274 lp_clk = dsi_fclk / 2 / lp_clk_div; 1275 1276 if (lp_clk < lp_clk_min || lp_clk > lp_clk_max) 1277 return -EINVAL; 1278 1279 lp_cinfo->lp_clk_div = lp_clk_div; 1280 lp_cinfo->lp_clk = lp_clk; 1281 1282 return 0; 1283 } 1284 1285 static int dsi_set_lp_clk_divisor(struct platform_device *dsidev) 1286 { 1287 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1288 unsigned long dsi_fclk; 1289 unsigned lp_clk_div; 1290 unsigned long lp_clk; 1291 unsigned lpdiv_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_LPDIV); 1292 1293 1294 lp_clk_div = dsi->user_lp_cinfo.lp_clk_div; 1295 1296 if (lp_clk_div == 0 || lp_clk_div > lpdiv_max) 1297 return -EINVAL; 1298 1299 dsi_fclk = dsi_fclk_rate(dsidev); 1300 1301 lp_clk = dsi_fclk / 2 / lp_clk_div; 1302 1303 DSSDBG("LP_CLK_DIV %u, LP_CLK %lu\n", lp_clk_div, lp_clk); 1304 dsi->current_lp_cinfo.lp_clk = lp_clk; 1305 dsi->current_lp_cinfo.lp_clk_div = lp_clk_div; 1306 1307 /* LP_CLK_DIVISOR */ 1308 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, lp_clk_div, 12, 0); 1309 1310 /* LP_RX_SYNCHRO_ENABLE */ 1311 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, dsi_fclk > 30000000 ? 1 : 0, 21, 21); 1312 1313 return 0; 1314 } 1315 1316 static void dsi_enable_scp_clk(struct platform_device *dsidev) 1317 { 1318 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1319 1320 if (dsi->scp_clk_refcount++ == 0) 1321 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 14, 14); /* CIO_CLK_ICG */ 1322 } 1323 1324 static void dsi_disable_scp_clk(struct platform_device *dsidev) 1325 { 1326 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1327 1328 WARN_ON(dsi->scp_clk_refcount == 0); 1329 if (--dsi->scp_clk_refcount == 0) 1330 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 14, 14); /* CIO_CLK_ICG */ 1331 } 1332 1333 enum dsi_pll_power_state { 1334 DSI_PLL_POWER_OFF = 0x0, 1335 DSI_PLL_POWER_ON_HSCLK = 0x1, 1336 DSI_PLL_POWER_ON_ALL = 0x2, 1337 DSI_PLL_POWER_ON_DIV = 0x3, 1338 }; 1339 1340 static int dsi_pll_power(struct platform_device *dsidev, 1341 enum dsi_pll_power_state state) 1342 { 1343 int t = 0; 1344 1345 /* DSI-PLL power command 0x3 is not working */ 1346 if (dss_has_feature(FEAT_DSI_PLL_PWR_BUG) && 1347 state == DSI_PLL_POWER_ON_DIV) 1348 state = DSI_PLL_POWER_ON_ALL; 1349 1350 /* PLL_PWR_CMD */ 1351 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, state, 31, 30); 1352 1353 /* PLL_PWR_STATUS */ 1354 while (FLD_GET(dsi_read_reg(dsidev, DSI_CLK_CTRL), 29, 28) != state) { 1355 if (++t > 1000) { 1356 DSSERR("Failed to set DSI PLL power mode to %d\n", 1357 state); 1358 return -ENODEV; 1359 } 1360 udelay(1); 1361 } 1362 1363 return 0; 1364 } 1365 1366 1367 static void dsi_pll_calc_dsi_fck(struct dss_pll_clock_info *cinfo) 1368 { 1369 unsigned long max_dsi_fck; 1370 1371 max_dsi_fck = dss_feat_get_param_max(FEAT_PARAM_DSI_FCK); 1372 1373 cinfo->mX[HSDIV_DSI] = DIV_ROUND_UP(cinfo->clkdco, max_dsi_fck); 1374 cinfo->clkout[HSDIV_DSI] = cinfo->clkdco / cinfo->mX[HSDIV_DSI]; 1375 } 1376 1377 static int dsi_pll_enable(struct dss_pll *pll) 1378 { 1379 struct dsi_data *dsi = container_of(pll, struct dsi_data, pll); 1380 struct platform_device *dsidev = dsi->pdev; 1381 int r = 0; 1382 1383 DSSDBG("PLL init\n"); 1384 1385 r = dsi_regulator_init(dsidev); 1386 if (r) 1387 return r; 1388 1389 r = dsi_runtime_get(dsidev); 1390 if (r) 1391 return r; 1392 1393 /* 1394 * Note: SCP CLK is not required on OMAP3, but it is required on OMAP4. 1395 */ 1396 dsi_enable_scp_clk(dsidev); 1397 1398 if (!dsi->vdds_dsi_enabled) { 1399 r = regulator_enable(dsi->vdds_dsi_reg); 1400 if (r) 1401 goto err0; 1402 dsi->vdds_dsi_enabled = true; 1403 } 1404 1405 /* XXX PLL does not come out of reset without this... */ 1406 dispc_pck_free_enable(1); 1407 1408 if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 0, 1) != 1) { 1409 DSSERR("PLL not coming out of reset.\n"); 1410 r = -ENODEV; 1411 dispc_pck_free_enable(0); 1412 goto err1; 1413 } 1414 1415 /* XXX ... but if left on, we get problems when planes do not 1416 * fill the whole display. No idea about this */ 1417 dispc_pck_free_enable(0); 1418 1419 r = dsi_pll_power(dsidev, DSI_PLL_POWER_ON_ALL); 1420 1421 if (r) 1422 goto err1; 1423 1424 DSSDBG("PLL init done\n"); 1425 1426 return 0; 1427 err1: 1428 if (dsi->vdds_dsi_enabled) { 1429 regulator_disable(dsi->vdds_dsi_reg); 1430 dsi->vdds_dsi_enabled = false; 1431 } 1432 err0: 1433 dsi_disable_scp_clk(dsidev); 1434 dsi_runtime_put(dsidev); 1435 return r; 1436 } 1437 1438 static void dsi_pll_uninit(struct platform_device *dsidev, bool disconnect_lanes) 1439 { 1440 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1441 1442 dsi_pll_power(dsidev, DSI_PLL_POWER_OFF); 1443 if (disconnect_lanes) { 1444 WARN_ON(!dsi->vdds_dsi_enabled); 1445 regulator_disable(dsi->vdds_dsi_reg); 1446 dsi->vdds_dsi_enabled = false; 1447 } 1448 1449 dsi_disable_scp_clk(dsidev); 1450 dsi_runtime_put(dsidev); 1451 1452 DSSDBG("PLL uninit done\n"); 1453 } 1454 1455 static void dsi_pll_disable(struct dss_pll *pll) 1456 { 1457 struct dsi_data *dsi = container_of(pll, struct dsi_data, pll); 1458 struct platform_device *dsidev = dsi->pdev; 1459 1460 dsi_pll_uninit(dsidev, true); 1461 } 1462 1463 static void dsi_dump_dsidev_clocks(struct platform_device *dsidev, 1464 struct seq_file *s) 1465 { 1466 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1467 struct dss_pll_clock_info *cinfo = &dsi->pll.cinfo; 1468 enum omap_dss_clk_source dispc_clk_src, dsi_clk_src; 1469 int dsi_module = dsi->module_id; 1470 struct dss_pll *pll = &dsi->pll; 1471 1472 dispc_clk_src = dss_get_dispc_clk_source(); 1473 dsi_clk_src = dss_get_dsi_clk_source(dsi_module); 1474 1475 if (dsi_runtime_get(dsidev)) 1476 return; 1477 1478 seq_printf(s, "- DSI%d PLL -\n", dsi_module + 1); 1479 1480 seq_printf(s, "dsi pll clkin\t%lu\n", clk_get_rate(pll->clkin)); 1481 1482 seq_printf(s, "Fint\t\t%-16lun %u\n", cinfo->fint, cinfo->n); 1483 1484 seq_printf(s, "CLKIN4DDR\t%-16lum %u\n", 1485 cinfo->clkdco, cinfo->m); 1486 1487 seq_printf(s, "DSI_PLL_HSDIV_DISPC (%s)\t%-16lum_dispc %u\t(%s)\n", 1488 dss_feat_get_clk_source_name(dsi_module == 0 ? 1489 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC : 1490 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC), 1491 cinfo->clkout[HSDIV_DISPC], 1492 cinfo->mX[HSDIV_DISPC], 1493 dispc_clk_src == OMAP_DSS_CLK_SRC_FCK ? 1494 "off" : "on"); 1495 1496 seq_printf(s, "DSI_PLL_HSDIV_DSI (%s)\t%-16lum_dsi %u\t(%s)\n", 1497 dss_feat_get_clk_source_name(dsi_module == 0 ? 1498 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI : 1499 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI), 1500 cinfo->clkout[HSDIV_DSI], 1501 cinfo->mX[HSDIV_DSI], 1502 dsi_clk_src == OMAP_DSS_CLK_SRC_FCK ? 1503 "off" : "on"); 1504 1505 seq_printf(s, "- DSI%d -\n", dsi_module + 1); 1506 1507 seq_printf(s, "dsi fclk source = %s (%s)\n", 1508 dss_get_generic_clk_source_name(dsi_clk_src), 1509 dss_feat_get_clk_source_name(dsi_clk_src)); 1510 1511 seq_printf(s, "DSI_FCLK\t%lu\n", dsi_fclk_rate(dsidev)); 1512 1513 seq_printf(s, "DDR_CLK\t\t%lu\n", 1514 cinfo->clkdco / 4); 1515 1516 seq_printf(s, "TxByteClkHS\t%lu\n", dsi_get_txbyteclkhs(dsidev)); 1517 1518 seq_printf(s, "LP_CLK\t\t%lu\n", dsi->current_lp_cinfo.lp_clk); 1519 1520 dsi_runtime_put(dsidev); 1521 } 1522 1523 void dsi_dump_clocks(struct seq_file *s) 1524 { 1525 struct platform_device *dsidev; 1526 int i; 1527 1528 for (i = 0; i < MAX_NUM_DSI; i++) { 1529 dsidev = dsi_get_dsidev_from_id(i); 1530 if (dsidev) 1531 dsi_dump_dsidev_clocks(dsidev, s); 1532 } 1533 } 1534 1535 #ifdef CONFIG_FB_OMAP2_DSS_COLLECT_IRQ_STATS 1536 static void dsi_dump_dsidev_irqs(struct platform_device *dsidev, 1537 struct seq_file *s) 1538 { 1539 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1540 unsigned long flags; 1541 struct dsi_irq_stats stats; 1542 1543 spin_lock_irqsave(&dsi->irq_stats_lock, flags); 1544 1545 stats = dsi->irq_stats; 1546 memset(&dsi->irq_stats, 0, sizeof(dsi->irq_stats)); 1547 dsi->irq_stats.last_reset = jiffies; 1548 1549 spin_unlock_irqrestore(&dsi->irq_stats_lock, flags); 1550 1551 seq_printf(s, "period %u ms\n", 1552 jiffies_to_msecs(jiffies - stats.last_reset)); 1553 1554 seq_printf(s, "irqs %d\n", stats.irq_count); 1555 #define PIS(x) \ 1556 seq_printf(s, "%-20s %10d\n", #x, stats.dsi_irqs[ffs(DSI_IRQ_##x)-1]) 1557 1558 seq_printf(s, "-- DSI%d interrupts --\n", dsi->module_id + 1); 1559 PIS(VC0); 1560 PIS(VC1); 1561 PIS(VC2); 1562 PIS(VC3); 1563 PIS(WAKEUP); 1564 PIS(RESYNC); 1565 PIS(PLL_LOCK); 1566 PIS(PLL_UNLOCK); 1567 PIS(PLL_RECALL); 1568 PIS(COMPLEXIO_ERR); 1569 PIS(HS_TX_TIMEOUT); 1570 PIS(LP_RX_TIMEOUT); 1571 PIS(TE_TRIGGER); 1572 PIS(ACK_TRIGGER); 1573 PIS(SYNC_LOST); 1574 PIS(LDO_POWER_GOOD); 1575 PIS(TA_TIMEOUT); 1576 #undef PIS 1577 1578 #define PIS(x) \ 1579 seq_printf(s, "%-20s %10d %10d %10d %10d\n", #x, \ 1580 stats.vc_irqs[0][ffs(DSI_VC_IRQ_##x)-1], \ 1581 stats.vc_irqs[1][ffs(DSI_VC_IRQ_##x)-1], \ 1582 stats.vc_irqs[2][ffs(DSI_VC_IRQ_##x)-1], \ 1583 stats.vc_irqs[3][ffs(DSI_VC_IRQ_##x)-1]); 1584 1585 seq_printf(s, "-- VC interrupts --\n"); 1586 PIS(CS); 1587 PIS(ECC_CORR); 1588 PIS(PACKET_SENT); 1589 PIS(FIFO_TX_OVF); 1590 PIS(FIFO_RX_OVF); 1591 PIS(BTA); 1592 PIS(ECC_NO_CORR); 1593 PIS(FIFO_TX_UDF); 1594 PIS(PP_BUSY_CHANGE); 1595 #undef PIS 1596 1597 #define PIS(x) \ 1598 seq_printf(s, "%-20s %10d\n", #x, \ 1599 stats.cio_irqs[ffs(DSI_CIO_IRQ_##x)-1]); 1600 1601 seq_printf(s, "-- CIO interrupts --\n"); 1602 PIS(ERRSYNCESC1); 1603 PIS(ERRSYNCESC2); 1604 PIS(ERRSYNCESC3); 1605 PIS(ERRESC1); 1606 PIS(ERRESC2); 1607 PIS(ERRESC3); 1608 PIS(ERRCONTROL1); 1609 PIS(ERRCONTROL2); 1610 PIS(ERRCONTROL3); 1611 PIS(STATEULPS1); 1612 PIS(STATEULPS2); 1613 PIS(STATEULPS3); 1614 PIS(ERRCONTENTIONLP0_1); 1615 PIS(ERRCONTENTIONLP1_1); 1616 PIS(ERRCONTENTIONLP0_2); 1617 PIS(ERRCONTENTIONLP1_2); 1618 PIS(ERRCONTENTIONLP0_3); 1619 PIS(ERRCONTENTIONLP1_3); 1620 PIS(ULPSACTIVENOT_ALL0); 1621 PIS(ULPSACTIVENOT_ALL1); 1622 #undef PIS 1623 } 1624 1625 static void dsi1_dump_irqs(struct seq_file *s) 1626 { 1627 struct platform_device *dsidev = dsi_get_dsidev_from_id(0); 1628 1629 dsi_dump_dsidev_irqs(dsidev, s); 1630 } 1631 1632 static void dsi2_dump_irqs(struct seq_file *s) 1633 { 1634 struct platform_device *dsidev = dsi_get_dsidev_from_id(1); 1635 1636 dsi_dump_dsidev_irqs(dsidev, s); 1637 } 1638 #endif 1639 1640 static void dsi_dump_dsidev_regs(struct platform_device *dsidev, 1641 struct seq_file *s) 1642 { 1643 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(dsidev, r)) 1644 1645 if (dsi_runtime_get(dsidev)) 1646 return; 1647 dsi_enable_scp_clk(dsidev); 1648 1649 DUMPREG(DSI_REVISION); 1650 DUMPREG(DSI_SYSCONFIG); 1651 DUMPREG(DSI_SYSSTATUS); 1652 DUMPREG(DSI_IRQSTATUS); 1653 DUMPREG(DSI_IRQENABLE); 1654 DUMPREG(DSI_CTRL); 1655 DUMPREG(DSI_COMPLEXIO_CFG1); 1656 DUMPREG(DSI_COMPLEXIO_IRQ_STATUS); 1657 DUMPREG(DSI_COMPLEXIO_IRQ_ENABLE); 1658 DUMPREG(DSI_CLK_CTRL); 1659 DUMPREG(DSI_TIMING1); 1660 DUMPREG(DSI_TIMING2); 1661 DUMPREG(DSI_VM_TIMING1); 1662 DUMPREG(DSI_VM_TIMING2); 1663 DUMPREG(DSI_VM_TIMING3); 1664 DUMPREG(DSI_CLK_TIMING); 1665 DUMPREG(DSI_TX_FIFO_VC_SIZE); 1666 DUMPREG(DSI_RX_FIFO_VC_SIZE); 1667 DUMPREG(DSI_COMPLEXIO_CFG2); 1668 DUMPREG(DSI_RX_FIFO_VC_FULLNESS); 1669 DUMPREG(DSI_VM_TIMING4); 1670 DUMPREG(DSI_TX_FIFO_VC_EMPTINESS); 1671 DUMPREG(DSI_VM_TIMING5); 1672 DUMPREG(DSI_VM_TIMING6); 1673 DUMPREG(DSI_VM_TIMING7); 1674 DUMPREG(DSI_STOPCLK_TIMING); 1675 1676 DUMPREG(DSI_VC_CTRL(0)); 1677 DUMPREG(DSI_VC_TE(0)); 1678 DUMPREG(DSI_VC_LONG_PACKET_HEADER(0)); 1679 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(0)); 1680 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(0)); 1681 DUMPREG(DSI_VC_IRQSTATUS(0)); 1682 DUMPREG(DSI_VC_IRQENABLE(0)); 1683 1684 DUMPREG(DSI_VC_CTRL(1)); 1685 DUMPREG(DSI_VC_TE(1)); 1686 DUMPREG(DSI_VC_LONG_PACKET_HEADER(1)); 1687 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(1)); 1688 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(1)); 1689 DUMPREG(DSI_VC_IRQSTATUS(1)); 1690 DUMPREG(DSI_VC_IRQENABLE(1)); 1691 1692 DUMPREG(DSI_VC_CTRL(2)); 1693 DUMPREG(DSI_VC_TE(2)); 1694 DUMPREG(DSI_VC_LONG_PACKET_HEADER(2)); 1695 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(2)); 1696 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(2)); 1697 DUMPREG(DSI_VC_IRQSTATUS(2)); 1698 DUMPREG(DSI_VC_IRQENABLE(2)); 1699 1700 DUMPREG(DSI_VC_CTRL(3)); 1701 DUMPREG(DSI_VC_TE(3)); 1702 DUMPREG(DSI_VC_LONG_PACKET_HEADER(3)); 1703 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(3)); 1704 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(3)); 1705 DUMPREG(DSI_VC_IRQSTATUS(3)); 1706 DUMPREG(DSI_VC_IRQENABLE(3)); 1707 1708 DUMPREG(DSI_DSIPHY_CFG0); 1709 DUMPREG(DSI_DSIPHY_CFG1); 1710 DUMPREG(DSI_DSIPHY_CFG2); 1711 DUMPREG(DSI_DSIPHY_CFG5); 1712 1713 DUMPREG(DSI_PLL_CONTROL); 1714 DUMPREG(DSI_PLL_STATUS); 1715 DUMPREG(DSI_PLL_GO); 1716 DUMPREG(DSI_PLL_CONFIGURATION1); 1717 DUMPREG(DSI_PLL_CONFIGURATION2); 1718 1719 dsi_disable_scp_clk(dsidev); 1720 dsi_runtime_put(dsidev); 1721 #undef DUMPREG 1722 } 1723 1724 static void dsi1_dump_regs(struct seq_file *s) 1725 { 1726 struct platform_device *dsidev = dsi_get_dsidev_from_id(0); 1727 1728 dsi_dump_dsidev_regs(dsidev, s); 1729 } 1730 1731 static void dsi2_dump_regs(struct seq_file *s) 1732 { 1733 struct platform_device *dsidev = dsi_get_dsidev_from_id(1); 1734 1735 dsi_dump_dsidev_regs(dsidev, s); 1736 } 1737 1738 enum dsi_cio_power_state { 1739 DSI_COMPLEXIO_POWER_OFF = 0x0, 1740 DSI_COMPLEXIO_POWER_ON = 0x1, 1741 DSI_COMPLEXIO_POWER_ULPS = 0x2, 1742 }; 1743 1744 static int dsi_cio_power(struct platform_device *dsidev, 1745 enum dsi_cio_power_state state) 1746 { 1747 int t = 0; 1748 1749 /* PWR_CMD */ 1750 REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG1, state, 28, 27); 1751 1752 /* PWR_STATUS */ 1753 while (FLD_GET(dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1), 1754 26, 25) != state) { 1755 if (++t > 1000) { 1756 DSSERR("failed to set complexio power state to " 1757 "%d\n", state); 1758 return -ENODEV; 1759 } 1760 udelay(1); 1761 } 1762 1763 return 0; 1764 } 1765 1766 static unsigned dsi_get_line_buf_size(struct platform_device *dsidev) 1767 { 1768 int val; 1769 1770 /* line buffer on OMAP3 is 1024 x 24bits */ 1771 /* XXX: for some reason using full buffer size causes 1772 * considerable TX slowdown with update sizes that fill the 1773 * whole buffer */ 1774 if (!dss_has_feature(FEAT_DSI_GNQ)) 1775 return 1023 * 3; 1776 1777 val = REG_GET(dsidev, DSI_GNQ, 14, 12); /* VP1_LINE_BUFFER_SIZE */ 1778 1779 switch (val) { 1780 case 1: 1781 return 512 * 3; /* 512x24 bits */ 1782 case 2: 1783 return 682 * 3; /* 682x24 bits */ 1784 case 3: 1785 return 853 * 3; /* 853x24 bits */ 1786 case 4: 1787 return 1024 * 3; /* 1024x24 bits */ 1788 case 5: 1789 return 1194 * 3; /* 1194x24 bits */ 1790 case 6: 1791 return 1365 * 3; /* 1365x24 bits */ 1792 case 7: 1793 return 1920 * 3; /* 1920x24 bits */ 1794 default: 1795 BUG(); 1796 return 0; 1797 } 1798 } 1799 1800 static int dsi_set_lane_config(struct platform_device *dsidev) 1801 { 1802 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1803 static const u8 offsets[] = { 0, 4, 8, 12, 16 }; 1804 static const enum dsi_lane_function functions[] = { 1805 DSI_LANE_CLK, 1806 DSI_LANE_DATA1, 1807 DSI_LANE_DATA2, 1808 DSI_LANE_DATA3, 1809 DSI_LANE_DATA4, 1810 }; 1811 u32 r; 1812 int i; 1813 1814 r = dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1); 1815 1816 for (i = 0; i < dsi->num_lanes_used; ++i) { 1817 unsigned offset = offsets[i]; 1818 unsigned polarity, lane_number; 1819 unsigned t; 1820 1821 for (t = 0; t < dsi->num_lanes_supported; ++t) 1822 if (dsi->lanes[t].function == functions[i]) 1823 break; 1824 1825 if (t == dsi->num_lanes_supported) 1826 return -EINVAL; 1827 1828 lane_number = t; 1829 polarity = dsi->lanes[t].polarity; 1830 1831 r = FLD_MOD(r, lane_number + 1, offset + 2, offset); 1832 r = FLD_MOD(r, polarity, offset + 3, offset + 3); 1833 } 1834 1835 /* clear the unused lanes */ 1836 for (; i < dsi->num_lanes_supported; ++i) { 1837 unsigned offset = offsets[i]; 1838 1839 r = FLD_MOD(r, 0, offset + 2, offset); 1840 r = FLD_MOD(r, 0, offset + 3, offset + 3); 1841 } 1842 1843 dsi_write_reg(dsidev, DSI_COMPLEXIO_CFG1, r); 1844 1845 return 0; 1846 } 1847 1848 static inline unsigned ns2ddr(struct platform_device *dsidev, unsigned ns) 1849 { 1850 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1851 1852 /* convert time in ns to ddr ticks, rounding up */ 1853 unsigned long ddr_clk = dsi->pll.cinfo.clkdco / 4; 1854 return (ns * (ddr_clk / 1000 / 1000) + 999) / 1000; 1855 } 1856 1857 static inline unsigned ddr2ns(struct platform_device *dsidev, unsigned ddr) 1858 { 1859 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1860 1861 unsigned long ddr_clk = dsi->pll.cinfo.clkdco / 4; 1862 return ddr * 1000 * 1000 / (ddr_clk / 1000); 1863 } 1864 1865 static void dsi_cio_timings(struct platform_device *dsidev) 1866 { 1867 u32 r; 1868 u32 ths_prepare, ths_prepare_ths_zero, ths_trail, ths_exit; 1869 u32 tlpx_half, tclk_trail, tclk_zero; 1870 u32 tclk_prepare; 1871 1872 /* calculate timings */ 1873 1874 /* 1 * DDR_CLK = 2 * UI */ 1875 1876 /* min 40ns + 4*UI max 85ns + 6*UI */ 1877 ths_prepare = ns2ddr(dsidev, 70) + 2; 1878 1879 /* min 145ns + 10*UI */ 1880 ths_prepare_ths_zero = ns2ddr(dsidev, 175) + 2; 1881 1882 /* min max(8*UI, 60ns+4*UI) */ 1883 ths_trail = ns2ddr(dsidev, 60) + 5; 1884 1885 /* min 100ns */ 1886 ths_exit = ns2ddr(dsidev, 145); 1887 1888 /* tlpx min 50n */ 1889 tlpx_half = ns2ddr(dsidev, 25); 1890 1891 /* min 60ns */ 1892 tclk_trail = ns2ddr(dsidev, 60) + 2; 1893 1894 /* min 38ns, max 95ns */ 1895 tclk_prepare = ns2ddr(dsidev, 65); 1896 1897 /* min tclk-prepare + tclk-zero = 300ns */ 1898 tclk_zero = ns2ddr(dsidev, 260); 1899 1900 DSSDBG("ths_prepare %u (%uns), ths_prepare_ths_zero %u (%uns)\n", 1901 ths_prepare, ddr2ns(dsidev, ths_prepare), 1902 ths_prepare_ths_zero, ddr2ns(dsidev, ths_prepare_ths_zero)); 1903 DSSDBG("ths_trail %u (%uns), ths_exit %u (%uns)\n", 1904 ths_trail, ddr2ns(dsidev, ths_trail), 1905 ths_exit, ddr2ns(dsidev, ths_exit)); 1906 1907 DSSDBG("tlpx_half %u (%uns), tclk_trail %u (%uns), " 1908 "tclk_zero %u (%uns)\n", 1909 tlpx_half, ddr2ns(dsidev, tlpx_half), 1910 tclk_trail, ddr2ns(dsidev, tclk_trail), 1911 tclk_zero, ddr2ns(dsidev, tclk_zero)); 1912 DSSDBG("tclk_prepare %u (%uns)\n", 1913 tclk_prepare, ddr2ns(dsidev, tclk_prepare)); 1914 1915 /* program timings */ 1916 1917 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0); 1918 r = FLD_MOD(r, ths_prepare, 31, 24); 1919 r = FLD_MOD(r, ths_prepare_ths_zero, 23, 16); 1920 r = FLD_MOD(r, ths_trail, 15, 8); 1921 r = FLD_MOD(r, ths_exit, 7, 0); 1922 dsi_write_reg(dsidev, DSI_DSIPHY_CFG0, r); 1923 1924 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1); 1925 r = FLD_MOD(r, tlpx_half, 20, 16); 1926 r = FLD_MOD(r, tclk_trail, 15, 8); 1927 r = FLD_MOD(r, tclk_zero, 7, 0); 1928 1929 if (dss_has_feature(FEAT_DSI_PHY_DCC)) { 1930 r = FLD_MOD(r, 0, 21, 21); /* DCCEN = disable */ 1931 r = FLD_MOD(r, 1, 22, 22); /* CLKINP_DIVBY2EN = enable */ 1932 r = FLD_MOD(r, 1, 23, 23); /* CLKINP_SEL = enable */ 1933 } 1934 1935 dsi_write_reg(dsidev, DSI_DSIPHY_CFG1, r); 1936 1937 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG2); 1938 r = FLD_MOD(r, tclk_prepare, 7, 0); 1939 dsi_write_reg(dsidev, DSI_DSIPHY_CFG2, r); 1940 } 1941 1942 /* lane masks have lane 0 at lsb. mask_p for positive lines, n for negative */ 1943 static void dsi_cio_enable_lane_override(struct platform_device *dsidev, 1944 unsigned mask_p, unsigned mask_n) 1945 { 1946 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1947 int i; 1948 u32 l; 1949 u8 lptxscp_start = dsi->num_lanes_supported == 3 ? 22 : 26; 1950 1951 l = 0; 1952 1953 for (i = 0; i < dsi->num_lanes_supported; ++i) { 1954 unsigned p = dsi->lanes[i].polarity; 1955 1956 if (mask_p & (1 << i)) 1957 l |= 1 << (i * 2 + (p ? 0 : 1)); 1958 1959 if (mask_n & (1 << i)) 1960 l |= 1 << (i * 2 + (p ? 1 : 0)); 1961 } 1962 1963 /* 1964 * Bits in REGLPTXSCPDAT4TO0DXDY: 1965 * 17: DY0 18: DX0 1966 * 19: DY1 20: DX1 1967 * 21: DY2 22: DX2 1968 * 23: DY3 24: DX3 1969 * 25: DY4 26: DX4 1970 */ 1971 1972 /* Set the lane override configuration */ 1973 1974 /* REGLPTXSCPDAT4TO0DXDY */ 1975 REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, l, lptxscp_start, 17); 1976 1977 /* Enable lane override */ 1978 1979 /* ENLPTXSCPDAT */ 1980 REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 1, 27, 27); 1981 } 1982 1983 static void dsi_cio_disable_lane_override(struct platform_device *dsidev) 1984 { 1985 /* Disable lane override */ 1986 REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 0, 27, 27); /* ENLPTXSCPDAT */ 1987 /* Reset the lane override configuration */ 1988 /* REGLPTXSCPDAT4TO0DXDY */ 1989 REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 0, 22, 17); 1990 } 1991 1992 static int dsi_cio_wait_tx_clk_esc_reset(struct platform_device *dsidev) 1993 { 1994 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1995 int t, i; 1996 bool in_use[DSI_MAX_NR_LANES]; 1997 static const u8 offsets_old[] = { 28, 27, 26 }; 1998 static const u8 offsets_new[] = { 24, 25, 26, 27, 28 }; 1999 const u8 *offsets; 2000 2001 if (dss_has_feature(FEAT_DSI_REVERSE_TXCLKESC)) 2002 offsets = offsets_old; 2003 else 2004 offsets = offsets_new; 2005 2006 for (i = 0; i < dsi->num_lanes_supported; ++i) 2007 in_use[i] = dsi->lanes[i].function != DSI_LANE_UNUSED; 2008 2009 t = 100000; 2010 while (true) { 2011 u32 l; 2012 int ok; 2013 2014 l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5); 2015 2016 ok = 0; 2017 for (i = 0; i < dsi->num_lanes_supported; ++i) { 2018 if (!in_use[i] || (l & (1 << offsets[i]))) 2019 ok++; 2020 } 2021 2022 if (ok == dsi->num_lanes_supported) 2023 break; 2024 2025 if (--t == 0) { 2026 for (i = 0; i < dsi->num_lanes_supported; ++i) { 2027 if (!in_use[i] || (l & (1 << offsets[i]))) 2028 continue; 2029 2030 DSSERR("CIO TXCLKESC%d domain not coming " \ 2031 "out of reset\n", i); 2032 } 2033 return -EIO; 2034 } 2035 } 2036 2037 return 0; 2038 } 2039 2040 /* return bitmask of enabled lanes, lane0 being the lsb */ 2041 static unsigned dsi_get_lane_mask(struct platform_device *dsidev) 2042 { 2043 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 2044 unsigned mask = 0; 2045 int i; 2046 2047 for (i = 0; i < dsi->num_lanes_supported; ++i) { 2048 if (dsi->lanes[i].function != DSI_LANE_UNUSED) 2049 mask |= 1 << i; 2050 } 2051 2052 return mask; 2053 } 2054 2055 static int dsi_cio_init(struct platform_device *dsidev) 2056 { 2057 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 2058 int r; 2059 u32 l; 2060 2061 DSSDBG("DSI CIO init starts"); 2062 2063 r = dss_dsi_enable_pads(dsi->module_id, dsi_get_lane_mask(dsidev)); 2064 if (r) 2065 return r; 2066 2067 dsi_enable_scp_clk(dsidev); 2068 2069 /* A dummy read using the SCP interface to any DSIPHY register is 2070 * required after DSIPHY reset to complete the reset of the DSI complex 2071 * I/O. */ 2072 dsi_read_reg(dsidev, DSI_DSIPHY_CFG5); 2073 2074 if (wait_for_bit_change(dsidev, DSI_DSIPHY_CFG5, 30, 1) != 1) { 2075 DSSERR("CIO SCP Clock domain not coming out of reset.\n"); 2076 r = -EIO; 2077 goto err_scp_clk_dom; 2078 } 2079 2080 r = dsi_set_lane_config(dsidev); 2081 if (r) 2082 goto err_scp_clk_dom; 2083 2084 /* set TX STOP MODE timer to maximum for this operation */ 2085 l = dsi_read_reg(dsidev, DSI_TIMING1); 2086 l = FLD_MOD(l, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */ 2087 l = FLD_MOD(l, 1, 14, 14); /* STOP_STATE_X16_IO */ 2088 l = FLD_MOD(l, 1, 13, 13); /* STOP_STATE_X4_IO */ 2089 l = FLD_MOD(l, 0x1fff, 12, 0); /* STOP_STATE_COUNTER_IO */ 2090 dsi_write_reg(dsidev, DSI_TIMING1, l); 2091 2092 if (dsi->ulps_enabled) { 2093 unsigned mask_p; 2094 int i; 2095 2096 DSSDBG("manual ulps exit\n"); 2097 2098 /* ULPS is exited by Mark-1 state for 1ms, followed by 2099 * stop state. DSS HW cannot do this via the normal 2100 * ULPS exit sequence, as after reset the DSS HW thinks 2101 * that we are not in ULPS mode, and refuses to send the 2102 * sequence. So we need to send the ULPS exit sequence 2103 * manually by setting positive lines high and negative lines 2104 * low for 1ms. 2105 */ 2106 2107 mask_p = 0; 2108 2109 for (i = 0; i < dsi->num_lanes_supported; ++i) { 2110 if (dsi->lanes[i].function == DSI_LANE_UNUSED) 2111 continue; 2112 mask_p |= 1 << i; 2113 } 2114 2115 dsi_cio_enable_lane_override(dsidev, mask_p, 0); 2116 } 2117 2118 r = dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_ON); 2119 if (r) 2120 goto err_cio_pwr; 2121 2122 if (wait_for_bit_change(dsidev, DSI_COMPLEXIO_CFG1, 29, 1) != 1) { 2123 DSSERR("CIO PWR clock domain not coming out of reset.\n"); 2124 r = -ENODEV; 2125 goto err_cio_pwr_dom; 2126 } 2127 2128 dsi_if_enable(dsidev, true); 2129 dsi_if_enable(dsidev, false); 2130 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 20, 20); /* LP_CLK_ENABLE */ 2131 2132 r = dsi_cio_wait_tx_clk_esc_reset(dsidev); 2133 if (r) 2134 goto err_tx_clk_esc_rst; 2135 2136 if (dsi->ulps_enabled) { 2137 /* Keep Mark-1 state for 1ms (as per DSI spec) */ 2138 ktime_t wait = ns_to_ktime(1000 * 1000); 2139 set_current_state(TASK_UNINTERRUPTIBLE); 2140 schedule_hrtimeout(&wait, HRTIMER_MODE_REL); 2141 2142 /* Disable the override. The lanes should be set to Mark-11 2143 * state by the HW */ 2144 dsi_cio_disable_lane_override(dsidev); 2145 } 2146 2147 /* FORCE_TX_STOP_MODE_IO */ 2148 REG_FLD_MOD(dsidev, DSI_TIMING1, 0, 15, 15); 2149 2150 dsi_cio_timings(dsidev); 2151 2152 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) { 2153 /* DDR_CLK_ALWAYS_ON */ 2154 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 2155 dsi->vm_timings.ddr_clk_always_on, 13, 13); 2156 } 2157 2158 dsi->ulps_enabled = false; 2159 2160 DSSDBG("CIO init done\n"); 2161 2162 return 0; 2163 2164 err_tx_clk_esc_rst: 2165 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 20, 20); /* LP_CLK_ENABLE */ 2166 err_cio_pwr_dom: 2167 dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_OFF); 2168 err_cio_pwr: 2169 if (dsi->ulps_enabled) 2170 dsi_cio_disable_lane_override(dsidev); 2171 err_scp_clk_dom: 2172 dsi_disable_scp_clk(dsidev); 2173 dss_dsi_disable_pads(dsi->module_id, dsi_get_lane_mask(dsidev)); 2174 return r; 2175 } 2176 2177 static void dsi_cio_uninit(struct platform_device *dsidev) 2178 { 2179 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 2180 2181 /* DDR_CLK_ALWAYS_ON */ 2182 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 13, 13); 2183 2184 dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_OFF); 2185 dsi_disable_scp_clk(dsidev); 2186 dss_dsi_disable_pads(dsi->module_id, dsi_get_lane_mask(dsidev)); 2187 } 2188 2189 static void dsi_config_tx_fifo(struct platform_device *dsidev, 2190 enum fifo_size size1, enum fifo_size size2, 2191 enum fifo_size size3, enum fifo_size size4) 2192 { 2193 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 2194 u32 r = 0; 2195 int add = 0; 2196 int i; 2197 2198 dsi->vc[0].tx_fifo_size = size1; 2199 dsi->vc[1].tx_fifo_size = size2; 2200 dsi->vc[2].tx_fifo_size = size3; 2201 dsi->vc[3].tx_fifo_size = size4; 2202 2203 for (i = 0; i < 4; i++) { 2204 u8 v; 2205 int size = dsi->vc[i].tx_fifo_size; 2206 2207 if (add + size > 4) { 2208 DSSERR("Illegal FIFO configuration\n"); 2209 BUG(); 2210 return; 2211 } 2212 2213 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4); 2214 r |= v << (8 * i); 2215 /*DSSDBG("TX FIFO vc %d: size %d, add %d\n", i, size, add); */ 2216 add += size; 2217 } 2218 2219 dsi_write_reg(dsidev, DSI_TX_FIFO_VC_SIZE, r); 2220 } 2221 2222 static void dsi_config_rx_fifo(struct platform_device *dsidev, 2223 enum fifo_size size1, enum fifo_size size2, 2224 enum fifo_size size3, enum fifo_size size4) 2225 { 2226 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 2227 u32 r = 0; 2228 int add = 0; 2229 int i; 2230 2231 dsi->vc[0].rx_fifo_size = size1; 2232 dsi->vc[1].rx_fifo_size = size2; 2233 dsi->vc[2].rx_fifo_size = size3; 2234 dsi->vc[3].rx_fifo_size = size4; 2235 2236 for (i = 0; i < 4; i++) { 2237 u8 v; 2238 int size = dsi->vc[i].rx_fifo_size; 2239 2240 if (add + size > 4) { 2241 DSSERR("Illegal FIFO configuration\n"); 2242 BUG(); 2243 return; 2244 } 2245 2246 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4); 2247 r |= v << (8 * i); 2248 /*DSSDBG("RX FIFO vc %d: size %d, add %d\n", i, size, add); */ 2249 add += size; 2250 } 2251 2252 dsi_write_reg(dsidev, DSI_RX_FIFO_VC_SIZE, r); 2253 } 2254 2255 static int dsi_force_tx_stop_mode_io(struct platform_device *dsidev) 2256 { 2257 u32 r; 2258 2259 r = dsi_read_reg(dsidev, DSI_TIMING1); 2260 r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */ 2261 dsi_write_reg(dsidev, DSI_TIMING1, r); 2262 2263 if (wait_for_bit_change(dsidev, DSI_TIMING1, 15, 0) != 0) { 2264 DSSERR("TX_STOP bit not going down\n"); 2265 return -EIO; 2266 } 2267 2268 return 0; 2269 } 2270 2271 static bool dsi_vc_is_enabled(struct platform_device *dsidev, int channel) 2272 { 2273 return REG_GET(dsidev, DSI_VC_CTRL(channel), 0, 0); 2274 } 2275 2276 static void dsi_packet_sent_handler_vp(void *data, u32 mask) 2277 { 2278 struct dsi_packet_sent_handler_data *vp_data = 2279 (struct dsi_packet_sent_handler_data *) data; 2280 struct dsi_data *dsi = dsi_get_dsidrv_data(vp_data->dsidev); 2281 const int channel = dsi->update_channel; 2282 u8 bit = dsi->te_enabled ? 30 : 31; 2283 2284 if (REG_GET(vp_data->dsidev, DSI_VC_TE(channel), bit, bit) == 0) 2285 complete(vp_data->completion); 2286 } 2287 2288 static int dsi_sync_vc_vp(struct platform_device *dsidev, int channel) 2289 { 2290 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 2291 DECLARE_COMPLETION_ONSTACK(completion); 2292 struct dsi_packet_sent_handler_data vp_data = { 2293 .dsidev = dsidev, 2294 .completion = &completion 2295 }; 2296 int r = 0; 2297 u8 bit; 2298 2299 bit = dsi->te_enabled ? 30 : 31; 2300 2301 r = dsi_register_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp, 2302 &vp_data, DSI_VC_IRQ_PACKET_SENT); 2303 if (r) 2304 goto err0; 2305 2306 /* Wait for completion only if TE_EN/TE_START is still set */ 2307 if (REG_GET(dsidev, DSI_VC_TE(channel), bit, bit)) { 2308 if (wait_for_completion_timeout(&completion, 2309 msecs_to_jiffies(10)) == 0) { 2310 DSSERR("Failed to complete previous frame transfer\n"); 2311 r = -EIO; 2312 goto err1; 2313 } 2314 } 2315 2316 dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp, 2317 &vp_data, DSI_VC_IRQ_PACKET_SENT); 2318 2319 return 0; 2320 err1: 2321 dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp, 2322 &vp_data, DSI_VC_IRQ_PACKET_SENT); 2323 err0: 2324 return r; 2325 } 2326 2327 static void dsi_packet_sent_handler_l4(void *data, u32 mask) 2328 { 2329 struct dsi_packet_sent_handler_data *l4_data = 2330 (struct dsi_packet_sent_handler_data *) data; 2331 struct dsi_data *dsi = dsi_get_dsidrv_data(l4_data->dsidev); 2332 const int channel = dsi->update_channel; 2333 2334 if (REG_GET(l4_data->dsidev, DSI_VC_CTRL(channel), 5, 5) == 0) 2335 complete(l4_data->completion); 2336 } 2337 2338 static int dsi_sync_vc_l4(struct platform_device *dsidev, int channel) 2339 { 2340 DECLARE_COMPLETION_ONSTACK(completion); 2341 struct dsi_packet_sent_handler_data l4_data = { 2342 .dsidev = dsidev, 2343 .completion = &completion 2344 }; 2345 int r = 0; 2346 2347 r = dsi_register_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4, 2348 &l4_data, DSI_VC_IRQ_PACKET_SENT); 2349 if (r) 2350 goto err0; 2351 2352 /* Wait for completion only if TX_FIFO_NOT_EMPTY is still set */ 2353 if (REG_GET(dsidev, DSI_VC_CTRL(channel), 5, 5)) { 2354 if (wait_for_completion_timeout(&completion, 2355 msecs_to_jiffies(10)) == 0) { 2356 DSSERR("Failed to complete previous l4 transfer\n"); 2357 r = -EIO; 2358 goto err1; 2359 } 2360 } 2361 2362 dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4, 2363 &l4_data, DSI_VC_IRQ_PACKET_SENT); 2364 2365 return 0; 2366 err1: 2367 dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4, 2368 &l4_data, DSI_VC_IRQ_PACKET_SENT); 2369 err0: 2370 return r; 2371 } 2372 2373 static int dsi_sync_vc(struct platform_device *dsidev, int channel) 2374 { 2375 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 2376 2377 WARN_ON(!dsi_bus_is_locked(dsidev)); 2378 2379 WARN_ON(in_interrupt()); 2380 2381 if (!dsi_vc_is_enabled(dsidev, channel)) 2382 return 0; 2383 2384 switch (dsi->vc[channel].source) { 2385 case DSI_VC_SOURCE_VP: 2386 return dsi_sync_vc_vp(dsidev, channel); 2387 case DSI_VC_SOURCE_L4: 2388 return dsi_sync_vc_l4(dsidev, channel); 2389 default: 2390 BUG(); 2391 return -EINVAL; 2392 } 2393 } 2394 2395 static int dsi_vc_enable(struct platform_device *dsidev, int channel, 2396 bool enable) 2397 { 2398 DSSDBG("dsi_vc_enable channel %d, enable %d\n", 2399 channel, enable); 2400 2401 enable = enable ? 1 : 0; 2402 2403 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 0, 0); 2404 2405 if (wait_for_bit_change(dsidev, DSI_VC_CTRL(channel), 2406 0, enable) != enable) { 2407 DSSERR("Failed to set dsi_vc_enable to %d\n", enable); 2408 return -EIO; 2409 } 2410 2411 return 0; 2412 } 2413 2414 static void dsi_vc_initial_config(struct platform_device *dsidev, int channel) 2415 { 2416 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 2417 u32 r; 2418 2419 DSSDBG("Initial config of virtual channel %d", channel); 2420 2421 r = dsi_read_reg(dsidev, DSI_VC_CTRL(channel)); 2422 2423 if (FLD_GET(r, 15, 15)) /* VC_BUSY */ 2424 DSSERR("VC(%d) busy when trying to configure it!\n", 2425 channel); 2426 2427 r = FLD_MOD(r, 0, 1, 1); /* SOURCE, 0 = L4 */ 2428 r = FLD_MOD(r, 0, 2, 2); /* BTA_SHORT_EN */ 2429 r = FLD_MOD(r, 0, 3, 3); /* BTA_LONG_EN */ 2430 r = FLD_MOD(r, 0, 4, 4); /* MODE, 0 = command */ 2431 r = FLD_MOD(r, 1, 7, 7); /* CS_TX_EN */ 2432 r = FLD_MOD(r, 1, 8, 8); /* ECC_TX_EN */ 2433 r = FLD_MOD(r, 0, 9, 9); /* MODE_SPEED, high speed on/off */ 2434 if (dss_has_feature(FEAT_DSI_VC_OCP_WIDTH)) 2435 r = FLD_MOD(r, 3, 11, 10); /* OCP_WIDTH = 32 bit */ 2436 2437 r = FLD_MOD(r, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */ 2438 r = FLD_MOD(r, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */ 2439 2440 dsi_write_reg(dsidev, DSI_VC_CTRL(channel), r); 2441 2442 dsi->vc[channel].source = DSI_VC_SOURCE_L4; 2443 } 2444 2445 static int dsi_vc_config_source(struct platform_device *dsidev, int channel, 2446 enum dsi_vc_source source) 2447 { 2448 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 2449 2450 if (dsi->vc[channel].source == source) 2451 return 0; 2452 2453 DSSDBG("Source config of virtual channel %d", channel); 2454 2455 dsi_sync_vc(dsidev, channel); 2456 2457 dsi_vc_enable(dsidev, channel, 0); 2458 2459 /* VC_BUSY */ 2460 if (wait_for_bit_change(dsidev, DSI_VC_CTRL(channel), 15, 0) != 0) { 2461 DSSERR("vc(%d) busy when trying to config for VP\n", channel); 2462 return -EIO; 2463 } 2464 2465 /* SOURCE, 0 = L4, 1 = video port */ 2466 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), source, 1, 1); 2467 2468 /* DCS_CMD_ENABLE */ 2469 if (dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC)) { 2470 bool enable = source == DSI_VC_SOURCE_VP; 2471 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 30, 30); 2472 } 2473 2474 dsi_vc_enable(dsidev, channel, 1); 2475 2476 dsi->vc[channel].source = source; 2477 2478 return 0; 2479 } 2480 2481 static void dsi_vc_enable_hs(struct omap_dss_device *dssdev, int channel, 2482 bool enable) 2483 { 2484 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 2485 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 2486 2487 DSSDBG("dsi_vc_enable_hs(%d, %d)\n", channel, enable); 2488 2489 WARN_ON(!dsi_bus_is_locked(dsidev)); 2490 2491 dsi_vc_enable(dsidev, channel, 0); 2492 dsi_if_enable(dsidev, 0); 2493 2494 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 9, 9); 2495 2496 dsi_vc_enable(dsidev, channel, 1); 2497 dsi_if_enable(dsidev, 1); 2498 2499 dsi_force_tx_stop_mode_io(dsidev); 2500 2501 /* start the DDR clock by sending a NULL packet */ 2502 if (dsi->vm_timings.ddr_clk_always_on && enable) 2503 dsi_vc_send_null(dssdev, channel); 2504 } 2505 2506 static void dsi_vc_flush_long_data(struct platform_device *dsidev, int channel) 2507 { 2508 while (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) { 2509 u32 val; 2510 val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel)); 2511 DSSDBG("\t\tb1 %#02x b2 %#02x b3 %#02x b4 %#02x\n", 2512 (val >> 0) & 0xff, 2513 (val >> 8) & 0xff, 2514 (val >> 16) & 0xff, 2515 (val >> 24) & 0xff); 2516 } 2517 } 2518 2519 static void dsi_show_rx_ack_with_err(u16 err) 2520 { 2521 DSSERR("\tACK with ERROR (%#x):\n", err); 2522 if (err & (1 << 0)) 2523 DSSERR("\t\tSoT Error\n"); 2524 if (err & (1 << 1)) 2525 DSSERR("\t\tSoT Sync Error\n"); 2526 if (err & (1 << 2)) 2527 DSSERR("\t\tEoT Sync Error\n"); 2528 if (err & (1 << 3)) 2529 DSSERR("\t\tEscape Mode Entry Command Error\n"); 2530 if (err & (1 << 4)) 2531 DSSERR("\t\tLP Transmit Sync Error\n"); 2532 if (err & (1 << 5)) 2533 DSSERR("\t\tHS Receive Timeout Error\n"); 2534 if (err & (1 << 6)) 2535 DSSERR("\t\tFalse Control Error\n"); 2536 if (err & (1 << 7)) 2537 DSSERR("\t\t(reserved7)\n"); 2538 if (err & (1 << 8)) 2539 DSSERR("\t\tECC Error, single-bit (corrected)\n"); 2540 if (err & (1 << 9)) 2541 DSSERR("\t\tECC Error, multi-bit (not corrected)\n"); 2542 if (err & (1 << 10)) 2543 DSSERR("\t\tChecksum Error\n"); 2544 if (err & (1 << 11)) 2545 DSSERR("\t\tData type not recognized\n"); 2546 if (err & (1 << 12)) 2547 DSSERR("\t\tInvalid VC ID\n"); 2548 if (err & (1 << 13)) 2549 DSSERR("\t\tInvalid Transmission Length\n"); 2550 if (err & (1 << 14)) 2551 DSSERR("\t\t(reserved14)\n"); 2552 if (err & (1 << 15)) 2553 DSSERR("\t\tDSI Protocol Violation\n"); 2554 } 2555 2556 static u16 dsi_vc_flush_receive_data(struct platform_device *dsidev, 2557 int channel) 2558 { 2559 /* RX_FIFO_NOT_EMPTY */ 2560 while (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) { 2561 u32 val; 2562 u8 dt; 2563 val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel)); 2564 DSSERR("\trawval %#08x\n", val); 2565 dt = FLD_GET(val, 5, 0); 2566 if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) { 2567 u16 err = FLD_GET(val, 23, 8); 2568 dsi_show_rx_ack_with_err(err); 2569 } else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE) { 2570 DSSERR("\tDCS short response, 1 byte: %#x\n", 2571 FLD_GET(val, 23, 8)); 2572 } else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE) { 2573 DSSERR("\tDCS short response, 2 byte: %#x\n", 2574 FLD_GET(val, 23, 8)); 2575 } else if (dt == MIPI_DSI_RX_DCS_LONG_READ_RESPONSE) { 2576 DSSERR("\tDCS long response, len %d\n", 2577 FLD_GET(val, 23, 8)); 2578 dsi_vc_flush_long_data(dsidev, channel); 2579 } else { 2580 DSSERR("\tunknown datatype 0x%02x\n", dt); 2581 } 2582 } 2583 return 0; 2584 } 2585 2586 static int dsi_vc_send_bta(struct platform_device *dsidev, int channel) 2587 { 2588 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 2589 2590 if (dsi->debug_write || dsi->debug_read) 2591 DSSDBG("dsi_vc_send_bta %d\n", channel); 2592 2593 WARN_ON(!dsi_bus_is_locked(dsidev)); 2594 2595 /* RX_FIFO_NOT_EMPTY */ 2596 if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) { 2597 DSSERR("rx fifo not empty when sending BTA, dumping data:\n"); 2598 dsi_vc_flush_receive_data(dsidev, channel); 2599 } 2600 2601 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 1, 6, 6); /* BTA_EN */ 2602 2603 /* flush posted write */ 2604 dsi_read_reg(dsidev, DSI_VC_CTRL(channel)); 2605 2606 return 0; 2607 } 2608 2609 static int dsi_vc_send_bta_sync(struct omap_dss_device *dssdev, int channel) 2610 { 2611 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 2612 DECLARE_COMPLETION_ONSTACK(completion); 2613 int r = 0; 2614 u32 err; 2615 2616 r = dsi_register_isr_vc(dsidev, channel, dsi_completion_handler, 2617 &completion, DSI_VC_IRQ_BTA); 2618 if (r) 2619 goto err0; 2620 2621 r = dsi_register_isr(dsidev, dsi_completion_handler, &completion, 2622 DSI_IRQ_ERROR_MASK); 2623 if (r) 2624 goto err1; 2625 2626 r = dsi_vc_send_bta(dsidev, channel); 2627 if (r) 2628 goto err2; 2629 2630 if (wait_for_completion_timeout(&completion, 2631 msecs_to_jiffies(500)) == 0) { 2632 DSSERR("Failed to receive BTA\n"); 2633 r = -EIO; 2634 goto err2; 2635 } 2636 2637 err = dsi_get_errors(dsidev); 2638 if (err) { 2639 DSSERR("Error while sending BTA: %x\n", err); 2640 r = -EIO; 2641 goto err2; 2642 } 2643 err2: 2644 dsi_unregister_isr(dsidev, dsi_completion_handler, &completion, 2645 DSI_IRQ_ERROR_MASK); 2646 err1: 2647 dsi_unregister_isr_vc(dsidev, channel, dsi_completion_handler, 2648 &completion, DSI_VC_IRQ_BTA); 2649 err0: 2650 return r; 2651 } 2652 2653 static inline void dsi_vc_write_long_header(struct platform_device *dsidev, 2654 int channel, u8 data_type, u16 len, u8 ecc) 2655 { 2656 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 2657 u32 val; 2658 u8 data_id; 2659 2660 WARN_ON(!dsi_bus_is_locked(dsidev)); 2661 2662 data_id = data_type | dsi->vc[channel].vc_id << 6; 2663 2664 val = FLD_VAL(data_id, 7, 0) | FLD_VAL(len, 23, 8) | 2665 FLD_VAL(ecc, 31, 24); 2666 2667 dsi_write_reg(dsidev, DSI_VC_LONG_PACKET_HEADER(channel), val); 2668 } 2669 2670 static inline void dsi_vc_write_long_payload(struct platform_device *dsidev, 2671 int channel, u8 b1, u8 b2, u8 b3, u8 b4) 2672 { 2673 u32 val; 2674 2675 val = b4 << 24 | b3 << 16 | b2 << 8 | b1 << 0; 2676 2677 /* DSSDBG("\twriting %02x, %02x, %02x, %02x (%#010x)\n", 2678 b1, b2, b3, b4, val); */ 2679 2680 dsi_write_reg(dsidev, DSI_VC_LONG_PACKET_PAYLOAD(channel), val); 2681 } 2682 2683 static int dsi_vc_send_long(struct platform_device *dsidev, int channel, 2684 u8 data_type, u8 *data, u16 len, u8 ecc) 2685 { 2686 /*u32 val; */ 2687 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 2688 int i; 2689 u8 *p; 2690 int r = 0; 2691 u8 b1, b2, b3, b4; 2692 2693 if (dsi->debug_write) 2694 DSSDBG("dsi_vc_send_long, %d bytes\n", len); 2695 2696 /* len + header */ 2697 if (dsi->vc[channel].tx_fifo_size * 32 * 4 < len + 4) { 2698 DSSERR("unable to send long packet: packet too long.\n"); 2699 return -EINVAL; 2700 } 2701 2702 dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_L4); 2703 2704 dsi_vc_write_long_header(dsidev, channel, data_type, len, ecc); 2705 2706 p = data; 2707 for (i = 0; i < len >> 2; i++) { 2708 if (dsi->debug_write) 2709 DSSDBG("\tsending full packet %d\n", i); 2710 2711 b1 = *p++; 2712 b2 = *p++; 2713 b3 = *p++; 2714 b4 = *p++; 2715 2716 dsi_vc_write_long_payload(dsidev, channel, b1, b2, b3, b4); 2717 } 2718 2719 i = len % 4; 2720 if (i) { 2721 b1 = 0; b2 = 0; b3 = 0; 2722 2723 if (dsi->debug_write) 2724 DSSDBG("\tsending remainder bytes %d\n", i); 2725 2726 switch (i) { 2727 case 3: 2728 b1 = *p++; 2729 b2 = *p++; 2730 b3 = *p++; 2731 break; 2732 case 2: 2733 b1 = *p++; 2734 b2 = *p++; 2735 break; 2736 case 1: 2737 b1 = *p++; 2738 break; 2739 } 2740 2741 dsi_vc_write_long_payload(dsidev, channel, b1, b2, b3, 0); 2742 } 2743 2744 return r; 2745 } 2746 2747 static int dsi_vc_send_short(struct platform_device *dsidev, int channel, 2748 u8 data_type, u16 data, u8 ecc) 2749 { 2750 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 2751 u32 r; 2752 u8 data_id; 2753 2754 WARN_ON(!dsi_bus_is_locked(dsidev)); 2755 2756 if (dsi->debug_write) 2757 DSSDBG("dsi_vc_send_short(ch%d, dt %#x, b1 %#x, b2 %#x)\n", 2758 channel, 2759 data_type, data & 0xff, (data >> 8) & 0xff); 2760 2761 dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_L4); 2762 2763 if (FLD_GET(dsi_read_reg(dsidev, DSI_VC_CTRL(channel)), 16, 16)) { 2764 DSSERR("ERROR FIFO FULL, aborting transfer\n"); 2765 return -EINVAL; 2766 } 2767 2768 data_id = data_type | dsi->vc[channel].vc_id << 6; 2769 2770 r = (data_id << 0) | (data << 8) | (ecc << 24); 2771 2772 dsi_write_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel), r); 2773 2774 return 0; 2775 } 2776 2777 static int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel) 2778 { 2779 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 2780 2781 return dsi_vc_send_long(dsidev, channel, MIPI_DSI_NULL_PACKET, NULL, 2782 0, 0); 2783 } 2784 2785 static int dsi_vc_write_nosync_common(struct platform_device *dsidev, 2786 int channel, u8 *data, int len, enum dss_dsi_content_type type) 2787 { 2788 int r; 2789 2790 if (len == 0) { 2791 BUG_ON(type == DSS_DSI_CONTENT_DCS); 2792 r = dsi_vc_send_short(dsidev, channel, 2793 MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM, 0, 0); 2794 } else if (len == 1) { 2795 r = dsi_vc_send_short(dsidev, channel, 2796 type == DSS_DSI_CONTENT_GENERIC ? 2797 MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM : 2798 MIPI_DSI_DCS_SHORT_WRITE, data[0], 0); 2799 } else if (len == 2) { 2800 r = dsi_vc_send_short(dsidev, channel, 2801 type == DSS_DSI_CONTENT_GENERIC ? 2802 MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM : 2803 MIPI_DSI_DCS_SHORT_WRITE_PARAM, 2804 data[0] | (data[1] << 8), 0); 2805 } else { 2806 r = dsi_vc_send_long(dsidev, channel, 2807 type == DSS_DSI_CONTENT_GENERIC ? 2808 MIPI_DSI_GENERIC_LONG_WRITE : 2809 MIPI_DSI_DCS_LONG_WRITE, data, len, 0); 2810 } 2811 2812 return r; 2813 } 2814 2815 static int dsi_vc_dcs_write_nosync(struct omap_dss_device *dssdev, int channel, 2816 u8 *data, int len) 2817 { 2818 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 2819 2820 return dsi_vc_write_nosync_common(dsidev, channel, data, len, 2821 DSS_DSI_CONTENT_DCS); 2822 } 2823 2824 static int dsi_vc_generic_write_nosync(struct omap_dss_device *dssdev, int channel, 2825 u8 *data, int len) 2826 { 2827 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 2828 2829 return dsi_vc_write_nosync_common(dsidev, channel, data, len, 2830 DSS_DSI_CONTENT_GENERIC); 2831 } 2832 2833 static int dsi_vc_write_common(struct omap_dss_device *dssdev, int channel, 2834 u8 *data, int len, enum dss_dsi_content_type type) 2835 { 2836 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 2837 int r; 2838 2839 r = dsi_vc_write_nosync_common(dsidev, channel, data, len, type); 2840 if (r) 2841 goto err; 2842 2843 r = dsi_vc_send_bta_sync(dssdev, channel); 2844 if (r) 2845 goto err; 2846 2847 /* RX_FIFO_NOT_EMPTY */ 2848 if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) { 2849 DSSERR("rx fifo not empty after write, dumping data:\n"); 2850 dsi_vc_flush_receive_data(dsidev, channel); 2851 r = -EIO; 2852 goto err; 2853 } 2854 2855 return 0; 2856 err: 2857 DSSERR("dsi_vc_write_common(ch %d, cmd 0x%02x, len %d) failed\n", 2858 channel, data[0], len); 2859 return r; 2860 } 2861 2862 static int dsi_vc_dcs_write(struct omap_dss_device *dssdev, int channel, u8 *data, 2863 int len) 2864 { 2865 return dsi_vc_write_common(dssdev, channel, data, len, 2866 DSS_DSI_CONTENT_DCS); 2867 } 2868 2869 static int dsi_vc_generic_write(struct omap_dss_device *dssdev, int channel, u8 *data, 2870 int len) 2871 { 2872 return dsi_vc_write_common(dssdev, channel, data, len, 2873 DSS_DSI_CONTENT_GENERIC); 2874 } 2875 2876 static int dsi_vc_dcs_send_read_request(struct platform_device *dsidev, 2877 int channel, u8 dcs_cmd) 2878 { 2879 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 2880 int r; 2881 2882 if (dsi->debug_read) 2883 DSSDBG("dsi_vc_dcs_send_read_request(ch%d, dcs_cmd %x)\n", 2884 channel, dcs_cmd); 2885 2886 r = dsi_vc_send_short(dsidev, channel, MIPI_DSI_DCS_READ, dcs_cmd, 0); 2887 if (r) { 2888 DSSERR("dsi_vc_dcs_send_read_request(ch %d, cmd 0x%02x)" 2889 " failed\n", channel, dcs_cmd); 2890 return r; 2891 } 2892 2893 return 0; 2894 } 2895 2896 static int dsi_vc_generic_send_read_request(struct platform_device *dsidev, 2897 int channel, u8 *reqdata, int reqlen) 2898 { 2899 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 2900 u16 data; 2901 u8 data_type; 2902 int r; 2903 2904 if (dsi->debug_read) 2905 DSSDBG("dsi_vc_generic_send_read_request(ch %d, reqlen %d)\n", 2906 channel, reqlen); 2907 2908 if (reqlen == 0) { 2909 data_type = MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM; 2910 data = 0; 2911 } else if (reqlen == 1) { 2912 data_type = MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM; 2913 data = reqdata[0]; 2914 } else if (reqlen == 2) { 2915 data_type = MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM; 2916 data = reqdata[0] | (reqdata[1] << 8); 2917 } else { 2918 BUG(); 2919 return -EINVAL; 2920 } 2921 2922 r = dsi_vc_send_short(dsidev, channel, data_type, data, 0); 2923 if (r) { 2924 DSSERR("dsi_vc_generic_send_read_request(ch %d, reqlen %d)" 2925 " failed\n", channel, reqlen); 2926 return r; 2927 } 2928 2929 return 0; 2930 } 2931 2932 static int dsi_vc_read_rx_fifo(struct platform_device *dsidev, int channel, 2933 u8 *buf, int buflen, enum dss_dsi_content_type type) 2934 { 2935 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 2936 u32 val; 2937 u8 dt; 2938 int r; 2939 2940 /* RX_FIFO_NOT_EMPTY */ 2941 if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20) == 0) { 2942 DSSERR("RX fifo empty when trying to read.\n"); 2943 r = -EIO; 2944 goto err; 2945 } 2946 2947 val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel)); 2948 if (dsi->debug_read) 2949 DSSDBG("\theader: %08x\n", val); 2950 dt = FLD_GET(val, 5, 0); 2951 if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) { 2952 u16 err = FLD_GET(val, 23, 8); 2953 dsi_show_rx_ack_with_err(err); 2954 r = -EIO; 2955 goto err; 2956 2957 } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ? 2958 MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE : 2959 MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE)) { 2960 u8 data = FLD_GET(val, 15, 8); 2961 if (dsi->debug_read) 2962 DSSDBG("\t%s short response, 1 byte: %02x\n", 2963 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" : 2964 "DCS", data); 2965 2966 if (buflen < 1) { 2967 r = -EIO; 2968 goto err; 2969 } 2970 2971 buf[0] = data; 2972 2973 return 1; 2974 } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ? 2975 MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE : 2976 MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE)) { 2977 u16 data = FLD_GET(val, 23, 8); 2978 if (dsi->debug_read) 2979 DSSDBG("\t%s short response, 2 byte: %04x\n", 2980 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" : 2981 "DCS", data); 2982 2983 if (buflen < 2) { 2984 r = -EIO; 2985 goto err; 2986 } 2987 2988 buf[0] = data & 0xff; 2989 buf[1] = (data >> 8) & 0xff; 2990 2991 return 2; 2992 } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ? 2993 MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE : 2994 MIPI_DSI_RX_DCS_LONG_READ_RESPONSE)) { 2995 int w; 2996 int len = FLD_GET(val, 23, 8); 2997 if (dsi->debug_read) 2998 DSSDBG("\t%s long response, len %d\n", 2999 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" : 3000 "DCS", len); 3001 3002 if (len > buflen) { 3003 r = -EIO; 3004 goto err; 3005 } 3006 3007 /* two byte checksum ends the packet, not included in len */ 3008 for (w = 0; w < len + 2;) { 3009 int b; 3010 val = dsi_read_reg(dsidev, 3011 DSI_VC_SHORT_PACKET_HEADER(channel)); 3012 if (dsi->debug_read) 3013 DSSDBG("\t\t%02x %02x %02x %02x\n", 3014 (val >> 0) & 0xff, 3015 (val >> 8) & 0xff, 3016 (val >> 16) & 0xff, 3017 (val >> 24) & 0xff); 3018 3019 for (b = 0; b < 4; ++b) { 3020 if (w < len) 3021 buf[w] = (val >> (b * 8)) & 0xff; 3022 /* we discard the 2 byte checksum */ 3023 ++w; 3024 } 3025 } 3026 3027 return len; 3028 } else { 3029 DSSERR("\tunknown datatype 0x%02x\n", dt); 3030 r = -EIO; 3031 goto err; 3032 } 3033 3034 err: 3035 DSSERR("dsi_vc_read_rx_fifo(ch %d type %s) failed\n", channel, 3036 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" : "DCS"); 3037 3038 return r; 3039 } 3040 3041 static int dsi_vc_dcs_read(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd, 3042 u8 *buf, int buflen) 3043 { 3044 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 3045 int r; 3046 3047 r = dsi_vc_dcs_send_read_request(dsidev, channel, dcs_cmd); 3048 if (r) 3049 goto err; 3050 3051 r = dsi_vc_send_bta_sync(dssdev, channel); 3052 if (r) 3053 goto err; 3054 3055 r = dsi_vc_read_rx_fifo(dsidev, channel, buf, buflen, 3056 DSS_DSI_CONTENT_DCS); 3057 if (r < 0) 3058 goto err; 3059 3060 if (r != buflen) { 3061 r = -EIO; 3062 goto err; 3063 } 3064 3065 return 0; 3066 err: 3067 DSSERR("dsi_vc_dcs_read(ch %d, cmd 0x%02x) failed\n", channel, dcs_cmd); 3068 return r; 3069 } 3070 3071 static int dsi_vc_generic_read(struct omap_dss_device *dssdev, int channel, 3072 u8 *reqdata, int reqlen, u8 *buf, int buflen) 3073 { 3074 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 3075 int r; 3076 3077 r = dsi_vc_generic_send_read_request(dsidev, channel, reqdata, reqlen); 3078 if (r) 3079 return r; 3080 3081 r = dsi_vc_send_bta_sync(dssdev, channel); 3082 if (r) 3083 return r; 3084 3085 r = dsi_vc_read_rx_fifo(dsidev, channel, buf, buflen, 3086 DSS_DSI_CONTENT_GENERIC); 3087 if (r < 0) 3088 return r; 3089 3090 if (r != buflen) { 3091 r = -EIO; 3092 return r; 3093 } 3094 3095 return 0; 3096 } 3097 3098 static int dsi_vc_set_max_rx_packet_size(struct omap_dss_device *dssdev, int channel, 3099 u16 len) 3100 { 3101 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 3102 3103 return dsi_vc_send_short(dsidev, channel, 3104 MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE, len, 0); 3105 } 3106 3107 static int dsi_enter_ulps(struct platform_device *dsidev) 3108 { 3109 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 3110 DECLARE_COMPLETION_ONSTACK(completion); 3111 int r, i; 3112 unsigned mask; 3113 3114 DSSDBG("Entering ULPS"); 3115 3116 WARN_ON(!dsi_bus_is_locked(dsidev)); 3117 3118 WARN_ON(dsi->ulps_enabled); 3119 3120 if (dsi->ulps_enabled) 3121 return 0; 3122 3123 /* DDR_CLK_ALWAYS_ON */ 3124 if (REG_GET(dsidev, DSI_CLK_CTRL, 13, 13)) { 3125 dsi_if_enable(dsidev, 0); 3126 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 13, 13); 3127 dsi_if_enable(dsidev, 1); 3128 } 3129 3130 dsi_sync_vc(dsidev, 0); 3131 dsi_sync_vc(dsidev, 1); 3132 dsi_sync_vc(dsidev, 2); 3133 dsi_sync_vc(dsidev, 3); 3134 3135 dsi_force_tx_stop_mode_io(dsidev); 3136 3137 dsi_vc_enable(dsidev, 0, false); 3138 dsi_vc_enable(dsidev, 1, false); 3139 dsi_vc_enable(dsidev, 2, false); 3140 dsi_vc_enable(dsidev, 3, false); 3141 3142 if (REG_GET(dsidev, DSI_COMPLEXIO_CFG2, 16, 16)) { /* HS_BUSY */ 3143 DSSERR("HS busy when enabling ULPS\n"); 3144 return -EIO; 3145 } 3146 3147 if (REG_GET(dsidev, DSI_COMPLEXIO_CFG2, 17, 17)) { /* LP_BUSY */ 3148 DSSERR("LP busy when enabling ULPS\n"); 3149 return -EIO; 3150 } 3151 3152 r = dsi_register_isr_cio(dsidev, dsi_completion_handler, &completion, 3153 DSI_CIO_IRQ_ULPSACTIVENOT_ALL0); 3154 if (r) 3155 return r; 3156 3157 mask = 0; 3158 3159 for (i = 0; i < dsi->num_lanes_supported; ++i) { 3160 if (dsi->lanes[i].function == DSI_LANE_UNUSED) 3161 continue; 3162 mask |= 1 << i; 3163 } 3164 /* Assert TxRequestEsc for data lanes and TxUlpsClk for clk lane */ 3165 /* LANEx_ULPS_SIG2 */ 3166 REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG2, mask, 9, 5); 3167 3168 /* flush posted write and wait for SCP interface to finish the write */ 3169 dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG2); 3170 3171 if (wait_for_completion_timeout(&completion, 3172 msecs_to_jiffies(1000)) == 0) { 3173 DSSERR("ULPS enable timeout\n"); 3174 r = -EIO; 3175 goto err; 3176 } 3177 3178 dsi_unregister_isr_cio(dsidev, dsi_completion_handler, &completion, 3179 DSI_CIO_IRQ_ULPSACTIVENOT_ALL0); 3180 3181 /* Reset LANEx_ULPS_SIG2 */ 3182 REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG2, 0, 9, 5); 3183 3184 /* flush posted write and wait for SCP interface to finish the write */ 3185 dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG2); 3186 3187 dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_ULPS); 3188 3189 dsi_if_enable(dsidev, false); 3190 3191 dsi->ulps_enabled = true; 3192 3193 return 0; 3194 3195 err: 3196 dsi_unregister_isr_cio(dsidev, dsi_completion_handler, &completion, 3197 DSI_CIO_IRQ_ULPSACTIVENOT_ALL0); 3198 return r; 3199 } 3200 3201 static void dsi_set_lp_rx_timeout(struct platform_device *dsidev, 3202 unsigned ticks, bool x4, bool x16) 3203 { 3204 unsigned long fck; 3205 unsigned long total_ticks; 3206 u32 r; 3207 3208 BUG_ON(ticks > 0x1fff); 3209 3210 /* ticks in DSI_FCK */ 3211 fck = dsi_fclk_rate(dsidev); 3212 3213 r = dsi_read_reg(dsidev, DSI_TIMING2); 3214 r = FLD_MOD(r, 1, 15, 15); /* LP_RX_TO */ 3215 r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* LP_RX_TO_X16 */ 3216 r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* LP_RX_TO_X4 */ 3217 r = FLD_MOD(r, ticks, 12, 0); /* LP_RX_COUNTER */ 3218 dsi_write_reg(dsidev, DSI_TIMING2, r); 3219 3220 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1); 3221 3222 DSSDBG("LP_RX_TO %lu ticks (%#x%s%s) = %lu ns\n", 3223 total_ticks, 3224 ticks, x4 ? " x4" : "", x16 ? " x16" : "", 3225 (total_ticks * 1000) / (fck / 1000 / 1000)); 3226 } 3227 3228 static void dsi_set_ta_timeout(struct platform_device *dsidev, unsigned ticks, 3229 bool x8, bool x16) 3230 { 3231 unsigned long fck; 3232 unsigned long total_ticks; 3233 u32 r; 3234 3235 BUG_ON(ticks > 0x1fff); 3236 3237 /* ticks in DSI_FCK */ 3238 fck = dsi_fclk_rate(dsidev); 3239 3240 r = dsi_read_reg(dsidev, DSI_TIMING1); 3241 r = FLD_MOD(r, 1, 31, 31); /* TA_TO */ 3242 r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* TA_TO_X16 */ 3243 r = FLD_MOD(r, x8 ? 1 : 0, 29, 29); /* TA_TO_X8 */ 3244 r = FLD_MOD(r, ticks, 28, 16); /* TA_TO_COUNTER */ 3245 dsi_write_reg(dsidev, DSI_TIMING1, r); 3246 3247 total_ticks = ticks * (x16 ? 16 : 1) * (x8 ? 8 : 1); 3248 3249 DSSDBG("TA_TO %lu ticks (%#x%s%s) = %lu ns\n", 3250 total_ticks, 3251 ticks, x8 ? " x8" : "", x16 ? " x16" : "", 3252 (total_ticks * 1000) / (fck / 1000 / 1000)); 3253 } 3254 3255 static void dsi_set_stop_state_counter(struct platform_device *dsidev, 3256 unsigned ticks, bool x4, bool x16) 3257 { 3258 unsigned long fck; 3259 unsigned long total_ticks; 3260 u32 r; 3261 3262 BUG_ON(ticks > 0x1fff); 3263 3264 /* ticks in DSI_FCK */ 3265 fck = dsi_fclk_rate(dsidev); 3266 3267 r = dsi_read_reg(dsidev, DSI_TIMING1); 3268 r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */ 3269 r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* STOP_STATE_X16_IO */ 3270 r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* STOP_STATE_X4_IO */ 3271 r = FLD_MOD(r, ticks, 12, 0); /* STOP_STATE_COUNTER_IO */ 3272 dsi_write_reg(dsidev, DSI_TIMING1, r); 3273 3274 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1); 3275 3276 DSSDBG("STOP_STATE_COUNTER %lu ticks (%#x%s%s) = %lu ns\n", 3277 total_ticks, 3278 ticks, x4 ? " x4" : "", x16 ? " x16" : "", 3279 (total_ticks * 1000) / (fck / 1000 / 1000)); 3280 } 3281 3282 static void dsi_set_hs_tx_timeout(struct platform_device *dsidev, 3283 unsigned ticks, bool x4, bool x16) 3284 { 3285 unsigned long fck; 3286 unsigned long total_ticks; 3287 u32 r; 3288 3289 BUG_ON(ticks > 0x1fff); 3290 3291 /* ticks in TxByteClkHS */ 3292 fck = dsi_get_txbyteclkhs(dsidev); 3293 3294 r = dsi_read_reg(dsidev, DSI_TIMING2); 3295 r = FLD_MOD(r, 1, 31, 31); /* HS_TX_TO */ 3296 r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* HS_TX_TO_X16 */ 3297 r = FLD_MOD(r, x4 ? 1 : 0, 29, 29); /* HS_TX_TO_X8 (4 really) */ 3298 r = FLD_MOD(r, ticks, 28, 16); /* HS_TX_TO_COUNTER */ 3299 dsi_write_reg(dsidev, DSI_TIMING2, r); 3300 3301 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1); 3302 3303 DSSDBG("HS_TX_TO %lu ticks (%#x%s%s) = %lu ns\n", 3304 total_ticks, 3305 ticks, x4 ? " x4" : "", x16 ? " x16" : "", 3306 (total_ticks * 1000) / (fck / 1000 / 1000)); 3307 } 3308 3309 static void dsi_config_vp_num_line_buffers(struct platform_device *dsidev) 3310 { 3311 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 3312 int num_line_buffers; 3313 3314 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) { 3315 int bpp = dsi_get_pixel_size(dsi->pix_fmt); 3316 struct omap_video_timings *timings = &dsi->timings; 3317 /* 3318 * Don't use line buffers if width is greater than the video 3319 * port's line buffer size 3320 */ 3321 if (dsi->line_buffer_size <= timings->x_res * bpp / 8) 3322 num_line_buffers = 0; 3323 else 3324 num_line_buffers = 2; 3325 } else { 3326 /* Use maximum number of line buffers in command mode */ 3327 num_line_buffers = 2; 3328 } 3329 3330 /* LINE_BUFFER */ 3331 REG_FLD_MOD(dsidev, DSI_CTRL, num_line_buffers, 13, 12); 3332 } 3333 3334 static void dsi_config_vp_sync_events(struct platform_device *dsidev) 3335 { 3336 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 3337 bool sync_end; 3338 u32 r; 3339 3340 if (dsi->vm_timings.trans_mode == OMAP_DSS_DSI_PULSE_MODE) 3341 sync_end = true; 3342 else 3343 sync_end = false; 3344 3345 r = dsi_read_reg(dsidev, DSI_CTRL); 3346 r = FLD_MOD(r, 1, 9, 9); /* VP_DE_POL */ 3347 r = FLD_MOD(r, 1, 10, 10); /* VP_HSYNC_POL */ 3348 r = FLD_MOD(r, 1, 11, 11); /* VP_VSYNC_POL */ 3349 r = FLD_MOD(r, 1, 15, 15); /* VP_VSYNC_START */ 3350 r = FLD_MOD(r, sync_end, 16, 16); /* VP_VSYNC_END */ 3351 r = FLD_MOD(r, 1, 17, 17); /* VP_HSYNC_START */ 3352 r = FLD_MOD(r, sync_end, 18, 18); /* VP_HSYNC_END */ 3353 dsi_write_reg(dsidev, DSI_CTRL, r); 3354 } 3355 3356 static void dsi_config_blanking_modes(struct platform_device *dsidev) 3357 { 3358 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 3359 int blanking_mode = dsi->vm_timings.blanking_mode; 3360 int hfp_blanking_mode = dsi->vm_timings.hfp_blanking_mode; 3361 int hbp_blanking_mode = dsi->vm_timings.hbp_blanking_mode; 3362 int hsa_blanking_mode = dsi->vm_timings.hsa_blanking_mode; 3363 u32 r; 3364 3365 /* 3366 * 0 = TX FIFO packets sent or LPS in corresponding blanking periods 3367 * 1 = Long blanking packets are sent in corresponding blanking periods 3368 */ 3369 r = dsi_read_reg(dsidev, DSI_CTRL); 3370 r = FLD_MOD(r, blanking_mode, 20, 20); /* BLANKING_MODE */ 3371 r = FLD_MOD(r, hfp_blanking_mode, 21, 21); /* HFP_BLANKING */ 3372 r = FLD_MOD(r, hbp_blanking_mode, 22, 22); /* HBP_BLANKING */ 3373 r = FLD_MOD(r, hsa_blanking_mode, 23, 23); /* HSA_BLANKING */ 3374 dsi_write_reg(dsidev, DSI_CTRL, r); 3375 } 3376 3377 /* 3378 * According to section 'HS Command Mode Interleaving' in OMAP TRM, Scenario 3 3379 * results in maximum transition time for data and clock lanes to enter and 3380 * exit HS mode. Hence, this is the scenario where the least amount of command 3381 * mode data can be interleaved. We program the minimum amount of TXBYTECLKHS 3382 * clock cycles that can be used to interleave command mode data in HS so that 3383 * all scenarios are satisfied. 3384 */ 3385 static int dsi_compute_interleave_hs(int blank, bool ddr_alwon, int enter_hs, 3386 int exit_hs, int exiths_clk, int ddr_pre, int ddr_post) 3387 { 3388 int transition; 3389 3390 /* 3391 * If DDR_CLK_ALWAYS_ON is set, we need to consider HS mode transition 3392 * time of data lanes only, if it isn't set, we need to consider HS 3393 * transition time of both data and clock lanes. HS transition time 3394 * of Scenario 3 is considered. 3395 */ 3396 if (ddr_alwon) { 3397 transition = enter_hs + exit_hs + max(enter_hs, 2) + 1; 3398 } else { 3399 int trans1, trans2; 3400 trans1 = ddr_pre + enter_hs + exit_hs + max(enter_hs, 2) + 1; 3401 trans2 = ddr_pre + enter_hs + exiths_clk + ddr_post + ddr_pre + 3402 enter_hs + 1; 3403 transition = max(trans1, trans2); 3404 } 3405 3406 return blank > transition ? blank - transition : 0; 3407 } 3408 3409 /* 3410 * According to section 'LP Command Mode Interleaving' in OMAP TRM, Scenario 1 3411 * results in maximum transition time for data lanes to enter and exit LP mode. 3412 * Hence, this is the scenario where the least amount of command mode data can 3413 * be interleaved. We program the minimum amount of bytes that can be 3414 * interleaved in LP so that all scenarios are satisfied. 3415 */ 3416 static int dsi_compute_interleave_lp(int blank, int enter_hs, int exit_hs, 3417 int lp_clk_div, int tdsi_fclk) 3418 { 3419 int trans_lp; /* time required for a LP transition, in TXBYTECLKHS */ 3420 int tlp_avail; /* time left for interleaving commands, in CLKIN4DDR */ 3421 int ttxclkesc; /* period of LP transmit escape clock, in CLKIN4DDR */ 3422 int thsbyte_clk = 16; /* Period of TXBYTECLKHS clock, in CLKIN4DDR */ 3423 int lp_inter; /* cmd mode data that can be interleaved, in bytes */ 3424 3425 /* maximum LP transition time according to Scenario 1 */ 3426 trans_lp = exit_hs + max(enter_hs, 2) + 1; 3427 3428 /* CLKIN4DDR = 16 * TXBYTECLKHS */ 3429 tlp_avail = thsbyte_clk * (blank - trans_lp); 3430 3431 ttxclkesc = tdsi_fclk * lp_clk_div; 3432 3433 lp_inter = ((tlp_avail - 8 * thsbyte_clk - 5 * tdsi_fclk) / ttxclkesc - 3434 26) / 16; 3435 3436 return max(lp_inter, 0); 3437 } 3438 3439 static void dsi_config_cmd_mode_interleaving(struct platform_device *dsidev) 3440 { 3441 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 3442 int blanking_mode; 3443 int hfp_blanking_mode, hbp_blanking_mode, hsa_blanking_mode; 3444 int hsa, hfp, hbp, width_bytes, bllp, lp_clk_div; 3445 int ddr_clk_pre, ddr_clk_post, enter_hs_mode_lat, exit_hs_mode_lat; 3446 int tclk_trail, ths_exit, exiths_clk; 3447 bool ddr_alwon; 3448 struct omap_video_timings *timings = &dsi->timings; 3449 int bpp = dsi_get_pixel_size(dsi->pix_fmt); 3450 int ndl = dsi->num_lanes_used - 1; 3451 int dsi_fclk_hsdiv = dsi->user_dsi_cinfo.mX[HSDIV_DSI] + 1; 3452 int hsa_interleave_hs = 0, hsa_interleave_lp = 0; 3453 int hfp_interleave_hs = 0, hfp_interleave_lp = 0; 3454 int hbp_interleave_hs = 0, hbp_interleave_lp = 0; 3455 int bl_interleave_hs = 0, bl_interleave_lp = 0; 3456 u32 r; 3457 3458 r = dsi_read_reg(dsidev, DSI_CTRL); 3459 blanking_mode = FLD_GET(r, 20, 20); 3460 hfp_blanking_mode = FLD_GET(r, 21, 21); 3461 hbp_blanking_mode = FLD_GET(r, 22, 22); 3462 hsa_blanking_mode = FLD_GET(r, 23, 23); 3463 3464 r = dsi_read_reg(dsidev, DSI_VM_TIMING1); 3465 hbp = FLD_GET(r, 11, 0); 3466 hfp = FLD_GET(r, 23, 12); 3467 hsa = FLD_GET(r, 31, 24); 3468 3469 r = dsi_read_reg(dsidev, DSI_CLK_TIMING); 3470 ddr_clk_post = FLD_GET(r, 7, 0); 3471 ddr_clk_pre = FLD_GET(r, 15, 8); 3472 3473 r = dsi_read_reg(dsidev, DSI_VM_TIMING7); 3474 exit_hs_mode_lat = FLD_GET(r, 15, 0); 3475 enter_hs_mode_lat = FLD_GET(r, 31, 16); 3476 3477 r = dsi_read_reg(dsidev, DSI_CLK_CTRL); 3478 lp_clk_div = FLD_GET(r, 12, 0); 3479 ddr_alwon = FLD_GET(r, 13, 13); 3480 3481 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0); 3482 ths_exit = FLD_GET(r, 7, 0); 3483 3484 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1); 3485 tclk_trail = FLD_GET(r, 15, 8); 3486 3487 exiths_clk = ths_exit + tclk_trail; 3488 3489 width_bytes = DIV_ROUND_UP(timings->x_res * bpp, 8); 3490 bllp = hbp + hfp + hsa + DIV_ROUND_UP(width_bytes + 6, ndl); 3491 3492 if (!hsa_blanking_mode) { 3493 hsa_interleave_hs = dsi_compute_interleave_hs(hsa, ddr_alwon, 3494 enter_hs_mode_lat, exit_hs_mode_lat, 3495 exiths_clk, ddr_clk_pre, ddr_clk_post); 3496 hsa_interleave_lp = dsi_compute_interleave_lp(hsa, 3497 enter_hs_mode_lat, exit_hs_mode_lat, 3498 lp_clk_div, dsi_fclk_hsdiv); 3499 } 3500 3501 if (!hfp_blanking_mode) { 3502 hfp_interleave_hs = dsi_compute_interleave_hs(hfp, ddr_alwon, 3503 enter_hs_mode_lat, exit_hs_mode_lat, 3504 exiths_clk, ddr_clk_pre, ddr_clk_post); 3505 hfp_interleave_lp = dsi_compute_interleave_lp(hfp, 3506 enter_hs_mode_lat, exit_hs_mode_lat, 3507 lp_clk_div, dsi_fclk_hsdiv); 3508 } 3509 3510 if (!hbp_blanking_mode) { 3511 hbp_interleave_hs = dsi_compute_interleave_hs(hbp, ddr_alwon, 3512 enter_hs_mode_lat, exit_hs_mode_lat, 3513 exiths_clk, ddr_clk_pre, ddr_clk_post); 3514 3515 hbp_interleave_lp = dsi_compute_interleave_lp(hbp, 3516 enter_hs_mode_lat, exit_hs_mode_lat, 3517 lp_clk_div, dsi_fclk_hsdiv); 3518 } 3519 3520 if (!blanking_mode) { 3521 bl_interleave_hs = dsi_compute_interleave_hs(bllp, ddr_alwon, 3522 enter_hs_mode_lat, exit_hs_mode_lat, 3523 exiths_clk, ddr_clk_pre, ddr_clk_post); 3524 3525 bl_interleave_lp = dsi_compute_interleave_lp(bllp, 3526 enter_hs_mode_lat, exit_hs_mode_lat, 3527 lp_clk_div, dsi_fclk_hsdiv); 3528 } 3529 3530 DSSDBG("DSI HS interleaving(TXBYTECLKHS) HSA %d, HFP %d, HBP %d, BLLP %d\n", 3531 hsa_interleave_hs, hfp_interleave_hs, hbp_interleave_hs, 3532 bl_interleave_hs); 3533 3534 DSSDBG("DSI LP interleaving(bytes) HSA %d, HFP %d, HBP %d, BLLP %d\n", 3535 hsa_interleave_lp, hfp_interleave_lp, hbp_interleave_lp, 3536 bl_interleave_lp); 3537 3538 r = dsi_read_reg(dsidev, DSI_VM_TIMING4); 3539 r = FLD_MOD(r, hsa_interleave_hs, 23, 16); 3540 r = FLD_MOD(r, hfp_interleave_hs, 15, 8); 3541 r = FLD_MOD(r, hbp_interleave_hs, 7, 0); 3542 dsi_write_reg(dsidev, DSI_VM_TIMING4, r); 3543 3544 r = dsi_read_reg(dsidev, DSI_VM_TIMING5); 3545 r = FLD_MOD(r, hsa_interleave_lp, 23, 16); 3546 r = FLD_MOD(r, hfp_interleave_lp, 15, 8); 3547 r = FLD_MOD(r, hbp_interleave_lp, 7, 0); 3548 dsi_write_reg(dsidev, DSI_VM_TIMING5, r); 3549 3550 r = dsi_read_reg(dsidev, DSI_VM_TIMING6); 3551 r = FLD_MOD(r, bl_interleave_hs, 31, 15); 3552 r = FLD_MOD(r, bl_interleave_lp, 16, 0); 3553 dsi_write_reg(dsidev, DSI_VM_TIMING6, r); 3554 } 3555 3556 static int dsi_proto_config(struct platform_device *dsidev) 3557 { 3558 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 3559 u32 r; 3560 int buswidth = 0; 3561 3562 dsi_config_tx_fifo(dsidev, DSI_FIFO_SIZE_32, 3563 DSI_FIFO_SIZE_32, 3564 DSI_FIFO_SIZE_32, 3565 DSI_FIFO_SIZE_32); 3566 3567 dsi_config_rx_fifo(dsidev, DSI_FIFO_SIZE_32, 3568 DSI_FIFO_SIZE_32, 3569 DSI_FIFO_SIZE_32, 3570 DSI_FIFO_SIZE_32); 3571 3572 /* XXX what values for the timeouts? */ 3573 dsi_set_stop_state_counter(dsidev, 0x1000, false, false); 3574 dsi_set_ta_timeout(dsidev, 0x1fff, true, true); 3575 dsi_set_lp_rx_timeout(dsidev, 0x1fff, true, true); 3576 dsi_set_hs_tx_timeout(dsidev, 0x1fff, true, true); 3577 3578 switch (dsi_get_pixel_size(dsi->pix_fmt)) { 3579 case 16: 3580 buswidth = 0; 3581 break; 3582 case 18: 3583 buswidth = 1; 3584 break; 3585 case 24: 3586 buswidth = 2; 3587 break; 3588 default: 3589 BUG(); 3590 return -EINVAL; 3591 } 3592 3593 r = dsi_read_reg(dsidev, DSI_CTRL); 3594 r = FLD_MOD(r, 1, 1, 1); /* CS_RX_EN */ 3595 r = FLD_MOD(r, 1, 2, 2); /* ECC_RX_EN */ 3596 r = FLD_MOD(r, 1, 3, 3); /* TX_FIFO_ARBITRATION */ 3597 r = FLD_MOD(r, 1, 4, 4); /* VP_CLK_RATIO, always 1, see errata*/ 3598 r = FLD_MOD(r, buswidth, 7, 6); /* VP_DATA_BUS_WIDTH */ 3599 r = FLD_MOD(r, 0, 8, 8); /* VP_CLK_POL */ 3600 r = FLD_MOD(r, 1, 14, 14); /* TRIGGER_RESET_MODE */ 3601 r = FLD_MOD(r, 1, 19, 19); /* EOT_ENABLE */ 3602 if (!dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC)) { 3603 r = FLD_MOD(r, 1, 24, 24); /* DCS_CMD_ENABLE */ 3604 /* DCS_CMD_CODE, 1=start, 0=continue */ 3605 r = FLD_MOD(r, 0, 25, 25); 3606 } 3607 3608 dsi_write_reg(dsidev, DSI_CTRL, r); 3609 3610 dsi_config_vp_num_line_buffers(dsidev); 3611 3612 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) { 3613 dsi_config_vp_sync_events(dsidev); 3614 dsi_config_blanking_modes(dsidev); 3615 dsi_config_cmd_mode_interleaving(dsidev); 3616 } 3617 3618 dsi_vc_initial_config(dsidev, 0); 3619 dsi_vc_initial_config(dsidev, 1); 3620 dsi_vc_initial_config(dsidev, 2); 3621 dsi_vc_initial_config(dsidev, 3); 3622 3623 return 0; 3624 } 3625 3626 static void dsi_proto_timings(struct platform_device *dsidev) 3627 { 3628 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 3629 unsigned tlpx, tclk_zero, tclk_prepare; 3630 unsigned tclk_pre, tclk_post; 3631 unsigned ths_prepare, ths_prepare_ths_zero, ths_zero; 3632 unsigned ths_trail, ths_exit; 3633 unsigned ddr_clk_pre, ddr_clk_post; 3634 unsigned enter_hs_mode_lat, exit_hs_mode_lat; 3635 unsigned ths_eot; 3636 int ndl = dsi->num_lanes_used - 1; 3637 u32 r; 3638 3639 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0); 3640 ths_prepare = FLD_GET(r, 31, 24); 3641 ths_prepare_ths_zero = FLD_GET(r, 23, 16); 3642 ths_zero = ths_prepare_ths_zero - ths_prepare; 3643 ths_trail = FLD_GET(r, 15, 8); 3644 ths_exit = FLD_GET(r, 7, 0); 3645 3646 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1); 3647 tlpx = FLD_GET(r, 20, 16) * 2; 3648 tclk_zero = FLD_GET(r, 7, 0); 3649 3650 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG2); 3651 tclk_prepare = FLD_GET(r, 7, 0); 3652 3653 /* min 8*UI */ 3654 tclk_pre = 20; 3655 /* min 60ns + 52*UI */ 3656 tclk_post = ns2ddr(dsidev, 60) + 26; 3657 3658 ths_eot = DIV_ROUND_UP(4, ndl); 3659 3660 ddr_clk_pre = DIV_ROUND_UP(tclk_pre + tlpx + tclk_zero + tclk_prepare, 3661 4); 3662 ddr_clk_post = DIV_ROUND_UP(tclk_post + ths_trail, 4) + ths_eot; 3663 3664 BUG_ON(ddr_clk_pre == 0 || ddr_clk_pre > 255); 3665 BUG_ON(ddr_clk_post == 0 || ddr_clk_post > 255); 3666 3667 r = dsi_read_reg(dsidev, DSI_CLK_TIMING); 3668 r = FLD_MOD(r, ddr_clk_pre, 15, 8); 3669 r = FLD_MOD(r, ddr_clk_post, 7, 0); 3670 dsi_write_reg(dsidev, DSI_CLK_TIMING, r); 3671 3672 DSSDBG("ddr_clk_pre %u, ddr_clk_post %u\n", 3673 ddr_clk_pre, 3674 ddr_clk_post); 3675 3676 enter_hs_mode_lat = 1 + DIV_ROUND_UP(tlpx, 4) + 3677 DIV_ROUND_UP(ths_prepare, 4) + 3678 DIV_ROUND_UP(ths_zero + 3, 4); 3679 3680 exit_hs_mode_lat = DIV_ROUND_UP(ths_trail + ths_exit, 4) + 1 + ths_eot; 3681 3682 r = FLD_VAL(enter_hs_mode_lat, 31, 16) | 3683 FLD_VAL(exit_hs_mode_lat, 15, 0); 3684 dsi_write_reg(dsidev, DSI_VM_TIMING7, r); 3685 3686 DSSDBG("enter_hs_mode_lat %u, exit_hs_mode_lat %u\n", 3687 enter_hs_mode_lat, exit_hs_mode_lat); 3688 3689 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) { 3690 /* TODO: Implement a video mode check_timings function */ 3691 int hsa = dsi->vm_timings.hsa; 3692 int hfp = dsi->vm_timings.hfp; 3693 int hbp = dsi->vm_timings.hbp; 3694 int vsa = dsi->vm_timings.vsa; 3695 int vfp = dsi->vm_timings.vfp; 3696 int vbp = dsi->vm_timings.vbp; 3697 int window_sync = dsi->vm_timings.window_sync; 3698 bool hsync_end; 3699 struct omap_video_timings *timings = &dsi->timings; 3700 int bpp = dsi_get_pixel_size(dsi->pix_fmt); 3701 int tl, t_he, width_bytes; 3702 3703 hsync_end = dsi->vm_timings.trans_mode == OMAP_DSS_DSI_PULSE_MODE; 3704 t_he = hsync_end ? 3705 ((hsa == 0 && ndl == 3) ? 1 : DIV_ROUND_UP(4, ndl)) : 0; 3706 3707 width_bytes = DIV_ROUND_UP(timings->x_res * bpp, 8); 3708 3709 /* TL = t_HS + HSA + t_HE + HFP + ceil((WC + 6) / NDL) + HBP */ 3710 tl = DIV_ROUND_UP(4, ndl) + (hsync_end ? hsa : 0) + t_he + hfp + 3711 DIV_ROUND_UP(width_bytes + 6, ndl) + hbp; 3712 3713 DSSDBG("HBP: %d, HFP: %d, HSA: %d, TL: %d TXBYTECLKHS\n", hbp, 3714 hfp, hsync_end ? hsa : 0, tl); 3715 DSSDBG("VBP: %d, VFP: %d, VSA: %d, VACT: %d lines\n", vbp, vfp, 3716 vsa, timings->y_res); 3717 3718 r = dsi_read_reg(dsidev, DSI_VM_TIMING1); 3719 r = FLD_MOD(r, hbp, 11, 0); /* HBP */ 3720 r = FLD_MOD(r, hfp, 23, 12); /* HFP */ 3721 r = FLD_MOD(r, hsync_end ? hsa : 0, 31, 24); /* HSA */ 3722 dsi_write_reg(dsidev, DSI_VM_TIMING1, r); 3723 3724 r = dsi_read_reg(dsidev, DSI_VM_TIMING2); 3725 r = FLD_MOD(r, vbp, 7, 0); /* VBP */ 3726 r = FLD_MOD(r, vfp, 15, 8); /* VFP */ 3727 r = FLD_MOD(r, vsa, 23, 16); /* VSA */ 3728 r = FLD_MOD(r, window_sync, 27, 24); /* WINDOW_SYNC */ 3729 dsi_write_reg(dsidev, DSI_VM_TIMING2, r); 3730 3731 r = dsi_read_reg(dsidev, DSI_VM_TIMING3); 3732 r = FLD_MOD(r, timings->y_res, 14, 0); /* VACT */ 3733 r = FLD_MOD(r, tl, 31, 16); /* TL */ 3734 dsi_write_reg(dsidev, DSI_VM_TIMING3, r); 3735 } 3736 } 3737 3738 static int dsi_configure_pins(struct omap_dss_device *dssdev, 3739 const struct omap_dsi_pin_config *pin_cfg) 3740 { 3741 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 3742 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 3743 int num_pins; 3744 const int *pins; 3745 struct dsi_lane_config lanes[DSI_MAX_NR_LANES]; 3746 int num_lanes; 3747 int i; 3748 3749 static const enum dsi_lane_function functions[] = { 3750 DSI_LANE_CLK, 3751 DSI_LANE_DATA1, 3752 DSI_LANE_DATA2, 3753 DSI_LANE_DATA3, 3754 DSI_LANE_DATA4, 3755 }; 3756 3757 num_pins = pin_cfg->num_pins; 3758 pins = pin_cfg->pins; 3759 3760 if (num_pins < 4 || num_pins > dsi->num_lanes_supported * 2 3761 || num_pins % 2 != 0) 3762 return -EINVAL; 3763 3764 for (i = 0; i < DSI_MAX_NR_LANES; ++i) 3765 lanes[i].function = DSI_LANE_UNUSED; 3766 3767 num_lanes = 0; 3768 3769 for (i = 0; i < num_pins; i += 2) { 3770 u8 lane, pol; 3771 int dx, dy; 3772 3773 dx = pins[i]; 3774 dy = pins[i + 1]; 3775 3776 if (dx < 0 || dx >= dsi->num_lanes_supported * 2) 3777 return -EINVAL; 3778 3779 if (dy < 0 || dy >= dsi->num_lanes_supported * 2) 3780 return -EINVAL; 3781 3782 if (dx & 1) { 3783 if (dy != dx - 1) 3784 return -EINVAL; 3785 pol = 1; 3786 } else { 3787 if (dy != dx + 1) 3788 return -EINVAL; 3789 pol = 0; 3790 } 3791 3792 lane = dx / 2; 3793 3794 lanes[lane].function = functions[i / 2]; 3795 lanes[lane].polarity = pol; 3796 num_lanes++; 3797 } 3798 3799 memcpy(dsi->lanes, lanes, sizeof(dsi->lanes)); 3800 dsi->num_lanes_used = num_lanes; 3801 3802 return 0; 3803 } 3804 3805 static int dsi_enable_video_output(struct omap_dss_device *dssdev, int channel) 3806 { 3807 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 3808 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 3809 struct omap_overlay_manager *mgr = dsi->output.manager; 3810 int bpp = dsi_get_pixel_size(dsi->pix_fmt); 3811 struct omap_dss_device *out = &dsi->output; 3812 u8 data_type; 3813 u16 word_count; 3814 int r; 3815 3816 if (out->manager == NULL) { 3817 DSSERR("failed to enable display: no output/manager\n"); 3818 return -ENODEV; 3819 } 3820 3821 r = dsi_display_init_dispc(dsidev, mgr); 3822 if (r) 3823 goto err_init_dispc; 3824 3825 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) { 3826 switch (dsi->pix_fmt) { 3827 case OMAP_DSS_DSI_FMT_RGB888: 3828 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_24; 3829 break; 3830 case OMAP_DSS_DSI_FMT_RGB666: 3831 data_type = MIPI_DSI_PIXEL_STREAM_3BYTE_18; 3832 break; 3833 case OMAP_DSS_DSI_FMT_RGB666_PACKED: 3834 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_18; 3835 break; 3836 case OMAP_DSS_DSI_FMT_RGB565: 3837 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_16; 3838 break; 3839 default: 3840 r = -EINVAL; 3841 goto err_pix_fmt; 3842 } 3843 3844 dsi_if_enable(dsidev, false); 3845 dsi_vc_enable(dsidev, channel, false); 3846 3847 /* MODE, 1 = video mode */ 3848 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 1, 4, 4); 3849 3850 word_count = DIV_ROUND_UP(dsi->timings.x_res * bpp, 8); 3851 3852 dsi_vc_write_long_header(dsidev, channel, data_type, 3853 word_count, 0); 3854 3855 dsi_vc_enable(dsidev, channel, true); 3856 dsi_if_enable(dsidev, true); 3857 } 3858 3859 r = dss_mgr_enable(mgr); 3860 if (r) 3861 goto err_mgr_enable; 3862 3863 return 0; 3864 3865 err_mgr_enable: 3866 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) { 3867 dsi_if_enable(dsidev, false); 3868 dsi_vc_enable(dsidev, channel, false); 3869 } 3870 err_pix_fmt: 3871 dsi_display_uninit_dispc(dsidev, mgr); 3872 err_init_dispc: 3873 return r; 3874 } 3875 3876 static void dsi_disable_video_output(struct omap_dss_device *dssdev, int channel) 3877 { 3878 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 3879 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 3880 struct omap_overlay_manager *mgr = dsi->output.manager; 3881 3882 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) { 3883 dsi_if_enable(dsidev, false); 3884 dsi_vc_enable(dsidev, channel, false); 3885 3886 /* MODE, 0 = command mode */ 3887 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 0, 4, 4); 3888 3889 dsi_vc_enable(dsidev, channel, true); 3890 dsi_if_enable(dsidev, true); 3891 } 3892 3893 dss_mgr_disable(mgr); 3894 3895 dsi_display_uninit_dispc(dsidev, mgr); 3896 } 3897 3898 static void dsi_update_screen_dispc(struct platform_device *dsidev) 3899 { 3900 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 3901 struct omap_overlay_manager *mgr = dsi->output.manager; 3902 unsigned bytespp; 3903 unsigned bytespl; 3904 unsigned bytespf; 3905 unsigned total_len; 3906 unsigned packet_payload; 3907 unsigned packet_len; 3908 u32 l; 3909 int r; 3910 const unsigned channel = dsi->update_channel; 3911 const unsigned line_buf_size = dsi->line_buffer_size; 3912 u16 w = dsi->timings.x_res; 3913 u16 h = dsi->timings.y_res; 3914 3915 DSSDBG("dsi_update_screen_dispc(%dx%d)\n", w, h); 3916 3917 dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_VP); 3918 3919 bytespp = dsi_get_pixel_size(dsi->pix_fmt) / 8; 3920 bytespl = w * bytespp; 3921 bytespf = bytespl * h; 3922 3923 /* NOTE: packet_payload has to be equal to N * bytespl, where N is 3924 * number of lines in a packet. See errata about VP_CLK_RATIO */ 3925 3926 if (bytespf < line_buf_size) 3927 packet_payload = bytespf; 3928 else 3929 packet_payload = (line_buf_size) / bytespl * bytespl; 3930 3931 packet_len = packet_payload + 1; /* 1 byte for DCS cmd */ 3932 total_len = (bytespf / packet_payload) * packet_len; 3933 3934 if (bytespf % packet_payload) 3935 total_len += (bytespf % packet_payload) + 1; 3936 3937 l = FLD_VAL(total_len, 23, 0); /* TE_SIZE */ 3938 dsi_write_reg(dsidev, DSI_VC_TE(channel), l); 3939 3940 dsi_vc_write_long_header(dsidev, channel, MIPI_DSI_DCS_LONG_WRITE, 3941 packet_len, 0); 3942 3943 if (dsi->te_enabled) 3944 l = FLD_MOD(l, 1, 30, 30); /* TE_EN */ 3945 else 3946 l = FLD_MOD(l, 1, 31, 31); /* TE_START */ 3947 dsi_write_reg(dsidev, DSI_VC_TE(channel), l); 3948 3949 /* We put SIDLEMODE to no-idle for the duration of the transfer, 3950 * because DSS interrupts are not capable of waking up the CPU and the 3951 * framedone interrupt could be delayed for quite a long time. I think 3952 * the same goes for any DSS interrupts, but for some reason I have not 3953 * seen the problem anywhere else than here. 3954 */ 3955 dispc_disable_sidle(); 3956 3957 dsi_perf_mark_start(dsidev); 3958 3959 r = schedule_delayed_work(&dsi->framedone_timeout_work, 3960 msecs_to_jiffies(250)); 3961 BUG_ON(r == 0); 3962 3963 dss_mgr_set_timings(mgr, &dsi->timings); 3964 3965 dss_mgr_start_update(mgr); 3966 3967 if (dsi->te_enabled) { 3968 /* disable LP_RX_TO, so that we can receive TE. Time to wait 3969 * for TE is longer than the timer allows */ 3970 REG_FLD_MOD(dsidev, DSI_TIMING2, 0, 15, 15); /* LP_RX_TO */ 3971 3972 dsi_vc_send_bta(dsidev, channel); 3973 3974 #ifdef DSI_CATCH_MISSING_TE 3975 mod_timer(&dsi->te_timer, jiffies + msecs_to_jiffies(250)); 3976 #endif 3977 } 3978 } 3979 3980 #ifdef DSI_CATCH_MISSING_TE 3981 static void dsi_te_timeout(struct timer_list *unused) 3982 { 3983 DSSERR("TE not received for 250ms!\n"); 3984 } 3985 #endif 3986 3987 static void dsi_handle_framedone(struct platform_device *dsidev, int error) 3988 { 3989 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 3990 3991 /* SIDLEMODE back to smart-idle */ 3992 dispc_enable_sidle(); 3993 3994 if (dsi->te_enabled) { 3995 /* enable LP_RX_TO again after the TE */ 3996 REG_FLD_MOD(dsidev, DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */ 3997 } 3998 3999 dsi->framedone_callback(error, dsi->framedone_data); 4000 4001 if (!error) 4002 dsi_perf_show(dsidev, "DISPC"); 4003 } 4004 4005 static void dsi_framedone_timeout_work_callback(struct work_struct *work) 4006 { 4007 struct dsi_data *dsi = container_of(work, struct dsi_data, 4008 framedone_timeout_work.work); 4009 /* XXX While extremely unlikely, we could get FRAMEDONE interrupt after 4010 * 250ms which would conflict with this timeout work. What should be 4011 * done is first cancel the transfer on the HW, and then cancel the 4012 * possibly scheduled framedone work. However, cancelling the transfer 4013 * on the HW is buggy, and would probably require resetting the whole 4014 * DSI */ 4015 4016 DSSERR("Framedone not received for 250ms!\n"); 4017 4018 dsi_handle_framedone(dsi->pdev, -ETIMEDOUT); 4019 } 4020 4021 static void dsi_framedone_irq_callback(void *data) 4022 { 4023 struct platform_device *dsidev = (struct platform_device *) data; 4024 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 4025 4026 /* Note: We get FRAMEDONE when DISPC has finished sending pixels and 4027 * turns itself off. However, DSI still has the pixels in its buffers, 4028 * and is sending the data. 4029 */ 4030 4031 cancel_delayed_work(&dsi->framedone_timeout_work); 4032 4033 dsi_handle_framedone(dsidev, 0); 4034 } 4035 4036 static int dsi_update(struct omap_dss_device *dssdev, int channel, 4037 void (*callback)(int, void *), void *data) 4038 { 4039 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 4040 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 4041 4042 dsi_perf_mark_setup(dsidev); 4043 4044 dsi->update_channel = channel; 4045 4046 dsi->framedone_callback = callback; 4047 dsi->framedone_data = data; 4048 4049 #ifdef DSI_PERF_MEASURE 4050 dsi->update_bytes = dsi->timings.x_res * dsi->timings.y_res * 4051 dsi_get_pixel_size(dsi->pix_fmt) / 8; 4052 #endif 4053 dsi_update_screen_dispc(dsidev); 4054 4055 return 0; 4056 } 4057 4058 /* Display funcs */ 4059 4060 static int dsi_configure_dispc_clocks(struct platform_device *dsidev) 4061 { 4062 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 4063 struct dispc_clock_info dispc_cinfo; 4064 int r; 4065 unsigned long fck; 4066 4067 fck = dsi_get_pll_hsdiv_dispc_rate(dsidev); 4068 4069 dispc_cinfo.lck_div = dsi->user_dispc_cinfo.lck_div; 4070 dispc_cinfo.pck_div = dsi->user_dispc_cinfo.pck_div; 4071 4072 r = dispc_calc_clock_rates(fck, &dispc_cinfo); 4073 if (r) { 4074 DSSERR("Failed to calc dispc clocks\n"); 4075 return r; 4076 } 4077 4078 dsi->mgr_config.clock_info = dispc_cinfo; 4079 4080 return 0; 4081 } 4082 4083 static int dsi_display_init_dispc(struct platform_device *dsidev, 4084 struct omap_overlay_manager *mgr) 4085 { 4086 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 4087 int r; 4088 4089 dss_select_lcd_clk_source(mgr->id, dsi->module_id == 0 ? 4090 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC : 4091 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC); 4092 4093 if (dsi->mode == OMAP_DSS_DSI_CMD_MODE) { 4094 r = dss_mgr_register_framedone_handler(mgr, 4095 dsi_framedone_irq_callback, dsidev); 4096 if (r) { 4097 DSSERR("can't register FRAMEDONE handler\n"); 4098 goto err; 4099 } 4100 4101 dsi->mgr_config.stallmode = true; 4102 dsi->mgr_config.fifohandcheck = true; 4103 } else { 4104 dsi->mgr_config.stallmode = false; 4105 dsi->mgr_config.fifohandcheck = false; 4106 } 4107 4108 /* 4109 * override interlace, logic level and edge related parameters in 4110 * omap_video_timings with default values 4111 */ 4112 dsi->timings.interlace = false; 4113 dsi->timings.hsync_level = OMAPDSS_SIG_ACTIVE_HIGH; 4114 dsi->timings.vsync_level = OMAPDSS_SIG_ACTIVE_HIGH; 4115 dsi->timings.data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE; 4116 dsi->timings.de_level = OMAPDSS_SIG_ACTIVE_HIGH; 4117 dsi->timings.sync_pclk_edge = OMAPDSS_DRIVE_SIG_FALLING_EDGE; 4118 4119 dss_mgr_set_timings(mgr, &dsi->timings); 4120 4121 r = dsi_configure_dispc_clocks(dsidev); 4122 if (r) 4123 goto err1; 4124 4125 dsi->mgr_config.io_pad_mode = DSS_IO_PAD_MODE_BYPASS; 4126 dsi->mgr_config.video_port_width = 4127 dsi_get_pixel_size(dsi->pix_fmt); 4128 dsi->mgr_config.lcden_sig_polarity = 0; 4129 4130 dss_mgr_set_lcd_config(mgr, &dsi->mgr_config); 4131 4132 return 0; 4133 err1: 4134 if (dsi->mode == OMAP_DSS_DSI_CMD_MODE) 4135 dss_mgr_unregister_framedone_handler(mgr, 4136 dsi_framedone_irq_callback, dsidev); 4137 err: 4138 dss_select_lcd_clk_source(mgr->id, OMAP_DSS_CLK_SRC_FCK); 4139 return r; 4140 } 4141 4142 static void dsi_display_uninit_dispc(struct platform_device *dsidev, 4143 struct omap_overlay_manager *mgr) 4144 { 4145 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 4146 4147 if (dsi->mode == OMAP_DSS_DSI_CMD_MODE) 4148 dss_mgr_unregister_framedone_handler(mgr, 4149 dsi_framedone_irq_callback, dsidev); 4150 4151 dss_select_lcd_clk_source(mgr->id, OMAP_DSS_CLK_SRC_FCK); 4152 } 4153 4154 static int dsi_configure_dsi_clocks(struct platform_device *dsidev) 4155 { 4156 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 4157 struct dss_pll_clock_info cinfo; 4158 int r; 4159 4160 cinfo = dsi->user_dsi_cinfo; 4161 4162 r = dss_pll_set_config(&dsi->pll, &cinfo); 4163 if (r) { 4164 DSSERR("Failed to set dsi clocks\n"); 4165 return r; 4166 } 4167 4168 return 0; 4169 } 4170 4171 static int dsi_display_init_dsi(struct platform_device *dsidev) 4172 { 4173 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 4174 int r; 4175 4176 r = dss_pll_enable(&dsi->pll); 4177 if (r) 4178 goto err0; 4179 4180 r = dsi_configure_dsi_clocks(dsidev); 4181 if (r) 4182 goto err1; 4183 4184 dss_select_dsi_clk_source(dsi->module_id, dsi->module_id == 0 ? 4185 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI : 4186 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI); 4187 4188 DSSDBG("PLL OK\n"); 4189 4190 r = dsi_cio_init(dsidev); 4191 if (r) 4192 goto err2; 4193 4194 _dsi_print_reset_status(dsidev); 4195 4196 dsi_proto_timings(dsidev); 4197 dsi_set_lp_clk_divisor(dsidev); 4198 4199 if (1) 4200 _dsi_print_reset_status(dsidev); 4201 4202 r = dsi_proto_config(dsidev); 4203 if (r) 4204 goto err3; 4205 4206 /* enable interface */ 4207 dsi_vc_enable(dsidev, 0, 1); 4208 dsi_vc_enable(dsidev, 1, 1); 4209 dsi_vc_enable(dsidev, 2, 1); 4210 dsi_vc_enable(dsidev, 3, 1); 4211 dsi_if_enable(dsidev, 1); 4212 dsi_force_tx_stop_mode_io(dsidev); 4213 4214 return 0; 4215 err3: 4216 dsi_cio_uninit(dsidev); 4217 err2: 4218 dss_select_dsi_clk_source(dsi->module_id, OMAP_DSS_CLK_SRC_FCK); 4219 err1: 4220 dss_pll_disable(&dsi->pll); 4221 err0: 4222 return r; 4223 } 4224 4225 static void dsi_display_uninit_dsi(struct platform_device *dsidev, 4226 bool disconnect_lanes, bool enter_ulps) 4227 { 4228 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 4229 4230 if (enter_ulps && !dsi->ulps_enabled) 4231 dsi_enter_ulps(dsidev); 4232 4233 /* disable interface */ 4234 dsi_if_enable(dsidev, 0); 4235 dsi_vc_enable(dsidev, 0, 0); 4236 dsi_vc_enable(dsidev, 1, 0); 4237 dsi_vc_enable(dsidev, 2, 0); 4238 dsi_vc_enable(dsidev, 3, 0); 4239 4240 dss_select_dsi_clk_source(dsi->module_id, OMAP_DSS_CLK_SRC_FCK); 4241 dsi_cio_uninit(dsidev); 4242 dsi_pll_uninit(dsidev, disconnect_lanes); 4243 } 4244 4245 static int dsi_display_enable(struct omap_dss_device *dssdev) 4246 { 4247 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 4248 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 4249 int r = 0; 4250 4251 DSSDBG("dsi_display_enable\n"); 4252 4253 WARN_ON(!dsi_bus_is_locked(dsidev)); 4254 4255 mutex_lock(&dsi->lock); 4256 4257 r = dsi_runtime_get(dsidev); 4258 if (r) 4259 goto err_get_dsi; 4260 4261 _dsi_initialize_irq(dsidev); 4262 4263 r = dsi_display_init_dsi(dsidev); 4264 if (r) 4265 goto err_init_dsi; 4266 4267 mutex_unlock(&dsi->lock); 4268 4269 return 0; 4270 4271 err_init_dsi: 4272 dsi_runtime_put(dsidev); 4273 err_get_dsi: 4274 mutex_unlock(&dsi->lock); 4275 DSSDBG("dsi_display_enable FAILED\n"); 4276 return r; 4277 } 4278 4279 static void dsi_display_disable(struct omap_dss_device *dssdev, 4280 bool disconnect_lanes, bool enter_ulps) 4281 { 4282 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 4283 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 4284 4285 DSSDBG("dsi_display_disable\n"); 4286 4287 WARN_ON(!dsi_bus_is_locked(dsidev)); 4288 4289 mutex_lock(&dsi->lock); 4290 4291 dsi_sync_vc(dsidev, 0); 4292 dsi_sync_vc(dsidev, 1); 4293 dsi_sync_vc(dsidev, 2); 4294 dsi_sync_vc(dsidev, 3); 4295 4296 dsi_display_uninit_dsi(dsidev, disconnect_lanes, enter_ulps); 4297 4298 dsi_runtime_put(dsidev); 4299 4300 mutex_unlock(&dsi->lock); 4301 } 4302 4303 static int dsi_enable_te(struct omap_dss_device *dssdev, bool enable) 4304 { 4305 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 4306 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 4307 4308 dsi->te_enabled = enable; 4309 return 0; 4310 } 4311 4312 #ifdef PRINT_VERBOSE_VM_TIMINGS 4313 static void print_dsi_vm(const char *str, 4314 const struct omap_dss_dsi_videomode_timings *t) 4315 { 4316 unsigned long byteclk = t->hsclk / 4; 4317 int bl, wc, pps, tot; 4318 4319 wc = DIV_ROUND_UP(t->hact * t->bitspp, 8); 4320 pps = DIV_ROUND_UP(wc + 6, t->ndl); /* pixel packet size */ 4321 bl = t->hss + t->hsa + t->hse + t->hbp + t->hfp; 4322 tot = bl + pps; 4323 4324 #define TO_DSI_T(x) ((u32)div64_u64((u64)x * 1000000000llu, byteclk)) 4325 4326 pr_debug("%s bck %lu, %u/%u/%u/%u/%u/%u = %u+%u = %u, " 4327 "%u/%u/%u/%u/%u/%u = %u + %u = %u\n", 4328 str, 4329 byteclk, 4330 t->hss, t->hsa, t->hse, t->hbp, pps, t->hfp, 4331 bl, pps, tot, 4332 TO_DSI_T(t->hss), 4333 TO_DSI_T(t->hsa), 4334 TO_DSI_T(t->hse), 4335 TO_DSI_T(t->hbp), 4336 TO_DSI_T(pps), 4337 TO_DSI_T(t->hfp), 4338 4339 TO_DSI_T(bl), 4340 TO_DSI_T(pps), 4341 4342 TO_DSI_T(tot)); 4343 #undef TO_DSI_T 4344 } 4345 4346 static void print_dispc_vm(const char *str, const struct omap_video_timings *t) 4347 { 4348 unsigned long pck = t->pixelclock; 4349 int hact, bl, tot; 4350 4351 hact = t->x_res; 4352 bl = t->hsw + t->hbp + t->hfp; 4353 tot = hact + bl; 4354 4355 #define TO_DISPC_T(x) ((u32)div64_u64((u64)x * 1000000000llu, pck)) 4356 4357 pr_debug("%s pck %lu, %u/%u/%u/%u = %u+%u = %u, " 4358 "%u/%u/%u/%u = %u + %u = %u\n", 4359 str, 4360 pck, 4361 t->hsw, t->hbp, hact, t->hfp, 4362 bl, hact, tot, 4363 TO_DISPC_T(t->hsw), 4364 TO_DISPC_T(t->hbp), 4365 TO_DISPC_T(hact), 4366 TO_DISPC_T(t->hfp), 4367 TO_DISPC_T(bl), 4368 TO_DISPC_T(hact), 4369 TO_DISPC_T(tot)); 4370 #undef TO_DISPC_T 4371 } 4372 4373 /* note: this is not quite accurate */ 4374 static void print_dsi_dispc_vm(const char *str, 4375 const struct omap_dss_dsi_videomode_timings *t) 4376 { 4377 struct omap_video_timings vm = { 0 }; 4378 unsigned long byteclk = t->hsclk / 4; 4379 unsigned long pck; 4380 u64 dsi_tput; 4381 int dsi_hact, dsi_htot; 4382 4383 dsi_tput = (u64)byteclk * t->ndl * 8; 4384 pck = (u32)div64_u64(dsi_tput, t->bitspp); 4385 dsi_hact = DIV_ROUND_UP(DIV_ROUND_UP(t->hact * t->bitspp, 8) + 6, t->ndl); 4386 dsi_htot = t->hss + t->hsa + t->hse + t->hbp + dsi_hact + t->hfp; 4387 4388 vm.pixelclock = pck; 4389 vm.hsw = div64_u64((u64)(t->hsa + t->hse) * pck, byteclk); 4390 vm.hbp = div64_u64((u64)t->hbp * pck, byteclk); 4391 vm.hfp = div64_u64((u64)t->hfp * pck, byteclk); 4392 vm.x_res = t->hact; 4393 4394 print_dispc_vm(str, &vm); 4395 } 4396 #endif /* PRINT_VERBOSE_VM_TIMINGS */ 4397 4398 static bool dsi_cm_calc_dispc_cb(int lckd, int pckd, unsigned long lck, 4399 unsigned long pck, void *data) 4400 { 4401 struct dsi_clk_calc_ctx *ctx = data; 4402 struct omap_video_timings *t = &ctx->dispc_vm; 4403 4404 ctx->dispc_cinfo.lck_div = lckd; 4405 ctx->dispc_cinfo.pck_div = pckd; 4406 ctx->dispc_cinfo.lck = lck; 4407 ctx->dispc_cinfo.pck = pck; 4408 4409 *t = *ctx->config->timings; 4410 t->pixelclock = pck; 4411 t->x_res = ctx->config->timings->x_res; 4412 t->y_res = ctx->config->timings->y_res; 4413 t->hsw = t->hfp = t->hbp = t->vsw = 1; 4414 t->vfp = t->vbp = 0; 4415 4416 return true; 4417 } 4418 4419 static bool dsi_cm_calc_hsdiv_cb(int m_dispc, unsigned long dispc, 4420 void *data) 4421 { 4422 struct dsi_clk_calc_ctx *ctx = data; 4423 4424 ctx->dsi_cinfo.mX[HSDIV_DISPC] = m_dispc; 4425 ctx->dsi_cinfo.clkout[HSDIV_DISPC] = dispc; 4426 4427 return dispc_div_calc(dispc, ctx->req_pck_min, ctx->req_pck_max, 4428 dsi_cm_calc_dispc_cb, ctx); 4429 } 4430 4431 static bool dsi_cm_calc_pll_cb(int n, int m, unsigned long fint, 4432 unsigned long clkdco, void *data) 4433 { 4434 struct dsi_clk_calc_ctx *ctx = data; 4435 4436 ctx->dsi_cinfo.n = n; 4437 ctx->dsi_cinfo.m = m; 4438 ctx->dsi_cinfo.fint = fint; 4439 ctx->dsi_cinfo.clkdco = clkdco; 4440 4441 return dss_pll_hsdiv_calc(ctx->pll, clkdco, ctx->req_pck_min, 4442 dss_feat_get_param_max(FEAT_PARAM_DSS_FCK), 4443 dsi_cm_calc_hsdiv_cb, ctx); 4444 } 4445 4446 static bool dsi_cm_calc(struct dsi_data *dsi, 4447 const struct omap_dss_dsi_config *cfg, 4448 struct dsi_clk_calc_ctx *ctx) 4449 { 4450 unsigned long clkin; 4451 int bitspp, ndl; 4452 unsigned long pll_min, pll_max; 4453 unsigned long pck, txbyteclk; 4454 4455 clkin = clk_get_rate(dsi->pll.clkin); 4456 bitspp = dsi_get_pixel_size(cfg->pixel_format); 4457 ndl = dsi->num_lanes_used - 1; 4458 4459 /* 4460 * Here we should calculate minimum txbyteclk to be able to send the 4461 * frame in time, and also to handle TE. That's not very simple, though, 4462 * especially as we go to LP between each pixel packet due to HW 4463 * "feature". So let's just estimate very roughly and multiply by 1.5. 4464 */ 4465 pck = cfg->timings->pixelclock; 4466 pck = pck * 3 / 2; 4467 txbyteclk = pck * bitspp / 8 / ndl; 4468 4469 memset(ctx, 0, sizeof(*ctx)); 4470 ctx->dsidev = dsi->pdev; 4471 ctx->pll = &dsi->pll; 4472 ctx->config = cfg; 4473 ctx->req_pck_min = pck; 4474 ctx->req_pck_nom = pck; 4475 ctx->req_pck_max = pck * 3 / 2; 4476 4477 pll_min = max(cfg->hs_clk_min * 4, txbyteclk * 4 * 4); 4478 pll_max = cfg->hs_clk_max * 4; 4479 4480 return dss_pll_calc(ctx->pll, clkin, 4481 pll_min, pll_max, 4482 dsi_cm_calc_pll_cb, ctx); 4483 } 4484 4485 static bool dsi_vm_calc_blanking(struct dsi_clk_calc_ctx *ctx) 4486 { 4487 struct dsi_data *dsi = dsi_get_dsidrv_data(ctx->dsidev); 4488 const struct omap_dss_dsi_config *cfg = ctx->config; 4489 int bitspp = dsi_get_pixel_size(cfg->pixel_format); 4490 int ndl = dsi->num_lanes_used - 1; 4491 unsigned long hsclk = ctx->dsi_cinfo.clkdco / 4; 4492 unsigned long byteclk = hsclk / 4; 4493 4494 unsigned long dispc_pck, req_pck_min, req_pck_nom, req_pck_max; 4495 int xres; 4496 int panel_htot, panel_hbl; /* pixels */ 4497 int dispc_htot, dispc_hbl; /* pixels */ 4498 int dsi_htot, dsi_hact, dsi_hbl, hss, hse; /* byteclks */ 4499 int hfp, hsa, hbp; 4500 const struct omap_video_timings *req_vm; 4501 struct omap_video_timings *dispc_vm; 4502 struct omap_dss_dsi_videomode_timings *dsi_vm; 4503 u64 dsi_tput, dispc_tput; 4504 4505 dsi_tput = (u64)byteclk * ndl * 8; 4506 4507 req_vm = cfg->timings; 4508 req_pck_min = ctx->req_pck_min; 4509 req_pck_max = ctx->req_pck_max; 4510 req_pck_nom = ctx->req_pck_nom; 4511 4512 dispc_pck = ctx->dispc_cinfo.pck; 4513 dispc_tput = (u64)dispc_pck * bitspp; 4514 4515 xres = req_vm->x_res; 4516 4517 panel_hbl = req_vm->hfp + req_vm->hbp + req_vm->hsw; 4518 panel_htot = xres + panel_hbl; 4519 4520 dsi_hact = DIV_ROUND_UP(DIV_ROUND_UP(xres * bitspp, 8) + 6, ndl); 4521 4522 /* 4523 * When there are no line buffers, DISPC and DSI must have the 4524 * same tput. Otherwise DISPC tput needs to be higher than DSI's. 4525 */ 4526 if (dsi->line_buffer_size < xres * bitspp / 8) { 4527 if (dispc_tput != dsi_tput) 4528 return false; 4529 } else { 4530 if (dispc_tput < dsi_tput) 4531 return false; 4532 } 4533 4534 /* DSI tput must be over the min requirement */ 4535 if (dsi_tput < (u64)bitspp * req_pck_min) 4536 return false; 4537 4538 /* When non-burst mode, DSI tput must be below max requirement. */ 4539 if (cfg->trans_mode != OMAP_DSS_DSI_BURST_MODE) { 4540 if (dsi_tput > (u64)bitspp * req_pck_max) 4541 return false; 4542 } 4543 4544 hss = DIV_ROUND_UP(4, ndl); 4545 4546 if (cfg->trans_mode == OMAP_DSS_DSI_PULSE_MODE) { 4547 if (ndl == 3 && req_vm->hsw == 0) 4548 hse = 1; 4549 else 4550 hse = DIV_ROUND_UP(4, ndl); 4551 } else { 4552 hse = 0; 4553 } 4554 4555 /* DSI htot to match the panel's nominal pck */ 4556 dsi_htot = div64_u64((u64)panel_htot * byteclk, req_pck_nom); 4557 4558 /* fail if there would be no time for blanking */ 4559 if (dsi_htot < hss + hse + dsi_hact) 4560 return false; 4561 4562 /* total DSI blanking needed to achieve panel's TL */ 4563 dsi_hbl = dsi_htot - dsi_hact; 4564 4565 /* DISPC htot to match the DSI TL */ 4566 dispc_htot = div64_u64((u64)dsi_htot * dispc_pck, byteclk); 4567 4568 /* verify that the DSI and DISPC TLs are the same */ 4569 if ((u64)dsi_htot * dispc_pck != (u64)dispc_htot * byteclk) 4570 return false; 4571 4572 dispc_hbl = dispc_htot - xres; 4573 4574 /* setup DSI videomode */ 4575 4576 dsi_vm = &ctx->dsi_vm; 4577 memset(dsi_vm, 0, sizeof(*dsi_vm)); 4578 4579 dsi_vm->hsclk = hsclk; 4580 4581 dsi_vm->ndl = ndl; 4582 dsi_vm->bitspp = bitspp; 4583 4584 if (cfg->trans_mode != OMAP_DSS_DSI_PULSE_MODE) { 4585 hsa = 0; 4586 } else if (ndl == 3 && req_vm->hsw == 0) { 4587 hsa = 0; 4588 } else { 4589 hsa = div64_u64((u64)req_vm->hsw * byteclk, req_pck_nom); 4590 hsa = max(hsa - hse, 1); 4591 } 4592 4593 hbp = div64_u64((u64)req_vm->hbp * byteclk, req_pck_nom); 4594 hbp = max(hbp, 1); 4595 4596 hfp = dsi_hbl - (hss + hsa + hse + hbp); 4597 if (hfp < 1) { 4598 int t; 4599 /* we need to take cycles from hbp */ 4600 4601 t = 1 - hfp; 4602 hbp = max(hbp - t, 1); 4603 hfp = dsi_hbl - (hss + hsa + hse + hbp); 4604 4605 if (hfp < 1 && hsa > 0) { 4606 /* we need to take cycles from hsa */ 4607 t = 1 - hfp; 4608 hsa = max(hsa - t, 1); 4609 hfp = dsi_hbl - (hss + hsa + hse + hbp); 4610 } 4611 } 4612 4613 if (hfp < 1) 4614 return false; 4615 4616 dsi_vm->hss = hss; 4617 dsi_vm->hsa = hsa; 4618 dsi_vm->hse = hse; 4619 dsi_vm->hbp = hbp; 4620 dsi_vm->hact = xres; 4621 dsi_vm->hfp = hfp; 4622 4623 dsi_vm->vsa = req_vm->vsw; 4624 dsi_vm->vbp = req_vm->vbp; 4625 dsi_vm->vact = req_vm->y_res; 4626 dsi_vm->vfp = req_vm->vfp; 4627 4628 dsi_vm->trans_mode = cfg->trans_mode; 4629 4630 dsi_vm->blanking_mode = 0; 4631 dsi_vm->hsa_blanking_mode = 1; 4632 dsi_vm->hfp_blanking_mode = 1; 4633 dsi_vm->hbp_blanking_mode = 1; 4634 4635 dsi_vm->ddr_clk_always_on = cfg->ddr_clk_always_on; 4636 dsi_vm->window_sync = 4; 4637 4638 /* setup DISPC videomode */ 4639 4640 dispc_vm = &ctx->dispc_vm; 4641 *dispc_vm = *req_vm; 4642 dispc_vm->pixelclock = dispc_pck; 4643 4644 if (cfg->trans_mode == OMAP_DSS_DSI_PULSE_MODE) { 4645 hsa = div64_u64((u64)req_vm->hsw * dispc_pck, 4646 req_pck_nom); 4647 hsa = max(hsa, 1); 4648 } else { 4649 hsa = 1; 4650 } 4651 4652 hbp = div64_u64((u64)req_vm->hbp * dispc_pck, req_pck_nom); 4653 hbp = max(hbp, 1); 4654 4655 hfp = dispc_hbl - hsa - hbp; 4656 if (hfp < 1) { 4657 int t; 4658 /* we need to take cycles from hbp */ 4659 4660 t = 1 - hfp; 4661 hbp = max(hbp - t, 1); 4662 hfp = dispc_hbl - hsa - hbp; 4663 4664 if (hfp < 1) { 4665 /* we need to take cycles from hsa */ 4666 t = 1 - hfp; 4667 hsa = max(hsa - t, 1); 4668 hfp = dispc_hbl - hsa - hbp; 4669 } 4670 } 4671 4672 if (hfp < 1) 4673 return false; 4674 4675 dispc_vm->hfp = hfp; 4676 dispc_vm->hsw = hsa; 4677 dispc_vm->hbp = hbp; 4678 4679 return true; 4680 } 4681 4682 4683 static bool dsi_vm_calc_dispc_cb(int lckd, int pckd, unsigned long lck, 4684 unsigned long pck, void *data) 4685 { 4686 struct dsi_clk_calc_ctx *ctx = data; 4687 4688 ctx->dispc_cinfo.lck_div = lckd; 4689 ctx->dispc_cinfo.pck_div = pckd; 4690 ctx->dispc_cinfo.lck = lck; 4691 ctx->dispc_cinfo.pck = pck; 4692 4693 if (dsi_vm_calc_blanking(ctx) == false) 4694 return false; 4695 4696 #ifdef PRINT_VERBOSE_VM_TIMINGS 4697 print_dispc_vm("dispc", &ctx->dispc_vm); 4698 print_dsi_vm("dsi ", &ctx->dsi_vm); 4699 print_dispc_vm("req ", ctx->config->timings); 4700 print_dsi_dispc_vm("act ", &ctx->dsi_vm); 4701 #endif 4702 4703 return true; 4704 } 4705 4706 static bool dsi_vm_calc_hsdiv_cb(int m_dispc, unsigned long dispc, 4707 void *data) 4708 { 4709 struct dsi_clk_calc_ctx *ctx = data; 4710 unsigned long pck_max; 4711 4712 ctx->dsi_cinfo.mX[HSDIV_DISPC] = m_dispc; 4713 ctx->dsi_cinfo.clkout[HSDIV_DISPC] = dispc; 4714 4715 /* 4716 * In burst mode we can let the dispc pck be arbitrarily high, but it 4717 * limits our scaling abilities. So for now, don't aim too high. 4718 */ 4719 4720 if (ctx->config->trans_mode == OMAP_DSS_DSI_BURST_MODE) 4721 pck_max = ctx->req_pck_max + 10000000; 4722 else 4723 pck_max = ctx->req_pck_max; 4724 4725 return dispc_div_calc(dispc, ctx->req_pck_min, pck_max, 4726 dsi_vm_calc_dispc_cb, ctx); 4727 } 4728 4729 static bool dsi_vm_calc_pll_cb(int n, int m, unsigned long fint, 4730 unsigned long clkdco, void *data) 4731 { 4732 struct dsi_clk_calc_ctx *ctx = data; 4733 4734 ctx->dsi_cinfo.n = n; 4735 ctx->dsi_cinfo.m = m; 4736 ctx->dsi_cinfo.fint = fint; 4737 ctx->dsi_cinfo.clkdco = clkdco; 4738 4739 return dss_pll_hsdiv_calc(ctx->pll, clkdco, ctx->req_pck_min, 4740 dss_feat_get_param_max(FEAT_PARAM_DSS_FCK), 4741 dsi_vm_calc_hsdiv_cb, ctx); 4742 } 4743 4744 static bool dsi_vm_calc(struct dsi_data *dsi, 4745 const struct omap_dss_dsi_config *cfg, 4746 struct dsi_clk_calc_ctx *ctx) 4747 { 4748 const struct omap_video_timings *t = cfg->timings; 4749 unsigned long clkin; 4750 unsigned long pll_min; 4751 unsigned long pll_max; 4752 int ndl = dsi->num_lanes_used - 1; 4753 int bitspp = dsi_get_pixel_size(cfg->pixel_format); 4754 unsigned long byteclk_min; 4755 4756 clkin = clk_get_rate(dsi->pll.clkin); 4757 4758 memset(ctx, 0, sizeof(*ctx)); 4759 ctx->dsidev = dsi->pdev; 4760 ctx->pll = &dsi->pll; 4761 ctx->config = cfg; 4762 4763 /* these limits should come from the panel driver */ 4764 ctx->req_pck_min = t->pixelclock - 1000; 4765 ctx->req_pck_nom = t->pixelclock; 4766 ctx->req_pck_max = t->pixelclock + 1000; 4767 4768 byteclk_min = div64_u64((u64)ctx->req_pck_min * bitspp, ndl * 8); 4769 pll_min = max(cfg->hs_clk_min * 4, byteclk_min * 4 * 4); 4770 4771 if (cfg->trans_mode == OMAP_DSS_DSI_BURST_MODE) { 4772 pll_max = cfg->hs_clk_max * 4; 4773 } else { 4774 unsigned long byteclk_max; 4775 byteclk_max = div64_u64((u64)ctx->req_pck_max * bitspp, 4776 ndl * 8); 4777 4778 pll_max = byteclk_max * 4 * 4; 4779 } 4780 4781 return dss_pll_calc(ctx->pll, clkin, 4782 pll_min, pll_max, 4783 dsi_vm_calc_pll_cb, ctx); 4784 } 4785 4786 static int dsi_set_config(struct omap_dss_device *dssdev, 4787 const struct omap_dss_dsi_config *config) 4788 { 4789 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 4790 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 4791 struct dsi_clk_calc_ctx ctx; 4792 bool ok; 4793 int r; 4794 4795 mutex_lock(&dsi->lock); 4796 4797 dsi->pix_fmt = config->pixel_format; 4798 dsi->mode = config->mode; 4799 4800 if (config->mode == OMAP_DSS_DSI_VIDEO_MODE) 4801 ok = dsi_vm_calc(dsi, config, &ctx); 4802 else 4803 ok = dsi_cm_calc(dsi, config, &ctx); 4804 4805 if (!ok) { 4806 DSSERR("failed to find suitable DSI clock settings\n"); 4807 r = -EINVAL; 4808 goto err; 4809 } 4810 4811 dsi_pll_calc_dsi_fck(&ctx.dsi_cinfo); 4812 4813 r = dsi_lp_clock_calc(ctx.dsi_cinfo.clkout[HSDIV_DSI], 4814 config->lp_clk_min, config->lp_clk_max, &dsi->user_lp_cinfo); 4815 if (r) { 4816 DSSERR("failed to find suitable DSI LP clock settings\n"); 4817 goto err; 4818 } 4819 4820 dsi->user_dsi_cinfo = ctx.dsi_cinfo; 4821 dsi->user_dispc_cinfo = ctx.dispc_cinfo; 4822 4823 dsi->timings = ctx.dispc_vm; 4824 dsi->vm_timings = ctx.dsi_vm; 4825 4826 mutex_unlock(&dsi->lock); 4827 4828 return 0; 4829 err: 4830 mutex_unlock(&dsi->lock); 4831 4832 return r; 4833 } 4834 4835 /* 4836 * Return a hardcoded channel for the DSI output. This should work for 4837 * current use cases, but this can be later expanded to either resolve 4838 * the channel in some more dynamic manner, or get the channel as a user 4839 * parameter. 4840 */ 4841 static enum omap_channel dsi_get_channel(int module_id) 4842 { 4843 switch (omapdss_get_version()) { 4844 case OMAPDSS_VER_OMAP24xx: 4845 case OMAPDSS_VER_AM43xx: 4846 DSSWARN("DSI not supported\n"); 4847 return OMAP_DSS_CHANNEL_LCD; 4848 4849 case OMAPDSS_VER_OMAP34xx_ES1: 4850 case OMAPDSS_VER_OMAP34xx_ES3: 4851 case OMAPDSS_VER_OMAP3630: 4852 case OMAPDSS_VER_AM35xx: 4853 return OMAP_DSS_CHANNEL_LCD; 4854 4855 case OMAPDSS_VER_OMAP4430_ES1: 4856 case OMAPDSS_VER_OMAP4430_ES2: 4857 case OMAPDSS_VER_OMAP4: 4858 switch (module_id) { 4859 case 0: 4860 return OMAP_DSS_CHANNEL_LCD; 4861 case 1: 4862 return OMAP_DSS_CHANNEL_LCD2; 4863 default: 4864 DSSWARN("unsupported module id\n"); 4865 return OMAP_DSS_CHANNEL_LCD; 4866 } 4867 4868 case OMAPDSS_VER_OMAP5: 4869 switch (module_id) { 4870 case 0: 4871 return OMAP_DSS_CHANNEL_LCD; 4872 case 1: 4873 return OMAP_DSS_CHANNEL_LCD3; 4874 default: 4875 DSSWARN("unsupported module id\n"); 4876 return OMAP_DSS_CHANNEL_LCD; 4877 } 4878 4879 default: 4880 DSSWARN("unsupported DSS version\n"); 4881 return OMAP_DSS_CHANNEL_LCD; 4882 } 4883 } 4884 4885 static int dsi_request_vc(struct omap_dss_device *dssdev, int *channel) 4886 { 4887 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 4888 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 4889 int i; 4890 4891 for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) { 4892 if (!dsi->vc[i].dssdev) { 4893 dsi->vc[i].dssdev = dssdev; 4894 *channel = i; 4895 return 0; 4896 } 4897 } 4898 4899 DSSERR("cannot get VC for display %s", dssdev->name); 4900 return -ENOSPC; 4901 } 4902 4903 static int dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id) 4904 { 4905 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 4906 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 4907 4908 if (vc_id < 0 || vc_id > 3) { 4909 DSSERR("VC ID out of range\n"); 4910 return -EINVAL; 4911 } 4912 4913 if (channel < 0 || channel > 3) { 4914 DSSERR("Virtual Channel out of range\n"); 4915 return -EINVAL; 4916 } 4917 4918 if (dsi->vc[channel].dssdev != dssdev) { 4919 DSSERR("Virtual Channel not allocated to display %s\n", 4920 dssdev->name); 4921 return -EINVAL; 4922 } 4923 4924 dsi->vc[channel].vc_id = vc_id; 4925 4926 return 0; 4927 } 4928 4929 static void dsi_release_vc(struct omap_dss_device *dssdev, int channel) 4930 { 4931 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 4932 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 4933 4934 if ((channel >= 0 && channel <= 3) && 4935 dsi->vc[channel].dssdev == dssdev) { 4936 dsi->vc[channel].dssdev = NULL; 4937 dsi->vc[channel].vc_id = 0; 4938 } 4939 } 4940 4941 4942 static int dsi_get_clocks(struct platform_device *dsidev) 4943 { 4944 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 4945 struct clk *clk; 4946 4947 clk = devm_clk_get(&dsidev->dev, "fck"); 4948 if (IS_ERR(clk)) { 4949 DSSERR("can't get fck\n"); 4950 return PTR_ERR(clk); 4951 } 4952 4953 dsi->dss_clk = clk; 4954 4955 return 0; 4956 } 4957 4958 static int dsi_connect(struct omap_dss_device *dssdev, 4959 struct omap_dss_device *dst) 4960 { 4961 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 4962 struct omap_overlay_manager *mgr; 4963 int r; 4964 4965 r = dsi_regulator_init(dsidev); 4966 if (r) 4967 return r; 4968 4969 mgr = omap_dss_get_overlay_manager(dssdev->dispc_channel); 4970 if (!mgr) 4971 return -ENODEV; 4972 4973 r = dss_mgr_connect(mgr, dssdev); 4974 if (r) 4975 return r; 4976 4977 r = omapdss_output_set_device(dssdev, dst); 4978 if (r) { 4979 DSSERR("failed to connect output to new device: %s\n", 4980 dssdev->name); 4981 dss_mgr_disconnect(mgr, dssdev); 4982 return r; 4983 } 4984 4985 return 0; 4986 } 4987 4988 static void dsi_disconnect(struct omap_dss_device *dssdev, 4989 struct omap_dss_device *dst) 4990 { 4991 WARN_ON(dst != dssdev->dst); 4992 4993 if (dst != dssdev->dst) 4994 return; 4995 4996 omapdss_output_unset_device(dssdev); 4997 4998 if (dssdev->manager) 4999 dss_mgr_disconnect(dssdev->manager, dssdev); 5000 } 5001 5002 static const struct omapdss_dsi_ops dsi_ops = { 5003 .connect = dsi_connect, 5004 .disconnect = dsi_disconnect, 5005 5006 .bus_lock = dsi_bus_lock, 5007 .bus_unlock = dsi_bus_unlock, 5008 5009 .enable = dsi_display_enable, 5010 .disable = dsi_display_disable, 5011 5012 .enable_hs = dsi_vc_enable_hs, 5013 5014 .configure_pins = dsi_configure_pins, 5015 .set_config = dsi_set_config, 5016 5017 .enable_video_output = dsi_enable_video_output, 5018 .disable_video_output = dsi_disable_video_output, 5019 5020 .update = dsi_update, 5021 5022 .enable_te = dsi_enable_te, 5023 5024 .request_vc = dsi_request_vc, 5025 .set_vc_id = dsi_set_vc_id, 5026 .release_vc = dsi_release_vc, 5027 5028 .dcs_write = dsi_vc_dcs_write, 5029 .dcs_write_nosync = dsi_vc_dcs_write_nosync, 5030 .dcs_read = dsi_vc_dcs_read, 5031 5032 .gen_write = dsi_vc_generic_write, 5033 .gen_write_nosync = dsi_vc_generic_write_nosync, 5034 .gen_read = dsi_vc_generic_read, 5035 5036 .bta_sync = dsi_vc_send_bta_sync, 5037 5038 .set_max_rx_packet_size = dsi_vc_set_max_rx_packet_size, 5039 }; 5040 5041 static void dsi_init_output(struct platform_device *dsidev) 5042 { 5043 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 5044 struct omap_dss_device *out = &dsi->output; 5045 5046 out->dev = &dsidev->dev; 5047 out->id = dsi->module_id == 0 ? 5048 OMAP_DSS_OUTPUT_DSI1 : OMAP_DSS_OUTPUT_DSI2; 5049 5050 out->output_type = OMAP_DISPLAY_TYPE_DSI; 5051 out->name = dsi->module_id == 0 ? "dsi.0" : "dsi.1"; 5052 out->dispc_channel = dsi_get_channel(dsi->module_id); 5053 out->ops.dsi = &dsi_ops; 5054 out->owner = THIS_MODULE; 5055 5056 omapdss_register_output(out); 5057 } 5058 5059 static void dsi_uninit_output(struct platform_device *dsidev) 5060 { 5061 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 5062 struct omap_dss_device *out = &dsi->output; 5063 5064 omapdss_unregister_output(out); 5065 } 5066 5067 static int dsi_probe_of(struct platform_device *pdev) 5068 { 5069 struct device_node *node = pdev->dev.of_node; 5070 struct dsi_data *dsi = dsi_get_dsidrv_data(pdev); 5071 struct property *prop; 5072 u32 lane_arr[10]; 5073 int len, num_pins; 5074 int r, i; 5075 struct device_node *ep; 5076 struct omap_dsi_pin_config pin_cfg; 5077 5078 ep = omapdss_of_get_first_endpoint(node); 5079 if (!ep) 5080 return 0; 5081 5082 prop = of_find_property(ep, "lanes", &len); 5083 if (prop == NULL) { 5084 dev_err(&pdev->dev, "failed to find lane data\n"); 5085 r = -EINVAL; 5086 goto err; 5087 } 5088 5089 num_pins = len / sizeof(u32); 5090 5091 if (num_pins < 4 || num_pins % 2 != 0 || 5092 num_pins > dsi->num_lanes_supported * 2) { 5093 dev_err(&pdev->dev, "bad number of lanes\n"); 5094 r = -EINVAL; 5095 goto err; 5096 } 5097 5098 r = of_property_read_u32_array(ep, "lanes", lane_arr, num_pins); 5099 if (r) { 5100 dev_err(&pdev->dev, "failed to read lane data\n"); 5101 goto err; 5102 } 5103 5104 pin_cfg.num_pins = num_pins; 5105 for (i = 0; i < num_pins; ++i) 5106 pin_cfg.pins[i] = (int)lane_arr[i]; 5107 5108 r = dsi_configure_pins(&dsi->output, &pin_cfg); 5109 if (r) { 5110 dev_err(&pdev->dev, "failed to configure pins"); 5111 goto err; 5112 } 5113 5114 of_node_put(ep); 5115 5116 return 0; 5117 5118 err: 5119 of_node_put(ep); 5120 return r; 5121 } 5122 5123 static const struct dss_pll_ops dsi_pll_ops = { 5124 .enable = dsi_pll_enable, 5125 .disable = dsi_pll_disable, 5126 .set_config = dss_pll_write_config_type_a, 5127 }; 5128 5129 static const struct dss_pll_hw dss_omap3_dsi_pll_hw = { 5130 .n_max = (1 << 7) - 1, 5131 .m_max = (1 << 11) - 1, 5132 .mX_max = (1 << 4) - 1, 5133 .fint_min = 750000, 5134 .fint_max = 2100000, 5135 .clkdco_low = 1000000000, 5136 .clkdco_max = 1800000000, 5137 5138 .n_msb = 7, 5139 .n_lsb = 1, 5140 .m_msb = 18, 5141 .m_lsb = 8, 5142 5143 .mX_msb[0] = 22, 5144 .mX_lsb[0] = 19, 5145 .mX_msb[1] = 26, 5146 .mX_lsb[1] = 23, 5147 5148 .has_stopmode = true, 5149 .has_freqsel = true, 5150 .has_selfreqdco = false, 5151 .has_refsel = false, 5152 }; 5153 5154 static const struct dss_pll_hw dss_omap4_dsi_pll_hw = { 5155 .n_max = (1 << 8) - 1, 5156 .m_max = (1 << 12) - 1, 5157 .mX_max = (1 << 5) - 1, 5158 .fint_min = 500000, 5159 .fint_max = 2500000, 5160 .clkdco_low = 1000000000, 5161 .clkdco_max = 1800000000, 5162 5163 .n_msb = 8, 5164 .n_lsb = 1, 5165 .m_msb = 20, 5166 .m_lsb = 9, 5167 5168 .mX_msb[0] = 25, 5169 .mX_lsb[0] = 21, 5170 .mX_msb[1] = 30, 5171 .mX_lsb[1] = 26, 5172 5173 .has_stopmode = true, 5174 .has_freqsel = false, 5175 .has_selfreqdco = false, 5176 .has_refsel = false, 5177 }; 5178 5179 static const struct dss_pll_hw dss_omap5_dsi_pll_hw = { 5180 .n_max = (1 << 8) - 1, 5181 .m_max = (1 << 12) - 1, 5182 .mX_max = (1 << 5) - 1, 5183 .fint_min = 150000, 5184 .fint_max = 52000000, 5185 .clkdco_low = 1000000000, 5186 .clkdco_max = 1800000000, 5187 5188 .n_msb = 8, 5189 .n_lsb = 1, 5190 .m_msb = 20, 5191 .m_lsb = 9, 5192 5193 .mX_msb[0] = 25, 5194 .mX_lsb[0] = 21, 5195 .mX_msb[1] = 30, 5196 .mX_lsb[1] = 26, 5197 5198 .has_stopmode = true, 5199 .has_freqsel = false, 5200 .has_selfreqdco = true, 5201 .has_refsel = true, 5202 }; 5203 5204 static int dsi_init_pll_data(struct platform_device *dsidev) 5205 { 5206 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 5207 struct dss_pll *pll = &dsi->pll; 5208 struct clk *clk; 5209 int r; 5210 5211 clk = devm_clk_get(&dsidev->dev, "sys_clk"); 5212 if (IS_ERR(clk)) { 5213 DSSERR("can't get sys_clk\n"); 5214 return PTR_ERR(clk); 5215 } 5216 5217 pll->name = dsi->module_id == 0 ? "dsi0" : "dsi1"; 5218 pll->id = dsi->module_id == 0 ? DSS_PLL_DSI1 : DSS_PLL_DSI2; 5219 pll->clkin = clk; 5220 pll->base = dsi->pll_base; 5221 5222 switch (omapdss_get_version()) { 5223 case OMAPDSS_VER_OMAP34xx_ES1: 5224 case OMAPDSS_VER_OMAP34xx_ES3: 5225 case OMAPDSS_VER_OMAP3630: 5226 case OMAPDSS_VER_AM35xx: 5227 pll->hw = &dss_omap3_dsi_pll_hw; 5228 break; 5229 5230 case OMAPDSS_VER_OMAP4430_ES1: 5231 case OMAPDSS_VER_OMAP4430_ES2: 5232 case OMAPDSS_VER_OMAP4: 5233 pll->hw = &dss_omap4_dsi_pll_hw; 5234 break; 5235 5236 case OMAPDSS_VER_OMAP5: 5237 pll->hw = &dss_omap5_dsi_pll_hw; 5238 break; 5239 5240 default: 5241 return -ENODEV; 5242 } 5243 5244 pll->ops = &dsi_pll_ops; 5245 5246 r = dss_pll_register(pll); 5247 if (r) 5248 return r; 5249 5250 return 0; 5251 } 5252 5253 /* DSI1 HW IP initialisation */ 5254 static int dsi_bind(struct device *dev, struct device *master, void *data) 5255 { 5256 struct platform_device *dsidev = to_platform_device(dev); 5257 u32 rev; 5258 int r, i; 5259 struct dsi_data *dsi; 5260 struct resource *dsi_mem; 5261 struct resource *res; 5262 struct resource temp_res; 5263 5264 dsi = devm_kzalloc(&dsidev->dev, sizeof(*dsi), GFP_KERNEL); 5265 if (!dsi) 5266 return -ENOMEM; 5267 5268 dsi->pdev = dsidev; 5269 platform_set_drvdata(dsidev, dsi); 5270 5271 spin_lock_init(&dsi->irq_lock); 5272 spin_lock_init(&dsi->errors_lock); 5273 dsi->errors = 0; 5274 5275 #ifdef CONFIG_FB_OMAP2_DSS_COLLECT_IRQ_STATS 5276 spin_lock_init(&dsi->irq_stats_lock); 5277 dsi->irq_stats.last_reset = jiffies; 5278 #endif 5279 5280 mutex_init(&dsi->lock); 5281 sema_init(&dsi->bus_lock, 1); 5282 5283 INIT_DEFERRABLE_WORK(&dsi->framedone_timeout_work, 5284 dsi_framedone_timeout_work_callback); 5285 5286 #ifdef DSI_CATCH_MISSING_TE 5287 timer_setup(&dsi->te_timer, dsi_te_timeout, 0); 5288 #endif 5289 5290 res = platform_get_resource_byname(dsidev, IORESOURCE_MEM, "proto"); 5291 if (!res) { 5292 res = platform_get_resource(dsidev, IORESOURCE_MEM, 0); 5293 if (!res) { 5294 DSSERR("can't get IORESOURCE_MEM DSI\n"); 5295 return -EINVAL; 5296 } 5297 5298 temp_res.start = res->start; 5299 temp_res.end = temp_res.start + DSI_PROTO_SZ - 1; 5300 res = &temp_res; 5301 } 5302 5303 dsi_mem = res; 5304 5305 dsi->proto_base = devm_ioremap(&dsidev->dev, res->start, 5306 resource_size(res)); 5307 if (!dsi->proto_base) { 5308 DSSERR("can't ioremap DSI protocol engine\n"); 5309 return -ENOMEM; 5310 } 5311 5312 res = platform_get_resource_byname(dsidev, IORESOURCE_MEM, "phy"); 5313 if (!res) { 5314 res = platform_get_resource(dsidev, IORESOURCE_MEM, 0); 5315 if (!res) { 5316 DSSERR("can't get IORESOURCE_MEM DSI\n"); 5317 return -EINVAL; 5318 } 5319 5320 temp_res.start = res->start + DSI_PHY_OFFSET; 5321 temp_res.end = temp_res.start + DSI_PHY_SZ - 1; 5322 res = &temp_res; 5323 } 5324 5325 dsi->phy_base = devm_ioremap(&dsidev->dev, res->start, 5326 resource_size(res)); 5327 if (!dsi->phy_base) { 5328 DSSERR("can't ioremap DSI PHY\n"); 5329 return -ENOMEM; 5330 } 5331 5332 res = platform_get_resource_byname(dsidev, IORESOURCE_MEM, "pll"); 5333 if (!res) { 5334 res = platform_get_resource(dsidev, IORESOURCE_MEM, 0); 5335 if (!res) { 5336 DSSERR("can't get IORESOURCE_MEM DSI\n"); 5337 return -EINVAL; 5338 } 5339 5340 temp_res.start = res->start + DSI_PLL_OFFSET; 5341 temp_res.end = temp_res.start + DSI_PLL_SZ - 1; 5342 res = &temp_res; 5343 } 5344 5345 dsi->pll_base = devm_ioremap(&dsidev->dev, res->start, 5346 resource_size(res)); 5347 if (!dsi->pll_base) { 5348 DSSERR("can't ioremap DSI PLL\n"); 5349 return -ENOMEM; 5350 } 5351 5352 dsi->irq = platform_get_irq(dsi->pdev, 0); 5353 if (dsi->irq < 0) { 5354 DSSERR("platform_get_irq failed\n"); 5355 return -ENODEV; 5356 } 5357 5358 r = devm_request_irq(&dsidev->dev, dsi->irq, omap_dsi_irq_handler, 5359 IRQF_SHARED, dev_name(&dsidev->dev), dsi->pdev); 5360 if (r < 0) { 5361 DSSERR("request_irq failed\n"); 5362 return r; 5363 } 5364 5365 if (dsidev->dev.of_node) { 5366 const struct of_device_id *match; 5367 const struct dsi_module_id_data *d; 5368 5369 match = of_match_node(dsi_of_match, dsidev->dev.of_node); 5370 if (!match) { 5371 DSSERR("unsupported DSI module\n"); 5372 return -ENODEV; 5373 } 5374 5375 d = match->data; 5376 5377 while (d->address != 0 && d->address != dsi_mem->start) 5378 d++; 5379 5380 if (d->address == 0) { 5381 DSSERR("unsupported DSI module\n"); 5382 return -ENODEV; 5383 } 5384 5385 dsi->module_id = d->id; 5386 } else { 5387 dsi->module_id = dsidev->id; 5388 } 5389 5390 /* DSI VCs initialization */ 5391 for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) { 5392 dsi->vc[i].source = DSI_VC_SOURCE_L4; 5393 dsi->vc[i].dssdev = NULL; 5394 dsi->vc[i].vc_id = 0; 5395 } 5396 5397 r = dsi_get_clocks(dsidev); 5398 if (r) 5399 return r; 5400 5401 dsi_init_pll_data(dsidev); 5402 5403 pm_runtime_enable(&dsidev->dev); 5404 5405 r = dsi_runtime_get(dsidev); 5406 if (r) 5407 goto err_runtime_get; 5408 5409 rev = dsi_read_reg(dsidev, DSI_REVISION); 5410 dev_dbg(&dsidev->dev, "OMAP DSI rev %d.%d\n", 5411 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0)); 5412 5413 /* DSI on OMAP3 doesn't have register DSI_GNQ, set number 5414 * of data to 3 by default */ 5415 if (dss_has_feature(FEAT_DSI_GNQ)) 5416 /* NB_DATA_LANES */ 5417 dsi->num_lanes_supported = 1 + REG_GET(dsidev, DSI_GNQ, 11, 9); 5418 else 5419 dsi->num_lanes_supported = 3; 5420 5421 dsi->line_buffer_size = dsi_get_line_buf_size(dsidev); 5422 5423 dsi_init_output(dsidev); 5424 5425 if (dsidev->dev.of_node) { 5426 r = dsi_probe_of(dsidev); 5427 if (r) { 5428 DSSERR("Invalid DSI DT data\n"); 5429 goto err_probe_of; 5430 } 5431 5432 r = of_platform_populate(dsidev->dev.of_node, NULL, NULL, 5433 &dsidev->dev); 5434 if (r) 5435 DSSERR("Failed to populate DSI child devices: %d\n", r); 5436 } 5437 5438 dsi_runtime_put(dsidev); 5439 5440 if (dsi->module_id == 0) 5441 dss_debugfs_create_file("dsi1_regs", dsi1_dump_regs); 5442 else if (dsi->module_id == 1) 5443 dss_debugfs_create_file("dsi2_regs", dsi2_dump_regs); 5444 5445 #ifdef CONFIG_FB_OMAP2_DSS_COLLECT_IRQ_STATS 5446 if (dsi->module_id == 0) 5447 dss_debugfs_create_file("dsi1_irqs", dsi1_dump_irqs); 5448 else if (dsi->module_id == 1) 5449 dss_debugfs_create_file("dsi2_irqs", dsi2_dump_irqs); 5450 #endif 5451 5452 return 0; 5453 5454 err_probe_of: 5455 dsi_uninit_output(dsidev); 5456 dsi_runtime_put(dsidev); 5457 5458 err_runtime_get: 5459 pm_runtime_disable(&dsidev->dev); 5460 return r; 5461 } 5462 5463 static void dsi_unbind(struct device *dev, struct device *master, void *data) 5464 { 5465 struct platform_device *dsidev = to_platform_device(dev); 5466 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 5467 5468 of_platform_depopulate(&dsidev->dev); 5469 5470 WARN_ON(dsi->scp_clk_refcount > 0); 5471 5472 dss_pll_unregister(&dsi->pll); 5473 5474 dsi_uninit_output(dsidev); 5475 5476 pm_runtime_disable(&dsidev->dev); 5477 5478 if (dsi->vdds_dsi_reg != NULL && dsi->vdds_dsi_enabled) { 5479 regulator_disable(dsi->vdds_dsi_reg); 5480 dsi->vdds_dsi_enabled = false; 5481 } 5482 } 5483 5484 static const struct component_ops dsi_component_ops = { 5485 .bind = dsi_bind, 5486 .unbind = dsi_unbind, 5487 }; 5488 5489 static int dsi_probe(struct platform_device *pdev) 5490 { 5491 return component_add(&pdev->dev, &dsi_component_ops); 5492 } 5493 5494 static int dsi_remove(struct platform_device *pdev) 5495 { 5496 component_del(&pdev->dev, &dsi_component_ops); 5497 return 0; 5498 } 5499 5500 static int dsi_runtime_suspend(struct device *dev) 5501 { 5502 struct platform_device *pdev = to_platform_device(dev); 5503 struct dsi_data *dsi = dsi_get_dsidrv_data(pdev); 5504 5505 dsi->is_enabled = false; 5506 /* ensure the irq handler sees the is_enabled value */ 5507 smp_wmb(); 5508 /* wait for current handler to finish before turning the DSI off */ 5509 synchronize_irq(dsi->irq); 5510 5511 dispc_runtime_put(); 5512 5513 return 0; 5514 } 5515 5516 static int dsi_runtime_resume(struct device *dev) 5517 { 5518 struct platform_device *pdev = to_platform_device(dev); 5519 struct dsi_data *dsi = dsi_get_dsidrv_data(pdev); 5520 int r; 5521 5522 r = dispc_runtime_get(); 5523 if (r) 5524 return r; 5525 5526 dsi->is_enabled = true; 5527 /* ensure the irq handler sees the is_enabled value */ 5528 smp_wmb(); 5529 5530 return 0; 5531 } 5532 5533 static const struct dev_pm_ops dsi_pm_ops = { 5534 .runtime_suspend = dsi_runtime_suspend, 5535 .runtime_resume = dsi_runtime_resume, 5536 }; 5537 5538 static const struct dsi_module_id_data dsi_of_data_omap3[] = { 5539 { .address = 0x4804fc00, .id = 0, }, 5540 { }, 5541 }; 5542 5543 static const struct dsi_module_id_data dsi_of_data_omap4[] = { 5544 { .address = 0x58004000, .id = 0, }, 5545 { .address = 0x58005000, .id = 1, }, 5546 { }, 5547 }; 5548 5549 static const struct dsi_module_id_data dsi_of_data_omap5[] = { 5550 { .address = 0x58004000, .id = 0, }, 5551 { .address = 0x58009000, .id = 1, }, 5552 { }, 5553 }; 5554 5555 static const struct of_device_id dsi_of_match[] = { 5556 { .compatible = "ti,omap3-dsi", .data = dsi_of_data_omap3, }, 5557 { .compatible = "ti,omap4-dsi", .data = dsi_of_data_omap4, }, 5558 { .compatible = "ti,omap5-dsi", .data = dsi_of_data_omap5, }, 5559 {}, 5560 }; 5561 5562 static struct platform_driver omap_dsihw_driver = { 5563 .probe = dsi_probe, 5564 .remove = dsi_remove, 5565 .driver = { 5566 .name = "omapdss_dsi", 5567 .pm = &dsi_pm_ops, 5568 .of_match_table = dsi_of_match, 5569 .suppress_bind_attrs = true, 5570 }, 5571 }; 5572 5573 int __init dsi_init_platform_driver(void) 5574 { 5575 return platform_driver_register(&omap_dsihw_driver); 5576 } 5577 5578 void dsi_uninit_platform_driver(void) 5579 { 5580 platform_driver_unregister(&omap_dsihw_driver); 5581 } 5582