1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * linux/drivers/video/omap2/dss/dsi.c 4 * 5 * Copyright (C) 2009 Nokia Corporation 6 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> 7 */ 8 9 #define DSS_SUBSYS_NAME "DSI" 10 11 #include <linux/kernel.h> 12 #include <linux/io.h> 13 #include <linux/clk.h> 14 #include <linux/device.h> 15 #include <linux/err.h> 16 #include <linux/interrupt.h> 17 #include <linux/delay.h> 18 #include <linux/mutex.h> 19 #include <linux/module.h> 20 #include <linux/semaphore.h> 21 #include <linux/seq_file.h> 22 #include <linux/platform_device.h> 23 #include <linux/regulator/consumer.h> 24 #include <linux/wait.h> 25 #include <linux/workqueue.h> 26 #include <linux/sched.h> 27 #include <linux/slab.h> 28 #include <linux/debugfs.h> 29 #include <linux/pm_runtime.h> 30 #include <linux/of.h> 31 #include <linux/of_platform.h> 32 #include <linux/component.h> 33 34 #include <video/omapfb_dss.h> 35 #include <video/mipi_display.h> 36 37 #include "dss.h" 38 #include "dss_features.h" 39 40 #define DSI_CATCH_MISSING_TE 41 42 struct dsi_reg { u16 module; u16 idx; }; 43 44 #define DSI_REG(mod, idx) ((const struct dsi_reg) { mod, idx }) 45 46 /* DSI Protocol Engine */ 47 48 #define DSI_PROTO 0 49 #define DSI_PROTO_SZ 0x200 50 51 #define DSI_REVISION DSI_REG(DSI_PROTO, 0x0000) 52 #define DSI_SYSCONFIG DSI_REG(DSI_PROTO, 0x0010) 53 #define DSI_SYSSTATUS DSI_REG(DSI_PROTO, 0x0014) 54 #define DSI_IRQSTATUS DSI_REG(DSI_PROTO, 0x0018) 55 #define DSI_IRQENABLE DSI_REG(DSI_PROTO, 0x001C) 56 #define DSI_CTRL DSI_REG(DSI_PROTO, 0x0040) 57 #define DSI_GNQ DSI_REG(DSI_PROTO, 0x0044) 58 #define DSI_COMPLEXIO_CFG1 DSI_REG(DSI_PROTO, 0x0048) 59 #define DSI_COMPLEXIO_IRQ_STATUS DSI_REG(DSI_PROTO, 0x004C) 60 #define DSI_COMPLEXIO_IRQ_ENABLE DSI_REG(DSI_PROTO, 0x0050) 61 #define DSI_CLK_CTRL DSI_REG(DSI_PROTO, 0x0054) 62 #define DSI_TIMING1 DSI_REG(DSI_PROTO, 0x0058) 63 #define DSI_TIMING2 DSI_REG(DSI_PROTO, 0x005C) 64 #define DSI_VM_TIMING1 DSI_REG(DSI_PROTO, 0x0060) 65 #define DSI_VM_TIMING2 DSI_REG(DSI_PROTO, 0x0064) 66 #define DSI_VM_TIMING3 DSI_REG(DSI_PROTO, 0x0068) 67 #define DSI_CLK_TIMING DSI_REG(DSI_PROTO, 0x006C) 68 #define DSI_TX_FIFO_VC_SIZE DSI_REG(DSI_PROTO, 0x0070) 69 #define DSI_RX_FIFO_VC_SIZE DSI_REG(DSI_PROTO, 0x0074) 70 #define DSI_COMPLEXIO_CFG2 DSI_REG(DSI_PROTO, 0x0078) 71 #define DSI_RX_FIFO_VC_FULLNESS DSI_REG(DSI_PROTO, 0x007C) 72 #define DSI_VM_TIMING4 DSI_REG(DSI_PROTO, 0x0080) 73 #define DSI_TX_FIFO_VC_EMPTINESS DSI_REG(DSI_PROTO, 0x0084) 74 #define DSI_VM_TIMING5 DSI_REG(DSI_PROTO, 0x0088) 75 #define DSI_VM_TIMING6 DSI_REG(DSI_PROTO, 0x008C) 76 #define DSI_VM_TIMING7 DSI_REG(DSI_PROTO, 0x0090) 77 #define DSI_STOPCLK_TIMING DSI_REG(DSI_PROTO, 0x0094) 78 #define DSI_VC_CTRL(n) DSI_REG(DSI_PROTO, 0x0100 + (n * 0x20)) 79 #define DSI_VC_TE(n) DSI_REG(DSI_PROTO, 0x0104 + (n * 0x20)) 80 #define DSI_VC_LONG_PACKET_HEADER(n) DSI_REG(DSI_PROTO, 0x0108 + (n * 0x20)) 81 #define DSI_VC_LONG_PACKET_PAYLOAD(n) DSI_REG(DSI_PROTO, 0x010C + (n * 0x20)) 82 #define DSI_VC_SHORT_PACKET_HEADER(n) DSI_REG(DSI_PROTO, 0x0110 + (n * 0x20)) 83 #define DSI_VC_IRQSTATUS(n) DSI_REG(DSI_PROTO, 0x0118 + (n * 0x20)) 84 #define DSI_VC_IRQENABLE(n) DSI_REG(DSI_PROTO, 0x011C + (n * 0x20)) 85 86 /* DSIPHY_SCP */ 87 88 #define DSI_PHY 1 89 #define DSI_PHY_OFFSET 0x200 90 #define DSI_PHY_SZ 0x40 91 92 #define DSI_DSIPHY_CFG0 DSI_REG(DSI_PHY, 0x0000) 93 #define DSI_DSIPHY_CFG1 DSI_REG(DSI_PHY, 0x0004) 94 #define DSI_DSIPHY_CFG2 DSI_REG(DSI_PHY, 0x0008) 95 #define DSI_DSIPHY_CFG5 DSI_REG(DSI_PHY, 0x0014) 96 #define DSI_DSIPHY_CFG10 DSI_REG(DSI_PHY, 0x0028) 97 98 /* DSI_PLL_CTRL_SCP */ 99 100 #define DSI_PLL 2 101 #define DSI_PLL_OFFSET 0x300 102 #define DSI_PLL_SZ 0x20 103 104 #define DSI_PLL_CONTROL DSI_REG(DSI_PLL, 0x0000) 105 #define DSI_PLL_STATUS DSI_REG(DSI_PLL, 0x0004) 106 #define DSI_PLL_GO DSI_REG(DSI_PLL, 0x0008) 107 #define DSI_PLL_CONFIGURATION1 DSI_REG(DSI_PLL, 0x000C) 108 #define DSI_PLL_CONFIGURATION2 DSI_REG(DSI_PLL, 0x0010) 109 110 #define REG_GET(dsidev, idx, start, end) \ 111 FLD_GET(dsi_read_reg(dsidev, idx), start, end) 112 113 #define REG_FLD_MOD(dsidev, idx, val, start, end) \ 114 dsi_write_reg(dsidev, idx, FLD_MOD(dsi_read_reg(dsidev, idx), val, start, end)) 115 116 /* Global interrupts */ 117 #define DSI_IRQ_VC0 (1 << 0) 118 #define DSI_IRQ_VC1 (1 << 1) 119 #define DSI_IRQ_VC2 (1 << 2) 120 #define DSI_IRQ_VC3 (1 << 3) 121 #define DSI_IRQ_WAKEUP (1 << 4) 122 #define DSI_IRQ_RESYNC (1 << 5) 123 #define DSI_IRQ_PLL_LOCK (1 << 7) 124 #define DSI_IRQ_PLL_UNLOCK (1 << 8) 125 #define DSI_IRQ_PLL_RECALL (1 << 9) 126 #define DSI_IRQ_COMPLEXIO_ERR (1 << 10) 127 #define DSI_IRQ_HS_TX_TIMEOUT (1 << 14) 128 #define DSI_IRQ_LP_RX_TIMEOUT (1 << 15) 129 #define DSI_IRQ_TE_TRIGGER (1 << 16) 130 #define DSI_IRQ_ACK_TRIGGER (1 << 17) 131 #define DSI_IRQ_SYNC_LOST (1 << 18) 132 #define DSI_IRQ_LDO_POWER_GOOD (1 << 19) 133 #define DSI_IRQ_TA_TIMEOUT (1 << 20) 134 #define DSI_IRQ_ERROR_MASK \ 135 (DSI_IRQ_HS_TX_TIMEOUT | DSI_IRQ_LP_RX_TIMEOUT | DSI_IRQ_SYNC_LOST | \ 136 DSI_IRQ_TA_TIMEOUT) 137 #define DSI_IRQ_CHANNEL_MASK 0xf 138 139 /* Virtual channel interrupts */ 140 #define DSI_VC_IRQ_CS (1 << 0) 141 #define DSI_VC_IRQ_ECC_CORR (1 << 1) 142 #define DSI_VC_IRQ_PACKET_SENT (1 << 2) 143 #define DSI_VC_IRQ_FIFO_TX_OVF (1 << 3) 144 #define DSI_VC_IRQ_FIFO_RX_OVF (1 << 4) 145 #define DSI_VC_IRQ_BTA (1 << 5) 146 #define DSI_VC_IRQ_ECC_NO_CORR (1 << 6) 147 #define DSI_VC_IRQ_FIFO_TX_UDF (1 << 7) 148 #define DSI_VC_IRQ_PP_BUSY_CHANGE (1 << 8) 149 #define DSI_VC_IRQ_ERROR_MASK \ 150 (DSI_VC_IRQ_CS | DSI_VC_IRQ_ECC_CORR | DSI_VC_IRQ_FIFO_TX_OVF | \ 151 DSI_VC_IRQ_FIFO_RX_OVF | DSI_VC_IRQ_ECC_NO_CORR | \ 152 DSI_VC_IRQ_FIFO_TX_UDF) 153 154 /* ComplexIO interrupts */ 155 #define DSI_CIO_IRQ_ERRSYNCESC1 (1 << 0) 156 #define DSI_CIO_IRQ_ERRSYNCESC2 (1 << 1) 157 #define DSI_CIO_IRQ_ERRSYNCESC3 (1 << 2) 158 #define DSI_CIO_IRQ_ERRSYNCESC4 (1 << 3) 159 #define DSI_CIO_IRQ_ERRSYNCESC5 (1 << 4) 160 #define DSI_CIO_IRQ_ERRESC1 (1 << 5) 161 #define DSI_CIO_IRQ_ERRESC2 (1 << 6) 162 #define DSI_CIO_IRQ_ERRESC3 (1 << 7) 163 #define DSI_CIO_IRQ_ERRESC4 (1 << 8) 164 #define DSI_CIO_IRQ_ERRESC5 (1 << 9) 165 #define DSI_CIO_IRQ_ERRCONTROL1 (1 << 10) 166 #define DSI_CIO_IRQ_ERRCONTROL2 (1 << 11) 167 #define DSI_CIO_IRQ_ERRCONTROL3 (1 << 12) 168 #define DSI_CIO_IRQ_ERRCONTROL4 (1 << 13) 169 #define DSI_CIO_IRQ_ERRCONTROL5 (1 << 14) 170 #define DSI_CIO_IRQ_STATEULPS1 (1 << 15) 171 #define DSI_CIO_IRQ_STATEULPS2 (1 << 16) 172 #define DSI_CIO_IRQ_STATEULPS3 (1 << 17) 173 #define DSI_CIO_IRQ_STATEULPS4 (1 << 18) 174 #define DSI_CIO_IRQ_STATEULPS5 (1 << 19) 175 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_1 (1 << 20) 176 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_1 (1 << 21) 177 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_2 (1 << 22) 178 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_2 (1 << 23) 179 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_3 (1 << 24) 180 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_3 (1 << 25) 181 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_4 (1 << 26) 182 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_4 (1 << 27) 183 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_5 (1 << 28) 184 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_5 (1 << 29) 185 #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL0 (1 << 30) 186 #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL1 (1 << 31) 187 #define DSI_CIO_IRQ_ERROR_MASK \ 188 (DSI_CIO_IRQ_ERRSYNCESC1 | DSI_CIO_IRQ_ERRSYNCESC2 | \ 189 DSI_CIO_IRQ_ERRSYNCESC3 | DSI_CIO_IRQ_ERRSYNCESC4 | \ 190 DSI_CIO_IRQ_ERRSYNCESC5 | \ 191 DSI_CIO_IRQ_ERRESC1 | DSI_CIO_IRQ_ERRESC2 | \ 192 DSI_CIO_IRQ_ERRESC3 | DSI_CIO_IRQ_ERRESC4 | \ 193 DSI_CIO_IRQ_ERRESC5 | \ 194 DSI_CIO_IRQ_ERRCONTROL1 | DSI_CIO_IRQ_ERRCONTROL2 | \ 195 DSI_CIO_IRQ_ERRCONTROL3 | DSI_CIO_IRQ_ERRCONTROL4 | \ 196 DSI_CIO_IRQ_ERRCONTROL5 | \ 197 DSI_CIO_IRQ_ERRCONTENTIONLP0_1 | DSI_CIO_IRQ_ERRCONTENTIONLP1_1 | \ 198 DSI_CIO_IRQ_ERRCONTENTIONLP0_2 | DSI_CIO_IRQ_ERRCONTENTIONLP1_2 | \ 199 DSI_CIO_IRQ_ERRCONTENTIONLP0_3 | DSI_CIO_IRQ_ERRCONTENTIONLP1_3 | \ 200 DSI_CIO_IRQ_ERRCONTENTIONLP0_4 | DSI_CIO_IRQ_ERRCONTENTIONLP1_4 | \ 201 DSI_CIO_IRQ_ERRCONTENTIONLP0_5 | DSI_CIO_IRQ_ERRCONTENTIONLP1_5) 202 203 typedef void (*omap_dsi_isr_t) (void *arg, u32 mask); 204 205 static int dsi_display_init_dispc(struct platform_device *dsidev, 206 struct omap_overlay_manager *mgr); 207 static void dsi_display_uninit_dispc(struct platform_device *dsidev, 208 struct omap_overlay_manager *mgr); 209 210 static int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel); 211 212 /* DSI PLL HSDIV indices */ 213 #define HSDIV_DISPC 0 214 #define HSDIV_DSI 1 215 216 #define DSI_MAX_NR_ISRS 2 217 #define DSI_MAX_NR_LANES 5 218 219 enum dsi_lane_function { 220 DSI_LANE_UNUSED = 0, 221 DSI_LANE_CLK, 222 DSI_LANE_DATA1, 223 DSI_LANE_DATA2, 224 DSI_LANE_DATA3, 225 DSI_LANE_DATA4, 226 }; 227 228 struct dsi_lane_config { 229 enum dsi_lane_function function; 230 u8 polarity; 231 }; 232 233 struct dsi_isr_data { 234 omap_dsi_isr_t isr; 235 void *arg; 236 u32 mask; 237 }; 238 239 enum fifo_size { 240 DSI_FIFO_SIZE_0 = 0, 241 DSI_FIFO_SIZE_32 = 1, 242 DSI_FIFO_SIZE_64 = 2, 243 DSI_FIFO_SIZE_96 = 3, 244 DSI_FIFO_SIZE_128 = 4, 245 }; 246 247 enum dsi_vc_source { 248 DSI_VC_SOURCE_L4 = 0, 249 DSI_VC_SOURCE_VP, 250 }; 251 252 struct dsi_irq_stats { 253 unsigned long last_reset; 254 unsigned irq_count; 255 unsigned dsi_irqs[32]; 256 unsigned vc_irqs[4][32]; 257 unsigned cio_irqs[32]; 258 }; 259 260 struct dsi_isr_tables { 261 struct dsi_isr_data isr_table[DSI_MAX_NR_ISRS]; 262 struct dsi_isr_data isr_table_vc[4][DSI_MAX_NR_ISRS]; 263 struct dsi_isr_data isr_table_cio[DSI_MAX_NR_ISRS]; 264 }; 265 266 struct dsi_clk_calc_ctx { 267 struct platform_device *dsidev; 268 struct dss_pll *pll; 269 270 /* inputs */ 271 272 const struct omap_dss_dsi_config *config; 273 274 unsigned long req_pck_min, req_pck_nom, req_pck_max; 275 276 /* outputs */ 277 278 struct dss_pll_clock_info dsi_cinfo; 279 struct dispc_clock_info dispc_cinfo; 280 281 struct omap_video_timings dispc_vm; 282 struct omap_dss_dsi_videomode_timings dsi_vm; 283 }; 284 285 struct dsi_lp_clock_info { 286 unsigned long lp_clk; 287 u16 lp_clk_div; 288 }; 289 290 struct dsi_data { 291 struct platform_device *pdev; 292 void __iomem *proto_base; 293 void __iomem *phy_base; 294 void __iomem *pll_base; 295 296 int module_id; 297 298 int irq; 299 300 bool is_enabled; 301 302 struct clk *dss_clk; 303 304 struct dispc_clock_info user_dispc_cinfo; 305 struct dss_pll_clock_info user_dsi_cinfo; 306 307 struct dsi_lp_clock_info user_lp_cinfo; 308 struct dsi_lp_clock_info current_lp_cinfo; 309 310 struct dss_pll pll; 311 312 bool vdds_dsi_enabled; 313 struct regulator *vdds_dsi_reg; 314 315 struct { 316 enum dsi_vc_source source; 317 struct omap_dss_device *dssdev; 318 enum fifo_size tx_fifo_size; 319 enum fifo_size rx_fifo_size; 320 int vc_id; 321 } vc[4]; 322 323 struct mutex lock; 324 struct semaphore bus_lock; 325 326 spinlock_t irq_lock; 327 struct dsi_isr_tables isr_tables; 328 /* space for a copy used by the interrupt handler */ 329 struct dsi_isr_tables isr_tables_copy; 330 331 int update_channel; 332 #ifdef DSI_PERF_MEASURE 333 unsigned update_bytes; 334 #endif 335 336 bool te_enabled; 337 bool ulps_enabled; 338 339 void (*framedone_callback)(int, void *); 340 void *framedone_data; 341 342 struct delayed_work framedone_timeout_work; 343 344 #ifdef DSI_CATCH_MISSING_TE 345 struct timer_list te_timer; 346 #endif 347 348 unsigned long cache_req_pck; 349 unsigned long cache_clk_freq; 350 struct dss_pll_clock_info cache_cinfo; 351 352 u32 errors; 353 spinlock_t errors_lock; 354 #ifdef DSI_PERF_MEASURE 355 ktime_t perf_setup_time; 356 ktime_t perf_start_time; 357 #endif 358 int debug_read; 359 int debug_write; 360 361 #ifdef CONFIG_FB_OMAP2_DSS_COLLECT_IRQ_STATS 362 spinlock_t irq_stats_lock; 363 struct dsi_irq_stats irq_stats; 364 #endif 365 366 unsigned num_lanes_supported; 367 unsigned line_buffer_size; 368 369 struct dsi_lane_config lanes[DSI_MAX_NR_LANES]; 370 unsigned num_lanes_used; 371 372 unsigned scp_clk_refcount; 373 374 struct dss_lcd_mgr_config mgr_config; 375 struct omap_video_timings timings; 376 enum omap_dss_dsi_pixel_format pix_fmt; 377 enum omap_dss_dsi_mode mode; 378 struct omap_dss_dsi_videomode_timings vm_timings; 379 380 struct omap_dss_device output; 381 }; 382 383 struct dsi_packet_sent_handler_data { 384 struct platform_device *dsidev; 385 struct completion *completion; 386 }; 387 388 struct dsi_module_id_data { 389 u32 address; 390 int id; 391 }; 392 393 static const struct of_device_id dsi_of_match[]; 394 395 #ifdef DSI_PERF_MEASURE 396 static bool dsi_perf; 397 module_param(dsi_perf, bool, 0644); 398 #endif 399 400 static inline struct dsi_data *dsi_get_dsidrv_data(struct platform_device *dsidev) 401 { 402 return dev_get_drvdata(&dsidev->dev); 403 } 404 405 static inline struct platform_device *dsi_get_dsidev_from_dssdev(struct omap_dss_device *dssdev) 406 { 407 return to_platform_device(dssdev->dev); 408 } 409 410 static struct platform_device *dsi_get_dsidev_from_id(int module) 411 { 412 struct omap_dss_device *out; 413 enum omap_dss_output_id id; 414 415 switch (module) { 416 case 0: 417 id = OMAP_DSS_OUTPUT_DSI1; 418 break; 419 case 1: 420 id = OMAP_DSS_OUTPUT_DSI2; 421 break; 422 default: 423 return NULL; 424 } 425 426 out = omap_dss_get_output(id); 427 428 return out ? to_platform_device(out->dev) : NULL; 429 } 430 431 static inline void dsi_write_reg(struct platform_device *dsidev, 432 const struct dsi_reg idx, u32 val) 433 { 434 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 435 void __iomem *base; 436 437 switch(idx.module) { 438 case DSI_PROTO: base = dsi->proto_base; break; 439 case DSI_PHY: base = dsi->phy_base; break; 440 case DSI_PLL: base = dsi->pll_base; break; 441 default: return; 442 } 443 444 __raw_writel(val, base + idx.idx); 445 } 446 447 static inline u32 dsi_read_reg(struct platform_device *dsidev, 448 const struct dsi_reg idx) 449 { 450 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 451 void __iomem *base; 452 453 switch(idx.module) { 454 case DSI_PROTO: base = dsi->proto_base; break; 455 case DSI_PHY: base = dsi->phy_base; break; 456 case DSI_PLL: base = dsi->pll_base; break; 457 default: return 0; 458 } 459 460 return __raw_readl(base + idx.idx); 461 } 462 463 static void dsi_bus_lock(struct omap_dss_device *dssdev) 464 { 465 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 466 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 467 468 down(&dsi->bus_lock); 469 } 470 471 static void dsi_bus_unlock(struct omap_dss_device *dssdev) 472 { 473 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 474 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 475 476 up(&dsi->bus_lock); 477 } 478 479 static bool dsi_bus_is_locked(struct platform_device *dsidev) 480 { 481 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 482 483 return dsi->bus_lock.count == 0; 484 } 485 486 static void dsi_completion_handler(void *data, u32 mask) 487 { 488 complete((struct completion *)data); 489 } 490 491 static inline int wait_for_bit_change(struct platform_device *dsidev, 492 const struct dsi_reg idx, int bitnum, int value) 493 { 494 unsigned long timeout; 495 ktime_t wait; 496 int t; 497 498 /* first busyloop to see if the bit changes right away */ 499 t = 100; 500 while (t-- > 0) { 501 if (REG_GET(dsidev, idx, bitnum, bitnum) == value) 502 return value; 503 } 504 505 /* then loop for 500ms, sleeping for 1ms in between */ 506 timeout = jiffies + msecs_to_jiffies(500); 507 while (time_before(jiffies, timeout)) { 508 if (REG_GET(dsidev, idx, bitnum, bitnum) == value) 509 return value; 510 511 wait = ns_to_ktime(1000 * 1000); 512 set_current_state(TASK_UNINTERRUPTIBLE); 513 schedule_hrtimeout(&wait, HRTIMER_MODE_REL); 514 } 515 516 return !value; 517 } 518 519 u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt) 520 { 521 switch (fmt) { 522 case OMAP_DSS_DSI_FMT_RGB888: 523 case OMAP_DSS_DSI_FMT_RGB666: 524 return 24; 525 case OMAP_DSS_DSI_FMT_RGB666_PACKED: 526 return 18; 527 case OMAP_DSS_DSI_FMT_RGB565: 528 return 16; 529 default: 530 BUG(); 531 return 0; 532 } 533 } 534 535 #ifdef DSI_PERF_MEASURE 536 static void dsi_perf_mark_setup(struct platform_device *dsidev) 537 { 538 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 539 dsi->perf_setup_time = ktime_get(); 540 } 541 542 static void dsi_perf_mark_start(struct platform_device *dsidev) 543 { 544 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 545 dsi->perf_start_time = ktime_get(); 546 } 547 548 static void dsi_perf_show(struct platform_device *dsidev, const char *name) 549 { 550 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 551 ktime_t t, setup_time, trans_time; 552 u32 total_bytes; 553 u32 setup_us, trans_us, total_us; 554 555 if (!dsi_perf) 556 return; 557 558 t = ktime_get(); 559 560 setup_time = ktime_sub(dsi->perf_start_time, dsi->perf_setup_time); 561 setup_us = (u32)ktime_to_us(setup_time); 562 if (setup_us == 0) 563 setup_us = 1; 564 565 trans_time = ktime_sub(t, dsi->perf_start_time); 566 trans_us = (u32)ktime_to_us(trans_time); 567 if (trans_us == 0) 568 trans_us = 1; 569 570 total_us = setup_us + trans_us; 571 572 total_bytes = dsi->update_bytes; 573 574 printk(KERN_INFO "DSI(%s): %u us + %u us = %u us (%uHz), " 575 "%u bytes, %u kbytes/sec\n", 576 name, 577 setup_us, 578 trans_us, 579 total_us, 580 1000*1000 / total_us, 581 total_bytes, 582 total_bytes * 1000 / total_us); 583 } 584 #else 585 static inline void dsi_perf_mark_setup(struct platform_device *dsidev) 586 { 587 } 588 589 static inline void dsi_perf_mark_start(struct platform_device *dsidev) 590 { 591 } 592 593 static inline void dsi_perf_show(struct platform_device *dsidev, 594 const char *name) 595 { 596 } 597 #endif 598 599 static int verbose_irq; 600 601 static void print_irq_status(u32 status) 602 { 603 if (status == 0) 604 return; 605 606 if (!verbose_irq && (status & ~DSI_IRQ_CHANNEL_MASK) == 0) 607 return; 608 609 #define PIS(x) (status & DSI_IRQ_##x) ? (#x " ") : "" 610 611 pr_debug("DSI IRQ: 0x%x: %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", 612 status, 613 verbose_irq ? PIS(VC0) : "", 614 verbose_irq ? PIS(VC1) : "", 615 verbose_irq ? PIS(VC2) : "", 616 verbose_irq ? PIS(VC3) : "", 617 PIS(WAKEUP), 618 PIS(RESYNC), 619 PIS(PLL_LOCK), 620 PIS(PLL_UNLOCK), 621 PIS(PLL_RECALL), 622 PIS(COMPLEXIO_ERR), 623 PIS(HS_TX_TIMEOUT), 624 PIS(LP_RX_TIMEOUT), 625 PIS(TE_TRIGGER), 626 PIS(ACK_TRIGGER), 627 PIS(SYNC_LOST), 628 PIS(LDO_POWER_GOOD), 629 PIS(TA_TIMEOUT)); 630 #undef PIS 631 } 632 633 static void print_irq_status_vc(int channel, u32 status) 634 { 635 if (status == 0) 636 return; 637 638 if (!verbose_irq && (status & ~DSI_VC_IRQ_PACKET_SENT) == 0) 639 return; 640 641 #define PIS(x) (status & DSI_VC_IRQ_##x) ? (#x " ") : "" 642 643 pr_debug("DSI VC(%d) IRQ 0x%x: %s%s%s%s%s%s%s%s%s\n", 644 channel, 645 status, 646 PIS(CS), 647 PIS(ECC_CORR), 648 PIS(ECC_NO_CORR), 649 verbose_irq ? PIS(PACKET_SENT) : "", 650 PIS(BTA), 651 PIS(FIFO_TX_OVF), 652 PIS(FIFO_RX_OVF), 653 PIS(FIFO_TX_UDF), 654 PIS(PP_BUSY_CHANGE)); 655 #undef PIS 656 } 657 658 static void print_irq_status_cio(u32 status) 659 { 660 if (status == 0) 661 return; 662 663 #define PIS(x) (status & DSI_CIO_IRQ_##x) ? (#x " ") : "" 664 665 pr_debug("DSI CIO IRQ 0x%x: %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", 666 status, 667 PIS(ERRSYNCESC1), 668 PIS(ERRSYNCESC2), 669 PIS(ERRSYNCESC3), 670 PIS(ERRESC1), 671 PIS(ERRESC2), 672 PIS(ERRESC3), 673 PIS(ERRCONTROL1), 674 PIS(ERRCONTROL2), 675 PIS(ERRCONTROL3), 676 PIS(STATEULPS1), 677 PIS(STATEULPS2), 678 PIS(STATEULPS3), 679 PIS(ERRCONTENTIONLP0_1), 680 PIS(ERRCONTENTIONLP1_1), 681 PIS(ERRCONTENTIONLP0_2), 682 PIS(ERRCONTENTIONLP1_2), 683 PIS(ERRCONTENTIONLP0_3), 684 PIS(ERRCONTENTIONLP1_3), 685 PIS(ULPSACTIVENOT_ALL0), 686 PIS(ULPSACTIVENOT_ALL1)); 687 #undef PIS 688 } 689 690 #ifdef CONFIG_FB_OMAP2_DSS_COLLECT_IRQ_STATS 691 static void dsi_collect_irq_stats(struct platform_device *dsidev, u32 irqstatus, 692 u32 *vcstatus, u32 ciostatus) 693 { 694 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 695 int i; 696 697 spin_lock(&dsi->irq_stats_lock); 698 699 dsi->irq_stats.irq_count++; 700 dss_collect_irq_stats(irqstatus, dsi->irq_stats.dsi_irqs); 701 702 for (i = 0; i < 4; ++i) 703 dss_collect_irq_stats(vcstatus[i], dsi->irq_stats.vc_irqs[i]); 704 705 dss_collect_irq_stats(ciostatus, dsi->irq_stats.cio_irqs); 706 707 spin_unlock(&dsi->irq_stats_lock); 708 } 709 #else 710 #define dsi_collect_irq_stats(dsidev, irqstatus, vcstatus, ciostatus) 711 #endif 712 713 static int debug_irq; 714 715 static void dsi_handle_irq_errors(struct platform_device *dsidev, u32 irqstatus, 716 u32 *vcstatus, u32 ciostatus) 717 { 718 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 719 int i; 720 721 if (irqstatus & DSI_IRQ_ERROR_MASK) { 722 DSSERR("DSI error, irqstatus %x\n", irqstatus); 723 print_irq_status(irqstatus); 724 spin_lock(&dsi->errors_lock); 725 dsi->errors |= irqstatus & DSI_IRQ_ERROR_MASK; 726 spin_unlock(&dsi->errors_lock); 727 } else if (debug_irq) { 728 print_irq_status(irqstatus); 729 } 730 731 for (i = 0; i < 4; ++i) { 732 if (vcstatus[i] & DSI_VC_IRQ_ERROR_MASK) { 733 DSSERR("DSI VC(%d) error, vc irqstatus %x\n", 734 i, vcstatus[i]); 735 print_irq_status_vc(i, vcstatus[i]); 736 } else if (debug_irq) { 737 print_irq_status_vc(i, vcstatus[i]); 738 } 739 } 740 741 if (ciostatus & DSI_CIO_IRQ_ERROR_MASK) { 742 DSSERR("DSI CIO error, cio irqstatus %x\n", ciostatus); 743 print_irq_status_cio(ciostatus); 744 } else if (debug_irq) { 745 print_irq_status_cio(ciostatus); 746 } 747 } 748 749 static void dsi_call_isrs(struct dsi_isr_data *isr_array, 750 unsigned isr_array_size, u32 irqstatus) 751 { 752 struct dsi_isr_data *isr_data; 753 int i; 754 755 for (i = 0; i < isr_array_size; i++) { 756 isr_data = &isr_array[i]; 757 if (isr_data->isr && isr_data->mask & irqstatus) 758 isr_data->isr(isr_data->arg, irqstatus); 759 } 760 } 761 762 static void dsi_handle_isrs(struct dsi_isr_tables *isr_tables, 763 u32 irqstatus, u32 *vcstatus, u32 ciostatus) 764 { 765 int i; 766 767 dsi_call_isrs(isr_tables->isr_table, 768 ARRAY_SIZE(isr_tables->isr_table), 769 irqstatus); 770 771 for (i = 0; i < 4; ++i) { 772 if (vcstatus[i] == 0) 773 continue; 774 dsi_call_isrs(isr_tables->isr_table_vc[i], 775 ARRAY_SIZE(isr_tables->isr_table_vc[i]), 776 vcstatus[i]); 777 } 778 779 if (ciostatus != 0) 780 dsi_call_isrs(isr_tables->isr_table_cio, 781 ARRAY_SIZE(isr_tables->isr_table_cio), 782 ciostatus); 783 } 784 785 static irqreturn_t omap_dsi_irq_handler(int irq, void *arg) 786 { 787 struct platform_device *dsidev; 788 struct dsi_data *dsi; 789 u32 irqstatus, vcstatus[4], ciostatus; 790 int i; 791 792 dsidev = (struct platform_device *) arg; 793 dsi = dsi_get_dsidrv_data(dsidev); 794 795 if (!dsi->is_enabled) 796 return IRQ_NONE; 797 798 spin_lock(&dsi->irq_lock); 799 800 irqstatus = dsi_read_reg(dsidev, DSI_IRQSTATUS); 801 802 /* IRQ is not for us */ 803 if (!irqstatus) { 804 spin_unlock(&dsi->irq_lock); 805 return IRQ_NONE; 806 } 807 808 dsi_write_reg(dsidev, DSI_IRQSTATUS, irqstatus & ~DSI_IRQ_CHANNEL_MASK); 809 /* flush posted write */ 810 dsi_read_reg(dsidev, DSI_IRQSTATUS); 811 812 for (i = 0; i < 4; ++i) { 813 if ((irqstatus & (1 << i)) == 0) { 814 vcstatus[i] = 0; 815 continue; 816 } 817 818 vcstatus[i] = dsi_read_reg(dsidev, DSI_VC_IRQSTATUS(i)); 819 820 dsi_write_reg(dsidev, DSI_VC_IRQSTATUS(i), vcstatus[i]); 821 /* flush posted write */ 822 dsi_read_reg(dsidev, DSI_VC_IRQSTATUS(i)); 823 } 824 825 if (irqstatus & DSI_IRQ_COMPLEXIO_ERR) { 826 ciostatus = dsi_read_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS); 827 828 dsi_write_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS, ciostatus); 829 /* flush posted write */ 830 dsi_read_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS); 831 } else { 832 ciostatus = 0; 833 } 834 835 #ifdef DSI_CATCH_MISSING_TE 836 if (irqstatus & DSI_IRQ_TE_TRIGGER) 837 del_timer(&dsi->te_timer); 838 #endif 839 840 /* make a copy and unlock, so that isrs can unregister 841 * themselves */ 842 memcpy(&dsi->isr_tables_copy, &dsi->isr_tables, 843 sizeof(dsi->isr_tables)); 844 845 spin_unlock(&dsi->irq_lock); 846 847 dsi_handle_isrs(&dsi->isr_tables_copy, irqstatus, vcstatus, ciostatus); 848 849 dsi_handle_irq_errors(dsidev, irqstatus, vcstatus, ciostatus); 850 851 dsi_collect_irq_stats(dsidev, irqstatus, vcstatus, ciostatus); 852 853 return IRQ_HANDLED; 854 } 855 856 /* dsi->irq_lock has to be locked by the caller */ 857 static void _omap_dsi_configure_irqs(struct platform_device *dsidev, 858 struct dsi_isr_data *isr_array, 859 unsigned isr_array_size, u32 default_mask, 860 const struct dsi_reg enable_reg, 861 const struct dsi_reg status_reg) 862 { 863 struct dsi_isr_data *isr_data; 864 u32 mask; 865 u32 old_mask; 866 int i; 867 868 mask = default_mask; 869 870 for (i = 0; i < isr_array_size; i++) { 871 isr_data = &isr_array[i]; 872 873 if (isr_data->isr == NULL) 874 continue; 875 876 mask |= isr_data->mask; 877 } 878 879 old_mask = dsi_read_reg(dsidev, enable_reg); 880 /* clear the irqstatus for newly enabled irqs */ 881 dsi_write_reg(dsidev, status_reg, (mask ^ old_mask) & mask); 882 dsi_write_reg(dsidev, enable_reg, mask); 883 884 /* flush posted writes */ 885 dsi_read_reg(dsidev, enable_reg); 886 dsi_read_reg(dsidev, status_reg); 887 } 888 889 /* dsi->irq_lock has to be locked by the caller */ 890 static void _omap_dsi_set_irqs(struct platform_device *dsidev) 891 { 892 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 893 u32 mask = DSI_IRQ_ERROR_MASK; 894 #ifdef DSI_CATCH_MISSING_TE 895 mask |= DSI_IRQ_TE_TRIGGER; 896 #endif 897 _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table, 898 ARRAY_SIZE(dsi->isr_tables.isr_table), mask, 899 DSI_IRQENABLE, DSI_IRQSTATUS); 900 } 901 902 /* dsi->irq_lock has to be locked by the caller */ 903 static void _omap_dsi_set_irqs_vc(struct platform_device *dsidev, int vc) 904 { 905 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 906 907 _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table_vc[vc], 908 ARRAY_SIZE(dsi->isr_tables.isr_table_vc[vc]), 909 DSI_VC_IRQ_ERROR_MASK, 910 DSI_VC_IRQENABLE(vc), DSI_VC_IRQSTATUS(vc)); 911 } 912 913 /* dsi->irq_lock has to be locked by the caller */ 914 static void _omap_dsi_set_irqs_cio(struct platform_device *dsidev) 915 { 916 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 917 918 _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table_cio, 919 ARRAY_SIZE(dsi->isr_tables.isr_table_cio), 920 DSI_CIO_IRQ_ERROR_MASK, 921 DSI_COMPLEXIO_IRQ_ENABLE, DSI_COMPLEXIO_IRQ_STATUS); 922 } 923 924 static void _dsi_initialize_irq(struct platform_device *dsidev) 925 { 926 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 927 unsigned long flags; 928 int vc; 929 930 spin_lock_irqsave(&dsi->irq_lock, flags); 931 932 memset(&dsi->isr_tables, 0, sizeof(dsi->isr_tables)); 933 934 _omap_dsi_set_irqs(dsidev); 935 for (vc = 0; vc < 4; ++vc) 936 _omap_dsi_set_irqs_vc(dsidev, vc); 937 _omap_dsi_set_irqs_cio(dsidev); 938 939 spin_unlock_irqrestore(&dsi->irq_lock, flags); 940 } 941 942 static int _dsi_register_isr(omap_dsi_isr_t isr, void *arg, u32 mask, 943 struct dsi_isr_data *isr_array, unsigned isr_array_size) 944 { 945 struct dsi_isr_data *isr_data; 946 int free_idx; 947 int i; 948 949 BUG_ON(isr == NULL); 950 951 /* check for duplicate entry and find a free slot */ 952 free_idx = -1; 953 for (i = 0; i < isr_array_size; i++) { 954 isr_data = &isr_array[i]; 955 956 if (isr_data->isr == isr && isr_data->arg == arg && 957 isr_data->mask == mask) { 958 return -EINVAL; 959 } 960 961 if (isr_data->isr == NULL && free_idx == -1) 962 free_idx = i; 963 } 964 965 if (free_idx == -1) 966 return -EBUSY; 967 968 isr_data = &isr_array[free_idx]; 969 isr_data->isr = isr; 970 isr_data->arg = arg; 971 isr_data->mask = mask; 972 973 return 0; 974 } 975 976 static int _dsi_unregister_isr(omap_dsi_isr_t isr, void *arg, u32 mask, 977 struct dsi_isr_data *isr_array, unsigned isr_array_size) 978 { 979 struct dsi_isr_data *isr_data; 980 int i; 981 982 for (i = 0; i < isr_array_size; i++) { 983 isr_data = &isr_array[i]; 984 if (isr_data->isr != isr || isr_data->arg != arg || 985 isr_data->mask != mask) 986 continue; 987 988 isr_data->isr = NULL; 989 isr_data->arg = NULL; 990 isr_data->mask = 0; 991 992 return 0; 993 } 994 995 return -EINVAL; 996 } 997 998 static int dsi_register_isr(struct platform_device *dsidev, omap_dsi_isr_t isr, 999 void *arg, u32 mask) 1000 { 1001 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1002 unsigned long flags; 1003 int r; 1004 1005 spin_lock_irqsave(&dsi->irq_lock, flags); 1006 1007 r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table, 1008 ARRAY_SIZE(dsi->isr_tables.isr_table)); 1009 1010 if (r == 0) 1011 _omap_dsi_set_irqs(dsidev); 1012 1013 spin_unlock_irqrestore(&dsi->irq_lock, flags); 1014 1015 return r; 1016 } 1017 1018 static int dsi_unregister_isr(struct platform_device *dsidev, 1019 omap_dsi_isr_t isr, void *arg, u32 mask) 1020 { 1021 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1022 unsigned long flags; 1023 int r; 1024 1025 spin_lock_irqsave(&dsi->irq_lock, flags); 1026 1027 r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table, 1028 ARRAY_SIZE(dsi->isr_tables.isr_table)); 1029 1030 if (r == 0) 1031 _omap_dsi_set_irqs(dsidev); 1032 1033 spin_unlock_irqrestore(&dsi->irq_lock, flags); 1034 1035 return r; 1036 } 1037 1038 static int dsi_register_isr_vc(struct platform_device *dsidev, int channel, 1039 omap_dsi_isr_t isr, void *arg, u32 mask) 1040 { 1041 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1042 unsigned long flags; 1043 int r; 1044 1045 spin_lock_irqsave(&dsi->irq_lock, flags); 1046 1047 r = _dsi_register_isr(isr, arg, mask, 1048 dsi->isr_tables.isr_table_vc[channel], 1049 ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel])); 1050 1051 if (r == 0) 1052 _omap_dsi_set_irqs_vc(dsidev, channel); 1053 1054 spin_unlock_irqrestore(&dsi->irq_lock, flags); 1055 1056 return r; 1057 } 1058 1059 static int dsi_unregister_isr_vc(struct platform_device *dsidev, int channel, 1060 omap_dsi_isr_t isr, void *arg, u32 mask) 1061 { 1062 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1063 unsigned long flags; 1064 int r; 1065 1066 spin_lock_irqsave(&dsi->irq_lock, flags); 1067 1068 r = _dsi_unregister_isr(isr, arg, mask, 1069 dsi->isr_tables.isr_table_vc[channel], 1070 ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel])); 1071 1072 if (r == 0) 1073 _omap_dsi_set_irqs_vc(dsidev, channel); 1074 1075 spin_unlock_irqrestore(&dsi->irq_lock, flags); 1076 1077 return r; 1078 } 1079 1080 static int dsi_register_isr_cio(struct platform_device *dsidev, 1081 omap_dsi_isr_t isr, void *arg, u32 mask) 1082 { 1083 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1084 unsigned long flags; 1085 int r; 1086 1087 spin_lock_irqsave(&dsi->irq_lock, flags); 1088 1089 r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio, 1090 ARRAY_SIZE(dsi->isr_tables.isr_table_cio)); 1091 1092 if (r == 0) 1093 _omap_dsi_set_irqs_cio(dsidev); 1094 1095 spin_unlock_irqrestore(&dsi->irq_lock, flags); 1096 1097 return r; 1098 } 1099 1100 static int dsi_unregister_isr_cio(struct platform_device *dsidev, 1101 omap_dsi_isr_t isr, void *arg, u32 mask) 1102 { 1103 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1104 unsigned long flags; 1105 int r; 1106 1107 spin_lock_irqsave(&dsi->irq_lock, flags); 1108 1109 r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio, 1110 ARRAY_SIZE(dsi->isr_tables.isr_table_cio)); 1111 1112 if (r == 0) 1113 _omap_dsi_set_irqs_cio(dsidev); 1114 1115 spin_unlock_irqrestore(&dsi->irq_lock, flags); 1116 1117 return r; 1118 } 1119 1120 static u32 dsi_get_errors(struct platform_device *dsidev) 1121 { 1122 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1123 unsigned long flags; 1124 u32 e; 1125 spin_lock_irqsave(&dsi->errors_lock, flags); 1126 e = dsi->errors; 1127 dsi->errors = 0; 1128 spin_unlock_irqrestore(&dsi->errors_lock, flags); 1129 return e; 1130 } 1131 1132 static int dsi_runtime_get(struct platform_device *dsidev) 1133 { 1134 int r; 1135 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1136 1137 DSSDBG("dsi_runtime_get\n"); 1138 1139 r = pm_runtime_get_sync(&dsi->pdev->dev); 1140 if (WARN_ON(r < 0)) { 1141 pm_runtime_put_sync(&dsi->pdev->dev); 1142 return r; 1143 } 1144 return 0; 1145 } 1146 1147 static void dsi_runtime_put(struct platform_device *dsidev) 1148 { 1149 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1150 int r; 1151 1152 DSSDBG("dsi_runtime_put\n"); 1153 1154 r = pm_runtime_put_sync(&dsi->pdev->dev); 1155 WARN_ON(r < 0 && r != -ENOSYS); 1156 } 1157 1158 static int dsi_regulator_init(struct platform_device *dsidev) 1159 { 1160 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1161 struct regulator *vdds_dsi; 1162 1163 if (dsi->vdds_dsi_reg != NULL) 1164 return 0; 1165 1166 vdds_dsi = devm_regulator_get(&dsi->pdev->dev, "vdd"); 1167 1168 if (IS_ERR(vdds_dsi)) { 1169 if (PTR_ERR(vdds_dsi) != -EPROBE_DEFER) 1170 DSSERR("can't get DSI VDD regulator\n"); 1171 return PTR_ERR(vdds_dsi); 1172 } 1173 1174 dsi->vdds_dsi_reg = vdds_dsi; 1175 1176 return 0; 1177 } 1178 1179 static void _dsi_print_reset_status(struct platform_device *dsidev) 1180 { 1181 u32 l; 1182 int b0, b1, b2; 1183 1184 /* A dummy read using the SCP interface to any DSIPHY register is 1185 * required after DSIPHY reset to complete the reset of the DSI complex 1186 * I/O. */ 1187 l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5); 1188 1189 if (dss_has_feature(FEAT_DSI_REVERSE_TXCLKESC)) { 1190 b0 = 28; 1191 b1 = 27; 1192 b2 = 26; 1193 } else { 1194 b0 = 24; 1195 b1 = 25; 1196 b2 = 26; 1197 } 1198 1199 #define DSI_FLD_GET(fld, start, end)\ 1200 FLD_GET(dsi_read_reg(dsidev, DSI_##fld), start, end) 1201 1202 pr_debug("DSI resets: PLL (%d) CIO (%d) PHY (%x%x%x, %d, %d, %d)\n", 1203 DSI_FLD_GET(PLL_STATUS, 0, 0), 1204 DSI_FLD_GET(COMPLEXIO_CFG1, 29, 29), 1205 DSI_FLD_GET(DSIPHY_CFG5, b0, b0), 1206 DSI_FLD_GET(DSIPHY_CFG5, b1, b1), 1207 DSI_FLD_GET(DSIPHY_CFG5, b2, b2), 1208 DSI_FLD_GET(DSIPHY_CFG5, 29, 29), 1209 DSI_FLD_GET(DSIPHY_CFG5, 30, 30), 1210 DSI_FLD_GET(DSIPHY_CFG5, 31, 31)); 1211 1212 #undef DSI_FLD_GET 1213 } 1214 1215 static inline int dsi_if_enable(struct platform_device *dsidev, bool enable) 1216 { 1217 DSSDBG("dsi_if_enable(%d)\n", enable); 1218 1219 enable = enable ? 1 : 0; 1220 REG_FLD_MOD(dsidev, DSI_CTRL, enable, 0, 0); /* IF_EN */ 1221 1222 if (wait_for_bit_change(dsidev, DSI_CTRL, 0, enable) != enable) { 1223 DSSERR("Failed to set dsi_if_enable to %d\n", enable); 1224 return -EIO; 1225 } 1226 1227 return 0; 1228 } 1229 1230 static unsigned long dsi_get_pll_hsdiv_dispc_rate(struct platform_device *dsidev) 1231 { 1232 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1233 1234 return dsi->pll.cinfo.clkout[HSDIV_DISPC]; 1235 } 1236 1237 static unsigned long dsi_get_pll_hsdiv_dsi_rate(struct platform_device *dsidev) 1238 { 1239 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1240 1241 return dsi->pll.cinfo.clkout[HSDIV_DSI]; 1242 } 1243 1244 static unsigned long dsi_get_txbyteclkhs(struct platform_device *dsidev) 1245 { 1246 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1247 1248 return dsi->pll.cinfo.clkdco / 16; 1249 } 1250 1251 static unsigned long dsi_fclk_rate(struct platform_device *dsidev) 1252 { 1253 unsigned long r; 1254 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1255 1256 if (dss_get_dsi_clk_source(dsi->module_id) == OMAP_DSS_CLK_SRC_FCK) { 1257 /* DSI FCLK source is DSS_CLK_FCK */ 1258 r = clk_get_rate(dsi->dss_clk); 1259 } else { 1260 /* DSI FCLK source is dsi_pll_hsdiv_dsi_clk */ 1261 r = dsi_get_pll_hsdiv_dsi_rate(dsidev); 1262 } 1263 1264 return r; 1265 } 1266 1267 static int dsi_lp_clock_calc(unsigned long dsi_fclk, 1268 unsigned long lp_clk_min, unsigned long lp_clk_max, 1269 struct dsi_lp_clock_info *lp_cinfo) 1270 { 1271 unsigned lp_clk_div; 1272 unsigned long lp_clk; 1273 1274 lp_clk_div = DIV_ROUND_UP(dsi_fclk, lp_clk_max * 2); 1275 lp_clk = dsi_fclk / 2 / lp_clk_div; 1276 1277 if (lp_clk < lp_clk_min || lp_clk > lp_clk_max) 1278 return -EINVAL; 1279 1280 lp_cinfo->lp_clk_div = lp_clk_div; 1281 lp_cinfo->lp_clk = lp_clk; 1282 1283 return 0; 1284 } 1285 1286 static int dsi_set_lp_clk_divisor(struct platform_device *dsidev) 1287 { 1288 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1289 unsigned long dsi_fclk; 1290 unsigned lp_clk_div; 1291 unsigned long lp_clk; 1292 unsigned lpdiv_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_LPDIV); 1293 1294 1295 lp_clk_div = dsi->user_lp_cinfo.lp_clk_div; 1296 1297 if (lp_clk_div == 0 || lp_clk_div > lpdiv_max) 1298 return -EINVAL; 1299 1300 dsi_fclk = dsi_fclk_rate(dsidev); 1301 1302 lp_clk = dsi_fclk / 2 / lp_clk_div; 1303 1304 DSSDBG("LP_CLK_DIV %u, LP_CLK %lu\n", lp_clk_div, lp_clk); 1305 dsi->current_lp_cinfo.lp_clk = lp_clk; 1306 dsi->current_lp_cinfo.lp_clk_div = lp_clk_div; 1307 1308 /* LP_CLK_DIVISOR */ 1309 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, lp_clk_div, 12, 0); 1310 1311 /* LP_RX_SYNCHRO_ENABLE */ 1312 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, dsi_fclk > 30000000 ? 1 : 0, 21, 21); 1313 1314 return 0; 1315 } 1316 1317 static void dsi_enable_scp_clk(struct platform_device *dsidev) 1318 { 1319 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1320 1321 if (dsi->scp_clk_refcount++ == 0) 1322 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 14, 14); /* CIO_CLK_ICG */ 1323 } 1324 1325 static void dsi_disable_scp_clk(struct platform_device *dsidev) 1326 { 1327 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1328 1329 WARN_ON(dsi->scp_clk_refcount == 0); 1330 if (--dsi->scp_clk_refcount == 0) 1331 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 14, 14); /* CIO_CLK_ICG */ 1332 } 1333 1334 enum dsi_pll_power_state { 1335 DSI_PLL_POWER_OFF = 0x0, 1336 DSI_PLL_POWER_ON_HSCLK = 0x1, 1337 DSI_PLL_POWER_ON_ALL = 0x2, 1338 DSI_PLL_POWER_ON_DIV = 0x3, 1339 }; 1340 1341 static int dsi_pll_power(struct platform_device *dsidev, 1342 enum dsi_pll_power_state state) 1343 { 1344 int t = 0; 1345 1346 /* DSI-PLL power command 0x3 is not working */ 1347 if (dss_has_feature(FEAT_DSI_PLL_PWR_BUG) && 1348 state == DSI_PLL_POWER_ON_DIV) 1349 state = DSI_PLL_POWER_ON_ALL; 1350 1351 /* PLL_PWR_CMD */ 1352 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, state, 31, 30); 1353 1354 /* PLL_PWR_STATUS */ 1355 while (FLD_GET(dsi_read_reg(dsidev, DSI_CLK_CTRL), 29, 28) != state) { 1356 if (++t > 1000) { 1357 DSSERR("Failed to set DSI PLL power mode to %d\n", 1358 state); 1359 return -ENODEV; 1360 } 1361 udelay(1); 1362 } 1363 1364 return 0; 1365 } 1366 1367 1368 static void dsi_pll_calc_dsi_fck(struct dss_pll_clock_info *cinfo) 1369 { 1370 unsigned long max_dsi_fck; 1371 1372 max_dsi_fck = dss_feat_get_param_max(FEAT_PARAM_DSI_FCK); 1373 1374 cinfo->mX[HSDIV_DSI] = DIV_ROUND_UP(cinfo->clkdco, max_dsi_fck); 1375 cinfo->clkout[HSDIV_DSI] = cinfo->clkdco / cinfo->mX[HSDIV_DSI]; 1376 } 1377 1378 static int dsi_pll_enable(struct dss_pll *pll) 1379 { 1380 struct dsi_data *dsi = container_of(pll, struct dsi_data, pll); 1381 struct platform_device *dsidev = dsi->pdev; 1382 int r = 0; 1383 1384 DSSDBG("PLL init\n"); 1385 1386 r = dsi_regulator_init(dsidev); 1387 if (r) 1388 return r; 1389 1390 r = dsi_runtime_get(dsidev); 1391 if (r) 1392 return r; 1393 1394 /* 1395 * Note: SCP CLK is not required on OMAP3, but it is required on OMAP4. 1396 */ 1397 dsi_enable_scp_clk(dsidev); 1398 1399 if (!dsi->vdds_dsi_enabled) { 1400 r = regulator_enable(dsi->vdds_dsi_reg); 1401 if (r) 1402 goto err0; 1403 dsi->vdds_dsi_enabled = true; 1404 } 1405 1406 /* XXX PLL does not come out of reset without this... */ 1407 dispc_pck_free_enable(1); 1408 1409 if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 0, 1) != 1) { 1410 DSSERR("PLL not coming out of reset.\n"); 1411 r = -ENODEV; 1412 dispc_pck_free_enable(0); 1413 goto err1; 1414 } 1415 1416 /* XXX ... but if left on, we get problems when planes do not 1417 * fill the whole display. No idea about this */ 1418 dispc_pck_free_enable(0); 1419 1420 r = dsi_pll_power(dsidev, DSI_PLL_POWER_ON_ALL); 1421 1422 if (r) 1423 goto err1; 1424 1425 DSSDBG("PLL init done\n"); 1426 1427 return 0; 1428 err1: 1429 if (dsi->vdds_dsi_enabled) { 1430 regulator_disable(dsi->vdds_dsi_reg); 1431 dsi->vdds_dsi_enabled = false; 1432 } 1433 err0: 1434 dsi_disable_scp_clk(dsidev); 1435 dsi_runtime_put(dsidev); 1436 return r; 1437 } 1438 1439 static void dsi_pll_uninit(struct platform_device *dsidev, bool disconnect_lanes) 1440 { 1441 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1442 1443 dsi_pll_power(dsidev, DSI_PLL_POWER_OFF); 1444 if (disconnect_lanes) { 1445 WARN_ON(!dsi->vdds_dsi_enabled); 1446 regulator_disable(dsi->vdds_dsi_reg); 1447 dsi->vdds_dsi_enabled = false; 1448 } 1449 1450 dsi_disable_scp_clk(dsidev); 1451 dsi_runtime_put(dsidev); 1452 1453 DSSDBG("PLL uninit done\n"); 1454 } 1455 1456 static void dsi_pll_disable(struct dss_pll *pll) 1457 { 1458 struct dsi_data *dsi = container_of(pll, struct dsi_data, pll); 1459 struct platform_device *dsidev = dsi->pdev; 1460 1461 dsi_pll_uninit(dsidev, true); 1462 } 1463 1464 static void dsi_dump_dsidev_clocks(struct platform_device *dsidev, 1465 struct seq_file *s) 1466 { 1467 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1468 struct dss_pll_clock_info *cinfo = &dsi->pll.cinfo; 1469 enum omap_dss_clk_source dispc_clk_src, dsi_clk_src; 1470 int dsi_module = dsi->module_id; 1471 struct dss_pll *pll = &dsi->pll; 1472 1473 dispc_clk_src = dss_get_dispc_clk_source(); 1474 dsi_clk_src = dss_get_dsi_clk_source(dsi_module); 1475 1476 if (dsi_runtime_get(dsidev)) 1477 return; 1478 1479 seq_printf(s, "- DSI%d PLL -\n", dsi_module + 1); 1480 1481 seq_printf(s, "dsi pll clkin\t%lu\n", clk_get_rate(pll->clkin)); 1482 1483 seq_printf(s, "Fint\t\t%-16lun %u\n", cinfo->fint, cinfo->n); 1484 1485 seq_printf(s, "CLKIN4DDR\t%-16lum %u\n", 1486 cinfo->clkdco, cinfo->m); 1487 1488 seq_printf(s, "DSI_PLL_HSDIV_DISPC (%s)\t%-16lum_dispc %u\t(%s)\n", 1489 dss_feat_get_clk_source_name(dsi_module == 0 ? 1490 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC : 1491 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC), 1492 cinfo->clkout[HSDIV_DISPC], 1493 cinfo->mX[HSDIV_DISPC], 1494 dispc_clk_src == OMAP_DSS_CLK_SRC_FCK ? 1495 "off" : "on"); 1496 1497 seq_printf(s, "DSI_PLL_HSDIV_DSI (%s)\t%-16lum_dsi %u\t(%s)\n", 1498 dss_feat_get_clk_source_name(dsi_module == 0 ? 1499 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI : 1500 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI), 1501 cinfo->clkout[HSDIV_DSI], 1502 cinfo->mX[HSDIV_DSI], 1503 dsi_clk_src == OMAP_DSS_CLK_SRC_FCK ? 1504 "off" : "on"); 1505 1506 seq_printf(s, "- DSI%d -\n", dsi_module + 1); 1507 1508 seq_printf(s, "dsi fclk source = %s (%s)\n", 1509 dss_get_generic_clk_source_name(dsi_clk_src), 1510 dss_feat_get_clk_source_name(dsi_clk_src)); 1511 1512 seq_printf(s, "DSI_FCLK\t%lu\n", dsi_fclk_rate(dsidev)); 1513 1514 seq_printf(s, "DDR_CLK\t\t%lu\n", 1515 cinfo->clkdco / 4); 1516 1517 seq_printf(s, "TxByteClkHS\t%lu\n", dsi_get_txbyteclkhs(dsidev)); 1518 1519 seq_printf(s, "LP_CLK\t\t%lu\n", dsi->current_lp_cinfo.lp_clk); 1520 1521 dsi_runtime_put(dsidev); 1522 } 1523 1524 void dsi_dump_clocks(struct seq_file *s) 1525 { 1526 struct platform_device *dsidev; 1527 int i; 1528 1529 for (i = 0; i < MAX_NUM_DSI; i++) { 1530 dsidev = dsi_get_dsidev_from_id(i); 1531 if (dsidev) 1532 dsi_dump_dsidev_clocks(dsidev, s); 1533 } 1534 } 1535 1536 #ifdef CONFIG_FB_OMAP2_DSS_COLLECT_IRQ_STATS 1537 static void dsi_dump_dsidev_irqs(struct platform_device *dsidev, 1538 struct seq_file *s) 1539 { 1540 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1541 unsigned long flags; 1542 struct dsi_irq_stats stats; 1543 1544 spin_lock_irqsave(&dsi->irq_stats_lock, flags); 1545 1546 stats = dsi->irq_stats; 1547 memset(&dsi->irq_stats, 0, sizeof(dsi->irq_stats)); 1548 dsi->irq_stats.last_reset = jiffies; 1549 1550 spin_unlock_irqrestore(&dsi->irq_stats_lock, flags); 1551 1552 seq_printf(s, "period %u ms\n", 1553 jiffies_to_msecs(jiffies - stats.last_reset)); 1554 1555 seq_printf(s, "irqs %d\n", stats.irq_count); 1556 #define PIS(x) \ 1557 seq_printf(s, "%-20s %10d\n", #x, stats.dsi_irqs[ffs(DSI_IRQ_##x)-1]); 1558 1559 seq_printf(s, "-- DSI%d interrupts --\n", dsi->module_id + 1); 1560 PIS(VC0); 1561 PIS(VC1); 1562 PIS(VC2); 1563 PIS(VC3); 1564 PIS(WAKEUP); 1565 PIS(RESYNC); 1566 PIS(PLL_LOCK); 1567 PIS(PLL_UNLOCK); 1568 PIS(PLL_RECALL); 1569 PIS(COMPLEXIO_ERR); 1570 PIS(HS_TX_TIMEOUT); 1571 PIS(LP_RX_TIMEOUT); 1572 PIS(TE_TRIGGER); 1573 PIS(ACK_TRIGGER); 1574 PIS(SYNC_LOST); 1575 PIS(LDO_POWER_GOOD); 1576 PIS(TA_TIMEOUT); 1577 #undef PIS 1578 1579 #define PIS(x) \ 1580 seq_printf(s, "%-20s %10d %10d %10d %10d\n", #x, \ 1581 stats.vc_irqs[0][ffs(DSI_VC_IRQ_##x)-1], \ 1582 stats.vc_irqs[1][ffs(DSI_VC_IRQ_##x)-1], \ 1583 stats.vc_irqs[2][ffs(DSI_VC_IRQ_##x)-1], \ 1584 stats.vc_irqs[3][ffs(DSI_VC_IRQ_##x)-1]); 1585 1586 seq_printf(s, "-- VC interrupts --\n"); 1587 PIS(CS); 1588 PIS(ECC_CORR); 1589 PIS(PACKET_SENT); 1590 PIS(FIFO_TX_OVF); 1591 PIS(FIFO_RX_OVF); 1592 PIS(BTA); 1593 PIS(ECC_NO_CORR); 1594 PIS(FIFO_TX_UDF); 1595 PIS(PP_BUSY_CHANGE); 1596 #undef PIS 1597 1598 #define PIS(x) \ 1599 seq_printf(s, "%-20s %10d\n", #x, \ 1600 stats.cio_irqs[ffs(DSI_CIO_IRQ_##x)-1]); 1601 1602 seq_printf(s, "-- CIO interrupts --\n"); 1603 PIS(ERRSYNCESC1); 1604 PIS(ERRSYNCESC2); 1605 PIS(ERRSYNCESC3); 1606 PIS(ERRESC1); 1607 PIS(ERRESC2); 1608 PIS(ERRESC3); 1609 PIS(ERRCONTROL1); 1610 PIS(ERRCONTROL2); 1611 PIS(ERRCONTROL3); 1612 PIS(STATEULPS1); 1613 PIS(STATEULPS2); 1614 PIS(STATEULPS3); 1615 PIS(ERRCONTENTIONLP0_1); 1616 PIS(ERRCONTENTIONLP1_1); 1617 PIS(ERRCONTENTIONLP0_2); 1618 PIS(ERRCONTENTIONLP1_2); 1619 PIS(ERRCONTENTIONLP0_3); 1620 PIS(ERRCONTENTIONLP1_3); 1621 PIS(ULPSACTIVENOT_ALL0); 1622 PIS(ULPSACTIVENOT_ALL1); 1623 #undef PIS 1624 } 1625 1626 static void dsi1_dump_irqs(struct seq_file *s) 1627 { 1628 struct platform_device *dsidev = dsi_get_dsidev_from_id(0); 1629 1630 dsi_dump_dsidev_irqs(dsidev, s); 1631 } 1632 1633 static void dsi2_dump_irqs(struct seq_file *s) 1634 { 1635 struct platform_device *dsidev = dsi_get_dsidev_from_id(1); 1636 1637 dsi_dump_dsidev_irqs(dsidev, s); 1638 } 1639 #endif 1640 1641 static void dsi_dump_dsidev_regs(struct platform_device *dsidev, 1642 struct seq_file *s) 1643 { 1644 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(dsidev, r)) 1645 1646 if (dsi_runtime_get(dsidev)) 1647 return; 1648 dsi_enable_scp_clk(dsidev); 1649 1650 DUMPREG(DSI_REVISION); 1651 DUMPREG(DSI_SYSCONFIG); 1652 DUMPREG(DSI_SYSSTATUS); 1653 DUMPREG(DSI_IRQSTATUS); 1654 DUMPREG(DSI_IRQENABLE); 1655 DUMPREG(DSI_CTRL); 1656 DUMPREG(DSI_COMPLEXIO_CFG1); 1657 DUMPREG(DSI_COMPLEXIO_IRQ_STATUS); 1658 DUMPREG(DSI_COMPLEXIO_IRQ_ENABLE); 1659 DUMPREG(DSI_CLK_CTRL); 1660 DUMPREG(DSI_TIMING1); 1661 DUMPREG(DSI_TIMING2); 1662 DUMPREG(DSI_VM_TIMING1); 1663 DUMPREG(DSI_VM_TIMING2); 1664 DUMPREG(DSI_VM_TIMING3); 1665 DUMPREG(DSI_CLK_TIMING); 1666 DUMPREG(DSI_TX_FIFO_VC_SIZE); 1667 DUMPREG(DSI_RX_FIFO_VC_SIZE); 1668 DUMPREG(DSI_COMPLEXIO_CFG2); 1669 DUMPREG(DSI_RX_FIFO_VC_FULLNESS); 1670 DUMPREG(DSI_VM_TIMING4); 1671 DUMPREG(DSI_TX_FIFO_VC_EMPTINESS); 1672 DUMPREG(DSI_VM_TIMING5); 1673 DUMPREG(DSI_VM_TIMING6); 1674 DUMPREG(DSI_VM_TIMING7); 1675 DUMPREG(DSI_STOPCLK_TIMING); 1676 1677 DUMPREG(DSI_VC_CTRL(0)); 1678 DUMPREG(DSI_VC_TE(0)); 1679 DUMPREG(DSI_VC_LONG_PACKET_HEADER(0)); 1680 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(0)); 1681 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(0)); 1682 DUMPREG(DSI_VC_IRQSTATUS(0)); 1683 DUMPREG(DSI_VC_IRQENABLE(0)); 1684 1685 DUMPREG(DSI_VC_CTRL(1)); 1686 DUMPREG(DSI_VC_TE(1)); 1687 DUMPREG(DSI_VC_LONG_PACKET_HEADER(1)); 1688 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(1)); 1689 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(1)); 1690 DUMPREG(DSI_VC_IRQSTATUS(1)); 1691 DUMPREG(DSI_VC_IRQENABLE(1)); 1692 1693 DUMPREG(DSI_VC_CTRL(2)); 1694 DUMPREG(DSI_VC_TE(2)); 1695 DUMPREG(DSI_VC_LONG_PACKET_HEADER(2)); 1696 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(2)); 1697 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(2)); 1698 DUMPREG(DSI_VC_IRQSTATUS(2)); 1699 DUMPREG(DSI_VC_IRQENABLE(2)); 1700 1701 DUMPREG(DSI_VC_CTRL(3)); 1702 DUMPREG(DSI_VC_TE(3)); 1703 DUMPREG(DSI_VC_LONG_PACKET_HEADER(3)); 1704 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(3)); 1705 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(3)); 1706 DUMPREG(DSI_VC_IRQSTATUS(3)); 1707 DUMPREG(DSI_VC_IRQENABLE(3)); 1708 1709 DUMPREG(DSI_DSIPHY_CFG0); 1710 DUMPREG(DSI_DSIPHY_CFG1); 1711 DUMPREG(DSI_DSIPHY_CFG2); 1712 DUMPREG(DSI_DSIPHY_CFG5); 1713 1714 DUMPREG(DSI_PLL_CONTROL); 1715 DUMPREG(DSI_PLL_STATUS); 1716 DUMPREG(DSI_PLL_GO); 1717 DUMPREG(DSI_PLL_CONFIGURATION1); 1718 DUMPREG(DSI_PLL_CONFIGURATION2); 1719 1720 dsi_disable_scp_clk(dsidev); 1721 dsi_runtime_put(dsidev); 1722 #undef DUMPREG 1723 } 1724 1725 static void dsi1_dump_regs(struct seq_file *s) 1726 { 1727 struct platform_device *dsidev = dsi_get_dsidev_from_id(0); 1728 1729 dsi_dump_dsidev_regs(dsidev, s); 1730 } 1731 1732 static void dsi2_dump_regs(struct seq_file *s) 1733 { 1734 struct platform_device *dsidev = dsi_get_dsidev_from_id(1); 1735 1736 dsi_dump_dsidev_regs(dsidev, s); 1737 } 1738 1739 enum dsi_cio_power_state { 1740 DSI_COMPLEXIO_POWER_OFF = 0x0, 1741 DSI_COMPLEXIO_POWER_ON = 0x1, 1742 DSI_COMPLEXIO_POWER_ULPS = 0x2, 1743 }; 1744 1745 static int dsi_cio_power(struct platform_device *dsidev, 1746 enum dsi_cio_power_state state) 1747 { 1748 int t = 0; 1749 1750 /* PWR_CMD */ 1751 REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG1, state, 28, 27); 1752 1753 /* PWR_STATUS */ 1754 while (FLD_GET(dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1), 1755 26, 25) != state) { 1756 if (++t > 1000) { 1757 DSSERR("failed to set complexio power state to " 1758 "%d\n", state); 1759 return -ENODEV; 1760 } 1761 udelay(1); 1762 } 1763 1764 return 0; 1765 } 1766 1767 static unsigned dsi_get_line_buf_size(struct platform_device *dsidev) 1768 { 1769 int val; 1770 1771 /* line buffer on OMAP3 is 1024 x 24bits */ 1772 /* XXX: for some reason using full buffer size causes 1773 * considerable TX slowdown with update sizes that fill the 1774 * whole buffer */ 1775 if (!dss_has_feature(FEAT_DSI_GNQ)) 1776 return 1023 * 3; 1777 1778 val = REG_GET(dsidev, DSI_GNQ, 14, 12); /* VP1_LINE_BUFFER_SIZE */ 1779 1780 switch (val) { 1781 case 1: 1782 return 512 * 3; /* 512x24 bits */ 1783 case 2: 1784 return 682 * 3; /* 682x24 bits */ 1785 case 3: 1786 return 853 * 3; /* 853x24 bits */ 1787 case 4: 1788 return 1024 * 3; /* 1024x24 bits */ 1789 case 5: 1790 return 1194 * 3; /* 1194x24 bits */ 1791 case 6: 1792 return 1365 * 3; /* 1365x24 bits */ 1793 case 7: 1794 return 1920 * 3; /* 1920x24 bits */ 1795 default: 1796 BUG(); 1797 return 0; 1798 } 1799 } 1800 1801 static int dsi_set_lane_config(struct platform_device *dsidev) 1802 { 1803 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1804 static const u8 offsets[] = { 0, 4, 8, 12, 16 }; 1805 static const enum dsi_lane_function functions[] = { 1806 DSI_LANE_CLK, 1807 DSI_LANE_DATA1, 1808 DSI_LANE_DATA2, 1809 DSI_LANE_DATA3, 1810 DSI_LANE_DATA4, 1811 }; 1812 u32 r; 1813 int i; 1814 1815 r = dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1); 1816 1817 for (i = 0; i < dsi->num_lanes_used; ++i) { 1818 unsigned offset = offsets[i]; 1819 unsigned polarity, lane_number; 1820 unsigned t; 1821 1822 for (t = 0; t < dsi->num_lanes_supported; ++t) 1823 if (dsi->lanes[t].function == functions[i]) 1824 break; 1825 1826 if (t == dsi->num_lanes_supported) 1827 return -EINVAL; 1828 1829 lane_number = t; 1830 polarity = dsi->lanes[t].polarity; 1831 1832 r = FLD_MOD(r, lane_number + 1, offset + 2, offset); 1833 r = FLD_MOD(r, polarity, offset + 3, offset + 3); 1834 } 1835 1836 /* clear the unused lanes */ 1837 for (; i < dsi->num_lanes_supported; ++i) { 1838 unsigned offset = offsets[i]; 1839 1840 r = FLD_MOD(r, 0, offset + 2, offset); 1841 r = FLD_MOD(r, 0, offset + 3, offset + 3); 1842 } 1843 1844 dsi_write_reg(dsidev, DSI_COMPLEXIO_CFG1, r); 1845 1846 return 0; 1847 } 1848 1849 static inline unsigned ns2ddr(struct platform_device *dsidev, unsigned ns) 1850 { 1851 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1852 1853 /* convert time in ns to ddr ticks, rounding up */ 1854 unsigned long ddr_clk = dsi->pll.cinfo.clkdco / 4; 1855 return (ns * (ddr_clk / 1000 / 1000) + 999) / 1000; 1856 } 1857 1858 static inline unsigned ddr2ns(struct platform_device *dsidev, unsigned ddr) 1859 { 1860 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1861 1862 unsigned long ddr_clk = dsi->pll.cinfo.clkdco / 4; 1863 return ddr * 1000 * 1000 / (ddr_clk / 1000); 1864 } 1865 1866 static void dsi_cio_timings(struct platform_device *dsidev) 1867 { 1868 u32 r; 1869 u32 ths_prepare, ths_prepare_ths_zero, ths_trail, ths_exit; 1870 u32 tlpx_half, tclk_trail, tclk_zero; 1871 u32 tclk_prepare; 1872 1873 /* calculate timings */ 1874 1875 /* 1 * DDR_CLK = 2 * UI */ 1876 1877 /* min 40ns + 4*UI max 85ns + 6*UI */ 1878 ths_prepare = ns2ddr(dsidev, 70) + 2; 1879 1880 /* min 145ns + 10*UI */ 1881 ths_prepare_ths_zero = ns2ddr(dsidev, 175) + 2; 1882 1883 /* min max(8*UI, 60ns+4*UI) */ 1884 ths_trail = ns2ddr(dsidev, 60) + 5; 1885 1886 /* min 100ns */ 1887 ths_exit = ns2ddr(dsidev, 145); 1888 1889 /* tlpx min 50n */ 1890 tlpx_half = ns2ddr(dsidev, 25); 1891 1892 /* min 60ns */ 1893 tclk_trail = ns2ddr(dsidev, 60) + 2; 1894 1895 /* min 38ns, max 95ns */ 1896 tclk_prepare = ns2ddr(dsidev, 65); 1897 1898 /* min tclk-prepare + tclk-zero = 300ns */ 1899 tclk_zero = ns2ddr(dsidev, 260); 1900 1901 DSSDBG("ths_prepare %u (%uns), ths_prepare_ths_zero %u (%uns)\n", 1902 ths_prepare, ddr2ns(dsidev, ths_prepare), 1903 ths_prepare_ths_zero, ddr2ns(dsidev, ths_prepare_ths_zero)); 1904 DSSDBG("ths_trail %u (%uns), ths_exit %u (%uns)\n", 1905 ths_trail, ddr2ns(dsidev, ths_trail), 1906 ths_exit, ddr2ns(dsidev, ths_exit)); 1907 1908 DSSDBG("tlpx_half %u (%uns), tclk_trail %u (%uns), " 1909 "tclk_zero %u (%uns)\n", 1910 tlpx_half, ddr2ns(dsidev, tlpx_half), 1911 tclk_trail, ddr2ns(dsidev, tclk_trail), 1912 tclk_zero, ddr2ns(dsidev, tclk_zero)); 1913 DSSDBG("tclk_prepare %u (%uns)\n", 1914 tclk_prepare, ddr2ns(dsidev, tclk_prepare)); 1915 1916 /* program timings */ 1917 1918 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0); 1919 r = FLD_MOD(r, ths_prepare, 31, 24); 1920 r = FLD_MOD(r, ths_prepare_ths_zero, 23, 16); 1921 r = FLD_MOD(r, ths_trail, 15, 8); 1922 r = FLD_MOD(r, ths_exit, 7, 0); 1923 dsi_write_reg(dsidev, DSI_DSIPHY_CFG0, r); 1924 1925 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1); 1926 r = FLD_MOD(r, tlpx_half, 20, 16); 1927 r = FLD_MOD(r, tclk_trail, 15, 8); 1928 r = FLD_MOD(r, tclk_zero, 7, 0); 1929 1930 if (dss_has_feature(FEAT_DSI_PHY_DCC)) { 1931 r = FLD_MOD(r, 0, 21, 21); /* DCCEN = disable */ 1932 r = FLD_MOD(r, 1, 22, 22); /* CLKINP_DIVBY2EN = enable */ 1933 r = FLD_MOD(r, 1, 23, 23); /* CLKINP_SEL = enable */ 1934 } 1935 1936 dsi_write_reg(dsidev, DSI_DSIPHY_CFG1, r); 1937 1938 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG2); 1939 r = FLD_MOD(r, tclk_prepare, 7, 0); 1940 dsi_write_reg(dsidev, DSI_DSIPHY_CFG2, r); 1941 } 1942 1943 /* lane masks have lane 0 at lsb. mask_p for positive lines, n for negative */ 1944 static void dsi_cio_enable_lane_override(struct platform_device *dsidev, 1945 unsigned mask_p, unsigned mask_n) 1946 { 1947 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1948 int i; 1949 u32 l; 1950 u8 lptxscp_start = dsi->num_lanes_supported == 3 ? 22 : 26; 1951 1952 l = 0; 1953 1954 for (i = 0; i < dsi->num_lanes_supported; ++i) { 1955 unsigned p = dsi->lanes[i].polarity; 1956 1957 if (mask_p & (1 << i)) 1958 l |= 1 << (i * 2 + (p ? 0 : 1)); 1959 1960 if (mask_n & (1 << i)) 1961 l |= 1 << (i * 2 + (p ? 1 : 0)); 1962 } 1963 1964 /* 1965 * Bits in REGLPTXSCPDAT4TO0DXDY: 1966 * 17: DY0 18: DX0 1967 * 19: DY1 20: DX1 1968 * 21: DY2 22: DX2 1969 * 23: DY3 24: DX3 1970 * 25: DY4 26: DX4 1971 */ 1972 1973 /* Set the lane override configuration */ 1974 1975 /* REGLPTXSCPDAT4TO0DXDY */ 1976 REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, l, lptxscp_start, 17); 1977 1978 /* Enable lane override */ 1979 1980 /* ENLPTXSCPDAT */ 1981 REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 1, 27, 27); 1982 } 1983 1984 static void dsi_cio_disable_lane_override(struct platform_device *dsidev) 1985 { 1986 /* Disable lane override */ 1987 REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 0, 27, 27); /* ENLPTXSCPDAT */ 1988 /* Reset the lane override configuration */ 1989 /* REGLPTXSCPDAT4TO0DXDY */ 1990 REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 0, 22, 17); 1991 } 1992 1993 static int dsi_cio_wait_tx_clk_esc_reset(struct platform_device *dsidev) 1994 { 1995 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1996 int t, i; 1997 bool in_use[DSI_MAX_NR_LANES]; 1998 static const u8 offsets_old[] = { 28, 27, 26 }; 1999 static const u8 offsets_new[] = { 24, 25, 26, 27, 28 }; 2000 const u8 *offsets; 2001 2002 if (dss_has_feature(FEAT_DSI_REVERSE_TXCLKESC)) 2003 offsets = offsets_old; 2004 else 2005 offsets = offsets_new; 2006 2007 for (i = 0; i < dsi->num_lanes_supported; ++i) 2008 in_use[i] = dsi->lanes[i].function != DSI_LANE_UNUSED; 2009 2010 t = 100000; 2011 while (true) { 2012 u32 l; 2013 int ok; 2014 2015 l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5); 2016 2017 ok = 0; 2018 for (i = 0; i < dsi->num_lanes_supported; ++i) { 2019 if (!in_use[i] || (l & (1 << offsets[i]))) 2020 ok++; 2021 } 2022 2023 if (ok == dsi->num_lanes_supported) 2024 break; 2025 2026 if (--t == 0) { 2027 for (i = 0; i < dsi->num_lanes_supported; ++i) { 2028 if (!in_use[i] || (l & (1 << offsets[i]))) 2029 continue; 2030 2031 DSSERR("CIO TXCLKESC%d domain not coming " \ 2032 "out of reset\n", i); 2033 } 2034 return -EIO; 2035 } 2036 } 2037 2038 return 0; 2039 } 2040 2041 /* return bitmask of enabled lanes, lane0 being the lsb */ 2042 static unsigned dsi_get_lane_mask(struct platform_device *dsidev) 2043 { 2044 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 2045 unsigned mask = 0; 2046 int i; 2047 2048 for (i = 0; i < dsi->num_lanes_supported; ++i) { 2049 if (dsi->lanes[i].function != DSI_LANE_UNUSED) 2050 mask |= 1 << i; 2051 } 2052 2053 return mask; 2054 } 2055 2056 static int dsi_cio_init(struct platform_device *dsidev) 2057 { 2058 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 2059 int r; 2060 u32 l; 2061 2062 DSSDBG("DSI CIO init starts"); 2063 2064 r = dss_dsi_enable_pads(dsi->module_id, dsi_get_lane_mask(dsidev)); 2065 if (r) 2066 return r; 2067 2068 dsi_enable_scp_clk(dsidev); 2069 2070 /* A dummy read using the SCP interface to any DSIPHY register is 2071 * required after DSIPHY reset to complete the reset of the DSI complex 2072 * I/O. */ 2073 dsi_read_reg(dsidev, DSI_DSIPHY_CFG5); 2074 2075 if (wait_for_bit_change(dsidev, DSI_DSIPHY_CFG5, 30, 1) != 1) { 2076 DSSERR("CIO SCP Clock domain not coming out of reset.\n"); 2077 r = -EIO; 2078 goto err_scp_clk_dom; 2079 } 2080 2081 r = dsi_set_lane_config(dsidev); 2082 if (r) 2083 goto err_scp_clk_dom; 2084 2085 /* set TX STOP MODE timer to maximum for this operation */ 2086 l = dsi_read_reg(dsidev, DSI_TIMING1); 2087 l = FLD_MOD(l, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */ 2088 l = FLD_MOD(l, 1, 14, 14); /* STOP_STATE_X16_IO */ 2089 l = FLD_MOD(l, 1, 13, 13); /* STOP_STATE_X4_IO */ 2090 l = FLD_MOD(l, 0x1fff, 12, 0); /* STOP_STATE_COUNTER_IO */ 2091 dsi_write_reg(dsidev, DSI_TIMING1, l); 2092 2093 if (dsi->ulps_enabled) { 2094 unsigned mask_p; 2095 int i; 2096 2097 DSSDBG("manual ulps exit\n"); 2098 2099 /* ULPS is exited by Mark-1 state for 1ms, followed by 2100 * stop state. DSS HW cannot do this via the normal 2101 * ULPS exit sequence, as after reset the DSS HW thinks 2102 * that we are not in ULPS mode, and refuses to send the 2103 * sequence. So we need to send the ULPS exit sequence 2104 * manually by setting positive lines high and negative lines 2105 * low for 1ms. 2106 */ 2107 2108 mask_p = 0; 2109 2110 for (i = 0; i < dsi->num_lanes_supported; ++i) { 2111 if (dsi->lanes[i].function == DSI_LANE_UNUSED) 2112 continue; 2113 mask_p |= 1 << i; 2114 } 2115 2116 dsi_cio_enable_lane_override(dsidev, mask_p, 0); 2117 } 2118 2119 r = dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_ON); 2120 if (r) 2121 goto err_cio_pwr; 2122 2123 if (wait_for_bit_change(dsidev, DSI_COMPLEXIO_CFG1, 29, 1) != 1) { 2124 DSSERR("CIO PWR clock domain not coming out of reset.\n"); 2125 r = -ENODEV; 2126 goto err_cio_pwr_dom; 2127 } 2128 2129 dsi_if_enable(dsidev, true); 2130 dsi_if_enable(dsidev, false); 2131 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 20, 20); /* LP_CLK_ENABLE */ 2132 2133 r = dsi_cio_wait_tx_clk_esc_reset(dsidev); 2134 if (r) 2135 goto err_tx_clk_esc_rst; 2136 2137 if (dsi->ulps_enabled) { 2138 /* Keep Mark-1 state for 1ms (as per DSI spec) */ 2139 ktime_t wait = ns_to_ktime(1000 * 1000); 2140 set_current_state(TASK_UNINTERRUPTIBLE); 2141 schedule_hrtimeout(&wait, HRTIMER_MODE_REL); 2142 2143 /* Disable the override. The lanes should be set to Mark-11 2144 * state by the HW */ 2145 dsi_cio_disable_lane_override(dsidev); 2146 } 2147 2148 /* FORCE_TX_STOP_MODE_IO */ 2149 REG_FLD_MOD(dsidev, DSI_TIMING1, 0, 15, 15); 2150 2151 dsi_cio_timings(dsidev); 2152 2153 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) { 2154 /* DDR_CLK_ALWAYS_ON */ 2155 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 2156 dsi->vm_timings.ddr_clk_always_on, 13, 13); 2157 } 2158 2159 dsi->ulps_enabled = false; 2160 2161 DSSDBG("CIO init done\n"); 2162 2163 return 0; 2164 2165 err_tx_clk_esc_rst: 2166 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 20, 20); /* LP_CLK_ENABLE */ 2167 err_cio_pwr_dom: 2168 dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_OFF); 2169 err_cio_pwr: 2170 if (dsi->ulps_enabled) 2171 dsi_cio_disable_lane_override(dsidev); 2172 err_scp_clk_dom: 2173 dsi_disable_scp_clk(dsidev); 2174 dss_dsi_disable_pads(dsi->module_id, dsi_get_lane_mask(dsidev)); 2175 return r; 2176 } 2177 2178 static void dsi_cio_uninit(struct platform_device *dsidev) 2179 { 2180 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 2181 2182 /* DDR_CLK_ALWAYS_ON */ 2183 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 13, 13); 2184 2185 dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_OFF); 2186 dsi_disable_scp_clk(dsidev); 2187 dss_dsi_disable_pads(dsi->module_id, dsi_get_lane_mask(dsidev)); 2188 } 2189 2190 static void dsi_config_tx_fifo(struct platform_device *dsidev, 2191 enum fifo_size size1, enum fifo_size size2, 2192 enum fifo_size size3, enum fifo_size size4) 2193 { 2194 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 2195 u32 r = 0; 2196 int add = 0; 2197 int i; 2198 2199 dsi->vc[0].tx_fifo_size = size1; 2200 dsi->vc[1].tx_fifo_size = size2; 2201 dsi->vc[2].tx_fifo_size = size3; 2202 dsi->vc[3].tx_fifo_size = size4; 2203 2204 for (i = 0; i < 4; i++) { 2205 u8 v; 2206 int size = dsi->vc[i].tx_fifo_size; 2207 2208 if (add + size > 4) { 2209 DSSERR("Illegal FIFO configuration\n"); 2210 BUG(); 2211 return; 2212 } 2213 2214 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4); 2215 r |= v << (8 * i); 2216 /*DSSDBG("TX FIFO vc %d: size %d, add %d\n", i, size, add); */ 2217 add += size; 2218 } 2219 2220 dsi_write_reg(dsidev, DSI_TX_FIFO_VC_SIZE, r); 2221 } 2222 2223 static void dsi_config_rx_fifo(struct platform_device *dsidev, 2224 enum fifo_size size1, enum fifo_size size2, 2225 enum fifo_size size3, enum fifo_size size4) 2226 { 2227 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 2228 u32 r = 0; 2229 int add = 0; 2230 int i; 2231 2232 dsi->vc[0].rx_fifo_size = size1; 2233 dsi->vc[1].rx_fifo_size = size2; 2234 dsi->vc[2].rx_fifo_size = size3; 2235 dsi->vc[3].rx_fifo_size = size4; 2236 2237 for (i = 0; i < 4; i++) { 2238 u8 v; 2239 int size = dsi->vc[i].rx_fifo_size; 2240 2241 if (add + size > 4) { 2242 DSSERR("Illegal FIFO configuration\n"); 2243 BUG(); 2244 return; 2245 } 2246 2247 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4); 2248 r |= v << (8 * i); 2249 /*DSSDBG("RX FIFO vc %d: size %d, add %d\n", i, size, add); */ 2250 add += size; 2251 } 2252 2253 dsi_write_reg(dsidev, DSI_RX_FIFO_VC_SIZE, r); 2254 } 2255 2256 static int dsi_force_tx_stop_mode_io(struct platform_device *dsidev) 2257 { 2258 u32 r; 2259 2260 r = dsi_read_reg(dsidev, DSI_TIMING1); 2261 r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */ 2262 dsi_write_reg(dsidev, DSI_TIMING1, r); 2263 2264 if (wait_for_bit_change(dsidev, DSI_TIMING1, 15, 0) != 0) { 2265 DSSERR("TX_STOP bit not going down\n"); 2266 return -EIO; 2267 } 2268 2269 return 0; 2270 } 2271 2272 static bool dsi_vc_is_enabled(struct platform_device *dsidev, int channel) 2273 { 2274 return REG_GET(dsidev, DSI_VC_CTRL(channel), 0, 0); 2275 } 2276 2277 static void dsi_packet_sent_handler_vp(void *data, u32 mask) 2278 { 2279 struct dsi_packet_sent_handler_data *vp_data = 2280 (struct dsi_packet_sent_handler_data *) data; 2281 struct dsi_data *dsi = dsi_get_dsidrv_data(vp_data->dsidev); 2282 const int channel = dsi->update_channel; 2283 u8 bit = dsi->te_enabled ? 30 : 31; 2284 2285 if (REG_GET(vp_data->dsidev, DSI_VC_TE(channel), bit, bit) == 0) 2286 complete(vp_data->completion); 2287 } 2288 2289 static int dsi_sync_vc_vp(struct platform_device *dsidev, int channel) 2290 { 2291 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 2292 DECLARE_COMPLETION_ONSTACK(completion); 2293 struct dsi_packet_sent_handler_data vp_data = { 2294 .dsidev = dsidev, 2295 .completion = &completion 2296 }; 2297 int r = 0; 2298 u8 bit; 2299 2300 bit = dsi->te_enabled ? 30 : 31; 2301 2302 r = dsi_register_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp, 2303 &vp_data, DSI_VC_IRQ_PACKET_SENT); 2304 if (r) 2305 goto err0; 2306 2307 /* Wait for completion only if TE_EN/TE_START is still set */ 2308 if (REG_GET(dsidev, DSI_VC_TE(channel), bit, bit)) { 2309 if (wait_for_completion_timeout(&completion, 2310 msecs_to_jiffies(10)) == 0) { 2311 DSSERR("Failed to complete previous frame transfer\n"); 2312 r = -EIO; 2313 goto err1; 2314 } 2315 } 2316 2317 dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp, 2318 &vp_data, DSI_VC_IRQ_PACKET_SENT); 2319 2320 return 0; 2321 err1: 2322 dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp, 2323 &vp_data, DSI_VC_IRQ_PACKET_SENT); 2324 err0: 2325 return r; 2326 } 2327 2328 static void dsi_packet_sent_handler_l4(void *data, u32 mask) 2329 { 2330 struct dsi_packet_sent_handler_data *l4_data = 2331 (struct dsi_packet_sent_handler_data *) data; 2332 struct dsi_data *dsi = dsi_get_dsidrv_data(l4_data->dsidev); 2333 const int channel = dsi->update_channel; 2334 2335 if (REG_GET(l4_data->dsidev, DSI_VC_CTRL(channel), 5, 5) == 0) 2336 complete(l4_data->completion); 2337 } 2338 2339 static int dsi_sync_vc_l4(struct platform_device *dsidev, int channel) 2340 { 2341 DECLARE_COMPLETION_ONSTACK(completion); 2342 struct dsi_packet_sent_handler_data l4_data = { 2343 .dsidev = dsidev, 2344 .completion = &completion 2345 }; 2346 int r = 0; 2347 2348 r = dsi_register_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4, 2349 &l4_data, DSI_VC_IRQ_PACKET_SENT); 2350 if (r) 2351 goto err0; 2352 2353 /* Wait for completion only if TX_FIFO_NOT_EMPTY is still set */ 2354 if (REG_GET(dsidev, DSI_VC_CTRL(channel), 5, 5)) { 2355 if (wait_for_completion_timeout(&completion, 2356 msecs_to_jiffies(10)) == 0) { 2357 DSSERR("Failed to complete previous l4 transfer\n"); 2358 r = -EIO; 2359 goto err1; 2360 } 2361 } 2362 2363 dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4, 2364 &l4_data, DSI_VC_IRQ_PACKET_SENT); 2365 2366 return 0; 2367 err1: 2368 dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4, 2369 &l4_data, DSI_VC_IRQ_PACKET_SENT); 2370 err0: 2371 return r; 2372 } 2373 2374 static int dsi_sync_vc(struct platform_device *dsidev, int channel) 2375 { 2376 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 2377 2378 WARN_ON(!dsi_bus_is_locked(dsidev)); 2379 2380 WARN_ON(in_interrupt()); 2381 2382 if (!dsi_vc_is_enabled(dsidev, channel)) 2383 return 0; 2384 2385 switch (dsi->vc[channel].source) { 2386 case DSI_VC_SOURCE_VP: 2387 return dsi_sync_vc_vp(dsidev, channel); 2388 case DSI_VC_SOURCE_L4: 2389 return dsi_sync_vc_l4(dsidev, channel); 2390 default: 2391 BUG(); 2392 return -EINVAL; 2393 } 2394 } 2395 2396 static int dsi_vc_enable(struct platform_device *dsidev, int channel, 2397 bool enable) 2398 { 2399 DSSDBG("dsi_vc_enable channel %d, enable %d\n", 2400 channel, enable); 2401 2402 enable = enable ? 1 : 0; 2403 2404 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 0, 0); 2405 2406 if (wait_for_bit_change(dsidev, DSI_VC_CTRL(channel), 2407 0, enable) != enable) { 2408 DSSERR("Failed to set dsi_vc_enable to %d\n", enable); 2409 return -EIO; 2410 } 2411 2412 return 0; 2413 } 2414 2415 static void dsi_vc_initial_config(struct platform_device *dsidev, int channel) 2416 { 2417 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 2418 u32 r; 2419 2420 DSSDBG("Initial config of virtual channel %d", channel); 2421 2422 r = dsi_read_reg(dsidev, DSI_VC_CTRL(channel)); 2423 2424 if (FLD_GET(r, 15, 15)) /* VC_BUSY */ 2425 DSSERR("VC(%d) busy when trying to configure it!\n", 2426 channel); 2427 2428 r = FLD_MOD(r, 0, 1, 1); /* SOURCE, 0 = L4 */ 2429 r = FLD_MOD(r, 0, 2, 2); /* BTA_SHORT_EN */ 2430 r = FLD_MOD(r, 0, 3, 3); /* BTA_LONG_EN */ 2431 r = FLD_MOD(r, 0, 4, 4); /* MODE, 0 = command */ 2432 r = FLD_MOD(r, 1, 7, 7); /* CS_TX_EN */ 2433 r = FLD_MOD(r, 1, 8, 8); /* ECC_TX_EN */ 2434 r = FLD_MOD(r, 0, 9, 9); /* MODE_SPEED, high speed on/off */ 2435 if (dss_has_feature(FEAT_DSI_VC_OCP_WIDTH)) 2436 r = FLD_MOD(r, 3, 11, 10); /* OCP_WIDTH = 32 bit */ 2437 2438 r = FLD_MOD(r, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */ 2439 r = FLD_MOD(r, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */ 2440 2441 dsi_write_reg(dsidev, DSI_VC_CTRL(channel), r); 2442 2443 dsi->vc[channel].source = DSI_VC_SOURCE_L4; 2444 } 2445 2446 static int dsi_vc_config_source(struct platform_device *dsidev, int channel, 2447 enum dsi_vc_source source) 2448 { 2449 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 2450 2451 if (dsi->vc[channel].source == source) 2452 return 0; 2453 2454 DSSDBG("Source config of virtual channel %d", channel); 2455 2456 dsi_sync_vc(dsidev, channel); 2457 2458 dsi_vc_enable(dsidev, channel, 0); 2459 2460 /* VC_BUSY */ 2461 if (wait_for_bit_change(dsidev, DSI_VC_CTRL(channel), 15, 0) != 0) { 2462 DSSERR("vc(%d) busy when trying to config for VP\n", channel); 2463 return -EIO; 2464 } 2465 2466 /* SOURCE, 0 = L4, 1 = video port */ 2467 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), source, 1, 1); 2468 2469 /* DCS_CMD_ENABLE */ 2470 if (dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC)) { 2471 bool enable = source == DSI_VC_SOURCE_VP; 2472 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 30, 30); 2473 } 2474 2475 dsi_vc_enable(dsidev, channel, 1); 2476 2477 dsi->vc[channel].source = source; 2478 2479 return 0; 2480 } 2481 2482 static void dsi_vc_enable_hs(struct omap_dss_device *dssdev, int channel, 2483 bool enable) 2484 { 2485 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 2486 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 2487 2488 DSSDBG("dsi_vc_enable_hs(%d, %d)\n", channel, enable); 2489 2490 WARN_ON(!dsi_bus_is_locked(dsidev)); 2491 2492 dsi_vc_enable(dsidev, channel, 0); 2493 dsi_if_enable(dsidev, 0); 2494 2495 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 9, 9); 2496 2497 dsi_vc_enable(dsidev, channel, 1); 2498 dsi_if_enable(dsidev, 1); 2499 2500 dsi_force_tx_stop_mode_io(dsidev); 2501 2502 /* start the DDR clock by sending a NULL packet */ 2503 if (dsi->vm_timings.ddr_clk_always_on && enable) 2504 dsi_vc_send_null(dssdev, channel); 2505 } 2506 2507 static void dsi_vc_flush_long_data(struct platform_device *dsidev, int channel) 2508 { 2509 while (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) { 2510 u32 val; 2511 val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel)); 2512 DSSDBG("\t\tb1 %#02x b2 %#02x b3 %#02x b4 %#02x\n", 2513 (val >> 0) & 0xff, 2514 (val >> 8) & 0xff, 2515 (val >> 16) & 0xff, 2516 (val >> 24) & 0xff); 2517 } 2518 } 2519 2520 static void dsi_show_rx_ack_with_err(u16 err) 2521 { 2522 DSSERR("\tACK with ERROR (%#x):\n", err); 2523 if (err & (1 << 0)) 2524 DSSERR("\t\tSoT Error\n"); 2525 if (err & (1 << 1)) 2526 DSSERR("\t\tSoT Sync Error\n"); 2527 if (err & (1 << 2)) 2528 DSSERR("\t\tEoT Sync Error\n"); 2529 if (err & (1 << 3)) 2530 DSSERR("\t\tEscape Mode Entry Command Error\n"); 2531 if (err & (1 << 4)) 2532 DSSERR("\t\tLP Transmit Sync Error\n"); 2533 if (err & (1 << 5)) 2534 DSSERR("\t\tHS Receive Timeout Error\n"); 2535 if (err & (1 << 6)) 2536 DSSERR("\t\tFalse Control Error\n"); 2537 if (err & (1 << 7)) 2538 DSSERR("\t\t(reserved7)\n"); 2539 if (err & (1 << 8)) 2540 DSSERR("\t\tECC Error, single-bit (corrected)\n"); 2541 if (err & (1 << 9)) 2542 DSSERR("\t\tECC Error, multi-bit (not corrected)\n"); 2543 if (err & (1 << 10)) 2544 DSSERR("\t\tChecksum Error\n"); 2545 if (err & (1 << 11)) 2546 DSSERR("\t\tData type not recognized\n"); 2547 if (err & (1 << 12)) 2548 DSSERR("\t\tInvalid VC ID\n"); 2549 if (err & (1 << 13)) 2550 DSSERR("\t\tInvalid Transmission Length\n"); 2551 if (err & (1 << 14)) 2552 DSSERR("\t\t(reserved14)\n"); 2553 if (err & (1 << 15)) 2554 DSSERR("\t\tDSI Protocol Violation\n"); 2555 } 2556 2557 static u16 dsi_vc_flush_receive_data(struct platform_device *dsidev, 2558 int channel) 2559 { 2560 /* RX_FIFO_NOT_EMPTY */ 2561 while (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) { 2562 u32 val; 2563 u8 dt; 2564 val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel)); 2565 DSSERR("\trawval %#08x\n", val); 2566 dt = FLD_GET(val, 5, 0); 2567 if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) { 2568 u16 err = FLD_GET(val, 23, 8); 2569 dsi_show_rx_ack_with_err(err); 2570 } else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE) { 2571 DSSERR("\tDCS short response, 1 byte: %#x\n", 2572 FLD_GET(val, 23, 8)); 2573 } else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE) { 2574 DSSERR("\tDCS short response, 2 byte: %#x\n", 2575 FLD_GET(val, 23, 8)); 2576 } else if (dt == MIPI_DSI_RX_DCS_LONG_READ_RESPONSE) { 2577 DSSERR("\tDCS long response, len %d\n", 2578 FLD_GET(val, 23, 8)); 2579 dsi_vc_flush_long_data(dsidev, channel); 2580 } else { 2581 DSSERR("\tunknown datatype 0x%02x\n", dt); 2582 } 2583 } 2584 return 0; 2585 } 2586 2587 static int dsi_vc_send_bta(struct platform_device *dsidev, int channel) 2588 { 2589 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 2590 2591 if (dsi->debug_write || dsi->debug_read) 2592 DSSDBG("dsi_vc_send_bta %d\n", channel); 2593 2594 WARN_ON(!dsi_bus_is_locked(dsidev)); 2595 2596 /* RX_FIFO_NOT_EMPTY */ 2597 if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) { 2598 DSSERR("rx fifo not empty when sending BTA, dumping data:\n"); 2599 dsi_vc_flush_receive_data(dsidev, channel); 2600 } 2601 2602 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 1, 6, 6); /* BTA_EN */ 2603 2604 /* flush posted write */ 2605 dsi_read_reg(dsidev, DSI_VC_CTRL(channel)); 2606 2607 return 0; 2608 } 2609 2610 static int dsi_vc_send_bta_sync(struct omap_dss_device *dssdev, int channel) 2611 { 2612 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 2613 DECLARE_COMPLETION_ONSTACK(completion); 2614 int r = 0; 2615 u32 err; 2616 2617 r = dsi_register_isr_vc(dsidev, channel, dsi_completion_handler, 2618 &completion, DSI_VC_IRQ_BTA); 2619 if (r) 2620 goto err0; 2621 2622 r = dsi_register_isr(dsidev, dsi_completion_handler, &completion, 2623 DSI_IRQ_ERROR_MASK); 2624 if (r) 2625 goto err1; 2626 2627 r = dsi_vc_send_bta(dsidev, channel); 2628 if (r) 2629 goto err2; 2630 2631 if (wait_for_completion_timeout(&completion, 2632 msecs_to_jiffies(500)) == 0) { 2633 DSSERR("Failed to receive BTA\n"); 2634 r = -EIO; 2635 goto err2; 2636 } 2637 2638 err = dsi_get_errors(dsidev); 2639 if (err) { 2640 DSSERR("Error while sending BTA: %x\n", err); 2641 r = -EIO; 2642 goto err2; 2643 } 2644 err2: 2645 dsi_unregister_isr(dsidev, dsi_completion_handler, &completion, 2646 DSI_IRQ_ERROR_MASK); 2647 err1: 2648 dsi_unregister_isr_vc(dsidev, channel, dsi_completion_handler, 2649 &completion, DSI_VC_IRQ_BTA); 2650 err0: 2651 return r; 2652 } 2653 2654 static inline void dsi_vc_write_long_header(struct platform_device *dsidev, 2655 int channel, u8 data_type, u16 len, u8 ecc) 2656 { 2657 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 2658 u32 val; 2659 u8 data_id; 2660 2661 WARN_ON(!dsi_bus_is_locked(dsidev)); 2662 2663 data_id = data_type | dsi->vc[channel].vc_id << 6; 2664 2665 val = FLD_VAL(data_id, 7, 0) | FLD_VAL(len, 23, 8) | 2666 FLD_VAL(ecc, 31, 24); 2667 2668 dsi_write_reg(dsidev, DSI_VC_LONG_PACKET_HEADER(channel), val); 2669 } 2670 2671 static inline void dsi_vc_write_long_payload(struct platform_device *dsidev, 2672 int channel, u8 b1, u8 b2, u8 b3, u8 b4) 2673 { 2674 u32 val; 2675 2676 val = b4 << 24 | b3 << 16 | b2 << 8 | b1 << 0; 2677 2678 /* DSSDBG("\twriting %02x, %02x, %02x, %02x (%#010x)\n", 2679 b1, b2, b3, b4, val); */ 2680 2681 dsi_write_reg(dsidev, DSI_VC_LONG_PACKET_PAYLOAD(channel), val); 2682 } 2683 2684 static int dsi_vc_send_long(struct platform_device *dsidev, int channel, 2685 u8 data_type, u8 *data, u16 len, u8 ecc) 2686 { 2687 /*u32 val; */ 2688 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 2689 int i; 2690 u8 *p; 2691 int r = 0; 2692 u8 b1, b2, b3, b4; 2693 2694 if (dsi->debug_write) 2695 DSSDBG("dsi_vc_send_long, %d bytes\n", len); 2696 2697 /* len + header */ 2698 if (dsi->vc[channel].tx_fifo_size * 32 * 4 < len + 4) { 2699 DSSERR("unable to send long packet: packet too long.\n"); 2700 return -EINVAL; 2701 } 2702 2703 dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_L4); 2704 2705 dsi_vc_write_long_header(dsidev, channel, data_type, len, ecc); 2706 2707 p = data; 2708 for (i = 0; i < len >> 2; i++) { 2709 if (dsi->debug_write) 2710 DSSDBG("\tsending full packet %d\n", i); 2711 2712 b1 = *p++; 2713 b2 = *p++; 2714 b3 = *p++; 2715 b4 = *p++; 2716 2717 dsi_vc_write_long_payload(dsidev, channel, b1, b2, b3, b4); 2718 } 2719 2720 i = len % 4; 2721 if (i) { 2722 b1 = 0; b2 = 0; b3 = 0; 2723 2724 if (dsi->debug_write) 2725 DSSDBG("\tsending remainder bytes %d\n", i); 2726 2727 switch (i) { 2728 case 3: 2729 b1 = *p++; 2730 b2 = *p++; 2731 b3 = *p++; 2732 break; 2733 case 2: 2734 b1 = *p++; 2735 b2 = *p++; 2736 break; 2737 case 1: 2738 b1 = *p++; 2739 break; 2740 } 2741 2742 dsi_vc_write_long_payload(dsidev, channel, b1, b2, b3, 0); 2743 } 2744 2745 return r; 2746 } 2747 2748 static int dsi_vc_send_short(struct platform_device *dsidev, int channel, 2749 u8 data_type, u16 data, u8 ecc) 2750 { 2751 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 2752 u32 r; 2753 u8 data_id; 2754 2755 WARN_ON(!dsi_bus_is_locked(dsidev)); 2756 2757 if (dsi->debug_write) 2758 DSSDBG("dsi_vc_send_short(ch%d, dt %#x, b1 %#x, b2 %#x)\n", 2759 channel, 2760 data_type, data & 0xff, (data >> 8) & 0xff); 2761 2762 dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_L4); 2763 2764 if (FLD_GET(dsi_read_reg(dsidev, DSI_VC_CTRL(channel)), 16, 16)) { 2765 DSSERR("ERROR FIFO FULL, aborting transfer\n"); 2766 return -EINVAL; 2767 } 2768 2769 data_id = data_type | dsi->vc[channel].vc_id << 6; 2770 2771 r = (data_id << 0) | (data << 8) | (ecc << 24); 2772 2773 dsi_write_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel), r); 2774 2775 return 0; 2776 } 2777 2778 static int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel) 2779 { 2780 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 2781 2782 return dsi_vc_send_long(dsidev, channel, MIPI_DSI_NULL_PACKET, NULL, 2783 0, 0); 2784 } 2785 2786 static int dsi_vc_write_nosync_common(struct platform_device *dsidev, 2787 int channel, u8 *data, int len, enum dss_dsi_content_type type) 2788 { 2789 int r; 2790 2791 if (len == 0) { 2792 BUG_ON(type == DSS_DSI_CONTENT_DCS); 2793 r = dsi_vc_send_short(dsidev, channel, 2794 MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM, 0, 0); 2795 } else if (len == 1) { 2796 r = dsi_vc_send_short(dsidev, channel, 2797 type == DSS_DSI_CONTENT_GENERIC ? 2798 MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM : 2799 MIPI_DSI_DCS_SHORT_WRITE, data[0], 0); 2800 } else if (len == 2) { 2801 r = dsi_vc_send_short(dsidev, channel, 2802 type == DSS_DSI_CONTENT_GENERIC ? 2803 MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM : 2804 MIPI_DSI_DCS_SHORT_WRITE_PARAM, 2805 data[0] | (data[1] << 8), 0); 2806 } else { 2807 r = dsi_vc_send_long(dsidev, channel, 2808 type == DSS_DSI_CONTENT_GENERIC ? 2809 MIPI_DSI_GENERIC_LONG_WRITE : 2810 MIPI_DSI_DCS_LONG_WRITE, data, len, 0); 2811 } 2812 2813 return r; 2814 } 2815 2816 static int dsi_vc_dcs_write_nosync(struct omap_dss_device *dssdev, int channel, 2817 u8 *data, int len) 2818 { 2819 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 2820 2821 return dsi_vc_write_nosync_common(dsidev, channel, data, len, 2822 DSS_DSI_CONTENT_DCS); 2823 } 2824 2825 static int dsi_vc_generic_write_nosync(struct omap_dss_device *dssdev, int channel, 2826 u8 *data, int len) 2827 { 2828 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 2829 2830 return dsi_vc_write_nosync_common(dsidev, channel, data, len, 2831 DSS_DSI_CONTENT_GENERIC); 2832 } 2833 2834 static int dsi_vc_write_common(struct omap_dss_device *dssdev, int channel, 2835 u8 *data, int len, enum dss_dsi_content_type type) 2836 { 2837 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 2838 int r; 2839 2840 r = dsi_vc_write_nosync_common(dsidev, channel, data, len, type); 2841 if (r) 2842 goto err; 2843 2844 r = dsi_vc_send_bta_sync(dssdev, channel); 2845 if (r) 2846 goto err; 2847 2848 /* RX_FIFO_NOT_EMPTY */ 2849 if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) { 2850 DSSERR("rx fifo not empty after write, dumping data:\n"); 2851 dsi_vc_flush_receive_data(dsidev, channel); 2852 r = -EIO; 2853 goto err; 2854 } 2855 2856 return 0; 2857 err: 2858 DSSERR("dsi_vc_write_common(ch %d, cmd 0x%02x, len %d) failed\n", 2859 channel, data[0], len); 2860 return r; 2861 } 2862 2863 static int dsi_vc_dcs_write(struct omap_dss_device *dssdev, int channel, u8 *data, 2864 int len) 2865 { 2866 return dsi_vc_write_common(dssdev, channel, data, len, 2867 DSS_DSI_CONTENT_DCS); 2868 } 2869 2870 static int dsi_vc_generic_write(struct omap_dss_device *dssdev, int channel, u8 *data, 2871 int len) 2872 { 2873 return dsi_vc_write_common(dssdev, channel, data, len, 2874 DSS_DSI_CONTENT_GENERIC); 2875 } 2876 2877 static int dsi_vc_dcs_send_read_request(struct platform_device *dsidev, 2878 int channel, u8 dcs_cmd) 2879 { 2880 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 2881 int r; 2882 2883 if (dsi->debug_read) 2884 DSSDBG("dsi_vc_dcs_send_read_request(ch%d, dcs_cmd %x)\n", 2885 channel, dcs_cmd); 2886 2887 r = dsi_vc_send_short(dsidev, channel, MIPI_DSI_DCS_READ, dcs_cmd, 0); 2888 if (r) { 2889 DSSERR("dsi_vc_dcs_send_read_request(ch %d, cmd 0x%02x)" 2890 " failed\n", channel, dcs_cmd); 2891 return r; 2892 } 2893 2894 return 0; 2895 } 2896 2897 static int dsi_vc_generic_send_read_request(struct platform_device *dsidev, 2898 int channel, u8 *reqdata, int reqlen) 2899 { 2900 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 2901 u16 data; 2902 u8 data_type; 2903 int r; 2904 2905 if (dsi->debug_read) 2906 DSSDBG("dsi_vc_generic_send_read_request(ch %d, reqlen %d)\n", 2907 channel, reqlen); 2908 2909 if (reqlen == 0) { 2910 data_type = MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM; 2911 data = 0; 2912 } else if (reqlen == 1) { 2913 data_type = MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM; 2914 data = reqdata[0]; 2915 } else if (reqlen == 2) { 2916 data_type = MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM; 2917 data = reqdata[0] | (reqdata[1] << 8); 2918 } else { 2919 BUG(); 2920 return -EINVAL; 2921 } 2922 2923 r = dsi_vc_send_short(dsidev, channel, data_type, data, 0); 2924 if (r) { 2925 DSSERR("dsi_vc_generic_send_read_request(ch %d, reqlen %d)" 2926 " failed\n", channel, reqlen); 2927 return r; 2928 } 2929 2930 return 0; 2931 } 2932 2933 static int dsi_vc_read_rx_fifo(struct platform_device *dsidev, int channel, 2934 u8 *buf, int buflen, enum dss_dsi_content_type type) 2935 { 2936 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 2937 u32 val; 2938 u8 dt; 2939 int r; 2940 2941 /* RX_FIFO_NOT_EMPTY */ 2942 if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20) == 0) { 2943 DSSERR("RX fifo empty when trying to read.\n"); 2944 r = -EIO; 2945 goto err; 2946 } 2947 2948 val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel)); 2949 if (dsi->debug_read) 2950 DSSDBG("\theader: %08x\n", val); 2951 dt = FLD_GET(val, 5, 0); 2952 if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) { 2953 u16 err = FLD_GET(val, 23, 8); 2954 dsi_show_rx_ack_with_err(err); 2955 r = -EIO; 2956 goto err; 2957 2958 } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ? 2959 MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE : 2960 MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE)) { 2961 u8 data = FLD_GET(val, 15, 8); 2962 if (dsi->debug_read) 2963 DSSDBG("\t%s short response, 1 byte: %02x\n", 2964 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" : 2965 "DCS", data); 2966 2967 if (buflen < 1) { 2968 r = -EIO; 2969 goto err; 2970 } 2971 2972 buf[0] = data; 2973 2974 return 1; 2975 } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ? 2976 MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE : 2977 MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE)) { 2978 u16 data = FLD_GET(val, 23, 8); 2979 if (dsi->debug_read) 2980 DSSDBG("\t%s short response, 2 byte: %04x\n", 2981 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" : 2982 "DCS", data); 2983 2984 if (buflen < 2) { 2985 r = -EIO; 2986 goto err; 2987 } 2988 2989 buf[0] = data & 0xff; 2990 buf[1] = (data >> 8) & 0xff; 2991 2992 return 2; 2993 } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ? 2994 MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE : 2995 MIPI_DSI_RX_DCS_LONG_READ_RESPONSE)) { 2996 int w; 2997 int len = FLD_GET(val, 23, 8); 2998 if (dsi->debug_read) 2999 DSSDBG("\t%s long response, len %d\n", 3000 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" : 3001 "DCS", len); 3002 3003 if (len > buflen) { 3004 r = -EIO; 3005 goto err; 3006 } 3007 3008 /* two byte checksum ends the packet, not included in len */ 3009 for (w = 0; w < len + 2;) { 3010 int b; 3011 val = dsi_read_reg(dsidev, 3012 DSI_VC_SHORT_PACKET_HEADER(channel)); 3013 if (dsi->debug_read) 3014 DSSDBG("\t\t%02x %02x %02x %02x\n", 3015 (val >> 0) & 0xff, 3016 (val >> 8) & 0xff, 3017 (val >> 16) & 0xff, 3018 (val >> 24) & 0xff); 3019 3020 for (b = 0; b < 4; ++b) { 3021 if (w < len) 3022 buf[w] = (val >> (b * 8)) & 0xff; 3023 /* we discard the 2 byte checksum */ 3024 ++w; 3025 } 3026 } 3027 3028 return len; 3029 } else { 3030 DSSERR("\tunknown datatype 0x%02x\n", dt); 3031 r = -EIO; 3032 goto err; 3033 } 3034 3035 err: 3036 DSSERR("dsi_vc_read_rx_fifo(ch %d type %s) failed\n", channel, 3037 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" : "DCS"); 3038 3039 return r; 3040 } 3041 3042 static int dsi_vc_dcs_read(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd, 3043 u8 *buf, int buflen) 3044 { 3045 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 3046 int r; 3047 3048 r = dsi_vc_dcs_send_read_request(dsidev, channel, dcs_cmd); 3049 if (r) 3050 goto err; 3051 3052 r = dsi_vc_send_bta_sync(dssdev, channel); 3053 if (r) 3054 goto err; 3055 3056 r = dsi_vc_read_rx_fifo(dsidev, channel, buf, buflen, 3057 DSS_DSI_CONTENT_DCS); 3058 if (r < 0) 3059 goto err; 3060 3061 if (r != buflen) { 3062 r = -EIO; 3063 goto err; 3064 } 3065 3066 return 0; 3067 err: 3068 DSSERR("dsi_vc_dcs_read(ch %d, cmd 0x%02x) failed\n", channel, dcs_cmd); 3069 return r; 3070 } 3071 3072 static int dsi_vc_generic_read(struct omap_dss_device *dssdev, int channel, 3073 u8 *reqdata, int reqlen, u8 *buf, int buflen) 3074 { 3075 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 3076 int r; 3077 3078 r = dsi_vc_generic_send_read_request(dsidev, channel, reqdata, reqlen); 3079 if (r) 3080 return r; 3081 3082 r = dsi_vc_send_bta_sync(dssdev, channel); 3083 if (r) 3084 return r; 3085 3086 r = dsi_vc_read_rx_fifo(dsidev, channel, buf, buflen, 3087 DSS_DSI_CONTENT_GENERIC); 3088 if (r < 0) 3089 return r; 3090 3091 if (r != buflen) { 3092 r = -EIO; 3093 return r; 3094 } 3095 3096 return 0; 3097 } 3098 3099 static int dsi_vc_set_max_rx_packet_size(struct omap_dss_device *dssdev, int channel, 3100 u16 len) 3101 { 3102 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 3103 3104 return dsi_vc_send_short(dsidev, channel, 3105 MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE, len, 0); 3106 } 3107 3108 static int dsi_enter_ulps(struct platform_device *dsidev) 3109 { 3110 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 3111 DECLARE_COMPLETION_ONSTACK(completion); 3112 int r, i; 3113 unsigned mask; 3114 3115 DSSDBG("Entering ULPS"); 3116 3117 WARN_ON(!dsi_bus_is_locked(dsidev)); 3118 3119 WARN_ON(dsi->ulps_enabled); 3120 3121 if (dsi->ulps_enabled) 3122 return 0; 3123 3124 /* DDR_CLK_ALWAYS_ON */ 3125 if (REG_GET(dsidev, DSI_CLK_CTRL, 13, 13)) { 3126 dsi_if_enable(dsidev, 0); 3127 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 13, 13); 3128 dsi_if_enable(dsidev, 1); 3129 } 3130 3131 dsi_sync_vc(dsidev, 0); 3132 dsi_sync_vc(dsidev, 1); 3133 dsi_sync_vc(dsidev, 2); 3134 dsi_sync_vc(dsidev, 3); 3135 3136 dsi_force_tx_stop_mode_io(dsidev); 3137 3138 dsi_vc_enable(dsidev, 0, false); 3139 dsi_vc_enable(dsidev, 1, false); 3140 dsi_vc_enable(dsidev, 2, false); 3141 dsi_vc_enable(dsidev, 3, false); 3142 3143 if (REG_GET(dsidev, DSI_COMPLEXIO_CFG2, 16, 16)) { /* HS_BUSY */ 3144 DSSERR("HS busy when enabling ULPS\n"); 3145 return -EIO; 3146 } 3147 3148 if (REG_GET(dsidev, DSI_COMPLEXIO_CFG2, 17, 17)) { /* LP_BUSY */ 3149 DSSERR("LP busy when enabling ULPS\n"); 3150 return -EIO; 3151 } 3152 3153 r = dsi_register_isr_cio(dsidev, dsi_completion_handler, &completion, 3154 DSI_CIO_IRQ_ULPSACTIVENOT_ALL0); 3155 if (r) 3156 return r; 3157 3158 mask = 0; 3159 3160 for (i = 0; i < dsi->num_lanes_supported; ++i) { 3161 if (dsi->lanes[i].function == DSI_LANE_UNUSED) 3162 continue; 3163 mask |= 1 << i; 3164 } 3165 /* Assert TxRequestEsc for data lanes and TxUlpsClk for clk lane */ 3166 /* LANEx_ULPS_SIG2 */ 3167 REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG2, mask, 9, 5); 3168 3169 /* flush posted write and wait for SCP interface to finish the write */ 3170 dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG2); 3171 3172 if (wait_for_completion_timeout(&completion, 3173 msecs_to_jiffies(1000)) == 0) { 3174 DSSERR("ULPS enable timeout\n"); 3175 r = -EIO; 3176 goto err; 3177 } 3178 3179 dsi_unregister_isr_cio(dsidev, dsi_completion_handler, &completion, 3180 DSI_CIO_IRQ_ULPSACTIVENOT_ALL0); 3181 3182 /* Reset LANEx_ULPS_SIG2 */ 3183 REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG2, 0, 9, 5); 3184 3185 /* flush posted write and wait for SCP interface to finish the write */ 3186 dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG2); 3187 3188 dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_ULPS); 3189 3190 dsi_if_enable(dsidev, false); 3191 3192 dsi->ulps_enabled = true; 3193 3194 return 0; 3195 3196 err: 3197 dsi_unregister_isr_cio(dsidev, dsi_completion_handler, &completion, 3198 DSI_CIO_IRQ_ULPSACTIVENOT_ALL0); 3199 return r; 3200 } 3201 3202 static void dsi_set_lp_rx_timeout(struct platform_device *dsidev, 3203 unsigned ticks, bool x4, bool x16) 3204 { 3205 unsigned long fck; 3206 unsigned long total_ticks; 3207 u32 r; 3208 3209 BUG_ON(ticks > 0x1fff); 3210 3211 /* ticks in DSI_FCK */ 3212 fck = dsi_fclk_rate(dsidev); 3213 3214 r = dsi_read_reg(dsidev, DSI_TIMING2); 3215 r = FLD_MOD(r, 1, 15, 15); /* LP_RX_TO */ 3216 r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* LP_RX_TO_X16 */ 3217 r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* LP_RX_TO_X4 */ 3218 r = FLD_MOD(r, ticks, 12, 0); /* LP_RX_COUNTER */ 3219 dsi_write_reg(dsidev, DSI_TIMING2, r); 3220 3221 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1); 3222 3223 DSSDBG("LP_RX_TO %lu ticks (%#x%s%s) = %lu ns\n", 3224 total_ticks, 3225 ticks, x4 ? " x4" : "", x16 ? " x16" : "", 3226 (total_ticks * 1000) / (fck / 1000 / 1000)); 3227 } 3228 3229 static void dsi_set_ta_timeout(struct platform_device *dsidev, unsigned ticks, 3230 bool x8, bool x16) 3231 { 3232 unsigned long fck; 3233 unsigned long total_ticks; 3234 u32 r; 3235 3236 BUG_ON(ticks > 0x1fff); 3237 3238 /* ticks in DSI_FCK */ 3239 fck = dsi_fclk_rate(dsidev); 3240 3241 r = dsi_read_reg(dsidev, DSI_TIMING1); 3242 r = FLD_MOD(r, 1, 31, 31); /* TA_TO */ 3243 r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* TA_TO_X16 */ 3244 r = FLD_MOD(r, x8 ? 1 : 0, 29, 29); /* TA_TO_X8 */ 3245 r = FLD_MOD(r, ticks, 28, 16); /* TA_TO_COUNTER */ 3246 dsi_write_reg(dsidev, DSI_TIMING1, r); 3247 3248 total_ticks = ticks * (x16 ? 16 : 1) * (x8 ? 8 : 1); 3249 3250 DSSDBG("TA_TO %lu ticks (%#x%s%s) = %lu ns\n", 3251 total_ticks, 3252 ticks, x8 ? " x8" : "", x16 ? " x16" : "", 3253 (total_ticks * 1000) / (fck / 1000 / 1000)); 3254 } 3255 3256 static void dsi_set_stop_state_counter(struct platform_device *dsidev, 3257 unsigned ticks, bool x4, bool x16) 3258 { 3259 unsigned long fck; 3260 unsigned long total_ticks; 3261 u32 r; 3262 3263 BUG_ON(ticks > 0x1fff); 3264 3265 /* ticks in DSI_FCK */ 3266 fck = dsi_fclk_rate(dsidev); 3267 3268 r = dsi_read_reg(dsidev, DSI_TIMING1); 3269 r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */ 3270 r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* STOP_STATE_X16_IO */ 3271 r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* STOP_STATE_X4_IO */ 3272 r = FLD_MOD(r, ticks, 12, 0); /* STOP_STATE_COUNTER_IO */ 3273 dsi_write_reg(dsidev, DSI_TIMING1, r); 3274 3275 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1); 3276 3277 DSSDBG("STOP_STATE_COUNTER %lu ticks (%#x%s%s) = %lu ns\n", 3278 total_ticks, 3279 ticks, x4 ? " x4" : "", x16 ? " x16" : "", 3280 (total_ticks * 1000) / (fck / 1000 / 1000)); 3281 } 3282 3283 static void dsi_set_hs_tx_timeout(struct platform_device *dsidev, 3284 unsigned ticks, bool x4, bool x16) 3285 { 3286 unsigned long fck; 3287 unsigned long total_ticks; 3288 u32 r; 3289 3290 BUG_ON(ticks > 0x1fff); 3291 3292 /* ticks in TxByteClkHS */ 3293 fck = dsi_get_txbyteclkhs(dsidev); 3294 3295 r = dsi_read_reg(dsidev, DSI_TIMING2); 3296 r = FLD_MOD(r, 1, 31, 31); /* HS_TX_TO */ 3297 r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* HS_TX_TO_X16 */ 3298 r = FLD_MOD(r, x4 ? 1 : 0, 29, 29); /* HS_TX_TO_X8 (4 really) */ 3299 r = FLD_MOD(r, ticks, 28, 16); /* HS_TX_TO_COUNTER */ 3300 dsi_write_reg(dsidev, DSI_TIMING2, r); 3301 3302 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1); 3303 3304 DSSDBG("HS_TX_TO %lu ticks (%#x%s%s) = %lu ns\n", 3305 total_ticks, 3306 ticks, x4 ? " x4" : "", x16 ? " x16" : "", 3307 (total_ticks * 1000) / (fck / 1000 / 1000)); 3308 } 3309 3310 static void dsi_config_vp_num_line_buffers(struct platform_device *dsidev) 3311 { 3312 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 3313 int num_line_buffers; 3314 3315 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) { 3316 int bpp = dsi_get_pixel_size(dsi->pix_fmt); 3317 struct omap_video_timings *timings = &dsi->timings; 3318 /* 3319 * Don't use line buffers if width is greater than the video 3320 * port's line buffer size 3321 */ 3322 if (dsi->line_buffer_size <= timings->x_res * bpp / 8) 3323 num_line_buffers = 0; 3324 else 3325 num_line_buffers = 2; 3326 } else { 3327 /* Use maximum number of line buffers in command mode */ 3328 num_line_buffers = 2; 3329 } 3330 3331 /* LINE_BUFFER */ 3332 REG_FLD_MOD(dsidev, DSI_CTRL, num_line_buffers, 13, 12); 3333 } 3334 3335 static void dsi_config_vp_sync_events(struct platform_device *dsidev) 3336 { 3337 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 3338 bool sync_end; 3339 u32 r; 3340 3341 if (dsi->vm_timings.trans_mode == OMAP_DSS_DSI_PULSE_MODE) 3342 sync_end = true; 3343 else 3344 sync_end = false; 3345 3346 r = dsi_read_reg(dsidev, DSI_CTRL); 3347 r = FLD_MOD(r, 1, 9, 9); /* VP_DE_POL */ 3348 r = FLD_MOD(r, 1, 10, 10); /* VP_HSYNC_POL */ 3349 r = FLD_MOD(r, 1, 11, 11); /* VP_VSYNC_POL */ 3350 r = FLD_MOD(r, 1, 15, 15); /* VP_VSYNC_START */ 3351 r = FLD_MOD(r, sync_end, 16, 16); /* VP_VSYNC_END */ 3352 r = FLD_MOD(r, 1, 17, 17); /* VP_HSYNC_START */ 3353 r = FLD_MOD(r, sync_end, 18, 18); /* VP_HSYNC_END */ 3354 dsi_write_reg(dsidev, DSI_CTRL, r); 3355 } 3356 3357 static void dsi_config_blanking_modes(struct platform_device *dsidev) 3358 { 3359 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 3360 int blanking_mode = dsi->vm_timings.blanking_mode; 3361 int hfp_blanking_mode = dsi->vm_timings.hfp_blanking_mode; 3362 int hbp_blanking_mode = dsi->vm_timings.hbp_blanking_mode; 3363 int hsa_blanking_mode = dsi->vm_timings.hsa_blanking_mode; 3364 u32 r; 3365 3366 /* 3367 * 0 = TX FIFO packets sent or LPS in corresponding blanking periods 3368 * 1 = Long blanking packets are sent in corresponding blanking periods 3369 */ 3370 r = dsi_read_reg(dsidev, DSI_CTRL); 3371 r = FLD_MOD(r, blanking_mode, 20, 20); /* BLANKING_MODE */ 3372 r = FLD_MOD(r, hfp_blanking_mode, 21, 21); /* HFP_BLANKING */ 3373 r = FLD_MOD(r, hbp_blanking_mode, 22, 22); /* HBP_BLANKING */ 3374 r = FLD_MOD(r, hsa_blanking_mode, 23, 23); /* HSA_BLANKING */ 3375 dsi_write_reg(dsidev, DSI_CTRL, r); 3376 } 3377 3378 /* 3379 * According to section 'HS Command Mode Interleaving' in OMAP TRM, Scenario 3 3380 * results in maximum transition time for data and clock lanes to enter and 3381 * exit HS mode. Hence, this is the scenario where the least amount of command 3382 * mode data can be interleaved. We program the minimum amount of TXBYTECLKHS 3383 * clock cycles that can be used to interleave command mode data in HS so that 3384 * all scenarios are satisfied. 3385 */ 3386 static int dsi_compute_interleave_hs(int blank, bool ddr_alwon, int enter_hs, 3387 int exit_hs, int exiths_clk, int ddr_pre, int ddr_post) 3388 { 3389 int transition; 3390 3391 /* 3392 * If DDR_CLK_ALWAYS_ON is set, we need to consider HS mode transition 3393 * time of data lanes only, if it isn't set, we need to consider HS 3394 * transition time of both data and clock lanes. HS transition time 3395 * of Scenario 3 is considered. 3396 */ 3397 if (ddr_alwon) { 3398 transition = enter_hs + exit_hs + max(enter_hs, 2) + 1; 3399 } else { 3400 int trans1, trans2; 3401 trans1 = ddr_pre + enter_hs + exit_hs + max(enter_hs, 2) + 1; 3402 trans2 = ddr_pre + enter_hs + exiths_clk + ddr_post + ddr_pre + 3403 enter_hs + 1; 3404 transition = max(trans1, trans2); 3405 } 3406 3407 return blank > transition ? blank - transition : 0; 3408 } 3409 3410 /* 3411 * According to section 'LP Command Mode Interleaving' in OMAP TRM, Scenario 1 3412 * results in maximum transition time for data lanes to enter and exit LP mode. 3413 * Hence, this is the scenario where the least amount of command mode data can 3414 * be interleaved. We program the minimum amount of bytes that can be 3415 * interleaved in LP so that all scenarios are satisfied. 3416 */ 3417 static int dsi_compute_interleave_lp(int blank, int enter_hs, int exit_hs, 3418 int lp_clk_div, int tdsi_fclk) 3419 { 3420 int trans_lp; /* time required for a LP transition, in TXBYTECLKHS */ 3421 int tlp_avail; /* time left for interleaving commands, in CLKIN4DDR */ 3422 int ttxclkesc; /* period of LP transmit escape clock, in CLKIN4DDR */ 3423 int thsbyte_clk = 16; /* Period of TXBYTECLKHS clock, in CLKIN4DDR */ 3424 int lp_inter; /* cmd mode data that can be interleaved, in bytes */ 3425 3426 /* maximum LP transition time according to Scenario 1 */ 3427 trans_lp = exit_hs + max(enter_hs, 2) + 1; 3428 3429 /* CLKIN4DDR = 16 * TXBYTECLKHS */ 3430 tlp_avail = thsbyte_clk * (blank - trans_lp); 3431 3432 ttxclkesc = tdsi_fclk * lp_clk_div; 3433 3434 lp_inter = ((tlp_avail - 8 * thsbyte_clk - 5 * tdsi_fclk) / ttxclkesc - 3435 26) / 16; 3436 3437 return max(lp_inter, 0); 3438 } 3439 3440 static void dsi_config_cmd_mode_interleaving(struct platform_device *dsidev) 3441 { 3442 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 3443 int blanking_mode; 3444 int hfp_blanking_mode, hbp_blanking_mode, hsa_blanking_mode; 3445 int hsa, hfp, hbp, width_bytes, bllp, lp_clk_div; 3446 int ddr_clk_pre, ddr_clk_post, enter_hs_mode_lat, exit_hs_mode_lat; 3447 int tclk_trail, ths_exit, exiths_clk; 3448 bool ddr_alwon; 3449 struct omap_video_timings *timings = &dsi->timings; 3450 int bpp = dsi_get_pixel_size(dsi->pix_fmt); 3451 int ndl = dsi->num_lanes_used - 1; 3452 int dsi_fclk_hsdiv = dsi->user_dsi_cinfo.mX[HSDIV_DSI] + 1; 3453 int hsa_interleave_hs = 0, hsa_interleave_lp = 0; 3454 int hfp_interleave_hs = 0, hfp_interleave_lp = 0; 3455 int hbp_interleave_hs = 0, hbp_interleave_lp = 0; 3456 int bl_interleave_hs = 0, bl_interleave_lp = 0; 3457 u32 r; 3458 3459 r = dsi_read_reg(dsidev, DSI_CTRL); 3460 blanking_mode = FLD_GET(r, 20, 20); 3461 hfp_blanking_mode = FLD_GET(r, 21, 21); 3462 hbp_blanking_mode = FLD_GET(r, 22, 22); 3463 hsa_blanking_mode = FLD_GET(r, 23, 23); 3464 3465 r = dsi_read_reg(dsidev, DSI_VM_TIMING1); 3466 hbp = FLD_GET(r, 11, 0); 3467 hfp = FLD_GET(r, 23, 12); 3468 hsa = FLD_GET(r, 31, 24); 3469 3470 r = dsi_read_reg(dsidev, DSI_CLK_TIMING); 3471 ddr_clk_post = FLD_GET(r, 7, 0); 3472 ddr_clk_pre = FLD_GET(r, 15, 8); 3473 3474 r = dsi_read_reg(dsidev, DSI_VM_TIMING7); 3475 exit_hs_mode_lat = FLD_GET(r, 15, 0); 3476 enter_hs_mode_lat = FLD_GET(r, 31, 16); 3477 3478 r = dsi_read_reg(dsidev, DSI_CLK_CTRL); 3479 lp_clk_div = FLD_GET(r, 12, 0); 3480 ddr_alwon = FLD_GET(r, 13, 13); 3481 3482 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0); 3483 ths_exit = FLD_GET(r, 7, 0); 3484 3485 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1); 3486 tclk_trail = FLD_GET(r, 15, 8); 3487 3488 exiths_clk = ths_exit + tclk_trail; 3489 3490 width_bytes = DIV_ROUND_UP(timings->x_res * bpp, 8); 3491 bllp = hbp + hfp + hsa + DIV_ROUND_UP(width_bytes + 6, ndl); 3492 3493 if (!hsa_blanking_mode) { 3494 hsa_interleave_hs = dsi_compute_interleave_hs(hsa, ddr_alwon, 3495 enter_hs_mode_lat, exit_hs_mode_lat, 3496 exiths_clk, ddr_clk_pre, ddr_clk_post); 3497 hsa_interleave_lp = dsi_compute_interleave_lp(hsa, 3498 enter_hs_mode_lat, exit_hs_mode_lat, 3499 lp_clk_div, dsi_fclk_hsdiv); 3500 } 3501 3502 if (!hfp_blanking_mode) { 3503 hfp_interleave_hs = dsi_compute_interleave_hs(hfp, ddr_alwon, 3504 enter_hs_mode_lat, exit_hs_mode_lat, 3505 exiths_clk, ddr_clk_pre, ddr_clk_post); 3506 hfp_interleave_lp = dsi_compute_interleave_lp(hfp, 3507 enter_hs_mode_lat, exit_hs_mode_lat, 3508 lp_clk_div, dsi_fclk_hsdiv); 3509 } 3510 3511 if (!hbp_blanking_mode) { 3512 hbp_interleave_hs = dsi_compute_interleave_hs(hbp, ddr_alwon, 3513 enter_hs_mode_lat, exit_hs_mode_lat, 3514 exiths_clk, ddr_clk_pre, ddr_clk_post); 3515 3516 hbp_interleave_lp = dsi_compute_interleave_lp(hbp, 3517 enter_hs_mode_lat, exit_hs_mode_lat, 3518 lp_clk_div, dsi_fclk_hsdiv); 3519 } 3520 3521 if (!blanking_mode) { 3522 bl_interleave_hs = dsi_compute_interleave_hs(bllp, ddr_alwon, 3523 enter_hs_mode_lat, exit_hs_mode_lat, 3524 exiths_clk, ddr_clk_pre, ddr_clk_post); 3525 3526 bl_interleave_lp = dsi_compute_interleave_lp(bllp, 3527 enter_hs_mode_lat, exit_hs_mode_lat, 3528 lp_clk_div, dsi_fclk_hsdiv); 3529 } 3530 3531 DSSDBG("DSI HS interleaving(TXBYTECLKHS) HSA %d, HFP %d, HBP %d, BLLP %d\n", 3532 hsa_interleave_hs, hfp_interleave_hs, hbp_interleave_hs, 3533 bl_interleave_hs); 3534 3535 DSSDBG("DSI LP interleaving(bytes) HSA %d, HFP %d, HBP %d, BLLP %d\n", 3536 hsa_interleave_lp, hfp_interleave_lp, hbp_interleave_lp, 3537 bl_interleave_lp); 3538 3539 r = dsi_read_reg(dsidev, DSI_VM_TIMING4); 3540 r = FLD_MOD(r, hsa_interleave_hs, 23, 16); 3541 r = FLD_MOD(r, hfp_interleave_hs, 15, 8); 3542 r = FLD_MOD(r, hbp_interleave_hs, 7, 0); 3543 dsi_write_reg(dsidev, DSI_VM_TIMING4, r); 3544 3545 r = dsi_read_reg(dsidev, DSI_VM_TIMING5); 3546 r = FLD_MOD(r, hsa_interleave_lp, 23, 16); 3547 r = FLD_MOD(r, hfp_interleave_lp, 15, 8); 3548 r = FLD_MOD(r, hbp_interleave_lp, 7, 0); 3549 dsi_write_reg(dsidev, DSI_VM_TIMING5, r); 3550 3551 r = dsi_read_reg(dsidev, DSI_VM_TIMING6); 3552 r = FLD_MOD(r, bl_interleave_hs, 31, 15); 3553 r = FLD_MOD(r, bl_interleave_lp, 16, 0); 3554 dsi_write_reg(dsidev, DSI_VM_TIMING6, r); 3555 } 3556 3557 static int dsi_proto_config(struct platform_device *dsidev) 3558 { 3559 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 3560 u32 r; 3561 int buswidth = 0; 3562 3563 dsi_config_tx_fifo(dsidev, DSI_FIFO_SIZE_32, 3564 DSI_FIFO_SIZE_32, 3565 DSI_FIFO_SIZE_32, 3566 DSI_FIFO_SIZE_32); 3567 3568 dsi_config_rx_fifo(dsidev, DSI_FIFO_SIZE_32, 3569 DSI_FIFO_SIZE_32, 3570 DSI_FIFO_SIZE_32, 3571 DSI_FIFO_SIZE_32); 3572 3573 /* XXX what values for the timeouts? */ 3574 dsi_set_stop_state_counter(dsidev, 0x1000, false, false); 3575 dsi_set_ta_timeout(dsidev, 0x1fff, true, true); 3576 dsi_set_lp_rx_timeout(dsidev, 0x1fff, true, true); 3577 dsi_set_hs_tx_timeout(dsidev, 0x1fff, true, true); 3578 3579 switch (dsi_get_pixel_size(dsi->pix_fmt)) { 3580 case 16: 3581 buswidth = 0; 3582 break; 3583 case 18: 3584 buswidth = 1; 3585 break; 3586 case 24: 3587 buswidth = 2; 3588 break; 3589 default: 3590 BUG(); 3591 return -EINVAL; 3592 } 3593 3594 r = dsi_read_reg(dsidev, DSI_CTRL); 3595 r = FLD_MOD(r, 1, 1, 1); /* CS_RX_EN */ 3596 r = FLD_MOD(r, 1, 2, 2); /* ECC_RX_EN */ 3597 r = FLD_MOD(r, 1, 3, 3); /* TX_FIFO_ARBITRATION */ 3598 r = FLD_MOD(r, 1, 4, 4); /* VP_CLK_RATIO, always 1, see errata*/ 3599 r = FLD_MOD(r, buswidth, 7, 6); /* VP_DATA_BUS_WIDTH */ 3600 r = FLD_MOD(r, 0, 8, 8); /* VP_CLK_POL */ 3601 r = FLD_MOD(r, 1, 14, 14); /* TRIGGER_RESET_MODE */ 3602 r = FLD_MOD(r, 1, 19, 19); /* EOT_ENABLE */ 3603 if (!dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC)) { 3604 r = FLD_MOD(r, 1, 24, 24); /* DCS_CMD_ENABLE */ 3605 /* DCS_CMD_CODE, 1=start, 0=continue */ 3606 r = FLD_MOD(r, 0, 25, 25); 3607 } 3608 3609 dsi_write_reg(dsidev, DSI_CTRL, r); 3610 3611 dsi_config_vp_num_line_buffers(dsidev); 3612 3613 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) { 3614 dsi_config_vp_sync_events(dsidev); 3615 dsi_config_blanking_modes(dsidev); 3616 dsi_config_cmd_mode_interleaving(dsidev); 3617 } 3618 3619 dsi_vc_initial_config(dsidev, 0); 3620 dsi_vc_initial_config(dsidev, 1); 3621 dsi_vc_initial_config(dsidev, 2); 3622 dsi_vc_initial_config(dsidev, 3); 3623 3624 return 0; 3625 } 3626 3627 static void dsi_proto_timings(struct platform_device *dsidev) 3628 { 3629 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 3630 unsigned tlpx, tclk_zero, tclk_prepare, tclk_trail; 3631 unsigned tclk_pre, tclk_post; 3632 unsigned ths_prepare, ths_prepare_ths_zero, ths_zero; 3633 unsigned ths_trail, ths_exit; 3634 unsigned ddr_clk_pre, ddr_clk_post; 3635 unsigned enter_hs_mode_lat, exit_hs_mode_lat; 3636 unsigned ths_eot; 3637 int ndl = dsi->num_lanes_used - 1; 3638 u32 r; 3639 3640 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0); 3641 ths_prepare = FLD_GET(r, 31, 24); 3642 ths_prepare_ths_zero = FLD_GET(r, 23, 16); 3643 ths_zero = ths_prepare_ths_zero - ths_prepare; 3644 ths_trail = FLD_GET(r, 15, 8); 3645 ths_exit = FLD_GET(r, 7, 0); 3646 3647 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1); 3648 tlpx = FLD_GET(r, 20, 16) * 2; 3649 tclk_trail = FLD_GET(r, 15, 8); 3650 tclk_zero = FLD_GET(r, 7, 0); 3651 3652 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG2); 3653 tclk_prepare = FLD_GET(r, 7, 0); 3654 3655 /* min 8*UI */ 3656 tclk_pre = 20; 3657 /* min 60ns + 52*UI */ 3658 tclk_post = ns2ddr(dsidev, 60) + 26; 3659 3660 ths_eot = DIV_ROUND_UP(4, ndl); 3661 3662 ddr_clk_pre = DIV_ROUND_UP(tclk_pre + tlpx + tclk_zero + tclk_prepare, 3663 4); 3664 ddr_clk_post = DIV_ROUND_UP(tclk_post + ths_trail, 4) + ths_eot; 3665 3666 BUG_ON(ddr_clk_pre == 0 || ddr_clk_pre > 255); 3667 BUG_ON(ddr_clk_post == 0 || ddr_clk_post > 255); 3668 3669 r = dsi_read_reg(dsidev, DSI_CLK_TIMING); 3670 r = FLD_MOD(r, ddr_clk_pre, 15, 8); 3671 r = FLD_MOD(r, ddr_clk_post, 7, 0); 3672 dsi_write_reg(dsidev, DSI_CLK_TIMING, r); 3673 3674 DSSDBG("ddr_clk_pre %u, ddr_clk_post %u\n", 3675 ddr_clk_pre, 3676 ddr_clk_post); 3677 3678 enter_hs_mode_lat = 1 + DIV_ROUND_UP(tlpx, 4) + 3679 DIV_ROUND_UP(ths_prepare, 4) + 3680 DIV_ROUND_UP(ths_zero + 3, 4); 3681 3682 exit_hs_mode_lat = DIV_ROUND_UP(ths_trail + ths_exit, 4) + 1 + ths_eot; 3683 3684 r = FLD_VAL(enter_hs_mode_lat, 31, 16) | 3685 FLD_VAL(exit_hs_mode_lat, 15, 0); 3686 dsi_write_reg(dsidev, DSI_VM_TIMING7, r); 3687 3688 DSSDBG("enter_hs_mode_lat %u, exit_hs_mode_lat %u\n", 3689 enter_hs_mode_lat, exit_hs_mode_lat); 3690 3691 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) { 3692 /* TODO: Implement a video mode check_timings function */ 3693 int hsa = dsi->vm_timings.hsa; 3694 int hfp = dsi->vm_timings.hfp; 3695 int hbp = dsi->vm_timings.hbp; 3696 int vsa = dsi->vm_timings.vsa; 3697 int vfp = dsi->vm_timings.vfp; 3698 int vbp = dsi->vm_timings.vbp; 3699 int window_sync = dsi->vm_timings.window_sync; 3700 bool hsync_end; 3701 struct omap_video_timings *timings = &dsi->timings; 3702 int bpp = dsi_get_pixel_size(dsi->pix_fmt); 3703 int tl, t_he, width_bytes; 3704 3705 hsync_end = dsi->vm_timings.trans_mode == OMAP_DSS_DSI_PULSE_MODE; 3706 t_he = hsync_end ? 3707 ((hsa == 0 && ndl == 3) ? 1 : DIV_ROUND_UP(4, ndl)) : 0; 3708 3709 width_bytes = DIV_ROUND_UP(timings->x_res * bpp, 8); 3710 3711 /* TL = t_HS + HSA + t_HE + HFP + ceil((WC + 6) / NDL) + HBP */ 3712 tl = DIV_ROUND_UP(4, ndl) + (hsync_end ? hsa : 0) + t_he + hfp + 3713 DIV_ROUND_UP(width_bytes + 6, ndl) + hbp; 3714 3715 DSSDBG("HBP: %d, HFP: %d, HSA: %d, TL: %d TXBYTECLKHS\n", hbp, 3716 hfp, hsync_end ? hsa : 0, tl); 3717 DSSDBG("VBP: %d, VFP: %d, VSA: %d, VACT: %d lines\n", vbp, vfp, 3718 vsa, timings->y_res); 3719 3720 r = dsi_read_reg(dsidev, DSI_VM_TIMING1); 3721 r = FLD_MOD(r, hbp, 11, 0); /* HBP */ 3722 r = FLD_MOD(r, hfp, 23, 12); /* HFP */ 3723 r = FLD_MOD(r, hsync_end ? hsa : 0, 31, 24); /* HSA */ 3724 dsi_write_reg(dsidev, DSI_VM_TIMING1, r); 3725 3726 r = dsi_read_reg(dsidev, DSI_VM_TIMING2); 3727 r = FLD_MOD(r, vbp, 7, 0); /* VBP */ 3728 r = FLD_MOD(r, vfp, 15, 8); /* VFP */ 3729 r = FLD_MOD(r, vsa, 23, 16); /* VSA */ 3730 r = FLD_MOD(r, window_sync, 27, 24); /* WINDOW_SYNC */ 3731 dsi_write_reg(dsidev, DSI_VM_TIMING2, r); 3732 3733 r = dsi_read_reg(dsidev, DSI_VM_TIMING3); 3734 r = FLD_MOD(r, timings->y_res, 14, 0); /* VACT */ 3735 r = FLD_MOD(r, tl, 31, 16); /* TL */ 3736 dsi_write_reg(dsidev, DSI_VM_TIMING3, r); 3737 } 3738 } 3739 3740 static int dsi_configure_pins(struct omap_dss_device *dssdev, 3741 const struct omap_dsi_pin_config *pin_cfg) 3742 { 3743 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 3744 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 3745 int num_pins; 3746 const int *pins; 3747 struct dsi_lane_config lanes[DSI_MAX_NR_LANES]; 3748 int num_lanes; 3749 int i; 3750 3751 static const enum dsi_lane_function functions[] = { 3752 DSI_LANE_CLK, 3753 DSI_LANE_DATA1, 3754 DSI_LANE_DATA2, 3755 DSI_LANE_DATA3, 3756 DSI_LANE_DATA4, 3757 }; 3758 3759 num_pins = pin_cfg->num_pins; 3760 pins = pin_cfg->pins; 3761 3762 if (num_pins < 4 || num_pins > dsi->num_lanes_supported * 2 3763 || num_pins % 2 != 0) 3764 return -EINVAL; 3765 3766 for (i = 0; i < DSI_MAX_NR_LANES; ++i) 3767 lanes[i].function = DSI_LANE_UNUSED; 3768 3769 num_lanes = 0; 3770 3771 for (i = 0; i < num_pins; i += 2) { 3772 u8 lane, pol; 3773 int dx, dy; 3774 3775 dx = pins[i]; 3776 dy = pins[i + 1]; 3777 3778 if (dx < 0 || dx >= dsi->num_lanes_supported * 2) 3779 return -EINVAL; 3780 3781 if (dy < 0 || dy >= dsi->num_lanes_supported * 2) 3782 return -EINVAL; 3783 3784 if (dx & 1) { 3785 if (dy != dx - 1) 3786 return -EINVAL; 3787 pol = 1; 3788 } else { 3789 if (dy != dx + 1) 3790 return -EINVAL; 3791 pol = 0; 3792 } 3793 3794 lane = dx / 2; 3795 3796 lanes[lane].function = functions[i / 2]; 3797 lanes[lane].polarity = pol; 3798 num_lanes++; 3799 } 3800 3801 memcpy(dsi->lanes, lanes, sizeof(dsi->lanes)); 3802 dsi->num_lanes_used = num_lanes; 3803 3804 return 0; 3805 } 3806 3807 static int dsi_enable_video_output(struct omap_dss_device *dssdev, int channel) 3808 { 3809 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 3810 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 3811 struct omap_overlay_manager *mgr = dsi->output.manager; 3812 int bpp = dsi_get_pixel_size(dsi->pix_fmt); 3813 struct omap_dss_device *out = &dsi->output; 3814 u8 data_type; 3815 u16 word_count; 3816 int r; 3817 3818 if (out->manager == NULL) { 3819 DSSERR("failed to enable display: no output/manager\n"); 3820 return -ENODEV; 3821 } 3822 3823 r = dsi_display_init_dispc(dsidev, mgr); 3824 if (r) 3825 goto err_init_dispc; 3826 3827 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) { 3828 switch (dsi->pix_fmt) { 3829 case OMAP_DSS_DSI_FMT_RGB888: 3830 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_24; 3831 break; 3832 case OMAP_DSS_DSI_FMT_RGB666: 3833 data_type = MIPI_DSI_PIXEL_STREAM_3BYTE_18; 3834 break; 3835 case OMAP_DSS_DSI_FMT_RGB666_PACKED: 3836 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_18; 3837 break; 3838 case OMAP_DSS_DSI_FMT_RGB565: 3839 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_16; 3840 break; 3841 default: 3842 r = -EINVAL; 3843 goto err_pix_fmt; 3844 } 3845 3846 dsi_if_enable(dsidev, false); 3847 dsi_vc_enable(dsidev, channel, false); 3848 3849 /* MODE, 1 = video mode */ 3850 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 1, 4, 4); 3851 3852 word_count = DIV_ROUND_UP(dsi->timings.x_res * bpp, 8); 3853 3854 dsi_vc_write_long_header(dsidev, channel, data_type, 3855 word_count, 0); 3856 3857 dsi_vc_enable(dsidev, channel, true); 3858 dsi_if_enable(dsidev, true); 3859 } 3860 3861 r = dss_mgr_enable(mgr); 3862 if (r) 3863 goto err_mgr_enable; 3864 3865 return 0; 3866 3867 err_mgr_enable: 3868 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) { 3869 dsi_if_enable(dsidev, false); 3870 dsi_vc_enable(dsidev, channel, false); 3871 } 3872 err_pix_fmt: 3873 dsi_display_uninit_dispc(dsidev, mgr); 3874 err_init_dispc: 3875 return r; 3876 } 3877 3878 static void dsi_disable_video_output(struct omap_dss_device *dssdev, int channel) 3879 { 3880 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 3881 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 3882 struct omap_overlay_manager *mgr = dsi->output.manager; 3883 3884 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) { 3885 dsi_if_enable(dsidev, false); 3886 dsi_vc_enable(dsidev, channel, false); 3887 3888 /* MODE, 0 = command mode */ 3889 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 0, 4, 4); 3890 3891 dsi_vc_enable(dsidev, channel, true); 3892 dsi_if_enable(dsidev, true); 3893 } 3894 3895 dss_mgr_disable(mgr); 3896 3897 dsi_display_uninit_dispc(dsidev, mgr); 3898 } 3899 3900 static void dsi_update_screen_dispc(struct platform_device *dsidev) 3901 { 3902 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 3903 struct omap_overlay_manager *mgr = dsi->output.manager; 3904 unsigned bytespp; 3905 unsigned bytespl; 3906 unsigned bytespf; 3907 unsigned total_len; 3908 unsigned packet_payload; 3909 unsigned packet_len; 3910 u32 l; 3911 int r; 3912 const unsigned channel = dsi->update_channel; 3913 const unsigned line_buf_size = dsi->line_buffer_size; 3914 u16 w = dsi->timings.x_res; 3915 u16 h = dsi->timings.y_res; 3916 3917 DSSDBG("dsi_update_screen_dispc(%dx%d)\n", w, h); 3918 3919 dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_VP); 3920 3921 bytespp = dsi_get_pixel_size(dsi->pix_fmt) / 8; 3922 bytespl = w * bytespp; 3923 bytespf = bytespl * h; 3924 3925 /* NOTE: packet_payload has to be equal to N * bytespl, where N is 3926 * number of lines in a packet. See errata about VP_CLK_RATIO */ 3927 3928 if (bytespf < line_buf_size) 3929 packet_payload = bytespf; 3930 else 3931 packet_payload = (line_buf_size) / bytespl * bytespl; 3932 3933 packet_len = packet_payload + 1; /* 1 byte for DCS cmd */ 3934 total_len = (bytespf / packet_payload) * packet_len; 3935 3936 if (bytespf % packet_payload) 3937 total_len += (bytespf % packet_payload) + 1; 3938 3939 l = FLD_VAL(total_len, 23, 0); /* TE_SIZE */ 3940 dsi_write_reg(dsidev, DSI_VC_TE(channel), l); 3941 3942 dsi_vc_write_long_header(dsidev, channel, MIPI_DSI_DCS_LONG_WRITE, 3943 packet_len, 0); 3944 3945 if (dsi->te_enabled) 3946 l = FLD_MOD(l, 1, 30, 30); /* TE_EN */ 3947 else 3948 l = FLD_MOD(l, 1, 31, 31); /* TE_START */ 3949 dsi_write_reg(dsidev, DSI_VC_TE(channel), l); 3950 3951 /* We put SIDLEMODE to no-idle for the duration of the transfer, 3952 * because DSS interrupts are not capable of waking up the CPU and the 3953 * framedone interrupt could be delayed for quite a long time. I think 3954 * the same goes for any DSS interrupts, but for some reason I have not 3955 * seen the problem anywhere else than here. 3956 */ 3957 dispc_disable_sidle(); 3958 3959 dsi_perf_mark_start(dsidev); 3960 3961 r = schedule_delayed_work(&dsi->framedone_timeout_work, 3962 msecs_to_jiffies(250)); 3963 BUG_ON(r == 0); 3964 3965 dss_mgr_set_timings(mgr, &dsi->timings); 3966 3967 dss_mgr_start_update(mgr); 3968 3969 if (dsi->te_enabled) { 3970 /* disable LP_RX_TO, so that we can receive TE. Time to wait 3971 * for TE is longer than the timer allows */ 3972 REG_FLD_MOD(dsidev, DSI_TIMING2, 0, 15, 15); /* LP_RX_TO */ 3973 3974 dsi_vc_send_bta(dsidev, channel); 3975 3976 #ifdef DSI_CATCH_MISSING_TE 3977 mod_timer(&dsi->te_timer, jiffies + msecs_to_jiffies(250)); 3978 #endif 3979 } 3980 } 3981 3982 #ifdef DSI_CATCH_MISSING_TE 3983 static void dsi_te_timeout(struct timer_list *unused) 3984 { 3985 DSSERR("TE not received for 250ms!\n"); 3986 } 3987 #endif 3988 3989 static void dsi_handle_framedone(struct platform_device *dsidev, int error) 3990 { 3991 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 3992 3993 /* SIDLEMODE back to smart-idle */ 3994 dispc_enable_sidle(); 3995 3996 if (dsi->te_enabled) { 3997 /* enable LP_RX_TO again after the TE */ 3998 REG_FLD_MOD(dsidev, DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */ 3999 } 4000 4001 dsi->framedone_callback(error, dsi->framedone_data); 4002 4003 if (!error) 4004 dsi_perf_show(dsidev, "DISPC"); 4005 } 4006 4007 static void dsi_framedone_timeout_work_callback(struct work_struct *work) 4008 { 4009 struct dsi_data *dsi = container_of(work, struct dsi_data, 4010 framedone_timeout_work.work); 4011 /* XXX While extremely unlikely, we could get FRAMEDONE interrupt after 4012 * 250ms which would conflict with this timeout work. What should be 4013 * done is first cancel the transfer on the HW, and then cancel the 4014 * possibly scheduled framedone work. However, cancelling the transfer 4015 * on the HW is buggy, and would probably require resetting the whole 4016 * DSI */ 4017 4018 DSSERR("Framedone not received for 250ms!\n"); 4019 4020 dsi_handle_framedone(dsi->pdev, -ETIMEDOUT); 4021 } 4022 4023 static void dsi_framedone_irq_callback(void *data) 4024 { 4025 struct platform_device *dsidev = (struct platform_device *) data; 4026 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 4027 4028 /* Note: We get FRAMEDONE when DISPC has finished sending pixels and 4029 * turns itself off. However, DSI still has the pixels in its buffers, 4030 * and is sending the data. 4031 */ 4032 4033 cancel_delayed_work(&dsi->framedone_timeout_work); 4034 4035 dsi_handle_framedone(dsidev, 0); 4036 } 4037 4038 static int dsi_update(struct omap_dss_device *dssdev, int channel, 4039 void (*callback)(int, void *), void *data) 4040 { 4041 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 4042 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 4043 u16 dw, dh; 4044 4045 dsi_perf_mark_setup(dsidev); 4046 4047 dsi->update_channel = channel; 4048 4049 dsi->framedone_callback = callback; 4050 dsi->framedone_data = data; 4051 4052 dw = dsi->timings.x_res; 4053 dh = dsi->timings.y_res; 4054 4055 #ifdef DSI_PERF_MEASURE 4056 dsi->update_bytes = dw * dh * 4057 dsi_get_pixel_size(dsi->pix_fmt) / 8; 4058 #endif 4059 dsi_update_screen_dispc(dsidev); 4060 4061 return 0; 4062 } 4063 4064 /* Display funcs */ 4065 4066 static int dsi_configure_dispc_clocks(struct platform_device *dsidev) 4067 { 4068 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 4069 struct dispc_clock_info dispc_cinfo; 4070 int r; 4071 unsigned long fck; 4072 4073 fck = dsi_get_pll_hsdiv_dispc_rate(dsidev); 4074 4075 dispc_cinfo.lck_div = dsi->user_dispc_cinfo.lck_div; 4076 dispc_cinfo.pck_div = dsi->user_dispc_cinfo.pck_div; 4077 4078 r = dispc_calc_clock_rates(fck, &dispc_cinfo); 4079 if (r) { 4080 DSSERR("Failed to calc dispc clocks\n"); 4081 return r; 4082 } 4083 4084 dsi->mgr_config.clock_info = dispc_cinfo; 4085 4086 return 0; 4087 } 4088 4089 static int dsi_display_init_dispc(struct platform_device *dsidev, 4090 struct omap_overlay_manager *mgr) 4091 { 4092 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 4093 int r; 4094 4095 dss_select_lcd_clk_source(mgr->id, dsi->module_id == 0 ? 4096 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC : 4097 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC); 4098 4099 if (dsi->mode == OMAP_DSS_DSI_CMD_MODE) { 4100 r = dss_mgr_register_framedone_handler(mgr, 4101 dsi_framedone_irq_callback, dsidev); 4102 if (r) { 4103 DSSERR("can't register FRAMEDONE handler\n"); 4104 goto err; 4105 } 4106 4107 dsi->mgr_config.stallmode = true; 4108 dsi->mgr_config.fifohandcheck = true; 4109 } else { 4110 dsi->mgr_config.stallmode = false; 4111 dsi->mgr_config.fifohandcheck = false; 4112 } 4113 4114 /* 4115 * override interlace, logic level and edge related parameters in 4116 * omap_video_timings with default values 4117 */ 4118 dsi->timings.interlace = false; 4119 dsi->timings.hsync_level = OMAPDSS_SIG_ACTIVE_HIGH; 4120 dsi->timings.vsync_level = OMAPDSS_SIG_ACTIVE_HIGH; 4121 dsi->timings.data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE; 4122 dsi->timings.de_level = OMAPDSS_SIG_ACTIVE_HIGH; 4123 dsi->timings.sync_pclk_edge = OMAPDSS_DRIVE_SIG_FALLING_EDGE; 4124 4125 dss_mgr_set_timings(mgr, &dsi->timings); 4126 4127 r = dsi_configure_dispc_clocks(dsidev); 4128 if (r) 4129 goto err1; 4130 4131 dsi->mgr_config.io_pad_mode = DSS_IO_PAD_MODE_BYPASS; 4132 dsi->mgr_config.video_port_width = 4133 dsi_get_pixel_size(dsi->pix_fmt); 4134 dsi->mgr_config.lcden_sig_polarity = 0; 4135 4136 dss_mgr_set_lcd_config(mgr, &dsi->mgr_config); 4137 4138 return 0; 4139 err1: 4140 if (dsi->mode == OMAP_DSS_DSI_CMD_MODE) 4141 dss_mgr_unregister_framedone_handler(mgr, 4142 dsi_framedone_irq_callback, dsidev); 4143 err: 4144 dss_select_lcd_clk_source(mgr->id, OMAP_DSS_CLK_SRC_FCK); 4145 return r; 4146 } 4147 4148 static void dsi_display_uninit_dispc(struct platform_device *dsidev, 4149 struct omap_overlay_manager *mgr) 4150 { 4151 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 4152 4153 if (dsi->mode == OMAP_DSS_DSI_CMD_MODE) 4154 dss_mgr_unregister_framedone_handler(mgr, 4155 dsi_framedone_irq_callback, dsidev); 4156 4157 dss_select_lcd_clk_source(mgr->id, OMAP_DSS_CLK_SRC_FCK); 4158 } 4159 4160 static int dsi_configure_dsi_clocks(struct platform_device *dsidev) 4161 { 4162 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 4163 struct dss_pll_clock_info cinfo; 4164 int r; 4165 4166 cinfo = dsi->user_dsi_cinfo; 4167 4168 r = dss_pll_set_config(&dsi->pll, &cinfo); 4169 if (r) { 4170 DSSERR("Failed to set dsi clocks\n"); 4171 return r; 4172 } 4173 4174 return 0; 4175 } 4176 4177 static int dsi_display_init_dsi(struct platform_device *dsidev) 4178 { 4179 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 4180 int r; 4181 4182 r = dss_pll_enable(&dsi->pll); 4183 if (r) 4184 goto err0; 4185 4186 r = dsi_configure_dsi_clocks(dsidev); 4187 if (r) 4188 goto err1; 4189 4190 dss_select_dsi_clk_source(dsi->module_id, dsi->module_id == 0 ? 4191 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI : 4192 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI); 4193 4194 DSSDBG("PLL OK\n"); 4195 4196 r = dsi_cio_init(dsidev); 4197 if (r) 4198 goto err2; 4199 4200 _dsi_print_reset_status(dsidev); 4201 4202 dsi_proto_timings(dsidev); 4203 dsi_set_lp_clk_divisor(dsidev); 4204 4205 if (1) 4206 _dsi_print_reset_status(dsidev); 4207 4208 r = dsi_proto_config(dsidev); 4209 if (r) 4210 goto err3; 4211 4212 /* enable interface */ 4213 dsi_vc_enable(dsidev, 0, 1); 4214 dsi_vc_enable(dsidev, 1, 1); 4215 dsi_vc_enable(dsidev, 2, 1); 4216 dsi_vc_enable(dsidev, 3, 1); 4217 dsi_if_enable(dsidev, 1); 4218 dsi_force_tx_stop_mode_io(dsidev); 4219 4220 return 0; 4221 err3: 4222 dsi_cio_uninit(dsidev); 4223 err2: 4224 dss_select_dsi_clk_source(dsi->module_id, OMAP_DSS_CLK_SRC_FCK); 4225 err1: 4226 dss_pll_disable(&dsi->pll); 4227 err0: 4228 return r; 4229 } 4230 4231 static void dsi_display_uninit_dsi(struct platform_device *dsidev, 4232 bool disconnect_lanes, bool enter_ulps) 4233 { 4234 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 4235 4236 if (enter_ulps && !dsi->ulps_enabled) 4237 dsi_enter_ulps(dsidev); 4238 4239 /* disable interface */ 4240 dsi_if_enable(dsidev, 0); 4241 dsi_vc_enable(dsidev, 0, 0); 4242 dsi_vc_enable(dsidev, 1, 0); 4243 dsi_vc_enable(dsidev, 2, 0); 4244 dsi_vc_enable(dsidev, 3, 0); 4245 4246 dss_select_dsi_clk_source(dsi->module_id, OMAP_DSS_CLK_SRC_FCK); 4247 dsi_cio_uninit(dsidev); 4248 dsi_pll_uninit(dsidev, disconnect_lanes); 4249 } 4250 4251 static int dsi_display_enable(struct omap_dss_device *dssdev) 4252 { 4253 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 4254 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 4255 int r = 0; 4256 4257 DSSDBG("dsi_display_enable\n"); 4258 4259 WARN_ON(!dsi_bus_is_locked(dsidev)); 4260 4261 mutex_lock(&dsi->lock); 4262 4263 r = dsi_runtime_get(dsidev); 4264 if (r) 4265 goto err_get_dsi; 4266 4267 _dsi_initialize_irq(dsidev); 4268 4269 r = dsi_display_init_dsi(dsidev); 4270 if (r) 4271 goto err_init_dsi; 4272 4273 mutex_unlock(&dsi->lock); 4274 4275 return 0; 4276 4277 err_init_dsi: 4278 dsi_runtime_put(dsidev); 4279 err_get_dsi: 4280 mutex_unlock(&dsi->lock); 4281 DSSDBG("dsi_display_enable FAILED\n"); 4282 return r; 4283 } 4284 4285 static void dsi_display_disable(struct omap_dss_device *dssdev, 4286 bool disconnect_lanes, bool enter_ulps) 4287 { 4288 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 4289 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 4290 4291 DSSDBG("dsi_display_disable\n"); 4292 4293 WARN_ON(!dsi_bus_is_locked(dsidev)); 4294 4295 mutex_lock(&dsi->lock); 4296 4297 dsi_sync_vc(dsidev, 0); 4298 dsi_sync_vc(dsidev, 1); 4299 dsi_sync_vc(dsidev, 2); 4300 dsi_sync_vc(dsidev, 3); 4301 4302 dsi_display_uninit_dsi(dsidev, disconnect_lanes, enter_ulps); 4303 4304 dsi_runtime_put(dsidev); 4305 4306 mutex_unlock(&dsi->lock); 4307 } 4308 4309 static int dsi_enable_te(struct omap_dss_device *dssdev, bool enable) 4310 { 4311 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 4312 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 4313 4314 dsi->te_enabled = enable; 4315 return 0; 4316 } 4317 4318 #ifdef PRINT_VERBOSE_VM_TIMINGS 4319 static void print_dsi_vm(const char *str, 4320 const struct omap_dss_dsi_videomode_timings *t) 4321 { 4322 unsigned long byteclk = t->hsclk / 4; 4323 int bl, wc, pps, tot; 4324 4325 wc = DIV_ROUND_UP(t->hact * t->bitspp, 8); 4326 pps = DIV_ROUND_UP(wc + 6, t->ndl); /* pixel packet size */ 4327 bl = t->hss + t->hsa + t->hse + t->hbp + t->hfp; 4328 tot = bl + pps; 4329 4330 #define TO_DSI_T(x) ((u32)div64_u64((u64)x * 1000000000llu, byteclk)) 4331 4332 pr_debug("%s bck %lu, %u/%u/%u/%u/%u/%u = %u+%u = %u, " 4333 "%u/%u/%u/%u/%u/%u = %u + %u = %u\n", 4334 str, 4335 byteclk, 4336 t->hss, t->hsa, t->hse, t->hbp, pps, t->hfp, 4337 bl, pps, tot, 4338 TO_DSI_T(t->hss), 4339 TO_DSI_T(t->hsa), 4340 TO_DSI_T(t->hse), 4341 TO_DSI_T(t->hbp), 4342 TO_DSI_T(pps), 4343 TO_DSI_T(t->hfp), 4344 4345 TO_DSI_T(bl), 4346 TO_DSI_T(pps), 4347 4348 TO_DSI_T(tot)); 4349 #undef TO_DSI_T 4350 } 4351 4352 static void print_dispc_vm(const char *str, const struct omap_video_timings *t) 4353 { 4354 unsigned long pck = t->pixelclock; 4355 int hact, bl, tot; 4356 4357 hact = t->x_res; 4358 bl = t->hsw + t->hbp + t->hfp; 4359 tot = hact + bl; 4360 4361 #define TO_DISPC_T(x) ((u32)div64_u64((u64)x * 1000000000llu, pck)) 4362 4363 pr_debug("%s pck %lu, %u/%u/%u/%u = %u+%u = %u, " 4364 "%u/%u/%u/%u = %u + %u = %u\n", 4365 str, 4366 pck, 4367 t->hsw, t->hbp, hact, t->hfp, 4368 bl, hact, tot, 4369 TO_DISPC_T(t->hsw), 4370 TO_DISPC_T(t->hbp), 4371 TO_DISPC_T(hact), 4372 TO_DISPC_T(t->hfp), 4373 TO_DISPC_T(bl), 4374 TO_DISPC_T(hact), 4375 TO_DISPC_T(tot)); 4376 #undef TO_DISPC_T 4377 } 4378 4379 /* note: this is not quite accurate */ 4380 static void print_dsi_dispc_vm(const char *str, 4381 const struct omap_dss_dsi_videomode_timings *t) 4382 { 4383 struct omap_video_timings vm = { 0 }; 4384 unsigned long byteclk = t->hsclk / 4; 4385 unsigned long pck; 4386 u64 dsi_tput; 4387 int dsi_hact, dsi_htot; 4388 4389 dsi_tput = (u64)byteclk * t->ndl * 8; 4390 pck = (u32)div64_u64(dsi_tput, t->bitspp); 4391 dsi_hact = DIV_ROUND_UP(DIV_ROUND_UP(t->hact * t->bitspp, 8) + 6, t->ndl); 4392 dsi_htot = t->hss + t->hsa + t->hse + t->hbp + dsi_hact + t->hfp; 4393 4394 vm.pixelclock = pck; 4395 vm.hsw = div64_u64((u64)(t->hsa + t->hse) * pck, byteclk); 4396 vm.hbp = div64_u64((u64)t->hbp * pck, byteclk); 4397 vm.hfp = div64_u64((u64)t->hfp * pck, byteclk); 4398 vm.x_res = t->hact; 4399 4400 print_dispc_vm(str, &vm); 4401 } 4402 #endif /* PRINT_VERBOSE_VM_TIMINGS */ 4403 4404 static bool dsi_cm_calc_dispc_cb(int lckd, int pckd, unsigned long lck, 4405 unsigned long pck, void *data) 4406 { 4407 struct dsi_clk_calc_ctx *ctx = data; 4408 struct omap_video_timings *t = &ctx->dispc_vm; 4409 4410 ctx->dispc_cinfo.lck_div = lckd; 4411 ctx->dispc_cinfo.pck_div = pckd; 4412 ctx->dispc_cinfo.lck = lck; 4413 ctx->dispc_cinfo.pck = pck; 4414 4415 *t = *ctx->config->timings; 4416 t->pixelclock = pck; 4417 t->x_res = ctx->config->timings->x_res; 4418 t->y_res = ctx->config->timings->y_res; 4419 t->hsw = t->hfp = t->hbp = t->vsw = 1; 4420 t->vfp = t->vbp = 0; 4421 4422 return true; 4423 } 4424 4425 static bool dsi_cm_calc_hsdiv_cb(int m_dispc, unsigned long dispc, 4426 void *data) 4427 { 4428 struct dsi_clk_calc_ctx *ctx = data; 4429 4430 ctx->dsi_cinfo.mX[HSDIV_DISPC] = m_dispc; 4431 ctx->dsi_cinfo.clkout[HSDIV_DISPC] = dispc; 4432 4433 return dispc_div_calc(dispc, ctx->req_pck_min, ctx->req_pck_max, 4434 dsi_cm_calc_dispc_cb, ctx); 4435 } 4436 4437 static bool dsi_cm_calc_pll_cb(int n, int m, unsigned long fint, 4438 unsigned long clkdco, void *data) 4439 { 4440 struct dsi_clk_calc_ctx *ctx = data; 4441 4442 ctx->dsi_cinfo.n = n; 4443 ctx->dsi_cinfo.m = m; 4444 ctx->dsi_cinfo.fint = fint; 4445 ctx->dsi_cinfo.clkdco = clkdco; 4446 4447 return dss_pll_hsdiv_calc(ctx->pll, clkdco, ctx->req_pck_min, 4448 dss_feat_get_param_max(FEAT_PARAM_DSS_FCK), 4449 dsi_cm_calc_hsdiv_cb, ctx); 4450 } 4451 4452 static bool dsi_cm_calc(struct dsi_data *dsi, 4453 const struct omap_dss_dsi_config *cfg, 4454 struct dsi_clk_calc_ctx *ctx) 4455 { 4456 unsigned long clkin; 4457 int bitspp, ndl; 4458 unsigned long pll_min, pll_max; 4459 unsigned long pck, txbyteclk; 4460 4461 clkin = clk_get_rate(dsi->pll.clkin); 4462 bitspp = dsi_get_pixel_size(cfg->pixel_format); 4463 ndl = dsi->num_lanes_used - 1; 4464 4465 /* 4466 * Here we should calculate minimum txbyteclk to be able to send the 4467 * frame in time, and also to handle TE. That's not very simple, though, 4468 * especially as we go to LP between each pixel packet due to HW 4469 * "feature". So let's just estimate very roughly and multiply by 1.5. 4470 */ 4471 pck = cfg->timings->pixelclock; 4472 pck = pck * 3 / 2; 4473 txbyteclk = pck * bitspp / 8 / ndl; 4474 4475 memset(ctx, 0, sizeof(*ctx)); 4476 ctx->dsidev = dsi->pdev; 4477 ctx->pll = &dsi->pll; 4478 ctx->config = cfg; 4479 ctx->req_pck_min = pck; 4480 ctx->req_pck_nom = pck; 4481 ctx->req_pck_max = pck * 3 / 2; 4482 4483 pll_min = max(cfg->hs_clk_min * 4, txbyteclk * 4 * 4); 4484 pll_max = cfg->hs_clk_max * 4; 4485 4486 return dss_pll_calc(ctx->pll, clkin, 4487 pll_min, pll_max, 4488 dsi_cm_calc_pll_cb, ctx); 4489 } 4490 4491 static bool dsi_vm_calc_blanking(struct dsi_clk_calc_ctx *ctx) 4492 { 4493 struct dsi_data *dsi = dsi_get_dsidrv_data(ctx->dsidev); 4494 const struct omap_dss_dsi_config *cfg = ctx->config; 4495 int bitspp = dsi_get_pixel_size(cfg->pixel_format); 4496 int ndl = dsi->num_lanes_used - 1; 4497 unsigned long hsclk = ctx->dsi_cinfo.clkdco / 4; 4498 unsigned long byteclk = hsclk / 4; 4499 4500 unsigned long dispc_pck, req_pck_min, req_pck_nom, req_pck_max; 4501 int xres; 4502 int panel_htot, panel_hbl; /* pixels */ 4503 int dispc_htot, dispc_hbl; /* pixels */ 4504 int dsi_htot, dsi_hact, dsi_hbl, hss, hse; /* byteclks */ 4505 int hfp, hsa, hbp; 4506 const struct omap_video_timings *req_vm; 4507 struct omap_video_timings *dispc_vm; 4508 struct omap_dss_dsi_videomode_timings *dsi_vm; 4509 u64 dsi_tput, dispc_tput; 4510 4511 dsi_tput = (u64)byteclk * ndl * 8; 4512 4513 req_vm = cfg->timings; 4514 req_pck_min = ctx->req_pck_min; 4515 req_pck_max = ctx->req_pck_max; 4516 req_pck_nom = ctx->req_pck_nom; 4517 4518 dispc_pck = ctx->dispc_cinfo.pck; 4519 dispc_tput = (u64)dispc_pck * bitspp; 4520 4521 xres = req_vm->x_res; 4522 4523 panel_hbl = req_vm->hfp + req_vm->hbp + req_vm->hsw; 4524 panel_htot = xres + panel_hbl; 4525 4526 dsi_hact = DIV_ROUND_UP(DIV_ROUND_UP(xres * bitspp, 8) + 6, ndl); 4527 4528 /* 4529 * When there are no line buffers, DISPC and DSI must have the 4530 * same tput. Otherwise DISPC tput needs to be higher than DSI's. 4531 */ 4532 if (dsi->line_buffer_size < xres * bitspp / 8) { 4533 if (dispc_tput != dsi_tput) 4534 return false; 4535 } else { 4536 if (dispc_tput < dsi_tput) 4537 return false; 4538 } 4539 4540 /* DSI tput must be over the min requirement */ 4541 if (dsi_tput < (u64)bitspp * req_pck_min) 4542 return false; 4543 4544 /* When non-burst mode, DSI tput must be below max requirement. */ 4545 if (cfg->trans_mode != OMAP_DSS_DSI_BURST_MODE) { 4546 if (dsi_tput > (u64)bitspp * req_pck_max) 4547 return false; 4548 } 4549 4550 hss = DIV_ROUND_UP(4, ndl); 4551 4552 if (cfg->trans_mode == OMAP_DSS_DSI_PULSE_MODE) { 4553 if (ndl == 3 && req_vm->hsw == 0) 4554 hse = 1; 4555 else 4556 hse = DIV_ROUND_UP(4, ndl); 4557 } else { 4558 hse = 0; 4559 } 4560 4561 /* DSI htot to match the panel's nominal pck */ 4562 dsi_htot = div64_u64((u64)panel_htot * byteclk, req_pck_nom); 4563 4564 /* fail if there would be no time for blanking */ 4565 if (dsi_htot < hss + hse + dsi_hact) 4566 return false; 4567 4568 /* total DSI blanking needed to achieve panel's TL */ 4569 dsi_hbl = dsi_htot - dsi_hact; 4570 4571 /* DISPC htot to match the DSI TL */ 4572 dispc_htot = div64_u64((u64)dsi_htot * dispc_pck, byteclk); 4573 4574 /* verify that the DSI and DISPC TLs are the same */ 4575 if ((u64)dsi_htot * dispc_pck != (u64)dispc_htot * byteclk) 4576 return false; 4577 4578 dispc_hbl = dispc_htot - xres; 4579 4580 /* setup DSI videomode */ 4581 4582 dsi_vm = &ctx->dsi_vm; 4583 memset(dsi_vm, 0, sizeof(*dsi_vm)); 4584 4585 dsi_vm->hsclk = hsclk; 4586 4587 dsi_vm->ndl = ndl; 4588 dsi_vm->bitspp = bitspp; 4589 4590 if (cfg->trans_mode != OMAP_DSS_DSI_PULSE_MODE) { 4591 hsa = 0; 4592 } else if (ndl == 3 && req_vm->hsw == 0) { 4593 hsa = 0; 4594 } else { 4595 hsa = div64_u64((u64)req_vm->hsw * byteclk, req_pck_nom); 4596 hsa = max(hsa - hse, 1); 4597 } 4598 4599 hbp = div64_u64((u64)req_vm->hbp * byteclk, req_pck_nom); 4600 hbp = max(hbp, 1); 4601 4602 hfp = dsi_hbl - (hss + hsa + hse + hbp); 4603 if (hfp < 1) { 4604 int t; 4605 /* we need to take cycles from hbp */ 4606 4607 t = 1 - hfp; 4608 hbp = max(hbp - t, 1); 4609 hfp = dsi_hbl - (hss + hsa + hse + hbp); 4610 4611 if (hfp < 1 && hsa > 0) { 4612 /* we need to take cycles from hsa */ 4613 t = 1 - hfp; 4614 hsa = max(hsa - t, 1); 4615 hfp = dsi_hbl - (hss + hsa + hse + hbp); 4616 } 4617 } 4618 4619 if (hfp < 1) 4620 return false; 4621 4622 dsi_vm->hss = hss; 4623 dsi_vm->hsa = hsa; 4624 dsi_vm->hse = hse; 4625 dsi_vm->hbp = hbp; 4626 dsi_vm->hact = xres; 4627 dsi_vm->hfp = hfp; 4628 4629 dsi_vm->vsa = req_vm->vsw; 4630 dsi_vm->vbp = req_vm->vbp; 4631 dsi_vm->vact = req_vm->y_res; 4632 dsi_vm->vfp = req_vm->vfp; 4633 4634 dsi_vm->trans_mode = cfg->trans_mode; 4635 4636 dsi_vm->blanking_mode = 0; 4637 dsi_vm->hsa_blanking_mode = 1; 4638 dsi_vm->hfp_blanking_mode = 1; 4639 dsi_vm->hbp_blanking_mode = 1; 4640 4641 dsi_vm->ddr_clk_always_on = cfg->ddr_clk_always_on; 4642 dsi_vm->window_sync = 4; 4643 4644 /* setup DISPC videomode */ 4645 4646 dispc_vm = &ctx->dispc_vm; 4647 *dispc_vm = *req_vm; 4648 dispc_vm->pixelclock = dispc_pck; 4649 4650 if (cfg->trans_mode == OMAP_DSS_DSI_PULSE_MODE) { 4651 hsa = div64_u64((u64)req_vm->hsw * dispc_pck, 4652 req_pck_nom); 4653 hsa = max(hsa, 1); 4654 } else { 4655 hsa = 1; 4656 } 4657 4658 hbp = div64_u64((u64)req_vm->hbp * dispc_pck, req_pck_nom); 4659 hbp = max(hbp, 1); 4660 4661 hfp = dispc_hbl - hsa - hbp; 4662 if (hfp < 1) { 4663 int t; 4664 /* we need to take cycles from hbp */ 4665 4666 t = 1 - hfp; 4667 hbp = max(hbp - t, 1); 4668 hfp = dispc_hbl - hsa - hbp; 4669 4670 if (hfp < 1) { 4671 /* we need to take cycles from hsa */ 4672 t = 1 - hfp; 4673 hsa = max(hsa - t, 1); 4674 hfp = dispc_hbl - hsa - hbp; 4675 } 4676 } 4677 4678 if (hfp < 1) 4679 return false; 4680 4681 dispc_vm->hfp = hfp; 4682 dispc_vm->hsw = hsa; 4683 dispc_vm->hbp = hbp; 4684 4685 return true; 4686 } 4687 4688 4689 static bool dsi_vm_calc_dispc_cb(int lckd, int pckd, unsigned long lck, 4690 unsigned long pck, void *data) 4691 { 4692 struct dsi_clk_calc_ctx *ctx = data; 4693 4694 ctx->dispc_cinfo.lck_div = lckd; 4695 ctx->dispc_cinfo.pck_div = pckd; 4696 ctx->dispc_cinfo.lck = lck; 4697 ctx->dispc_cinfo.pck = pck; 4698 4699 if (dsi_vm_calc_blanking(ctx) == false) 4700 return false; 4701 4702 #ifdef PRINT_VERBOSE_VM_TIMINGS 4703 print_dispc_vm("dispc", &ctx->dispc_vm); 4704 print_dsi_vm("dsi ", &ctx->dsi_vm); 4705 print_dispc_vm("req ", ctx->config->timings); 4706 print_dsi_dispc_vm("act ", &ctx->dsi_vm); 4707 #endif 4708 4709 return true; 4710 } 4711 4712 static bool dsi_vm_calc_hsdiv_cb(int m_dispc, unsigned long dispc, 4713 void *data) 4714 { 4715 struct dsi_clk_calc_ctx *ctx = data; 4716 unsigned long pck_max; 4717 4718 ctx->dsi_cinfo.mX[HSDIV_DISPC] = m_dispc; 4719 ctx->dsi_cinfo.clkout[HSDIV_DISPC] = dispc; 4720 4721 /* 4722 * In burst mode we can let the dispc pck be arbitrarily high, but it 4723 * limits our scaling abilities. So for now, don't aim too high. 4724 */ 4725 4726 if (ctx->config->trans_mode == OMAP_DSS_DSI_BURST_MODE) 4727 pck_max = ctx->req_pck_max + 10000000; 4728 else 4729 pck_max = ctx->req_pck_max; 4730 4731 return dispc_div_calc(dispc, ctx->req_pck_min, pck_max, 4732 dsi_vm_calc_dispc_cb, ctx); 4733 } 4734 4735 static bool dsi_vm_calc_pll_cb(int n, int m, unsigned long fint, 4736 unsigned long clkdco, void *data) 4737 { 4738 struct dsi_clk_calc_ctx *ctx = data; 4739 4740 ctx->dsi_cinfo.n = n; 4741 ctx->dsi_cinfo.m = m; 4742 ctx->dsi_cinfo.fint = fint; 4743 ctx->dsi_cinfo.clkdco = clkdco; 4744 4745 return dss_pll_hsdiv_calc(ctx->pll, clkdco, ctx->req_pck_min, 4746 dss_feat_get_param_max(FEAT_PARAM_DSS_FCK), 4747 dsi_vm_calc_hsdiv_cb, ctx); 4748 } 4749 4750 static bool dsi_vm_calc(struct dsi_data *dsi, 4751 const struct omap_dss_dsi_config *cfg, 4752 struct dsi_clk_calc_ctx *ctx) 4753 { 4754 const struct omap_video_timings *t = cfg->timings; 4755 unsigned long clkin; 4756 unsigned long pll_min; 4757 unsigned long pll_max; 4758 int ndl = dsi->num_lanes_used - 1; 4759 int bitspp = dsi_get_pixel_size(cfg->pixel_format); 4760 unsigned long byteclk_min; 4761 4762 clkin = clk_get_rate(dsi->pll.clkin); 4763 4764 memset(ctx, 0, sizeof(*ctx)); 4765 ctx->dsidev = dsi->pdev; 4766 ctx->pll = &dsi->pll; 4767 ctx->config = cfg; 4768 4769 /* these limits should come from the panel driver */ 4770 ctx->req_pck_min = t->pixelclock - 1000; 4771 ctx->req_pck_nom = t->pixelclock; 4772 ctx->req_pck_max = t->pixelclock + 1000; 4773 4774 byteclk_min = div64_u64((u64)ctx->req_pck_min * bitspp, ndl * 8); 4775 pll_min = max(cfg->hs_clk_min * 4, byteclk_min * 4 * 4); 4776 4777 if (cfg->trans_mode == OMAP_DSS_DSI_BURST_MODE) { 4778 pll_max = cfg->hs_clk_max * 4; 4779 } else { 4780 unsigned long byteclk_max; 4781 byteclk_max = div64_u64((u64)ctx->req_pck_max * bitspp, 4782 ndl * 8); 4783 4784 pll_max = byteclk_max * 4 * 4; 4785 } 4786 4787 return dss_pll_calc(ctx->pll, clkin, 4788 pll_min, pll_max, 4789 dsi_vm_calc_pll_cb, ctx); 4790 } 4791 4792 static int dsi_set_config(struct omap_dss_device *dssdev, 4793 const struct omap_dss_dsi_config *config) 4794 { 4795 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 4796 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 4797 struct dsi_clk_calc_ctx ctx; 4798 bool ok; 4799 int r; 4800 4801 mutex_lock(&dsi->lock); 4802 4803 dsi->pix_fmt = config->pixel_format; 4804 dsi->mode = config->mode; 4805 4806 if (config->mode == OMAP_DSS_DSI_VIDEO_MODE) 4807 ok = dsi_vm_calc(dsi, config, &ctx); 4808 else 4809 ok = dsi_cm_calc(dsi, config, &ctx); 4810 4811 if (!ok) { 4812 DSSERR("failed to find suitable DSI clock settings\n"); 4813 r = -EINVAL; 4814 goto err; 4815 } 4816 4817 dsi_pll_calc_dsi_fck(&ctx.dsi_cinfo); 4818 4819 r = dsi_lp_clock_calc(ctx.dsi_cinfo.clkout[HSDIV_DSI], 4820 config->lp_clk_min, config->lp_clk_max, &dsi->user_lp_cinfo); 4821 if (r) { 4822 DSSERR("failed to find suitable DSI LP clock settings\n"); 4823 goto err; 4824 } 4825 4826 dsi->user_dsi_cinfo = ctx.dsi_cinfo; 4827 dsi->user_dispc_cinfo = ctx.dispc_cinfo; 4828 4829 dsi->timings = ctx.dispc_vm; 4830 dsi->vm_timings = ctx.dsi_vm; 4831 4832 mutex_unlock(&dsi->lock); 4833 4834 return 0; 4835 err: 4836 mutex_unlock(&dsi->lock); 4837 4838 return r; 4839 } 4840 4841 /* 4842 * Return a hardcoded channel for the DSI output. This should work for 4843 * current use cases, but this can be later expanded to either resolve 4844 * the channel in some more dynamic manner, or get the channel as a user 4845 * parameter. 4846 */ 4847 static enum omap_channel dsi_get_channel(int module_id) 4848 { 4849 switch (omapdss_get_version()) { 4850 case OMAPDSS_VER_OMAP24xx: 4851 case OMAPDSS_VER_AM43xx: 4852 DSSWARN("DSI not supported\n"); 4853 return OMAP_DSS_CHANNEL_LCD; 4854 4855 case OMAPDSS_VER_OMAP34xx_ES1: 4856 case OMAPDSS_VER_OMAP34xx_ES3: 4857 case OMAPDSS_VER_OMAP3630: 4858 case OMAPDSS_VER_AM35xx: 4859 return OMAP_DSS_CHANNEL_LCD; 4860 4861 case OMAPDSS_VER_OMAP4430_ES1: 4862 case OMAPDSS_VER_OMAP4430_ES2: 4863 case OMAPDSS_VER_OMAP4: 4864 switch (module_id) { 4865 case 0: 4866 return OMAP_DSS_CHANNEL_LCD; 4867 case 1: 4868 return OMAP_DSS_CHANNEL_LCD2; 4869 default: 4870 DSSWARN("unsupported module id\n"); 4871 return OMAP_DSS_CHANNEL_LCD; 4872 } 4873 4874 case OMAPDSS_VER_OMAP5: 4875 switch (module_id) { 4876 case 0: 4877 return OMAP_DSS_CHANNEL_LCD; 4878 case 1: 4879 return OMAP_DSS_CHANNEL_LCD3; 4880 default: 4881 DSSWARN("unsupported module id\n"); 4882 return OMAP_DSS_CHANNEL_LCD; 4883 } 4884 4885 default: 4886 DSSWARN("unsupported DSS version\n"); 4887 return OMAP_DSS_CHANNEL_LCD; 4888 } 4889 } 4890 4891 static int dsi_request_vc(struct omap_dss_device *dssdev, int *channel) 4892 { 4893 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 4894 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 4895 int i; 4896 4897 for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) { 4898 if (!dsi->vc[i].dssdev) { 4899 dsi->vc[i].dssdev = dssdev; 4900 *channel = i; 4901 return 0; 4902 } 4903 } 4904 4905 DSSERR("cannot get VC for display %s", dssdev->name); 4906 return -ENOSPC; 4907 } 4908 4909 static int dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id) 4910 { 4911 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 4912 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 4913 4914 if (vc_id < 0 || vc_id > 3) { 4915 DSSERR("VC ID out of range\n"); 4916 return -EINVAL; 4917 } 4918 4919 if (channel < 0 || channel > 3) { 4920 DSSERR("Virtual Channel out of range\n"); 4921 return -EINVAL; 4922 } 4923 4924 if (dsi->vc[channel].dssdev != dssdev) { 4925 DSSERR("Virtual Channel not allocated to display %s\n", 4926 dssdev->name); 4927 return -EINVAL; 4928 } 4929 4930 dsi->vc[channel].vc_id = vc_id; 4931 4932 return 0; 4933 } 4934 4935 static void dsi_release_vc(struct omap_dss_device *dssdev, int channel) 4936 { 4937 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 4938 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 4939 4940 if ((channel >= 0 && channel <= 3) && 4941 dsi->vc[channel].dssdev == dssdev) { 4942 dsi->vc[channel].dssdev = NULL; 4943 dsi->vc[channel].vc_id = 0; 4944 } 4945 } 4946 4947 4948 static int dsi_get_clocks(struct platform_device *dsidev) 4949 { 4950 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 4951 struct clk *clk; 4952 4953 clk = devm_clk_get(&dsidev->dev, "fck"); 4954 if (IS_ERR(clk)) { 4955 DSSERR("can't get fck\n"); 4956 return PTR_ERR(clk); 4957 } 4958 4959 dsi->dss_clk = clk; 4960 4961 return 0; 4962 } 4963 4964 static int dsi_connect(struct omap_dss_device *dssdev, 4965 struct omap_dss_device *dst) 4966 { 4967 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 4968 struct omap_overlay_manager *mgr; 4969 int r; 4970 4971 r = dsi_regulator_init(dsidev); 4972 if (r) 4973 return r; 4974 4975 mgr = omap_dss_get_overlay_manager(dssdev->dispc_channel); 4976 if (!mgr) 4977 return -ENODEV; 4978 4979 r = dss_mgr_connect(mgr, dssdev); 4980 if (r) 4981 return r; 4982 4983 r = omapdss_output_set_device(dssdev, dst); 4984 if (r) { 4985 DSSERR("failed to connect output to new device: %s\n", 4986 dssdev->name); 4987 dss_mgr_disconnect(mgr, dssdev); 4988 return r; 4989 } 4990 4991 return 0; 4992 } 4993 4994 static void dsi_disconnect(struct omap_dss_device *dssdev, 4995 struct omap_dss_device *dst) 4996 { 4997 WARN_ON(dst != dssdev->dst); 4998 4999 if (dst != dssdev->dst) 5000 return; 5001 5002 omapdss_output_unset_device(dssdev); 5003 5004 if (dssdev->manager) 5005 dss_mgr_disconnect(dssdev->manager, dssdev); 5006 } 5007 5008 static const struct omapdss_dsi_ops dsi_ops = { 5009 .connect = dsi_connect, 5010 .disconnect = dsi_disconnect, 5011 5012 .bus_lock = dsi_bus_lock, 5013 .bus_unlock = dsi_bus_unlock, 5014 5015 .enable = dsi_display_enable, 5016 .disable = dsi_display_disable, 5017 5018 .enable_hs = dsi_vc_enable_hs, 5019 5020 .configure_pins = dsi_configure_pins, 5021 .set_config = dsi_set_config, 5022 5023 .enable_video_output = dsi_enable_video_output, 5024 .disable_video_output = dsi_disable_video_output, 5025 5026 .update = dsi_update, 5027 5028 .enable_te = dsi_enable_te, 5029 5030 .request_vc = dsi_request_vc, 5031 .set_vc_id = dsi_set_vc_id, 5032 .release_vc = dsi_release_vc, 5033 5034 .dcs_write = dsi_vc_dcs_write, 5035 .dcs_write_nosync = dsi_vc_dcs_write_nosync, 5036 .dcs_read = dsi_vc_dcs_read, 5037 5038 .gen_write = dsi_vc_generic_write, 5039 .gen_write_nosync = dsi_vc_generic_write_nosync, 5040 .gen_read = dsi_vc_generic_read, 5041 5042 .bta_sync = dsi_vc_send_bta_sync, 5043 5044 .set_max_rx_packet_size = dsi_vc_set_max_rx_packet_size, 5045 }; 5046 5047 static void dsi_init_output(struct platform_device *dsidev) 5048 { 5049 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 5050 struct omap_dss_device *out = &dsi->output; 5051 5052 out->dev = &dsidev->dev; 5053 out->id = dsi->module_id == 0 ? 5054 OMAP_DSS_OUTPUT_DSI1 : OMAP_DSS_OUTPUT_DSI2; 5055 5056 out->output_type = OMAP_DISPLAY_TYPE_DSI; 5057 out->name = dsi->module_id == 0 ? "dsi.0" : "dsi.1"; 5058 out->dispc_channel = dsi_get_channel(dsi->module_id); 5059 out->ops.dsi = &dsi_ops; 5060 out->owner = THIS_MODULE; 5061 5062 omapdss_register_output(out); 5063 } 5064 5065 static void dsi_uninit_output(struct platform_device *dsidev) 5066 { 5067 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 5068 struct omap_dss_device *out = &dsi->output; 5069 5070 omapdss_unregister_output(out); 5071 } 5072 5073 static int dsi_probe_of(struct platform_device *pdev) 5074 { 5075 struct device_node *node = pdev->dev.of_node; 5076 struct dsi_data *dsi = dsi_get_dsidrv_data(pdev); 5077 struct property *prop; 5078 u32 lane_arr[10]; 5079 int len, num_pins; 5080 int r, i; 5081 struct device_node *ep; 5082 struct omap_dsi_pin_config pin_cfg; 5083 5084 ep = omapdss_of_get_first_endpoint(node); 5085 if (!ep) 5086 return 0; 5087 5088 prop = of_find_property(ep, "lanes", &len); 5089 if (prop == NULL) { 5090 dev_err(&pdev->dev, "failed to find lane data\n"); 5091 r = -EINVAL; 5092 goto err; 5093 } 5094 5095 num_pins = len / sizeof(u32); 5096 5097 if (num_pins < 4 || num_pins % 2 != 0 || 5098 num_pins > dsi->num_lanes_supported * 2) { 5099 dev_err(&pdev->dev, "bad number of lanes\n"); 5100 r = -EINVAL; 5101 goto err; 5102 } 5103 5104 r = of_property_read_u32_array(ep, "lanes", lane_arr, num_pins); 5105 if (r) { 5106 dev_err(&pdev->dev, "failed to read lane data\n"); 5107 goto err; 5108 } 5109 5110 pin_cfg.num_pins = num_pins; 5111 for (i = 0; i < num_pins; ++i) 5112 pin_cfg.pins[i] = (int)lane_arr[i]; 5113 5114 r = dsi_configure_pins(&dsi->output, &pin_cfg); 5115 if (r) { 5116 dev_err(&pdev->dev, "failed to configure pins"); 5117 goto err; 5118 } 5119 5120 of_node_put(ep); 5121 5122 return 0; 5123 5124 err: 5125 of_node_put(ep); 5126 return r; 5127 } 5128 5129 static const struct dss_pll_ops dsi_pll_ops = { 5130 .enable = dsi_pll_enable, 5131 .disable = dsi_pll_disable, 5132 .set_config = dss_pll_write_config_type_a, 5133 }; 5134 5135 static const struct dss_pll_hw dss_omap3_dsi_pll_hw = { 5136 .n_max = (1 << 7) - 1, 5137 .m_max = (1 << 11) - 1, 5138 .mX_max = (1 << 4) - 1, 5139 .fint_min = 750000, 5140 .fint_max = 2100000, 5141 .clkdco_low = 1000000000, 5142 .clkdco_max = 1800000000, 5143 5144 .n_msb = 7, 5145 .n_lsb = 1, 5146 .m_msb = 18, 5147 .m_lsb = 8, 5148 5149 .mX_msb[0] = 22, 5150 .mX_lsb[0] = 19, 5151 .mX_msb[1] = 26, 5152 .mX_lsb[1] = 23, 5153 5154 .has_stopmode = true, 5155 .has_freqsel = true, 5156 .has_selfreqdco = false, 5157 .has_refsel = false, 5158 }; 5159 5160 static const struct dss_pll_hw dss_omap4_dsi_pll_hw = { 5161 .n_max = (1 << 8) - 1, 5162 .m_max = (1 << 12) - 1, 5163 .mX_max = (1 << 5) - 1, 5164 .fint_min = 500000, 5165 .fint_max = 2500000, 5166 .clkdco_low = 1000000000, 5167 .clkdco_max = 1800000000, 5168 5169 .n_msb = 8, 5170 .n_lsb = 1, 5171 .m_msb = 20, 5172 .m_lsb = 9, 5173 5174 .mX_msb[0] = 25, 5175 .mX_lsb[0] = 21, 5176 .mX_msb[1] = 30, 5177 .mX_lsb[1] = 26, 5178 5179 .has_stopmode = true, 5180 .has_freqsel = false, 5181 .has_selfreqdco = false, 5182 .has_refsel = false, 5183 }; 5184 5185 static const struct dss_pll_hw dss_omap5_dsi_pll_hw = { 5186 .n_max = (1 << 8) - 1, 5187 .m_max = (1 << 12) - 1, 5188 .mX_max = (1 << 5) - 1, 5189 .fint_min = 150000, 5190 .fint_max = 52000000, 5191 .clkdco_low = 1000000000, 5192 .clkdco_max = 1800000000, 5193 5194 .n_msb = 8, 5195 .n_lsb = 1, 5196 .m_msb = 20, 5197 .m_lsb = 9, 5198 5199 .mX_msb[0] = 25, 5200 .mX_lsb[0] = 21, 5201 .mX_msb[1] = 30, 5202 .mX_lsb[1] = 26, 5203 5204 .has_stopmode = true, 5205 .has_freqsel = false, 5206 .has_selfreqdco = true, 5207 .has_refsel = true, 5208 }; 5209 5210 static int dsi_init_pll_data(struct platform_device *dsidev) 5211 { 5212 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 5213 struct dss_pll *pll = &dsi->pll; 5214 struct clk *clk; 5215 int r; 5216 5217 clk = devm_clk_get(&dsidev->dev, "sys_clk"); 5218 if (IS_ERR(clk)) { 5219 DSSERR("can't get sys_clk\n"); 5220 return PTR_ERR(clk); 5221 } 5222 5223 pll->name = dsi->module_id == 0 ? "dsi0" : "dsi1"; 5224 pll->id = dsi->module_id == 0 ? DSS_PLL_DSI1 : DSS_PLL_DSI2; 5225 pll->clkin = clk; 5226 pll->base = dsi->pll_base; 5227 5228 switch (omapdss_get_version()) { 5229 case OMAPDSS_VER_OMAP34xx_ES1: 5230 case OMAPDSS_VER_OMAP34xx_ES3: 5231 case OMAPDSS_VER_OMAP3630: 5232 case OMAPDSS_VER_AM35xx: 5233 pll->hw = &dss_omap3_dsi_pll_hw; 5234 break; 5235 5236 case OMAPDSS_VER_OMAP4430_ES1: 5237 case OMAPDSS_VER_OMAP4430_ES2: 5238 case OMAPDSS_VER_OMAP4: 5239 pll->hw = &dss_omap4_dsi_pll_hw; 5240 break; 5241 5242 case OMAPDSS_VER_OMAP5: 5243 pll->hw = &dss_omap5_dsi_pll_hw; 5244 break; 5245 5246 default: 5247 return -ENODEV; 5248 } 5249 5250 pll->ops = &dsi_pll_ops; 5251 5252 r = dss_pll_register(pll); 5253 if (r) 5254 return r; 5255 5256 return 0; 5257 } 5258 5259 /* DSI1 HW IP initialisation */ 5260 static int dsi_bind(struct device *dev, struct device *master, void *data) 5261 { 5262 struct platform_device *dsidev = to_platform_device(dev); 5263 u32 rev; 5264 int r, i; 5265 struct dsi_data *dsi; 5266 struct resource *dsi_mem; 5267 struct resource *res; 5268 struct resource temp_res; 5269 5270 dsi = devm_kzalloc(&dsidev->dev, sizeof(*dsi), GFP_KERNEL); 5271 if (!dsi) 5272 return -ENOMEM; 5273 5274 dsi->pdev = dsidev; 5275 dev_set_drvdata(&dsidev->dev, dsi); 5276 5277 spin_lock_init(&dsi->irq_lock); 5278 spin_lock_init(&dsi->errors_lock); 5279 dsi->errors = 0; 5280 5281 #ifdef CONFIG_FB_OMAP2_DSS_COLLECT_IRQ_STATS 5282 spin_lock_init(&dsi->irq_stats_lock); 5283 dsi->irq_stats.last_reset = jiffies; 5284 #endif 5285 5286 mutex_init(&dsi->lock); 5287 sema_init(&dsi->bus_lock, 1); 5288 5289 INIT_DEFERRABLE_WORK(&dsi->framedone_timeout_work, 5290 dsi_framedone_timeout_work_callback); 5291 5292 #ifdef DSI_CATCH_MISSING_TE 5293 timer_setup(&dsi->te_timer, dsi_te_timeout, 0); 5294 #endif 5295 5296 res = platform_get_resource_byname(dsidev, IORESOURCE_MEM, "proto"); 5297 if (!res) { 5298 res = platform_get_resource(dsidev, IORESOURCE_MEM, 0); 5299 if (!res) { 5300 DSSERR("can't get IORESOURCE_MEM DSI\n"); 5301 return -EINVAL; 5302 } 5303 5304 temp_res.start = res->start; 5305 temp_res.end = temp_res.start + DSI_PROTO_SZ - 1; 5306 res = &temp_res; 5307 } 5308 5309 dsi_mem = res; 5310 5311 dsi->proto_base = devm_ioremap(&dsidev->dev, res->start, 5312 resource_size(res)); 5313 if (!dsi->proto_base) { 5314 DSSERR("can't ioremap DSI protocol engine\n"); 5315 return -ENOMEM; 5316 } 5317 5318 res = platform_get_resource_byname(dsidev, IORESOURCE_MEM, "phy"); 5319 if (!res) { 5320 res = platform_get_resource(dsidev, IORESOURCE_MEM, 0); 5321 if (!res) { 5322 DSSERR("can't get IORESOURCE_MEM DSI\n"); 5323 return -EINVAL; 5324 } 5325 5326 temp_res.start = res->start + DSI_PHY_OFFSET; 5327 temp_res.end = temp_res.start + DSI_PHY_SZ - 1; 5328 res = &temp_res; 5329 } 5330 5331 dsi->phy_base = devm_ioremap(&dsidev->dev, res->start, 5332 resource_size(res)); 5333 if (!dsi->phy_base) { 5334 DSSERR("can't ioremap DSI PHY\n"); 5335 return -ENOMEM; 5336 } 5337 5338 res = platform_get_resource_byname(dsidev, IORESOURCE_MEM, "pll"); 5339 if (!res) { 5340 res = platform_get_resource(dsidev, IORESOURCE_MEM, 0); 5341 if (!res) { 5342 DSSERR("can't get IORESOURCE_MEM DSI\n"); 5343 return -EINVAL; 5344 } 5345 5346 temp_res.start = res->start + DSI_PLL_OFFSET; 5347 temp_res.end = temp_res.start + DSI_PLL_SZ - 1; 5348 res = &temp_res; 5349 } 5350 5351 dsi->pll_base = devm_ioremap(&dsidev->dev, res->start, 5352 resource_size(res)); 5353 if (!dsi->pll_base) { 5354 DSSERR("can't ioremap DSI PLL\n"); 5355 return -ENOMEM; 5356 } 5357 5358 dsi->irq = platform_get_irq(dsi->pdev, 0); 5359 if (dsi->irq < 0) { 5360 DSSERR("platform_get_irq failed\n"); 5361 return -ENODEV; 5362 } 5363 5364 r = devm_request_irq(&dsidev->dev, dsi->irq, omap_dsi_irq_handler, 5365 IRQF_SHARED, dev_name(&dsidev->dev), dsi->pdev); 5366 if (r < 0) { 5367 DSSERR("request_irq failed\n"); 5368 return r; 5369 } 5370 5371 if (dsidev->dev.of_node) { 5372 const struct of_device_id *match; 5373 const struct dsi_module_id_data *d; 5374 5375 match = of_match_node(dsi_of_match, dsidev->dev.of_node); 5376 if (!match) { 5377 DSSERR("unsupported DSI module\n"); 5378 return -ENODEV; 5379 } 5380 5381 d = match->data; 5382 5383 while (d->address != 0 && d->address != dsi_mem->start) 5384 d++; 5385 5386 if (d->address == 0) { 5387 DSSERR("unsupported DSI module\n"); 5388 return -ENODEV; 5389 } 5390 5391 dsi->module_id = d->id; 5392 } else { 5393 dsi->module_id = dsidev->id; 5394 } 5395 5396 /* DSI VCs initialization */ 5397 for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) { 5398 dsi->vc[i].source = DSI_VC_SOURCE_L4; 5399 dsi->vc[i].dssdev = NULL; 5400 dsi->vc[i].vc_id = 0; 5401 } 5402 5403 r = dsi_get_clocks(dsidev); 5404 if (r) 5405 return r; 5406 5407 dsi_init_pll_data(dsidev); 5408 5409 pm_runtime_enable(&dsidev->dev); 5410 5411 r = dsi_runtime_get(dsidev); 5412 if (r) 5413 goto err_runtime_get; 5414 5415 rev = dsi_read_reg(dsidev, DSI_REVISION); 5416 dev_dbg(&dsidev->dev, "OMAP DSI rev %d.%d\n", 5417 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0)); 5418 5419 /* DSI on OMAP3 doesn't have register DSI_GNQ, set number 5420 * of data to 3 by default */ 5421 if (dss_has_feature(FEAT_DSI_GNQ)) 5422 /* NB_DATA_LANES */ 5423 dsi->num_lanes_supported = 1 + REG_GET(dsidev, DSI_GNQ, 11, 9); 5424 else 5425 dsi->num_lanes_supported = 3; 5426 5427 dsi->line_buffer_size = dsi_get_line_buf_size(dsidev); 5428 5429 dsi_init_output(dsidev); 5430 5431 if (dsidev->dev.of_node) { 5432 r = dsi_probe_of(dsidev); 5433 if (r) { 5434 DSSERR("Invalid DSI DT data\n"); 5435 goto err_probe_of; 5436 } 5437 5438 r = of_platform_populate(dsidev->dev.of_node, NULL, NULL, 5439 &dsidev->dev); 5440 if (r) 5441 DSSERR("Failed to populate DSI child devices: %d\n", r); 5442 } 5443 5444 dsi_runtime_put(dsidev); 5445 5446 if (dsi->module_id == 0) 5447 dss_debugfs_create_file("dsi1_regs", dsi1_dump_regs); 5448 else if (dsi->module_id == 1) 5449 dss_debugfs_create_file("dsi2_regs", dsi2_dump_regs); 5450 5451 #ifdef CONFIG_FB_OMAP2_DSS_COLLECT_IRQ_STATS 5452 if (dsi->module_id == 0) 5453 dss_debugfs_create_file("dsi1_irqs", dsi1_dump_irqs); 5454 else if (dsi->module_id == 1) 5455 dss_debugfs_create_file("dsi2_irqs", dsi2_dump_irqs); 5456 #endif 5457 5458 return 0; 5459 5460 err_probe_of: 5461 dsi_uninit_output(dsidev); 5462 dsi_runtime_put(dsidev); 5463 5464 err_runtime_get: 5465 pm_runtime_disable(&dsidev->dev); 5466 return r; 5467 } 5468 5469 static void dsi_unbind(struct device *dev, struct device *master, void *data) 5470 { 5471 struct platform_device *dsidev = to_platform_device(dev); 5472 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 5473 5474 of_platform_depopulate(&dsidev->dev); 5475 5476 WARN_ON(dsi->scp_clk_refcount > 0); 5477 5478 dss_pll_unregister(&dsi->pll); 5479 5480 dsi_uninit_output(dsidev); 5481 5482 pm_runtime_disable(&dsidev->dev); 5483 5484 if (dsi->vdds_dsi_reg != NULL && dsi->vdds_dsi_enabled) { 5485 regulator_disable(dsi->vdds_dsi_reg); 5486 dsi->vdds_dsi_enabled = false; 5487 } 5488 } 5489 5490 static const struct component_ops dsi_component_ops = { 5491 .bind = dsi_bind, 5492 .unbind = dsi_unbind, 5493 }; 5494 5495 static int dsi_probe(struct platform_device *pdev) 5496 { 5497 return component_add(&pdev->dev, &dsi_component_ops); 5498 } 5499 5500 static int dsi_remove(struct platform_device *pdev) 5501 { 5502 component_del(&pdev->dev, &dsi_component_ops); 5503 return 0; 5504 } 5505 5506 static int dsi_runtime_suspend(struct device *dev) 5507 { 5508 struct platform_device *pdev = to_platform_device(dev); 5509 struct dsi_data *dsi = dsi_get_dsidrv_data(pdev); 5510 5511 dsi->is_enabled = false; 5512 /* ensure the irq handler sees the is_enabled value */ 5513 smp_wmb(); 5514 /* wait for current handler to finish before turning the DSI off */ 5515 synchronize_irq(dsi->irq); 5516 5517 dispc_runtime_put(); 5518 5519 return 0; 5520 } 5521 5522 static int dsi_runtime_resume(struct device *dev) 5523 { 5524 struct platform_device *pdev = to_platform_device(dev); 5525 struct dsi_data *dsi = dsi_get_dsidrv_data(pdev); 5526 int r; 5527 5528 r = dispc_runtime_get(); 5529 if (r) 5530 return r; 5531 5532 dsi->is_enabled = true; 5533 /* ensure the irq handler sees the is_enabled value */ 5534 smp_wmb(); 5535 5536 return 0; 5537 } 5538 5539 static const struct dev_pm_ops dsi_pm_ops = { 5540 .runtime_suspend = dsi_runtime_suspend, 5541 .runtime_resume = dsi_runtime_resume, 5542 }; 5543 5544 static const struct dsi_module_id_data dsi_of_data_omap3[] = { 5545 { .address = 0x4804fc00, .id = 0, }, 5546 { }, 5547 }; 5548 5549 static const struct dsi_module_id_data dsi_of_data_omap4[] = { 5550 { .address = 0x58004000, .id = 0, }, 5551 { .address = 0x58005000, .id = 1, }, 5552 { }, 5553 }; 5554 5555 static const struct dsi_module_id_data dsi_of_data_omap5[] = { 5556 { .address = 0x58004000, .id = 0, }, 5557 { .address = 0x58009000, .id = 1, }, 5558 { }, 5559 }; 5560 5561 static const struct of_device_id dsi_of_match[] = { 5562 { .compatible = "ti,omap3-dsi", .data = dsi_of_data_omap3, }, 5563 { .compatible = "ti,omap4-dsi", .data = dsi_of_data_omap4, }, 5564 { .compatible = "ti,omap5-dsi", .data = dsi_of_data_omap5, }, 5565 {}, 5566 }; 5567 5568 static struct platform_driver omap_dsihw_driver = { 5569 .probe = dsi_probe, 5570 .remove = dsi_remove, 5571 .driver = { 5572 .name = "omapdss_dsi", 5573 .pm = &dsi_pm_ops, 5574 .of_match_table = dsi_of_match, 5575 .suppress_bind_attrs = true, 5576 }, 5577 }; 5578 5579 int __init dsi_init_platform_driver(void) 5580 { 5581 return platform_driver_register(&omap_dsihw_driver); 5582 } 5583 5584 void dsi_uninit_platform_driver(void) 5585 { 5586 platform_driver_unregister(&omap_dsihw_driver); 5587 } 5588