1 /* 2 * linux/drivers/video/omap2/dss/dsi.c 3 * 4 * Copyright (C) 2009 Nokia Corporation 5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License version 2 as published by 9 * the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #define DSS_SUBSYS_NAME "DSI" 21 22 #include <linux/kernel.h> 23 #include <linux/io.h> 24 #include <linux/clk.h> 25 #include <linux/device.h> 26 #include <linux/err.h> 27 #include <linux/interrupt.h> 28 #include <linux/delay.h> 29 #include <linux/mutex.h> 30 #include <linux/module.h> 31 #include <linux/semaphore.h> 32 #include <linux/seq_file.h> 33 #include <linux/platform_device.h> 34 #include <linux/regulator/consumer.h> 35 #include <linux/wait.h> 36 #include <linux/workqueue.h> 37 #include <linux/sched.h> 38 #include <linux/slab.h> 39 #include <linux/debugfs.h> 40 #include <linux/pm_runtime.h> 41 #include <linux/of.h> 42 #include <linux/of_platform.h> 43 #include <linux/component.h> 44 45 #include <video/omapfb_dss.h> 46 #include <video/mipi_display.h> 47 48 #include "dss.h" 49 #include "dss_features.h" 50 51 #define DSI_CATCH_MISSING_TE 52 53 struct dsi_reg { u16 module; u16 idx; }; 54 55 #define DSI_REG(mod, idx) ((const struct dsi_reg) { mod, idx }) 56 57 /* DSI Protocol Engine */ 58 59 #define DSI_PROTO 0 60 #define DSI_PROTO_SZ 0x200 61 62 #define DSI_REVISION DSI_REG(DSI_PROTO, 0x0000) 63 #define DSI_SYSCONFIG DSI_REG(DSI_PROTO, 0x0010) 64 #define DSI_SYSSTATUS DSI_REG(DSI_PROTO, 0x0014) 65 #define DSI_IRQSTATUS DSI_REG(DSI_PROTO, 0x0018) 66 #define DSI_IRQENABLE DSI_REG(DSI_PROTO, 0x001C) 67 #define DSI_CTRL DSI_REG(DSI_PROTO, 0x0040) 68 #define DSI_GNQ DSI_REG(DSI_PROTO, 0x0044) 69 #define DSI_COMPLEXIO_CFG1 DSI_REG(DSI_PROTO, 0x0048) 70 #define DSI_COMPLEXIO_IRQ_STATUS DSI_REG(DSI_PROTO, 0x004C) 71 #define DSI_COMPLEXIO_IRQ_ENABLE DSI_REG(DSI_PROTO, 0x0050) 72 #define DSI_CLK_CTRL DSI_REG(DSI_PROTO, 0x0054) 73 #define DSI_TIMING1 DSI_REG(DSI_PROTO, 0x0058) 74 #define DSI_TIMING2 DSI_REG(DSI_PROTO, 0x005C) 75 #define DSI_VM_TIMING1 DSI_REG(DSI_PROTO, 0x0060) 76 #define DSI_VM_TIMING2 DSI_REG(DSI_PROTO, 0x0064) 77 #define DSI_VM_TIMING3 DSI_REG(DSI_PROTO, 0x0068) 78 #define DSI_CLK_TIMING DSI_REG(DSI_PROTO, 0x006C) 79 #define DSI_TX_FIFO_VC_SIZE DSI_REG(DSI_PROTO, 0x0070) 80 #define DSI_RX_FIFO_VC_SIZE DSI_REG(DSI_PROTO, 0x0074) 81 #define DSI_COMPLEXIO_CFG2 DSI_REG(DSI_PROTO, 0x0078) 82 #define DSI_RX_FIFO_VC_FULLNESS DSI_REG(DSI_PROTO, 0x007C) 83 #define DSI_VM_TIMING4 DSI_REG(DSI_PROTO, 0x0080) 84 #define DSI_TX_FIFO_VC_EMPTINESS DSI_REG(DSI_PROTO, 0x0084) 85 #define DSI_VM_TIMING5 DSI_REG(DSI_PROTO, 0x0088) 86 #define DSI_VM_TIMING6 DSI_REG(DSI_PROTO, 0x008C) 87 #define DSI_VM_TIMING7 DSI_REG(DSI_PROTO, 0x0090) 88 #define DSI_STOPCLK_TIMING DSI_REG(DSI_PROTO, 0x0094) 89 #define DSI_VC_CTRL(n) DSI_REG(DSI_PROTO, 0x0100 + (n * 0x20)) 90 #define DSI_VC_TE(n) DSI_REG(DSI_PROTO, 0x0104 + (n * 0x20)) 91 #define DSI_VC_LONG_PACKET_HEADER(n) DSI_REG(DSI_PROTO, 0x0108 + (n * 0x20)) 92 #define DSI_VC_LONG_PACKET_PAYLOAD(n) DSI_REG(DSI_PROTO, 0x010C + (n * 0x20)) 93 #define DSI_VC_SHORT_PACKET_HEADER(n) DSI_REG(DSI_PROTO, 0x0110 + (n * 0x20)) 94 #define DSI_VC_IRQSTATUS(n) DSI_REG(DSI_PROTO, 0x0118 + (n * 0x20)) 95 #define DSI_VC_IRQENABLE(n) DSI_REG(DSI_PROTO, 0x011C + (n * 0x20)) 96 97 /* DSIPHY_SCP */ 98 99 #define DSI_PHY 1 100 #define DSI_PHY_OFFSET 0x200 101 #define DSI_PHY_SZ 0x40 102 103 #define DSI_DSIPHY_CFG0 DSI_REG(DSI_PHY, 0x0000) 104 #define DSI_DSIPHY_CFG1 DSI_REG(DSI_PHY, 0x0004) 105 #define DSI_DSIPHY_CFG2 DSI_REG(DSI_PHY, 0x0008) 106 #define DSI_DSIPHY_CFG5 DSI_REG(DSI_PHY, 0x0014) 107 #define DSI_DSIPHY_CFG10 DSI_REG(DSI_PHY, 0x0028) 108 109 /* DSI_PLL_CTRL_SCP */ 110 111 #define DSI_PLL 2 112 #define DSI_PLL_OFFSET 0x300 113 #define DSI_PLL_SZ 0x20 114 115 #define DSI_PLL_CONTROL DSI_REG(DSI_PLL, 0x0000) 116 #define DSI_PLL_STATUS DSI_REG(DSI_PLL, 0x0004) 117 #define DSI_PLL_GO DSI_REG(DSI_PLL, 0x0008) 118 #define DSI_PLL_CONFIGURATION1 DSI_REG(DSI_PLL, 0x000C) 119 #define DSI_PLL_CONFIGURATION2 DSI_REG(DSI_PLL, 0x0010) 120 121 #define REG_GET(dsidev, idx, start, end) \ 122 FLD_GET(dsi_read_reg(dsidev, idx), start, end) 123 124 #define REG_FLD_MOD(dsidev, idx, val, start, end) \ 125 dsi_write_reg(dsidev, idx, FLD_MOD(dsi_read_reg(dsidev, idx), val, start, end)) 126 127 /* Global interrupts */ 128 #define DSI_IRQ_VC0 (1 << 0) 129 #define DSI_IRQ_VC1 (1 << 1) 130 #define DSI_IRQ_VC2 (1 << 2) 131 #define DSI_IRQ_VC3 (1 << 3) 132 #define DSI_IRQ_WAKEUP (1 << 4) 133 #define DSI_IRQ_RESYNC (1 << 5) 134 #define DSI_IRQ_PLL_LOCK (1 << 7) 135 #define DSI_IRQ_PLL_UNLOCK (1 << 8) 136 #define DSI_IRQ_PLL_RECALL (1 << 9) 137 #define DSI_IRQ_COMPLEXIO_ERR (1 << 10) 138 #define DSI_IRQ_HS_TX_TIMEOUT (1 << 14) 139 #define DSI_IRQ_LP_RX_TIMEOUT (1 << 15) 140 #define DSI_IRQ_TE_TRIGGER (1 << 16) 141 #define DSI_IRQ_ACK_TRIGGER (1 << 17) 142 #define DSI_IRQ_SYNC_LOST (1 << 18) 143 #define DSI_IRQ_LDO_POWER_GOOD (1 << 19) 144 #define DSI_IRQ_TA_TIMEOUT (1 << 20) 145 #define DSI_IRQ_ERROR_MASK \ 146 (DSI_IRQ_HS_TX_TIMEOUT | DSI_IRQ_LP_RX_TIMEOUT | DSI_IRQ_SYNC_LOST | \ 147 DSI_IRQ_TA_TIMEOUT) 148 #define DSI_IRQ_CHANNEL_MASK 0xf 149 150 /* Virtual channel interrupts */ 151 #define DSI_VC_IRQ_CS (1 << 0) 152 #define DSI_VC_IRQ_ECC_CORR (1 << 1) 153 #define DSI_VC_IRQ_PACKET_SENT (1 << 2) 154 #define DSI_VC_IRQ_FIFO_TX_OVF (1 << 3) 155 #define DSI_VC_IRQ_FIFO_RX_OVF (1 << 4) 156 #define DSI_VC_IRQ_BTA (1 << 5) 157 #define DSI_VC_IRQ_ECC_NO_CORR (1 << 6) 158 #define DSI_VC_IRQ_FIFO_TX_UDF (1 << 7) 159 #define DSI_VC_IRQ_PP_BUSY_CHANGE (1 << 8) 160 #define DSI_VC_IRQ_ERROR_MASK \ 161 (DSI_VC_IRQ_CS | DSI_VC_IRQ_ECC_CORR | DSI_VC_IRQ_FIFO_TX_OVF | \ 162 DSI_VC_IRQ_FIFO_RX_OVF | DSI_VC_IRQ_ECC_NO_CORR | \ 163 DSI_VC_IRQ_FIFO_TX_UDF) 164 165 /* ComplexIO interrupts */ 166 #define DSI_CIO_IRQ_ERRSYNCESC1 (1 << 0) 167 #define DSI_CIO_IRQ_ERRSYNCESC2 (1 << 1) 168 #define DSI_CIO_IRQ_ERRSYNCESC3 (1 << 2) 169 #define DSI_CIO_IRQ_ERRSYNCESC4 (1 << 3) 170 #define DSI_CIO_IRQ_ERRSYNCESC5 (1 << 4) 171 #define DSI_CIO_IRQ_ERRESC1 (1 << 5) 172 #define DSI_CIO_IRQ_ERRESC2 (1 << 6) 173 #define DSI_CIO_IRQ_ERRESC3 (1 << 7) 174 #define DSI_CIO_IRQ_ERRESC4 (1 << 8) 175 #define DSI_CIO_IRQ_ERRESC5 (1 << 9) 176 #define DSI_CIO_IRQ_ERRCONTROL1 (1 << 10) 177 #define DSI_CIO_IRQ_ERRCONTROL2 (1 << 11) 178 #define DSI_CIO_IRQ_ERRCONTROL3 (1 << 12) 179 #define DSI_CIO_IRQ_ERRCONTROL4 (1 << 13) 180 #define DSI_CIO_IRQ_ERRCONTROL5 (1 << 14) 181 #define DSI_CIO_IRQ_STATEULPS1 (1 << 15) 182 #define DSI_CIO_IRQ_STATEULPS2 (1 << 16) 183 #define DSI_CIO_IRQ_STATEULPS3 (1 << 17) 184 #define DSI_CIO_IRQ_STATEULPS4 (1 << 18) 185 #define DSI_CIO_IRQ_STATEULPS5 (1 << 19) 186 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_1 (1 << 20) 187 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_1 (1 << 21) 188 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_2 (1 << 22) 189 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_2 (1 << 23) 190 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_3 (1 << 24) 191 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_3 (1 << 25) 192 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_4 (1 << 26) 193 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_4 (1 << 27) 194 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_5 (1 << 28) 195 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_5 (1 << 29) 196 #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL0 (1 << 30) 197 #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL1 (1 << 31) 198 #define DSI_CIO_IRQ_ERROR_MASK \ 199 (DSI_CIO_IRQ_ERRSYNCESC1 | DSI_CIO_IRQ_ERRSYNCESC2 | \ 200 DSI_CIO_IRQ_ERRSYNCESC3 | DSI_CIO_IRQ_ERRSYNCESC4 | \ 201 DSI_CIO_IRQ_ERRSYNCESC5 | \ 202 DSI_CIO_IRQ_ERRESC1 | DSI_CIO_IRQ_ERRESC2 | \ 203 DSI_CIO_IRQ_ERRESC3 | DSI_CIO_IRQ_ERRESC4 | \ 204 DSI_CIO_IRQ_ERRESC5 | \ 205 DSI_CIO_IRQ_ERRCONTROL1 | DSI_CIO_IRQ_ERRCONTROL2 | \ 206 DSI_CIO_IRQ_ERRCONTROL3 | DSI_CIO_IRQ_ERRCONTROL4 | \ 207 DSI_CIO_IRQ_ERRCONTROL5 | \ 208 DSI_CIO_IRQ_ERRCONTENTIONLP0_1 | DSI_CIO_IRQ_ERRCONTENTIONLP1_1 | \ 209 DSI_CIO_IRQ_ERRCONTENTIONLP0_2 | DSI_CIO_IRQ_ERRCONTENTIONLP1_2 | \ 210 DSI_CIO_IRQ_ERRCONTENTIONLP0_3 | DSI_CIO_IRQ_ERRCONTENTIONLP1_3 | \ 211 DSI_CIO_IRQ_ERRCONTENTIONLP0_4 | DSI_CIO_IRQ_ERRCONTENTIONLP1_4 | \ 212 DSI_CIO_IRQ_ERRCONTENTIONLP0_5 | DSI_CIO_IRQ_ERRCONTENTIONLP1_5) 213 214 typedef void (*omap_dsi_isr_t) (void *arg, u32 mask); 215 216 static int dsi_display_init_dispc(struct platform_device *dsidev, 217 struct omap_overlay_manager *mgr); 218 static void dsi_display_uninit_dispc(struct platform_device *dsidev, 219 struct omap_overlay_manager *mgr); 220 221 static int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel); 222 223 /* DSI PLL HSDIV indices */ 224 #define HSDIV_DISPC 0 225 #define HSDIV_DSI 1 226 227 #define DSI_MAX_NR_ISRS 2 228 #define DSI_MAX_NR_LANES 5 229 230 enum dsi_lane_function { 231 DSI_LANE_UNUSED = 0, 232 DSI_LANE_CLK, 233 DSI_LANE_DATA1, 234 DSI_LANE_DATA2, 235 DSI_LANE_DATA3, 236 DSI_LANE_DATA4, 237 }; 238 239 struct dsi_lane_config { 240 enum dsi_lane_function function; 241 u8 polarity; 242 }; 243 244 struct dsi_isr_data { 245 omap_dsi_isr_t isr; 246 void *arg; 247 u32 mask; 248 }; 249 250 enum fifo_size { 251 DSI_FIFO_SIZE_0 = 0, 252 DSI_FIFO_SIZE_32 = 1, 253 DSI_FIFO_SIZE_64 = 2, 254 DSI_FIFO_SIZE_96 = 3, 255 DSI_FIFO_SIZE_128 = 4, 256 }; 257 258 enum dsi_vc_source { 259 DSI_VC_SOURCE_L4 = 0, 260 DSI_VC_SOURCE_VP, 261 }; 262 263 struct dsi_irq_stats { 264 unsigned long last_reset; 265 unsigned irq_count; 266 unsigned dsi_irqs[32]; 267 unsigned vc_irqs[4][32]; 268 unsigned cio_irqs[32]; 269 }; 270 271 struct dsi_isr_tables { 272 struct dsi_isr_data isr_table[DSI_MAX_NR_ISRS]; 273 struct dsi_isr_data isr_table_vc[4][DSI_MAX_NR_ISRS]; 274 struct dsi_isr_data isr_table_cio[DSI_MAX_NR_ISRS]; 275 }; 276 277 struct dsi_clk_calc_ctx { 278 struct platform_device *dsidev; 279 struct dss_pll *pll; 280 281 /* inputs */ 282 283 const struct omap_dss_dsi_config *config; 284 285 unsigned long req_pck_min, req_pck_nom, req_pck_max; 286 287 /* outputs */ 288 289 struct dss_pll_clock_info dsi_cinfo; 290 struct dispc_clock_info dispc_cinfo; 291 292 struct omap_video_timings dispc_vm; 293 struct omap_dss_dsi_videomode_timings dsi_vm; 294 }; 295 296 struct dsi_lp_clock_info { 297 unsigned long lp_clk; 298 u16 lp_clk_div; 299 }; 300 301 struct dsi_data { 302 struct platform_device *pdev; 303 void __iomem *proto_base; 304 void __iomem *phy_base; 305 void __iomem *pll_base; 306 307 int module_id; 308 309 int irq; 310 311 bool is_enabled; 312 313 struct clk *dss_clk; 314 315 struct dispc_clock_info user_dispc_cinfo; 316 struct dss_pll_clock_info user_dsi_cinfo; 317 318 struct dsi_lp_clock_info user_lp_cinfo; 319 struct dsi_lp_clock_info current_lp_cinfo; 320 321 struct dss_pll pll; 322 323 bool vdds_dsi_enabled; 324 struct regulator *vdds_dsi_reg; 325 326 struct { 327 enum dsi_vc_source source; 328 struct omap_dss_device *dssdev; 329 enum fifo_size tx_fifo_size; 330 enum fifo_size rx_fifo_size; 331 int vc_id; 332 } vc[4]; 333 334 struct mutex lock; 335 struct semaphore bus_lock; 336 337 spinlock_t irq_lock; 338 struct dsi_isr_tables isr_tables; 339 /* space for a copy used by the interrupt handler */ 340 struct dsi_isr_tables isr_tables_copy; 341 342 int update_channel; 343 #ifdef DSI_PERF_MEASURE 344 unsigned update_bytes; 345 #endif 346 347 bool te_enabled; 348 bool ulps_enabled; 349 350 void (*framedone_callback)(int, void *); 351 void *framedone_data; 352 353 struct delayed_work framedone_timeout_work; 354 355 #ifdef DSI_CATCH_MISSING_TE 356 struct timer_list te_timer; 357 #endif 358 359 unsigned long cache_req_pck; 360 unsigned long cache_clk_freq; 361 struct dss_pll_clock_info cache_cinfo; 362 363 u32 errors; 364 spinlock_t errors_lock; 365 #ifdef DSI_PERF_MEASURE 366 ktime_t perf_setup_time; 367 ktime_t perf_start_time; 368 #endif 369 int debug_read; 370 int debug_write; 371 372 #ifdef CONFIG_FB_OMAP2_DSS_COLLECT_IRQ_STATS 373 spinlock_t irq_stats_lock; 374 struct dsi_irq_stats irq_stats; 375 #endif 376 377 unsigned num_lanes_supported; 378 unsigned line_buffer_size; 379 380 struct dsi_lane_config lanes[DSI_MAX_NR_LANES]; 381 unsigned num_lanes_used; 382 383 unsigned scp_clk_refcount; 384 385 struct dss_lcd_mgr_config mgr_config; 386 struct omap_video_timings timings; 387 enum omap_dss_dsi_pixel_format pix_fmt; 388 enum omap_dss_dsi_mode mode; 389 struct omap_dss_dsi_videomode_timings vm_timings; 390 391 struct omap_dss_device output; 392 }; 393 394 struct dsi_packet_sent_handler_data { 395 struct platform_device *dsidev; 396 struct completion *completion; 397 }; 398 399 struct dsi_module_id_data { 400 u32 address; 401 int id; 402 }; 403 404 static const struct of_device_id dsi_of_match[]; 405 406 #ifdef DSI_PERF_MEASURE 407 static bool dsi_perf; 408 module_param(dsi_perf, bool, 0644); 409 #endif 410 411 static inline struct dsi_data *dsi_get_dsidrv_data(struct platform_device *dsidev) 412 { 413 return dev_get_drvdata(&dsidev->dev); 414 } 415 416 static inline struct platform_device *dsi_get_dsidev_from_dssdev(struct omap_dss_device *dssdev) 417 { 418 return to_platform_device(dssdev->dev); 419 } 420 421 static struct platform_device *dsi_get_dsidev_from_id(int module) 422 { 423 struct omap_dss_device *out; 424 enum omap_dss_output_id id; 425 426 switch (module) { 427 case 0: 428 id = OMAP_DSS_OUTPUT_DSI1; 429 break; 430 case 1: 431 id = OMAP_DSS_OUTPUT_DSI2; 432 break; 433 default: 434 return NULL; 435 } 436 437 out = omap_dss_get_output(id); 438 439 return out ? to_platform_device(out->dev) : NULL; 440 } 441 442 static inline void dsi_write_reg(struct platform_device *dsidev, 443 const struct dsi_reg idx, u32 val) 444 { 445 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 446 void __iomem *base; 447 448 switch(idx.module) { 449 case DSI_PROTO: base = dsi->proto_base; break; 450 case DSI_PHY: base = dsi->phy_base; break; 451 case DSI_PLL: base = dsi->pll_base; break; 452 default: return; 453 } 454 455 __raw_writel(val, base + idx.idx); 456 } 457 458 static inline u32 dsi_read_reg(struct platform_device *dsidev, 459 const struct dsi_reg idx) 460 { 461 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 462 void __iomem *base; 463 464 switch(idx.module) { 465 case DSI_PROTO: base = dsi->proto_base; break; 466 case DSI_PHY: base = dsi->phy_base; break; 467 case DSI_PLL: base = dsi->pll_base; break; 468 default: return 0; 469 } 470 471 return __raw_readl(base + idx.idx); 472 } 473 474 static void dsi_bus_lock(struct omap_dss_device *dssdev) 475 { 476 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 477 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 478 479 down(&dsi->bus_lock); 480 } 481 482 static void dsi_bus_unlock(struct omap_dss_device *dssdev) 483 { 484 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 485 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 486 487 up(&dsi->bus_lock); 488 } 489 490 static bool dsi_bus_is_locked(struct platform_device *dsidev) 491 { 492 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 493 494 return dsi->bus_lock.count == 0; 495 } 496 497 static void dsi_completion_handler(void *data, u32 mask) 498 { 499 complete((struct completion *)data); 500 } 501 502 static inline int wait_for_bit_change(struct platform_device *dsidev, 503 const struct dsi_reg idx, int bitnum, int value) 504 { 505 unsigned long timeout; 506 ktime_t wait; 507 int t; 508 509 /* first busyloop to see if the bit changes right away */ 510 t = 100; 511 while (t-- > 0) { 512 if (REG_GET(dsidev, idx, bitnum, bitnum) == value) 513 return value; 514 } 515 516 /* then loop for 500ms, sleeping for 1ms in between */ 517 timeout = jiffies + msecs_to_jiffies(500); 518 while (time_before(jiffies, timeout)) { 519 if (REG_GET(dsidev, idx, bitnum, bitnum) == value) 520 return value; 521 522 wait = ns_to_ktime(1000 * 1000); 523 set_current_state(TASK_UNINTERRUPTIBLE); 524 schedule_hrtimeout(&wait, HRTIMER_MODE_REL); 525 } 526 527 return !value; 528 } 529 530 u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt) 531 { 532 switch (fmt) { 533 case OMAP_DSS_DSI_FMT_RGB888: 534 case OMAP_DSS_DSI_FMT_RGB666: 535 return 24; 536 case OMAP_DSS_DSI_FMT_RGB666_PACKED: 537 return 18; 538 case OMAP_DSS_DSI_FMT_RGB565: 539 return 16; 540 default: 541 BUG(); 542 return 0; 543 } 544 } 545 546 #ifdef DSI_PERF_MEASURE 547 static void dsi_perf_mark_setup(struct platform_device *dsidev) 548 { 549 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 550 dsi->perf_setup_time = ktime_get(); 551 } 552 553 static void dsi_perf_mark_start(struct platform_device *dsidev) 554 { 555 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 556 dsi->perf_start_time = ktime_get(); 557 } 558 559 static void dsi_perf_show(struct platform_device *dsidev, const char *name) 560 { 561 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 562 ktime_t t, setup_time, trans_time; 563 u32 total_bytes; 564 u32 setup_us, trans_us, total_us; 565 566 if (!dsi_perf) 567 return; 568 569 t = ktime_get(); 570 571 setup_time = ktime_sub(dsi->perf_start_time, dsi->perf_setup_time); 572 setup_us = (u32)ktime_to_us(setup_time); 573 if (setup_us == 0) 574 setup_us = 1; 575 576 trans_time = ktime_sub(t, dsi->perf_start_time); 577 trans_us = (u32)ktime_to_us(trans_time); 578 if (trans_us == 0) 579 trans_us = 1; 580 581 total_us = setup_us + trans_us; 582 583 total_bytes = dsi->update_bytes; 584 585 printk(KERN_INFO "DSI(%s): %u us + %u us = %u us (%uHz), " 586 "%u bytes, %u kbytes/sec\n", 587 name, 588 setup_us, 589 trans_us, 590 total_us, 591 1000*1000 / total_us, 592 total_bytes, 593 total_bytes * 1000 / total_us); 594 } 595 #else 596 static inline void dsi_perf_mark_setup(struct platform_device *dsidev) 597 { 598 } 599 600 static inline void dsi_perf_mark_start(struct platform_device *dsidev) 601 { 602 } 603 604 static inline void dsi_perf_show(struct platform_device *dsidev, 605 const char *name) 606 { 607 } 608 #endif 609 610 static int verbose_irq; 611 612 static void print_irq_status(u32 status) 613 { 614 if (status == 0) 615 return; 616 617 if (!verbose_irq && (status & ~DSI_IRQ_CHANNEL_MASK) == 0) 618 return; 619 620 #define PIS(x) (status & DSI_IRQ_##x) ? (#x " ") : "" 621 622 pr_debug("DSI IRQ: 0x%x: %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", 623 status, 624 verbose_irq ? PIS(VC0) : "", 625 verbose_irq ? PIS(VC1) : "", 626 verbose_irq ? PIS(VC2) : "", 627 verbose_irq ? PIS(VC3) : "", 628 PIS(WAKEUP), 629 PIS(RESYNC), 630 PIS(PLL_LOCK), 631 PIS(PLL_UNLOCK), 632 PIS(PLL_RECALL), 633 PIS(COMPLEXIO_ERR), 634 PIS(HS_TX_TIMEOUT), 635 PIS(LP_RX_TIMEOUT), 636 PIS(TE_TRIGGER), 637 PIS(ACK_TRIGGER), 638 PIS(SYNC_LOST), 639 PIS(LDO_POWER_GOOD), 640 PIS(TA_TIMEOUT)); 641 #undef PIS 642 } 643 644 static void print_irq_status_vc(int channel, u32 status) 645 { 646 if (status == 0) 647 return; 648 649 if (!verbose_irq && (status & ~DSI_VC_IRQ_PACKET_SENT) == 0) 650 return; 651 652 #define PIS(x) (status & DSI_VC_IRQ_##x) ? (#x " ") : "" 653 654 pr_debug("DSI VC(%d) IRQ 0x%x: %s%s%s%s%s%s%s%s%s\n", 655 channel, 656 status, 657 PIS(CS), 658 PIS(ECC_CORR), 659 PIS(ECC_NO_CORR), 660 verbose_irq ? PIS(PACKET_SENT) : "", 661 PIS(BTA), 662 PIS(FIFO_TX_OVF), 663 PIS(FIFO_RX_OVF), 664 PIS(FIFO_TX_UDF), 665 PIS(PP_BUSY_CHANGE)); 666 #undef PIS 667 } 668 669 static void print_irq_status_cio(u32 status) 670 { 671 if (status == 0) 672 return; 673 674 #define PIS(x) (status & DSI_CIO_IRQ_##x) ? (#x " ") : "" 675 676 pr_debug("DSI CIO IRQ 0x%x: %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", 677 status, 678 PIS(ERRSYNCESC1), 679 PIS(ERRSYNCESC2), 680 PIS(ERRSYNCESC3), 681 PIS(ERRESC1), 682 PIS(ERRESC2), 683 PIS(ERRESC3), 684 PIS(ERRCONTROL1), 685 PIS(ERRCONTROL2), 686 PIS(ERRCONTROL3), 687 PIS(STATEULPS1), 688 PIS(STATEULPS2), 689 PIS(STATEULPS3), 690 PIS(ERRCONTENTIONLP0_1), 691 PIS(ERRCONTENTIONLP1_1), 692 PIS(ERRCONTENTIONLP0_2), 693 PIS(ERRCONTENTIONLP1_2), 694 PIS(ERRCONTENTIONLP0_3), 695 PIS(ERRCONTENTIONLP1_3), 696 PIS(ULPSACTIVENOT_ALL0), 697 PIS(ULPSACTIVENOT_ALL1)); 698 #undef PIS 699 } 700 701 #ifdef CONFIG_FB_OMAP2_DSS_COLLECT_IRQ_STATS 702 static void dsi_collect_irq_stats(struct platform_device *dsidev, u32 irqstatus, 703 u32 *vcstatus, u32 ciostatus) 704 { 705 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 706 int i; 707 708 spin_lock(&dsi->irq_stats_lock); 709 710 dsi->irq_stats.irq_count++; 711 dss_collect_irq_stats(irqstatus, dsi->irq_stats.dsi_irqs); 712 713 for (i = 0; i < 4; ++i) 714 dss_collect_irq_stats(vcstatus[i], dsi->irq_stats.vc_irqs[i]); 715 716 dss_collect_irq_stats(ciostatus, dsi->irq_stats.cio_irqs); 717 718 spin_unlock(&dsi->irq_stats_lock); 719 } 720 #else 721 #define dsi_collect_irq_stats(dsidev, irqstatus, vcstatus, ciostatus) 722 #endif 723 724 static int debug_irq; 725 726 static void dsi_handle_irq_errors(struct platform_device *dsidev, u32 irqstatus, 727 u32 *vcstatus, u32 ciostatus) 728 { 729 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 730 int i; 731 732 if (irqstatus & DSI_IRQ_ERROR_MASK) { 733 DSSERR("DSI error, irqstatus %x\n", irqstatus); 734 print_irq_status(irqstatus); 735 spin_lock(&dsi->errors_lock); 736 dsi->errors |= irqstatus & DSI_IRQ_ERROR_MASK; 737 spin_unlock(&dsi->errors_lock); 738 } else if (debug_irq) { 739 print_irq_status(irqstatus); 740 } 741 742 for (i = 0; i < 4; ++i) { 743 if (vcstatus[i] & DSI_VC_IRQ_ERROR_MASK) { 744 DSSERR("DSI VC(%d) error, vc irqstatus %x\n", 745 i, vcstatus[i]); 746 print_irq_status_vc(i, vcstatus[i]); 747 } else if (debug_irq) { 748 print_irq_status_vc(i, vcstatus[i]); 749 } 750 } 751 752 if (ciostatus & DSI_CIO_IRQ_ERROR_MASK) { 753 DSSERR("DSI CIO error, cio irqstatus %x\n", ciostatus); 754 print_irq_status_cio(ciostatus); 755 } else if (debug_irq) { 756 print_irq_status_cio(ciostatus); 757 } 758 } 759 760 static void dsi_call_isrs(struct dsi_isr_data *isr_array, 761 unsigned isr_array_size, u32 irqstatus) 762 { 763 struct dsi_isr_data *isr_data; 764 int i; 765 766 for (i = 0; i < isr_array_size; i++) { 767 isr_data = &isr_array[i]; 768 if (isr_data->isr && isr_data->mask & irqstatus) 769 isr_data->isr(isr_data->arg, irqstatus); 770 } 771 } 772 773 static void dsi_handle_isrs(struct dsi_isr_tables *isr_tables, 774 u32 irqstatus, u32 *vcstatus, u32 ciostatus) 775 { 776 int i; 777 778 dsi_call_isrs(isr_tables->isr_table, 779 ARRAY_SIZE(isr_tables->isr_table), 780 irqstatus); 781 782 for (i = 0; i < 4; ++i) { 783 if (vcstatus[i] == 0) 784 continue; 785 dsi_call_isrs(isr_tables->isr_table_vc[i], 786 ARRAY_SIZE(isr_tables->isr_table_vc[i]), 787 vcstatus[i]); 788 } 789 790 if (ciostatus != 0) 791 dsi_call_isrs(isr_tables->isr_table_cio, 792 ARRAY_SIZE(isr_tables->isr_table_cio), 793 ciostatus); 794 } 795 796 static irqreturn_t omap_dsi_irq_handler(int irq, void *arg) 797 { 798 struct platform_device *dsidev; 799 struct dsi_data *dsi; 800 u32 irqstatus, vcstatus[4], ciostatus; 801 int i; 802 803 dsidev = (struct platform_device *) arg; 804 dsi = dsi_get_dsidrv_data(dsidev); 805 806 if (!dsi->is_enabled) 807 return IRQ_NONE; 808 809 spin_lock(&dsi->irq_lock); 810 811 irqstatus = dsi_read_reg(dsidev, DSI_IRQSTATUS); 812 813 /* IRQ is not for us */ 814 if (!irqstatus) { 815 spin_unlock(&dsi->irq_lock); 816 return IRQ_NONE; 817 } 818 819 dsi_write_reg(dsidev, DSI_IRQSTATUS, irqstatus & ~DSI_IRQ_CHANNEL_MASK); 820 /* flush posted write */ 821 dsi_read_reg(dsidev, DSI_IRQSTATUS); 822 823 for (i = 0; i < 4; ++i) { 824 if ((irqstatus & (1 << i)) == 0) { 825 vcstatus[i] = 0; 826 continue; 827 } 828 829 vcstatus[i] = dsi_read_reg(dsidev, DSI_VC_IRQSTATUS(i)); 830 831 dsi_write_reg(dsidev, DSI_VC_IRQSTATUS(i), vcstatus[i]); 832 /* flush posted write */ 833 dsi_read_reg(dsidev, DSI_VC_IRQSTATUS(i)); 834 } 835 836 if (irqstatus & DSI_IRQ_COMPLEXIO_ERR) { 837 ciostatus = dsi_read_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS); 838 839 dsi_write_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS, ciostatus); 840 /* flush posted write */ 841 dsi_read_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS); 842 } else { 843 ciostatus = 0; 844 } 845 846 #ifdef DSI_CATCH_MISSING_TE 847 if (irqstatus & DSI_IRQ_TE_TRIGGER) 848 del_timer(&dsi->te_timer); 849 #endif 850 851 /* make a copy and unlock, so that isrs can unregister 852 * themselves */ 853 memcpy(&dsi->isr_tables_copy, &dsi->isr_tables, 854 sizeof(dsi->isr_tables)); 855 856 spin_unlock(&dsi->irq_lock); 857 858 dsi_handle_isrs(&dsi->isr_tables_copy, irqstatus, vcstatus, ciostatus); 859 860 dsi_handle_irq_errors(dsidev, irqstatus, vcstatus, ciostatus); 861 862 dsi_collect_irq_stats(dsidev, irqstatus, vcstatus, ciostatus); 863 864 return IRQ_HANDLED; 865 } 866 867 /* dsi->irq_lock has to be locked by the caller */ 868 static void _omap_dsi_configure_irqs(struct platform_device *dsidev, 869 struct dsi_isr_data *isr_array, 870 unsigned isr_array_size, u32 default_mask, 871 const struct dsi_reg enable_reg, 872 const struct dsi_reg status_reg) 873 { 874 struct dsi_isr_data *isr_data; 875 u32 mask; 876 u32 old_mask; 877 int i; 878 879 mask = default_mask; 880 881 for (i = 0; i < isr_array_size; i++) { 882 isr_data = &isr_array[i]; 883 884 if (isr_data->isr == NULL) 885 continue; 886 887 mask |= isr_data->mask; 888 } 889 890 old_mask = dsi_read_reg(dsidev, enable_reg); 891 /* clear the irqstatus for newly enabled irqs */ 892 dsi_write_reg(dsidev, status_reg, (mask ^ old_mask) & mask); 893 dsi_write_reg(dsidev, enable_reg, mask); 894 895 /* flush posted writes */ 896 dsi_read_reg(dsidev, enable_reg); 897 dsi_read_reg(dsidev, status_reg); 898 } 899 900 /* dsi->irq_lock has to be locked by the caller */ 901 static void _omap_dsi_set_irqs(struct platform_device *dsidev) 902 { 903 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 904 u32 mask = DSI_IRQ_ERROR_MASK; 905 #ifdef DSI_CATCH_MISSING_TE 906 mask |= DSI_IRQ_TE_TRIGGER; 907 #endif 908 _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table, 909 ARRAY_SIZE(dsi->isr_tables.isr_table), mask, 910 DSI_IRQENABLE, DSI_IRQSTATUS); 911 } 912 913 /* dsi->irq_lock has to be locked by the caller */ 914 static void _omap_dsi_set_irqs_vc(struct platform_device *dsidev, int vc) 915 { 916 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 917 918 _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table_vc[vc], 919 ARRAY_SIZE(dsi->isr_tables.isr_table_vc[vc]), 920 DSI_VC_IRQ_ERROR_MASK, 921 DSI_VC_IRQENABLE(vc), DSI_VC_IRQSTATUS(vc)); 922 } 923 924 /* dsi->irq_lock has to be locked by the caller */ 925 static void _omap_dsi_set_irqs_cio(struct platform_device *dsidev) 926 { 927 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 928 929 _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table_cio, 930 ARRAY_SIZE(dsi->isr_tables.isr_table_cio), 931 DSI_CIO_IRQ_ERROR_MASK, 932 DSI_COMPLEXIO_IRQ_ENABLE, DSI_COMPLEXIO_IRQ_STATUS); 933 } 934 935 static void _dsi_initialize_irq(struct platform_device *dsidev) 936 { 937 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 938 unsigned long flags; 939 int vc; 940 941 spin_lock_irqsave(&dsi->irq_lock, flags); 942 943 memset(&dsi->isr_tables, 0, sizeof(dsi->isr_tables)); 944 945 _omap_dsi_set_irqs(dsidev); 946 for (vc = 0; vc < 4; ++vc) 947 _omap_dsi_set_irqs_vc(dsidev, vc); 948 _omap_dsi_set_irqs_cio(dsidev); 949 950 spin_unlock_irqrestore(&dsi->irq_lock, flags); 951 } 952 953 static int _dsi_register_isr(omap_dsi_isr_t isr, void *arg, u32 mask, 954 struct dsi_isr_data *isr_array, unsigned isr_array_size) 955 { 956 struct dsi_isr_data *isr_data; 957 int free_idx; 958 int i; 959 960 BUG_ON(isr == NULL); 961 962 /* check for duplicate entry and find a free slot */ 963 free_idx = -1; 964 for (i = 0; i < isr_array_size; i++) { 965 isr_data = &isr_array[i]; 966 967 if (isr_data->isr == isr && isr_data->arg == arg && 968 isr_data->mask == mask) { 969 return -EINVAL; 970 } 971 972 if (isr_data->isr == NULL && free_idx == -1) 973 free_idx = i; 974 } 975 976 if (free_idx == -1) 977 return -EBUSY; 978 979 isr_data = &isr_array[free_idx]; 980 isr_data->isr = isr; 981 isr_data->arg = arg; 982 isr_data->mask = mask; 983 984 return 0; 985 } 986 987 static int _dsi_unregister_isr(omap_dsi_isr_t isr, void *arg, u32 mask, 988 struct dsi_isr_data *isr_array, unsigned isr_array_size) 989 { 990 struct dsi_isr_data *isr_data; 991 int i; 992 993 for (i = 0; i < isr_array_size; i++) { 994 isr_data = &isr_array[i]; 995 if (isr_data->isr != isr || isr_data->arg != arg || 996 isr_data->mask != mask) 997 continue; 998 999 isr_data->isr = NULL; 1000 isr_data->arg = NULL; 1001 isr_data->mask = 0; 1002 1003 return 0; 1004 } 1005 1006 return -EINVAL; 1007 } 1008 1009 static int dsi_register_isr(struct platform_device *dsidev, omap_dsi_isr_t isr, 1010 void *arg, u32 mask) 1011 { 1012 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1013 unsigned long flags; 1014 int r; 1015 1016 spin_lock_irqsave(&dsi->irq_lock, flags); 1017 1018 r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table, 1019 ARRAY_SIZE(dsi->isr_tables.isr_table)); 1020 1021 if (r == 0) 1022 _omap_dsi_set_irqs(dsidev); 1023 1024 spin_unlock_irqrestore(&dsi->irq_lock, flags); 1025 1026 return r; 1027 } 1028 1029 static int dsi_unregister_isr(struct platform_device *dsidev, 1030 omap_dsi_isr_t isr, void *arg, u32 mask) 1031 { 1032 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1033 unsigned long flags; 1034 int r; 1035 1036 spin_lock_irqsave(&dsi->irq_lock, flags); 1037 1038 r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table, 1039 ARRAY_SIZE(dsi->isr_tables.isr_table)); 1040 1041 if (r == 0) 1042 _omap_dsi_set_irqs(dsidev); 1043 1044 spin_unlock_irqrestore(&dsi->irq_lock, flags); 1045 1046 return r; 1047 } 1048 1049 static int dsi_register_isr_vc(struct platform_device *dsidev, int channel, 1050 omap_dsi_isr_t isr, void *arg, u32 mask) 1051 { 1052 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1053 unsigned long flags; 1054 int r; 1055 1056 spin_lock_irqsave(&dsi->irq_lock, flags); 1057 1058 r = _dsi_register_isr(isr, arg, mask, 1059 dsi->isr_tables.isr_table_vc[channel], 1060 ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel])); 1061 1062 if (r == 0) 1063 _omap_dsi_set_irqs_vc(dsidev, channel); 1064 1065 spin_unlock_irqrestore(&dsi->irq_lock, flags); 1066 1067 return r; 1068 } 1069 1070 static int dsi_unregister_isr_vc(struct platform_device *dsidev, int channel, 1071 omap_dsi_isr_t isr, void *arg, u32 mask) 1072 { 1073 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1074 unsigned long flags; 1075 int r; 1076 1077 spin_lock_irqsave(&dsi->irq_lock, flags); 1078 1079 r = _dsi_unregister_isr(isr, arg, mask, 1080 dsi->isr_tables.isr_table_vc[channel], 1081 ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel])); 1082 1083 if (r == 0) 1084 _omap_dsi_set_irqs_vc(dsidev, channel); 1085 1086 spin_unlock_irqrestore(&dsi->irq_lock, flags); 1087 1088 return r; 1089 } 1090 1091 static int dsi_register_isr_cio(struct platform_device *dsidev, 1092 omap_dsi_isr_t isr, void *arg, u32 mask) 1093 { 1094 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1095 unsigned long flags; 1096 int r; 1097 1098 spin_lock_irqsave(&dsi->irq_lock, flags); 1099 1100 r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio, 1101 ARRAY_SIZE(dsi->isr_tables.isr_table_cio)); 1102 1103 if (r == 0) 1104 _omap_dsi_set_irqs_cio(dsidev); 1105 1106 spin_unlock_irqrestore(&dsi->irq_lock, flags); 1107 1108 return r; 1109 } 1110 1111 static int dsi_unregister_isr_cio(struct platform_device *dsidev, 1112 omap_dsi_isr_t isr, void *arg, u32 mask) 1113 { 1114 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1115 unsigned long flags; 1116 int r; 1117 1118 spin_lock_irqsave(&dsi->irq_lock, flags); 1119 1120 r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio, 1121 ARRAY_SIZE(dsi->isr_tables.isr_table_cio)); 1122 1123 if (r == 0) 1124 _omap_dsi_set_irqs_cio(dsidev); 1125 1126 spin_unlock_irqrestore(&dsi->irq_lock, flags); 1127 1128 return r; 1129 } 1130 1131 static u32 dsi_get_errors(struct platform_device *dsidev) 1132 { 1133 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1134 unsigned long flags; 1135 u32 e; 1136 spin_lock_irqsave(&dsi->errors_lock, flags); 1137 e = dsi->errors; 1138 dsi->errors = 0; 1139 spin_unlock_irqrestore(&dsi->errors_lock, flags); 1140 return e; 1141 } 1142 1143 static int dsi_runtime_get(struct platform_device *dsidev) 1144 { 1145 int r; 1146 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1147 1148 DSSDBG("dsi_runtime_get\n"); 1149 1150 r = pm_runtime_get_sync(&dsi->pdev->dev); 1151 WARN_ON(r < 0); 1152 return r < 0 ? r : 0; 1153 } 1154 1155 static void dsi_runtime_put(struct platform_device *dsidev) 1156 { 1157 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1158 int r; 1159 1160 DSSDBG("dsi_runtime_put\n"); 1161 1162 r = pm_runtime_put_sync(&dsi->pdev->dev); 1163 WARN_ON(r < 0 && r != -ENOSYS); 1164 } 1165 1166 static int dsi_regulator_init(struct platform_device *dsidev) 1167 { 1168 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1169 struct regulator *vdds_dsi; 1170 int r; 1171 1172 if (dsi->vdds_dsi_reg != NULL) 1173 return 0; 1174 1175 vdds_dsi = devm_regulator_get(&dsi->pdev->dev, "vdd"); 1176 1177 if (IS_ERR(vdds_dsi)) { 1178 if (PTR_ERR(vdds_dsi) != -EPROBE_DEFER) 1179 DSSERR("can't get DSI VDD regulator\n"); 1180 return PTR_ERR(vdds_dsi); 1181 } 1182 1183 r = regulator_set_voltage(vdds_dsi, 1800000, 1800000); 1184 if (r) { 1185 devm_regulator_put(vdds_dsi); 1186 DSSERR("can't set the DSI regulator voltage\n"); 1187 return r; 1188 } 1189 1190 dsi->vdds_dsi_reg = vdds_dsi; 1191 1192 return 0; 1193 } 1194 1195 static void _dsi_print_reset_status(struct platform_device *dsidev) 1196 { 1197 u32 l; 1198 int b0, b1, b2; 1199 1200 /* A dummy read using the SCP interface to any DSIPHY register is 1201 * required after DSIPHY reset to complete the reset of the DSI complex 1202 * I/O. */ 1203 l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5); 1204 1205 if (dss_has_feature(FEAT_DSI_REVERSE_TXCLKESC)) { 1206 b0 = 28; 1207 b1 = 27; 1208 b2 = 26; 1209 } else { 1210 b0 = 24; 1211 b1 = 25; 1212 b2 = 26; 1213 } 1214 1215 #define DSI_FLD_GET(fld, start, end)\ 1216 FLD_GET(dsi_read_reg(dsidev, DSI_##fld), start, end) 1217 1218 pr_debug("DSI resets: PLL (%d) CIO (%d) PHY (%x%x%x, %d, %d, %d)\n", 1219 DSI_FLD_GET(PLL_STATUS, 0, 0), 1220 DSI_FLD_GET(COMPLEXIO_CFG1, 29, 29), 1221 DSI_FLD_GET(DSIPHY_CFG5, b0, b0), 1222 DSI_FLD_GET(DSIPHY_CFG5, b1, b1), 1223 DSI_FLD_GET(DSIPHY_CFG5, b2, b2), 1224 DSI_FLD_GET(DSIPHY_CFG5, 29, 29), 1225 DSI_FLD_GET(DSIPHY_CFG5, 30, 30), 1226 DSI_FLD_GET(DSIPHY_CFG5, 31, 31)); 1227 1228 #undef DSI_FLD_GET 1229 } 1230 1231 static inline int dsi_if_enable(struct platform_device *dsidev, bool enable) 1232 { 1233 DSSDBG("dsi_if_enable(%d)\n", enable); 1234 1235 enable = enable ? 1 : 0; 1236 REG_FLD_MOD(dsidev, DSI_CTRL, enable, 0, 0); /* IF_EN */ 1237 1238 if (wait_for_bit_change(dsidev, DSI_CTRL, 0, enable) != enable) { 1239 DSSERR("Failed to set dsi_if_enable to %d\n", enable); 1240 return -EIO; 1241 } 1242 1243 return 0; 1244 } 1245 1246 static unsigned long dsi_get_pll_hsdiv_dispc_rate(struct platform_device *dsidev) 1247 { 1248 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1249 1250 return dsi->pll.cinfo.clkout[HSDIV_DISPC]; 1251 } 1252 1253 static unsigned long dsi_get_pll_hsdiv_dsi_rate(struct platform_device *dsidev) 1254 { 1255 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1256 1257 return dsi->pll.cinfo.clkout[HSDIV_DSI]; 1258 } 1259 1260 static unsigned long dsi_get_txbyteclkhs(struct platform_device *dsidev) 1261 { 1262 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1263 1264 return dsi->pll.cinfo.clkdco / 16; 1265 } 1266 1267 static unsigned long dsi_fclk_rate(struct platform_device *dsidev) 1268 { 1269 unsigned long r; 1270 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1271 1272 if (dss_get_dsi_clk_source(dsi->module_id) == OMAP_DSS_CLK_SRC_FCK) { 1273 /* DSI FCLK source is DSS_CLK_FCK */ 1274 r = clk_get_rate(dsi->dss_clk); 1275 } else { 1276 /* DSI FCLK source is dsi_pll_hsdiv_dsi_clk */ 1277 r = dsi_get_pll_hsdiv_dsi_rate(dsidev); 1278 } 1279 1280 return r; 1281 } 1282 1283 static int dsi_lp_clock_calc(unsigned long dsi_fclk, 1284 unsigned long lp_clk_min, unsigned long lp_clk_max, 1285 struct dsi_lp_clock_info *lp_cinfo) 1286 { 1287 unsigned lp_clk_div; 1288 unsigned long lp_clk; 1289 1290 lp_clk_div = DIV_ROUND_UP(dsi_fclk, lp_clk_max * 2); 1291 lp_clk = dsi_fclk / 2 / lp_clk_div; 1292 1293 if (lp_clk < lp_clk_min || lp_clk > lp_clk_max) 1294 return -EINVAL; 1295 1296 lp_cinfo->lp_clk_div = lp_clk_div; 1297 lp_cinfo->lp_clk = lp_clk; 1298 1299 return 0; 1300 } 1301 1302 static int dsi_set_lp_clk_divisor(struct platform_device *dsidev) 1303 { 1304 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1305 unsigned long dsi_fclk; 1306 unsigned lp_clk_div; 1307 unsigned long lp_clk; 1308 unsigned lpdiv_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_LPDIV); 1309 1310 1311 lp_clk_div = dsi->user_lp_cinfo.lp_clk_div; 1312 1313 if (lp_clk_div == 0 || lp_clk_div > lpdiv_max) 1314 return -EINVAL; 1315 1316 dsi_fclk = dsi_fclk_rate(dsidev); 1317 1318 lp_clk = dsi_fclk / 2 / lp_clk_div; 1319 1320 DSSDBG("LP_CLK_DIV %u, LP_CLK %lu\n", lp_clk_div, lp_clk); 1321 dsi->current_lp_cinfo.lp_clk = lp_clk; 1322 dsi->current_lp_cinfo.lp_clk_div = lp_clk_div; 1323 1324 /* LP_CLK_DIVISOR */ 1325 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, lp_clk_div, 12, 0); 1326 1327 /* LP_RX_SYNCHRO_ENABLE */ 1328 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, dsi_fclk > 30000000 ? 1 : 0, 21, 21); 1329 1330 return 0; 1331 } 1332 1333 static void dsi_enable_scp_clk(struct platform_device *dsidev) 1334 { 1335 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1336 1337 if (dsi->scp_clk_refcount++ == 0) 1338 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 14, 14); /* CIO_CLK_ICG */ 1339 } 1340 1341 static void dsi_disable_scp_clk(struct platform_device *dsidev) 1342 { 1343 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1344 1345 WARN_ON(dsi->scp_clk_refcount == 0); 1346 if (--dsi->scp_clk_refcount == 0) 1347 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 14, 14); /* CIO_CLK_ICG */ 1348 } 1349 1350 enum dsi_pll_power_state { 1351 DSI_PLL_POWER_OFF = 0x0, 1352 DSI_PLL_POWER_ON_HSCLK = 0x1, 1353 DSI_PLL_POWER_ON_ALL = 0x2, 1354 DSI_PLL_POWER_ON_DIV = 0x3, 1355 }; 1356 1357 static int dsi_pll_power(struct platform_device *dsidev, 1358 enum dsi_pll_power_state state) 1359 { 1360 int t = 0; 1361 1362 /* DSI-PLL power command 0x3 is not working */ 1363 if (dss_has_feature(FEAT_DSI_PLL_PWR_BUG) && 1364 state == DSI_PLL_POWER_ON_DIV) 1365 state = DSI_PLL_POWER_ON_ALL; 1366 1367 /* PLL_PWR_CMD */ 1368 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, state, 31, 30); 1369 1370 /* PLL_PWR_STATUS */ 1371 while (FLD_GET(dsi_read_reg(dsidev, DSI_CLK_CTRL), 29, 28) != state) { 1372 if (++t > 1000) { 1373 DSSERR("Failed to set DSI PLL power mode to %d\n", 1374 state); 1375 return -ENODEV; 1376 } 1377 udelay(1); 1378 } 1379 1380 return 0; 1381 } 1382 1383 1384 static void dsi_pll_calc_dsi_fck(struct dss_pll_clock_info *cinfo) 1385 { 1386 unsigned long max_dsi_fck; 1387 1388 max_dsi_fck = dss_feat_get_param_max(FEAT_PARAM_DSI_FCK); 1389 1390 cinfo->mX[HSDIV_DSI] = DIV_ROUND_UP(cinfo->clkdco, max_dsi_fck); 1391 cinfo->clkout[HSDIV_DSI] = cinfo->clkdco / cinfo->mX[HSDIV_DSI]; 1392 } 1393 1394 static int dsi_pll_enable(struct dss_pll *pll) 1395 { 1396 struct dsi_data *dsi = container_of(pll, struct dsi_data, pll); 1397 struct platform_device *dsidev = dsi->pdev; 1398 int r = 0; 1399 1400 DSSDBG("PLL init\n"); 1401 1402 r = dsi_regulator_init(dsidev); 1403 if (r) 1404 return r; 1405 1406 r = dsi_runtime_get(dsidev); 1407 if (r) 1408 return r; 1409 1410 /* 1411 * Note: SCP CLK is not required on OMAP3, but it is required on OMAP4. 1412 */ 1413 dsi_enable_scp_clk(dsidev); 1414 1415 if (!dsi->vdds_dsi_enabled) { 1416 r = regulator_enable(dsi->vdds_dsi_reg); 1417 if (r) 1418 goto err0; 1419 dsi->vdds_dsi_enabled = true; 1420 } 1421 1422 /* XXX PLL does not come out of reset without this... */ 1423 dispc_pck_free_enable(1); 1424 1425 if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 0, 1) != 1) { 1426 DSSERR("PLL not coming out of reset.\n"); 1427 r = -ENODEV; 1428 dispc_pck_free_enable(0); 1429 goto err1; 1430 } 1431 1432 /* XXX ... but if left on, we get problems when planes do not 1433 * fill the whole display. No idea about this */ 1434 dispc_pck_free_enable(0); 1435 1436 r = dsi_pll_power(dsidev, DSI_PLL_POWER_ON_ALL); 1437 1438 if (r) 1439 goto err1; 1440 1441 DSSDBG("PLL init done\n"); 1442 1443 return 0; 1444 err1: 1445 if (dsi->vdds_dsi_enabled) { 1446 regulator_disable(dsi->vdds_dsi_reg); 1447 dsi->vdds_dsi_enabled = false; 1448 } 1449 err0: 1450 dsi_disable_scp_clk(dsidev); 1451 dsi_runtime_put(dsidev); 1452 return r; 1453 } 1454 1455 static void dsi_pll_uninit(struct platform_device *dsidev, bool disconnect_lanes) 1456 { 1457 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1458 1459 dsi_pll_power(dsidev, DSI_PLL_POWER_OFF); 1460 if (disconnect_lanes) { 1461 WARN_ON(!dsi->vdds_dsi_enabled); 1462 regulator_disable(dsi->vdds_dsi_reg); 1463 dsi->vdds_dsi_enabled = false; 1464 } 1465 1466 dsi_disable_scp_clk(dsidev); 1467 dsi_runtime_put(dsidev); 1468 1469 DSSDBG("PLL uninit done\n"); 1470 } 1471 1472 static void dsi_pll_disable(struct dss_pll *pll) 1473 { 1474 struct dsi_data *dsi = container_of(pll, struct dsi_data, pll); 1475 struct platform_device *dsidev = dsi->pdev; 1476 1477 dsi_pll_uninit(dsidev, true); 1478 } 1479 1480 static void dsi_dump_dsidev_clocks(struct platform_device *dsidev, 1481 struct seq_file *s) 1482 { 1483 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1484 struct dss_pll_clock_info *cinfo = &dsi->pll.cinfo; 1485 enum omap_dss_clk_source dispc_clk_src, dsi_clk_src; 1486 int dsi_module = dsi->module_id; 1487 struct dss_pll *pll = &dsi->pll; 1488 1489 dispc_clk_src = dss_get_dispc_clk_source(); 1490 dsi_clk_src = dss_get_dsi_clk_source(dsi_module); 1491 1492 if (dsi_runtime_get(dsidev)) 1493 return; 1494 1495 seq_printf(s, "- DSI%d PLL -\n", dsi_module + 1); 1496 1497 seq_printf(s, "dsi pll clkin\t%lu\n", clk_get_rate(pll->clkin)); 1498 1499 seq_printf(s, "Fint\t\t%-16lun %u\n", cinfo->fint, cinfo->n); 1500 1501 seq_printf(s, "CLKIN4DDR\t%-16lum %u\n", 1502 cinfo->clkdco, cinfo->m); 1503 1504 seq_printf(s, "DSI_PLL_HSDIV_DISPC (%s)\t%-16lum_dispc %u\t(%s)\n", 1505 dss_feat_get_clk_source_name(dsi_module == 0 ? 1506 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC : 1507 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC), 1508 cinfo->clkout[HSDIV_DISPC], 1509 cinfo->mX[HSDIV_DISPC], 1510 dispc_clk_src == OMAP_DSS_CLK_SRC_FCK ? 1511 "off" : "on"); 1512 1513 seq_printf(s, "DSI_PLL_HSDIV_DSI (%s)\t%-16lum_dsi %u\t(%s)\n", 1514 dss_feat_get_clk_source_name(dsi_module == 0 ? 1515 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI : 1516 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI), 1517 cinfo->clkout[HSDIV_DSI], 1518 cinfo->mX[HSDIV_DSI], 1519 dsi_clk_src == OMAP_DSS_CLK_SRC_FCK ? 1520 "off" : "on"); 1521 1522 seq_printf(s, "- DSI%d -\n", dsi_module + 1); 1523 1524 seq_printf(s, "dsi fclk source = %s (%s)\n", 1525 dss_get_generic_clk_source_name(dsi_clk_src), 1526 dss_feat_get_clk_source_name(dsi_clk_src)); 1527 1528 seq_printf(s, "DSI_FCLK\t%lu\n", dsi_fclk_rate(dsidev)); 1529 1530 seq_printf(s, "DDR_CLK\t\t%lu\n", 1531 cinfo->clkdco / 4); 1532 1533 seq_printf(s, "TxByteClkHS\t%lu\n", dsi_get_txbyteclkhs(dsidev)); 1534 1535 seq_printf(s, "LP_CLK\t\t%lu\n", dsi->current_lp_cinfo.lp_clk); 1536 1537 dsi_runtime_put(dsidev); 1538 } 1539 1540 void dsi_dump_clocks(struct seq_file *s) 1541 { 1542 struct platform_device *dsidev; 1543 int i; 1544 1545 for (i = 0; i < MAX_NUM_DSI; i++) { 1546 dsidev = dsi_get_dsidev_from_id(i); 1547 if (dsidev) 1548 dsi_dump_dsidev_clocks(dsidev, s); 1549 } 1550 } 1551 1552 #ifdef CONFIG_FB_OMAP2_DSS_COLLECT_IRQ_STATS 1553 static void dsi_dump_dsidev_irqs(struct platform_device *dsidev, 1554 struct seq_file *s) 1555 { 1556 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1557 unsigned long flags; 1558 struct dsi_irq_stats stats; 1559 1560 spin_lock_irqsave(&dsi->irq_stats_lock, flags); 1561 1562 stats = dsi->irq_stats; 1563 memset(&dsi->irq_stats, 0, sizeof(dsi->irq_stats)); 1564 dsi->irq_stats.last_reset = jiffies; 1565 1566 spin_unlock_irqrestore(&dsi->irq_stats_lock, flags); 1567 1568 seq_printf(s, "period %u ms\n", 1569 jiffies_to_msecs(jiffies - stats.last_reset)); 1570 1571 seq_printf(s, "irqs %d\n", stats.irq_count); 1572 #define PIS(x) \ 1573 seq_printf(s, "%-20s %10d\n", #x, stats.dsi_irqs[ffs(DSI_IRQ_##x)-1]); 1574 1575 seq_printf(s, "-- DSI%d interrupts --\n", dsi->module_id + 1); 1576 PIS(VC0); 1577 PIS(VC1); 1578 PIS(VC2); 1579 PIS(VC3); 1580 PIS(WAKEUP); 1581 PIS(RESYNC); 1582 PIS(PLL_LOCK); 1583 PIS(PLL_UNLOCK); 1584 PIS(PLL_RECALL); 1585 PIS(COMPLEXIO_ERR); 1586 PIS(HS_TX_TIMEOUT); 1587 PIS(LP_RX_TIMEOUT); 1588 PIS(TE_TRIGGER); 1589 PIS(ACK_TRIGGER); 1590 PIS(SYNC_LOST); 1591 PIS(LDO_POWER_GOOD); 1592 PIS(TA_TIMEOUT); 1593 #undef PIS 1594 1595 #define PIS(x) \ 1596 seq_printf(s, "%-20s %10d %10d %10d %10d\n", #x, \ 1597 stats.vc_irqs[0][ffs(DSI_VC_IRQ_##x)-1], \ 1598 stats.vc_irqs[1][ffs(DSI_VC_IRQ_##x)-1], \ 1599 stats.vc_irqs[2][ffs(DSI_VC_IRQ_##x)-1], \ 1600 stats.vc_irqs[3][ffs(DSI_VC_IRQ_##x)-1]); 1601 1602 seq_printf(s, "-- VC interrupts --\n"); 1603 PIS(CS); 1604 PIS(ECC_CORR); 1605 PIS(PACKET_SENT); 1606 PIS(FIFO_TX_OVF); 1607 PIS(FIFO_RX_OVF); 1608 PIS(BTA); 1609 PIS(ECC_NO_CORR); 1610 PIS(FIFO_TX_UDF); 1611 PIS(PP_BUSY_CHANGE); 1612 #undef PIS 1613 1614 #define PIS(x) \ 1615 seq_printf(s, "%-20s %10d\n", #x, \ 1616 stats.cio_irqs[ffs(DSI_CIO_IRQ_##x)-1]); 1617 1618 seq_printf(s, "-- CIO interrupts --\n"); 1619 PIS(ERRSYNCESC1); 1620 PIS(ERRSYNCESC2); 1621 PIS(ERRSYNCESC3); 1622 PIS(ERRESC1); 1623 PIS(ERRESC2); 1624 PIS(ERRESC3); 1625 PIS(ERRCONTROL1); 1626 PIS(ERRCONTROL2); 1627 PIS(ERRCONTROL3); 1628 PIS(STATEULPS1); 1629 PIS(STATEULPS2); 1630 PIS(STATEULPS3); 1631 PIS(ERRCONTENTIONLP0_1); 1632 PIS(ERRCONTENTIONLP1_1); 1633 PIS(ERRCONTENTIONLP0_2); 1634 PIS(ERRCONTENTIONLP1_2); 1635 PIS(ERRCONTENTIONLP0_3); 1636 PIS(ERRCONTENTIONLP1_3); 1637 PIS(ULPSACTIVENOT_ALL0); 1638 PIS(ULPSACTIVENOT_ALL1); 1639 #undef PIS 1640 } 1641 1642 static void dsi1_dump_irqs(struct seq_file *s) 1643 { 1644 struct platform_device *dsidev = dsi_get_dsidev_from_id(0); 1645 1646 dsi_dump_dsidev_irqs(dsidev, s); 1647 } 1648 1649 static void dsi2_dump_irqs(struct seq_file *s) 1650 { 1651 struct platform_device *dsidev = dsi_get_dsidev_from_id(1); 1652 1653 dsi_dump_dsidev_irqs(dsidev, s); 1654 } 1655 #endif 1656 1657 static void dsi_dump_dsidev_regs(struct platform_device *dsidev, 1658 struct seq_file *s) 1659 { 1660 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(dsidev, r)) 1661 1662 if (dsi_runtime_get(dsidev)) 1663 return; 1664 dsi_enable_scp_clk(dsidev); 1665 1666 DUMPREG(DSI_REVISION); 1667 DUMPREG(DSI_SYSCONFIG); 1668 DUMPREG(DSI_SYSSTATUS); 1669 DUMPREG(DSI_IRQSTATUS); 1670 DUMPREG(DSI_IRQENABLE); 1671 DUMPREG(DSI_CTRL); 1672 DUMPREG(DSI_COMPLEXIO_CFG1); 1673 DUMPREG(DSI_COMPLEXIO_IRQ_STATUS); 1674 DUMPREG(DSI_COMPLEXIO_IRQ_ENABLE); 1675 DUMPREG(DSI_CLK_CTRL); 1676 DUMPREG(DSI_TIMING1); 1677 DUMPREG(DSI_TIMING2); 1678 DUMPREG(DSI_VM_TIMING1); 1679 DUMPREG(DSI_VM_TIMING2); 1680 DUMPREG(DSI_VM_TIMING3); 1681 DUMPREG(DSI_CLK_TIMING); 1682 DUMPREG(DSI_TX_FIFO_VC_SIZE); 1683 DUMPREG(DSI_RX_FIFO_VC_SIZE); 1684 DUMPREG(DSI_COMPLEXIO_CFG2); 1685 DUMPREG(DSI_RX_FIFO_VC_FULLNESS); 1686 DUMPREG(DSI_VM_TIMING4); 1687 DUMPREG(DSI_TX_FIFO_VC_EMPTINESS); 1688 DUMPREG(DSI_VM_TIMING5); 1689 DUMPREG(DSI_VM_TIMING6); 1690 DUMPREG(DSI_VM_TIMING7); 1691 DUMPREG(DSI_STOPCLK_TIMING); 1692 1693 DUMPREG(DSI_VC_CTRL(0)); 1694 DUMPREG(DSI_VC_TE(0)); 1695 DUMPREG(DSI_VC_LONG_PACKET_HEADER(0)); 1696 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(0)); 1697 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(0)); 1698 DUMPREG(DSI_VC_IRQSTATUS(0)); 1699 DUMPREG(DSI_VC_IRQENABLE(0)); 1700 1701 DUMPREG(DSI_VC_CTRL(1)); 1702 DUMPREG(DSI_VC_TE(1)); 1703 DUMPREG(DSI_VC_LONG_PACKET_HEADER(1)); 1704 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(1)); 1705 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(1)); 1706 DUMPREG(DSI_VC_IRQSTATUS(1)); 1707 DUMPREG(DSI_VC_IRQENABLE(1)); 1708 1709 DUMPREG(DSI_VC_CTRL(2)); 1710 DUMPREG(DSI_VC_TE(2)); 1711 DUMPREG(DSI_VC_LONG_PACKET_HEADER(2)); 1712 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(2)); 1713 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(2)); 1714 DUMPREG(DSI_VC_IRQSTATUS(2)); 1715 DUMPREG(DSI_VC_IRQENABLE(2)); 1716 1717 DUMPREG(DSI_VC_CTRL(3)); 1718 DUMPREG(DSI_VC_TE(3)); 1719 DUMPREG(DSI_VC_LONG_PACKET_HEADER(3)); 1720 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(3)); 1721 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(3)); 1722 DUMPREG(DSI_VC_IRQSTATUS(3)); 1723 DUMPREG(DSI_VC_IRQENABLE(3)); 1724 1725 DUMPREG(DSI_DSIPHY_CFG0); 1726 DUMPREG(DSI_DSIPHY_CFG1); 1727 DUMPREG(DSI_DSIPHY_CFG2); 1728 DUMPREG(DSI_DSIPHY_CFG5); 1729 1730 DUMPREG(DSI_PLL_CONTROL); 1731 DUMPREG(DSI_PLL_STATUS); 1732 DUMPREG(DSI_PLL_GO); 1733 DUMPREG(DSI_PLL_CONFIGURATION1); 1734 DUMPREG(DSI_PLL_CONFIGURATION2); 1735 1736 dsi_disable_scp_clk(dsidev); 1737 dsi_runtime_put(dsidev); 1738 #undef DUMPREG 1739 } 1740 1741 static void dsi1_dump_regs(struct seq_file *s) 1742 { 1743 struct platform_device *dsidev = dsi_get_dsidev_from_id(0); 1744 1745 dsi_dump_dsidev_regs(dsidev, s); 1746 } 1747 1748 static void dsi2_dump_regs(struct seq_file *s) 1749 { 1750 struct platform_device *dsidev = dsi_get_dsidev_from_id(1); 1751 1752 dsi_dump_dsidev_regs(dsidev, s); 1753 } 1754 1755 enum dsi_cio_power_state { 1756 DSI_COMPLEXIO_POWER_OFF = 0x0, 1757 DSI_COMPLEXIO_POWER_ON = 0x1, 1758 DSI_COMPLEXIO_POWER_ULPS = 0x2, 1759 }; 1760 1761 static int dsi_cio_power(struct platform_device *dsidev, 1762 enum dsi_cio_power_state state) 1763 { 1764 int t = 0; 1765 1766 /* PWR_CMD */ 1767 REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG1, state, 28, 27); 1768 1769 /* PWR_STATUS */ 1770 while (FLD_GET(dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1), 1771 26, 25) != state) { 1772 if (++t > 1000) { 1773 DSSERR("failed to set complexio power state to " 1774 "%d\n", state); 1775 return -ENODEV; 1776 } 1777 udelay(1); 1778 } 1779 1780 return 0; 1781 } 1782 1783 static unsigned dsi_get_line_buf_size(struct platform_device *dsidev) 1784 { 1785 int val; 1786 1787 /* line buffer on OMAP3 is 1024 x 24bits */ 1788 /* XXX: for some reason using full buffer size causes 1789 * considerable TX slowdown with update sizes that fill the 1790 * whole buffer */ 1791 if (!dss_has_feature(FEAT_DSI_GNQ)) 1792 return 1023 * 3; 1793 1794 val = REG_GET(dsidev, DSI_GNQ, 14, 12); /* VP1_LINE_BUFFER_SIZE */ 1795 1796 switch (val) { 1797 case 1: 1798 return 512 * 3; /* 512x24 bits */ 1799 case 2: 1800 return 682 * 3; /* 682x24 bits */ 1801 case 3: 1802 return 853 * 3; /* 853x24 bits */ 1803 case 4: 1804 return 1024 * 3; /* 1024x24 bits */ 1805 case 5: 1806 return 1194 * 3; /* 1194x24 bits */ 1807 case 6: 1808 return 1365 * 3; /* 1365x24 bits */ 1809 case 7: 1810 return 1920 * 3; /* 1920x24 bits */ 1811 default: 1812 BUG(); 1813 return 0; 1814 } 1815 } 1816 1817 static int dsi_set_lane_config(struct platform_device *dsidev) 1818 { 1819 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1820 static const u8 offsets[] = { 0, 4, 8, 12, 16 }; 1821 static const enum dsi_lane_function functions[] = { 1822 DSI_LANE_CLK, 1823 DSI_LANE_DATA1, 1824 DSI_LANE_DATA2, 1825 DSI_LANE_DATA3, 1826 DSI_LANE_DATA4, 1827 }; 1828 u32 r; 1829 int i; 1830 1831 r = dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1); 1832 1833 for (i = 0; i < dsi->num_lanes_used; ++i) { 1834 unsigned offset = offsets[i]; 1835 unsigned polarity, lane_number; 1836 unsigned t; 1837 1838 for (t = 0; t < dsi->num_lanes_supported; ++t) 1839 if (dsi->lanes[t].function == functions[i]) 1840 break; 1841 1842 if (t == dsi->num_lanes_supported) 1843 return -EINVAL; 1844 1845 lane_number = t; 1846 polarity = dsi->lanes[t].polarity; 1847 1848 r = FLD_MOD(r, lane_number + 1, offset + 2, offset); 1849 r = FLD_MOD(r, polarity, offset + 3, offset + 3); 1850 } 1851 1852 /* clear the unused lanes */ 1853 for (; i < dsi->num_lanes_supported; ++i) { 1854 unsigned offset = offsets[i]; 1855 1856 r = FLD_MOD(r, 0, offset + 2, offset); 1857 r = FLD_MOD(r, 0, offset + 3, offset + 3); 1858 } 1859 1860 dsi_write_reg(dsidev, DSI_COMPLEXIO_CFG1, r); 1861 1862 return 0; 1863 } 1864 1865 static inline unsigned ns2ddr(struct platform_device *dsidev, unsigned ns) 1866 { 1867 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1868 1869 /* convert time in ns to ddr ticks, rounding up */ 1870 unsigned long ddr_clk = dsi->pll.cinfo.clkdco / 4; 1871 return (ns * (ddr_clk / 1000 / 1000) + 999) / 1000; 1872 } 1873 1874 static inline unsigned ddr2ns(struct platform_device *dsidev, unsigned ddr) 1875 { 1876 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1877 1878 unsigned long ddr_clk = dsi->pll.cinfo.clkdco / 4; 1879 return ddr * 1000 * 1000 / (ddr_clk / 1000); 1880 } 1881 1882 static void dsi_cio_timings(struct platform_device *dsidev) 1883 { 1884 u32 r; 1885 u32 ths_prepare, ths_prepare_ths_zero, ths_trail, ths_exit; 1886 u32 tlpx_half, tclk_trail, tclk_zero; 1887 u32 tclk_prepare; 1888 1889 /* calculate timings */ 1890 1891 /* 1 * DDR_CLK = 2 * UI */ 1892 1893 /* min 40ns + 4*UI max 85ns + 6*UI */ 1894 ths_prepare = ns2ddr(dsidev, 70) + 2; 1895 1896 /* min 145ns + 10*UI */ 1897 ths_prepare_ths_zero = ns2ddr(dsidev, 175) + 2; 1898 1899 /* min max(8*UI, 60ns+4*UI) */ 1900 ths_trail = ns2ddr(dsidev, 60) + 5; 1901 1902 /* min 100ns */ 1903 ths_exit = ns2ddr(dsidev, 145); 1904 1905 /* tlpx min 50n */ 1906 tlpx_half = ns2ddr(dsidev, 25); 1907 1908 /* min 60ns */ 1909 tclk_trail = ns2ddr(dsidev, 60) + 2; 1910 1911 /* min 38ns, max 95ns */ 1912 tclk_prepare = ns2ddr(dsidev, 65); 1913 1914 /* min tclk-prepare + tclk-zero = 300ns */ 1915 tclk_zero = ns2ddr(dsidev, 260); 1916 1917 DSSDBG("ths_prepare %u (%uns), ths_prepare_ths_zero %u (%uns)\n", 1918 ths_prepare, ddr2ns(dsidev, ths_prepare), 1919 ths_prepare_ths_zero, ddr2ns(dsidev, ths_prepare_ths_zero)); 1920 DSSDBG("ths_trail %u (%uns), ths_exit %u (%uns)\n", 1921 ths_trail, ddr2ns(dsidev, ths_trail), 1922 ths_exit, ddr2ns(dsidev, ths_exit)); 1923 1924 DSSDBG("tlpx_half %u (%uns), tclk_trail %u (%uns), " 1925 "tclk_zero %u (%uns)\n", 1926 tlpx_half, ddr2ns(dsidev, tlpx_half), 1927 tclk_trail, ddr2ns(dsidev, tclk_trail), 1928 tclk_zero, ddr2ns(dsidev, tclk_zero)); 1929 DSSDBG("tclk_prepare %u (%uns)\n", 1930 tclk_prepare, ddr2ns(dsidev, tclk_prepare)); 1931 1932 /* program timings */ 1933 1934 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0); 1935 r = FLD_MOD(r, ths_prepare, 31, 24); 1936 r = FLD_MOD(r, ths_prepare_ths_zero, 23, 16); 1937 r = FLD_MOD(r, ths_trail, 15, 8); 1938 r = FLD_MOD(r, ths_exit, 7, 0); 1939 dsi_write_reg(dsidev, DSI_DSIPHY_CFG0, r); 1940 1941 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1); 1942 r = FLD_MOD(r, tlpx_half, 20, 16); 1943 r = FLD_MOD(r, tclk_trail, 15, 8); 1944 r = FLD_MOD(r, tclk_zero, 7, 0); 1945 1946 if (dss_has_feature(FEAT_DSI_PHY_DCC)) { 1947 r = FLD_MOD(r, 0, 21, 21); /* DCCEN = disable */ 1948 r = FLD_MOD(r, 1, 22, 22); /* CLKINP_DIVBY2EN = enable */ 1949 r = FLD_MOD(r, 1, 23, 23); /* CLKINP_SEL = enable */ 1950 } 1951 1952 dsi_write_reg(dsidev, DSI_DSIPHY_CFG1, r); 1953 1954 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG2); 1955 r = FLD_MOD(r, tclk_prepare, 7, 0); 1956 dsi_write_reg(dsidev, DSI_DSIPHY_CFG2, r); 1957 } 1958 1959 /* lane masks have lane 0 at lsb. mask_p for positive lines, n for negative */ 1960 static void dsi_cio_enable_lane_override(struct platform_device *dsidev, 1961 unsigned mask_p, unsigned mask_n) 1962 { 1963 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1964 int i; 1965 u32 l; 1966 u8 lptxscp_start = dsi->num_lanes_supported == 3 ? 22 : 26; 1967 1968 l = 0; 1969 1970 for (i = 0; i < dsi->num_lanes_supported; ++i) { 1971 unsigned p = dsi->lanes[i].polarity; 1972 1973 if (mask_p & (1 << i)) 1974 l |= 1 << (i * 2 + (p ? 0 : 1)); 1975 1976 if (mask_n & (1 << i)) 1977 l |= 1 << (i * 2 + (p ? 1 : 0)); 1978 } 1979 1980 /* 1981 * Bits in REGLPTXSCPDAT4TO0DXDY: 1982 * 17: DY0 18: DX0 1983 * 19: DY1 20: DX1 1984 * 21: DY2 22: DX2 1985 * 23: DY3 24: DX3 1986 * 25: DY4 26: DX4 1987 */ 1988 1989 /* Set the lane override configuration */ 1990 1991 /* REGLPTXSCPDAT4TO0DXDY */ 1992 REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, l, lptxscp_start, 17); 1993 1994 /* Enable lane override */ 1995 1996 /* ENLPTXSCPDAT */ 1997 REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 1, 27, 27); 1998 } 1999 2000 static void dsi_cio_disable_lane_override(struct platform_device *dsidev) 2001 { 2002 /* Disable lane override */ 2003 REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 0, 27, 27); /* ENLPTXSCPDAT */ 2004 /* Reset the lane override configuration */ 2005 /* REGLPTXSCPDAT4TO0DXDY */ 2006 REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 0, 22, 17); 2007 } 2008 2009 static int dsi_cio_wait_tx_clk_esc_reset(struct platform_device *dsidev) 2010 { 2011 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 2012 int t, i; 2013 bool in_use[DSI_MAX_NR_LANES]; 2014 static const u8 offsets_old[] = { 28, 27, 26 }; 2015 static const u8 offsets_new[] = { 24, 25, 26, 27, 28 }; 2016 const u8 *offsets; 2017 2018 if (dss_has_feature(FEAT_DSI_REVERSE_TXCLKESC)) 2019 offsets = offsets_old; 2020 else 2021 offsets = offsets_new; 2022 2023 for (i = 0; i < dsi->num_lanes_supported; ++i) 2024 in_use[i] = dsi->lanes[i].function != DSI_LANE_UNUSED; 2025 2026 t = 100000; 2027 while (true) { 2028 u32 l; 2029 int ok; 2030 2031 l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5); 2032 2033 ok = 0; 2034 for (i = 0; i < dsi->num_lanes_supported; ++i) { 2035 if (!in_use[i] || (l & (1 << offsets[i]))) 2036 ok++; 2037 } 2038 2039 if (ok == dsi->num_lanes_supported) 2040 break; 2041 2042 if (--t == 0) { 2043 for (i = 0; i < dsi->num_lanes_supported; ++i) { 2044 if (!in_use[i] || (l & (1 << offsets[i]))) 2045 continue; 2046 2047 DSSERR("CIO TXCLKESC%d domain not coming " \ 2048 "out of reset\n", i); 2049 } 2050 return -EIO; 2051 } 2052 } 2053 2054 return 0; 2055 } 2056 2057 /* return bitmask of enabled lanes, lane0 being the lsb */ 2058 static unsigned dsi_get_lane_mask(struct platform_device *dsidev) 2059 { 2060 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 2061 unsigned mask = 0; 2062 int i; 2063 2064 for (i = 0; i < dsi->num_lanes_supported; ++i) { 2065 if (dsi->lanes[i].function != DSI_LANE_UNUSED) 2066 mask |= 1 << i; 2067 } 2068 2069 return mask; 2070 } 2071 2072 static int dsi_cio_init(struct platform_device *dsidev) 2073 { 2074 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 2075 int r; 2076 u32 l; 2077 2078 DSSDBG("DSI CIO init starts"); 2079 2080 r = dss_dsi_enable_pads(dsi->module_id, dsi_get_lane_mask(dsidev)); 2081 if (r) 2082 return r; 2083 2084 dsi_enable_scp_clk(dsidev); 2085 2086 /* A dummy read using the SCP interface to any DSIPHY register is 2087 * required after DSIPHY reset to complete the reset of the DSI complex 2088 * I/O. */ 2089 dsi_read_reg(dsidev, DSI_DSIPHY_CFG5); 2090 2091 if (wait_for_bit_change(dsidev, DSI_DSIPHY_CFG5, 30, 1) != 1) { 2092 DSSERR("CIO SCP Clock domain not coming out of reset.\n"); 2093 r = -EIO; 2094 goto err_scp_clk_dom; 2095 } 2096 2097 r = dsi_set_lane_config(dsidev); 2098 if (r) 2099 goto err_scp_clk_dom; 2100 2101 /* set TX STOP MODE timer to maximum for this operation */ 2102 l = dsi_read_reg(dsidev, DSI_TIMING1); 2103 l = FLD_MOD(l, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */ 2104 l = FLD_MOD(l, 1, 14, 14); /* STOP_STATE_X16_IO */ 2105 l = FLD_MOD(l, 1, 13, 13); /* STOP_STATE_X4_IO */ 2106 l = FLD_MOD(l, 0x1fff, 12, 0); /* STOP_STATE_COUNTER_IO */ 2107 dsi_write_reg(dsidev, DSI_TIMING1, l); 2108 2109 if (dsi->ulps_enabled) { 2110 unsigned mask_p; 2111 int i; 2112 2113 DSSDBG("manual ulps exit\n"); 2114 2115 /* ULPS is exited by Mark-1 state for 1ms, followed by 2116 * stop state. DSS HW cannot do this via the normal 2117 * ULPS exit sequence, as after reset the DSS HW thinks 2118 * that we are not in ULPS mode, and refuses to send the 2119 * sequence. So we need to send the ULPS exit sequence 2120 * manually by setting positive lines high and negative lines 2121 * low for 1ms. 2122 */ 2123 2124 mask_p = 0; 2125 2126 for (i = 0; i < dsi->num_lanes_supported; ++i) { 2127 if (dsi->lanes[i].function == DSI_LANE_UNUSED) 2128 continue; 2129 mask_p |= 1 << i; 2130 } 2131 2132 dsi_cio_enable_lane_override(dsidev, mask_p, 0); 2133 } 2134 2135 r = dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_ON); 2136 if (r) 2137 goto err_cio_pwr; 2138 2139 if (wait_for_bit_change(dsidev, DSI_COMPLEXIO_CFG1, 29, 1) != 1) { 2140 DSSERR("CIO PWR clock domain not coming out of reset.\n"); 2141 r = -ENODEV; 2142 goto err_cio_pwr_dom; 2143 } 2144 2145 dsi_if_enable(dsidev, true); 2146 dsi_if_enable(dsidev, false); 2147 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 20, 20); /* LP_CLK_ENABLE */ 2148 2149 r = dsi_cio_wait_tx_clk_esc_reset(dsidev); 2150 if (r) 2151 goto err_tx_clk_esc_rst; 2152 2153 if (dsi->ulps_enabled) { 2154 /* Keep Mark-1 state for 1ms (as per DSI spec) */ 2155 ktime_t wait = ns_to_ktime(1000 * 1000); 2156 set_current_state(TASK_UNINTERRUPTIBLE); 2157 schedule_hrtimeout(&wait, HRTIMER_MODE_REL); 2158 2159 /* Disable the override. The lanes should be set to Mark-11 2160 * state by the HW */ 2161 dsi_cio_disable_lane_override(dsidev); 2162 } 2163 2164 /* FORCE_TX_STOP_MODE_IO */ 2165 REG_FLD_MOD(dsidev, DSI_TIMING1, 0, 15, 15); 2166 2167 dsi_cio_timings(dsidev); 2168 2169 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) { 2170 /* DDR_CLK_ALWAYS_ON */ 2171 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 2172 dsi->vm_timings.ddr_clk_always_on, 13, 13); 2173 } 2174 2175 dsi->ulps_enabled = false; 2176 2177 DSSDBG("CIO init done\n"); 2178 2179 return 0; 2180 2181 err_tx_clk_esc_rst: 2182 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 20, 20); /* LP_CLK_ENABLE */ 2183 err_cio_pwr_dom: 2184 dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_OFF); 2185 err_cio_pwr: 2186 if (dsi->ulps_enabled) 2187 dsi_cio_disable_lane_override(dsidev); 2188 err_scp_clk_dom: 2189 dsi_disable_scp_clk(dsidev); 2190 dss_dsi_disable_pads(dsi->module_id, dsi_get_lane_mask(dsidev)); 2191 return r; 2192 } 2193 2194 static void dsi_cio_uninit(struct platform_device *dsidev) 2195 { 2196 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 2197 2198 /* DDR_CLK_ALWAYS_ON */ 2199 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 13, 13); 2200 2201 dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_OFF); 2202 dsi_disable_scp_clk(dsidev); 2203 dss_dsi_disable_pads(dsi->module_id, dsi_get_lane_mask(dsidev)); 2204 } 2205 2206 static void dsi_config_tx_fifo(struct platform_device *dsidev, 2207 enum fifo_size size1, enum fifo_size size2, 2208 enum fifo_size size3, enum fifo_size size4) 2209 { 2210 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 2211 u32 r = 0; 2212 int add = 0; 2213 int i; 2214 2215 dsi->vc[0].tx_fifo_size = size1; 2216 dsi->vc[1].tx_fifo_size = size2; 2217 dsi->vc[2].tx_fifo_size = size3; 2218 dsi->vc[3].tx_fifo_size = size4; 2219 2220 for (i = 0; i < 4; i++) { 2221 u8 v; 2222 int size = dsi->vc[i].tx_fifo_size; 2223 2224 if (add + size > 4) { 2225 DSSERR("Illegal FIFO configuration\n"); 2226 BUG(); 2227 return; 2228 } 2229 2230 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4); 2231 r |= v << (8 * i); 2232 /*DSSDBG("TX FIFO vc %d: size %d, add %d\n", i, size, add); */ 2233 add += size; 2234 } 2235 2236 dsi_write_reg(dsidev, DSI_TX_FIFO_VC_SIZE, r); 2237 } 2238 2239 static void dsi_config_rx_fifo(struct platform_device *dsidev, 2240 enum fifo_size size1, enum fifo_size size2, 2241 enum fifo_size size3, enum fifo_size size4) 2242 { 2243 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 2244 u32 r = 0; 2245 int add = 0; 2246 int i; 2247 2248 dsi->vc[0].rx_fifo_size = size1; 2249 dsi->vc[1].rx_fifo_size = size2; 2250 dsi->vc[2].rx_fifo_size = size3; 2251 dsi->vc[3].rx_fifo_size = size4; 2252 2253 for (i = 0; i < 4; i++) { 2254 u8 v; 2255 int size = dsi->vc[i].rx_fifo_size; 2256 2257 if (add + size > 4) { 2258 DSSERR("Illegal FIFO configuration\n"); 2259 BUG(); 2260 return; 2261 } 2262 2263 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4); 2264 r |= v << (8 * i); 2265 /*DSSDBG("RX FIFO vc %d: size %d, add %d\n", i, size, add); */ 2266 add += size; 2267 } 2268 2269 dsi_write_reg(dsidev, DSI_RX_FIFO_VC_SIZE, r); 2270 } 2271 2272 static int dsi_force_tx_stop_mode_io(struct platform_device *dsidev) 2273 { 2274 u32 r; 2275 2276 r = dsi_read_reg(dsidev, DSI_TIMING1); 2277 r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */ 2278 dsi_write_reg(dsidev, DSI_TIMING1, r); 2279 2280 if (wait_for_bit_change(dsidev, DSI_TIMING1, 15, 0) != 0) { 2281 DSSERR("TX_STOP bit not going down\n"); 2282 return -EIO; 2283 } 2284 2285 return 0; 2286 } 2287 2288 static bool dsi_vc_is_enabled(struct platform_device *dsidev, int channel) 2289 { 2290 return REG_GET(dsidev, DSI_VC_CTRL(channel), 0, 0); 2291 } 2292 2293 static void dsi_packet_sent_handler_vp(void *data, u32 mask) 2294 { 2295 struct dsi_packet_sent_handler_data *vp_data = 2296 (struct dsi_packet_sent_handler_data *) data; 2297 struct dsi_data *dsi = dsi_get_dsidrv_data(vp_data->dsidev); 2298 const int channel = dsi->update_channel; 2299 u8 bit = dsi->te_enabled ? 30 : 31; 2300 2301 if (REG_GET(vp_data->dsidev, DSI_VC_TE(channel), bit, bit) == 0) 2302 complete(vp_data->completion); 2303 } 2304 2305 static int dsi_sync_vc_vp(struct platform_device *dsidev, int channel) 2306 { 2307 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 2308 DECLARE_COMPLETION_ONSTACK(completion); 2309 struct dsi_packet_sent_handler_data vp_data = { 2310 .dsidev = dsidev, 2311 .completion = &completion 2312 }; 2313 int r = 0; 2314 u8 bit; 2315 2316 bit = dsi->te_enabled ? 30 : 31; 2317 2318 r = dsi_register_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp, 2319 &vp_data, DSI_VC_IRQ_PACKET_SENT); 2320 if (r) 2321 goto err0; 2322 2323 /* Wait for completion only if TE_EN/TE_START is still set */ 2324 if (REG_GET(dsidev, DSI_VC_TE(channel), bit, bit)) { 2325 if (wait_for_completion_timeout(&completion, 2326 msecs_to_jiffies(10)) == 0) { 2327 DSSERR("Failed to complete previous frame transfer\n"); 2328 r = -EIO; 2329 goto err1; 2330 } 2331 } 2332 2333 dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp, 2334 &vp_data, DSI_VC_IRQ_PACKET_SENT); 2335 2336 return 0; 2337 err1: 2338 dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp, 2339 &vp_data, DSI_VC_IRQ_PACKET_SENT); 2340 err0: 2341 return r; 2342 } 2343 2344 static void dsi_packet_sent_handler_l4(void *data, u32 mask) 2345 { 2346 struct dsi_packet_sent_handler_data *l4_data = 2347 (struct dsi_packet_sent_handler_data *) data; 2348 struct dsi_data *dsi = dsi_get_dsidrv_data(l4_data->dsidev); 2349 const int channel = dsi->update_channel; 2350 2351 if (REG_GET(l4_data->dsidev, DSI_VC_CTRL(channel), 5, 5) == 0) 2352 complete(l4_data->completion); 2353 } 2354 2355 static int dsi_sync_vc_l4(struct platform_device *dsidev, int channel) 2356 { 2357 DECLARE_COMPLETION_ONSTACK(completion); 2358 struct dsi_packet_sent_handler_data l4_data = { 2359 .dsidev = dsidev, 2360 .completion = &completion 2361 }; 2362 int r = 0; 2363 2364 r = dsi_register_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4, 2365 &l4_data, DSI_VC_IRQ_PACKET_SENT); 2366 if (r) 2367 goto err0; 2368 2369 /* Wait for completion only if TX_FIFO_NOT_EMPTY is still set */ 2370 if (REG_GET(dsidev, DSI_VC_CTRL(channel), 5, 5)) { 2371 if (wait_for_completion_timeout(&completion, 2372 msecs_to_jiffies(10)) == 0) { 2373 DSSERR("Failed to complete previous l4 transfer\n"); 2374 r = -EIO; 2375 goto err1; 2376 } 2377 } 2378 2379 dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4, 2380 &l4_data, DSI_VC_IRQ_PACKET_SENT); 2381 2382 return 0; 2383 err1: 2384 dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4, 2385 &l4_data, DSI_VC_IRQ_PACKET_SENT); 2386 err0: 2387 return r; 2388 } 2389 2390 static int dsi_sync_vc(struct platform_device *dsidev, int channel) 2391 { 2392 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 2393 2394 WARN_ON(!dsi_bus_is_locked(dsidev)); 2395 2396 WARN_ON(in_interrupt()); 2397 2398 if (!dsi_vc_is_enabled(dsidev, channel)) 2399 return 0; 2400 2401 switch (dsi->vc[channel].source) { 2402 case DSI_VC_SOURCE_VP: 2403 return dsi_sync_vc_vp(dsidev, channel); 2404 case DSI_VC_SOURCE_L4: 2405 return dsi_sync_vc_l4(dsidev, channel); 2406 default: 2407 BUG(); 2408 return -EINVAL; 2409 } 2410 } 2411 2412 static int dsi_vc_enable(struct platform_device *dsidev, int channel, 2413 bool enable) 2414 { 2415 DSSDBG("dsi_vc_enable channel %d, enable %d\n", 2416 channel, enable); 2417 2418 enable = enable ? 1 : 0; 2419 2420 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 0, 0); 2421 2422 if (wait_for_bit_change(dsidev, DSI_VC_CTRL(channel), 2423 0, enable) != enable) { 2424 DSSERR("Failed to set dsi_vc_enable to %d\n", enable); 2425 return -EIO; 2426 } 2427 2428 return 0; 2429 } 2430 2431 static void dsi_vc_initial_config(struct platform_device *dsidev, int channel) 2432 { 2433 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 2434 u32 r; 2435 2436 DSSDBG("Initial config of virtual channel %d", channel); 2437 2438 r = dsi_read_reg(dsidev, DSI_VC_CTRL(channel)); 2439 2440 if (FLD_GET(r, 15, 15)) /* VC_BUSY */ 2441 DSSERR("VC(%d) busy when trying to configure it!\n", 2442 channel); 2443 2444 r = FLD_MOD(r, 0, 1, 1); /* SOURCE, 0 = L4 */ 2445 r = FLD_MOD(r, 0, 2, 2); /* BTA_SHORT_EN */ 2446 r = FLD_MOD(r, 0, 3, 3); /* BTA_LONG_EN */ 2447 r = FLD_MOD(r, 0, 4, 4); /* MODE, 0 = command */ 2448 r = FLD_MOD(r, 1, 7, 7); /* CS_TX_EN */ 2449 r = FLD_MOD(r, 1, 8, 8); /* ECC_TX_EN */ 2450 r = FLD_MOD(r, 0, 9, 9); /* MODE_SPEED, high speed on/off */ 2451 if (dss_has_feature(FEAT_DSI_VC_OCP_WIDTH)) 2452 r = FLD_MOD(r, 3, 11, 10); /* OCP_WIDTH = 32 bit */ 2453 2454 r = FLD_MOD(r, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */ 2455 r = FLD_MOD(r, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */ 2456 2457 dsi_write_reg(dsidev, DSI_VC_CTRL(channel), r); 2458 2459 dsi->vc[channel].source = DSI_VC_SOURCE_L4; 2460 } 2461 2462 static int dsi_vc_config_source(struct platform_device *dsidev, int channel, 2463 enum dsi_vc_source source) 2464 { 2465 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 2466 2467 if (dsi->vc[channel].source == source) 2468 return 0; 2469 2470 DSSDBG("Source config of virtual channel %d", channel); 2471 2472 dsi_sync_vc(dsidev, channel); 2473 2474 dsi_vc_enable(dsidev, channel, 0); 2475 2476 /* VC_BUSY */ 2477 if (wait_for_bit_change(dsidev, DSI_VC_CTRL(channel), 15, 0) != 0) { 2478 DSSERR("vc(%d) busy when trying to config for VP\n", channel); 2479 return -EIO; 2480 } 2481 2482 /* SOURCE, 0 = L4, 1 = video port */ 2483 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), source, 1, 1); 2484 2485 /* DCS_CMD_ENABLE */ 2486 if (dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC)) { 2487 bool enable = source == DSI_VC_SOURCE_VP; 2488 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 30, 30); 2489 } 2490 2491 dsi_vc_enable(dsidev, channel, 1); 2492 2493 dsi->vc[channel].source = source; 2494 2495 return 0; 2496 } 2497 2498 static void dsi_vc_enable_hs(struct omap_dss_device *dssdev, int channel, 2499 bool enable) 2500 { 2501 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 2502 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 2503 2504 DSSDBG("dsi_vc_enable_hs(%d, %d)\n", channel, enable); 2505 2506 WARN_ON(!dsi_bus_is_locked(dsidev)); 2507 2508 dsi_vc_enable(dsidev, channel, 0); 2509 dsi_if_enable(dsidev, 0); 2510 2511 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 9, 9); 2512 2513 dsi_vc_enable(dsidev, channel, 1); 2514 dsi_if_enable(dsidev, 1); 2515 2516 dsi_force_tx_stop_mode_io(dsidev); 2517 2518 /* start the DDR clock by sending a NULL packet */ 2519 if (dsi->vm_timings.ddr_clk_always_on && enable) 2520 dsi_vc_send_null(dssdev, channel); 2521 } 2522 2523 static void dsi_vc_flush_long_data(struct platform_device *dsidev, int channel) 2524 { 2525 while (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) { 2526 u32 val; 2527 val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel)); 2528 DSSDBG("\t\tb1 %#02x b2 %#02x b3 %#02x b4 %#02x\n", 2529 (val >> 0) & 0xff, 2530 (val >> 8) & 0xff, 2531 (val >> 16) & 0xff, 2532 (val >> 24) & 0xff); 2533 } 2534 } 2535 2536 static void dsi_show_rx_ack_with_err(u16 err) 2537 { 2538 DSSERR("\tACK with ERROR (%#x):\n", err); 2539 if (err & (1 << 0)) 2540 DSSERR("\t\tSoT Error\n"); 2541 if (err & (1 << 1)) 2542 DSSERR("\t\tSoT Sync Error\n"); 2543 if (err & (1 << 2)) 2544 DSSERR("\t\tEoT Sync Error\n"); 2545 if (err & (1 << 3)) 2546 DSSERR("\t\tEscape Mode Entry Command Error\n"); 2547 if (err & (1 << 4)) 2548 DSSERR("\t\tLP Transmit Sync Error\n"); 2549 if (err & (1 << 5)) 2550 DSSERR("\t\tHS Receive Timeout Error\n"); 2551 if (err & (1 << 6)) 2552 DSSERR("\t\tFalse Control Error\n"); 2553 if (err & (1 << 7)) 2554 DSSERR("\t\t(reserved7)\n"); 2555 if (err & (1 << 8)) 2556 DSSERR("\t\tECC Error, single-bit (corrected)\n"); 2557 if (err & (1 << 9)) 2558 DSSERR("\t\tECC Error, multi-bit (not corrected)\n"); 2559 if (err & (1 << 10)) 2560 DSSERR("\t\tChecksum Error\n"); 2561 if (err & (1 << 11)) 2562 DSSERR("\t\tData type not recognized\n"); 2563 if (err & (1 << 12)) 2564 DSSERR("\t\tInvalid VC ID\n"); 2565 if (err & (1 << 13)) 2566 DSSERR("\t\tInvalid Transmission Length\n"); 2567 if (err & (1 << 14)) 2568 DSSERR("\t\t(reserved14)\n"); 2569 if (err & (1 << 15)) 2570 DSSERR("\t\tDSI Protocol Violation\n"); 2571 } 2572 2573 static u16 dsi_vc_flush_receive_data(struct platform_device *dsidev, 2574 int channel) 2575 { 2576 /* RX_FIFO_NOT_EMPTY */ 2577 while (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) { 2578 u32 val; 2579 u8 dt; 2580 val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel)); 2581 DSSERR("\trawval %#08x\n", val); 2582 dt = FLD_GET(val, 5, 0); 2583 if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) { 2584 u16 err = FLD_GET(val, 23, 8); 2585 dsi_show_rx_ack_with_err(err); 2586 } else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE) { 2587 DSSERR("\tDCS short response, 1 byte: %#x\n", 2588 FLD_GET(val, 23, 8)); 2589 } else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE) { 2590 DSSERR("\tDCS short response, 2 byte: %#x\n", 2591 FLD_GET(val, 23, 8)); 2592 } else if (dt == MIPI_DSI_RX_DCS_LONG_READ_RESPONSE) { 2593 DSSERR("\tDCS long response, len %d\n", 2594 FLD_GET(val, 23, 8)); 2595 dsi_vc_flush_long_data(dsidev, channel); 2596 } else { 2597 DSSERR("\tunknown datatype 0x%02x\n", dt); 2598 } 2599 } 2600 return 0; 2601 } 2602 2603 static int dsi_vc_send_bta(struct platform_device *dsidev, int channel) 2604 { 2605 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 2606 2607 if (dsi->debug_write || dsi->debug_read) 2608 DSSDBG("dsi_vc_send_bta %d\n", channel); 2609 2610 WARN_ON(!dsi_bus_is_locked(dsidev)); 2611 2612 /* RX_FIFO_NOT_EMPTY */ 2613 if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) { 2614 DSSERR("rx fifo not empty when sending BTA, dumping data:\n"); 2615 dsi_vc_flush_receive_data(dsidev, channel); 2616 } 2617 2618 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 1, 6, 6); /* BTA_EN */ 2619 2620 /* flush posted write */ 2621 dsi_read_reg(dsidev, DSI_VC_CTRL(channel)); 2622 2623 return 0; 2624 } 2625 2626 static int dsi_vc_send_bta_sync(struct omap_dss_device *dssdev, int channel) 2627 { 2628 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 2629 DECLARE_COMPLETION_ONSTACK(completion); 2630 int r = 0; 2631 u32 err; 2632 2633 r = dsi_register_isr_vc(dsidev, channel, dsi_completion_handler, 2634 &completion, DSI_VC_IRQ_BTA); 2635 if (r) 2636 goto err0; 2637 2638 r = dsi_register_isr(dsidev, dsi_completion_handler, &completion, 2639 DSI_IRQ_ERROR_MASK); 2640 if (r) 2641 goto err1; 2642 2643 r = dsi_vc_send_bta(dsidev, channel); 2644 if (r) 2645 goto err2; 2646 2647 if (wait_for_completion_timeout(&completion, 2648 msecs_to_jiffies(500)) == 0) { 2649 DSSERR("Failed to receive BTA\n"); 2650 r = -EIO; 2651 goto err2; 2652 } 2653 2654 err = dsi_get_errors(dsidev); 2655 if (err) { 2656 DSSERR("Error while sending BTA: %x\n", err); 2657 r = -EIO; 2658 goto err2; 2659 } 2660 err2: 2661 dsi_unregister_isr(dsidev, dsi_completion_handler, &completion, 2662 DSI_IRQ_ERROR_MASK); 2663 err1: 2664 dsi_unregister_isr_vc(dsidev, channel, dsi_completion_handler, 2665 &completion, DSI_VC_IRQ_BTA); 2666 err0: 2667 return r; 2668 } 2669 2670 static inline void dsi_vc_write_long_header(struct platform_device *dsidev, 2671 int channel, u8 data_type, u16 len, u8 ecc) 2672 { 2673 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 2674 u32 val; 2675 u8 data_id; 2676 2677 WARN_ON(!dsi_bus_is_locked(dsidev)); 2678 2679 data_id = data_type | dsi->vc[channel].vc_id << 6; 2680 2681 val = FLD_VAL(data_id, 7, 0) | FLD_VAL(len, 23, 8) | 2682 FLD_VAL(ecc, 31, 24); 2683 2684 dsi_write_reg(dsidev, DSI_VC_LONG_PACKET_HEADER(channel), val); 2685 } 2686 2687 static inline void dsi_vc_write_long_payload(struct platform_device *dsidev, 2688 int channel, u8 b1, u8 b2, u8 b3, u8 b4) 2689 { 2690 u32 val; 2691 2692 val = b4 << 24 | b3 << 16 | b2 << 8 | b1 << 0; 2693 2694 /* DSSDBG("\twriting %02x, %02x, %02x, %02x (%#010x)\n", 2695 b1, b2, b3, b4, val); */ 2696 2697 dsi_write_reg(dsidev, DSI_VC_LONG_PACKET_PAYLOAD(channel), val); 2698 } 2699 2700 static int dsi_vc_send_long(struct platform_device *dsidev, int channel, 2701 u8 data_type, u8 *data, u16 len, u8 ecc) 2702 { 2703 /*u32 val; */ 2704 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 2705 int i; 2706 u8 *p; 2707 int r = 0; 2708 u8 b1, b2, b3, b4; 2709 2710 if (dsi->debug_write) 2711 DSSDBG("dsi_vc_send_long, %d bytes\n", len); 2712 2713 /* len + header */ 2714 if (dsi->vc[channel].tx_fifo_size * 32 * 4 < len + 4) { 2715 DSSERR("unable to send long packet: packet too long.\n"); 2716 return -EINVAL; 2717 } 2718 2719 dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_L4); 2720 2721 dsi_vc_write_long_header(dsidev, channel, data_type, len, ecc); 2722 2723 p = data; 2724 for (i = 0; i < len >> 2; i++) { 2725 if (dsi->debug_write) 2726 DSSDBG("\tsending full packet %d\n", i); 2727 2728 b1 = *p++; 2729 b2 = *p++; 2730 b3 = *p++; 2731 b4 = *p++; 2732 2733 dsi_vc_write_long_payload(dsidev, channel, b1, b2, b3, b4); 2734 } 2735 2736 i = len % 4; 2737 if (i) { 2738 b1 = 0; b2 = 0; b3 = 0; 2739 2740 if (dsi->debug_write) 2741 DSSDBG("\tsending remainder bytes %d\n", i); 2742 2743 switch (i) { 2744 case 3: 2745 b1 = *p++; 2746 b2 = *p++; 2747 b3 = *p++; 2748 break; 2749 case 2: 2750 b1 = *p++; 2751 b2 = *p++; 2752 break; 2753 case 1: 2754 b1 = *p++; 2755 break; 2756 } 2757 2758 dsi_vc_write_long_payload(dsidev, channel, b1, b2, b3, 0); 2759 } 2760 2761 return r; 2762 } 2763 2764 static int dsi_vc_send_short(struct platform_device *dsidev, int channel, 2765 u8 data_type, u16 data, u8 ecc) 2766 { 2767 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 2768 u32 r; 2769 u8 data_id; 2770 2771 WARN_ON(!dsi_bus_is_locked(dsidev)); 2772 2773 if (dsi->debug_write) 2774 DSSDBG("dsi_vc_send_short(ch%d, dt %#x, b1 %#x, b2 %#x)\n", 2775 channel, 2776 data_type, data & 0xff, (data >> 8) & 0xff); 2777 2778 dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_L4); 2779 2780 if (FLD_GET(dsi_read_reg(dsidev, DSI_VC_CTRL(channel)), 16, 16)) { 2781 DSSERR("ERROR FIFO FULL, aborting transfer\n"); 2782 return -EINVAL; 2783 } 2784 2785 data_id = data_type | dsi->vc[channel].vc_id << 6; 2786 2787 r = (data_id << 0) | (data << 8) | (ecc << 24); 2788 2789 dsi_write_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel), r); 2790 2791 return 0; 2792 } 2793 2794 static int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel) 2795 { 2796 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 2797 2798 return dsi_vc_send_long(dsidev, channel, MIPI_DSI_NULL_PACKET, NULL, 2799 0, 0); 2800 } 2801 2802 static int dsi_vc_write_nosync_common(struct platform_device *dsidev, 2803 int channel, u8 *data, int len, enum dss_dsi_content_type type) 2804 { 2805 int r; 2806 2807 if (len == 0) { 2808 BUG_ON(type == DSS_DSI_CONTENT_DCS); 2809 r = dsi_vc_send_short(dsidev, channel, 2810 MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM, 0, 0); 2811 } else if (len == 1) { 2812 r = dsi_vc_send_short(dsidev, channel, 2813 type == DSS_DSI_CONTENT_GENERIC ? 2814 MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM : 2815 MIPI_DSI_DCS_SHORT_WRITE, data[0], 0); 2816 } else if (len == 2) { 2817 r = dsi_vc_send_short(dsidev, channel, 2818 type == DSS_DSI_CONTENT_GENERIC ? 2819 MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM : 2820 MIPI_DSI_DCS_SHORT_WRITE_PARAM, 2821 data[0] | (data[1] << 8), 0); 2822 } else { 2823 r = dsi_vc_send_long(dsidev, channel, 2824 type == DSS_DSI_CONTENT_GENERIC ? 2825 MIPI_DSI_GENERIC_LONG_WRITE : 2826 MIPI_DSI_DCS_LONG_WRITE, data, len, 0); 2827 } 2828 2829 return r; 2830 } 2831 2832 static int dsi_vc_dcs_write_nosync(struct omap_dss_device *dssdev, int channel, 2833 u8 *data, int len) 2834 { 2835 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 2836 2837 return dsi_vc_write_nosync_common(dsidev, channel, data, len, 2838 DSS_DSI_CONTENT_DCS); 2839 } 2840 2841 static int dsi_vc_generic_write_nosync(struct omap_dss_device *dssdev, int channel, 2842 u8 *data, int len) 2843 { 2844 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 2845 2846 return dsi_vc_write_nosync_common(dsidev, channel, data, len, 2847 DSS_DSI_CONTENT_GENERIC); 2848 } 2849 2850 static int dsi_vc_write_common(struct omap_dss_device *dssdev, int channel, 2851 u8 *data, int len, enum dss_dsi_content_type type) 2852 { 2853 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 2854 int r; 2855 2856 r = dsi_vc_write_nosync_common(dsidev, channel, data, len, type); 2857 if (r) 2858 goto err; 2859 2860 r = dsi_vc_send_bta_sync(dssdev, channel); 2861 if (r) 2862 goto err; 2863 2864 /* RX_FIFO_NOT_EMPTY */ 2865 if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) { 2866 DSSERR("rx fifo not empty after write, dumping data:\n"); 2867 dsi_vc_flush_receive_data(dsidev, channel); 2868 r = -EIO; 2869 goto err; 2870 } 2871 2872 return 0; 2873 err: 2874 DSSERR("dsi_vc_write_common(ch %d, cmd 0x%02x, len %d) failed\n", 2875 channel, data[0], len); 2876 return r; 2877 } 2878 2879 static int dsi_vc_dcs_write(struct omap_dss_device *dssdev, int channel, u8 *data, 2880 int len) 2881 { 2882 return dsi_vc_write_common(dssdev, channel, data, len, 2883 DSS_DSI_CONTENT_DCS); 2884 } 2885 2886 static int dsi_vc_generic_write(struct omap_dss_device *dssdev, int channel, u8 *data, 2887 int len) 2888 { 2889 return dsi_vc_write_common(dssdev, channel, data, len, 2890 DSS_DSI_CONTENT_GENERIC); 2891 } 2892 2893 static int dsi_vc_dcs_send_read_request(struct platform_device *dsidev, 2894 int channel, u8 dcs_cmd) 2895 { 2896 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 2897 int r; 2898 2899 if (dsi->debug_read) 2900 DSSDBG("dsi_vc_dcs_send_read_request(ch%d, dcs_cmd %x)\n", 2901 channel, dcs_cmd); 2902 2903 r = dsi_vc_send_short(dsidev, channel, MIPI_DSI_DCS_READ, dcs_cmd, 0); 2904 if (r) { 2905 DSSERR("dsi_vc_dcs_send_read_request(ch %d, cmd 0x%02x)" 2906 " failed\n", channel, dcs_cmd); 2907 return r; 2908 } 2909 2910 return 0; 2911 } 2912 2913 static int dsi_vc_generic_send_read_request(struct platform_device *dsidev, 2914 int channel, u8 *reqdata, int reqlen) 2915 { 2916 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 2917 u16 data; 2918 u8 data_type; 2919 int r; 2920 2921 if (dsi->debug_read) 2922 DSSDBG("dsi_vc_generic_send_read_request(ch %d, reqlen %d)\n", 2923 channel, reqlen); 2924 2925 if (reqlen == 0) { 2926 data_type = MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM; 2927 data = 0; 2928 } else if (reqlen == 1) { 2929 data_type = MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM; 2930 data = reqdata[0]; 2931 } else if (reqlen == 2) { 2932 data_type = MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM; 2933 data = reqdata[0] | (reqdata[1] << 8); 2934 } else { 2935 BUG(); 2936 return -EINVAL; 2937 } 2938 2939 r = dsi_vc_send_short(dsidev, channel, data_type, data, 0); 2940 if (r) { 2941 DSSERR("dsi_vc_generic_send_read_request(ch %d, reqlen %d)" 2942 " failed\n", channel, reqlen); 2943 return r; 2944 } 2945 2946 return 0; 2947 } 2948 2949 static int dsi_vc_read_rx_fifo(struct platform_device *dsidev, int channel, 2950 u8 *buf, int buflen, enum dss_dsi_content_type type) 2951 { 2952 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 2953 u32 val; 2954 u8 dt; 2955 int r; 2956 2957 /* RX_FIFO_NOT_EMPTY */ 2958 if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20) == 0) { 2959 DSSERR("RX fifo empty when trying to read.\n"); 2960 r = -EIO; 2961 goto err; 2962 } 2963 2964 val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel)); 2965 if (dsi->debug_read) 2966 DSSDBG("\theader: %08x\n", val); 2967 dt = FLD_GET(val, 5, 0); 2968 if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) { 2969 u16 err = FLD_GET(val, 23, 8); 2970 dsi_show_rx_ack_with_err(err); 2971 r = -EIO; 2972 goto err; 2973 2974 } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ? 2975 MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE : 2976 MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE)) { 2977 u8 data = FLD_GET(val, 15, 8); 2978 if (dsi->debug_read) 2979 DSSDBG("\t%s short response, 1 byte: %02x\n", 2980 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" : 2981 "DCS", data); 2982 2983 if (buflen < 1) { 2984 r = -EIO; 2985 goto err; 2986 } 2987 2988 buf[0] = data; 2989 2990 return 1; 2991 } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ? 2992 MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE : 2993 MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE)) { 2994 u16 data = FLD_GET(val, 23, 8); 2995 if (dsi->debug_read) 2996 DSSDBG("\t%s short response, 2 byte: %04x\n", 2997 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" : 2998 "DCS", data); 2999 3000 if (buflen < 2) { 3001 r = -EIO; 3002 goto err; 3003 } 3004 3005 buf[0] = data & 0xff; 3006 buf[1] = (data >> 8) & 0xff; 3007 3008 return 2; 3009 } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ? 3010 MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE : 3011 MIPI_DSI_RX_DCS_LONG_READ_RESPONSE)) { 3012 int w; 3013 int len = FLD_GET(val, 23, 8); 3014 if (dsi->debug_read) 3015 DSSDBG("\t%s long response, len %d\n", 3016 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" : 3017 "DCS", len); 3018 3019 if (len > buflen) { 3020 r = -EIO; 3021 goto err; 3022 } 3023 3024 /* two byte checksum ends the packet, not included in len */ 3025 for (w = 0; w < len + 2;) { 3026 int b; 3027 val = dsi_read_reg(dsidev, 3028 DSI_VC_SHORT_PACKET_HEADER(channel)); 3029 if (dsi->debug_read) 3030 DSSDBG("\t\t%02x %02x %02x %02x\n", 3031 (val >> 0) & 0xff, 3032 (val >> 8) & 0xff, 3033 (val >> 16) & 0xff, 3034 (val >> 24) & 0xff); 3035 3036 for (b = 0; b < 4; ++b) { 3037 if (w < len) 3038 buf[w] = (val >> (b * 8)) & 0xff; 3039 /* we discard the 2 byte checksum */ 3040 ++w; 3041 } 3042 } 3043 3044 return len; 3045 } else { 3046 DSSERR("\tunknown datatype 0x%02x\n", dt); 3047 r = -EIO; 3048 goto err; 3049 } 3050 3051 err: 3052 DSSERR("dsi_vc_read_rx_fifo(ch %d type %s) failed\n", channel, 3053 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" : "DCS"); 3054 3055 return r; 3056 } 3057 3058 static int dsi_vc_dcs_read(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd, 3059 u8 *buf, int buflen) 3060 { 3061 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 3062 int r; 3063 3064 r = dsi_vc_dcs_send_read_request(dsidev, channel, dcs_cmd); 3065 if (r) 3066 goto err; 3067 3068 r = dsi_vc_send_bta_sync(dssdev, channel); 3069 if (r) 3070 goto err; 3071 3072 r = dsi_vc_read_rx_fifo(dsidev, channel, buf, buflen, 3073 DSS_DSI_CONTENT_DCS); 3074 if (r < 0) 3075 goto err; 3076 3077 if (r != buflen) { 3078 r = -EIO; 3079 goto err; 3080 } 3081 3082 return 0; 3083 err: 3084 DSSERR("dsi_vc_dcs_read(ch %d, cmd 0x%02x) failed\n", channel, dcs_cmd); 3085 return r; 3086 } 3087 3088 static int dsi_vc_generic_read(struct omap_dss_device *dssdev, int channel, 3089 u8 *reqdata, int reqlen, u8 *buf, int buflen) 3090 { 3091 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 3092 int r; 3093 3094 r = dsi_vc_generic_send_read_request(dsidev, channel, reqdata, reqlen); 3095 if (r) 3096 return r; 3097 3098 r = dsi_vc_send_bta_sync(dssdev, channel); 3099 if (r) 3100 return r; 3101 3102 r = dsi_vc_read_rx_fifo(dsidev, channel, buf, buflen, 3103 DSS_DSI_CONTENT_GENERIC); 3104 if (r < 0) 3105 return r; 3106 3107 if (r != buflen) { 3108 r = -EIO; 3109 return r; 3110 } 3111 3112 return 0; 3113 } 3114 3115 static int dsi_vc_set_max_rx_packet_size(struct omap_dss_device *dssdev, int channel, 3116 u16 len) 3117 { 3118 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 3119 3120 return dsi_vc_send_short(dsidev, channel, 3121 MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE, len, 0); 3122 } 3123 3124 static int dsi_enter_ulps(struct platform_device *dsidev) 3125 { 3126 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 3127 DECLARE_COMPLETION_ONSTACK(completion); 3128 int r, i; 3129 unsigned mask; 3130 3131 DSSDBG("Entering ULPS"); 3132 3133 WARN_ON(!dsi_bus_is_locked(dsidev)); 3134 3135 WARN_ON(dsi->ulps_enabled); 3136 3137 if (dsi->ulps_enabled) 3138 return 0; 3139 3140 /* DDR_CLK_ALWAYS_ON */ 3141 if (REG_GET(dsidev, DSI_CLK_CTRL, 13, 13)) { 3142 dsi_if_enable(dsidev, 0); 3143 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 13, 13); 3144 dsi_if_enable(dsidev, 1); 3145 } 3146 3147 dsi_sync_vc(dsidev, 0); 3148 dsi_sync_vc(dsidev, 1); 3149 dsi_sync_vc(dsidev, 2); 3150 dsi_sync_vc(dsidev, 3); 3151 3152 dsi_force_tx_stop_mode_io(dsidev); 3153 3154 dsi_vc_enable(dsidev, 0, false); 3155 dsi_vc_enable(dsidev, 1, false); 3156 dsi_vc_enable(dsidev, 2, false); 3157 dsi_vc_enable(dsidev, 3, false); 3158 3159 if (REG_GET(dsidev, DSI_COMPLEXIO_CFG2, 16, 16)) { /* HS_BUSY */ 3160 DSSERR("HS busy when enabling ULPS\n"); 3161 return -EIO; 3162 } 3163 3164 if (REG_GET(dsidev, DSI_COMPLEXIO_CFG2, 17, 17)) { /* LP_BUSY */ 3165 DSSERR("LP busy when enabling ULPS\n"); 3166 return -EIO; 3167 } 3168 3169 r = dsi_register_isr_cio(dsidev, dsi_completion_handler, &completion, 3170 DSI_CIO_IRQ_ULPSACTIVENOT_ALL0); 3171 if (r) 3172 return r; 3173 3174 mask = 0; 3175 3176 for (i = 0; i < dsi->num_lanes_supported; ++i) { 3177 if (dsi->lanes[i].function == DSI_LANE_UNUSED) 3178 continue; 3179 mask |= 1 << i; 3180 } 3181 /* Assert TxRequestEsc for data lanes and TxUlpsClk for clk lane */ 3182 /* LANEx_ULPS_SIG2 */ 3183 REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG2, mask, 9, 5); 3184 3185 /* flush posted write and wait for SCP interface to finish the write */ 3186 dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG2); 3187 3188 if (wait_for_completion_timeout(&completion, 3189 msecs_to_jiffies(1000)) == 0) { 3190 DSSERR("ULPS enable timeout\n"); 3191 r = -EIO; 3192 goto err; 3193 } 3194 3195 dsi_unregister_isr_cio(dsidev, dsi_completion_handler, &completion, 3196 DSI_CIO_IRQ_ULPSACTIVENOT_ALL0); 3197 3198 /* Reset LANEx_ULPS_SIG2 */ 3199 REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG2, 0, 9, 5); 3200 3201 /* flush posted write and wait for SCP interface to finish the write */ 3202 dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG2); 3203 3204 dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_ULPS); 3205 3206 dsi_if_enable(dsidev, false); 3207 3208 dsi->ulps_enabled = true; 3209 3210 return 0; 3211 3212 err: 3213 dsi_unregister_isr_cio(dsidev, dsi_completion_handler, &completion, 3214 DSI_CIO_IRQ_ULPSACTIVENOT_ALL0); 3215 return r; 3216 } 3217 3218 static void dsi_set_lp_rx_timeout(struct platform_device *dsidev, 3219 unsigned ticks, bool x4, bool x16) 3220 { 3221 unsigned long fck; 3222 unsigned long total_ticks; 3223 u32 r; 3224 3225 BUG_ON(ticks > 0x1fff); 3226 3227 /* ticks in DSI_FCK */ 3228 fck = dsi_fclk_rate(dsidev); 3229 3230 r = dsi_read_reg(dsidev, DSI_TIMING2); 3231 r = FLD_MOD(r, 1, 15, 15); /* LP_RX_TO */ 3232 r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* LP_RX_TO_X16 */ 3233 r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* LP_RX_TO_X4 */ 3234 r = FLD_MOD(r, ticks, 12, 0); /* LP_RX_COUNTER */ 3235 dsi_write_reg(dsidev, DSI_TIMING2, r); 3236 3237 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1); 3238 3239 DSSDBG("LP_RX_TO %lu ticks (%#x%s%s) = %lu ns\n", 3240 total_ticks, 3241 ticks, x4 ? " x4" : "", x16 ? " x16" : "", 3242 (total_ticks * 1000) / (fck / 1000 / 1000)); 3243 } 3244 3245 static void dsi_set_ta_timeout(struct platform_device *dsidev, unsigned ticks, 3246 bool x8, bool x16) 3247 { 3248 unsigned long fck; 3249 unsigned long total_ticks; 3250 u32 r; 3251 3252 BUG_ON(ticks > 0x1fff); 3253 3254 /* ticks in DSI_FCK */ 3255 fck = dsi_fclk_rate(dsidev); 3256 3257 r = dsi_read_reg(dsidev, DSI_TIMING1); 3258 r = FLD_MOD(r, 1, 31, 31); /* TA_TO */ 3259 r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* TA_TO_X16 */ 3260 r = FLD_MOD(r, x8 ? 1 : 0, 29, 29); /* TA_TO_X8 */ 3261 r = FLD_MOD(r, ticks, 28, 16); /* TA_TO_COUNTER */ 3262 dsi_write_reg(dsidev, DSI_TIMING1, r); 3263 3264 total_ticks = ticks * (x16 ? 16 : 1) * (x8 ? 8 : 1); 3265 3266 DSSDBG("TA_TO %lu ticks (%#x%s%s) = %lu ns\n", 3267 total_ticks, 3268 ticks, x8 ? " x8" : "", x16 ? " x16" : "", 3269 (total_ticks * 1000) / (fck / 1000 / 1000)); 3270 } 3271 3272 static void dsi_set_stop_state_counter(struct platform_device *dsidev, 3273 unsigned ticks, bool x4, bool x16) 3274 { 3275 unsigned long fck; 3276 unsigned long total_ticks; 3277 u32 r; 3278 3279 BUG_ON(ticks > 0x1fff); 3280 3281 /* ticks in DSI_FCK */ 3282 fck = dsi_fclk_rate(dsidev); 3283 3284 r = dsi_read_reg(dsidev, DSI_TIMING1); 3285 r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */ 3286 r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* STOP_STATE_X16_IO */ 3287 r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* STOP_STATE_X4_IO */ 3288 r = FLD_MOD(r, ticks, 12, 0); /* STOP_STATE_COUNTER_IO */ 3289 dsi_write_reg(dsidev, DSI_TIMING1, r); 3290 3291 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1); 3292 3293 DSSDBG("STOP_STATE_COUNTER %lu ticks (%#x%s%s) = %lu ns\n", 3294 total_ticks, 3295 ticks, x4 ? " x4" : "", x16 ? " x16" : "", 3296 (total_ticks * 1000) / (fck / 1000 / 1000)); 3297 } 3298 3299 static void dsi_set_hs_tx_timeout(struct platform_device *dsidev, 3300 unsigned ticks, bool x4, bool x16) 3301 { 3302 unsigned long fck; 3303 unsigned long total_ticks; 3304 u32 r; 3305 3306 BUG_ON(ticks > 0x1fff); 3307 3308 /* ticks in TxByteClkHS */ 3309 fck = dsi_get_txbyteclkhs(dsidev); 3310 3311 r = dsi_read_reg(dsidev, DSI_TIMING2); 3312 r = FLD_MOD(r, 1, 31, 31); /* HS_TX_TO */ 3313 r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* HS_TX_TO_X16 */ 3314 r = FLD_MOD(r, x4 ? 1 : 0, 29, 29); /* HS_TX_TO_X8 (4 really) */ 3315 r = FLD_MOD(r, ticks, 28, 16); /* HS_TX_TO_COUNTER */ 3316 dsi_write_reg(dsidev, DSI_TIMING2, r); 3317 3318 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1); 3319 3320 DSSDBG("HS_TX_TO %lu ticks (%#x%s%s) = %lu ns\n", 3321 total_ticks, 3322 ticks, x4 ? " x4" : "", x16 ? " x16" : "", 3323 (total_ticks * 1000) / (fck / 1000 / 1000)); 3324 } 3325 3326 static void dsi_config_vp_num_line_buffers(struct platform_device *dsidev) 3327 { 3328 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 3329 int num_line_buffers; 3330 3331 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) { 3332 int bpp = dsi_get_pixel_size(dsi->pix_fmt); 3333 struct omap_video_timings *timings = &dsi->timings; 3334 /* 3335 * Don't use line buffers if width is greater than the video 3336 * port's line buffer size 3337 */ 3338 if (dsi->line_buffer_size <= timings->x_res * bpp / 8) 3339 num_line_buffers = 0; 3340 else 3341 num_line_buffers = 2; 3342 } else { 3343 /* Use maximum number of line buffers in command mode */ 3344 num_line_buffers = 2; 3345 } 3346 3347 /* LINE_BUFFER */ 3348 REG_FLD_MOD(dsidev, DSI_CTRL, num_line_buffers, 13, 12); 3349 } 3350 3351 static void dsi_config_vp_sync_events(struct platform_device *dsidev) 3352 { 3353 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 3354 bool sync_end; 3355 u32 r; 3356 3357 if (dsi->vm_timings.trans_mode == OMAP_DSS_DSI_PULSE_MODE) 3358 sync_end = true; 3359 else 3360 sync_end = false; 3361 3362 r = dsi_read_reg(dsidev, DSI_CTRL); 3363 r = FLD_MOD(r, 1, 9, 9); /* VP_DE_POL */ 3364 r = FLD_MOD(r, 1, 10, 10); /* VP_HSYNC_POL */ 3365 r = FLD_MOD(r, 1, 11, 11); /* VP_VSYNC_POL */ 3366 r = FLD_MOD(r, 1, 15, 15); /* VP_VSYNC_START */ 3367 r = FLD_MOD(r, sync_end, 16, 16); /* VP_VSYNC_END */ 3368 r = FLD_MOD(r, 1, 17, 17); /* VP_HSYNC_START */ 3369 r = FLD_MOD(r, sync_end, 18, 18); /* VP_HSYNC_END */ 3370 dsi_write_reg(dsidev, DSI_CTRL, r); 3371 } 3372 3373 static void dsi_config_blanking_modes(struct platform_device *dsidev) 3374 { 3375 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 3376 int blanking_mode = dsi->vm_timings.blanking_mode; 3377 int hfp_blanking_mode = dsi->vm_timings.hfp_blanking_mode; 3378 int hbp_blanking_mode = dsi->vm_timings.hbp_blanking_mode; 3379 int hsa_blanking_mode = dsi->vm_timings.hsa_blanking_mode; 3380 u32 r; 3381 3382 /* 3383 * 0 = TX FIFO packets sent or LPS in corresponding blanking periods 3384 * 1 = Long blanking packets are sent in corresponding blanking periods 3385 */ 3386 r = dsi_read_reg(dsidev, DSI_CTRL); 3387 r = FLD_MOD(r, blanking_mode, 20, 20); /* BLANKING_MODE */ 3388 r = FLD_MOD(r, hfp_blanking_mode, 21, 21); /* HFP_BLANKING */ 3389 r = FLD_MOD(r, hbp_blanking_mode, 22, 22); /* HBP_BLANKING */ 3390 r = FLD_MOD(r, hsa_blanking_mode, 23, 23); /* HSA_BLANKING */ 3391 dsi_write_reg(dsidev, DSI_CTRL, r); 3392 } 3393 3394 /* 3395 * According to section 'HS Command Mode Interleaving' in OMAP TRM, Scenario 3 3396 * results in maximum transition time for data and clock lanes to enter and 3397 * exit HS mode. Hence, this is the scenario where the least amount of command 3398 * mode data can be interleaved. We program the minimum amount of TXBYTECLKHS 3399 * clock cycles that can be used to interleave command mode data in HS so that 3400 * all scenarios are satisfied. 3401 */ 3402 static int dsi_compute_interleave_hs(int blank, bool ddr_alwon, int enter_hs, 3403 int exit_hs, int exiths_clk, int ddr_pre, int ddr_post) 3404 { 3405 int transition; 3406 3407 /* 3408 * If DDR_CLK_ALWAYS_ON is set, we need to consider HS mode transition 3409 * time of data lanes only, if it isn't set, we need to consider HS 3410 * transition time of both data and clock lanes. HS transition time 3411 * of Scenario 3 is considered. 3412 */ 3413 if (ddr_alwon) { 3414 transition = enter_hs + exit_hs + max(enter_hs, 2) + 1; 3415 } else { 3416 int trans1, trans2; 3417 trans1 = ddr_pre + enter_hs + exit_hs + max(enter_hs, 2) + 1; 3418 trans2 = ddr_pre + enter_hs + exiths_clk + ddr_post + ddr_pre + 3419 enter_hs + 1; 3420 transition = max(trans1, trans2); 3421 } 3422 3423 return blank > transition ? blank - transition : 0; 3424 } 3425 3426 /* 3427 * According to section 'LP Command Mode Interleaving' in OMAP TRM, Scenario 1 3428 * results in maximum transition time for data lanes to enter and exit LP mode. 3429 * Hence, this is the scenario where the least amount of command mode data can 3430 * be interleaved. We program the minimum amount of bytes that can be 3431 * interleaved in LP so that all scenarios are satisfied. 3432 */ 3433 static int dsi_compute_interleave_lp(int blank, int enter_hs, int exit_hs, 3434 int lp_clk_div, int tdsi_fclk) 3435 { 3436 int trans_lp; /* time required for a LP transition, in TXBYTECLKHS */ 3437 int tlp_avail; /* time left for interleaving commands, in CLKIN4DDR */ 3438 int ttxclkesc; /* period of LP transmit escape clock, in CLKIN4DDR */ 3439 int thsbyte_clk = 16; /* Period of TXBYTECLKHS clock, in CLKIN4DDR */ 3440 int lp_inter; /* cmd mode data that can be interleaved, in bytes */ 3441 3442 /* maximum LP transition time according to Scenario 1 */ 3443 trans_lp = exit_hs + max(enter_hs, 2) + 1; 3444 3445 /* CLKIN4DDR = 16 * TXBYTECLKHS */ 3446 tlp_avail = thsbyte_clk * (blank - trans_lp); 3447 3448 ttxclkesc = tdsi_fclk * lp_clk_div; 3449 3450 lp_inter = ((tlp_avail - 8 * thsbyte_clk - 5 * tdsi_fclk) / ttxclkesc - 3451 26) / 16; 3452 3453 return max(lp_inter, 0); 3454 } 3455 3456 static void dsi_config_cmd_mode_interleaving(struct platform_device *dsidev) 3457 { 3458 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 3459 int blanking_mode; 3460 int hfp_blanking_mode, hbp_blanking_mode, hsa_blanking_mode; 3461 int hsa, hfp, hbp, width_bytes, bllp, lp_clk_div; 3462 int ddr_clk_pre, ddr_clk_post, enter_hs_mode_lat, exit_hs_mode_lat; 3463 int tclk_trail, ths_exit, exiths_clk; 3464 bool ddr_alwon; 3465 struct omap_video_timings *timings = &dsi->timings; 3466 int bpp = dsi_get_pixel_size(dsi->pix_fmt); 3467 int ndl = dsi->num_lanes_used - 1; 3468 int dsi_fclk_hsdiv = dsi->user_dsi_cinfo.mX[HSDIV_DSI] + 1; 3469 int hsa_interleave_hs = 0, hsa_interleave_lp = 0; 3470 int hfp_interleave_hs = 0, hfp_interleave_lp = 0; 3471 int hbp_interleave_hs = 0, hbp_interleave_lp = 0; 3472 int bl_interleave_hs = 0, bl_interleave_lp = 0; 3473 u32 r; 3474 3475 r = dsi_read_reg(dsidev, DSI_CTRL); 3476 blanking_mode = FLD_GET(r, 20, 20); 3477 hfp_blanking_mode = FLD_GET(r, 21, 21); 3478 hbp_blanking_mode = FLD_GET(r, 22, 22); 3479 hsa_blanking_mode = FLD_GET(r, 23, 23); 3480 3481 r = dsi_read_reg(dsidev, DSI_VM_TIMING1); 3482 hbp = FLD_GET(r, 11, 0); 3483 hfp = FLD_GET(r, 23, 12); 3484 hsa = FLD_GET(r, 31, 24); 3485 3486 r = dsi_read_reg(dsidev, DSI_CLK_TIMING); 3487 ddr_clk_post = FLD_GET(r, 7, 0); 3488 ddr_clk_pre = FLD_GET(r, 15, 8); 3489 3490 r = dsi_read_reg(dsidev, DSI_VM_TIMING7); 3491 exit_hs_mode_lat = FLD_GET(r, 15, 0); 3492 enter_hs_mode_lat = FLD_GET(r, 31, 16); 3493 3494 r = dsi_read_reg(dsidev, DSI_CLK_CTRL); 3495 lp_clk_div = FLD_GET(r, 12, 0); 3496 ddr_alwon = FLD_GET(r, 13, 13); 3497 3498 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0); 3499 ths_exit = FLD_GET(r, 7, 0); 3500 3501 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1); 3502 tclk_trail = FLD_GET(r, 15, 8); 3503 3504 exiths_clk = ths_exit + tclk_trail; 3505 3506 width_bytes = DIV_ROUND_UP(timings->x_res * bpp, 8); 3507 bllp = hbp + hfp + hsa + DIV_ROUND_UP(width_bytes + 6, ndl); 3508 3509 if (!hsa_blanking_mode) { 3510 hsa_interleave_hs = dsi_compute_interleave_hs(hsa, ddr_alwon, 3511 enter_hs_mode_lat, exit_hs_mode_lat, 3512 exiths_clk, ddr_clk_pre, ddr_clk_post); 3513 hsa_interleave_lp = dsi_compute_interleave_lp(hsa, 3514 enter_hs_mode_lat, exit_hs_mode_lat, 3515 lp_clk_div, dsi_fclk_hsdiv); 3516 } 3517 3518 if (!hfp_blanking_mode) { 3519 hfp_interleave_hs = dsi_compute_interleave_hs(hfp, ddr_alwon, 3520 enter_hs_mode_lat, exit_hs_mode_lat, 3521 exiths_clk, ddr_clk_pre, ddr_clk_post); 3522 hfp_interleave_lp = dsi_compute_interleave_lp(hfp, 3523 enter_hs_mode_lat, exit_hs_mode_lat, 3524 lp_clk_div, dsi_fclk_hsdiv); 3525 } 3526 3527 if (!hbp_blanking_mode) { 3528 hbp_interleave_hs = dsi_compute_interleave_hs(hbp, ddr_alwon, 3529 enter_hs_mode_lat, exit_hs_mode_lat, 3530 exiths_clk, ddr_clk_pre, ddr_clk_post); 3531 3532 hbp_interleave_lp = dsi_compute_interleave_lp(hbp, 3533 enter_hs_mode_lat, exit_hs_mode_lat, 3534 lp_clk_div, dsi_fclk_hsdiv); 3535 } 3536 3537 if (!blanking_mode) { 3538 bl_interleave_hs = dsi_compute_interleave_hs(bllp, ddr_alwon, 3539 enter_hs_mode_lat, exit_hs_mode_lat, 3540 exiths_clk, ddr_clk_pre, ddr_clk_post); 3541 3542 bl_interleave_lp = dsi_compute_interleave_lp(bllp, 3543 enter_hs_mode_lat, exit_hs_mode_lat, 3544 lp_clk_div, dsi_fclk_hsdiv); 3545 } 3546 3547 DSSDBG("DSI HS interleaving(TXBYTECLKHS) HSA %d, HFP %d, HBP %d, BLLP %d\n", 3548 hsa_interleave_hs, hfp_interleave_hs, hbp_interleave_hs, 3549 bl_interleave_hs); 3550 3551 DSSDBG("DSI LP interleaving(bytes) HSA %d, HFP %d, HBP %d, BLLP %d\n", 3552 hsa_interleave_lp, hfp_interleave_lp, hbp_interleave_lp, 3553 bl_interleave_lp); 3554 3555 r = dsi_read_reg(dsidev, DSI_VM_TIMING4); 3556 r = FLD_MOD(r, hsa_interleave_hs, 23, 16); 3557 r = FLD_MOD(r, hfp_interleave_hs, 15, 8); 3558 r = FLD_MOD(r, hbp_interleave_hs, 7, 0); 3559 dsi_write_reg(dsidev, DSI_VM_TIMING4, r); 3560 3561 r = dsi_read_reg(dsidev, DSI_VM_TIMING5); 3562 r = FLD_MOD(r, hsa_interleave_lp, 23, 16); 3563 r = FLD_MOD(r, hfp_interleave_lp, 15, 8); 3564 r = FLD_MOD(r, hbp_interleave_lp, 7, 0); 3565 dsi_write_reg(dsidev, DSI_VM_TIMING5, r); 3566 3567 r = dsi_read_reg(dsidev, DSI_VM_TIMING6); 3568 r = FLD_MOD(r, bl_interleave_hs, 31, 15); 3569 r = FLD_MOD(r, bl_interleave_lp, 16, 0); 3570 dsi_write_reg(dsidev, DSI_VM_TIMING6, r); 3571 } 3572 3573 static int dsi_proto_config(struct platform_device *dsidev) 3574 { 3575 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 3576 u32 r; 3577 int buswidth = 0; 3578 3579 dsi_config_tx_fifo(dsidev, DSI_FIFO_SIZE_32, 3580 DSI_FIFO_SIZE_32, 3581 DSI_FIFO_SIZE_32, 3582 DSI_FIFO_SIZE_32); 3583 3584 dsi_config_rx_fifo(dsidev, DSI_FIFO_SIZE_32, 3585 DSI_FIFO_SIZE_32, 3586 DSI_FIFO_SIZE_32, 3587 DSI_FIFO_SIZE_32); 3588 3589 /* XXX what values for the timeouts? */ 3590 dsi_set_stop_state_counter(dsidev, 0x1000, false, false); 3591 dsi_set_ta_timeout(dsidev, 0x1fff, true, true); 3592 dsi_set_lp_rx_timeout(dsidev, 0x1fff, true, true); 3593 dsi_set_hs_tx_timeout(dsidev, 0x1fff, true, true); 3594 3595 switch (dsi_get_pixel_size(dsi->pix_fmt)) { 3596 case 16: 3597 buswidth = 0; 3598 break; 3599 case 18: 3600 buswidth = 1; 3601 break; 3602 case 24: 3603 buswidth = 2; 3604 break; 3605 default: 3606 BUG(); 3607 return -EINVAL; 3608 } 3609 3610 r = dsi_read_reg(dsidev, DSI_CTRL); 3611 r = FLD_MOD(r, 1, 1, 1); /* CS_RX_EN */ 3612 r = FLD_MOD(r, 1, 2, 2); /* ECC_RX_EN */ 3613 r = FLD_MOD(r, 1, 3, 3); /* TX_FIFO_ARBITRATION */ 3614 r = FLD_MOD(r, 1, 4, 4); /* VP_CLK_RATIO, always 1, see errata*/ 3615 r = FLD_MOD(r, buswidth, 7, 6); /* VP_DATA_BUS_WIDTH */ 3616 r = FLD_MOD(r, 0, 8, 8); /* VP_CLK_POL */ 3617 r = FLD_MOD(r, 1, 14, 14); /* TRIGGER_RESET_MODE */ 3618 r = FLD_MOD(r, 1, 19, 19); /* EOT_ENABLE */ 3619 if (!dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC)) { 3620 r = FLD_MOD(r, 1, 24, 24); /* DCS_CMD_ENABLE */ 3621 /* DCS_CMD_CODE, 1=start, 0=continue */ 3622 r = FLD_MOD(r, 0, 25, 25); 3623 } 3624 3625 dsi_write_reg(dsidev, DSI_CTRL, r); 3626 3627 dsi_config_vp_num_line_buffers(dsidev); 3628 3629 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) { 3630 dsi_config_vp_sync_events(dsidev); 3631 dsi_config_blanking_modes(dsidev); 3632 dsi_config_cmd_mode_interleaving(dsidev); 3633 } 3634 3635 dsi_vc_initial_config(dsidev, 0); 3636 dsi_vc_initial_config(dsidev, 1); 3637 dsi_vc_initial_config(dsidev, 2); 3638 dsi_vc_initial_config(dsidev, 3); 3639 3640 return 0; 3641 } 3642 3643 static void dsi_proto_timings(struct platform_device *dsidev) 3644 { 3645 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 3646 unsigned tlpx, tclk_zero, tclk_prepare, tclk_trail; 3647 unsigned tclk_pre, tclk_post; 3648 unsigned ths_prepare, ths_prepare_ths_zero, ths_zero; 3649 unsigned ths_trail, ths_exit; 3650 unsigned ddr_clk_pre, ddr_clk_post; 3651 unsigned enter_hs_mode_lat, exit_hs_mode_lat; 3652 unsigned ths_eot; 3653 int ndl = dsi->num_lanes_used - 1; 3654 u32 r; 3655 3656 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0); 3657 ths_prepare = FLD_GET(r, 31, 24); 3658 ths_prepare_ths_zero = FLD_GET(r, 23, 16); 3659 ths_zero = ths_prepare_ths_zero - ths_prepare; 3660 ths_trail = FLD_GET(r, 15, 8); 3661 ths_exit = FLD_GET(r, 7, 0); 3662 3663 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1); 3664 tlpx = FLD_GET(r, 20, 16) * 2; 3665 tclk_trail = FLD_GET(r, 15, 8); 3666 tclk_zero = FLD_GET(r, 7, 0); 3667 3668 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG2); 3669 tclk_prepare = FLD_GET(r, 7, 0); 3670 3671 /* min 8*UI */ 3672 tclk_pre = 20; 3673 /* min 60ns + 52*UI */ 3674 tclk_post = ns2ddr(dsidev, 60) + 26; 3675 3676 ths_eot = DIV_ROUND_UP(4, ndl); 3677 3678 ddr_clk_pre = DIV_ROUND_UP(tclk_pre + tlpx + tclk_zero + tclk_prepare, 3679 4); 3680 ddr_clk_post = DIV_ROUND_UP(tclk_post + ths_trail, 4) + ths_eot; 3681 3682 BUG_ON(ddr_clk_pre == 0 || ddr_clk_pre > 255); 3683 BUG_ON(ddr_clk_post == 0 || ddr_clk_post > 255); 3684 3685 r = dsi_read_reg(dsidev, DSI_CLK_TIMING); 3686 r = FLD_MOD(r, ddr_clk_pre, 15, 8); 3687 r = FLD_MOD(r, ddr_clk_post, 7, 0); 3688 dsi_write_reg(dsidev, DSI_CLK_TIMING, r); 3689 3690 DSSDBG("ddr_clk_pre %u, ddr_clk_post %u\n", 3691 ddr_clk_pre, 3692 ddr_clk_post); 3693 3694 enter_hs_mode_lat = 1 + DIV_ROUND_UP(tlpx, 4) + 3695 DIV_ROUND_UP(ths_prepare, 4) + 3696 DIV_ROUND_UP(ths_zero + 3, 4); 3697 3698 exit_hs_mode_lat = DIV_ROUND_UP(ths_trail + ths_exit, 4) + 1 + ths_eot; 3699 3700 r = FLD_VAL(enter_hs_mode_lat, 31, 16) | 3701 FLD_VAL(exit_hs_mode_lat, 15, 0); 3702 dsi_write_reg(dsidev, DSI_VM_TIMING7, r); 3703 3704 DSSDBG("enter_hs_mode_lat %u, exit_hs_mode_lat %u\n", 3705 enter_hs_mode_lat, exit_hs_mode_lat); 3706 3707 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) { 3708 /* TODO: Implement a video mode check_timings function */ 3709 int hsa = dsi->vm_timings.hsa; 3710 int hfp = dsi->vm_timings.hfp; 3711 int hbp = dsi->vm_timings.hbp; 3712 int vsa = dsi->vm_timings.vsa; 3713 int vfp = dsi->vm_timings.vfp; 3714 int vbp = dsi->vm_timings.vbp; 3715 int window_sync = dsi->vm_timings.window_sync; 3716 bool hsync_end; 3717 struct omap_video_timings *timings = &dsi->timings; 3718 int bpp = dsi_get_pixel_size(dsi->pix_fmt); 3719 int tl, t_he, width_bytes; 3720 3721 hsync_end = dsi->vm_timings.trans_mode == OMAP_DSS_DSI_PULSE_MODE; 3722 t_he = hsync_end ? 3723 ((hsa == 0 && ndl == 3) ? 1 : DIV_ROUND_UP(4, ndl)) : 0; 3724 3725 width_bytes = DIV_ROUND_UP(timings->x_res * bpp, 8); 3726 3727 /* TL = t_HS + HSA + t_HE + HFP + ceil((WC + 6) / NDL) + HBP */ 3728 tl = DIV_ROUND_UP(4, ndl) + (hsync_end ? hsa : 0) + t_he + hfp + 3729 DIV_ROUND_UP(width_bytes + 6, ndl) + hbp; 3730 3731 DSSDBG("HBP: %d, HFP: %d, HSA: %d, TL: %d TXBYTECLKHS\n", hbp, 3732 hfp, hsync_end ? hsa : 0, tl); 3733 DSSDBG("VBP: %d, VFP: %d, VSA: %d, VACT: %d lines\n", vbp, vfp, 3734 vsa, timings->y_res); 3735 3736 r = dsi_read_reg(dsidev, DSI_VM_TIMING1); 3737 r = FLD_MOD(r, hbp, 11, 0); /* HBP */ 3738 r = FLD_MOD(r, hfp, 23, 12); /* HFP */ 3739 r = FLD_MOD(r, hsync_end ? hsa : 0, 31, 24); /* HSA */ 3740 dsi_write_reg(dsidev, DSI_VM_TIMING1, r); 3741 3742 r = dsi_read_reg(dsidev, DSI_VM_TIMING2); 3743 r = FLD_MOD(r, vbp, 7, 0); /* VBP */ 3744 r = FLD_MOD(r, vfp, 15, 8); /* VFP */ 3745 r = FLD_MOD(r, vsa, 23, 16); /* VSA */ 3746 r = FLD_MOD(r, window_sync, 27, 24); /* WINDOW_SYNC */ 3747 dsi_write_reg(dsidev, DSI_VM_TIMING2, r); 3748 3749 r = dsi_read_reg(dsidev, DSI_VM_TIMING3); 3750 r = FLD_MOD(r, timings->y_res, 14, 0); /* VACT */ 3751 r = FLD_MOD(r, tl, 31, 16); /* TL */ 3752 dsi_write_reg(dsidev, DSI_VM_TIMING3, r); 3753 } 3754 } 3755 3756 static int dsi_configure_pins(struct omap_dss_device *dssdev, 3757 const struct omap_dsi_pin_config *pin_cfg) 3758 { 3759 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 3760 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 3761 int num_pins; 3762 const int *pins; 3763 struct dsi_lane_config lanes[DSI_MAX_NR_LANES]; 3764 int num_lanes; 3765 int i; 3766 3767 static const enum dsi_lane_function functions[] = { 3768 DSI_LANE_CLK, 3769 DSI_LANE_DATA1, 3770 DSI_LANE_DATA2, 3771 DSI_LANE_DATA3, 3772 DSI_LANE_DATA4, 3773 }; 3774 3775 num_pins = pin_cfg->num_pins; 3776 pins = pin_cfg->pins; 3777 3778 if (num_pins < 4 || num_pins > dsi->num_lanes_supported * 2 3779 || num_pins % 2 != 0) 3780 return -EINVAL; 3781 3782 for (i = 0; i < DSI_MAX_NR_LANES; ++i) 3783 lanes[i].function = DSI_LANE_UNUSED; 3784 3785 num_lanes = 0; 3786 3787 for (i = 0; i < num_pins; i += 2) { 3788 u8 lane, pol; 3789 int dx, dy; 3790 3791 dx = pins[i]; 3792 dy = pins[i + 1]; 3793 3794 if (dx < 0 || dx >= dsi->num_lanes_supported * 2) 3795 return -EINVAL; 3796 3797 if (dy < 0 || dy >= dsi->num_lanes_supported * 2) 3798 return -EINVAL; 3799 3800 if (dx & 1) { 3801 if (dy != dx - 1) 3802 return -EINVAL; 3803 pol = 1; 3804 } else { 3805 if (dy != dx + 1) 3806 return -EINVAL; 3807 pol = 0; 3808 } 3809 3810 lane = dx / 2; 3811 3812 lanes[lane].function = functions[i / 2]; 3813 lanes[lane].polarity = pol; 3814 num_lanes++; 3815 } 3816 3817 memcpy(dsi->lanes, lanes, sizeof(dsi->lanes)); 3818 dsi->num_lanes_used = num_lanes; 3819 3820 return 0; 3821 } 3822 3823 static int dsi_enable_video_output(struct omap_dss_device *dssdev, int channel) 3824 { 3825 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 3826 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 3827 struct omap_overlay_manager *mgr = dsi->output.manager; 3828 int bpp = dsi_get_pixel_size(dsi->pix_fmt); 3829 struct omap_dss_device *out = &dsi->output; 3830 u8 data_type; 3831 u16 word_count; 3832 int r; 3833 3834 if (out->manager == NULL) { 3835 DSSERR("failed to enable display: no output/manager\n"); 3836 return -ENODEV; 3837 } 3838 3839 r = dsi_display_init_dispc(dsidev, mgr); 3840 if (r) 3841 goto err_init_dispc; 3842 3843 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) { 3844 switch (dsi->pix_fmt) { 3845 case OMAP_DSS_DSI_FMT_RGB888: 3846 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_24; 3847 break; 3848 case OMAP_DSS_DSI_FMT_RGB666: 3849 data_type = MIPI_DSI_PIXEL_STREAM_3BYTE_18; 3850 break; 3851 case OMAP_DSS_DSI_FMT_RGB666_PACKED: 3852 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_18; 3853 break; 3854 case OMAP_DSS_DSI_FMT_RGB565: 3855 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_16; 3856 break; 3857 default: 3858 r = -EINVAL; 3859 goto err_pix_fmt; 3860 } 3861 3862 dsi_if_enable(dsidev, false); 3863 dsi_vc_enable(dsidev, channel, false); 3864 3865 /* MODE, 1 = video mode */ 3866 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 1, 4, 4); 3867 3868 word_count = DIV_ROUND_UP(dsi->timings.x_res * bpp, 8); 3869 3870 dsi_vc_write_long_header(dsidev, channel, data_type, 3871 word_count, 0); 3872 3873 dsi_vc_enable(dsidev, channel, true); 3874 dsi_if_enable(dsidev, true); 3875 } 3876 3877 r = dss_mgr_enable(mgr); 3878 if (r) 3879 goto err_mgr_enable; 3880 3881 return 0; 3882 3883 err_mgr_enable: 3884 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) { 3885 dsi_if_enable(dsidev, false); 3886 dsi_vc_enable(dsidev, channel, false); 3887 } 3888 err_pix_fmt: 3889 dsi_display_uninit_dispc(dsidev, mgr); 3890 err_init_dispc: 3891 return r; 3892 } 3893 3894 static void dsi_disable_video_output(struct omap_dss_device *dssdev, int channel) 3895 { 3896 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 3897 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 3898 struct omap_overlay_manager *mgr = dsi->output.manager; 3899 3900 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) { 3901 dsi_if_enable(dsidev, false); 3902 dsi_vc_enable(dsidev, channel, false); 3903 3904 /* MODE, 0 = command mode */ 3905 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 0, 4, 4); 3906 3907 dsi_vc_enable(dsidev, channel, true); 3908 dsi_if_enable(dsidev, true); 3909 } 3910 3911 dss_mgr_disable(mgr); 3912 3913 dsi_display_uninit_dispc(dsidev, mgr); 3914 } 3915 3916 static void dsi_update_screen_dispc(struct platform_device *dsidev) 3917 { 3918 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 3919 struct omap_overlay_manager *mgr = dsi->output.manager; 3920 unsigned bytespp; 3921 unsigned bytespl; 3922 unsigned bytespf; 3923 unsigned total_len; 3924 unsigned packet_payload; 3925 unsigned packet_len; 3926 u32 l; 3927 int r; 3928 const unsigned channel = dsi->update_channel; 3929 const unsigned line_buf_size = dsi->line_buffer_size; 3930 u16 w = dsi->timings.x_res; 3931 u16 h = dsi->timings.y_res; 3932 3933 DSSDBG("dsi_update_screen_dispc(%dx%d)\n", w, h); 3934 3935 dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_VP); 3936 3937 bytespp = dsi_get_pixel_size(dsi->pix_fmt) / 8; 3938 bytespl = w * bytespp; 3939 bytespf = bytespl * h; 3940 3941 /* NOTE: packet_payload has to be equal to N * bytespl, where N is 3942 * number of lines in a packet. See errata about VP_CLK_RATIO */ 3943 3944 if (bytespf < line_buf_size) 3945 packet_payload = bytespf; 3946 else 3947 packet_payload = (line_buf_size) / bytespl * bytespl; 3948 3949 packet_len = packet_payload + 1; /* 1 byte for DCS cmd */ 3950 total_len = (bytespf / packet_payload) * packet_len; 3951 3952 if (bytespf % packet_payload) 3953 total_len += (bytespf % packet_payload) + 1; 3954 3955 l = FLD_VAL(total_len, 23, 0); /* TE_SIZE */ 3956 dsi_write_reg(dsidev, DSI_VC_TE(channel), l); 3957 3958 dsi_vc_write_long_header(dsidev, channel, MIPI_DSI_DCS_LONG_WRITE, 3959 packet_len, 0); 3960 3961 if (dsi->te_enabled) 3962 l = FLD_MOD(l, 1, 30, 30); /* TE_EN */ 3963 else 3964 l = FLD_MOD(l, 1, 31, 31); /* TE_START */ 3965 dsi_write_reg(dsidev, DSI_VC_TE(channel), l); 3966 3967 /* We put SIDLEMODE to no-idle for the duration of the transfer, 3968 * because DSS interrupts are not capable of waking up the CPU and the 3969 * framedone interrupt could be delayed for quite a long time. I think 3970 * the same goes for any DSS interrupts, but for some reason I have not 3971 * seen the problem anywhere else than here. 3972 */ 3973 dispc_disable_sidle(); 3974 3975 dsi_perf_mark_start(dsidev); 3976 3977 r = schedule_delayed_work(&dsi->framedone_timeout_work, 3978 msecs_to_jiffies(250)); 3979 BUG_ON(r == 0); 3980 3981 dss_mgr_set_timings(mgr, &dsi->timings); 3982 3983 dss_mgr_start_update(mgr); 3984 3985 if (dsi->te_enabled) { 3986 /* disable LP_RX_TO, so that we can receive TE. Time to wait 3987 * for TE is longer than the timer allows */ 3988 REG_FLD_MOD(dsidev, DSI_TIMING2, 0, 15, 15); /* LP_RX_TO */ 3989 3990 dsi_vc_send_bta(dsidev, channel); 3991 3992 #ifdef DSI_CATCH_MISSING_TE 3993 mod_timer(&dsi->te_timer, jiffies + msecs_to_jiffies(250)); 3994 #endif 3995 } 3996 } 3997 3998 #ifdef DSI_CATCH_MISSING_TE 3999 static void dsi_te_timeout(unsigned long arg) 4000 { 4001 DSSERR("TE not received for 250ms!\n"); 4002 } 4003 #endif 4004 4005 static void dsi_handle_framedone(struct platform_device *dsidev, int error) 4006 { 4007 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 4008 4009 /* SIDLEMODE back to smart-idle */ 4010 dispc_enable_sidle(); 4011 4012 if (dsi->te_enabled) { 4013 /* enable LP_RX_TO again after the TE */ 4014 REG_FLD_MOD(dsidev, DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */ 4015 } 4016 4017 dsi->framedone_callback(error, dsi->framedone_data); 4018 4019 if (!error) 4020 dsi_perf_show(dsidev, "DISPC"); 4021 } 4022 4023 static void dsi_framedone_timeout_work_callback(struct work_struct *work) 4024 { 4025 struct dsi_data *dsi = container_of(work, struct dsi_data, 4026 framedone_timeout_work.work); 4027 /* XXX While extremely unlikely, we could get FRAMEDONE interrupt after 4028 * 250ms which would conflict with this timeout work. What should be 4029 * done is first cancel the transfer on the HW, and then cancel the 4030 * possibly scheduled framedone work. However, cancelling the transfer 4031 * on the HW is buggy, and would probably require resetting the whole 4032 * DSI */ 4033 4034 DSSERR("Framedone not received for 250ms!\n"); 4035 4036 dsi_handle_framedone(dsi->pdev, -ETIMEDOUT); 4037 } 4038 4039 static void dsi_framedone_irq_callback(void *data) 4040 { 4041 struct platform_device *dsidev = (struct platform_device *) data; 4042 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 4043 4044 /* Note: We get FRAMEDONE when DISPC has finished sending pixels and 4045 * turns itself off. However, DSI still has the pixels in its buffers, 4046 * and is sending the data. 4047 */ 4048 4049 cancel_delayed_work(&dsi->framedone_timeout_work); 4050 4051 dsi_handle_framedone(dsidev, 0); 4052 } 4053 4054 static int dsi_update(struct omap_dss_device *dssdev, int channel, 4055 void (*callback)(int, void *), void *data) 4056 { 4057 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 4058 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 4059 u16 dw, dh; 4060 4061 dsi_perf_mark_setup(dsidev); 4062 4063 dsi->update_channel = channel; 4064 4065 dsi->framedone_callback = callback; 4066 dsi->framedone_data = data; 4067 4068 dw = dsi->timings.x_res; 4069 dh = dsi->timings.y_res; 4070 4071 #ifdef DSI_PERF_MEASURE 4072 dsi->update_bytes = dw * dh * 4073 dsi_get_pixel_size(dsi->pix_fmt) / 8; 4074 #endif 4075 dsi_update_screen_dispc(dsidev); 4076 4077 return 0; 4078 } 4079 4080 /* Display funcs */ 4081 4082 static int dsi_configure_dispc_clocks(struct platform_device *dsidev) 4083 { 4084 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 4085 struct dispc_clock_info dispc_cinfo; 4086 int r; 4087 unsigned long fck; 4088 4089 fck = dsi_get_pll_hsdiv_dispc_rate(dsidev); 4090 4091 dispc_cinfo.lck_div = dsi->user_dispc_cinfo.lck_div; 4092 dispc_cinfo.pck_div = dsi->user_dispc_cinfo.pck_div; 4093 4094 r = dispc_calc_clock_rates(fck, &dispc_cinfo); 4095 if (r) { 4096 DSSERR("Failed to calc dispc clocks\n"); 4097 return r; 4098 } 4099 4100 dsi->mgr_config.clock_info = dispc_cinfo; 4101 4102 return 0; 4103 } 4104 4105 static int dsi_display_init_dispc(struct platform_device *dsidev, 4106 struct omap_overlay_manager *mgr) 4107 { 4108 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 4109 int r; 4110 4111 dss_select_lcd_clk_source(mgr->id, dsi->module_id == 0 ? 4112 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC : 4113 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC); 4114 4115 if (dsi->mode == OMAP_DSS_DSI_CMD_MODE) { 4116 r = dss_mgr_register_framedone_handler(mgr, 4117 dsi_framedone_irq_callback, dsidev); 4118 if (r) { 4119 DSSERR("can't register FRAMEDONE handler\n"); 4120 goto err; 4121 } 4122 4123 dsi->mgr_config.stallmode = true; 4124 dsi->mgr_config.fifohandcheck = true; 4125 } else { 4126 dsi->mgr_config.stallmode = false; 4127 dsi->mgr_config.fifohandcheck = false; 4128 } 4129 4130 /* 4131 * override interlace, logic level and edge related parameters in 4132 * omap_video_timings with default values 4133 */ 4134 dsi->timings.interlace = false; 4135 dsi->timings.hsync_level = OMAPDSS_SIG_ACTIVE_HIGH; 4136 dsi->timings.vsync_level = OMAPDSS_SIG_ACTIVE_HIGH; 4137 dsi->timings.data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE; 4138 dsi->timings.de_level = OMAPDSS_SIG_ACTIVE_HIGH; 4139 dsi->timings.sync_pclk_edge = OMAPDSS_DRIVE_SIG_FALLING_EDGE; 4140 4141 dss_mgr_set_timings(mgr, &dsi->timings); 4142 4143 r = dsi_configure_dispc_clocks(dsidev); 4144 if (r) 4145 goto err1; 4146 4147 dsi->mgr_config.io_pad_mode = DSS_IO_PAD_MODE_BYPASS; 4148 dsi->mgr_config.video_port_width = 4149 dsi_get_pixel_size(dsi->pix_fmt); 4150 dsi->mgr_config.lcden_sig_polarity = 0; 4151 4152 dss_mgr_set_lcd_config(mgr, &dsi->mgr_config); 4153 4154 return 0; 4155 err1: 4156 if (dsi->mode == OMAP_DSS_DSI_CMD_MODE) 4157 dss_mgr_unregister_framedone_handler(mgr, 4158 dsi_framedone_irq_callback, dsidev); 4159 err: 4160 dss_select_lcd_clk_source(mgr->id, OMAP_DSS_CLK_SRC_FCK); 4161 return r; 4162 } 4163 4164 static void dsi_display_uninit_dispc(struct platform_device *dsidev, 4165 struct omap_overlay_manager *mgr) 4166 { 4167 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 4168 4169 if (dsi->mode == OMAP_DSS_DSI_CMD_MODE) 4170 dss_mgr_unregister_framedone_handler(mgr, 4171 dsi_framedone_irq_callback, dsidev); 4172 4173 dss_select_lcd_clk_source(mgr->id, OMAP_DSS_CLK_SRC_FCK); 4174 } 4175 4176 static int dsi_configure_dsi_clocks(struct platform_device *dsidev) 4177 { 4178 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 4179 struct dss_pll_clock_info cinfo; 4180 int r; 4181 4182 cinfo = dsi->user_dsi_cinfo; 4183 4184 r = dss_pll_set_config(&dsi->pll, &cinfo); 4185 if (r) { 4186 DSSERR("Failed to set dsi clocks\n"); 4187 return r; 4188 } 4189 4190 return 0; 4191 } 4192 4193 static int dsi_display_init_dsi(struct platform_device *dsidev) 4194 { 4195 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 4196 int r; 4197 4198 r = dss_pll_enable(&dsi->pll); 4199 if (r) 4200 goto err0; 4201 4202 r = dsi_configure_dsi_clocks(dsidev); 4203 if (r) 4204 goto err1; 4205 4206 dss_select_dsi_clk_source(dsi->module_id, dsi->module_id == 0 ? 4207 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI : 4208 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI); 4209 4210 DSSDBG("PLL OK\n"); 4211 4212 r = dsi_cio_init(dsidev); 4213 if (r) 4214 goto err2; 4215 4216 _dsi_print_reset_status(dsidev); 4217 4218 dsi_proto_timings(dsidev); 4219 dsi_set_lp_clk_divisor(dsidev); 4220 4221 if (1) 4222 _dsi_print_reset_status(dsidev); 4223 4224 r = dsi_proto_config(dsidev); 4225 if (r) 4226 goto err3; 4227 4228 /* enable interface */ 4229 dsi_vc_enable(dsidev, 0, 1); 4230 dsi_vc_enable(dsidev, 1, 1); 4231 dsi_vc_enable(dsidev, 2, 1); 4232 dsi_vc_enable(dsidev, 3, 1); 4233 dsi_if_enable(dsidev, 1); 4234 dsi_force_tx_stop_mode_io(dsidev); 4235 4236 return 0; 4237 err3: 4238 dsi_cio_uninit(dsidev); 4239 err2: 4240 dss_select_dsi_clk_source(dsi->module_id, OMAP_DSS_CLK_SRC_FCK); 4241 err1: 4242 dss_pll_disable(&dsi->pll); 4243 err0: 4244 return r; 4245 } 4246 4247 static void dsi_display_uninit_dsi(struct platform_device *dsidev, 4248 bool disconnect_lanes, bool enter_ulps) 4249 { 4250 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 4251 4252 if (enter_ulps && !dsi->ulps_enabled) 4253 dsi_enter_ulps(dsidev); 4254 4255 /* disable interface */ 4256 dsi_if_enable(dsidev, 0); 4257 dsi_vc_enable(dsidev, 0, 0); 4258 dsi_vc_enable(dsidev, 1, 0); 4259 dsi_vc_enable(dsidev, 2, 0); 4260 dsi_vc_enable(dsidev, 3, 0); 4261 4262 dss_select_dsi_clk_source(dsi->module_id, OMAP_DSS_CLK_SRC_FCK); 4263 dsi_cio_uninit(dsidev); 4264 dsi_pll_uninit(dsidev, disconnect_lanes); 4265 } 4266 4267 static int dsi_display_enable(struct omap_dss_device *dssdev) 4268 { 4269 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 4270 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 4271 int r = 0; 4272 4273 DSSDBG("dsi_display_enable\n"); 4274 4275 WARN_ON(!dsi_bus_is_locked(dsidev)); 4276 4277 mutex_lock(&dsi->lock); 4278 4279 r = dsi_runtime_get(dsidev); 4280 if (r) 4281 goto err_get_dsi; 4282 4283 _dsi_initialize_irq(dsidev); 4284 4285 r = dsi_display_init_dsi(dsidev); 4286 if (r) 4287 goto err_init_dsi; 4288 4289 mutex_unlock(&dsi->lock); 4290 4291 return 0; 4292 4293 err_init_dsi: 4294 dsi_runtime_put(dsidev); 4295 err_get_dsi: 4296 mutex_unlock(&dsi->lock); 4297 DSSDBG("dsi_display_enable FAILED\n"); 4298 return r; 4299 } 4300 4301 static void dsi_display_disable(struct omap_dss_device *dssdev, 4302 bool disconnect_lanes, bool enter_ulps) 4303 { 4304 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 4305 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 4306 4307 DSSDBG("dsi_display_disable\n"); 4308 4309 WARN_ON(!dsi_bus_is_locked(dsidev)); 4310 4311 mutex_lock(&dsi->lock); 4312 4313 dsi_sync_vc(dsidev, 0); 4314 dsi_sync_vc(dsidev, 1); 4315 dsi_sync_vc(dsidev, 2); 4316 dsi_sync_vc(dsidev, 3); 4317 4318 dsi_display_uninit_dsi(dsidev, disconnect_lanes, enter_ulps); 4319 4320 dsi_runtime_put(dsidev); 4321 4322 mutex_unlock(&dsi->lock); 4323 } 4324 4325 static int dsi_enable_te(struct omap_dss_device *dssdev, bool enable) 4326 { 4327 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 4328 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 4329 4330 dsi->te_enabled = enable; 4331 return 0; 4332 } 4333 4334 #ifdef PRINT_VERBOSE_VM_TIMINGS 4335 static void print_dsi_vm(const char *str, 4336 const struct omap_dss_dsi_videomode_timings *t) 4337 { 4338 unsigned long byteclk = t->hsclk / 4; 4339 int bl, wc, pps, tot; 4340 4341 wc = DIV_ROUND_UP(t->hact * t->bitspp, 8); 4342 pps = DIV_ROUND_UP(wc + 6, t->ndl); /* pixel packet size */ 4343 bl = t->hss + t->hsa + t->hse + t->hbp + t->hfp; 4344 tot = bl + pps; 4345 4346 #define TO_DSI_T(x) ((u32)div64_u64((u64)x * 1000000000llu, byteclk)) 4347 4348 pr_debug("%s bck %lu, %u/%u/%u/%u/%u/%u = %u+%u = %u, " 4349 "%u/%u/%u/%u/%u/%u = %u + %u = %u\n", 4350 str, 4351 byteclk, 4352 t->hss, t->hsa, t->hse, t->hbp, pps, t->hfp, 4353 bl, pps, tot, 4354 TO_DSI_T(t->hss), 4355 TO_DSI_T(t->hsa), 4356 TO_DSI_T(t->hse), 4357 TO_DSI_T(t->hbp), 4358 TO_DSI_T(pps), 4359 TO_DSI_T(t->hfp), 4360 4361 TO_DSI_T(bl), 4362 TO_DSI_T(pps), 4363 4364 TO_DSI_T(tot)); 4365 #undef TO_DSI_T 4366 } 4367 4368 static void print_dispc_vm(const char *str, const struct omap_video_timings *t) 4369 { 4370 unsigned long pck = t->pixelclock; 4371 int hact, bl, tot; 4372 4373 hact = t->x_res; 4374 bl = t->hsw + t->hbp + t->hfp; 4375 tot = hact + bl; 4376 4377 #define TO_DISPC_T(x) ((u32)div64_u64((u64)x * 1000000000llu, pck)) 4378 4379 pr_debug("%s pck %lu, %u/%u/%u/%u = %u+%u = %u, " 4380 "%u/%u/%u/%u = %u + %u = %u\n", 4381 str, 4382 pck, 4383 t->hsw, t->hbp, hact, t->hfp, 4384 bl, hact, tot, 4385 TO_DISPC_T(t->hsw), 4386 TO_DISPC_T(t->hbp), 4387 TO_DISPC_T(hact), 4388 TO_DISPC_T(t->hfp), 4389 TO_DISPC_T(bl), 4390 TO_DISPC_T(hact), 4391 TO_DISPC_T(tot)); 4392 #undef TO_DISPC_T 4393 } 4394 4395 /* note: this is not quite accurate */ 4396 static void print_dsi_dispc_vm(const char *str, 4397 const struct omap_dss_dsi_videomode_timings *t) 4398 { 4399 struct omap_video_timings vm = { 0 }; 4400 unsigned long byteclk = t->hsclk / 4; 4401 unsigned long pck; 4402 u64 dsi_tput; 4403 int dsi_hact, dsi_htot; 4404 4405 dsi_tput = (u64)byteclk * t->ndl * 8; 4406 pck = (u32)div64_u64(dsi_tput, t->bitspp); 4407 dsi_hact = DIV_ROUND_UP(DIV_ROUND_UP(t->hact * t->bitspp, 8) + 6, t->ndl); 4408 dsi_htot = t->hss + t->hsa + t->hse + t->hbp + dsi_hact + t->hfp; 4409 4410 vm.pixelclock = pck; 4411 vm.hsw = div64_u64((u64)(t->hsa + t->hse) * pck, byteclk); 4412 vm.hbp = div64_u64((u64)t->hbp * pck, byteclk); 4413 vm.hfp = div64_u64((u64)t->hfp * pck, byteclk); 4414 vm.x_res = t->hact; 4415 4416 print_dispc_vm(str, &vm); 4417 } 4418 #endif /* PRINT_VERBOSE_VM_TIMINGS */ 4419 4420 static bool dsi_cm_calc_dispc_cb(int lckd, int pckd, unsigned long lck, 4421 unsigned long pck, void *data) 4422 { 4423 struct dsi_clk_calc_ctx *ctx = data; 4424 struct omap_video_timings *t = &ctx->dispc_vm; 4425 4426 ctx->dispc_cinfo.lck_div = lckd; 4427 ctx->dispc_cinfo.pck_div = pckd; 4428 ctx->dispc_cinfo.lck = lck; 4429 ctx->dispc_cinfo.pck = pck; 4430 4431 *t = *ctx->config->timings; 4432 t->pixelclock = pck; 4433 t->x_res = ctx->config->timings->x_res; 4434 t->y_res = ctx->config->timings->y_res; 4435 t->hsw = t->hfp = t->hbp = t->vsw = 1; 4436 t->vfp = t->vbp = 0; 4437 4438 return true; 4439 } 4440 4441 static bool dsi_cm_calc_hsdiv_cb(int m_dispc, unsigned long dispc, 4442 void *data) 4443 { 4444 struct dsi_clk_calc_ctx *ctx = data; 4445 4446 ctx->dsi_cinfo.mX[HSDIV_DISPC] = m_dispc; 4447 ctx->dsi_cinfo.clkout[HSDIV_DISPC] = dispc; 4448 4449 return dispc_div_calc(dispc, ctx->req_pck_min, ctx->req_pck_max, 4450 dsi_cm_calc_dispc_cb, ctx); 4451 } 4452 4453 static bool dsi_cm_calc_pll_cb(int n, int m, unsigned long fint, 4454 unsigned long clkdco, void *data) 4455 { 4456 struct dsi_clk_calc_ctx *ctx = data; 4457 4458 ctx->dsi_cinfo.n = n; 4459 ctx->dsi_cinfo.m = m; 4460 ctx->dsi_cinfo.fint = fint; 4461 ctx->dsi_cinfo.clkdco = clkdco; 4462 4463 return dss_pll_hsdiv_calc(ctx->pll, clkdco, ctx->req_pck_min, 4464 dss_feat_get_param_max(FEAT_PARAM_DSS_FCK), 4465 dsi_cm_calc_hsdiv_cb, ctx); 4466 } 4467 4468 static bool dsi_cm_calc(struct dsi_data *dsi, 4469 const struct omap_dss_dsi_config *cfg, 4470 struct dsi_clk_calc_ctx *ctx) 4471 { 4472 unsigned long clkin; 4473 int bitspp, ndl; 4474 unsigned long pll_min, pll_max; 4475 unsigned long pck, txbyteclk; 4476 4477 clkin = clk_get_rate(dsi->pll.clkin); 4478 bitspp = dsi_get_pixel_size(cfg->pixel_format); 4479 ndl = dsi->num_lanes_used - 1; 4480 4481 /* 4482 * Here we should calculate minimum txbyteclk to be able to send the 4483 * frame in time, and also to handle TE. That's not very simple, though, 4484 * especially as we go to LP between each pixel packet due to HW 4485 * "feature". So let's just estimate very roughly and multiply by 1.5. 4486 */ 4487 pck = cfg->timings->pixelclock; 4488 pck = pck * 3 / 2; 4489 txbyteclk = pck * bitspp / 8 / ndl; 4490 4491 memset(ctx, 0, sizeof(*ctx)); 4492 ctx->dsidev = dsi->pdev; 4493 ctx->pll = &dsi->pll; 4494 ctx->config = cfg; 4495 ctx->req_pck_min = pck; 4496 ctx->req_pck_nom = pck; 4497 ctx->req_pck_max = pck * 3 / 2; 4498 4499 pll_min = max(cfg->hs_clk_min * 4, txbyteclk * 4 * 4); 4500 pll_max = cfg->hs_clk_max * 4; 4501 4502 return dss_pll_calc(ctx->pll, clkin, 4503 pll_min, pll_max, 4504 dsi_cm_calc_pll_cb, ctx); 4505 } 4506 4507 static bool dsi_vm_calc_blanking(struct dsi_clk_calc_ctx *ctx) 4508 { 4509 struct dsi_data *dsi = dsi_get_dsidrv_data(ctx->dsidev); 4510 const struct omap_dss_dsi_config *cfg = ctx->config; 4511 int bitspp = dsi_get_pixel_size(cfg->pixel_format); 4512 int ndl = dsi->num_lanes_used - 1; 4513 unsigned long hsclk = ctx->dsi_cinfo.clkdco / 4; 4514 unsigned long byteclk = hsclk / 4; 4515 4516 unsigned long dispc_pck, req_pck_min, req_pck_nom, req_pck_max; 4517 int xres; 4518 int panel_htot, panel_hbl; /* pixels */ 4519 int dispc_htot, dispc_hbl; /* pixels */ 4520 int dsi_htot, dsi_hact, dsi_hbl, hss, hse; /* byteclks */ 4521 int hfp, hsa, hbp; 4522 const struct omap_video_timings *req_vm; 4523 struct omap_video_timings *dispc_vm; 4524 struct omap_dss_dsi_videomode_timings *dsi_vm; 4525 u64 dsi_tput, dispc_tput; 4526 4527 dsi_tput = (u64)byteclk * ndl * 8; 4528 4529 req_vm = cfg->timings; 4530 req_pck_min = ctx->req_pck_min; 4531 req_pck_max = ctx->req_pck_max; 4532 req_pck_nom = ctx->req_pck_nom; 4533 4534 dispc_pck = ctx->dispc_cinfo.pck; 4535 dispc_tput = (u64)dispc_pck * bitspp; 4536 4537 xres = req_vm->x_res; 4538 4539 panel_hbl = req_vm->hfp + req_vm->hbp + req_vm->hsw; 4540 panel_htot = xres + panel_hbl; 4541 4542 dsi_hact = DIV_ROUND_UP(DIV_ROUND_UP(xres * bitspp, 8) + 6, ndl); 4543 4544 /* 4545 * When there are no line buffers, DISPC and DSI must have the 4546 * same tput. Otherwise DISPC tput needs to be higher than DSI's. 4547 */ 4548 if (dsi->line_buffer_size < xres * bitspp / 8) { 4549 if (dispc_tput != dsi_tput) 4550 return false; 4551 } else { 4552 if (dispc_tput < dsi_tput) 4553 return false; 4554 } 4555 4556 /* DSI tput must be over the min requirement */ 4557 if (dsi_tput < (u64)bitspp * req_pck_min) 4558 return false; 4559 4560 /* When non-burst mode, DSI tput must be below max requirement. */ 4561 if (cfg->trans_mode != OMAP_DSS_DSI_BURST_MODE) { 4562 if (dsi_tput > (u64)bitspp * req_pck_max) 4563 return false; 4564 } 4565 4566 hss = DIV_ROUND_UP(4, ndl); 4567 4568 if (cfg->trans_mode == OMAP_DSS_DSI_PULSE_MODE) { 4569 if (ndl == 3 && req_vm->hsw == 0) 4570 hse = 1; 4571 else 4572 hse = DIV_ROUND_UP(4, ndl); 4573 } else { 4574 hse = 0; 4575 } 4576 4577 /* DSI htot to match the panel's nominal pck */ 4578 dsi_htot = div64_u64((u64)panel_htot * byteclk, req_pck_nom); 4579 4580 /* fail if there would be no time for blanking */ 4581 if (dsi_htot < hss + hse + dsi_hact) 4582 return false; 4583 4584 /* total DSI blanking needed to achieve panel's TL */ 4585 dsi_hbl = dsi_htot - dsi_hact; 4586 4587 /* DISPC htot to match the DSI TL */ 4588 dispc_htot = div64_u64((u64)dsi_htot * dispc_pck, byteclk); 4589 4590 /* verify that the DSI and DISPC TLs are the same */ 4591 if ((u64)dsi_htot * dispc_pck != (u64)dispc_htot * byteclk) 4592 return false; 4593 4594 dispc_hbl = dispc_htot - xres; 4595 4596 /* setup DSI videomode */ 4597 4598 dsi_vm = &ctx->dsi_vm; 4599 memset(dsi_vm, 0, sizeof(*dsi_vm)); 4600 4601 dsi_vm->hsclk = hsclk; 4602 4603 dsi_vm->ndl = ndl; 4604 dsi_vm->bitspp = bitspp; 4605 4606 if (cfg->trans_mode != OMAP_DSS_DSI_PULSE_MODE) { 4607 hsa = 0; 4608 } else if (ndl == 3 && req_vm->hsw == 0) { 4609 hsa = 0; 4610 } else { 4611 hsa = div64_u64((u64)req_vm->hsw * byteclk, req_pck_nom); 4612 hsa = max(hsa - hse, 1); 4613 } 4614 4615 hbp = div64_u64((u64)req_vm->hbp * byteclk, req_pck_nom); 4616 hbp = max(hbp, 1); 4617 4618 hfp = dsi_hbl - (hss + hsa + hse + hbp); 4619 if (hfp < 1) { 4620 int t; 4621 /* we need to take cycles from hbp */ 4622 4623 t = 1 - hfp; 4624 hbp = max(hbp - t, 1); 4625 hfp = dsi_hbl - (hss + hsa + hse + hbp); 4626 4627 if (hfp < 1 && hsa > 0) { 4628 /* we need to take cycles from hsa */ 4629 t = 1 - hfp; 4630 hsa = max(hsa - t, 1); 4631 hfp = dsi_hbl - (hss + hsa + hse + hbp); 4632 } 4633 } 4634 4635 if (hfp < 1) 4636 return false; 4637 4638 dsi_vm->hss = hss; 4639 dsi_vm->hsa = hsa; 4640 dsi_vm->hse = hse; 4641 dsi_vm->hbp = hbp; 4642 dsi_vm->hact = xres; 4643 dsi_vm->hfp = hfp; 4644 4645 dsi_vm->vsa = req_vm->vsw; 4646 dsi_vm->vbp = req_vm->vbp; 4647 dsi_vm->vact = req_vm->y_res; 4648 dsi_vm->vfp = req_vm->vfp; 4649 4650 dsi_vm->trans_mode = cfg->trans_mode; 4651 4652 dsi_vm->blanking_mode = 0; 4653 dsi_vm->hsa_blanking_mode = 1; 4654 dsi_vm->hfp_blanking_mode = 1; 4655 dsi_vm->hbp_blanking_mode = 1; 4656 4657 dsi_vm->ddr_clk_always_on = cfg->ddr_clk_always_on; 4658 dsi_vm->window_sync = 4; 4659 4660 /* setup DISPC videomode */ 4661 4662 dispc_vm = &ctx->dispc_vm; 4663 *dispc_vm = *req_vm; 4664 dispc_vm->pixelclock = dispc_pck; 4665 4666 if (cfg->trans_mode == OMAP_DSS_DSI_PULSE_MODE) { 4667 hsa = div64_u64((u64)req_vm->hsw * dispc_pck, 4668 req_pck_nom); 4669 hsa = max(hsa, 1); 4670 } else { 4671 hsa = 1; 4672 } 4673 4674 hbp = div64_u64((u64)req_vm->hbp * dispc_pck, req_pck_nom); 4675 hbp = max(hbp, 1); 4676 4677 hfp = dispc_hbl - hsa - hbp; 4678 if (hfp < 1) { 4679 int t; 4680 /* we need to take cycles from hbp */ 4681 4682 t = 1 - hfp; 4683 hbp = max(hbp - t, 1); 4684 hfp = dispc_hbl - hsa - hbp; 4685 4686 if (hfp < 1) { 4687 /* we need to take cycles from hsa */ 4688 t = 1 - hfp; 4689 hsa = max(hsa - t, 1); 4690 hfp = dispc_hbl - hsa - hbp; 4691 } 4692 } 4693 4694 if (hfp < 1) 4695 return false; 4696 4697 dispc_vm->hfp = hfp; 4698 dispc_vm->hsw = hsa; 4699 dispc_vm->hbp = hbp; 4700 4701 return true; 4702 } 4703 4704 4705 static bool dsi_vm_calc_dispc_cb(int lckd, int pckd, unsigned long lck, 4706 unsigned long pck, void *data) 4707 { 4708 struct dsi_clk_calc_ctx *ctx = data; 4709 4710 ctx->dispc_cinfo.lck_div = lckd; 4711 ctx->dispc_cinfo.pck_div = pckd; 4712 ctx->dispc_cinfo.lck = lck; 4713 ctx->dispc_cinfo.pck = pck; 4714 4715 if (dsi_vm_calc_blanking(ctx) == false) 4716 return false; 4717 4718 #ifdef PRINT_VERBOSE_VM_TIMINGS 4719 print_dispc_vm("dispc", &ctx->dispc_vm); 4720 print_dsi_vm("dsi ", &ctx->dsi_vm); 4721 print_dispc_vm("req ", ctx->config->timings); 4722 print_dsi_dispc_vm("act ", &ctx->dsi_vm); 4723 #endif 4724 4725 return true; 4726 } 4727 4728 static bool dsi_vm_calc_hsdiv_cb(int m_dispc, unsigned long dispc, 4729 void *data) 4730 { 4731 struct dsi_clk_calc_ctx *ctx = data; 4732 unsigned long pck_max; 4733 4734 ctx->dsi_cinfo.mX[HSDIV_DISPC] = m_dispc; 4735 ctx->dsi_cinfo.clkout[HSDIV_DISPC] = dispc; 4736 4737 /* 4738 * In burst mode we can let the dispc pck be arbitrarily high, but it 4739 * limits our scaling abilities. So for now, don't aim too high. 4740 */ 4741 4742 if (ctx->config->trans_mode == OMAP_DSS_DSI_BURST_MODE) 4743 pck_max = ctx->req_pck_max + 10000000; 4744 else 4745 pck_max = ctx->req_pck_max; 4746 4747 return dispc_div_calc(dispc, ctx->req_pck_min, pck_max, 4748 dsi_vm_calc_dispc_cb, ctx); 4749 } 4750 4751 static bool dsi_vm_calc_pll_cb(int n, int m, unsigned long fint, 4752 unsigned long clkdco, void *data) 4753 { 4754 struct dsi_clk_calc_ctx *ctx = data; 4755 4756 ctx->dsi_cinfo.n = n; 4757 ctx->dsi_cinfo.m = m; 4758 ctx->dsi_cinfo.fint = fint; 4759 ctx->dsi_cinfo.clkdco = clkdco; 4760 4761 return dss_pll_hsdiv_calc(ctx->pll, clkdco, ctx->req_pck_min, 4762 dss_feat_get_param_max(FEAT_PARAM_DSS_FCK), 4763 dsi_vm_calc_hsdiv_cb, ctx); 4764 } 4765 4766 static bool dsi_vm_calc(struct dsi_data *dsi, 4767 const struct omap_dss_dsi_config *cfg, 4768 struct dsi_clk_calc_ctx *ctx) 4769 { 4770 const struct omap_video_timings *t = cfg->timings; 4771 unsigned long clkin; 4772 unsigned long pll_min; 4773 unsigned long pll_max; 4774 int ndl = dsi->num_lanes_used - 1; 4775 int bitspp = dsi_get_pixel_size(cfg->pixel_format); 4776 unsigned long byteclk_min; 4777 4778 clkin = clk_get_rate(dsi->pll.clkin); 4779 4780 memset(ctx, 0, sizeof(*ctx)); 4781 ctx->dsidev = dsi->pdev; 4782 ctx->pll = &dsi->pll; 4783 ctx->config = cfg; 4784 4785 /* these limits should come from the panel driver */ 4786 ctx->req_pck_min = t->pixelclock - 1000; 4787 ctx->req_pck_nom = t->pixelclock; 4788 ctx->req_pck_max = t->pixelclock + 1000; 4789 4790 byteclk_min = div64_u64((u64)ctx->req_pck_min * bitspp, ndl * 8); 4791 pll_min = max(cfg->hs_clk_min * 4, byteclk_min * 4 * 4); 4792 4793 if (cfg->trans_mode == OMAP_DSS_DSI_BURST_MODE) { 4794 pll_max = cfg->hs_clk_max * 4; 4795 } else { 4796 unsigned long byteclk_max; 4797 byteclk_max = div64_u64((u64)ctx->req_pck_max * bitspp, 4798 ndl * 8); 4799 4800 pll_max = byteclk_max * 4 * 4; 4801 } 4802 4803 return dss_pll_calc(ctx->pll, clkin, 4804 pll_min, pll_max, 4805 dsi_vm_calc_pll_cb, ctx); 4806 } 4807 4808 static int dsi_set_config(struct omap_dss_device *dssdev, 4809 const struct omap_dss_dsi_config *config) 4810 { 4811 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 4812 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 4813 struct dsi_clk_calc_ctx ctx; 4814 bool ok; 4815 int r; 4816 4817 mutex_lock(&dsi->lock); 4818 4819 dsi->pix_fmt = config->pixel_format; 4820 dsi->mode = config->mode; 4821 4822 if (config->mode == OMAP_DSS_DSI_VIDEO_MODE) 4823 ok = dsi_vm_calc(dsi, config, &ctx); 4824 else 4825 ok = dsi_cm_calc(dsi, config, &ctx); 4826 4827 if (!ok) { 4828 DSSERR("failed to find suitable DSI clock settings\n"); 4829 r = -EINVAL; 4830 goto err; 4831 } 4832 4833 dsi_pll_calc_dsi_fck(&ctx.dsi_cinfo); 4834 4835 r = dsi_lp_clock_calc(ctx.dsi_cinfo.clkout[HSDIV_DSI], 4836 config->lp_clk_min, config->lp_clk_max, &dsi->user_lp_cinfo); 4837 if (r) { 4838 DSSERR("failed to find suitable DSI LP clock settings\n"); 4839 goto err; 4840 } 4841 4842 dsi->user_dsi_cinfo = ctx.dsi_cinfo; 4843 dsi->user_dispc_cinfo = ctx.dispc_cinfo; 4844 4845 dsi->timings = ctx.dispc_vm; 4846 dsi->vm_timings = ctx.dsi_vm; 4847 4848 mutex_unlock(&dsi->lock); 4849 4850 return 0; 4851 err: 4852 mutex_unlock(&dsi->lock); 4853 4854 return r; 4855 } 4856 4857 /* 4858 * Return a hardcoded channel for the DSI output. This should work for 4859 * current use cases, but this can be later expanded to either resolve 4860 * the channel in some more dynamic manner, or get the channel as a user 4861 * parameter. 4862 */ 4863 static enum omap_channel dsi_get_channel(int module_id) 4864 { 4865 switch (omapdss_get_version()) { 4866 case OMAPDSS_VER_OMAP24xx: 4867 case OMAPDSS_VER_AM43xx: 4868 DSSWARN("DSI not supported\n"); 4869 return OMAP_DSS_CHANNEL_LCD; 4870 4871 case OMAPDSS_VER_OMAP34xx_ES1: 4872 case OMAPDSS_VER_OMAP34xx_ES3: 4873 case OMAPDSS_VER_OMAP3630: 4874 case OMAPDSS_VER_AM35xx: 4875 return OMAP_DSS_CHANNEL_LCD; 4876 4877 case OMAPDSS_VER_OMAP4430_ES1: 4878 case OMAPDSS_VER_OMAP4430_ES2: 4879 case OMAPDSS_VER_OMAP4: 4880 switch (module_id) { 4881 case 0: 4882 return OMAP_DSS_CHANNEL_LCD; 4883 case 1: 4884 return OMAP_DSS_CHANNEL_LCD2; 4885 default: 4886 DSSWARN("unsupported module id\n"); 4887 return OMAP_DSS_CHANNEL_LCD; 4888 } 4889 4890 case OMAPDSS_VER_OMAP5: 4891 switch (module_id) { 4892 case 0: 4893 return OMAP_DSS_CHANNEL_LCD; 4894 case 1: 4895 return OMAP_DSS_CHANNEL_LCD3; 4896 default: 4897 DSSWARN("unsupported module id\n"); 4898 return OMAP_DSS_CHANNEL_LCD; 4899 } 4900 4901 default: 4902 DSSWARN("unsupported DSS version\n"); 4903 return OMAP_DSS_CHANNEL_LCD; 4904 } 4905 } 4906 4907 static int dsi_request_vc(struct omap_dss_device *dssdev, int *channel) 4908 { 4909 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 4910 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 4911 int i; 4912 4913 for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) { 4914 if (!dsi->vc[i].dssdev) { 4915 dsi->vc[i].dssdev = dssdev; 4916 *channel = i; 4917 return 0; 4918 } 4919 } 4920 4921 DSSERR("cannot get VC for display %s", dssdev->name); 4922 return -ENOSPC; 4923 } 4924 4925 static int dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id) 4926 { 4927 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 4928 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 4929 4930 if (vc_id < 0 || vc_id > 3) { 4931 DSSERR("VC ID out of range\n"); 4932 return -EINVAL; 4933 } 4934 4935 if (channel < 0 || channel > 3) { 4936 DSSERR("Virtual Channel out of range\n"); 4937 return -EINVAL; 4938 } 4939 4940 if (dsi->vc[channel].dssdev != dssdev) { 4941 DSSERR("Virtual Channel not allocated to display %s\n", 4942 dssdev->name); 4943 return -EINVAL; 4944 } 4945 4946 dsi->vc[channel].vc_id = vc_id; 4947 4948 return 0; 4949 } 4950 4951 static void dsi_release_vc(struct omap_dss_device *dssdev, int channel) 4952 { 4953 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 4954 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 4955 4956 if ((channel >= 0 && channel <= 3) && 4957 dsi->vc[channel].dssdev == dssdev) { 4958 dsi->vc[channel].dssdev = NULL; 4959 dsi->vc[channel].vc_id = 0; 4960 } 4961 } 4962 4963 4964 static int dsi_get_clocks(struct platform_device *dsidev) 4965 { 4966 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 4967 struct clk *clk; 4968 4969 clk = devm_clk_get(&dsidev->dev, "fck"); 4970 if (IS_ERR(clk)) { 4971 DSSERR("can't get fck\n"); 4972 return PTR_ERR(clk); 4973 } 4974 4975 dsi->dss_clk = clk; 4976 4977 return 0; 4978 } 4979 4980 static int dsi_connect(struct omap_dss_device *dssdev, 4981 struct omap_dss_device *dst) 4982 { 4983 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 4984 struct omap_overlay_manager *mgr; 4985 int r; 4986 4987 r = dsi_regulator_init(dsidev); 4988 if (r) 4989 return r; 4990 4991 mgr = omap_dss_get_overlay_manager(dssdev->dispc_channel); 4992 if (!mgr) 4993 return -ENODEV; 4994 4995 r = dss_mgr_connect(mgr, dssdev); 4996 if (r) 4997 return r; 4998 4999 r = omapdss_output_set_device(dssdev, dst); 5000 if (r) { 5001 DSSERR("failed to connect output to new device: %s\n", 5002 dssdev->name); 5003 dss_mgr_disconnect(mgr, dssdev); 5004 return r; 5005 } 5006 5007 return 0; 5008 } 5009 5010 static void dsi_disconnect(struct omap_dss_device *dssdev, 5011 struct omap_dss_device *dst) 5012 { 5013 WARN_ON(dst != dssdev->dst); 5014 5015 if (dst != dssdev->dst) 5016 return; 5017 5018 omapdss_output_unset_device(dssdev); 5019 5020 if (dssdev->manager) 5021 dss_mgr_disconnect(dssdev->manager, dssdev); 5022 } 5023 5024 static const struct omapdss_dsi_ops dsi_ops = { 5025 .connect = dsi_connect, 5026 .disconnect = dsi_disconnect, 5027 5028 .bus_lock = dsi_bus_lock, 5029 .bus_unlock = dsi_bus_unlock, 5030 5031 .enable = dsi_display_enable, 5032 .disable = dsi_display_disable, 5033 5034 .enable_hs = dsi_vc_enable_hs, 5035 5036 .configure_pins = dsi_configure_pins, 5037 .set_config = dsi_set_config, 5038 5039 .enable_video_output = dsi_enable_video_output, 5040 .disable_video_output = dsi_disable_video_output, 5041 5042 .update = dsi_update, 5043 5044 .enable_te = dsi_enable_te, 5045 5046 .request_vc = dsi_request_vc, 5047 .set_vc_id = dsi_set_vc_id, 5048 .release_vc = dsi_release_vc, 5049 5050 .dcs_write = dsi_vc_dcs_write, 5051 .dcs_write_nosync = dsi_vc_dcs_write_nosync, 5052 .dcs_read = dsi_vc_dcs_read, 5053 5054 .gen_write = dsi_vc_generic_write, 5055 .gen_write_nosync = dsi_vc_generic_write_nosync, 5056 .gen_read = dsi_vc_generic_read, 5057 5058 .bta_sync = dsi_vc_send_bta_sync, 5059 5060 .set_max_rx_packet_size = dsi_vc_set_max_rx_packet_size, 5061 }; 5062 5063 static void dsi_init_output(struct platform_device *dsidev) 5064 { 5065 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 5066 struct omap_dss_device *out = &dsi->output; 5067 5068 out->dev = &dsidev->dev; 5069 out->id = dsi->module_id == 0 ? 5070 OMAP_DSS_OUTPUT_DSI1 : OMAP_DSS_OUTPUT_DSI2; 5071 5072 out->output_type = OMAP_DISPLAY_TYPE_DSI; 5073 out->name = dsi->module_id == 0 ? "dsi.0" : "dsi.1"; 5074 out->dispc_channel = dsi_get_channel(dsi->module_id); 5075 out->ops.dsi = &dsi_ops; 5076 out->owner = THIS_MODULE; 5077 5078 omapdss_register_output(out); 5079 } 5080 5081 static void dsi_uninit_output(struct platform_device *dsidev) 5082 { 5083 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 5084 struct omap_dss_device *out = &dsi->output; 5085 5086 omapdss_unregister_output(out); 5087 } 5088 5089 static int dsi_probe_of(struct platform_device *pdev) 5090 { 5091 struct device_node *node = pdev->dev.of_node; 5092 struct dsi_data *dsi = dsi_get_dsidrv_data(pdev); 5093 struct property *prop; 5094 u32 lane_arr[10]; 5095 int len, num_pins; 5096 int r, i; 5097 struct device_node *ep; 5098 struct omap_dsi_pin_config pin_cfg; 5099 5100 ep = omapdss_of_get_first_endpoint(node); 5101 if (!ep) 5102 return 0; 5103 5104 prop = of_find_property(ep, "lanes", &len); 5105 if (prop == NULL) { 5106 dev_err(&pdev->dev, "failed to find lane data\n"); 5107 r = -EINVAL; 5108 goto err; 5109 } 5110 5111 num_pins = len / sizeof(u32); 5112 5113 if (num_pins < 4 || num_pins % 2 != 0 || 5114 num_pins > dsi->num_lanes_supported * 2) { 5115 dev_err(&pdev->dev, "bad number of lanes\n"); 5116 r = -EINVAL; 5117 goto err; 5118 } 5119 5120 r = of_property_read_u32_array(ep, "lanes", lane_arr, num_pins); 5121 if (r) { 5122 dev_err(&pdev->dev, "failed to read lane data\n"); 5123 goto err; 5124 } 5125 5126 pin_cfg.num_pins = num_pins; 5127 for (i = 0; i < num_pins; ++i) 5128 pin_cfg.pins[i] = (int)lane_arr[i]; 5129 5130 r = dsi_configure_pins(&dsi->output, &pin_cfg); 5131 if (r) { 5132 dev_err(&pdev->dev, "failed to configure pins"); 5133 goto err; 5134 } 5135 5136 of_node_put(ep); 5137 5138 return 0; 5139 5140 err: 5141 of_node_put(ep); 5142 return r; 5143 } 5144 5145 static const struct dss_pll_ops dsi_pll_ops = { 5146 .enable = dsi_pll_enable, 5147 .disable = dsi_pll_disable, 5148 .set_config = dss_pll_write_config_type_a, 5149 }; 5150 5151 static const struct dss_pll_hw dss_omap3_dsi_pll_hw = { 5152 .n_max = (1 << 7) - 1, 5153 .m_max = (1 << 11) - 1, 5154 .mX_max = (1 << 4) - 1, 5155 .fint_min = 750000, 5156 .fint_max = 2100000, 5157 .clkdco_low = 1000000000, 5158 .clkdco_max = 1800000000, 5159 5160 .n_msb = 7, 5161 .n_lsb = 1, 5162 .m_msb = 18, 5163 .m_lsb = 8, 5164 5165 .mX_msb[0] = 22, 5166 .mX_lsb[0] = 19, 5167 .mX_msb[1] = 26, 5168 .mX_lsb[1] = 23, 5169 5170 .has_stopmode = true, 5171 .has_freqsel = true, 5172 .has_selfreqdco = false, 5173 .has_refsel = false, 5174 }; 5175 5176 static const struct dss_pll_hw dss_omap4_dsi_pll_hw = { 5177 .n_max = (1 << 8) - 1, 5178 .m_max = (1 << 12) - 1, 5179 .mX_max = (1 << 5) - 1, 5180 .fint_min = 500000, 5181 .fint_max = 2500000, 5182 .clkdco_low = 1000000000, 5183 .clkdco_max = 1800000000, 5184 5185 .n_msb = 8, 5186 .n_lsb = 1, 5187 .m_msb = 20, 5188 .m_lsb = 9, 5189 5190 .mX_msb[0] = 25, 5191 .mX_lsb[0] = 21, 5192 .mX_msb[1] = 30, 5193 .mX_lsb[1] = 26, 5194 5195 .has_stopmode = true, 5196 .has_freqsel = false, 5197 .has_selfreqdco = false, 5198 .has_refsel = false, 5199 }; 5200 5201 static const struct dss_pll_hw dss_omap5_dsi_pll_hw = { 5202 .n_max = (1 << 8) - 1, 5203 .m_max = (1 << 12) - 1, 5204 .mX_max = (1 << 5) - 1, 5205 .fint_min = 150000, 5206 .fint_max = 52000000, 5207 .clkdco_low = 1000000000, 5208 .clkdco_max = 1800000000, 5209 5210 .n_msb = 8, 5211 .n_lsb = 1, 5212 .m_msb = 20, 5213 .m_lsb = 9, 5214 5215 .mX_msb[0] = 25, 5216 .mX_lsb[0] = 21, 5217 .mX_msb[1] = 30, 5218 .mX_lsb[1] = 26, 5219 5220 .has_stopmode = true, 5221 .has_freqsel = false, 5222 .has_selfreqdco = true, 5223 .has_refsel = true, 5224 }; 5225 5226 static int dsi_init_pll_data(struct platform_device *dsidev) 5227 { 5228 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 5229 struct dss_pll *pll = &dsi->pll; 5230 struct clk *clk; 5231 int r; 5232 5233 clk = devm_clk_get(&dsidev->dev, "sys_clk"); 5234 if (IS_ERR(clk)) { 5235 DSSERR("can't get sys_clk\n"); 5236 return PTR_ERR(clk); 5237 } 5238 5239 pll->name = dsi->module_id == 0 ? "dsi0" : "dsi1"; 5240 pll->id = dsi->module_id == 0 ? DSS_PLL_DSI1 : DSS_PLL_DSI2; 5241 pll->clkin = clk; 5242 pll->base = dsi->pll_base; 5243 5244 switch (omapdss_get_version()) { 5245 case OMAPDSS_VER_OMAP34xx_ES1: 5246 case OMAPDSS_VER_OMAP34xx_ES3: 5247 case OMAPDSS_VER_OMAP3630: 5248 case OMAPDSS_VER_AM35xx: 5249 pll->hw = &dss_omap3_dsi_pll_hw; 5250 break; 5251 5252 case OMAPDSS_VER_OMAP4430_ES1: 5253 case OMAPDSS_VER_OMAP4430_ES2: 5254 case OMAPDSS_VER_OMAP4: 5255 pll->hw = &dss_omap4_dsi_pll_hw; 5256 break; 5257 5258 case OMAPDSS_VER_OMAP5: 5259 pll->hw = &dss_omap5_dsi_pll_hw; 5260 break; 5261 5262 default: 5263 return -ENODEV; 5264 } 5265 5266 pll->ops = &dsi_pll_ops; 5267 5268 r = dss_pll_register(pll); 5269 if (r) 5270 return r; 5271 5272 return 0; 5273 } 5274 5275 /* DSI1 HW IP initialisation */ 5276 static int dsi_bind(struct device *dev, struct device *master, void *data) 5277 { 5278 struct platform_device *dsidev = to_platform_device(dev); 5279 u32 rev; 5280 int r, i; 5281 struct dsi_data *dsi; 5282 struct resource *dsi_mem; 5283 struct resource *res; 5284 struct resource temp_res; 5285 5286 dsi = devm_kzalloc(&dsidev->dev, sizeof(*dsi), GFP_KERNEL); 5287 if (!dsi) 5288 return -ENOMEM; 5289 5290 dsi->pdev = dsidev; 5291 dev_set_drvdata(&dsidev->dev, dsi); 5292 5293 spin_lock_init(&dsi->irq_lock); 5294 spin_lock_init(&dsi->errors_lock); 5295 dsi->errors = 0; 5296 5297 #ifdef CONFIG_FB_OMAP2_DSS_COLLECT_IRQ_STATS 5298 spin_lock_init(&dsi->irq_stats_lock); 5299 dsi->irq_stats.last_reset = jiffies; 5300 #endif 5301 5302 mutex_init(&dsi->lock); 5303 sema_init(&dsi->bus_lock, 1); 5304 5305 INIT_DEFERRABLE_WORK(&dsi->framedone_timeout_work, 5306 dsi_framedone_timeout_work_callback); 5307 5308 #ifdef DSI_CATCH_MISSING_TE 5309 init_timer(&dsi->te_timer); 5310 dsi->te_timer.function = dsi_te_timeout; 5311 dsi->te_timer.data = 0; 5312 #endif 5313 5314 res = platform_get_resource_byname(dsidev, IORESOURCE_MEM, "proto"); 5315 if (!res) { 5316 res = platform_get_resource(dsidev, IORESOURCE_MEM, 0); 5317 if (!res) { 5318 DSSERR("can't get IORESOURCE_MEM DSI\n"); 5319 return -EINVAL; 5320 } 5321 5322 temp_res.start = res->start; 5323 temp_res.end = temp_res.start + DSI_PROTO_SZ - 1; 5324 res = &temp_res; 5325 } 5326 5327 dsi_mem = res; 5328 5329 dsi->proto_base = devm_ioremap(&dsidev->dev, res->start, 5330 resource_size(res)); 5331 if (!dsi->proto_base) { 5332 DSSERR("can't ioremap DSI protocol engine\n"); 5333 return -ENOMEM; 5334 } 5335 5336 res = platform_get_resource_byname(dsidev, IORESOURCE_MEM, "phy"); 5337 if (!res) { 5338 res = platform_get_resource(dsidev, IORESOURCE_MEM, 0); 5339 if (!res) { 5340 DSSERR("can't get IORESOURCE_MEM DSI\n"); 5341 return -EINVAL; 5342 } 5343 5344 temp_res.start = res->start + DSI_PHY_OFFSET; 5345 temp_res.end = temp_res.start + DSI_PHY_SZ - 1; 5346 res = &temp_res; 5347 } 5348 5349 dsi->phy_base = devm_ioremap(&dsidev->dev, res->start, 5350 resource_size(res)); 5351 if (!dsi->proto_base) { 5352 DSSERR("can't ioremap DSI PHY\n"); 5353 return -ENOMEM; 5354 } 5355 5356 res = platform_get_resource_byname(dsidev, IORESOURCE_MEM, "pll"); 5357 if (!res) { 5358 res = platform_get_resource(dsidev, IORESOURCE_MEM, 0); 5359 if (!res) { 5360 DSSERR("can't get IORESOURCE_MEM DSI\n"); 5361 return -EINVAL; 5362 } 5363 5364 temp_res.start = res->start + DSI_PLL_OFFSET; 5365 temp_res.end = temp_res.start + DSI_PLL_SZ - 1; 5366 res = &temp_res; 5367 } 5368 5369 dsi->pll_base = devm_ioremap(&dsidev->dev, res->start, 5370 resource_size(res)); 5371 if (!dsi->proto_base) { 5372 DSSERR("can't ioremap DSI PLL\n"); 5373 return -ENOMEM; 5374 } 5375 5376 dsi->irq = platform_get_irq(dsi->pdev, 0); 5377 if (dsi->irq < 0) { 5378 DSSERR("platform_get_irq failed\n"); 5379 return -ENODEV; 5380 } 5381 5382 r = devm_request_irq(&dsidev->dev, dsi->irq, omap_dsi_irq_handler, 5383 IRQF_SHARED, dev_name(&dsidev->dev), dsi->pdev); 5384 if (r < 0) { 5385 DSSERR("request_irq failed\n"); 5386 return r; 5387 } 5388 5389 if (dsidev->dev.of_node) { 5390 const struct of_device_id *match; 5391 const struct dsi_module_id_data *d; 5392 5393 match = of_match_node(dsi_of_match, dsidev->dev.of_node); 5394 if (!match) { 5395 DSSERR("unsupported DSI module\n"); 5396 return -ENODEV; 5397 } 5398 5399 d = match->data; 5400 5401 while (d->address != 0 && d->address != dsi_mem->start) 5402 d++; 5403 5404 if (d->address == 0) { 5405 DSSERR("unsupported DSI module\n"); 5406 return -ENODEV; 5407 } 5408 5409 dsi->module_id = d->id; 5410 } else { 5411 dsi->module_id = dsidev->id; 5412 } 5413 5414 /* DSI VCs initialization */ 5415 for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) { 5416 dsi->vc[i].source = DSI_VC_SOURCE_L4; 5417 dsi->vc[i].dssdev = NULL; 5418 dsi->vc[i].vc_id = 0; 5419 } 5420 5421 r = dsi_get_clocks(dsidev); 5422 if (r) 5423 return r; 5424 5425 dsi_init_pll_data(dsidev); 5426 5427 pm_runtime_enable(&dsidev->dev); 5428 5429 r = dsi_runtime_get(dsidev); 5430 if (r) 5431 goto err_runtime_get; 5432 5433 rev = dsi_read_reg(dsidev, DSI_REVISION); 5434 dev_dbg(&dsidev->dev, "OMAP DSI rev %d.%d\n", 5435 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0)); 5436 5437 /* DSI on OMAP3 doesn't have register DSI_GNQ, set number 5438 * of data to 3 by default */ 5439 if (dss_has_feature(FEAT_DSI_GNQ)) 5440 /* NB_DATA_LANES */ 5441 dsi->num_lanes_supported = 1 + REG_GET(dsidev, DSI_GNQ, 11, 9); 5442 else 5443 dsi->num_lanes_supported = 3; 5444 5445 dsi->line_buffer_size = dsi_get_line_buf_size(dsidev); 5446 5447 dsi_init_output(dsidev); 5448 5449 if (dsidev->dev.of_node) { 5450 r = dsi_probe_of(dsidev); 5451 if (r) { 5452 DSSERR("Invalid DSI DT data\n"); 5453 goto err_probe_of; 5454 } 5455 5456 r = of_platform_populate(dsidev->dev.of_node, NULL, NULL, 5457 &dsidev->dev); 5458 if (r) 5459 DSSERR("Failed to populate DSI child devices: %d\n", r); 5460 } 5461 5462 dsi_runtime_put(dsidev); 5463 5464 if (dsi->module_id == 0) 5465 dss_debugfs_create_file("dsi1_regs", dsi1_dump_regs); 5466 else if (dsi->module_id == 1) 5467 dss_debugfs_create_file("dsi2_regs", dsi2_dump_regs); 5468 5469 #ifdef CONFIG_FB_OMAP2_DSS_COLLECT_IRQ_STATS 5470 if (dsi->module_id == 0) 5471 dss_debugfs_create_file("dsi1_irqs", dsi1_dump_irqs); 5472 else if (dsi->module_id == 1) 5473 dss_debugfs_create_file("dsi2_irqs", dsi2_dump_irqs); 5474 #endif 5475 5476 return 0; 5477 5478 err_probe_of: 5479 dsi_uninit_output(dsidev); 5480 dsi_runtime_put(dsidev); 5481 5482 err_runtime_get: 5483 pm_runtime_disable(&dsidev->dev); 5484 return r; 5485 } 5486 5487 static void dsi_unbind(struct device *dev, struct device *master, void *data) 5488 { 5489 struct platform_device *dsidev = to_platform_device(dev); 5490 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 5491 5492 of_platform_depopulate(&dsidev->dev); 5493 5494 WARN_ON(dsi->scp_clk_refcount > 0); 5495 5496 dss_pll_unregister(&dsi->pll); 5497 5498 dsi_uninit_output(dsidev); 5499 5500 pm_runtime_disable(&dsidev->dev); 5501 5502 if (dsi->vdds_dsi_reg != NULL && dsi->vdds_dsi_enabled) { 5503 regulator_disable(dsi->vdds_dsi_reg); 5504 dsi->vdds_dsi_enabled = false; 5505 } 5506 } 5507 5508 static const struct component_ops dsi_component_ops = { 5509 .bind = dsi_bind, 5510 .unbind = dsi_unbind, 5511 }; 5512 5513 static int dsi_probe(struct platform_device *pdev) 5514 { 5515 return component_add(&pdev->dev, &dsi_component_ops); 5516 } 5517 5518 static int dsi_remove(struct platform_device *pdev) 5519 { 5520 component_del(&pdev->dev, &dsi_component_ops); 5521 return 0; 5522 } 5523 5524 static int dsi_runtime_suspend(struct device *dev) 5525 { 5526 struct platform_device *pdev = to_platform_device(dev); 5527 struct dsi_data *dsi = dsi_get_dsidrv_data(pdev); 5528 5529 dsi->is_enabled = false; 5530 /* ensure the irq handler sees the is_enabled value */ 5531 smp_wmb(); 5532 /* wait for current handler to finish before turning the DSI off */ 5533 synchronize_irq(dsi->irq); 5534 5535 dispc_runtime_put(); 5536 5537 return 0; 5538 } 5539 5540 static int dsi_runtime_resume(struct device *dev) 5541 { 5542 struct platform_device *pdev = to_platform_device(dev); 5543 struct dsi_data *dsi = dsi_get_dsidrv_data(pdev); 5544 int r; 5545 5546 r = dispc_runtime_get(); 5547 if (r) 5548 return r; 5549 5550 dsi->is_enabled = true; 5551 /* ensure the irq handler sees the is_enabled value */ 5552 smp_wmb(); 5553 5554 return 0; 5555 } 5556 5557 static const struct dev_pm_ops dsi_pm_ops = { 5558 .runtime_suspend = dsi_runtime_suspend, 5559 .runtime_resume = dsi_runtime_resume, 5560 }; 5561 5562 static const struct dsi_module_id_data dsi_of_data_omap3[] = { 5563 { .address = 0x4804fc00, .id = 0, }, 5564 { }, 5565 }; 5566 5567 static const struct dsi_module_id_data dsi_of_data_omap4[] = { 5568 { .address = 0x58004000, .id = 0, }, 5569 { .address = 0x58005000, .id = 1, }, 5570 { }, 5571 }; 5572 5573 static const struct dsi_module_id_data dsi_of_data_omap5[] = { 5574 { .address = 0x58004000, .id = 0, }, 5575 { .address = 0x58009000, .id = 1, }, 5576 { }, 5577 }; 5578 5579 static const struct of_device_id dsi_of_match[] = { 5580 { .compatible = "ti,omap3-dsi", .data = dsi_of_data_omap3, }, 5581 { .compatible = "ti,omap4-dsi", .data = dsi_of_data_omap4, }, 5582 { .compatible = "ti,omap5-dsi", .data = dsi_of_data_omap5, }, 5583 {}, 5584 }; 5585 5586 static struct platform_driver omap_dsihw_driver = { 5587 .probe = dsi_probe, 5588 .remove = dsi_remove, 5589 .driver = { 5590 .name = "omapdss_dsi", 5591 .pm = &dsi_pm_ops, 5592 .of_match_table = dsi_of_match, 5593 .suppress_bind_attrs = true, 5594 }, 5595 }; 5596 5597 int __init dsi_init_platform_driver(void) 5598 { 5599 return platform_driver_register(&omap_dsihw_driver); 5600 } 5601 5602 void dsi_uninit_platform_driver(void) 5603 { 5604 platform_driver_unregister(&omap_dsihw_driver); 5605 } 5606