1 /*
2  * linux/drivers/video/omap2/dss/dsi.c
3  *
4  * Copyright (C) 2009 Nokia Corporation
5  * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6  *
7  * This program is free software; you can redistribute it and/or modify it
8  * under the terms of the GNU General Public License version 2 as published by
9  * the Free Software Foundation.
10  *
11  * This program is distributed in the hope that it will be useful, but WITHOUT
12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
14  * more details.
15  *
16  * You should have received a copy of the GNU General Public License along with
17  * this program.  If not, see <http://www.gnu.org/licenses/>.
18  */
19 
20 #define DSS_SUBSYS_NAME "DSI"
21 
22 #include <linux/kernel.h>
23 #include <linux/io.h>
24 #include <linux/clk.h>
25 #include <linux/device.h>
26 #include <linux/err.h>
27 #include <linux/interrupt.h>
28 #include <linux/delay.h>
29 #include <linux/mutex.h>
30 #include <linux/module.h>
31 #include <linux/semaphore.h>
32 #include <linux/seq_file.h>
33 #include <linux/platform_device.h>
34 #include <linux/regulator/consumer.h>
35 #include <linux/wait.h>
36 #include <linux/workqueue.h>
37 #include <linux/sched.h>
38 #include <linux/slab.h>
39 #include <linux/debugfs.h>
40 #include <linux/pm_runtime.h>
41 #include <linux/of.h>
42 #include <linux/of_platform.h>
43 #include <linux/component.h>
44 
45 #include <video/omapfb_dss.h>
46 #include <video/mipi_display.h>
47 
48 #include "dss.h"
49 #include "dss_features.h"
50 
51 #define DSI_CATCH_MISSING_TE
52 
53 struct dsi_reg { u16 module; u16 idx; };
54 
55 #define DSI_REG(mod, idx)		((const struct dsi_reg) { mod, idx })
56 
57 /* DSI Protocol Engine */
58 
59 #define DSI_PROTO			0
60 #define DSI_PROTO_SZ			0x200
61 
62 #define DSI_REVISION			DSI_REG(DSI_PROTO, 0x0000)
63 #define DSI_SYSCONFIG			DSI_REG(DSI_PROTO, 0x0010)
64 #define DSI_SYSSTATUS			DSI_REG(DSI_PROTO, 0x0014)
65 #define DSI_IRQSTATUS			DSI_REG(DSI_PROTO, 0x0018)
66 #define DSI_IRQENABLE			DSI_REG(DSI_PROTO, 0x001C)
67 #define DSI_CTRL			DSI_REG(DSI_PROTO, 0x0040)
68 #define DSI_GNQ				DSI_REG(DSI_PROTO, 0x0044)
69 #define DSI_COMPLEXIO_CFG1		DSI_REG(DSI_PROTO, 0x0048)
70 #define DSI_COMPLEXIO_IRQ_STATUS	DSI_REG(DSI_PROTO, 0x004C)
71 #define DSI_COMPLEXIO_IRQ_ENABLE	DSI_REG(DSI_PROTO, 0x0050)
72 #define DSI_CLK_CTRL			DSI_REG(DSI_PROTO, 0x0054)
73 #define DSI_TIMING1			DSI_REG(DSI_PROTO, 0x0058)
74 #define DSI_TIMING2			DSI_REG(DSI_PROTO, 0x005C)
75 #define DSI_VM_TIMING1			DSI_REG(DSI_PROTO, 0x0060)
76 #define DSI_VM_TIMING2			DSI_REG(DSI_PROTO, 0x0064)
77 #define DSI_VM_TIMING3			DSI_REG(DSI_PROTO, 0x0068)
78 #define DSI_CLK_TIMING			DSI_REG(DSI_PROTO, 0x006C)
79 #define DSI_TX_FIFO_VC_SIZE		DSI_REG(DSI_PROTO, 0x0070)
80 #define DSI_RX_FIFO_VC_SIZE		DSI_REG(DSI_PROTO, 0x0074)
81 #define DSI_COMPLEXIO_CFG2		DSI_REG(DSI_PROTO, 0x0078)
82 #define DSI_RX_FIFO_VC_FULLNESS		DSI_REG(DSI_PROTO, 0x007C)
83 #define DSI_VM_TIMING4			DSI_REG(DSI_PROTO, 0x0080)
84 #define DSI_TX_FIFO_VC_EMPTINESS	DSI_REG(DSI_PROTO, 0x0084)
85 #define DSI_VM_TIMING5			DSI_REG(DSI_PROTO, 0x0088)
86 #define DSI_VM_TIMING6			DSI_REG(DSI_PROTO, 0x008C)
87 #define DSI_VM_TIMING7			DSI_REG(DSI_PROTO, 0x0090)
88 #define DSI_STOPCLK_TIMING		DSI_REG(DSI_PROTO, 0x0094)
89 #define DSI_VC_CTRL(n)			DSI_REG(DSI_PROTO, 0x0100 + (n * 0x20))
90 #define DSI_VC_TE(n)			DSI_REG(DSI_PROTO, 0x0104 + (n * 0x20))
91 #define DSI_VC_LONG_PACKET_HEADER(n)	DSI_REG(DSI_PROTO, 0x0108 + (n * 0x20))
92 #define DSI_VC_LONG_PACKET_PAYLOAD(n)	DSI_REG(DSI_PROTO, 0x010C + (n * 0x20))
93 #define DSI_VC_SHORT_PACKET_HEADER(n)	DSI_REG(DSI_PROTO, 0x0110 + (n * 0x20))
94 #define DSI_VC_IRQSTATUS(n)		DSI_REG(DSI_PROTO, 0x0118 + (n * 0x20))
95 #define DSI_VC_IRQENABLE(n)		DSI_REG(DSI_PROTO, 0x011C + (n * 0x20))
96 
97 /* DSIPHY_SCP */
98 
99 #define DSI_PHY				1
100 #define DSI_PHY_OFFSET			0x200
101 #define DSI_PHY_SZ			0x40
102 
103 #define DSI_DSIPHY_CFG0			DSI_REG(DSI_PHY, 0x0000)
104 #define DSI_DSIPHY_CFG1			DSI_REG(DSI_PHY, 0x0004)
105 #define DSI_DSIPHY_CFG2			DSI_REG(DSI_PHY, 0x0008)
106 #define DSI_DSIPHY_CFG5			DSI_REG(DSI_PHY, 0x0014)
107 #define DSI_DSIPHY_CFG10		DSI_REG(DSI_PHY, 0x0028)
108 
109 /* DSI_PLL_CTRL_SCP */
110 
111 #define DSI_PLL				2
112 #define DSI_PLL_OFFSET			0x300
113 #define DSI_PLL_SZ			0x20
114 
115 #define DSI_PLL_CONTROL			DSI_REG(DSI_PLL, 0x0000)
116 #define DSI_PLL_STATUS			DSI_REG(DSI_PLL, 0x0004)
117 #define DSI_PLL_GO			DSI_REG(DSI_PLL, 0x0008)
118 #define DSI_PLL_CONFIGURATION1		DSI_REG(DSI_PLL, 0x000C)
119 #define DSI_PLL_CONFIGURATION2		DSI_REG(DSI_PLL, 0x0010)
120 
121 #define REG_GET(dsidev, idx, start, end) \
122 	FLD_GET(dsi_read_reg(dsidev, idx), start, end)
123 
124 #define REG_FLD_MOD(dsidev, idx, val, start, end) \
125 	dsi_write_reg(dsidev, idx, FLD_MOD(dsi_read_reg(dsidev, idx), val, start, end))
126 
127 /* Global interrupts */
128 #define DSI_IRQ_VC0		(1 << 0)
129 #define DSI_IRQ_VC1		(1 << 1)
130 #define DSI_IRQ_VC2		(1 << 2)
131 #define DSI_IRQ_VC3		(1 << 3)
132 #define DSI_IRQ_WAKEUP		(1 << 4)
133 #define DSI_IRQ_RESYNC		(1 << 5)
134 #define DSI_IRQ_PLL_LOCK	(1 << 7)
135 #define DSI_IRQ_PLL_UNLOCK	(1 << 8)
136 #define DSI_IRQ_PLL_RECALL	(1 << 9)
137 #define DSI_IRQ_COMPLEXIO_ERR	(1 << 10)
138 #define DSI_IRQ_HS_TX_TIMEOUT	(1 << 14)
139 #define DSI_IRQ_LP_RX_TIMEOUT	(1 << 15)
140 #define DSI_IRQ_TE_TRIGGER	(1 << 16)
141 #define DSI_IRQ_ACK_TRIGGER	(1 << 17)
142 #define DSI_IRQ_SYNC_LOST	(1 << 18)
143 #define DSI_IRQ_LDO_POWER_GOOD	(1 << 19)
144 #define DSI_IRQ_TA_TIMEOUT	(1 << 20)
145 #define DSI_IRQ_ERROR_MASK \
146 	(DSI_IRQ_HS_TX_TIMEOUT | DSI_IRQ_LP_RX_TIMEOUT | DSI_IRQ_SYNC_LOST | \
147 	DSI_IRQ_TA_TIMEOUT)
148 #define DSI_IRQ_CHANNEL_MASK	0xf
149 
150 /* Virtual channel interrupts */
151 #define DSI_VC_IRQ_CS		(1 << 0)
152 #define DSI_VC_IRQ_ECC_CORR	(1 << 1)
153 #define DSI_VC_IRQ_PACKET_SENT	(1 << 2)
154 #define DSI_VC_IRQ_FIFO_TX_OVF	(1 << 3)
155 #define DSI_VC_IRQ_FIFO_RX_OVF	(1 << 4)
156 #define DSI_VC_IRQ_BTA		(1 << 5)
157 #define DSI_VC_IRQ_ECC_NO_CORR	(1 << 6)
158 #define DSI_VC_IRQ_FIFO_TX_UDF	(1 << 7)
159 #define DSI_VC_IRQ_PP_BUSY_CHANGE (1 << 8)
160 #define DSI_VC_IRQ_ERROR_MASK \
161 	(DSI_VC_IRQ_CS | DSI_VC_IRQ_ECC_CORR | DSI_VC_IRQ_FIFO_TX_OVF | \
162 	DSI_VC_IRQ_FIFO_RX_OVF | DSI_VC_IRQ_ECC_NO_CORR | \
163 	DSI_VC_IRQ_FIFO_TX_UDF)
164 
165 /* ComplexIO interrupts */
166 #define DSI_CIO_IRQ_ERRSYNCESC1		(1 << 0)
167 #define DSI_CIO_IRQ_ERRSYNCESC2		(1 << 1)
168 #define DSI_CIO_IRQ_ERRSYNCESC3		(1 << 2)
169 #define DSI_CIO_IRQ_ERRSYNCESC4		(1 << 3)
170 #define DSI_CIO_IRQ_ERRSYNCESC5		(1 << 4)
171 #define DSI_CIO_IRQ_ERRESC1		(1 << 5)
172 #define DSI_CIO_IRQ_ERRESC2		(1 << 6)
173 #define DSI_CIO_IRQ_ERRESC3		(1 << 7)
174 #define DSI_CIO_IRQ_ERRESC4		(1 << 8)
175 #define DSI_CIO_IRQ_ERRESC5		(1 << 9)
176 #define DSI_CIO_IRQ_ERRCONTROL1		(1 << 10)
177 #define DSI_CIO_IRQ_ERRCONTROL2		(1 << 11)
178 #define DSI_CIO_IRQ_ERRCONTROL3		(1 << 12)
179 #define DSI_CIO_IRQ_ERRCONTROL4		(1 << 13)
180 #define DSI_CIO_IRQ_ERRCONTROL5		(1 << 14)
181 #define DSI_CIO_IRQ_STATEULPS1		(1 << 15)
182 #define DSI_CIO_IRQ_STATEULPS2		(1 << 16)
183 #define DSI_CIO_IRQ_STATEULPS3		(1 << 17)
184 #define DSI_CIO_IRQ_STATEULPS4		(1 << 18)
185 #define DSI_CIO_IRQ_STATEULPS5		(1 << 19)
186 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_1	(1 << 20)
187 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_1	(1 << 21)
188 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_2	(1 << 22)
189 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_2	(1 << 23)
190 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_3	(1 << 24)
191 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_3	(1 << 25)
192 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_4	(1 << 26)
193 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_4	(1 << 27)
194 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_5	(1 << 28)
195 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_5	(1 << 29)
196 #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL0	(1 << 30)
197 #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL1	(1 << 31)
198 #define DSI_CIO_IRQ_ERROR_MASK \
199 	(DSI_CIO_IRQ_ERRSYNCESC1 | DSI_CIO_IRQ_ERRSYNCESC2 | \
200 	 DSI_CIO_IRQ_ERRSYNCESC3 | DSI_CIO_IRQ_ERRSYNCESC4 | \
201 	 DSI_CIO_IRQ_ERRSYNCESC5 | \
202 	 DSI_CIO_IRQ_ERRESC1 | DSI_CIO_IRQ_ERRESC2 | \
203 	 DSI_CIO_IRQ_ERRESC3 | DSI_CIO_IRQ_ERRESC4 | \
204 	 DSI_CIO_IRQ_ERRESC5 | \
205 	 DSI_CIO_IRQ_ERRCONTROL1 | DSI_CIO_IRQ_ERRCONTROL2 | \
206 	 DSI_CIO_IRQ_ERRCONTROL3 | DSI_CIO_IRQ_ERRCONTROL4 | \
207 	 DSI_CIO_IRQ_ERRCONTROL5 | \
208 	 DSI_CIO_IRQ_ERRCONTENTIONLP0_1 | DSI_CIO_IRQ_ERRCONTENTIONLP1_1 | \
209 	 DSI_CIO_IRQ_ERRCONTENTIONLP0_2 | DSI_CIO_IRQ_ERRCONTENTIONLP1_2 | \
210 	 DSI_CIO_IRQ_ERRCONTENTIONLP0_3 | DSI_CIO_IRQ_ERRCONTENTIONLP1_3 | \
211 	 DSI_CIO_IRQ_ERRCONTENTIONLP0_4 | DSI_CIO_IRQ_ERRCONTENTIONLP1_4 | \
212 	 DSI_CIO_IRQ_ERRCONTENTIONLP0_5 | DSI_CIO_IRQ_ERRCONTENTIONLP1_5)
213 
214 typedef void (*omap_dsi_isr_t) (void *arg, u32 mask);
215 
216 static int dsi_display_init_dispc(struct platform_device *dsidev,
217 	struct omap_overlay_manager *mgr);
218 static void dsi_display_uninit_dispc(struct platform_device *dsidev,
219 	struct omap_overlay_manager *mgr);
220 
221 static int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel);
222 
223 /* DSI PLL HSDIV indices */
224 #define HSDIV_DISPC	0
225 #define HSDIV_DSI	1
226 
227 #define DSI_MAX_NR_ISRS                2
228 #define DSI_MAX_NR_LANES	5
229 
230 enum dsi_lane_function {
231 	DSI_LANE_UNUSED	= 0,
232 	DSI_LANE_CLK,
233 	DSI_LANE_DATA1,
234 	DSI_LANE_DATA2,
235 	DSI_LANE_DATA3,
236 	DSI_LANE_DATA4,
237 };
238 
239 struct dsi_lane_config {
240 	enum dsi_lane_function function;
241 	u8 polarity;
242 };
243 
244 struct dsi_isr_data {
245 	omap_dsi_isr_t	isr;
246 	void		*arg;
247 	u32		mask;
248 };
249 
250 enum fifo_size {
251 	DSI_FIFO_SIZE_0		= 0,
252 	DSI_FIFO_SIZE_32	= 1,
253 	DSI_FIFO_SIZE_64	= 2,
254 	DSI_FIFO_SIZE_96	= 3,
255 	DSI_FIFO_SIZE_128	= 4,
256 };
257 
258 enum dsi_vc_source {
259 	DSI_VC_SOURCE_L4 = 0,
260 	DSI_VC_SOURCE_VP,
261 };
262 
263 struct dsi_irq_stats {
264 	unsigned long last_reset;
265 	unsigned irq_count;
266 	unsigned dsi_irqs[32];
267 	unsigned vc_irqs[4][32];
268 	unsigned cio_irqs[32];
269 };
270 
271 struct dsi_isr_tables {
272 	struct dsi_isr_data isr_table[DSI_MAX_NR_ISRS];
273 	struct dsi_isr_data isr_table_vc[4][DSI_MAX_NR_ISRS];
274 	struct dsi_isr_data isr_table_cio[DSI_MAX_NR_ISRS];
275 };
276 
277 struct dsi_clk_calc_ctx {
278 	struct platform_device *dsidev;
279 	struct dss_pll *pll;
280 
281 	/* inputs */
282 
283 	const struct omap_dss_dsi_config *config;
284 
285 	unsigned long req_pck_min, req_pck_nom, req_pck_max;
286 
287 	/* outputs */
288 
289 	struct dss_pll_clock_info dsi_cinfo;
290 	struct dispc_clock_info dispc_cinfo;
291 
292 	struct omap_video_timings dispc_vm;
293 	struct omap_dss_dsi_videomode_timings dsi_vm;
294 };
295 
296 struct dsi_lp_clock_info {
297 	unsigned long lp_clk;
298 	u16 lp_clk_div;
299 };
300 
301 struct dsi_data {
302 	struct platform_device *pdev;
303 	void __iomem *proto_base;
304 	void __iomem *phy_base;
305 	void __iomem *pll_base;
306 
307 	int module_id;
308 
309 	int irq;
310 
311 	bool is_enabled;
312 
313 	struct clk *dss_clk;
314 
315 	struct dispc_clock_info user_dispc_cinfo;
316 	struct dss_pll_clock_info user_dsi_cinfo;
317 
318 	struct dsi_lp_clock_info user_lp_cinfo;
319 	struct dsi_lp_clock_info current_lp_cinfo;
320 
321 	struct dss_pll pll;
322 
323 	bool vdds_dsi_enabled;
324 	struct regulator *vdds_dsi_reg;
325 
326 	struct {
327 		enum dsi_vc_source source;
328 		struct omap_dss_device *dssdev;
329 		enum fifo_size tx_fifo_size;
330 		enum fifo_size rx_fifo_size;
331 		int vc_id;
332 	} vc[4];
333 
334 	struct mutex lock;
335 	struct semaphore bus_lock;
336 
337 	spinlock_t irq_lock;
338 	struct dsi_isr_tables isr_tables;
339 	/* space for a copy used by the interrupt handler */
340 	struct dsi_isr_tables isr_tables_copy;
341 
342 	int update_channel;
343 #ifdef DSI_PERF_MEASURE
344 	unsigned update_bytes;
345 #endif
346 
347 	bool te_enabled;
348 	bool ulps_enabled;
349 
350 	void (*framedone_callback)(int, void *);
351 	void *framedone_data;
352 
353 	struct delayed_work framedone_timeout_work;
354 
355 #ifdef DSI_CATCH_MISSING_TE
356 	struct timer_list te_timer;
357 #endif
358 
359 	unsigned long cache_req_pck;
360 	unsigned long cache_clk_freq;
361 	struct dss_pll_clock_info cache_cinfo;
362 
363 	u32		errors;
364 	spinlock_t	errors_lock;
365 #ifdef DSI_PERF_MEASURE
366 	ktime_t perf_setup_time;
367 	ktime_t perf_start_time;
368 #endif
369 	int debug_read;
370 	int debug_write;
371 
372 #ifdef CONFIG_FB_OMAP2_DSS_COLLECT_IRQ_STATS
373 	spinlock_t irq_stats_lock;
374 	struct dsi_irq_stats irq_stats;
375 #endif
376 
377 	unsigned num_lanes_supported;
378 	unsigned line_buffer_size;
379 
380 	struct dsi_lane_config lanes[DSI_MAX_NR_LANES];
381 	unsigned num_lanes_used;
382 
383 	unsigned scp_clk_refcount;
384 
385 	struct dss_lcd_mgr_config mgr_config;
386 	struct omap_video_timings timings;
387 	enum omap_dss_dsi_pixel_format pix_fmt;
388 	enum omap_dss_dsi_mode mode;
389 	struct omap_dss_dsi_videomode_timings vm_timings;
390 
391 	struct omap_dss_device output;
392 };
393 
394 struct dsi_packet_sent_handler_data {
395 	struct platform_device *dsidev;
396 	struct completion *completion;
397 };
398 
399 struct dsi_module_id_data {
400 	u32 address;
401 	int id;
402 };
403 
404 static const struct of_device_id dsi_of_match[];
405 
406 #ifdef DSI_PERF_MEASURE
407 static bool dsi_perf;
408 module_param(dsi_perf, bool, 0644);
409 #endif
410 
411 static inline struct dsi_data *dsi_get_dsidrv_data(struct platform_device *dsidev)
412 {
413 	return dev_get_drvdata(&dsidev->dev);
414 }
415 
416 static inline struct platform_device *dsi_get_dsidev_from_dssdev(struct omap_dss_device *dssdev)
417 {
418 	return to_platform_device(dssdev->dev);
419 }
420 
421 static struct platform_device *dsi_get_dsidev_from_id(int module)
422 {
423 	struct omap_dss_device *out;
424 	enum omap_dss_output_id	id;
425 
426 	switch (module) {
427 	case 0:
428 		id = OMAP_DSS_OUTPUT_DSI1;
429 		break;
430 	case 1:
431 		id = OMAP_DSS_OUTPUT_DSI2;
432 		break;
433 	default:
434 		return NULL;
435 	}
436 
437 	out = omap_dss_get_output(id);
438 
439 	return out ? to_platform_device(out->dev) : NULL;
440 }
441 
442 static inline void dsi_write_reg(struct platform_device *dsidev,
443 		const struct dsi_reg idx, u32 val)
444 {
445 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
446 	void __iomem *base;
447 
448 	switch(idx.module) {
449 		case DSI_PROTO: base = dsi->proto_base; break;
450 		case DSI_PHY: base = dsi->phy_base; break;
451 		case DSI_PLL: base = dsi->pll_base; break;
452 		default: return;
453 	}
454 
455 	__raw_writel(val, base + idx.idx);
456 }
457 
458 static inline u32 dsi_read_reg(struct platform_device *dsidev,
459 		const struct dsi_reg idx)
460 {
461 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
462 	void __iomem *base;
463 
464 	switch(idx.module) {
465 		case DSI_PROTO: base = dsi->proto_base; break;
466 		case DSI_PHY: base = dsi->phy_base; break;
467 		case DSI_PLL: base = dsi->pll_base; break;
468 		default: return 0;
469 	}
470 
471 	return __raw_readl(base + idx.idx);
472 }
473 
474 static void dsi_bus_lock(struct omap_dss_device *dssdev)
475 {
476 	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
477 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
478 
479 	down(&dsi->bus_lock);
480 }
481 
482 static void dsi_bus_unlock(struct omap_dss_device *dssdev)
483 {
484 	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
485 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
486 
487 	up(&dsi->bus_lock);
488 }
489 
490 static bool dsi_bus_is_locked(struct platform_device *dsidev)
491 {
492 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
493 
494 	return dsi->bus_lock.count == 0;
495 }
496 
497 static void dsi_completion_handler(void *data, u32 mask)
498 {
499 	complete((struct completion *)data);
500 }
501 
502 static inline int wait_for_bit_change(struct platform_device *dsidev,
503 		const struct dsi_reg idx, int bitnum, int value)
504 {
505 	unsigned long timeout;
506 	ktime_t wait;
507 	int t;
508 
509 	/* first busyloop to see if the bit changes right away */
510 	t = 100;
511 	while (t-- > 0) {
512 		if (REG_GET(dsidev, idx, bitnum, bitnum) == value)
513 			return value;
514 	}
515 
516 	/* then loop for 500ms, sleeping for 1ms in between */
517 	timeout = jiffies + msecs_to_jiffies(500);
518 	while (time_before(jiffies, timeout)) {
519 		if (REG_GET(dsidev, idx, bitnum, bitnum) == value)
520 			return value;
521 
522 		wait = ns_to_ktime(1000 * 1000);
523 		set_current_state(TASK_UNINTERRUPTIBLE);
524 		schedule_hrtimeout(&wait, HRTIMER_MODE_REL);
525 	}
526 
527 	return !value;
528 }
529 
530 u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt)
531 {
532 	switch (fmt) {
533 	case OMAP_DSS_DSI_FMT_RGB888:
534 	case OMAP_DSS_DSI_FMT_RGB666:
535 		return 24;
536 	case OMAP_DSS_DSI_FMT_RGB666_PACKED:
537 		return 18;
538 	case OMAP_DSS_DSI_FMT_RGB565:
539 		return 16;
540 	default:
541 		BUG();
542 		return 0;
543 	}
544 }
545 
546 #ifdef DSI_PERF_MEASURE
547 static void dsi_perf_mark_setup(struct platform_device *dsidev)
548 {
549 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
550 	dsi->perf_setup_time = ktime_get();
551 }
552 
553 static void dsi_perf_mark_start(struct platform_device *dsidev)
554 {
555 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
556 	dsi->perf_start_time = ktime_get();
557 }
558 
559 static void dsi_perf_show(struct platform_device *dsidev, const char *name)
560 {
561 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
562 	ktime_t t, setup_time, trans_time;
563 	u32 total_bytes;
564 	u32 setup_us, trans_us, total_us;
565 
566 	if (!dsi_perf)
567 		return;
568 
569 	t = ktime_get();
570 
571 	setup_time = ktime_sub(dsi->perf_start_time, dsi->perf_setup_time);
572 	setup_us = (u32)ktime_to_us(setup_time);
573 	if (setup_us == 0)
574 		setup_us = 1;
575 
576 	trans_time = ktime_sub(t, dsi->perf_start_time);
577 	trans_us = (u32)ktime_to_us(trans_time);
578 	if (trans_us == 0)
579 		trans_us = 1;
580 
581 	total_us = setup_us + trans_us;
582 
583 	total_bytes = dsi->update_bytes;
584 
585 	printk(KERN_INFO "DSI(%s): %u us + %u us = %u us (%uHz), "
586 			"%u bytes, %u kbytes/sec\n",
587 			name,
588 			setup_us,
589 			trans_us,
590 			total_us,
591 			1000*1000 / total_us,
592 			total_bytes,
593 			total_bytes * 1000 / total_us);
594 }
595 #else
596 static inline void dsi_perf_mark_setup(struct platform_device *dsidev)
597 {
598 }
599 
600 static inline void dsi_perf_mark_start(struct platform_device *dsidev)
601 {
602 }
603 
604 static inline void dsi_perf_show(struct platform_device *dsidev,
605 		const char *name)
606 {
607 }
608 #endif
609 
610 static int verbose_irq;
611 
612 static void print_irq_status(u32 status)
613 {
614 	if (status == 0)
615 		return;
616 
617 	if (!verbose_irq && (status & ~DSI_IRQ_CHANNEL_MASK) == 0)
618 		return;
619 
620 #define PIS(x) (status & DSI_IRQ_##x) ? (#x " ") : ""
621 
622 	pr_debug("DSI IRQ: 0x%x: %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n",
623 		status,
624 		verbose_irq ? PIS(VC0) : "",
625 		verbose_irq ? PIS(VC1) : "",
626 		verbose_irq ? PIS(VC2) : "",
627 		verbose_irq ? PIS(VC3) : "",
628 		PIS(WAKEUP),
629 		PIS(RESYNC),
630 		PIS(PLL_LOCK),
631 		PIS(PLL_UNLOCK),
632 		PIS(PLL_RECALL),
633 		PIS(COMPLEXIO_ERR),
634 		PIS(HS_TX_TIMEOUT),
635 		PIS(LP_RX_TIMEOUT),
636 		PIS(TE_TRIGGER),
637 		PIS(ACK_TRIGGER),
638 		PIS(SYNC_LOST),
639 		PIS(LDO_POWER_GOOD),
640 		PIS(TA_TIMEOUT));
641 #undef PIS
642 }
643 
644 static void print_irq_status_vc(int channel, u32 status)
645 {
646 	if (status == 0)
647 		return;
648 
649 	if (!verbose_irq && (status & ~DSI_VC_IRQ_PACKET_SENT) == 0)
650 		return;
651 
652 #define PIS(x) (status & DSI_VC_IRQ_##x) ? (#x " ") : ""
653 
654 	pr_debug("DSI VC(%d) IRQ 0x%x: %s%s%s%s%s%s%s%s%s\n",
655 		channel,
656 		status,
657 		PIS(CS),
658 		PIS(ECC_CORR),
659 		PIS(ECC_NO_CORR),
660 		verbose_irq ? PIS(PACKET_SENT) : "",
661 		PIS(BTA),
662 		PIS(FIFO_TX_OVF),
663 		PIS(FIFO_RX_OVF),
664 		PIS(FIFO_TX_UDF),
665 		PIS(PP_BUSY_CHANGE));
666 #undef PIS
667 }
668 
669 static void print_irq_status_cio(u32 status)
670 {
671 	if (status == 0)
672 		return;
673 
674 #define PIS(x) (status & DSI_CIO_IRQ_##x) ? (#x " ") : ""
675 
676 	pr_debug("DSI CIO IRQ 0x%x: %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n",
677 		status,
678 		PIS(ERRSYNCESC1),
679 		PIS(ERRSYNCESC2),
680 		PIS(ERRSYNCESC3),
681 		PIS(ERRESC1),
682 		PIS(ERRESC2),
683 		PIS(ERRESC3),
684 		PIS(ERRCONTROL1),
685 		PIS(ERRCONTROL2),
686 		PIS(ERRCONTROL3),
687 		PIS(STATEULPS1),
688 		PIS(STATEULPS2),
689 		PIS(STATEULPS3),
690 		PIS(ERRCONTENTIONLP0_1),
691 		PIS(ERRCONTENTIONLP1_1),
692 		PIS(ERRCONTENTIONLP0_2),
693 		PIS(ERRCONTENTIONLP1_2),
694 		PIS(ERRCONTENTIONLP0_3),
695 		PIS(ERRCONTENTIONLP1_3),
696 		PIS(ULPSACTIVENOT_ALL0),
697 		PIS(ULPSACTIVENOT_ALL1));
698 #undef PIS
699 }
700 
701 #ifdef CONFIG_FB_OMAP2_DSS_COLLECT_IRQ_STATS
702 static void dsi_collect_irq_stats(struct platform_device *dsidev, u32 irqstatus,
703 		u32 *vcstatus, u32 ciostatus)
704 {
705 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
706 	int i;
707 
708 	spin_lock(&dsi->irq_stats_lock);
709 
710 	dsi->irq_stats.irq_count++;
711 	dss_collect_irq_stats(irqstatus, dsi->irq_stats.dsi_irqs);
712 
713 	for (i = 0; i < 4; ++i)
714 		dss_collect_irq_stats(vcstatus[i], dsi->irq_stats.vc_irqs[i]);
715 
716 	dss_collect_irq_stats(ciostatus, dsi->irq_stats.cio_irqs);
717 
718 	spin_unlock(&dsi->irq_stats_lock);
719 }
720 #else
721 #define dsi_collect_irq_stats(dsidev, irqstatus, vcstatus, ciostatus)
722 #endif
723 
724 static int debug_irq;
725 
726 static void dsi_handle_irq_errors(struct platform_device *dsidev, u32 irqstatus,
727 		u32 *vcstatus, u32 ciostatus)
728 {
729 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
730 	int i;
731 
732 	if (irqstatus & DSI_IRQ_ERROR_MASK) {
733 		DSSERR("DSI error, irqstatus %x\n", irqstatus);
734 		print_irq_status(irqstatus);
735 		spin_lock(&dsi->errors_lock);
736 		dsi->errors |= irqstatus & DSI_IRQ_ERROR_MASK;
737 		spin_unlock(&dsi->errors_lock);
738 	} else if (debug_irq) {
739 		print_irq_status(irqstatus);
740 	}
741 
742 	for (i = 0; i < 4; ++i) {
743 		if (vcstatus[i] & DSI_VC_IRQ_ERROR_MASK) {
744 			DSSERR("DSI VC(%d) error, vc irqstatus %x\n",
745 				       i, vcstatus[i]);
746 			print_irq_status_vc(i, vcstatus[i]);
747 		} else if (debug_irq) {
748 			print_irq_status_vc(i, vcstatus[i]);
749 		}
750 	}
751 
752 	if (ciostatus & DSI_CIO_IRQ_ERROR_MASK) {
753 		DSSERR("DSI CIO error, cio irqstatus %x\n", ciostatus);
754 		print_irq_status_cio(ciostatus);
755 	} else if (debug_irq) {
756 		print_irq_status_cio(ciostatus);
757 	}
758 }
759 
760 static void dsi_call_isrs(struct dsi_isr_data *isr_array,
761 		unsigned isr_array_size, u32 irqstatus)
762 {
763 	struct dsi_isr_data *isr_data;
764 	int i;
765 
766 	for (i = 0; i < isr_array_size; i++) {
767 		isr_data = &isr_array[i];
768 		if (isr_data->isr && isr_data->mask & irqstatus)
769 			isr_data->isr(isr_data->arg, irqstatus);
770 	}
771 }
772 
773 static void dsi_handle_isrs(struct dsi_isr_tables *isr_tables,
774 		u32 irqstatus, u32 *vcstatus, u32 ciostatus)
775 {
776 	int i;
777 
778 	dsi_call_isrs(isr_tables->isr_table,
779 			ARRAY_SIZE(isr_tables->isr_table),
780 			irqstatus);
781 
782 	for (i = 0; i < 4; ++i) {
783 		if (vcstatus[i] == 0)
784 			continue;
785 		dsi_call_isrs(isr_tables->isr_table_vc[i],
786 				ARRAY_SIZE(isr_tables->isr_table_vc[i]),
787 				vcstatus[i]);
788 	}
789 
790 	if (ciostatus != 0)
791 		dsi_call_isrs(isr_tables->isr_table_cio,
792 				ARRAY_SIZE(isr_tables->isr_table_cio),
793 				ciostatus);
794 }
795 
796 static irqreturn_t omap_dsi_irq_handler(int irq, void *arg)
797 {
798 	struct platform_device *dsidev;
799 	struct dsi_data *dsi;
800 	u32 irqstatus, vcstatus[4], ciostatus;
801 	int i;
802 
803 	dsidev = (struct platform_device *) arg;
804 	dsi = dsi_get_dsidrv_data(dsidev);
805 
806 	if (!dsi->is_enabled)
807 		return IRQ_NONE;
808 
809 	spin_lock(&dsi->irq_lock);
810 
811 	irqstatus = dsi_read_reg(dsidev, DSI_IRQSTATUS);
812 
813 	/* IRQ is not for us */
814 	if (!irqstatus) {
815 		spin_unlock(&dsi->irq_lock);
816 		return IRQ_NONE;
817 	}
818 
819 	dsi_write_reg(dsidev, DSI_IRQSTATUS, irqstatus & ~DSI_IRQ_CHANNEL_MASK);
820 	/* flush posted write */
821 	dsi_read_reg(dsidev, DSI_IRQSTATUS);
822 
823 	for (i = 0; i < 4; ++i) {
824 		if ((irqstatus & (1 << i)) == 0) {
825 			vcstatus[i] = 0;
826 			continue;
827 		}
828 
829 		vcstatus[i] = dsi_read_reg(dsidev, DSI_VC_IRQSTATUS(i));
830 
831 		dsi_write_reg(dsidev, DSI_VC_IRQSTATUS(i), vcstatus[i]);
832 		/* flush posted write */
833 		dsi_read_reg(dsidev, DSI_VC_IRQSTATUS(i));
834 	}
835 
836 	if (irqstatus & DSI_IRQ_COMPLEXIO_ERR) {
837 		ciostatus = dsi_read_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS);
838 
839 		dsi_write_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS, ciostatus);
840 		/* flush posted write */
841 		dsi_read_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS);
842 	} else {
843 		ciostatus = 0;
844 	}
845 
846 #ifdef DSI_CATCH_MISSING_TE
847 	if (irqstatus & DSI_IRQ_TE_TRIGGER)
848 		del_timer(&dsi->te_timer);
849 #endif
850 
851 	/* make a copy and unlock, so that isrs can unregister
852 	 * themselves */
853 	memcpy(&dsi->isr_tables_copy, &dsi->isr_tables,
854 		sizeof(dsi->isr_tables));
855 
856 	spin_unlock(&dsi->irq_lock);
857 
858 	dsi_handle_isrs(&dsi->isr_tables_copy, irqstatus, vcstatus, ciostatus);
859 
860 	dsi_handle_irq_errors(dsidev, irqstatus, vcstatus, ciostatus);
861 
862 	dsi_collect_irq_stats(dsidev, irqstatus, vcstatus, ciostatus);
863 
864 	return IRQ_HANDLED;
865 }
866 
867 /* dsi->irq_lock has to be locked by the caller */
868 static void _omap_dsi_configure_irqs(struct platform_device *dsidev,
869 		struct dsi_isr_data *isr_array,
870 		unsigned isr_array_size, u32 default_mask,
871 		const struct dsi_reg enable_reg,
872 		const struct dsi_reg status_reg)
873 {
874 	struct dsi_isr_data *isr_data;
875 	u32 mask;
876 	u32 old_mask;
877 	int i;
878 
879 	mask = default_mask;
880 
881 	for (i = 0; i < isr_array_size; i++) {
882 		isr_data = &isr_array[i];
883 
884 		if (isr_data->isr == NULL)
885 			continue;
886 
887 		mask |= isr_data->mask;
888 	}
889 
890 	old_mask = dsi_read_reg(dsidev, enable_reg);
891 	/* clear the irqstatus for newly enabled irqs */
892 	dsi_write_reg(dsidev, status_reg, (mask ^ old_mask) & mask);
893 	dsi_write_reg(dsidev, enable_reg, mask);
894 
895 	/* flush posted writes */
896 	dsi_read_reg(dsidev, enable_reg);
897 	dsi_read_reg(dsidev, status_reg);
898 }
899 
900 /* dsi->irq_lock has to be locked by the caller */
901 static void _omap_dsi_set_irqs(struct platform_device *dsidev)
902 {
903 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
904 	u32 mask = DSI_IRQ_ERROR_MASK;
905 #ifdef DSI_CATCH_MISSING_TE
906 	mask |= DSI_IRQ_TE_TRIGGER;
907 #endif
908 	_omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table,
909 			ARRAY_SIZE(dsi->isr_tables.isr_table), mask,
910 			DSI_IRQENABLE, DSI_IRQSTATUS);
911 }
912 
913 /* dsi->irq_lock has to be locked by the caller */
914 static void _omap_dsi_set_irqs_vc(struct platform_device *dsidev, int vc)
915 {
916 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
917 
918 	_omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table_vc[vc],
919 			ARRAY_SIZE(dsi->isr_tables.isr_table_vc[vc]),
920 			DSI_VC_IRQ_ERROR_MASK,
921 			DSI_VC_IRQENABLE(vc), DSI_VC_IRQSTATUS(vc));
922 }
923 
924 /* dsi->irq_lock has to be locked by the caller */
925 static void _omap_dsi_set_irqs_cio(struct platform_device *dsidev)
926 {
927 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
928 
929 	_omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table_cio,
930 			ARRAY_SIZE(dsi->isr_tables.isr_table_cio),
931 			DSI_CIO_IRQ_ERROR_MASK,
932 			DSI_COMPLEXIO_IRQ_ENABLE, DSI_COMPLEXIO_IRQ_STATUS);
933 }
934 
935 static void _dsi_initialize_irq(struct platform_device *dsidev)
936 {
937 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
938 	unsigned long flags;
939 	int vc;
940 
941 	spin_lock_irqsave(&dsi->irq_lock, flags);
942 
943 	memset(&dsi->isr_tables, 0, sizeof(dsi->isr_tables));
944 
945 	_omap_dsi_set_irqs(dsidev);
946 	for (vc = 0; vc < 4; ++vc)
947 		_omap_dsi_set_irqs_vc(dsidev, vc);
948 	_omap_dsi_set_irqs_cio(dsidev);
949 
950 	spin_unlock_irqrestore(&dsi->irq_lock, flags);
951 }
952 
953 static int _dsi_register_isr(omap_dsi_isr_t isr, void *arg, u32 mask,
954 		struct dsi_isr_data *isr_array, unsigned isr_array_size)
955 {
956 	struct dsi_isr_data *isr_data;
957 	int free_idx;
958 	int i;
959 
960 	BUG_ON(isr == NULL);
961 
962 	/* check for duplicate entry and find a free slot */
963 	free_idx = -1;
964 	for (i = 0; i < isr_array_size; i++) {
965 		isr_data = &isr_array[i];
966 
967 		if (isr_data->isr == isr && isr_data->arg == arg &&
968 				isr_data->mask == mask) {
969 			return -EINVAL;
970 		}
971 
972 		if (isr_data->isr == NULL && free_idx == -1)
973 			free_idx = i;
974 	}
975 
976 	if (free_idx == -1)
977 		return -EBUSY;
978 
979 	isr_data = &isr_array[free_idx];
980 	isr_data->isr = isr;
981 	isr_data->arg = arg;
982 	isr_data->mask = mask;
983 
984 	return 0;
985 }
986 
987 static int _dsi_unregister_isr(omap_dsi_isr_t isr, void *arg, u32 mask,
988 		struct dsi_isr_data *isr_array, unsigned isr_array_size)
989 {
990 	struct dsi_isr_data *isr_data;
991 	int i;
992 
993 	for (i = 0; i < isr_array_size; i++) {
994 		isr_data = &isr_array[i];
995 		if (isr_data->isr != isr || isr_data->arg != arg ||
996 				isr_data->mask != mask)
997 			continue;
998 
999 		isr_data->isr = NULL;
1000 		isr_data->arg = NULL;
1001 		isr_data->mask = 0;
1002 
1003 		return 0;
1004 	}
1005 
1006 	return -EINVAL;
1007 }
1008 
1009 static int dsi_register_isr(struct platform_device *dsidev, omap_dsi_isr_t isr,
1010 		void *arg, u32 mask)
1011 {
1012 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1013 	unsigned long flags;
1014 	int r;
1015 
1016 	spin_lock_irqsave(&dsi->irq_lock, flags);
1017 
1018 	r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table,
1019 			ARRAY_SIZE(dsi->isr_tables.isr_table));
1020 
1021 	if (r == 0)
1022 		_omap_dsi_set_irqs(dsidev);
1023 
1024 	spin_unlock_irqrestore(&dsi->irq_lock, flags);
1025 
1026 	return r;
1027 }
1028 
1029 static int dsi_unregister_isr(struct platform_device *dsidev,
1030 		omap_dsi_isr_t isr, void *arg, u32 mask)
1031 {
1032 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1033 	unsigned long flags;
1034 	int r;
1035 
1036 	spin_lock_irqsave(&dsi->irq_lock, flags);
1037 
1038 	r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table,
1039 			ARRAY_SIZE(dsi->isr_tables.isr_table));
1040 
1041 	if (r == 0)
1042 		_omap_dsi_set_irqs(dsidev);
1043 
1044 	spin_unlock_irqrestore(&dsi->irq_lock, flags);
1045 
1046 	return r;
1047 }
1048 
1049 static int dsi_register_isr_vc(struct platform_device *dsidev, int channel,
1050 		omap_dsi_isr_t isr, void *arg, u32 mask)
1051 {
1052 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1053 	unsigned long flags;
1054 	int r;
1055 
1056 	spin_lock_irqsave(&dsi->irq_lock, flags);
1057 
1058 	r = _dsi_register_isr(isr, arg, mask,
1059 			dsi->isr_tables.isr_table_vc[channel],
1060 			ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel]));
1061 
1062 	if (r == 0)
1063 		_omap_dsi_set_irqs_vc(dsidev, channel);
1064 
1065 	spin_unlock_irqrestore(&dsi->irq_lock, flags);
1066 
1067 	return r;
1068 }
1069 
1070 static int dsi_unregister_isr_vc(struct platform_device *dsidev, int channel,
1071 		omap_dsi_isr_t isr, void *arg, u32 mask)
1072 {
1073 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1074 	unsigned long flags;
1075 	int r;
1076 
1077 	spin_lock_irqsave(&dsi->irq_lock, flags);
1078 
1079 	r = _dsi_unregister_isr(isr, arg, mask,
1080 			dsi->isr_tables.isr_table_vc[channel],
1081 			ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel]));
1082 
1083 	if (r == 0)
1084 		_omap_dsi_set_irqs_vc(dsidev, channel);
1085 
1086 	spin_unlock_irqrestore(&dsi->irq_lock, flags);
1087 
1088 	return r;
1089 }
1090 
1091 static int dsi_register_isr_cio(struct platform_device *dsidev,
1092 		omap_dsi_isr_t isr, void *arg, u32 mask)
1093 {
1094 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1095 	unsigned long flags;
1096 	int r;
1097 
1098 	spin_lock_irqsave(&dsi->irq_lock, flags);
1099 
1100 	r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio,
1101 			ARRAY_SIZE(dsi->isr_tables.isr_table_cio));
1102 
1103 	if (r == 0)
1104 		_omap_dsi_set_irqs_cio(dsidev);
1105 
1106 	spin_unlock_irqrestore(&dsi->irq_lock, flags);
1107 
1108 	return r;
1109 }
1110 
1111 static int dsi_unregister_isr_cio(struct platform_device *dsidev,
1112 		omap_dsi_isr_t isr, void *arg, u32 mask)
1113 {
1114 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1115 	unsigned long flags;
1116 	int r;
1117 
1118 	spin_lock_irqsave(&dsi->irq_lock, flags);
1119 
1120 	r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio,
1121 			ARRAY_SIZE(dsi->isr_tables.isr_table_cio));
1122 
1123 	if (r == 0)
1124 		_omap_dsi_set_irqs_cio(dsidev);
1125 
1126 	spin_unlock_irqrestore(&dsi->irq_lock, flags);
1127 
1128 	return r;
1129 }
1130 
1131 static u32 dsi_get_errors(struct platform_device *dsidev)
1132 {
1133 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1134 	unsigned long flags;
1135 	u32 e;
1136 	spin_lock_irqsave(&dsi->errors_lock, flags);
1137 	e = dsi->errors;
1138 	dsi->errors = 0;
1139 	spin_unlock_irqrestore(&dsi->errors_lock, flags);
1140 	return e;
1141 }
1142 
1143 static int dsi_runtime_get(struct platform_device *dsidev)
1144 {
1145 	int r;
1146 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1147 
1148 	DSSDBG("dsi_runtime_get\n");
1149 
1150 	r = pm_runtime_get_sync(&dsi->pdev->dev);
1151 	WARN_ON(r < 0);
1152 	return r < 0 ? r : 0;
1153 }
1154 
1155 static void dsi_runtime_put(struct platform_device *dsidev)
1156 {
1157 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1158 	int r;
1159 
1160 	DSSDBG("dsi_runtime_put\n");
1161 
1162 	r = pm_runtime_put_sync(&dsi->pdev->dev);
1163 	WARN_ON(r < 0 && r != -ENOSYS);
1164 }
1165 
1166 static int dsi_regulator_init(struct platform_device *dsidev)
1167 {
1168 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1169 	struct regulator *vdds_dsi;
1170 
1171 	if (dsi->vdds_dsi_reg != NULL)
1172 		return 0;
1173 
1174 	vdds_dsi = devm_regulator_get(&dsi->pdev->dev, "vdd");
1175 
1176 	if (IS_ERR(vdds_dsi)) {
1177 		if (PTR_ERR(vdds_dsi) != -EPROBE_DEFER)
1178 			DSSERR("can't get DSI VDD regulator\n");
1179 		return PTR_ERR(vdds_dsi);
1180 	}
1181 
1182 	dsi->vdds_dsi_reg = vdds_dsi;
1183 
1184 	return 0;
1185 }
1186 
1187 static void _dsi_print_reset_status(struct platform_device *dsidev)
1188 {
1189 	u32 l;
1190 	int b0, b1, b2;
1191 
1192 	/* A dummy read using the SCP interface to any DSIPHY register is
1193 	 * required after DSIPHY reset to complete the reset of the DSI complex
1194 	 * I/O. */
1195 	l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
1196 
1197 	if (dss_has_feature(FEAT_DSI_REVERSE_TXCLKESC)) {
1198 		b0 = 28;
1199 		b1 = 27;
1200 		b2 = 26;
1201 	} else {
1202 		b0 = 24;
1203 		b1 = 25;
1204 		b2 = 26;
1205 	}
1206 
1207 #define DSI_FLD_GET(fld, start, end)\
1208 	FLD_GET(dsi_read_reg(dsidev, DSI_##fld), start, end)
1209 
1210 	pr_debug("DSI resets: PLL (%d) CIO (%d) PHY (%x%x%x, %d, %d, %d)\n",
1211 		DSI_FLD_GET(PLL_STATUS, 0, 0),
1212 		DSI_FLD_GET(COMPLEXIO_CFG1, 29, 29),
1213 		DSI_FLD_GET(DSIPHY_CFG5, b0, b0),
1214 		DSI_FLD_GET(DSIPHY_CFG5, b1, b1),
1215 		DSI_FLD_GET(DSIPHY_CFG5, b2, b2),
1216 		DSI_FLD_GET(DSIPHY_CFG5, 29, 29),
1217 		DSI_FLD_GET(DSIPHY_CFG5, 30, 30),
1218 		DSI_FLD_GET(DSIPHY_CFG5, 31, 31));
1219 
1220 #undef DSI_FLD_GET
1221 }
1222 
1223 static inline int dsi_if_enable(struct platform_device *dsidev, bool enable)
1224 {
1225 	DSSDBG("dsi_if_enable(%d)\n", enable);
1226 
1227 	enable = enable ? 1 : 0;
1228 	REG_FLD_MOD(dsidev, DSI_CTRL, enable, 0, 0); /* IF_EN */
1229 
1230 	if (wait_for_bit_change(dsidev, DSI_CTRL, 0, enable) != enable) {
1231 			DSSERR("Failed to set dsi_if_enable to %d\n", enable);
1232 			return -EIO;
1233 	}
1234 
1235 	return 0;
1236 }
1237 
1238 static unsigned long dsi_get_pll_hsdiv_dispc_rate(struct platform_device *dsidev)
1239 {
1240 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1241 
1242 	return dsi->pll.cinfo.clkout[HSDIV_DISPC];
1243 }
1244 
1245 static unsigned long dsi_get_pll_hsdiv_dsi_rate(struct platform_device *dsidev)
1246 {
1247 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1248 
1249 	return dsi->pll.cinfo.clkout[HSDIV_DSI];
1250 }
1251 
1252 static unsigned long dsi_get_txbyteclkhs(struct platform_device *dsidev)
1253 {
1254 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1255 
1256 	return dsi->pll.cinfo.clkdco / 16;
1257 }
1258 
1259 static unsigned long dsi_fclk_rate(struct platform_device *dsidev)
1260 {
1261 	unsigned long r;
1262 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1263 
1264 	if (dss_get_dsi_clk_source(dsi->module_id) == OMAP_DSS_CLK_SRC_FCK) {
1265 		/* DSI FCLK source is DSS_CLK_FCK */
1266 		r = clk_get_rate(dsi->dss_clk);
1267 	} else {
1268 		/* DSI FCLK source is dsi_pll_hsdiv_dsi_clk */
1269 		r = dsi_get_pll_hsdiv_dsi_rate(dsidev);
1270 	}
1271 
1272 	return r;
1273 }
1274 
1275 static int dsi_lp_clock_calc(unsigned long dsi_fclk,
1276 		unsigned long lp_clk_min, unsigned long lp_clk_max,
1277 		struct dsi_lp_clock_info *lp_cinfo)
1278 {
1279 	unsigned lp_clk_div;
1280 	unsigned long lp_clk;
1281 
1282 	lp_clk_div = DIV_ROUND_UP(dsi_fclk, lp_clk_max * 2);
1283 	lp_clk = dsi_fclk / 2 / lp_clk_div;
1284 
1285 	if (lp_clk < lp_clk_min || lp_clk > lp_clk_max)
1286 		return -EINVAL;
1287 
1288 	lp_cinfo->lp_clk_div = lp_clk_div;
1289 	lp_cinfo->lp_clk = lp_clk;
1290 
1291 	return 0;
1292 }
1293 
1294 static int dsi_set_lp_clk_divisor(struct platform_device *dsidev)
1295 {
1296 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1297 	unsigned long dsi_fclk;
1298 	unsigned lp_clk_div;
1299 	unsigned long lp_clk;
1300 	unsigned lpdiv_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_LPDIV);
1301 
1302 
1303 	lp_clk_div = dsi->user_lp_cinfo.lp_clk_div;
1304 
1305 	if (lp_clk_div == 0 || lp_clk_div > lpdiv_max)
1306 		return -EINVAL;
1307 
1308 	dsi_fclk = dsi_fclk_rate(dsidev);
1309 
1310 	lp_clk = dsi_fclk / 2 / lp_clk_div;
1311 
1312 	DSSDBG("LP_CLK_DIV %u, LP_CLK %lu\n", lp_clk_div, lp_clk);
1313 	dsi->current_lp_cinfo.lp_clk = lp_clk;
1314 	dsi->current_lp_cinfo.lp_clk_div = lp_clk_div;
1315 
1316 	/* LP_CLK_DIVISOR */
1317 	REG_FLD_MOD(dsidev, DSI_CLK_CTRL, lp_clk_div, 12, 0);
1318 
1319 	/* LP_RX_SYNCHRO_ENABLE */
1320 	REG_FLD_MOD(dsidev, DSI_CLK_CTRL, dsi_fclk > 30000000 ? 1 : 0, 21, 21);
1321 
1322 	return 0;
1323 }
1324 
1325 static void dsi_enable_scp_clk(struct platform_device *dsidev)
1326 {
1327 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1328 
1329 	if (dsi->scp_clk_refcount++ == 0)
1330 		REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 14, 14); /* CIO_CLK_ICG */
1331 }
1332 
1333 static void dsi_disable_scp_clk(struct platform_device *dsidev)
1334 {
1335 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1336 
1337 	WARN_ON(dsi->scp_clk_refcount == 0);
1338 	if (--dsi->scp_clk_refcount == 0)
1339 		REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 14, 14); /* CIO_CLK_ICG */
1340 }
1341 
1342 enum dsi_pll_power_state {
1343 	DSI_PLL_POWER_OFF	= 0x0,
1344 	DSI_PLL_POWER_ON_HSCLK	= 0x1,
1345 	DSI_PLL_POWER_ON_ALL	= 0x2,
1346 	DSI_PLL_POWER_ON_DIV	= 0x3,
1347 };
1348 
1349 static int dsi_pll_power(struct platform_device *dsidev,
1350 		enum dsi_pll_power_state state)
1351 {
1352 	int t = 0;
1353 
1354 	/* DSI-PLL power command 0x3 is not working */
1355 	if (dss_has_feature(FEAT_DSI_PLL_PWR_BUG) &&
1356 			state == DSI_PLL_POWER_ON_DIV)
1357 		state = DSI_PLL_POWER_ON_ALL;
1358 
1359 	/* PLL_PWR_CMD */
1360 	REG_FLD_MOD(dsidev, DSI_CLK_CTRL, state, 31, 30);
1361 
1362 	/* PLL_PWR_STATUS */
1363 	while (FLD_GET(dsi_read_reg(dsidev, DSI_CLK_CTRL), 29, 28) != state) {
1364 		if (++t > 1000) {
1365 			DSSERR("Failed to set DSI PLL power mode to %d\n",
1366 					state);
1367 			return -ENODEV;
1368 		}
1369 		udelay(1);
1370 	}
1371 
1372 	return 0;
1373 }
1374 
1375 
1376 static void dsi_pll_calc_dsi_fck(struct dss_pll_clock_info *cinfo)
1377 {
1378 	unsigned long max_dsi_fck;
1379 
1380 	max_dsi_fck = dss_feat_get_param_max(FEAT_PARAM_DSI_FCK);
1381 
1382 	cinfo->mX[HSDIV_DSI] = DIV_ROUND_UP(cinfo->clkdco, max_dsi_fck);
1383 	cinfo->clkout[HSDIV_DSI] = cinfo->clkdco / cinfo->mX[HSDIV_DSI];
1384 }
1385 
1386 static int dsi_pll_enable(struct dss_pll *pll)
1387 {
1388 	struct dsi_data *dsi = container_of(pll, struct dsi_data, pll);
1389 	struct platform_device *dsidev = dsi->pdev;
1390 	int r = 0;
1391 
1392 	DSSDBG("PLL init\n");
1393 
1394 	r = dsi_regulator_init(dsidev);
1395 	if (r)
1396 		return r;
1397 
1398 	r = dsi_runtime_get(dsidev);
1399 	if (r)
1400 		return r;
1401 
1402 	/*
1403 	 * Note: SCP CLK is not required on OMAP3, but it is required on OMAP4.
1404 	 */
1405 	dsi_enable_scp_clk(dsidev);
1406 
1407 	if (!dsi->vdds_dsi_enabled) {
1408 		r = regulator_enable(dsi->vdds_dsi_reg);
1409 		if (r)
1410 			goto err0;
1411 		dsi->vdds_dsi_enabled = true;
1412 	}
1413 
1414 	/* XXX PLL does not come out of reset without this... */
1415 	dispc_pck_free_enable(1);
1416 
1417 	if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 0, 1) != 1) {
1418 		DSSERR("PLL not coming out of reset.\n");
1419 		r = -ENODEV;
1420 		dispc_pck_free_enable(0);
1421 		goto err1;
1422 	}
1423 
1424 	/* XXX ... but if left on, we get problems when planes do not
1425 	 * fill the whole display. No idea about this */
1426 	dispc_pck_free_enable(0);
1427 
1428 	r = dsi_pll_power(dsidev, DSI_PLL_POWER_ON_ALL);
1429 
1430 	if (r)
1431 		goto err1;
1432 
1433 	DSSDBG("PLL init done\n");
1434 
1435 	return 0;
1436 err1:
1437 	if (dsi->vdds_dsi_enabled) {
1438 		regulator_disable(dsi->vdds_dsi_reg);
1439 		dsi->vdds_dsi_enabled = false;
1440 	}
1441 err0:
1442 	dsi_disable_scp_clk(dsidev);
1443 	dsi_runtime_put(dsidev);
1444 	return r;
1445 }
1446 
1447 static void dsi_pll_uninit(struct platform_device *dsidev, bool disconnect_lanes)
1448 {
1449 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1450 
1451 	dsi_pll_power(dsidev, DSI_PLL_POWER_OFF);
1452 	if (disconnect_lanes) {
1453 		WARN_ON(!dsi->vdds_dsi_enabled);
1454 		regulator_disable(dsi->vdds_dsi_reg);
1455 		dsi->vdds_dsi_enabled = false;
1456 	}
1457 
1458 	dsi_disable_scp_clk(dsidev);
1459 	dsi_runtime_put(dsidev);
1460 
1461 	DSSDBG("PLL uninit done\n");
1462 }
1463 
1464 static void dsi_pll_disable(struct dss_pll *pll)
1465 {
1466 	struct dsi_data *dsi = container_of(pll, struct dsi_data, pll);
1467 	struct platform_device *dsidev = dsi->pdev;
1468 
1469 	dsi_pll_uninit(dsidev, true);
1470 }
1471 
1472 static void dsi_dump_dsidev_clocks(struct platform_device *dsidev,
1473 		struct seq_file *s)
1474 {
1475 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1476 	struct dss_pll_clock_info *cinfo = &dsi->pll.cinfo;
1477 	enum omap_dss_clk_source dispc_clk_src, dsi_clk_src;
1478 	int dsi_module = dsi->module_id;
1479 	struct dss_pll *pll = &dsi->pll;
1480 
1481 	dispc_clk_src = dss_get_dispc_clk_source();
1482 	dsi_clk_src = dss_get_dsi_clk_source(dsi_module);
1483 
1484 	if (dsi_runtime_get(dsidev))
1485 		return;
1486 
1487 	seq_printf(s,	"- DSI%d PLL -\n", dsi_module + 1);
1488 
1489 	seq_printf(s,	"dsi pll clkin\t%lu\n", clk_get_rate(pll->clkin));
1490 
1491 	seq_printf(s,	"Fint\t\t%-16lun %u\n", cinfo->fint, cinfo->n);
1492 
1493 	seq_printf(s,	"CLKIN4DDR\t%-16lum %u\n",
1494 			cinfo->clkdco, cinfo->m);
1495 
1496 	seq_printf(s,	"DSI_PLL_HSDIV_DISPC (%s)\t%-16lum_dispc %u\t(%s)\n",
1497 			dss_feat_get_clk_source_name(dsi_module == 0 ?
1498 				OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC :
1499 				OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC),
1500 			cinfo->clkout[HSDIV_DISPC],
1501 			cinfo->mX[HSDIV_DISPC],
1502 			dispc_clk_src == OMAP_DSS_CLK_SRC_FCK ?
1503 			"off" : "on");
1504 
1505 	seq_printf(s,	"DSI_PLL_HSDIV_DSI (%s)\t%-16lum_dsi %u\t(%s)\n",
1506 			dss_feat_get_clk_source_name(dsi_module == 0 ?
1507 				OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI :
1508 				OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI),
1509 			cinfo->clkout[HSDIV_DSI],
1510 			cinfo->mX[HSDIV_DSI],
1511 			dsi_clk_src == OMAP_DSS_CLK_SRC_FCK ?
1512 			"off" : "on");
1513 
1514 	seq_printf(s,	"- DSI%d -\n", dsi_module + 1);
1515 
1516 	seq_printf(s,	"dsi fclk source = %s (%s)\n",
1517 			dss_get_generic_clk_source_name(dsi_clk_src),
1518 			dss_feat_get_clk_source_name(dsi_clk_src));
1519 
1520 	seq_printf(s,	"DSI_FCLK\t%lu\n", dsi_fclk_rate(dsidev));
1521 
1522 	seq_printf(s,	"DDR_CLK\t\t%lu\n",
1523 			cinfo->clkdco / 4);
1524 
1525 	seq_printf(s,	"TxByteClkHS\t%lu\n", dsi_get_txbyteclkhs(dsidev));
1526 
1527 	seq_printf(s,	"LP_CLK\t\t%lu\n", dsi->current_lp_cinfo.lp_clk);
1528 
1529 	dsi_runtime_put(dsidev);
1530 }
1531 
1532 void dsi_dump_clocks(struct seq_file *s)
1533 {
1534 	struct platform_device *dsidev;
1535 	int i;
1536 
1537 	for  (i = 0; i < MAX_NUM_DSI; i++) {
1538 		dsidev = dsi_get_dsidev_from_id(i);
1539 		if (dsidev)
1540 			dsi_dump_dsidev_clocks(dsidev, s);
1541 	}
1542 }
1543 
1544 #ifdef CONFIG_FB_OMAP2_DSS_COLLECT_IRQ_STATS
1545 static void dsi_dump_dsidev_irqs(struct platform_device *dsidev,
1546 		struct seq_file *s)
1547 {
1548 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1549 	unsigned long flags;
1550 	struct dsi_irq_stats stats;
1551 
1552 	spin_lock_irqsave(&dsi->irq_stats_lock, flags);
1553 
1554 	stats = dsi->irq_stats;
1555 	memset(&dsi->irq_stats, 0, sizeof(dsi->irq_stats));
1556 	dsi->irq_stats.last_reset = jiffies;
1557 
1558 	spin_unlock_irqrestore(&dsi->irq_stats_lock, flags);
1559 
1560 	seq_printf(s, "period %u ms\n",
1561 			jiffies_to_msecs(jiffies - stats.last_reset));
1562 
1563 	seq_printf(s, "irqs %d\n", stats.irq_count);
1564 #define PIS(x) \
1565 	seq_printf(s, "%-20s %10d\n", #x, stats.dsi_irqs[ffs(DSI_IRQ_##x)-1]);
1566 
1567 	seq_printf(s, "-- DSI%d interrupts --\n", dsi->module_id + 1);
1568 	PIS(VC0);
1569 	PIS(VC1);
1570 	PIS(VC2);
1571 	PIS(VC3);
1572 	PIS(WAKEUP);
1573 	PIS(RESYNC);
1574 	PIS(PLL_LOCK);
1575 	PIS(PLL_UNLOCK);
1576 	PIS(PLL_RECALL);
1577 	PIS(COMPLEXIO_ERR);
1578 	PIS(HS_TX_TIMEOUT);
1579 	PIS(LP_RX_TIMEOUT);
1580 	PIS(TE_TRIGGER);
1581 	PIS(ACK_TRIGGER);
1582 	PIS(SYNC_LOST);
1583 	PIS(LDO_POWER_GOOD);
1584 	PIS(TA_TIMEOUT);
1585 #undef PIS
1586 
1587 #define PIS(x) \
1588 	seq_printf(s, "%-20s %10d %10d %10d %10d\n", #x, \
1589 			stats.vc_irqs[0][ffs(DSI_VC_IRQ_##x)-1], \
1590 			stats.vc_irqs[1][ffs(DSI_VC_IRQ_##x)-1], \
1591 			stats.vc_irqs[2][ffs(DSI_VC_IRQ_##x)-1], \
1592 			stats.vc_irqs[3][ffs(DSI_VC_IRQ_##x)-1]);
1593 
1594 	seq_printf(s, "-- VC interrupts --\n");
1595 	PIS(CS);
1596 	PIS(ECC_CORR);
1597 	PIS(PACKET_SENT);
1598 	PIS(FIFO_TX_OVF);
1599 	PIS(FIFO_RX_OVF);
1600 	PIS(BTA);
1601 	PIS(ECC_NO_CORR);
1602 	PIS(FIFO_TX_UDF);
1603 	PIS(PP_BUSY_CHANGE);
1604 #undef PIS
1605 
1606 #define PIS(x) \
1607 	seq_printf(s, "%-20s %10d\n", #x, \
1608 			stats.cio_irqs[ffs(DSI_CIO_IRQ_##x)-1]);
1609 
1610 	seq_printf(s, "-- CIO interrupts --\n");
1611 	PIS(ERRSYNCESC1);
1612 	PIS(ERRSYNCESC2);
1613 	PIS(ERRSYNCESC3);
1614 	PIS(ERRESC1);
1615 	PIS(ERRESC2);
1616 	PIS(ERRESC3);
1617 	PIS(ERRCONTROL1);
1618 	PIS(ERRCONTROL2);
1619 	PIS(ERRCONTROL3);
1620 	PIS(STATEULPS1);
1621 	PIS(STATEULPS2);
1622 	PIS(STATEULPS3);
1623 	PIS(ERRCONTENTIONLP0_1);
1624 	PIS(ERRCONTENTIONLP1_1);
1625 	PIS(ERRCONTENTIONLP0_2);
1626 	PIS(ERRCONTENTIONLP1_2);
1627 	PIS(ERRCONTENTIONLP0_3);
1628 	PIS(ERRCONTENTIONLP1_3);
1629 	PIS(ULPSACTIVENOT_ALL0);
1630 	PIS(ULPSACTIVENOT_ALL1);
1631 #undef PIS
1632 }
1633 
1634 static void dsi1_dump_irqs(struct seq_file *s)
1635 {
1636 	struct platform_device *dsidev = dsi_get_dsidev_from_id(0);
1637 
1638 	dsi_dump_dsidev_irqs(dsidev, s);
1639 }
1640 
1641 static void dsi2_dump_irqs(struct seq_file *s)
1642 {
1643 	struct platform_device *dsidev = dsi_get_dsidev_from_id(1);
1644 
1645 	dsi_dump_dsidev_irqs(dsidev, s);
1646 }
1647 #endif
1648 
1649 static void dsi_dump_dsidev_regs(struct platform_device *dsidev,
1650 		struct seq_file *s)
1651 {
1652 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(dsidev, r))
1653 
1654 	if (dsi_runtime_get(dsidev))
1655 		return;
1656 	dsi_enable_scp_clk(dsidev);
1657 
1658 	DUMPREG(DSI_REVISION);
1659 	DUMPREG(DSI_SYSCONFIG);
1660 	DUMPREG(DSI_SYSSTATUS);
1661 	DUMPREG(DSI_IRQSTATUS);
1662 	DUMPREG(DSI_IRQENABLE);
1663 	DUMPREG(DSI_CTRL);
1664 	DUMPREG(DSI_COMPLEXIO_CFG1);
1665 	DUMPREG(DSI_COMPLEXIO_IRQ_STATUS);
1666 	DUMPREG(DSI_COMPLEXIO_IRQ_ENABLE);
1667 	DUMPREG(DSI_CLK_CTRL);
1668 	DUMPREG(DSI_TIMING1);
1669 	DUMPREG(DSI_TIMING2);
1670 	DUMPREG(DSI_VM_TIMING1);
1671 	DUMPREG(DSI_VM_TIMING2);
1672 	DUMPREG(DSI_VM_TIMING3);
1673 	DUMPREG(DSI_CLK_TIMING);
1674 	DUMPREG(DSI_TX_FIFO_VC_SIZE);
1675 	DUMPREG(DSI_RX_FIFO_VC_SIZE);
1676 	DUMPREG(DSI_COMPLEXIO_CFG2);
1677 	DUMPREG(DSI_RX_FIFO_VC_FULLNESS);
1678 	DUMPREG(DSI_VM_TIMING4);
1679 	DUMPREG(DSI_TX_FIFO_VC_EMPTINESS);
1680 	DUMPREG(DSI_VM_TIMING5);
1681 	DUMPREG(DSI_VM_TIMING6);
1682 	DUMPREG(DSI_VM_TIMING7);
1683 	DUMPREG(DSI_STOPCLK_TIMING);
1684 
1685 	DUMPREG(DSI_VC_CTRL(0));
1686 	DUMPREG(DSI_VC_TE(0));
1687 	DUMPREG(DSI_VC_LONG_PACKET_HEADER(0));
1688 	DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(0));
1689 	DUMPREG(DSI_VC_SHORT_PACKET_HEADER(0));
1690 	DUMPREG(DSI_VC_IRQSTATUS(0));
1691 	DUMPREG(DSI_VC_IRQENABLE(0));
1692 
1693 	DUMPREG(DSI_VC_CTRL(1));
1694 	DUMPREG(DSI_VC_TE(1));
1695 	DUMPREG(DSI_VC_LONG_PACKET_HEADER(1));
1696 	DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(1));
1697 	DUMPREG(DSI_VC_SHORT_PACKET_HEADER(1));
1698 	DUMPREG(DSI_VC_IRQSTATUS(1));
1699 	DUMPREG(DSI_VC_IRQENABLE(1));
1700 
1701 	DUMPREG(DSI_VC_CTRL(2));
1702 	DUMPREG(DSI_VC_TE(2));
1703 	DUMPREG(DSI_VC_LONG_PACKET_HEADER(2));
1704 	DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(2));
1705 	DUMPREG(DSI_VC_SHORT_PACKET_HEADER(2));
1706 	DUMPREG(DSI_VC_IRQSTATUS(2));
1707 	DUMPREG(DSI_VC_IRQENABLE(2));
1708 
1709 	DUMPREG(DSI_VC_CTRL(3));
1710 	DUMPREG(DSI_VC_TE(3));
1711 	DUMPREG(DSI_VC_LONG_PACKET_HEADER(3));
1712 	DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(3));
1713 	DUMPREG(DSI_VC_SHORT_PACKET_HEADER(3));
1714 	DUMPREG(DSI_VC_IRQSTATUS(3));
1715 	DUMPREG(DSI_VC_IRQENABLE(3));
1716 
1717 	DUMPREG(DSI_DSIPHY_CFG0);
1718 	DUMPREG(DSI_DSIPHY_CFG1);
1719 	DUMPREG(DSI_DSIPHY_CFG2);
1720 	DUMPREG(DSI_DSIPHY_CFG5);
1721 
1722 	DUMPREG(DSI_PLL_CONTROL);
1723 	DUMPREG(DSI_PLL_STATUS);
1724 	DUMPREG(DSI_PLL_GO);
1725 	DUMPREG(DSI_PLL_CONFIGURATION1);
1726 	DUMPREG(DSI_PLL_CONFIGURATION2);
1727 
1728 	dsi_disable_scp_clk(dsidev);
1729 	dsi_runtime_put(dsidev);
1730 #undef DUMPREG
1731 }
1732 
1733 static void dsi1_dump_regs(struct seq_file *s)
1734 {
1735 	struct platform_device *dsidev = dsi_get_dsidev_from_id(0);
1736 
1737 	dsi_dump_dsidev_regs(dsidev, s);
1738 }
1739 
1740 static void dsi2_dump_regs(struct seq_file *s)
1741 {
1742 	struct platform_device *dsidev = dsi_get_dsidev_from_id(1);
1743 
1744 	dsi_dump_dsidev_regs(dsidev, s);
1745 }
1746 
1747 enum dsi_cio_power_state {
1748 	DSI_COMPLEXIO_POWER_OFF		= 0x0,
1749 	DSI_COMPLEXIO_POWER_ON		= 0x1,
1750 	DSI_COMPLEXIO_POWER_ULPS	= 0x2,
1751 };
1752 
1753 static int dsi_cio_power(struct platform_device *dsidev,
1754 		enum dsi_cio_power_state state)
1755 {
1756 	int t = 0;
1757 
1758 	/* PWR_CMD */
1759 	REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG1, state, 28, 27);
1760 
1761 	/* PWR_STATUS */
1762 	while (FLD_GET(dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1),
1763 			26, 25) != state) {
1764 		if (++t > 1000) {
1765 			DSSERR("failed to set complexio power state to "
1766 					"%d\n", state);
1767 			return -ENODEV;
1768 		}
1769 		udelay(1);
1770 	}
1771 
1772 	return 0;
1773 }
1774 
1775 static unsigned dsi_get_line_buf_size(struct platform_device *dsidev)
1776 {
1777 	int val;
1778 
1779 	/* line buffer on OMAP3 is 1024 x 24bits */
1780 	/* XXX: for some reason using full buffer size causes
1781 	 * considerable TX slowdown with update sizes that fill the
1782 	 * whole buffer */
1783 	if (!dss_has_feature(FEAT_DSI_GNQ))
1784 		return 1023 * 3;
1785 
1786 	val = REG_GET(dsidev, DSI_GNQ, 14, 12); /* VP1_LINE_BUFFER_SIZE */
1787 
1788 	switch (val) {
1789 	case 1:
1790 		return 512 * 3;		/* 512x24 bits */
1791 	case 2:
1792 		return 682 * 3;		/* 682x24 bits */
1793 	case 3:
1794 		return 853 * 3;		/* 853x24 bits */
1795 	case 4:
1796 		return 1024 * 3;	/* 1024x24 bits */
1797 	case 5:
1798 		return 1194 * 3;	/* 1194x24 bits */
1799 	case 6:
1800 		return 1365 * 3;	/* 1365x24 bits */
1801 	case 7:
1802 		return 1920 * 3;	/* 1920x24 bits */
1803 	default:
1804 		BUG();
1805 		return 0;
1806 	}
1807 }
1808 
1809 static int dsi_set_lane_config(struct platform_device *dsidev)
1810 {
1811 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1812 	static const u8 offsets[] = { 0, 4, 8, 12, 16 };
1813 	static const enum dsi_lane_function functions[] = {
1814 		DSI_LANE_CLK,
1815 		DSI_LANE_DATA1,
1816 		DSI_LANE_DATA2,
1817 		DSI_LANE_DATA3,
1818 		DSI_LANE_DATA4,
1819 	};
1820 	u32 r;
1821 	int i;
1822 
1823 	r = dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1);
1824 
1825 	for (i = 0; i < dsi->num_lanes_used; ++i) {
1826 		unsigned offset = offsets[i];
1827 		unsigned polarity, lane_number;
1828 		unsigned t;
1829 
1830 		for (t = 0; t < dsi->num_lanes_supported; ++t)
1831 			if (dsi->lanes[t].function == functions[i])
1832 				break;
1833 
1834 		if (t == dsi->num_lanes_supported)
1835 			return -EINVAL;
1836 
1837 		lane_number = t;
1838 		polarity = dsi->lanes[t].polarity;
1839 
1840 		r = FLD_MOD(r, lane_number + 1, offset + 2, offset);
1841 		r = FLD_MOD(r, polarity, offset + 3, offset + 3);
1842 	}
1843 
1844 	/* clear the unused lanes */
1845 	for (; i < dsi->num_lanes_supported; ++i) {
1846 		unsigned offset = offsets[i];
1847 
1848 		r = FLD_MOD(r, 0, offset + 2, offset);
1849 		r = FLD_MOD(r, 0, offset + 3, offset + 3);
1850 	}
1851 
1852 	dsi_write_reg(dsidev, DSI_COMPLEXIO_CFG1, r);
1853 
1854 	return 0;
1855 }
1856 
1857 static inline unsigned ns2ddr(struct platform_device *dsidev, unsigned ns)
1858 {
1859 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1860 
1861 	/* convert time in ns to ddr ticks, rounding up */
1862 	unsigned long ddr_clk = dsi->pll.cinfo.clkdco / 4;
1863 	return (ns * (ddr_clk / 1000 / 1000) + 999) / 1000;
1864 }
1865 
1866 static inline unsigned ddr2ns(struct platform_device *dsidev, unsigned ddr)
1867 {
1868 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1869 
1870 	unsigned long ddr_clk = dsi->pll.cinfo.clkdco / 4;
1871 	return ddr * 1000 * 1000 / (ddr_clk / 1000);
1872 }
1873 
1874 static void dsi_cio_timings(struct platform_device *dsidev)
1875 {
1876 	u32 r;
1877 	u32 ths_prepare, ths_prepare_ths_zero, ths_trail, ths_exit;
1878 	u32 tlpx_half, tclk_trail, tclk_zero;
1879 	u32 tclk_prepare;
1880 
1881 	/* calculate timings */
1882 
1883 	/* 1 * DDR_CLK = 2 * UI */
1884 
1885 	/* min 40ns + 4*UI	max 85ns + 6*UI */
1886 	ths_prepare = ns2ddr(dsidev, 70) + 2;
1887 
1888 	/* min 145ns + 10*UI */
1889 	ths_prepare_ths_zero = ns2ddr(dsidev, 175) + 2;
1890 
1891 	/* min max(8*UI, 60ns+4*UI) */
1892 	ths_trail = ns2ddr(dsidev, 60) + 5;
1893 
1894 	/* min 100ns */
1895 	ths_exit = ns2ddr(dsidev, 145);
1896 
1897 	/* tlpx min 50n */
1898 	tlpx_half = ns2ddr(dsidev, 25);
1899 
1900 	/* min 60ns */
1901 	tclk_trail = ns2ddr(dsidev, 60) + 2;
1902 
1903 	/* min 38ns, max 95ns */
1904 	tclk_prepare = ns2ddr(dsidev, 65);
1905 
1906 	/* min tclk-prepare + tclk-zero = 300ns */
1907 	tclk_zero = ns2ddr(dsidev, 260);
1908 
1909 	DSSDBG("ths_prepare %u (%uns), ths_prepare_ths_zero %u (%uns)\n",
1910 		ths_prepare, ddr2ns(dsidev, ths_prepare),
1911 		ths_prepare_ths_zero, ddr2ns(dsidev, ths_prepare_ths_zero));
1912 	DSSDBG("ths_trail %u (%uns), ths_exit %u (%uns)\n",
1913 			ths_trail, ddr2ns(dsidev, ths_trail),
1914 			ths_exit, ddr2ns(dsidev, ths_exit));
1915 
1916 	DSSDBG("tlpx_half %u (%uns), tclk_trail %u (%uns), "
1917 			"tclk_zero %u (%uns)\n",
1918 			tlpx_half, ddr2ns(dsidev, tlpx_half),
1919 			tclk_trail, ddr2ns(dsidev, tclk_trail),
1920 			tclk_zero, ddr2ns(dsidev, tclk_zero));
1921 	DSSDBG("tclk_prepare %u (%uns)\n",
1922 			tclk_prepare, ddr2ns(dsidev, tclk_prepare));
1923 
1924 	/* program timings */
1925 
1926 	r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0);
1927 	r = FLD_MOD(r, ths_prepare, 31, 24);
1928 	r = FLD_MOD(r, ths_prepare_ths_zero, 23, 16);
1929 	r = FLD_MOD(r, ths_trail, 15, 8);
1930 	r = FLD_MOD(r, ths_exit, 7, 0);
1931 	dsi_write_reg(dsidev, DSI_DSIPHY_CFG0, r);
1932 
1933 	r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1);
1934 	r = FLD_MOD(r, tlpx_half, 20, 16);
1935 	r = FLD_MOD(r, tclk_trail, 15, 8);
1936 	r = FLD_MOD(r, tclk_zero, 7, 0);
1937 
1938 	if (dss_has_feature(FEAT_DSI_PHY_DCC)) {
1939 		r = FLD_MOD(r, 0, 21, 21);	/* DCCEN = disable */
1940 		r = FLD_MOD(r, 1, 22, 22);	/* CLKINP_DIVBY2EN = enable */
1941 		r = FLD_MOD(r, 1, 23, 23);	/* CLKINP_SEL = enable */
1942 	}
1943 
1944 	dsi_write_reg(dsidev, DSI_DSIPHY_CFG1, r);
1945 
1946 	r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG2);
1947 	r = FLD_MOD(r, tclk_prepare, 7, 0);
1948 	dsi_write_reg(dsidev, DSI_DSIPHY_CFG2, r);
1949 }
1950 
1951 /* lane masks have lane 0 at lsb. mask_p for positive lines, n for negative */
1952 static void dsi_cio_enable_lane_override(struct platform_device *dsidev,
1953 		unsigned mask_p, unsigned mask_n)
1954 {
1955 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1956 	int i;
1957 	u32 l;
1958 	u8 lptxscp_start = dsi->num_lanes_supported == 3 ? 22 : 26;
1959 
1960 	l = 0;
1961 
1962 	for (i = 0; i < dsi->num_lanes_supported; ++i) {
1963 		unsigned p = dsi->lanes[i].polarity;
1964 
1965 		if (mask_p & (1 << i))
1966 			l |= 1 << (i * 2 + (p ? 0 : 1));
1967 
1968 		if (mask_n & (1 << i))
1969 			l |= 1 << (i * 2 + (p ? 1 : 0));
1970 	}
1971 
1972 	/*
1973 	 * Bits in REGLPTXSCPDAT4TO0DXDY:
1974 	 * 17: DY0 18: DX0
1975 	 * 19: DY1 20: DX1
1976 	 * 21: DY2 22: DX2
1977 	 * 23: DY3 24: DX3
1978 	 * 25: DY4 26: DX4
1979 	 */
1980 
1981 	/* Set the lane override configuration */
1982 
1983 	/* REGLPTXSCPDAT4TO0DXDY */
1984 	REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, l, lptxscp_start, 17);
1985 
1986 	/* Enable lane override */
1987 
1988 	/* ENLPTXSCPDAT */
1989 	REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 1, 27, 27);
1990 }
1991 
1992 static void dsi_cio_disable_lane_override(struct platform_device *dsidev)
1993 {
1994 	/* Disable lane override */
1995 	REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 0, 27, 27); /* ENLPTXSCPDAT */
1996 	/* Reset the lane override configuration */
1997 	/* REGLPTXSCPDAT4TO0DXDY */
1998 	REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 0, 22, 17);
1999 }
2000 
2001 static int dsi_cio_wait_tx_clk_esc_reset(struct platform_device *dsidev)
2002 {
2003 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2004 	int t, i;
2005 	bool in_use[DSI_MAX_NR_LANES];
2006 	static const u8 offsets_old[] = { 28, 27, 26 };
2007 	static const u8 offsets_new[] = { 24, 25, 26, 27, 28 };
2008 	const u8 *offsets;
2009 
2010 	if (dss_has_feature(FEAT_DSI_REVERSE_TXCLKESC))
2011 		offsets = offsets_old;
2012 	else
2013 		offsets = offsets_new;
2014 
2015 	for (i = 0; i < dsi->num_lanes_supported; ++i)
2016 		in_use[i] = dsi->lanes[i].function != DSI_LANE_UNUSED;
2017 
2018 	t = 100000;
2019 	while (true) {
2020 		u32 l;
2021 		int ok;
2022 
2023 		l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
2024 
2025 		ok = 0;
2026 		for (i = 0; i < dsi->num_lanes_supported; ++i) {
2027 			if (!in_use[i] || (l & (1 << offsets[i])))
2028 				ok++;
2029 		}
2030 
2031 		if (ok == dsi->num_lanes_supported)
2032 			break;
2033 
2034 		if (--t == 0) {
2035 			for (i = 0; i < dsi->num_lanes_supported; ++i) {
2036 				if (!in_use[i] || (l & (1 << offsets[i])))
2037 					continue;
2038 
2039 				DSSERR("CIO TXCLKESC%d domain not coming " \
2040 						"out of reset\n", i);
2041 			}
2042 			return -EIO;
2043 		}
2044 	}
2045 
2046 	return 0;
2047 }
2048 
2049 /* return bitmask of enabled lanes, lane0 being the lsb */
2050 static unsigned dsi_get_lane_mask(struct platform_device *dsidev)
2051 {
2052 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2053 	unsigned mask = 0;
2054 	int i;
2055 
2056 	for (i = 0; i < dsi->num_lanes_supported; ++i) {
2057 		if (dsi->lanes[i].function != DSI_LANE_UNUSED)
2058 			mask |= 1 << i;
2059 	}
2060 
2061 	return mask;
2062 }
2063 
2064 static int dsi_cio_init(struct platform_device *dsidev)
2065 {
2066 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2067 	int r;
2068 	u32 l;
2069 
2070 	DSSDBG("DSI CIO init starts");
2071 
2072 	r = dss_dsi_enable_pads(dsi->module_id, dsi_get_lane_mask(dsidev));
2073 	if (r)
2074 		return r;
2075 
2076 	dsi_enable_scp_clk(dsidev);
2077 
2078 	/* A dummy read using the SCP interface to any DSIPHY register is
2079 	 * required after DSIPHY reset to complete the reset of the DSI complex
2080 	 * I/O. */
2081 	dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
2082 
2083 	if (wait_for_bit_change(dsidev, DSI_DSIPHY_CFG5, 30, 1) != 1) {
2084 		DSSERR("CIO SCP Clock domain not coming out of reset.\n");
2085 		r = -EIO;
2086 		goto err_scp_clk_dom;
2087 	}
2088 
2089 	r = dsi_set_lane_config(dsidev);
2090 	if (r)
2091 		goto err_scp_clk_dom;
2092 
2093 	/* set TX STOP MODE timer to maximum for this operation */
2094 	l = dsi_read_reg(dsidev, DSI_TIMING1);
2095 	l = FLD_MOD(l, 1, 15, 15);	/* FORCE_TX_STOP_MODE_IO */
2096 	l = FLD_MOD(l, 1, 14, 14);	/* STOP_STATE_X16_IO */
2097 	l = FLD_MOD(l, 1, 13, 13);	/* STOP_STATE_X4_IO */
2098 	l = FLD_MOD(l, 0x1fff, 12, 0);	/* STOP_STATE_COUNTER_IO */
2099 	dsi_write_reg(dsidev, DSI_TIMING1, l);
2100 
2101 	if (dsi->ulps_enabled) {
2102 		unsigned mask_p;
2103 		int i;
2104 
2105 		DSSDBG("manual ulps exit\n");
2106 
2107 		/* ULPS is exited by Mark-1 state for 1ms, followed by
2108 		 * stop state. DSS HW cannot do this via the normal
2109 		 * ULPS exit sequence, as after reset the DSS HW thinks
2110 		 * that we are not in ULPS mode, and refuses to send the
2111 		 * sequence. So we need to send the ULPS exit sequence
2112 		 * manually by setting positive lines high and negative lines
2113 		 * low for 1ms.
2114 		 */
2115 
2116 		mask_p = 0;
2117 
2118 		for (i = 0; i < dsi->num_lanes_supported; ++i) {
2119 			if (dsi->lanes[i].function == DSI_LANE_UNUSED)
2120 				continue;
2121 			mask_p |= 1 << i;
2122 		}
2123 
2124 		dsi_cio_enable_lane_override(dsidev, mask_p, 0);
2125 	}
2126 
2127 	r = dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_ON);
2128 	if (r)
2129 		goto err_cio_pwr;
2130 
2131 	if (wait_for_bit_change(dsidev, DSI_COMPLEXIO_CFG1, 29, 1) != 1) {
2132 		DSSERR("CIO PWR clock domain not coming out of reset.\n");
2133 		r = -ENODEV;
2134 		goto err_cio_pwr_dom;
2135 	}
2136 
2137 	dsi_if_enable(dsidev, true);
2138 	dsi_if_enable(dsidev, false);
2139 	REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 20, 20); /* LP_CLK_ENABLE */
2140 
2141 	r = dsi_cio_wait_tx_clk_esc_reset(dsidev);
2142 	if (r)
2143 		goto err_tx_clk_esc_rst;
2144 
2145 	if (dsi->ulps_enabled) {
2146 		/* Keep Mark-1 state for 1ms (as per DSI spec) */
2147 		ktime_t wait = ns_to_ktime(1000 * 1000);
2148 		set_current_state(TASK_UNINTERRUPTIBLE);
2149 		schedule_hrtimeout(&wait, HRTIMER_MODE_REL);
2150 
2151 		/* Disable the override. The lanes should be set to Mark-11
2152 		 * state by the HW */
2153 		dsi_cio_disable_lane_override(dsidev);
2154 	}
2155 
2156 	/* FORCE_TX_STOP_MODE_IO */
2157 	REG_FLD_MOD(dsidev, DSI_TIMING1, 0, 15, 15);
2158 
2159 	dsi_cio_timings(dsidev);
2160 
2161 	if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
2162 		/* DDR_CLK_ALWAYS_ON */
2163 		REG_FLD_MOD(dsidev, DSI_CLK_CTRL,
2164 			dsi->vm_timings.ddr_clk_always_on, 13, 13);
2165 	}
2166 
2167 	dsi->ulps_enabled = false;
2168 
2169 	DSSDBG("CIO init done\n");
2170 
2171 	return 0;
2172 
2173 err_tx_clk_esc_rst:
2174 	REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 20, 20); /* LP_CLK_ENABLE */
2175 err_cio_pwr_dom:
2176 	dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_OFF);
2177 err_cio_pwr:
2178 	if (dsi->ulps_enabled)
2179 		dsi_cio_disable_lane_override(dsidev);
2180 err_scp_clk_dom:
2181 	dsi_disable_scp_clk(dsidev);
2182 	dss_dsi_disable_pads(dsi->module_id, dsi_get_lane_mask(dsidev));
2183 	return r;
2184 }
2185 
2186 static void dsi_cio_uninit(struct platform_device *dsidev)
2187 {
2188 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2189 
2190 	/* DDR_CLK_ALWAYS_ON */
2191 	REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 13, 13);
2192 
2193 	dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_OFF);
2194 	dsi_disable_scp_clk(dsidev);
2195 	dss_dsi_disable_pads(dsi->module_id, dsi_get_lane_mask(dsidev));
2196 }
2197 
2198 static void dsi_config_tx_fifo(struct platform_device *dsidev,
2199 		enum fifo_size size1, enum fifo_size size2,
2200 		enum fifo_size size3, enum fifo_size size4)
2201 {
2202 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2203 	u32 r = 0;
2204 	int add = 0;
2205 	int i;
2206 
2207 	dsi->vc[0].tx_fifo_size = size1;
2208 	dsi->vc[1].tx_fifo_size = size2;
2209 	dsi->vc[2].tx_fifo_size = size3;
2210 	dsi->vc[3].tx_fifo_size = size4;
2211 
2212 	for (i = 0; i < 4; i++) {
2213 		u8 v;
2214 		int size = dsi->vc[i].tx_fifo_size;
2215 
2216 		if (add + size > 4) {
2217 			DSSERR("Illegal FIFO configuration\n");
2218 			BUG();
2219 			return;
2220 		}
2221 
2222 		v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
2223 		r |= v << (8 * i);
2224 		/*DSSDBG("TX FIFO vc %d: size %d, add %d\n", i, size, add); */
2225 		add += size;
2226 	}
2227 
2228 	dsi_write_reg(dsidev, DSI_TX_FIFO_VC_SIZE, r);
2229 }
2230 
2231 static void dsi_config_rx_fifo(struct platform_device *dsidev,
2232 		enum fifo_size size1, enum fifo_size size2,
2233 		enum fifo_size size3, enum fifo_size size4)
2234 {
2235 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2236 	u32 r = 0;
2237 	int add = 0;
2238 	int i;
2239 
2240 	dsi->vc[0].rx_fifo_size = size1;
2241 	dsi->vc[1].rx_fifo_size = size2;
2242 	dsi->vc[2].rx_fifo_size = size3;
2243 	dsi->vc[3].rx_fifo_size = size4;
2244 
2245 	for (i = 0; i < 4; i++) {
2246 		u8 v;
2247 		int size = dsi->vc[i].rx_fifo_size;
2248 
2249 		if (add + size > 4) {
2250 			DSSERR("Illegal FIFO configuration\n");
2251 			BUG();
2252 			return;
2253 		}
2254 
2255 		v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
2256 		r |= v << (8 * i);
2257 		/*DSSDBG("RX FIFO vc %d: size %d, add %d\n", i, size, add); */
2258 		add += size;
2259 	}
2260 
2261 	dsi_write_reg(dsidev, DSI_RX_FIFO_VC_SIZE, r);
2262 }
2263 
2264 static int dsi_force_tx_stop_mode_io(struct platform_device *dsidev)
2265 {
2266 	u32 r;
2267 
2268 	r = dsi_read_reg(dsidev, DSI_TIMING1);
2269 	r = FLD_MOD(r, 1, 15, 15);	/* FORCE_TX_STOP_MODE_IO */
2270 	dsi_write_reg(dsidev, DSI_TIMING1, r);
2271 
2272 	if (wait_for_bit_change(dsidev, DSI_TIMING1, 15, 0) != 0) {
2273 		DSSERR("TX_STOP bit not going down\n");
2274 		return -EIO;
2275 	}
2276 
2277 	return 0;
2278 }
2279 
2280 static bool dsi_vc_is_enabled(struct platform_device *dsidev, int channel)
2281 {
2282 	return REG_GET(dsidev, DSI_VC_CTRL(channel), 0, 0);
2283 }
2284 
2285 static void dsi_packet_sent_handler_vp(void *data, u32 mask)
2286 {
2287 	struct dsi_packet_sent_handler_data *vp_data =
2288 		(struct dsi_packet_sent_handler_data *) data;
2289 	struct dsi_data *dsi = dsi_get_dsidrv_data(vp_data->dsidev);
2290 	const int channel = dsi->update_channel;
2291 	u8 bit = dsi->te_enabled ? 30 : 31;
2292 
2293 	if (REG_GET(vp_data->dsidev, DSI_VC_TE(channel), bit, bit) == 0)
2294 		complete(vp_data->completion);
2295 }
2296 
2297 static int dsi_sync_vc_vp(struct platform_device *dsidev, int channel)
2298 {
2299 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2300 	DECLARE_COMPLETION_ONSTACK(completion);
2301 	struct dsi_packet_sent_handler_data vp_data = {
2302 		.dsidev = dsidev,
2303 		.completion = &completion
2304 	};
2305 	int r = 0;
2306 	u8 bit;
2307 
2308 	bit = dsi->te_enabled ? 30 : 31;
2309 
2310 	r = dsi_register_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp,
2311 		&vp_data, DSI_VC_IRQ_PACKET_SENT);
2312 	if (r)
2313 		goto err0;
2314 
2315 	/* Wait for completion only if TE_EN/TE_START is still set */
2316 	if (REG_GET(dsidev, DSI_VC_TE(channel), bit, bit)) {
2317 		if (wait_for_completion_timeout(&completion,
2318 				msecs_to_jiffies(10)) == 0) {
2319 			DSSERR("Failed to complete previous frame transfer\n");
2320 			r = -EIO;
2321 			goto err1;
2322 		}
2323 	}
2324 
2325 	dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp,
2326 		&vp_data, DSI_VC_IRQ_PACKET_SENT);
2327 
2328 	return 0;
2329 err1:
2330 	dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp,
2331 		&vp_data, DSI_VC_IRQ_PACKET_SENT);
2332 err0:
2333 	return r;
2334 }
2335 
2336 static void dsi_packet_sent_handler_l4(void *data, u32 mask)
2337 {
2338 	struct dsi_packet_sent_handler_data *l4_data =
2339 		(struct dsi_packet_sent_handler_data *) data;
2340 	struct dsi_data *dsi = dsi_get_dsidrv_data(l4_data->dsidev);
2341 	const int channel = dsi->update_channel;
2342 
2343 	if (REG_GET(l4_data->dsidev, DSI_VC_CTRL(channel), 5, 5) == 0)
2344 		complete(l4_data->completion);
2345 }
2346 
2347 static int dsi_sync_vc_l4(struct platform_device *dsidev, int channel)
2348 {
2349 	DECLARE_COMPLETION_ONSTACK(completion);
2350 	struct dsi_packet_sent_handler_data l4_data = {
2351 		.dsidev = dsidev,
2352 		.completion = &completion
2353 	};
2354 	int r = 0;
2355 
2356 	r = dsi_register_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4,
2357 		&l4_data, DSI_VC_IRQ_PACKET_SENT);
2358 	if (r)
2359 		goto err0;
2360 
2361 	/* Wait for completion only if TX_FIFO_NOT_EMPTY is still set */
2362 	if (REG_GET(dsidev, DSI_VC_CTRL(channel), 5, 5)) {
2363 		if (wait_for_completion_timeout(&completion,
2364 				msecs_to_jiffies(10)) == 0) {
2365 			DSSERR("Failed to complete previous l4 transfer\n");
2366 			r = -EIO;
2367 			goto err1;
2368 		}
2369 	}
2370 
2371 	dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4,
2372 		&l4_data, DSI_VC_IRQ_PACKET_SENT);
2373 
2374 	return 0;
2375 err1:
2376 	dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4,
2377 		&l4_data, DSI_VC_IRQ_PACKET_SENT);
2378 err0:
2379 	return r;
2380 }
2381 
2382 static int dsi_sync_vc(struct platform_device *dsidev, int channel)
2383 {
2384 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2385 
2386 	WARN_ON(!dsi_bus_is_locked(dsidev));
2387 
2388 	WARN_ON(in_interrupt());
2389 
2390 	if (!dsi_vc_is_enabled(dsidev, channel))
2391 		return 0;
2392 
2393 	switch (dsi->vc[channel].source) {
2394 	case DSI_VC_SOURCE_VP:
2395 		return dsi_sync_vc_vp(dsidev, channel);
2396 	case DSI_VC_SOURCE_L4:
2397 		return dsi_sync_vc_l4(dsidev, channel);
2398 	default:
2399 		BUG();
2400 		return -EINVAL;
2401 	}
2402 }
2403 
2404 static int dsi_vc_enable(struct platform_device *dsidev, int channel,
2405 		bool enable)
2406 {
2407 	DSSDBG("dsi_vc_enable channel %d, enable %d\n",
2408 			channel, enable);
2409 
2410 	enable = enable ? 1 : 0;
2411 
2412 	REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 0, 0);
2413 
2414 	if (wait_for_bit_change(dsidev, DSI_VC_CTRL(channel),
2415 		0, enable) != enable) {
2416 			DSSERR("Failed to set dsi_vc_enable to %d\n", enable);
2417 			return -EIO;
2418 	}
2419 
2420 	return 0;
2421 }
2422 
2423 static void dsi_vc_initial_config(struct platform_device *dsidev, int channel)
2424 {
2425 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2426 	u32 r;
2427 
2428 	DSSDBG("Initial config of virtual channel %d", channel);
2429 
2430 	r = dsi_read_reg(dsidev, DSI_VC_CTRL(channel));
2431 
2432 	if (FLD_GET(r, 15, 15)) /* VC_BUSY */
2433 		DSSERR("VC(%d) busy when trying to configure it!\n",
2434 				channel);
2435 
2436 	r = FLD_MOD(r, 0, 1, 1); /* SOURCE, 0 = L4 */
2437 	r = FLD_MOD(r, 0, 2, 2); /* BTA_SHORT_EN  */
2438 	r = FLD_MOD(r, 0, 3, 3); /* BTA_LONG_EN */
2439 	r = FLD_MOD(r, 0, 4, 4); /* MODE, 0 = command */
2440 	r = FLD_MOD(r, 1, 7, 7); /* CS_TX_EN */
2441 	r = FLD_MOD(r, 1, 8, 8); /* ECC_TX_EN */
2442 	r = FLD_MOD(r, 0, 9, 9); /* MODE_SPEED, high speed on/off */
2443 	if (dss_has_feature(FEAT_DSI_VC_OCP_WIDTH))
2444 		r = FLD_MOD(r, 3, 11, 10);	/* OCP_WIDTH = 32 bit */
2445 
2446 	r = FLD_MOD(r, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */
2447 	r = FLD_MOD(r, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */
2448 
2449 	dsi_write_reg(dsidev, DSI_VC_CTRL(channel), r);
2450 
2451 	dsi->vc[channel].source = DSI_VC_SOURCE_L4;
2452 }
2453 
2454 static int dsi_vc_config_source(struct platform_device *dsidev, int channel,
2455 		enum dsi_vc_source source)
2456 {
2457 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2458 
2459 	if (dsi->vc[channel].source == source)
2460 		return 0;
2461 
2462 	DSSDBG("Source config of virtual channel %d", channel);
2463 
2464 	dsi_sync_vc(dsidev, channel);
2465 
2466 	dsi_vc_enable(dsidev, channel, 0);
2467 
2468 	/* VC_BUSY */
2469 	if (wait_for_bit_change(dsidev, DSI_VC_CTRL(channel), 15, 0) != 0) {
2470 		DSSERR("vc(%d) busy when trying to config for VP\n", channel);
2471 		return -EIO;
2472 	}
2473 
2474 	/* SOURCE, 0 = L4, 1 = video port */
2475 	REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), source, 1, 1);
2476 
2477 	/* DCS_CMD_ENABLE */
2478 	if (dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC)) {
2479 		bool enable = source == DSI_VC_SOURCE_VP;
2480 		REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 30, 30);
2481 	}
2482 
2483 	dsi_vc_enable(dsidev, channel, 1);
2484 
2485 	dsi->vc[channel].source = source;
2486 
2487 	return 0;
2488 }
2489 
2490 static void dsi_vc_enable_hs(struct omap_dss_device *dssdev, int channel,
2491 		bool enable)
2492 {
2493 	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2494 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2495 
2496 	DSSDBG("dsi_vc_enable_hs(%d, %d)\n", channel, enable);
2497 
2498 	WARN_ON(!dsi_bus_is_locked(dsidev));
2499 
2500 	dsi_vc_enable(dsidev, channel, 0);
2501 	dsi_if_enable(dsidev, 0);
2502 
2503 	REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 9, 9);
2504 
2505 	dsi_vc_enable(dsidev, channel, 1);
2506 	dsi_if_enable(dsidev, 1);
2507 
2508 	dsi_force_tx_stop_mode_io(dsidev);
2509 
2510 	/* start the DDR clock by sending a NULL packet */
2511 	if (dsi->vm_timings.ddr_clk_always_on && enable)
2512 		dsi_vc_send_null(dssdev, channel);
2513 }
2514 
2515 static void dsi_vc_flush_long_data(struct platform_device *dsidev, int channel)
2516 {
2517 	while (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
2518 		u32 val;
2519 		val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));
2520 		DSSDBG("\t\tb1 %#02x b2 %#02x b3 %#02x b4 %#02x\n",
2521 				(val >> 0) & 0xff,
2522 				(val >> 8) & 0xff,
2523 				(val >> 16) & 0xff,
2524 				(val >> 24) & 0xff);
2525 	}
2526 }
2527 
2528 static void dsi_show_rx_ack_with_err(u16 err)
2529 {
2530 	DSSERR("\tACK with ERROR (%#x):\n", err);
2531 	if (err & (1 << 0))
2532 		DSSERR("\t\tSoT Error\n");
2533 	if (err & (1 << 1))
2534 		DSSERR("\t\tSoT Sync Error\n");
2535 	if (err & (1 << 2))
2536 		DSSERR("\t\tEoT Sync Error\n");
2537 	if (err & (1 << 3))
2538 		DSSERR("\t\tEscape Mode Entry Command Error\n");
2539 	if (err & (1 << 4))
2540 		DSSERR("\t\tLP Transmit Sync Error\n");
2541 	if (err & (1 << 5))
2542 		DSSERR("\t\tHS Receive Timeout Error\n");
2543 	if (err & (1 << 6))
2544 		DSSERR("\t\tFalse Control Error\n");
2545 	if (err & (1 << 7))
2546 		DSSERR("\t\t(reserved7)\n");
2547 	if (err & (1 << 8))
2548 		DSSERR("\t\tECC Error, single-bit (corrected)\n");
2549 	if (err & (1 << 9))
2550 		DSSERR("\t\tECC Error, multi-bit (not corrected)\n");
2551 	if (err & (1 << 10))
2552 		DSSERR("\t\tChecksum Error\n");
2553 	if (err & (1 << 11))
2554 		DSSERR("\t\tData type not recognized\n");
2555 	if (err & (1 << 12))
2556 		DSSERR("\t\tInvalid VC ID\n");
2557 	if (err & (1 << 13))
2558 		DSSERR("\t\tInvalid Transmission Length\n");
2559 	if (err & (1 << 14))
2560 		DSSERR("\t\t(reserved14)\n");
2561 	if (err & (1 << 15))
2562 		DSSERR("\t\tDSI Protocol Violation\n");
2563 }
2564 
2565 static u16 dsi_vc_flush_receive_data(struct platform_device *dsidev,
2566 		int channel)
2567 {
2568 	/* RX_FIFO_NOT_EMPTY */
2569 	while (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
2570 		u32 val;
2571 		u8 dt;
2572 		val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));
2573 		DSSERR("\trawval %#08x\n", val);
2574 		dt = FLD_GET(val, 5, 0);
2575 		if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) {
2576 			u16 err = FLD_GET(val, 23, 8);
2577 			dsi_show_rx_ack_with_err(err);
2578 		} else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE) {
2579 			DSSERR("\tDCS short response, 1 byte: %#x\n",
2580 					FLD_GET(val, 23, 8));
2581 		} else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE) {
2582 			DSSERR("\tDCS short response, 2 byte: %#x\n",
2583 					FLD_GET(val, 23, 8));
2584 		} else if (dt == MIPI_DSI_RX_DCS_LONG_READ_RESPONSE) {
2585 			DSSERR("\tDCS long response, len %d\n",
2586 					FLD_GET(val, 23, 8));
2587 			dsi_vc_flush_long_data(dsidev, channel);
2588 		} else {
2589 			DSSERR("\tunknown datatype 0x%02x\n", dt);
2590 		}
2591 	}
2592 	return 0;
2593 }
2594 
2595 static int dsi_vc_send_bta(struct platform_device *dsidev, int channel)
2596 {
2597 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2598 
2599 	if (dsi->debug_write || dsi->debug_read)
2600 		DSSDBG("dsi_vc_send_bta %d\n", channel);
2601 
2602 	WARN_ON(!dsi_bus_is_locked(dsidev));
2603 
2604 	/* RX_FIFO_NOT_EMPTY */
2605 	if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
2606 		DSSERR("rx fifo not empty when sending BTA, dumping data:\n");
2607 		dsi_vc_flush_receive_data(dsidev, channel);
2608 	}
2609 
2610 	REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 1, 6, 6); /* BTA_EN */
2611 
2612 	/* flush posted write */
2613 	dsi_read_reg(dsidev, DSI_VC_CTRL(channel));
2614 
2615 	return 0;
2616 }
2617 
2618 static int dsi_vc_send_bta_sync(struct omap_dss_device *dssdev, int channel)
2619 {
2620 	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2621 	DECLARE_COMPLETION_ONSTACK(completion);
2622 	int r = 0;
2623 	u32 err;
2624 
2625 	r = dsi_register_isr_vc(dsidev, channel, dsi_completion_handler,
2626 			&completion, DSI_VC_IRQ_BTA);
2627 	if (r)
2628 		goto err0;
2629 
2630 	r = dsi_register_isr(dsidev, dsi_completion_handler, &completion,
2631 			DSI_IRQ_ERROR_MASK);
2632 	if (r)
2633 		goto err1;
2634 
2635 	r = dsi_vc_send_bta(dsidev, channel);
2636 	if (r)
2637 		goto err2;
2638 
2639 	if (wait_for_completion_timeout(&completion,
2640 				msecs_to_jiffies(500)) == 0) {
2641 		DSSERR("Failed to receive BTA\n");
2642 		r = -EIO;
2643 		goto err2;
2644 	}
2645 
2646 	err = dsi_get_errors(dsidev);
2647 	if (err) {
2648 		DSSERR("Error while sending BTA: %x\n", err);
2649 		r = -EIO;
2650 		goto err2;
2651 	}
2652 err2:
2653 	dsi_unregister_isr(dsidev, dsi_completion_handler, &completion,
2654 			DSI_IRQ_ERROR_MASK);
2655 err1:
2656 	dsi_unregister_isr_vc(dsidev, channel, dsi_completion_handler,
2657 			&completion, DSI_VC_IRQ_BTA);
2658 err0:
2659 	return r;
2660 }
2661 
2662 static inline void dsi_vc_write_long_header(struct platform_device *dsidev,
2663 		int channel, u8 data_type, u16 len, u8 ecc)
2664 {
2665 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2666 	u32 val;
2667 	u8 data_id;
2668 
2669 	WARN_ON(!dsi_bus_is_locked(dsidev));
2670 
2671 	data_id = data_type | dsi->vc[channel].vc_id << 6;
2672 
2673 	val = FLD_VAL(data_id, 7, 0) | FLD_VAL(len, 23, 8) |
2674 		FLD_VAL(ecc, 31, 24);
2675 
2676 	dsi_write_reg(dsidev, DSI_VC_LONG_PACKET_HEADER(channel), val);
2677 }
2678 
2679 static inline void dsi_vc_write_long_payload(struct platform_device *dsidev,
2680 		int channel, u8 b1, u8 b2, u8 b3, u8 b4)
2681 {
2682 	u32 val;
2683 
2684 	val = b4 << 24 | b3 << 16 | b2 << 8  | b1 << 0;
2685 
2686 /*	DSSDBG("\twriting %02x, %02x, %02x, %02x (%#010x)\n",
2687 			b1, b2, b3, b4, val); */
2688 
2689 	dsi_write_reg(dsidev, DSI_VC_LONG_PACKET_PAYLOAD(channel), val);
2690 }
2691 
2692 static int dsi_vc_send_long(struct platform_device *dsidev, int channel,
2693 		u8 data_type, u8 *data, u16 len, u8 ecc)
2694 {
2695 	/*u32 val; */
2696 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2697 	int i;
2698 	u8 *p;
2699 	int r = 0;
2700 	u8 b1, b2, b3, b4;
2701 
2702 	if (dsi->debug_write)
2703 		DSSDBG("dsi_vc_send_long, %d bytes\n", len);
2704 
2705 	/* len + header */
2706 	if (dsi->vc[channel].tx_fifo_size * 32 * 4 < len + 4) {
2707 		DSSERR("unable to send long packet: packet too long.\n");
2708 		return -EINVAL;
2709 	}
2710 
2711 	dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_L4);
2712 
2713 	dsi_vc_write_long_header(dsidev, channel, data_type, len, ecc);
2714 
2715 	p = data;
2716 	for (i = 0; i < len >> 2; i++) {
2717 		if (dsi->debug_write)
2718 			DSSDBG("\tsending full packet %d\n", i);
2719 
2720 		b1 = *p++;
2721 		b2 = *p++;
2722 		b3 = *p++;
2723 		b4 = *p++;
2724 
2725 		dsi_vc_write_long_payload(dsidev, channel, b1, b2, b3, b4);
2726 	}
2727 
2728 	i = len % 4;
2729 	if (i) {
2730 		b1 = 0; b2 = 0; b3 = 0;
2731 
2732 		if (dsi->debug_write)
2733 			DSSDBG("\tsending remainder bytes %d\n", i);
2734 
2735 		switch (i) {
2736 		case 3:
2737 			b1 = *p++;
2738 			b2 = *p++;
2739 			b3 = *p++;
2740 			break;
2741 		case 2:
2742 			b1 = *p++;
2743 			b2 = *p++;
2744 			break;
2745 		case 1:
2746 			b1 = *p++;
2747 			break;
2748 		}
2749 
2750 		dsi_vc_write_long_payload(dsidev, channel, b1, b2, b3, 0);
2751 	}
2752 
2753 	return r;
2754 }
2755 
2756 static int dsi_vc_send_short(struct platform_device *dsidev, int channel,
2757 		u8 data_type, u16 data, u8 ecc)
2758 {
2759 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2760 	u32 r;
2761 	u8 data_id;
2762 
2763 	WARN_ON(!dsi_bus_is_locked(dsidev));
2764 
2765 	if (dsi->debug_write)
2766 		DSSDBG("dsi_vc_send_short(ch%d, dt %#x, b1 %#x, b2 %#x)\n",
2767 				channel,
2768 				data_type, data & 0xff, (data >> 8) & 0xff);
2769 
2770 	dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_L4);
2771 
2772 	if (FLD_GET(dsi_read_reg(dsidev, DSI_VC_CTRL(channel)), 16, 16)) {
2773 		DSSERR("ERROR FIFO FULL, aborting transfer\n");
2774 		return -EINVAL;
2775 	}
2776 
2777 	data_id = data_type | dsi->vc[channel].vc_id << 6;
2778 
2779 	r = (data_id << 0) | (data << 8) | (ecc << 24);
2780 
2781 	dsi_write_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel), r);
2782 
2783 	return 0;
2784 }
2785 
2786 static int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel)
2787 {
2788 	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2789 
2790 	return dsi_vc_send_long(dsidev, channel, MIPI_DSI_NULL_PACKET, NULL,
2791 		0, 0);
2792 }
2793 
2794 static int dsi_vc_write_nosync_common(struct platform_device *dsidev,
2795 		int channel, u8 *data, int len, enum dss_dsi_content_type type)
2796 {
2797 	int r;
2798 
2799 	if (len == 0) {
2800 		BUG_ON(type == DSS_DSI_CONTENT_DCS);
2801 		r = dsi_vc_send_short(dsidev, channel,
2802 				MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM, 0, 0);
2803 	} else if (len == 1) {
2804 		r = dsi_vc_send_short(dsidev, channel,
2805 				type == DSS_DSI_CONTENT_GENERIC ?
2806 				MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM :
2807 				MIPI_DSI_DCS_SHORT_WRITE, data[0], 0);
2808 	} else if (len == 2) {
2809 		r = dsi_vc_send_short(dsidev, channel,
2810 				type == DSS_DSI_CONTENT_GENERIC ?
2811 				MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM :
2812 				MIPI_DSI_DCS_SHORT_WRITE_PARAM,
2813 				data[0] | (data[1] << 8), 0);
2814 	} else {
2815 		r = dsi_vc_send_long(dsidev, channel,
2816 				type == DSS_DSI_CONTENT_GENERIC ?
2817 				MIPI_DSI_GENERIC_LONG_WRITE :
2818 				MIPI_DSI_DCS_LONG_WRITE, data, len, 0);
2819 	}
2820 
2821 	return r;
2822 }
2823 
2824 static int dsi_vc_dcs_write_nosync(struct omap_dss_device *dssdev, int channel,
2825 		u8 *data, int len)
2826 {
2827 	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2828 
2829 	return dsi_vc_write_nosync_common(dsidev, channel, data, len,
2830 			DSS_DSI_CONTENT_DCS);
2831 }
2832 
2833 static int dsi_vc_generic_write_nosync(struct omap_dss_device *dssdev, int channel,
2834 		u8 *data, int len)
2835 {
2836 	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2837 
2838 	return dsi_vc_write_nosync_common(dsidev, channel, data, len,
2839 			DSS_DSI_CONTENT_GENERIC);
2840 }
2841 
2842 static int dsi_vc_write_common(struct omap_dss_device *dssdev, int channel,
2843 		u8 *data, int len, enum dss_dsi_content_type type)
2844 {
2845 	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2846 	int r;
2847 
2848 	r = dsi_vc_write_nosync_common(dsidev, channel, data, len, type);
2849 	if (r)
2850 		goto err;
2851 
2852 	r = dsi_vc_send_bta_sync(dssdev, channel);
2853 	if (r)
2854 		goto err;
2855 
2856 	/* RX_FIFO_NOT_EMPTY */
2857 	if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
2858 		DSSERR("rx fifo not empty after write, dumping data:\n");
2859 		dsi_vc_flush_receive_data(dsidev, channel);
2860 		r = -EIO;
2861 		goto err;
2862 	}
2863 
2864 	return 0;
2865 err:
2866 	DSSERR("dsi_vc_write_common(ch %d, cmd 0x%02x, len %d) failed\n",
2867 			channel, data[0], len);
2868 	return r;
2869 }
2870 
2871 static int dsi_vc_dcs_write(struct omap_dss_device *dssdev, int channel, u8 *data,
2872 		int len)
2873 {
2874 	return dsi_vc_write_common(dssdev, channel, data, len,
2875 			DSS_DSI_CONTENT_DCS);
2876 }
2877 
2878 static int dsi_vc_generic_write(struct omap_dss_device *dssdev, int channel, u8 *data,
2879 		int len)
2880 {
2881 	return dsi_vc_write_common(dssdev, channel, data, len,
2882 			DSS_DSI_CONTENT_GENERIC);
2883 }
2884 
2885 static int dsi_vc_dcs_send_read_request(struct platform_device *dsidev,
2886 		int channel, u8 dcs_cmd)
2887 {
2888 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2889 	int r;
2890 
2891 	if (dsi->debug_read)
2892 		DSSDBG("dsi_vc_dcs_send_read_request(ch%d, dcs_cmd %x)\n",
2893 			channel, dcs_cmd);
2894 
2895 	r = dsi_vc_send_short(dsidev, channel, MIPI_DSI_DCS_READ, dcs_cmd, 0);
2896 	if (r) {
2897 		DSSERR("dsi_vc_dcs_send_read_request(ch %d, cmd 0x%02x)"
2898 			" failed\n", channel, dcs_cmd);
2899 		return r;
2900 	}
2901 
2902 	return 0;
2903 }
2904 
2905 static int dsi_vc_generic_send_read_request(struct platform_device *dsidev,
2906 		int channel, u8 *reqdata, int reqlen)
2907 {
2908 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2909 	u16 data;
2910 	u8 data_type;
2911 	int r;
2912 
2913 	if (dsi->debug_read)
2914 		DSSDBG("dsi_vc_generic_send_read_request(ch %d, reqlen %d)\n",
2915 			channel, reqlen);
2916 
2917 	if (reqlen == 0) {
2918 		data_type = MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM;
2919 		data = 0;
2920 	} else if (reqlen == 1) {
2921 		data_type = MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM;
2922 		data = reqdata[0];
2923 	} else if (reqlen == 2) {
2924 		data_type = MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM;
2925 		data = reqdata[0] | (reqdata[1] << 8);
2926 	} else {
2927 		BUG();
2928 		return -EINVAL;
2929 	}
2930 
2931 	r = dsi_vc_send_short(dsidev, channel, data_type, data, 0);
2932 	if (r) {
2933 		DSSERR("dsi_vc_generic_send_read_request(ch %d, reqlen %d)"
2934 			" failed\n", channel, reqlen);
2935 		return r;
2936 	}
2937 
2938 	return 0;
2939 }
2940 
2941 static int dsi_vc_read_rx_fifo(struct platform_device *dsidev, int channel,
2942 		u8 *buf, int buflen, enum dss_dsi_content_type type)
2943 {
2944 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2945 	u32 val;
2946 	u8 dt;
2947 	int r;
2948 
2949 	/* RX_FIFO_NOT_EMPTY */
2950 	if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20) == 0) {
2951 		DSSERR("RX fifo empty when trying to read.\n");
2952 		r = -EIO;
2953 		goto err;
2954 	}
2955 
2956 	val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));
2957 	if (dsi->debug_read)
2958 		DSSDBG("\theader: %08x\n", val);
2959 	dt = FLD_GET(val, 5, 0);
2960 	if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) {
2961 		u16 err = FLD_GET(val, 23, 8);
2962 		dsi_show_rx_ack_with_err(err);
2963 		r = -EIO;
2964 		goto err;
2965 
2966 	} else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
2967 			MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE :
2968 			MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE)) {
2969 		u8 data = FLD_GET(val, 15, 8);
2970 		if (dsi->debug_read)
2971 			DSSDBG("\t%s short response, 1 byte: %02x\n",
2972 				type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
2973 				"DCS", data);
2974 
2975 		if (buflen < 1) {
2976 			r = -EIO;
2977 			goto err;
2978 		}
2979 
2980 		buf[0] = data;
2981 
2982 		return 1;
2983 	} else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
2984 			MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE :
2985 			MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE)) {
2986 		u16 data = FLD_GET(val, 23, 8);
2987 		if (dsi->debug_read)
2988 			DSSDBG("\t%s short response, 2 byte: %04x\n",
2989 				type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
2990 				"DCS", data);
2991 
2992 		if (buflen < 2) {
2993 			r = -EIO;
2994 			goto err;
2995 		}
2996 
2997 		buf[0] = data & 0xff;
2998 		buf[1] = (data >> 8) & 0xff;
2999 
3000 		return 2;
3001 	} else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
3002 			MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE :
3003 			MIPI_DSI_RX_DCS_LONG_READ_RESPONSE)) {
3004 		int w;
3005 		int len = FLD_GET(val, 23, 8);
3006 		if (dsi->debug_read)
3007 			DSSDBG("\t%s long response, len %d\n",
3008 				type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
3009 				"DCS", len);
3010 
3011 		if (len > buflen) {
3012 			r = -EIO;
3013 			goto err;
3014 		}
3015 
3016 		/* two byte checksum ends the packet, not included in len */
3017 		for (w = 0; w < len + 2;) {
3018 			int b;
3019 			val = dsi_read_reg(dsidev,
3020 				DSI_VC_SHORT_PACKET_HEADER(channel));
3021 			if (dsi->debug_read)
3022 				DSSDBG("\t\t%02x %02x %02x %02x\n",
3023 						(val >> 0) & 0xff,
3024 						(val >> 8) & 0xff,
3025 						(val >> 16) & 0xff,
3026 						(val >> 24) & 0xff);
3027 
3028 			for (b = 0; b < 4; ++b) {
3029 				if (w < len)
3030 					buf[w] = (val >> (b * 8)) & 0xff;
3031 				/* we discard the 2 byte checksum */
3032 				++w;
3033 			}
3034 		}
3035 
3036 		return len;
3037 	} else {
3038 		DSSERR("\tunknown datatype 0x%02x\n", dt);
3039 		r = -EIO;
3040 		goto err;
3041 	}
3042 
3043 err:
3044 	DSSERR("dsi_vc_read_rx_fifo(ch %d type %s) failed\n", channel,
3045 		type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" : "DCS");
3046 
3047 	return r;
3048 }
3049 
3050 static int dsi_vc_dcs_read(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
3051 		u8 *buf, int buflen)
3052 {
3053 	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3054 	int r;
3055 
3056 	r = dsi_vc_dcs_send_read_request(dsidev, channel, dcs_cmd);
3057 	if (r)
3058 		goto err;
3059 
3060 	r = dsi_vc_send_bta_sync(dssdev, channel);
3061 	if (r)
3062 		goto err;
3063 
3064 	r = dsi_vc_read_rx_fifo(dsidev, channel, buf, buflen,
3065 		DSS_DSI_CONTENT_DCS);
3066 	if (r < 0)
3067 		goto err;
3068 
3069 	if (r != buflen) {
3070 		r = -EIO;
3071 		goto err;
3072 	}
3073 
3074 	return 0;
3075 err:
3076 	DSSERR("dsi_vc_dcs_read(ch %d, cmd 0x%02x) failed\n", channel, dcs_cmd);
3077 	return r;
3078 }
3079 
3080 static int dsi_vc_generic_read(struct omap_dss_device *dssdev, int channel,
3081 		u8 *reqdata, int reqlen, u8 *buf, int buflen)
3082 {
3083 	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3084 	int r;
3085 
3086 	r = dsi_vc_generic_send_read_request(dsidev, channel, reqdata, reqlen);
3087 	if (r)
3088 		return r;
3089 
3090 	r = dsi_vc_send_bta_sync(dssdev, channel);
3091 	if (r)
3092 		return r;
3093 
3094 	r = dsi_vc_read_rx_fifo(dsidev, channel, buf, buflen,
3095 		DSS_DSI_CONTENT_GENERIC);
3096 	if (r < 0)
3097 		return r;
3098 
3099 	if (r != buflen) {
3100 		r = -EIO;
3101 		return r;
3102 	}
3103 
3104 	return 0;
3105 }
3106 
3107 static int dsi_vc_set_max_rx_packet_size(struct omap_dss_device *dssdev, int channel,
3108 		u16 len)
3109 {
3110 	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3111 
3112 	return dsi_vc_send_short(dsidev, channel,
3113 			MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE, len, 0);
3114 }
3115 
3116 static int dsi_enter_ulps(struct platform_device *dsidev)
3117 {
3118 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3119 	DECLARE_COMPLETION_ONSTACK(completion);
3120 	int r, i;
3121 	unsigned mask;
3122 
3123 	DSSDBG("Entering ULPS");
3124 
3125 	WARN_ON(!dsi_bus_is_locked(dsidev));
3126 
3127 	WARN_ON(dsi->ulps_enabled);
3128 
3129 	if (dsi->ulps_enabled)
3130 		return 0;
3131 
3132 	/* DDR_CLK_ALWAYS_ON */
3133 	if (REG_GET(dsidev, DSI_CLK_CTRL, 13, 13)) {
3134 		dsi_if_enable(dsidev, 0);
3135 		REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 13, 13);
3136 		dsi_if_enable(dsidev, 1);
3137 	}
3138 
3139 	dsi_sync_vc(dsidev, 0);
3140 	dsi_sync_vc(dsidev, 1);
3141 	dsi_sync_vc(dsidev, 2);
3142 	dsi_sync_vc(dsidev, 3);
3143 
3144 	dsi_force_tx_stop_mode_io(dsidev);
3145 
3146 	dsi_vc_enable(dsidev, 0, false);
3147 	dsi_vc_enable(dsidev, 1, false);
3148 	dsi_vc_enable(dsidev, 2, false);
3149 	dsi_vc_enable(dsidev, 3, false);
3150 
3151 	if (REG_GET(dsidev, DSI_COMPLEXIO_CFG2, 16, 16)) {	/* HS_BUSY */
3152 		DSSERR("HS busy when enabling ULPS\n");
3153 		return -EIO;
3154 	}
3155 
3156 	if (REG_GET(dsidev, DSI_COMPLEXIO_CFG2, 17, 17)) {	/* LP_BUSY */
3157 		DSSERR("LP busy when enabling ULPS\n");
3158 		return -EIO;
3159 	}
3160 
3161 	r = dsi_register_isr_cio(dsidev, dsi_completion_handler, &completion,
3162 			DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
3163 	if (r)
3164 		return r;
3165 
3166 	mask = 0;
3167 
3168 	for (i = 0; i < dsi->num_lanes_supported; ++i) {
3169 		if (dsi->lanes[i].function == DSI_LANE_UNUSED)
3170 			continue;
3171 		mask |= 1 << i;
3172 	}
3173 	/* Assert TxRequestEsc for data lanes and TxUlpsClk for clk lane */
3174 	/* LANEx_ULPS_SIG2 */
3175 	REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG2, mask, 9, 5);
3176 
3177 	/* flush posted write and wait for SCP interface to finish the write */
3178 	dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG2);
3179 
3180 	if (wait_for_completion_timeout(&completion,
3181 				msecs_to_jiffies(1000)) == 0) {
3182 		DSSERR("ULPS enable timeout\n");
3183 		r = -EIO;
3184 		goto err;
3185 	}
3186 
3187 	dsi_unregister_isr_cio(dsidev, dsi_completion_handler, &completion,
3188 			DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
3189 
3190 	/* Reset LANEx_ULPS_SIG2 */
3191 	REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG2, 0, 9, 5);
3192 
3193 	/* flush posted write and wait for SCP interface to finish the write */
3194 	dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG2);
3195 
3196 	dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_ULPS);
3197 
3198 	dsi_if_enable(dsidev, false);
3199 
3200 	dsi->ulps_enabled = true;
3201 
3202 	return 0;
3203 
3204 err:
3205 	dsi_unregister_isr_cio(dsidev, dsi_completion_handler, &completion,
3206 			DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
3207 	return r;
3208 }
3209 
3210 static void dsi_set_lp_rx_timeout(struct platform_device *dsidev,
3211 		unsigned ticks, bool x4, bool x16)
3212 {
3213 	unsigned long fck;
3214 	unsigned long total_ticks;
3215 	u32 r;
3216 
3217 	BUG_ON(ticks > 0x1fff);
3218 
3219 	/* ticks in DSI_FCK */
3220 	fck = dsi_fclk_rate(dsidev);
3221 
3222 	r = dsi_read_reg(dsidev, DSI_TIMING2);
3223 	r = FLD_MOD(r, 1, 15, 15);	/* LP_RX_TO */
3224 	r = FLD_MOD(r, x16 ? 1 : 0, 14, 14);	/* LP_RX_TO_X16 */
3225 	r = FLD_MOD(r, x4 ? 1 : 0, 13, 13);	/* LP_RX_TO_X4 */
3226 	r = FLD_MOD(r, ticks, 12, 0);	/* LP_RX_COUNTER */
3227 	dsi_write_reg(dsidev, DSI_TIMING2, r);
3228 
3229 	total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
3230 
3231 	DSSDBG("LP_RX_TO %lu ticks (%#x%s%s) = %lu ns\n",
3232 			total_ticks,
3233 			ticks, x4 ? " x4" : "", x16 ? " x16" : "",
3234 			(total_ticks * 1000) / (fck / 1000 / 1000));
3235 }
3236 
3237 static void dsi_set_ta_timeout(struct platform_device *dsidev, unsigned ticks,
3238 		bool x8, bool x16)
3239 {
3240 	unsigned long fck;
3241 	unsigned long total_ticks;
3242 	u32 r;
3243 
3244 	BUG_ON(ticks > 0x1fff);
3245 
3246 	/* ticks in DSI_FCK */
3247 	fck = dsi_fclk_rate(dsidev);
3248 
3249 	r = dsi_read_reg(dsidev, DSI_TIMING1);
3250 	r = FLD_MOD(r, 1, 31, 31);	/* TA_TO */
3251 	r = FLD_MOD(r, x16 ? 1 : 0, 30, 30);	/* TA_TO_X16 */
3252 	r = FLD_MOD(r, x8 ? 1 : 0, 29, 29);	/* TA_TO_X8 */
3253 	r = FLD_MOD(r, ticks, 28, 16);	/* TA_TO_COUNTER */
3254 	dsi_write_reg(dsidev, DSI_TIMING1, r);
3255 
3256 	total_ticks = ticks * (x16 ? 16 : 1) * (x8 ? 8 : 1);
3257 
3258 	DSSDBG("TA_TO %lu ticks (%#x%s%s) = %lu ns\n",
3259 			total_ticks,
3260 			ticks, x8 ? " x8" : "", x16 ? " x16" : "",
3261 			(total_ticks * 1000) / (fck / 1000 / 1000));
3262 }
3263 
3264 static void dsi_set_stop_state_counter(struct platform_device *dsidev,
3265 		unsigned ticks, bool x4, bool x16)
3266 {
3267 	unsigned long fck;
3268 	unsigned long total_ticks;
3269 	u32 r;
3270 
3271 	BUG_ON(ticks > 0x1fff);
3272 
3273 	/* ticks in DSI_FCK */
3274 	fck = dsi_fclk_rate(dsidev);
3275 
3276 	r = dsi_read_reg(dsidev, DSI_TIMING1);
3277 	r = FLD_MOD(r, 1, 15, 15);	/* FORCE_TX_STOP_MODE_IO */
3278 	r = FLD_MOD(r, x16 ? 1 : 0, 14, 14);	/* STOP_STATE_X16_IO */
3279 	r = FLD_MOD(r, x4 ? 1 : 0, 13, 13);	/* STOP_STATE_X4_IO */
3280 	r = FLD_MOD(r, ticks, 12, 0);	/* STOP_STATE_COUNTER_IO */
3281 	dsi_write_reg(dsidev, DSI_TIMING1, r);
3282 
3283 	total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
3284 
3285 	DSSDBG("STOP_STATE_COUNTER %lu ticks (%#x%s%s) = %lu ns\n",
3286 			total_ticks,
3287 			ticks, x4 ? " x4" : "", x16 ? " x16" : "",
3288 			(total_ticks * 1000) / (fck / 1000 / 1000));
3289 }
3290 
3291 static void dsi_set_hs_tx_timeout(struct platform_device *dsidev,
3292 		unsigned ticks, bool x4, bool x16)
3293 {
3294 	unsigned long fck;
3295 	unsigned long total_ticks;
3296 	u32 r;
3297 
3298 	BUG_ON(ticks > 0x1fff);
3299 
3300 	/* ticks in TxByteClkHS */
3301 	fck = dsi_get_txbyteclkhs(dsidev);
3302 
3303 	r = dsi_read_reg(dsidev, DSI_TIMING2);
3304 	r = FLD_MOD(r, 1, 31, 31);	/* HS_TX_TO */
3305 	r = FLD_MOD(r, x16 ? 1 : 0, 30, 30);	/* HS_TX_TO_X16 */
3306 	r = FLD_MOD(r, x4 ? 1 : 0, 29, 29);	/* HS_TX_TO_X8 (4 really) */
3307 	r = FLD_MOD(r, ticks, 28, 16);	/* HS_TX_TO_COUNTER */
3308 	dsi_write_reg(dsidev, DSI_TIMING2, r);
3309 
3310 	total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
3311 
3312 	DSSDBG("HS_TX_TO %lu ticks (%#x%s%s) = %lu ns\n",
3313 			total_ticks,
3314 			ticks, x4 ? " x4" : "", x16 ? " x16" : "",
3315 			(total_ticks * 1000) / (fck / 1000 / 1000));
3316 }
3317 
3318 static void dsi_config_vp_num_line_buffers(struct platform_device *dsidev)
3319 {
3320 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3321 	int num_line_buffers;
3322 
3323 	if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
3324 		int bpp = dsi_get_pixel_size(dsi->pix_fmt);
3325 		struct omap_video_timings *timings = &dsi->timings;
3326 		/*
3327 		 * Don't use line buffers if width is greater than the video
3328 		 * port's line buffer size
3329 		 */
3330 		if (dsi->line_buffer_size <= timings->x_res * bpp / 8)
3331 			num_line_buffers = 0;
3332 		else
3333 			num_line_buffers = 2;
3334 	} else {
3335 		/* Use maximum number of line buffers in command mode */
3336 		num_line_buffers = 2;
3337 	}
3338 
3339 	/* LINE_BUFFER */
3340 	REG_FLD_MOD(dsidev, DSI_CTRL, num_line_buffers, 13, 12);
3341 }
3342 
3343 static void dsi_config_vp_sync_events(struct platform_device *dsidev)
3344 {
3345 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3346 	bool sync_end;
3347 	u32 r;
3348 
3349 	if (dsi->vm_timings.trans_mode == OMAP_DSS_DSI_PULSE_MODE)
3350 		sync_end = true;
3351 	else
3352 		sync_end = false;
3353 
3354 	r = dsi_read_reg(dsidev, DSI_CTRL);
3355 	r = FLD_MOD(r, 1, 9, 9);		/* VP_DE_POL */
3356 	r = FLD_MOD(r, 1, 10, 10);		/* VP_HSYNC_POL */
3357 	r = FLD_MOD(r, 1, 11, 11);		/* VP_VSYNC_POL */
3358 	r = FLD_MOD(r, 1, 15, 15);		/* VP_VSYNC_START */
3359 	r = FLD_MOD(r, sync_end, 16, 16);	/* VP_VSYNC_END */
3360 	r = FLD_MOD(r, 1, 17, 17);		/* VP_HSYNC_START */
3361 	r = FLD_MOD(r, sync_end, 18, 18);	/* VP_HSYNC_END */
3362 	dsi_write_reg(dsidev, DSI_CTRL, r);
3363 }
3364 
3365 static void dsi_config_blanking_modes(struct platform_device *dsidev)
3366 {
3367 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3368 	int blanking_mode = dsi->vm_timings.blanking_mode;
3369 	int hfp_blanking_mode = dsi->vm_timings.hfp_blanking_mode;
3370 	int hbp_blanking_mode = dsi->vm_timings.hbp_blanking_mode;
3371 	int hsa_blanking_mode = dsi->vm_timings.hsa_blanking_mode;
3372 	u32 r;
3373 
3374 	/*
3375 	 * 0 = TX FIFO packets sent or LPS in corresponding blanking periods
3376 	 * 1 = Long blanking packets are sent in corresponding blanking periods
3377 	 */
3378 	r = dsi_read_reg(dsidev, DSI_CTRL);
3379 	r = FLD_MOD(r, blanking_mode, 20, 20);		/* BLANKING_MODE */
3380 	r = FLD_MOD(r, hfp_blanking_mode, 21, 21);	/* HFP_BLANKING */
3381 	r = FLD_MOD(r, hbp_blanking_mode, 22, 22);	/* HBP_BLANKING */
3382 	r = FLD_MOD(r, hsa_blanking_mode, 23, 23);	/* HSA_BLANKING */
3383 	dsi_write_reg(dsidev, DSI_CTRL, r);
3384 }
3385 
3386 /*
3387  * According to section 'HS Command Mode Interleaving' in OMAP TRM, Scenario 3
3388  * results in maximum transition time for data and clock lanes to enter and
3389  * exit HS mode. Hence, this is the scenario where the least amount of command
3390  * mode data can be interleaved. We program the minimum amount of TXBYTECLKHS
3391  * clock cycles that can be used to interleave command mode data in HS so that
3392  * all scenarios are satisfied.
3393  */
3394 static int dsi_compute_interleave_hs(int blank, bool ddr_alwon, int enter_hs,
3395 		int exit_hs, int exiths_clk, int ddr_pre, int ddr_post)
3396 {
3397 	int transition;
3398 
3399 	/*
3400 	 * If DDR_CLK_ALWAYS_ON is set, we need to consider HS mode transition
3401 	 * time of data lanes only, if it isn't set, we need to consider HS
3402 	 * transition time of both data and clock lanes. HS transition time
3403 	 * of Scenario 3 is considered.
3404 	 */
3405 	if (ddr_alwon) {
3406 		transition = enter_hs + exit_hs + max(enter_hs, 2) + 1;
3407 	} else {
3408 		int trans1, trans2;
3409 		trans1 = ddr_pre + enter_hs + exit_hs + max(enter_hs, 2) + 1;
3410 		trans2 = ddr_pre + enter_hs + exiths_clk + ddr_post + ddr_pre +
3411 				enter_hs + 1;
3412 		transition = max(trans1, trans2);
3413 	}
3414 
3415 	return blank > transition ? blank - transition : 0;
3416 }
3417 
3418 /*
3419  * According to section 'LP Command Mode Interleaving' in OMAP TRM, Scenario 1
3420  * results in maximum transition time for data lanes to enter and exit LP mode.
3421  * Hence, this is the scenario where the least amount of command mode data can
3422  * be interleaved. We program the minimum amount of bytes that can be
3423  * interleaved in LP so that all scenarios are satisfied.
3424  */
3425 static int dsi_compute_interleave_lp(int blank, int enter_hs, int exit_hs,
3426 		int lp_clk_div, int tdsi_fclk)
3427 {
3428 	int trans_lp;	/* time required for a LP transition, in TXBYTECLKHS */
3429 	int tlp_avail;	/* time left for interleaving commands, in CLKIN4DDR */
3430 	int ttxclkesc;	/* period of LP transmit escape clock, in CLKIN4DDR */
3431 	int thsbyte_clk = 16;	/* Period of TXBYTECLKHS clock, in CLKIN4DDR */
3432 	int lp_inter;	/* cmd mode data that can be interleaved, in bytes */
3433 
3434 	/* maximum LP transition time according to Scenario 1 */
3435 	trans_lp = exit_hs + max(enter_hs, 2) + 1;
3436 
3437 	/* CLKIN4DDR = 16 * TXBYTECLKHS */
3438 	tlp_avail = thsbyte_clk * (blank - trans_lp);
3439 
3440 	ttxclkesc = tdsi_fclk * lp_clk_div;
3441 
3442 	lp_inter = ((tlp_avail - 8 * thsbyte_clk - 5 * tdsi_fclk) / ttxclkesc -
3443 			26) / 16;
3444 
3445 	return max(lp_inter, 0);
3446 }
3447 
3448 static void dsi_config_cmd_mode_interleaving(struct platform_device *dsidev)
3449 {
3450 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3451 	int blanking_mode;
3452 	int hfp_blanking_mode, hbp_blanking_mode, hsa_blanking_mode;
3453 	int hsa, hfp, hbp, width_bytes, bllp, lp_clk_div;
3454 	int ddr_clk_pre, ddr_clk_post, enter_hs_mode_lat, exit_hs_mode_lat;
3455 	int tclk_trail, ths_exit, exiths_clk;
3456 	bool ddr_alwon;
3457 	struct omap_video_timings *timings = &dsi->timings;
3458 	int bpp = dsi_get_pixel_size(dsi->pix_fmt);
3459 	int ndl = dsi->num_lanes_used - 1;
3460 	int dsi_fclk_hsdiv = dsi->user_dsi_cinfo.mX[HSDIV_DSI] + 1;
3461 	int hsa_interleave_hs = 0, hsa_interleave_lp = 0;
3462 	int hfp_interleave_hs = 0, hfp_interleave_lp = 0;
3463 	int hbp_interleave_hs = 0, hbp_interleave_lp = 0;
3464 	int bl_interleave_hs = 0, bl_interleave_lp = 0;
3465 	u32 r;
3466 
3467 	r = dsi_read_reg(dsidev, DSI_CTRL);
3468 	blanking_mode = FLD_GET(r, 20, 20);
3469 	hfp_blanking_mode = FLD_GET(r, 21, 21);
3470 	hbp_blanking_mode = FLD_GET(r, 22, 22);
3471 	hsa_blanking_mode = FLD_GET(r, 23, 23);
3472 
3473 	r = dsi_read_reg(dsidev, DSI_VM_TIMING1);
3474 	hbp = FLD_GET(r, 11, 0);
3475 	hfp = FLD_GET(r, 23, 12);
3476 	hsa = FLD_GET(r, 31, 24);
3477 
3478 	r = dsi_read_reg(dsidev, DSI_CLK_TIMING);
3479 	ddr_clk_post = FLD_GET(r, 7, 0);
3480 	ddr_clk_pre = FLD_GET(r, 15, 8);
3481 
3482 	r = dsi_read_reg(dsidev, DSI_VM_TIMING7);
3483 	exit_hs_mode_lat = FLD_GET(r, 15, 0);
3484 	enter_hs_mode_lat = FLD_GET(r, 31, 16);
3485 
3486 	r = dsi_read_reg(dsidev, DSI_CLK_CTRL);
3487 	lp_clk_div = FLD_GET(r, 12, 0);
3488 	ddr_alwon = FLD_GET(r, 13, 13);
3489 
3490 	r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0);
3491 	ths_exit = FLD_GET(r, 7, 0);
3492 
3493 	r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1);
3494 	tclk_trail = FLD_GET(r, 15, 8);
3495 
3496 	exiths_clk = ths_exit + tclk_trail;
3497 
3498 	width_bytes = DIV_ROUND_UP(timings->x_res * bpp, 8);
3499 	bllp = hbp + hfp + hsa + DIV_ROUND_UP(width_bytes + 6, ndl);
3500 
3501 	if (!hsa_blanking_mode) {
3502 		hsa_interleave_hs = dsi_compute_interleave_hs(hsa, ddr_alwon,
3503 					enter_hs_mode_lat, exit_hs_mode_lat,
3504 					exiths_clk, ddr_clk_pre, ddr_clk_post);
3505 		hsa_interleave_lp = dsi_compute_interleave_lp(hsa,
3506 					enter_hs_mode_lat, exit_hs_mode_lat,
3507 					lp_clk_div, dsi_fclk_hsdiv);
3508 	}
3509 
3510 	if (!hfp_blanking_mode) {
3511 		hfp_interleave_hs = dsi_compute_interleave_hs(hfp, ddr_alwon,
3512 					enter_hs_mode_lat, exit_hs_mode_lat,
3513 					exiths_clk, ddr_clk_pre, ddr_clk_post);
3514 		hfp_interleave_lp = dsi_compute_interleave_lp(hfp,
3515 					enter_hs_mode_lat, exit_hs_mode_lat,
3516 					lp_clk_div, dsi_fclk_hsdiv);
3517 	}
3518 
3519 	if (!hbp_blanking_mode) {
3520 		hbp_interleave_hs = dsi_compute_interleave_hs(hbp, ddr_alwon,
3521 					enter_hs_mode_lat, exit_hs_mode_lat,
3522 					exiths_clk, ddr_clk_pre, ddr_clk_post);
3523 
3524 		hbp_interleave_lp = dsi_compute_interleave_lp(hbp,
3525 					enter_hs_mode_lat, exit_hs_mode_lat,
3526 					lp_clk_div, dsi_fclk_hsdiv);
3527 	}
3528 
3529 	if (!blanking_mode) {
3530 		bl_interleave_hs = dsi_compute_interleave_hs(bllp, ddr_alwon,
3531 					enter_hs_mode_lat, exit_hs_mode_lat,
3532 					exiths_clk, ddr_clk_pre, ddr_clk_post);
3533 
3534 		bl_interleave_lp = dsi_compute_interleave_lp(bllp,
3535 					enter_hs_mode_lat, exit_hs_mode_lat,
3536 					lp_clk_div, dsi_fclk_hsdiv);
3537 	}
3538 
3539 	DSSDBG("DSI HS interleaving(TXBYTECLKHS) HSA %d, HFP %d, HBP %d, BLLP %d\n",
3540 		hsa_interleave_hs, hfp_interleave_hs, hbp_interleave_hs,
3541 		bl_interleave_hs);
3542 
3543 	DSSDBG("DSI LP interleaving(bytes) HSA %d, HFP %d, HBP %d, BLLP %d\n",
3544 		hsa_interleave_lp, hfp_interleave_lp, hbp_interleave_lp,
3545 		bl_interleave_lp);
3546 
3547 	r = dsi_read_reg(dsidev, DSI_VM_TIMING4);
3548 	r = FLD_MOD(r, hsa_interleave_hs, 23, 16);
3549 	r = FLD_MOD(r, hfp_interleave_hs, 15, 8);
3550 	r = FLD_MOD(r, hbp_interleave_hs, 7, 0);
3551 	dsi_write_reg(dsidev, DSI_VM_TIMING4, r);
3552 
3553 	r = dsi_read_reg(dsidev, DSI_VM_TIMING5);
3554 	r = FLD_MOD(r, hsa_interleave_lp, 23, 16);
3555 	r = FLD_MOD(r, hfp_interleave_lp, 15, 8);
3556 	r = FLD_MOD(r, hbp_interleave_lp, 7, 0);
3557 	dsi_write_reg(dsidev, DSI_VM_TIMING5, r);
3558 
3559 	r = dsi_read_reg(dsidev, DSI_VM_TIMING6);
3560 	r = FLD_MOD(r, bl_interleave_hs, 31, 15);
3561 	r = FLD_MOD(r, bl_interleave_lp, 16, 0);
3562 	dsi_write_reg(dsidev, DSI_VM_TIMING6, r);
3563 }
3564 
3565 static int dsi_proto_config(struct platform_device *dsidev)
3566 {
3567 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3568 	u32 r;
3569 	int buswidth = 0;
3570 
3571 	dsi_config_tx_fifo(dsidev, DSI_FIFO_SIZE_32,
3572 			DSI_FIFO_SIZE_32,
3573 			DSI_FIFO_SIZE_32,
3574 			DSI_FIFO_SIZE_32);
3575 
3576 	dsi_config_rx_fifo(dsidev, DSI_FIFO_SIZE_32,
3577 			DSI_FIFO_SIZE_32,
3578 			DSI_FIFO_SIZE_32,
3579 			DSI_FIFO_SIZE_32);
3580 
3581 	/* XXX what values for the timeouts? */
3582 	dsi_set_stop_state_counter(dsidev, 0x1000, false, false);
3583 	dsi_set_ta_timeout(dsidev, 0x1fff, true, true);
3584 	dsi_set_lp_rx_timeout(dsidev, 0x1fff, true, true);
3585 	dsi_set_hs_tx_timeout(dsidev, 0x1fff, true, true);
3586 
3587 	switch (dsi_get_pixel_size(dsi->pix_fmt)) {
3588 	case 16:
3589 		buswidth = 0;
3590 		break;
3591 	case 18:
3592 		buswidth = 1;
3593 		break;
3594 	case 24:
3595 		buswidth = 2;
3596 		break;
3597 	default:
3598 		BUG();
3599 		return -EINVAL;
3600 	}
3601 
3602 	r = dsi_read_reg(dsidev, DSI_CTRL);
3603 	r = FLD_MOD(r, 1, 1, 1);	/* CS_RX_EN */
3604 	r = FLD_MOD(r, 1, 2, 2);	/* ECC_RX_EN */
3605 	r = FLD_MOD(r, 1, 3, 3);	/* TX_FIFO_ARBITRATION */
3606 	r = FLD_MOD(r, 1, 4, 4);	/* VP_CLK_RATIO, always 1, see errata*/
3607 	r = FLD_MOD(r, buswidth, 7, 6); /* VP_DATA_BUS_WIDTH */
3608 	r = FLD_MOD(r, 0, 8, 8);	/* VP_CLK_POL */
3609 	r = FLD_MOD(r, 1, 14, 14);	/* TRIGGER_RESET_MODE */
3610 	r = FLD_MOD(r, 1, 19, 19);	/* EOT_ENABLE */
3611 	if (!dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC)) {
3612 		r = FLD_MOD(r, 1, 24, 24);	/* DCS_CMD_ENABLE */
3613 		/* DCS_CMD_CODE, 1=start, 0=continue */
3614 		r = FLD_MOD(r, 0, 25, 25);
3615 	}
3616 
3617 	dsi_write_reg(dsidev, DSI_CTRL, r);
3618 
3619 	dsi_config_vp_num_line_buffers(dsidev);
3620 
3621 	if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
3622 		dsi_config_vp_sync_events(dsidev);
3623 		dsi_config_blanking_modes(dsidev);
3624 		dsi_config_cmd_mode_interleaving(dsidev);
3625 	}
3626 
3627 	dsi_vc_initial_config(dsidev, 0);
3628 	dsi_vc_initial_config(dsidev, 1);
3629 	dsi_vc_initial_config(dsidev, 2);
3630 	dsi_vc_initial_config(dsidev, 3);
3631 
3632 	return 0;
3633 }
3634 
3635 static void dsi_proto_timings(struct platform_device *dsidev)
3636 {
3637 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3638 	unsigned tlpx, tclk_zero, tclk_prepare, tclk_trail;
3639 	unsigned tclk_pre, tclk_post;
3640 	unsigned ths_prepare, ths_prepare_ths_zero, ths_zero;
3641 	unsigned ths_trail, ths_exit;
3642 	unsigned ddr_clk_pre, ddr_clk_post;
3643 	unsigned enter_hs_mode_lat, exit_hs_mode_lat;
3644 	unsigned ths_eot;
3645 	int ndl = dsi->num_lanes_used - 1;
3646 	u32 r;
3647 
3648 	r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0);
3649 	ths_prepare = FLD_GET(r, 31, 24);
3650 	ths_prepare_ths_zero = FLD_GET(r, 23, 16);
3651 	ths_zero = ths_prepare_ths_zero - ths_prepare;
3652 	ths_trail = FLD_GET(r, 15, 8);
3653 	ths_exit = FLD_GET(r, 7, 0);
3654 
3655 	r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1);
3656 	tlpx = FLD_GET(r, 20, 16) * 2;
3657 	tclk_trail = FLD_GET(r, 15, 8);
3658 	tclk_zero = FLD_GET(r, 7, 0);
3659 
3660 	r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG2);
3661 	tclk_prepare = FLD_GET(r, 7, 0);
3662 
3663 	/* min 8*UI */
3664 	tclk_pre = 20;
3665 	/* min 60ns + 52*UI */
3666 	tclk_post = ns2ddr(dsidev, 60) + 26;
3667 
3668 	ths_eot = DIV_ROUND_UP(4, ndl);
3669 
3670 	ddr_clk_pre = DIV_ROUND_UP(tclk_pre + tlpx + tclk_zero + tclk_prepare,
3671 			4);
3672 	ddr_clk_post = DIV_ROUND_UP(tclk_post + ths_trail, 4) + ths_eot;
3673 
3674 	BUG_ON(ddr_clk_pre == 0 || ddr_clk_pre > 255);
3675 	BUG_ON(ddr_clk_post == 0 || ddr_clk_post > 255);
3676 
3677 	r = dsi_read_reg(dsidev, DSI_CLK_TIMING);
3678 	r = FLD_MOD(r, ddr_clk_pre, 15, 8);
3679 	r = FLD_MOD(r, ddr_clk_post, 7, 0);
3680 	dsi_write_reg(dsidev, DSI_CLK_TIMING, r);
3681 
3682 	DSSDBG("ddr_clk_pre %u, ddr_clk_post %u\n",
3683 			ddr_clk_pre,
3684 			ddr_clk_post);
3685 
3686 	enter_hs_mode_lat = 1 + DIV_ROUND_UP(tlpx, 4) +
3687 		DIV_ROUND_UP(ths_prepare, 4) +
3688 		DIV_ROUND_UP(ths_zero + 3, 4);
3689 
3690 	exit_hs_mode_lat = DIV_ROUND_UP(ths_trail + ths_exit, 4) + 1 + ths_eot;
3691 
3692 	r = FLD_VAL(enter_hs_mode_lat, 31, 16) |
3693 		FLD_VAL(exit_hs_mode_lat, 15, 0);
3694 	dsi_write_reg(dsidev, DSI_VM_TIMING7, r);
3695 
3696 	DSSDBG("enter_hs_mode_lat %u, exit_hs_mode_lat %u\n",
3697 			enter_hs_mode_lat, exit_hs_mode_lat);
3698 
3699 	 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
3700 		/* TODO: Implement a video mode check_timings function */
3701 		int hsa = dsi->vm_timings.hsa;
3702 		int hfp = dsi->vm_timings.hfp;
3703 		int hbp = dsi->vm_timings.hbp;
3704 		int vsa = dsi->vm_timings.vsa;
3705 		int vfp = dsi->vm_timings.vfp;
3706 		int vbp = dsi->vm_timings.vbp;
3707 		int window_sync = dsi->vm_timings.window_sync;
3708 		bool hsync_end;
3709 		struct omap_video_timings *timings = &dsi->timings;
3710 		int bpp = dsi_get_pixel_size(dsi->pix_fmt);
3711 		int tl, t_he, width_bytes;
3712 
3713 		hsync_end = dsi->vm_timings.trans_mode == OMAP_DSS_DSI_PULSE_MODE;
3714 		t_he = hsync_end ?
3715 			((hsa == 0 && ndl == 3) ? 1 : DIV_ROUND_UP(4, ndl)) : 0;
3716 
3717 		width_bytes = DIV_ROUND_UP(timings->x_res * bpp, 8);
3718 
3719 		/* TL = t_HS + HSA + t_HE + HFP + ceil((WC + 6) / NDL) + HBP */
3720 		tl = DIV_ROUND_UP(4, ndl) + (hsync_end ? hsa : 0) + t_he + hfp +
3721 			DIV_ROUND_UP(width_bytes + 6, ndl) + hbp;
3722 
3723 		DSSDBG("HBP: %d, HFP: %d, HSA: %d, TL: %d TXBYTECLKHS\n", hbp,
3724 			hfp, hsync_end ? hsa : 0, tl);
3725 		DSSDBG("VBP: %d, VFP: %d, VSA: %d, VACT: %d lines\n", vbp, vfp,
3726 			vsa, timings->y_res);
3727 
3728 		r = dsi_read_reg(dsidev, DSI_VM_TIMING1);
3729 		r = FLD_MOD(r, hbp, 11, 0);	/* HBP */
3730 		r = FLD_MOD(r, hfp, 23, 12);	/* HFP */
3731 		r = FLD_MOD(r, hsync_end ? hsa : 0, 31, 24);	/* HSA */
3732 		dsi_write_reg(dsidev, DSI_VM_TIMING1, r);
3733 
3734 		r = dsi_read_reg(dsidev, DSI_VM_TIMING2);
3735 		r = FLD_MOD(r, vbp, 7, 0);	/* VBP */
3736 		r = FLD_MOD(r, vfp, 15, 8);	/* VFP */
3737 		r = FLD_MOD(r, vsa, 23, 16);	/* VSA */
3738 		r = FLD_MOD(r, window_sync, 27, 24);	/* WINDOW_SYNC */
3739 		dsi_write_reg(dsidev, DSI_VM_TIMING2, r);
3740 
3741 		r = dsi_read_reg(dsidev, DSI_VM_TIMING3);
3742 		r = FLD_MOD(r, timings->y_res, 14, 0);	/* VACT */
3743 		r = FLD_MOD(r, tl, 31, 16);		/* TL */
3744 		dsi_write_reg(dsidev, DSI_VM_TIMING3, r);
3745 	}
3746 }
3747 
3748 static int dsi_configure_pins(struct omap_dss_device *dssdev,
3749 		const struct omap_dsi_pin_config *pin_cfg)
3750 {
3751 	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3752 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3753 	int num_pins;
3754 	const int *pins;
3755 	struct dsi_lane_config lanes[DSI_MAX_NR_LANES];
3756 	int num_lanes;
3757 	int i;
3758 
3759 	static const enum dsi_lane_function functions[] = {
3760 		DSI_LANE_CLK,
3761 		DSI_LANE_DATA1,
3762 		DSI_LANE_DATA2,
3763 		DSI_LANE_DATA3,
3764 		DSI_LANE_DATA4,
3765 	};
3766 
3767 	num_pins = pin_cfg->num_pins;
3768 	pins = pin_cfg->pins;
3769 
3770 	if (num_pins < 4 || num_pins > dsi->num_lanes_supported * 2
3771 			|| num_pins % 2 != 0)
3772 		return -EINVAL;
3773 
3774 	for (i = 0; i < DSI_MAX_NR_LANES; ++i)
3775 		lanes[i].function = DSI_LANE_UNUSED;
3776 
3777 	num_lanes = 0;
3778 
3779 	for (i = 0; i < num_pins; i += 2) {
3780 		u8 lane, pol;
3781 		int dx, dy;
3782 
3783 		dx = pins[i];
3784 		dy = pins[i + 1];
3785 
3786 		if (dx < 0 || dx >= dsi->num_lanes_supported * 2)
3787 			return -EINVAL;
3788 
3789 		if (dy < 0 || dy >= dsi->num_lanes_supported * 2)
3790 			return -EINVAL;
3791 
3792 		if (dx & 1) {
3793 			if (dy != dx - 1)
3794 				return -EINVAL;
3795 			pol = 1;
3796 		} else {
3797 			if (dy != dx + 1)
3798 				return -EINVAL;
3799 			pol = 0;
3800 		}
3801 
3802 		lane = dx / 2;
3803 
3804 		lanes[lane].function = functions[i / 2];
3805 		lanes[lane].polarity = pol;
3806 		num_lanes++;
3807 	}
3808 
3809 	memcpy(dsi->lanes, lanes, sizeof(dsi->lanes));
3810 	dsi->num_lanes_used = num_lanes;
3811 
3812 	return 0;
3813 }
3814 
3815 static int dsi_enable_video_output(struct omap_dss_device *dssdev, int channel)
3816 {
3817 	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3818 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3819 	struct omap_overlay_manager *mgr = dsi->output.manager;
3820 	int bpp = dsi_get_pixel_size(dsi->pix_fmt);
3821 	struct omap_dss_device *out = &dsi->output;
3822 	u8 data_type;
3823 	u16 word_count;
3824 	int r;
3825 
3826 	if (out->manager == NULL) {
3827 		DSSERR("failed to enable display: no output/manager\n");
3828 		return -ENODEV;
3829 	}
3830 
3831 	r = dsi_display_init_dispc(dsidev, mgr);
3832 	if (r)
3833 		goto err_init_dispc;
3834 
3835 	if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
3836 		switch (dsi->pix_fmt) {
3837 		case OMAP_DSS_DSI_FMT_RGB888:
3838 			data_type = MIPI_DSI_PACKED_PIXEL_STREAM_24;
3839 			break;
3840 		case OMAP_DSS_DSI_FMT_RGB666:
3841 			data_type = MIPI_DSI_PIXEL_STREAM_3BYTE_18;
3842 			break;
3843 		case OMAP_DSS_DSI_FMT_RGB666_PACKED:
3844 			data_type = MIPI_DSI_PACKED_PIXEL_STREAM_18;
3845 			break;
3846 		case OMAP_DSS_DSI_FMT_RGB565:
3847 			data_type = MIPI_DSI_PACKED_PIXEL_STREAM_16;
3848 			break;
3849 		default:
3850 			r = -EINVAL;
3851 			goto err_pix_fmt;
3852 		}
3853 
3854 		dsi_if_enable(dsidev, false);
3855 		dsi_vc_enable(dsidev, channel, false);
3856 
3857 		/* MODE, 1 = video mode */
3858 		REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 1, 4, 4);
3859 
3860 		word_count = DIV_ROUND_UP(dsi->timings.x_res * bpp, 8);
3861 
3862 		dsi_vc_write_long_header(dsidev, channel, data_type,
3863 				word_count, 0);
3864 
3865 		dsi_vc_enable(dsidev, channel, true);
3866 		dsi_if_enable(dsidev, true);
3867 	}
3868 
3869 	r = dss_mgr_enable(mgr);
3870 	if (r)
3871 		goto err_mgr_enable;
3872 
3873 	return 0;
3874 
3875 err_mgr_enable:
3876 	if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
3877 		dsi_if_enable(dsidev, false);
3878 		dsi_vc_enable(dsidev, channel, false);
3879 	}
3880 err_pix_fmt:
3881 	dsi_display_uninit_dispc(dsidev, mgr);
3882 err_init_dispc:
3883 	return r;
3884 }
3885 
3886 static void dsi_disable_video_output(struct omap_dss_device *dssdev, int channel)
3887 {
3888 	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3889 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3890 	struct omap_overlay_manager *mgr = dsi->output.manager;
3891 
3892 	if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
3893 		dsi_if_enable(dsidev, false);
3894 		dsi_vc_enable(dsidev, channel, false);
3895 
3896 		/* MODE, 0 = command mode */
3897 		REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 0, 4, 4);
3898 
3899 		dsi_vc_enable(dsidev, channel, true);
3900 		dsi_if_enable(dsidev, true);
3901 	}
3902 
3903 	dss_mgr_disable(mgr);
3904 
3905 	dsi_display_uninit_dispc(dsidev, mgr);
3906 }
3907 
3908 static void dsi_update_screen_dispc(struct platform_device *dsidev)
3909 {
3910 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3911 	struct omap_overlay_manager *mgr = dsi->output.manager;
3912 	unsigned bytespp;
3913 	unsigned bytespl;
3914 	unsigned bytespf;
3915 	unsigned total_len;
3916 	unsigned packet_payload;
3917 	unsigned packet_len;
3918 	u32 l;
3919 	int r;
3920 	const unsigned channel = dsi->update_channel;
3921 	const unsigned line_buf_size = dsi->line_buffer_size;
3922 	u16 w = dsi->timings.x_res;
3923 	u16 h = dsi->timings.y_res;
3924 
3925 	DSSDBG("dsi_update_screen_dispc(%dx%d)\n", w, h);
3926 
3927 	dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_VP);
3928 
3929 	bytespp	= dsi_get_pixel_size(dsi->pix_fmt) / 8;
3930 	bytespl = w * bytespp;
3931 	bytespf = bytespl * h;
3932 
3933 	/* NOTE: packet_payload has to be equal to N * bytespl, where N is
3934 	 * number of lines in a packet.  See errata about VP_CLK_RATIO */
3935 
3936 	if (bytespf < line_buf_size)
3937 		packet_payload = bytespf;
3938 	else
3939 		packet_payload = (line_buf_size) / bytespl * bytespl;
3940 
3941 	packet_len = packet_payload + 1;	/* 1 byte for DCS cmd */
3942 	total_len = (bytespf / packet_payload) * packet_len;
3943 
3944 	if (bytespf % packet_payload)
3945 		total_len += (bytespf % packet_payload) + 1;
3946 
3947 	l = FLD_VAL(total_len, 23, 0); /* TE_SIZE */
3948 	dsi_write_reg(dsidev, DSI_VC_TE(channel), l);
3949 
3950 	dsi_vc_write_long_header(dsidev, channel, MIPI_DSI_DCS_LONG_WRITE,
3951 		packet_len, 0);
3952 
3953 	if (dsi->te_enabled)
3954 		l = FLD_MOD(l, 1, 30, 30); /* TE_EN */
3955 	else
3956 		l = FLD_MOD(l, 1, 31, 31); /* TE_START */
3957 	dsi_write_reg(dsidev, DSI_VC_TE(channel), l);
3958 
3959 	/* We put SIDLEMODE to no-idle for the duration of the transfer,
3960 	 * because DSS interrupts are not capable of waking up the CPU and the
3961 	 * framedone interrupt could be delayed for quite a long time. I think
3962 	 * the same goes for any DSS interrupts, but for some reason I have not
3963 	 * seen the problem anywhere else than here.
3964 	 */
3965 	dispc_disable_sidle();
3966 
3967 	dsi_perf_mark_start(dsidev);
3968 
3969 	r = schedule_delayed_work(&dsi->framedone_timeout_work,
3970 		msecs_to_jiffies(250));
3971 	BUG_ON(r == 0);
3972 
3973 	dss_mgr_set_timings(mgr, &dsi->timings);
3974 
3975 	dss_mgr_start_update(mgr);
3976 
3977 	if (dsi->te_enabled) {
3978 		/* disable LP_RX_TO, so that we can receive TE.  Time to wait
3979 		 * for TE is longer than the timer allows */
3980 		REG_FLD_MOD(dsidev, DSI_TIMING2, 0, 15, 15); /* LP_RX_TO */
3981 
3982 		dsi_vc_send_bta(dsidev, channel);
3983 
3984 #ifdef DSI_CATCH_MISSING_TE
3985 		mod_timer(&dsi->te_timer, jiffies + msecs_to_jiffies(250));
3986 #endif
3987 	}
3988 }
3989 
3990 #ifdef DSI_CATCH_MISSING_TE
3991 static void dsi_te_timeout(struct timer_list *unused)
3992 {
3993 	DSSERR("TE not received for 250ms!\n");
3994 }
3995 #endif
3996 
3997 static void dsi_handle_framedone(struct platform_device *dsidev, int error)
3998 {
3999 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4000 
4001 	/* SIDLEMODE back to smart-idle */
4002 	dispc_enable_sidle();
4003 
4004 	if (dsi->te_enabled) {
4005 		/* enable LP_RX_TO again after the TE */
4006 		REG_FLD_MOD(dsidev, DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */
4007 	}
4008 
4009 	dsi->framedone_callback(error, dsi->framedone_data);
4010 
4011 	if (!error)
4012 		dsi_perf_show(dsidev, "DISPC");
4013 }
4014 
4015 static void dsi_framedone_timeout_work_callback(struct work_struct *work)
4016 {
4017 	struct dsi_data *dsi = container_of(work, struct dsi_data,
4018 			framedone_timeout_work.work);
4019 	/* XXX While extremely unlikely, we could get FRAMEDONE interrupt after
4020 	 * 250ms which would conflict with this timeout work. What should be
4021 	 * done is first cancel the transfer on the HW, and then cancel the
4022 	 * possibly scheduled framedone work. However, cancelling the transfer
4023 	 * on the HW is buggy, and would probably require resetting the whole
4024 	 * DSI */
4025 
4026 	DSSERR("Framedone not received for 250ms!\n");
4027 
4028 	dsi_handle_framedone(dsi->pdev, -ETIMEDOUT);
4029 }
4030 
4031 static void dsi_framedone_irq_callback(void *data)
4032 {
4033 	struct platform_device *dsidev = (struct platform_device *) data;
4034 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4035 
4036 	/* Note: We get FRAMEDONE when DISPC has finished sending pixels and
4037 	 * turns itself off. However, DSI still has the pixels in its buffers,
4038 	 * and is sending the data.
4039 	 */
4040 
4041 	cancel_delayed_work(&dsi->framedone_timeout_work);
4042 
4043 	dsi_handle_framedone(dsidev, 0);
4044 }
4045 
4046 static int dsi_update(struct omap_dss_device *dssdev, int channel,
4047 		void (*callback)(int, void *), void *data)
4048 {
4049 	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4050 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4051 	u16 dw, dh;
4052 
4053 	dsi_perf_mark_setup(dsidev);
4054 
4055 	dsi->update_channel = channel;
4056 
4057 	dsi->framedone_callback = callback;
4058 	dsi->framedone_data = data;
4059 
4060 	dw = dsi->timings.x_res;
4061 	dh = dsi->timings.y_res;
4062 
4063 #ifdef DSI_PERF_MEASURE
4064 	dsi->update_bytes = dw * dh *
4065 		dsi_get_pixel_size(dsi->pix_fmt) / 8;
4066 #endif
4067 	dsi_update_screen_dispc(dsidev);
4068 
4069 	return 0;
4070 }
4071 
4072 /* Display funcs */
4073 
4074 static int dsi_configure_dispc_clocks(struct platform_device *dsidev)
4075 {
4076 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4077 	struct dispc_clock_info dispc_cinfo;
4078 	int r;
4079 	unsigned long fck;
4080 
4081 	fck = dsi_get_pll_hsdiv_dispc_rate(dsidev);
4082 
4083 	dispc_cinfo.lck_div = dsi->user_dispc_cinfo.lck_div;
4084 	dispc_cinfo.pck_div = dsi->user_dispc_cinfo.pck_div;
4085 
4086 	r = dispc_calc_clock_rates(fck, &dispc_cinfo);
4087 	if (r) {
4088 		DSSERR("Failed to calc dispc clocks\n");
4089 		return r;
4090 	}
4091 
4092 	dsi->mgr_config.clock_info = dispc_cinfo;
4093 
4094 	return 0;
4095 }
4096 
4097 static int dsi_display_init_dispc(struct platform_device *dsidev,
4098 		struct omap_overlay_manager *mgr)
4099 {
4100 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4101 	int r;
4102 
4103 	dss_select_lcd_clk_source(mgr->id, dsi->module_id == 0 ?
4104 			OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC :
4105 			OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC);
4106 
4107 	if (dsi->mode == OMAP_DSS_DSI_CMD_MODE) {
4108 		r = dss_mgr_register_framedone_handler(mgr,
4109 				dsi_framedone_irq_callback, dsidev);
4110 		if (r) {
4111 			DSSERR("can't register FRAMEDONE handler\n");
4112 			goto err;
4113 		}
4114 
4115 		dsi->mgr_config.stallmode = true;
4116 		dsi->mgr_config.fifohandcheck = true;
4117 	} else {
4118 		dsi->mgr_config.stallmode = false;
4119 		dsi->mgr_config.fifohandcheck = false;
4120 	}
4121 
4122 	/*
4123 	 * override interlace, logic level and edge related parameters in
4124 	 * omap_video_timings with default values
4125 	 */
4126 	dsi->timings.interlace = false;
4127 	dsi->timings.hsync_level = OMAPDSS_SIG_ACTIVE_HIGH;
4128 	dsi->timings.vsync_level = OMAPDSS_SIG_ACTIVE_HIGH;
4129 	dsi->timings.data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE;
4130 	dsi->timings.de_level = OMAPDSS_SIG_ACTIVE_HIGH;
4131 	dsi->timings.sync_pclk_edge = OMAPDSS_DRIVE_SIG_FALLING_EDGE;
4132 
4133 	dss_mgr_set_timings(mgr, &dsi->timings);
4134 
4135 	r = dsi_configure_dispc_clocks(dsidev);
4136 	if (r)
4137 		goto err1;
4138 
4139 	dsi->mgr_config.io_pad_mode = DSS_IO_PAD_MODE_BYPASS;
4140 	dsi->mgr_config.video_port_width =
4141 			dsi_get_pixel_size(dsi->pix_fmt);
4142 	dsi->mgr_config.lcden_sig_polarity = 0;
4143 
4144 	dss_mgr_set_lcd_config(mgr, &dsi->mgr_config);
4145 
4146 	return 0;
4147 err1:
4148 	if (dsi->mode == OMAP_DSS_DSI_CMD_MODE)
4149 		dss_mgr_unregister_framedone_handler(mgr,
4150 				dsi_framedone_irq_callback, dsidev);
4151 err:
4152 	dss_select_lcd_clk_source(mgr->id, OMAP_DSS_CLK_SRC_FCK);
4153 	return r;
4154 }
4155 
4156 static void dsi_display_uninit_dispc(struct platform_device *dsidev,
4157 		struct omap_overlay_manager *mgr)
4158 {
4159 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4160 
4161 	if (dsi->mode == OMAP_DSS_DSI_CMD_MODE)
4162 		dss_mgr_unregister_framedone_handler(mgr,
4163 				dsi_framedone_irq_callback, dsidev);
4164 
4165 	dss_select_lcd_clk_source(mgr->id, OMAP_DSS_CLK_SRC_FCK);
4166 }
4167 
4168 static int dsi_configure_dsi_clocks(struct platform_device *dsidev)
4169 {
4170 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4171 	struct dss_pll_clock_info cinfo;
4172 	int r;
4173 
4174 	cinfo = dsi->user_dsi_cinfo;
4175 
4176 	r = dss_pll_set_config(&dsi->pll, &cinfo);
4177 	if (r) {
4178 		DSSERR("Failed to set dsi clocks\n");
4179 		return r;
4180 	}
4181 
4182 	return 0;
4183 }
4184 
4185 static int dsi_display_init_dsi(struct platform_device *dsidev)
4186 {
4187 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4188 	int r;
4189 
4190 	r = dss_pll_enable(&dsi->pll);
4191 	if (r)
4192 		goto err0;
4193 
4194 	r = dsi_configure_dsi_clocks(dsidev);
4195 	if (r)
4196 		goto err1;
4197 
4198 	dss_select_dsi_clk_source(dsi->module_id, dsi->module_id == 0 ?
4199 			OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI :
4200 			OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI);
4201 
4202 	DSSDBG("PLL OK\n");
4203 
4204 	r = dsi_cio_init(dsidev);
4205 	if (r)
4206 		goto err2;
4207 
4208 	_dsi_print_reset_status(dsidev);
4209 
4210 	dsi_proto_timings(dsidev);
4211 	dsi_set_lp_clk_divisor(dsidev);
4212 
4213 	if (1)
4214 		_dsi_print_reset_status(dsidev);
4215 
4216 	r = dsi_proto_config(dsidev);
4217 	if (r)
4218 		goto err3;
4219 
4220 	/* enable interface */
4221 	dsi_vc_enable(dsidev, 0, 1);
4222 	dsi_vc_enable(dsidev, 1, 1);
4223 	dsi_vc_enable(dsidev, 2, 1);
4224 	dsi_vc_enable(dsidev, 3, 1);
4225 	dsi_if_enable(dsidev, 1);
4226 	dsi_force_tx_stop_mode_io(dsidev);
4227 
4228 	return 0;
4229 err3:
4230 	dsi_cio_uninit(dsidev);
4231 err2:
4232 	dss_select_dsi_clk_source(dsi->module_id, OMAP_DSS_CLK_SRC_FCK);
4233 err1:
4234 	dss_pll_disable(&dsi->pll);
4235 err0:
4236 	return r;
4237 }
4238 
4239 static void dsi_display_uninit_dsi(struct platform_device *dsidev,
4240 		bool disconnect_lanes, bool enter_ulps)
4241 {
4242 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4243 
4244 	if (enter_ulps && !dsi->ulps_enabled)
4245 		dsi_enter_ulps(dsidev);
4246 
4247 	/* disable interface */
4248 	dsi_if_enable(dsidev, 0);
4249 	dsi_vc_enable(dsidev, 0, 0);
4250 	dsi_vc_enable(dsidev, 1, 0);
4251 	dsi_vc_enable(dsidev, 2, 0);
4252 	dsi_vc_enable(dsidev, 3, 0);
4253 
4254 	dss_select_dsi_clk_source(dsi->module_id, OMAP_DSS_CLK_SRC_FCK);
4255 	dsi_cio_uninit(dsidev);
4256 	dsi_pll_uninit(dsidev, disconnect_lanes);
4257 }
4258 
4259 static int dsi_display_enable(struct omap_dss_device *dssdev)
4260 {
4261 	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4262 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4263 	int r = 0;
4264 
4265 	DSSDBG("dsi_display_enable\n");
4266 
4267 	WARN_ON(!dsi_bus_is_locked(dsidev));
4268 
4269 	mutex_lock(&dsi->lock);
4270 
4271 	r = dsi_runtime_get(dsidev);
4272 	if (r)
4273 		goto err_get_dsi;
4274 
4275 	_dsi_initialize_irq(dsidev);
4276 
4277 	r = dsi_display_init_dsi(dsidev);
4278 	if (r)
4279 		goto err_init_dsi;
4280 
4281 	mutex_unlock(&dsi->lock);
4282 
4283 	return 0;
4284 
4285 err_init_dsi:
4286 	dsi_runtime_put(dsidev);
4287 err_get_dsi:
4288 	mutex_unlock(&dsi->lock);
4289 	DSSDBG("dsi_display_enable FAILED\n");
4290 	return r;
4291 }
4292 
4293 static void dsi_display_disable(struct omap_dss_device *dssdev,
4294 		bool disconnect_lanes, bool enter_ulps)
4295 {
4296 	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4297 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4298 
4299 	DSSDBG("dsi_display_disable\n");
4300 
4301 	WARN_ON(!dsi_bus_is_locked(dsidev));
4302 
4303 	mutex_lock(&dsi->lock);
4304 
4305 	dsi_sync_vc(dsidev, 0);
4306 	dsi_sync_vc(dsidev, 1);
4307 	dsi_sync_vc(dsidev, 2);
4308 	dsi_sync_vc(dsidev, 3);
4309 
4310 	dsi_display_uninit_dsi(dsidev, disconnect_lanes, enter_ulps);
4311 
4312 	dsi_runtime_put(dsidev);
4313 
4314 	mutex_unlock(&dsi->lock);
4315 }
4316 
4317 static int dsi_enable_te(struct omap_dss_device *dssdev, bool enable)
4318 {
4319 	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4320 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4321 
4322 	dsi->te_enabled = enable;
4323 	return 0;
4324 }
4325 
4326 #ifdef PRINT_VERBOSE_VM_TIMINGS
4327 static void print_dsi_vm(const char *str,
4328 		const struct omap_dss_dsi_videomode_timings *t)
4329 {
4330 	unsigned long byteclk = t->hsclk / 4;
4331 	int bl, wc, pps, tot;
4332 
4333 	wc = DIV_ROUND_UP(t->hact * t->bitspp, 8);
4334 	pps = DIV_ROUND_UP(wc + 6, t->ndl); /* pixel packet size */
4335 	bl = t->hss + t->hsa + t->hse + t->hbp + t->hfp;
4336 	tot = bl + pps;
4337 
4338 #define TO_DSI_T(x) ((u32)div64_u64((u64)x * 1000000000llu, byteclk))
4339 
4340 	pr_debug("%s bck %lu, %u/%u/%u/%u/%u/%u = %u+%u = %u, "
4341 			"%u/%u/%u/%u/%u/%u = %u + %u = %u\n",
4342 			str,
4343 			byteclk,
4344 			t->hss, t->hsa, t->hse, t->hbp, pps, t->hfp,
4345 			bl, pps, tot,
4346 			TO_DSI_T(t->hss),
4347 			TO_DSI_T(t->hsa),
4348 			TO_DSI_T(t->hse),
4349 			TO_DSI_T(t->hbp),
4350 			TO_DSI_T(pps),
4351 			TO_DSI_T(t->hfp),
4352 
4353 			TO_DSI_T(bl),
4354 			TO_DSI_T(pps),
4355 
4356 			TO_DSI_T(tot));
4357 #undef TO_DSI_T
4358 }
4359 
4360 static void print_dispc_vm(const char *str, const struct omap_video_timings *t)
4361 {
4362 	unsigned long pck = t->pixelclock;
4363 	int hact, bl, tot;
4364 
4365 	hact = t->x_res;
4366 	bl = t->hsw + t->hbp + t->hfp;
4367 	tot = hact + bl;
4368 
4369 #define TO_DISPC_T(x) ((u32)div64_u64((u64)x * 1000000000llu, pck))
4370 
4371 	pr_debug("%s pck %lu, %u/%u/%u/%u = %u+%u = %u, "
4372 			"%u/%u/%u/%u = %u + %u = %u\n",
4373 			str,
4374 			pck,
4375 			t->hsw, t->hbp, hact, t->hfp,
4376 			bl, hact, tot,
4377 			TO_DISPC_T(t->hsw),
4378 			TO_DISPC_T(t->hbp),
4379 			TO_DISPC_T(hact),
4380 			TO_DISPC_T(t->hfp),
4381 			TO_DISPC_T(bl),
4382 			TO_DISPC_T(hact),
4383 			TO_DISPC_T(tot));
4384 #undef TO_DISPC_T
4385 }
4386 
4387 /* note: this is not quite accurate */
4388 static void print_dsi_dispc_vm(const char *str,
4389 		const struct omap_dss_dsi_videomode_timings *t)
4390 {
4391 	struct omap_video_timings vm = { 0 };
4392 	unsigned long byteclk = t->hsclk / 4;
4393 	unsigned long pck;
4394 	u64 dsi_tput;
4395 	int dsi_hact, dsi_htot;
4396 
4397 	dsi_tput = (u64)byteclk * t->ndl * 8;
4398 	pck = (u32)div64_u64(dsi_tput, t->bitspp);
4399 	dsi_hact = DIV_ROUND_UP(DIV_ROUND_UP(t->hact * t->bitspp, 8) + 6, t->ndl);
4400 	dsi_htot = t->hss + t->hsa + t->hse + t->hbp + dsi_hact + t->hfp;
4401 
4402 	vm.pixelclock = pck;
4403 	vm.hsw = div64_u64((u64)(t->hsa + t->hse) * pck, byteclk);
4404 	vm.hbp = div64_u64((u64)t->hbp * pck, byteclk);
4405 	vm.hfp = div64_u64((u64)t->hfp * pck, byteclk);
4406 	vm.x_res = t->hact;
4407 
4408 	print_dispc_vm(str, &vm);
4409 }
4410 #endif /* PRINT_VERBOSE_VM_TIMINGS */
4411 
4412 static bool dsi_cm_calc_dispc_cb(int lckd, int pckd, unsigned long lck,
4413 		unsigned long pck, void *data)
4414 {
4415 	struct dsi_clk_calc_ctx *ctx = data;
4416 	struct omap_video_timings *t = &ctx->dispc_vm;
4417 
4418 	ctx->dispc_cinfo.lck_div = lckd;
4419 	ctx->dispc_cinfo.pck_div = pckd;
4420 	ctx->dispc_cinfo.lck = lck;
4421 	ctx->dispc_cinfo.pck = pck;
4422 
4423 	*t = *ctx->config->timings;
4424 	t->pixelclock = pck;
4425 	t->x_res = ctx->config->timings->x_res;
4426 	t->y_res = ctx->config->timings->y_res;
4427 	t->hsw = t->hfp = t->hbp = t->vsw = 1;
4428 	t->vfp = t->vbp = 0;
4429 
4430 	return true;
4431 }
4432 
4433 static bool dsi_cm_calc_hsdiv_cb(int m_dispc, unsigned long dispc,
4434 		void *data)
4435 {
4436 	struct dsi_clk_calc_ctx *ctx = data;
4437 
4438 	ctx->dsi_cinfo.mX[HSDIV_DISPC] = m_dispc;
4439 	ctx->dsi_cinfo.clkout[HSDIV_DISPC] = dispc;
4440 
4441 	return dispc_div_calc(dispc, ctx->req_pck_min, ctx->req_pck_max,
4442 			dsi_cm_calc_dispc_cb, ctx);
4443 }
4444 
4445 static bool dsi_cm_calc_pll_cb(int n, int m, unsigned long fint,
4446 		unsigned long clkdco, void *data)
4447 {
4448 	struct dsi_clk_calc_ctx *ctx = data;
4449 
4450 	ctx->dsi_cinfo.n = n;
4451 	ctx->dsi_cinfo.m = m;
4452 	ctx->dsi_cinfo.fint = fint;
4453 	ctx->dsi_cinfo.clkdco = clkdco;
4454 
4455 	return dss_pll_hsdiv_calc(ctx->pll, clkdco, ctx->req_pck_min,
4456 			dss_feat_get_param_max(FEAT_PARAM_DSS_FCK),
4457 			dsi_cm_calc_hsdiv_cb, ctx);
4458 }
4459 
4460 static bool dsi_cm_calc(struct dsi_data *dsi,
4461 		const struct omap_dss_dsi_config *cfg,
4462 		struct dsi_clk_calc_ctx *ctx)
4463 {
4464 	unsigned long clkin;
4465 	int bitspp, ndl;
4466 	unsigned long pll_min, pll_max;
4467 	unsigned long pck, txbyteclk;
4468 
4469 	clkin = clk_get_rate(dsi->pll.clkin);
4470 	bitspp = dsi_get_pixel_size(cfg->pixel_format);
4471 	ndl = dsi->num_lanes_used - 1;
4472 
4473 	/*
4474 	 * Here we should calculate minimum txbyteclk to be able to send the
4475 	 * frame in time, and also to handle TE. That's not very simple, though,
4476 	 * especially as we go to LP between each pixel packet due to HW
4477 	 * "feature". So let's just estimate very roughly and multiply by 1.5.
4478 	 */
4479 	pck = cfg->timings->pixelclock;
4480 	pck = pck * 3 / 2;
4481 	txbyteclk = pck * bitspp / 8 / ndl;
4482 
4483 	memset(ctx, 0, sizeof(*ctx));
4484 	ctx->dsidev = dsi->pdev;
4485 	ctx->pll = &dsi->pll;
4486 	ctx->config = cfg;
4487 	ctx->req_pck_min = pck;
4488 	ctx->req_pck_nom = pck;
4489 	ctx->req_pck_max = pck * 3 / 2;
4490 
4491 	pll_min = max(cfg->hs_clk_min * 4, txbyteclk * 4 * 4);
4492 	pll_max = cfg->hs_clk_max * 4;
4493 
4494 	return dss_pll_calc(ctx->pll, clkin,
4495 			pll_min, pll_max,
4496 			dsi_cm_calc_pll_cb, ctx);
4497 }
4498 
4499 static bool dsi_vm_calc_blanking(struct dsi_clk_calc_ctx *ctx)
4500 {
4501 	struct dsi_data *dsi = dsi_get_dsidrv_data(ctx->dsidev);
4502 	const struct omap_dss_dsi_config *cfg = ctx->config;
4503 	int bitspp = dsi_get_pixel_size(cfg->pixel_format);
4504 	int ndl = dsi->num_lanes_used - 1;
4505 	unsigned long hsclk = ctx->dsi_cinfo.clkdco / 4;
4506 	unsigned long byteclk = hsclk / 4;
4507 
4508 	unsigned long dispc_pck, req_pck_min, req_pck_nom, req_pck_max;
4509 	int xres;
4510 	int panel_htot, panel_hbl; /* pixels */
4511 	int dispc_htot, dispc_hbl; /* pixels */
4512 	int dsi_htot, dsi_hact, dsi_hbl, hss, hse; /* byteclks */
4513 	int hfp, hsa, hbp;
4514 	const struct omap_video_timings *req_vm;
4515 	struct omap_video_timings *dispc_vm;
4516 	struct omap_dss_dsi_videomode_timings *dsi_vm;
4517 	u64 dsi_tput, dispc_tput;
4518 
4519 	dsi_tput = (u64)byteclk * ndl * 8;
4520 
4521 	req_vm = cfg->timings;
4522 	req_pck_min = ctx->req_pck_min;
4523 	req_pck_max = ctx->req_pck_max;
4524 	req_pck_nom = ctx->req_pck_nom;
4525 
4526 	dispc_pck = ctx->dispc_cinfo.pck;
4527 	dispc_tput = (u64)dispc_pck * bitspp;
4528 
4529 	xres = req_vm->x_res;
4530 
4531 	panel_hbl = req_vm->hfp + req_vm->hbp + req_vm->hsw;
4532 	panel_htot = xres + panel_hbl;
4533 
4534 	dsi_hact = DIV_ROUND_UP(DIV_ROUND_UP(xres * bitspp, 8) + 6, ndl);
4535 
4536 	/*
4537 	 * When there are no line buffers, DISPC and DSI must have the
4538 	 * same tput. Otherwise DISPC tput needs to be higher than DSI's.
4539 	 */
4540 	if (dsi->line_buffer_size < xres * bitspp / 8) {
4541 		if (dispc_tput != dsi_tput)
4542 			return false;
4543 	} else {
4544 		if (dispc_tput < dsi_tput)
4545 			return false;
4546 	}
4547 
4548 	/* DSI tput must be over the min requirement */
4549 	if (dsi_tput < (u64)bitspp * req_pck_min)
4550 		return false;
4551 
4552 	/* When non-burst mode, DSI tput must be below max requirement. */
4553 	if (cfg->trans_mode != OMAP_DSS_DSI_BURST_MODE) {
4554 		if (dsi_tput > (u64)bitspp * req_pck_max)
4555 			return false;
4556 	}
4557 
4558 	hss = DIV_ROUND_UP(4, ndl);
4559 
4560 	if (cfg->trans_mode == OMAP_DSS_DSI_PULSE_MODE) {
4561 		if (ndl == 3 && req_vm->hsw == 0)
4562 			hse = 1;
4563 		else
4564 			hse = DIV_ROUND_UP(4, ndl);
4565 	} else {
4566 		hse = 0;
4567 	}
4568 
4569 	/* DSI htot to match the panel's nominal pck */
4570 	dsi_htot = div64_u64((u64)panel_htot * byteclk, req_pck_nom);
4571 
4572 	/* fail if there would be no time for blanking */
4573 	if (dsi_htot < hss + hse + dsi_hact)
4574 		return false;
4575 
4576 	/* total DSI blanking needed to achieve panel's TL */
4577 	dsi_hbl = dsi_htot - dsi_hact;
4578 
4579 	/* DISPC htot to match the DSI TL */
4580 	dispc_htot = div64_u64((u64)dsi_htot * dispc_pck, byteclk);
4581 
4582 	/* verify that the DSI and DISPC TLs are the same */
4583 	if ((u64)dsi_htot * dispc_pck != (u64)dispc_htot * byteclk)
4584 		return false;
4585 
4586 	dispc_hbl = dispc_htot - xres;
4587 
4588 	/* setup DSI videomode */
4589 
4590 	dsi_vm = &ctx->dsi_vm;
4591 	memset(dsi_vm, 0, sizeof(*dsi_vm));
4592 
4593 	dsi_vm->hsclk = hsclk;
4594 
4595 	dsi_vm->ndl = ndl;
4596 	dsi_vm->bitspp = bitspp;
4597 
4598 	if (cfg->trans_mode != OMAP_DSS_DSI_PULSE_MODE) {
4599 		hsa = 0;
4600 	} else if (ndl == 3 && req_vm->hsw == 0) {
4601 		hsa = 0;
4602 	} else {
4603 		hsa = div64_u64((u64)req_vm->hsw * byteclk, req_pck_nom);
4604 		hsa = max(hsa - hse, 1);
4605 	}
4606 
4607 	hbp = div64_u64((u64)req_vm->hbp * byteclk, req_pck_nom);
4608 	hbp = max(hbp, 1);
4609 
4610 	hfp = dsi_hbl - (hss + hsa + hse + hbp);
4611 	if (hfp < 1) {
4612 		int t;
4613 		/* we need to take cycles from hbp */
4614 
4615 		t = 1 - hfp;
4616 		hbp = max(hbp - t, 1);
4617 		hfp = dsi_hbl - (hss + hsa + hse + hbp);
4618 
4619 		if (hfp < 1 && hsa > 0) {
4620 			/* we need to take cycles from hsa */
4621 			t = 1 - hfp;
4622 			hsa = max(hsa - t, 1);
4623 			hfp = dsi_hbl - (hss + hsa + hse + hbp);
4624 		}
4625 	}
4626 
4627 	if (hfp < 1)
4628 		return false;
4629 
4630 	dsi_vm->hss = hss;
4631 	dsi_vm->hsa = hsa;
4632 	dsi_vm->hse = hse;
4633 	dsi_vm->hbp = hbp;
4634 	dsi_vm->hact = xres;
4635 	dsi_vm->hfp = hfp;
4636 
4637 	dsi_vm->vsa = req_vm->vsw;
4638 	dsi_vm->vbp = req_vm->vbp;
4639 	dsi_vm->vact = req_vm->y_res;
4640 	dsi_vm->vfp = req_vm->vfp;
4641 
4642 	dsi_vm->trans_mode = cfg->trans_mode;
4643 
4644 	dsi_vm->blanking_mode = 0;
4645 	dsi_vm->hsa_blanking_mode = 1;
4646 	dsi_vm->hfp_blanking_mode = 1;
4647 	dsi_vm->hbp_blanking_mode = 1;
4648 
4649 	dsi_vm->ddr_clk_always_on = cfg->ddr_clk_always_on;
4650 	dsi_vm->window_sync = 4;
4651 
4652 	/* setup DISPC videomode */
4653 
4654 	dispc_vm = &ctx->dispc_vm;
4655 	*dispc_vm = *req_vm;
4656 	dispc_vm->pixelclock = dispc_pck;
4657 
4658 	if (cfg->trans_mode == OMAP_DSS_DSI_PULSE_MODE) {
4659 		hsa = div64_u64((u64)req_vm->hsw * dispc_pck,
4660 				req_pck_nom);
4661 		hsa = max(hsa, 1);
4662 	} else {
4663 		hsa = 1;
4664 	}
4665 
4666 	hbp = div64_u64((u64)req_vm->hbp * dispc_pck, req_pck_nom);
4667 	hbp = max(hbp, 1);
4668 
4669 	hfp = dispc_hbl - hsa - hbp;
4670 	if (hfp < 1) {
4671 		int t;
4672 		/* we need to take cycles from hbp */
4673 
4674 		t = 1 - hfp;
4675 		hbp = max(hbp - t, 1);
4676 		hfp = dispc_hbl - hsa - hbp;
4677 
4678 		if (hfp < 1) {
4679 			/* we need to take cycles from hsa */
4680 			t = 1 - hfp;
4681 			hsa = max(hsa - t, 1);
4682 			hfp = dispc_hbl - hsa - hbp;
4683 		}
4684 	}
4685 
4686 	if (hfp < 1)
4687 		return false;
4688 
4689 	dispc_vm->hfp = hfp;
4690 	dispc_vm->hsw = hsa;
4691 	dispc_vm->hbp = hbp;
4692 
4693 	return true;
4694 }
4695 
4696 
4697 static bool dsi_vm_calc_dispc_cb(int lckd, int pckd, unsigned long lck,
4698 		unsigned long pck, void *data)
4699 {
4700 	struct dsi_clk_calc_ctx *ctx = data;
4701 
4702 	ctx->dispc_cinfo.lck_div = lckd;
4703 	ctx->dispc_cinfo.pck_div = pckd;
4704 	ctx->dispc_cinfo.lck = lck;
4705 	ctx->dispc_cinfo.pck = pck;
4706 
4707 	if (dsi_vm_calc_blanking(ctx) == false)
4708 		return false;
4709 
4710 #ifdef PRINT_VERBOSE_VM_TIMINGS
4711 	print_dispc_vm("dispc", &ctx->dispc_vm);
4712 	print_dsi_vm("dsi  ", &ctx->dsi_vm);
4713 	print_dispc_vm("req  ", ctx->config->timings);
4714 	print_dsi_dispc_vm("act  ", &ctx->dsi_vm);
4715 #endif
4716 
4717 	return true;
4718 }
4719 
4720 static bool dsi_vm_calc_hsdiv_cb(int m_dispc, unsigned long dispc,
4721 		void *data)
4722 {
4723 	struct dsi_clk_calc_ctx *ctx = data;
4724 	unsigned long pck_max;
4725 
4726 	ctx->dsi_cinfo.mX[HSDIV_DISPC] = m_dispc;
4727 	ctx->dsi_cinfo.clkout[HSDIV_DISPC] = dispc;
4728 
4729 	/*
4730 	 * In burst mode we can let the dispc pck be arbitrarily high, but it
4731 	 * limits our scaling abilities. So for now, don't aim too high.
4732 	 */
4733 
4734 	if (ctx->config->trans_mode == OMAP_DSS_DSI_BURST_MODE)
4735 		pck_max = ctx->req_pck_max + 10000000;
4736 	else
4737 		pck_max = ctx->req_pck_max;
4738 
4739 	return dispc_div_calc(dispc, ctx->req_pck_min, pck_max,
4740 			dsi_vm_calc_dispc_cb, ctx);
4741 }
4742 
4743 static bool dsi_vm_calc_pll_cb(int n, int m, unsigned long fint,
4744 		unsigned long clkdco, void *data)
4745 {
4746 	struct dsi_clk_calc_ctx *ctx = data;
4747 
4748 	ctx->dsi_cinfo.n = n;
4749 	ctx->dsi_cinfo.m = m;
4750 	ctx->dsi_cinfo.fint = fint;
4751 	ctx->dsi_cinfo.clkdco = clkdco;
4752 
4753 	return dss_pll_hsdiv_calc(ctx->pll, clkdco, ctx->req_pck_min,
4754 			dss_feat_get_param_max(FEAT_PARAM_DSS_FCK),
4755 			dsi_vm_calc_hsdiv_cb, ctx);
4756 }
4757 
4758 static bool dsi_vm_calc(struct dsi_data *dsi,
4759 		const struct omap_dss_dsi_config *cfg,
4760 		struct dsi_clk_calc_ctx *ctx)
4761 {
4762 	const struct omap_video_timings *t = cfg->timings;
4763 	unsigned long clkin;
4764 	unsigned long pll_min;
4765 	unsigned long pll_max;
4766 	int ndl = dsi->num_lanes_used - 1;
4767 	int bitspp = dsi_get_pixel_size(cfg->pixel_format);
4768 	unsigned long byteclk_min;
4769 
4770 	clkin = clk_get_rate(dsi->pll.clkin);
4771 
4772 	memset(ctx, 0, sizeof(*ctx));
4773 	ctx->dsidev = dsi->pdev;
4774 	ctx->pll = &dsi->pll;
4775 	ctx->config = cfg;
4776 
4777 	/* these limits should come from the panel driver */
4778 	ctx->req_pck_min = t->pixelclock - 1000;
4779 	ctx->req_pck_nom = t->pixelclock;
4780 	ctx->req_pck_max = t->pixelclock + 1000;
4781 
4782 	byteclk_min = div64_u64((u64)ctx->req_pck_min * bitspp, ndl * 8);
4783 	pll_min = max(cfg->hs_clk_min * 4, byteclk_min * 4 * 4);
4784 
4785 	if (cfg->trans_mode == OMAP_DSS_DSI_BURST_MODE) {
4786 		pll_max = cfg->hs_clk_max * 4;
4787 	} else {
4788 		unsigned long byteclk_max;
4789 		byteclk_max = div64_u64((u64)ctx->req_pck_max * bitspp,
4790 				ndl * 8);
4791 
4792 		pll_max = byteclk_max * 4 * 4;
4793 	}
4794 
4795 	return dss_pll_calc(ctx->pll, clkin,
4796 			pll_min, pll_max,
4797 			dsi_vm_calc_pll_cb, ctx);
4798 }
4799 
4800 static int dsi_set_config(struct omap_dss_device *dssdev,
4801 		const struct omap_dss_dsi_config *config)
4802 {
4803 	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4804 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4805 	struct dsi_clk_calc_ctx ctx;
4806 	bool ok;
4807 	int r;
4808 
4809 	mutex_lock(&dsi->lock);
4810 
4811 	dsi->pix_fmt = config->pixel_format;
4812 	dsi->mode = config->mode;
4813 
4814 	if (config->mode == OMAP_DSS_DSI_VIDEO_MODE)
4815 		ok = dsi_vm_calc(dsi, config, &ctx);
4816 	else
4817 		ok = dsi_cm_calc(dsi, config, &ctx);
4818 
4819 	if (!ok) {
4820 		DSSERR("failed to find suitable DSI clock settings\n");
4821 		r = -EINVAL;
4822 		goto err;
4823 	}
4824 
4825 	dsi_pll_calc_dsi_fck(&ctx.dsi_cinfo);
4826 
4827 	r = dsi_lp_clock_calc(ctx.dsi_cinfo.clkout[HSDIV_DSI],
4828 		config->lp_clk_min, config->lp_clk_max, &dsi->user_lp_cinfo);
4829 	if (r) {
4830 		DSSERR("failed to find suitable DSI LP clock settings\n");
4831 		goto err;
4832 	}
4833 
4834 	dsi->user_dsi_cinfo = ctx.dsi_cinfo;
4835 	dsi->user_dispc_cinfo = ctx.dispc_cinfo;
4836 
4837 	dsi->timings = ctx.dispc_vm;
4838 	dsi->vm_timings = ctx.dsi_vm;
4839 
4840 	mutex_unlock(&dsi->lock);
4841 
4842 	return 0;
4843 err:
4844 	mutex_unlock(&dsi->lock);
4845 
4846 	return r;
4847 }
4848 
4849 /*
4850  * Return a hardcoded channel for the DSI output. This should work for
4851  * current use cases, but this can be later expanded to either resolve
4852  * the channel in some more dynamic manner, or get the channel as a user
4853  * parameter.
4854  */
4855 static enum omap_channel dsi_get_channel(int module_id)
4856 {
4857 	switch (omapdss_get_version()) {
4858 	case OMAPDSS_VER_OMAP24xx:
4859 	case OMAPDSS_VER_AM43xx:
4860 		DSSWARN("DSI not supported\n");
4861 		return OMAP_DSS_CHANNEL_LCD;
4862 
4863 	case OMAPDSS_VER_OMAP34xx_ES1:
4864 	case OMAPDSS_VER_OMAP34xx_ES3:
4865 	case OMAPDSS_VER_OMAP3630:
4866 	case OMAPDSS_VER_AM35xx:
4867 		return OMAP_DSS_CHANNEL_LCD;
4868 
4869 	case OMAPDSS_VER_OMAP4430_ES1:
4870 	case OMAPDSS_VER_OMAP4430_ES2:
4871 	case OMAPDSS_VER_OMAP4:
4872 		switch (module_id) {
4873 		case 0:
4874 			return OMAP_DSS_CHANNEL_LCD;
4875 		case 1:
4876 			return OMAP_DSS_CHANNEL_LCD2;
4877 		default:
4878 			DSSWARN("unsupported module id\n");
4879 			return OMAP_DSS_CHANNEL_LCD;
4880 		}
4881 
4882 	case OMAPDSS_VER_OMAP5:
4883 		switch (module_id) {
4884 		case 0:
4885 			return OMAP_DSS_CHANNEL_LCD;
4886 		case 1:
4887 			return OMAP_DSS_CHANNEL_LCD3;
4888 		default:
4889 			DSSWARN("unsupported module id\n");
4890 			return OMAP_DSS_CHANNEL_LCD;
4891 		}
4892 
4893 	default:
4894 		DSSWARN("unsupported DSS version\n");
4895 		return OMAP_DSS_CHANNEL_LCD;
4896 	}
4897 }
4898 
4899 static int dsi_request_vc(struct omap_dss_device *dssdev, int *channel)
4900 {
4901 	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4902 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4903 	int i;
4904 
4905 	for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) {
4906 		if (!dsi->vc[i].dssdev) {
4907 			dsi->vc[i].dssdev = dssdev;
4908 			*channel = i;
4909 			return 0;
4910 		}
4911 	}
4912 
4913 	DSSERR("cannot get VC for display %s", dssdev->name);
4914 	return -ENOSPC;
4915 }
4916 
4917 static int dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id)
4918 {
4919 	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4920 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4921 
4922 	if (vc_id < 0 || vc_id > 3) {
4923 		DSSERR("VC ID out of range\n");
4924 		return -EINVAL;
4925 	}
4926 
4927 	if (channel < 0 || channel > 3) {
4928 		DSSERR("Virtual Channel out of range\n");
4929 		return -EINVAL;
4930 	}
4931 
4932 	if (dsi->vc[channel].dssdev != dssdev) {
4933 		DSSERR("Virtual Channel not allocated to display %s\n",
4934 			dssdev->name);
4935 		return -EINVAL;
4936 	}
4937 
4938 	dsi->vc[channel].vc_id = vc_id;
4939 
4940 	return 0;
4941 }
4942 
4943 static void dsi_release_vc(struct omap_dss_device *dssdev, int channel)
4944 {
4945 	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4946 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4947 
4948 	if ((channel >= 0 && channel <= 3) &&
4949 		dsi->vc[channel].dssdev == dssdev) {
4950 		dsi->vc[channel].dssdev = NULL;
4951 		dsi->vc[channel].vc_id = 0;
4952 	}
4953 }
4954 
4955 
4956 static int dsi_get_clocks(struct platform_device *dsidev)
4957 {
4958 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4959 	struct clk *clk;
4960 
4961 	clk = devm_clk_get(&dsidev->dev, "fck");
4962 	if (IS_ERR(clk)) {
4963 		DSSERR("can't get fck\n");
4964 		return PTR_ERR(clk);
4965 	}
4966 
4967 	dsi->dss_clk = clk;
4968 
4969 	return 0;
4970 }
4971 
4972 static int dsi_connect(struct omap_dss_device *dssdev,
4973 		struct omap_dss_device *dst)
4974 {
4975 	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4976 	struct omap_overlay_manager *mgr;
4977 	int r;
4978 
4979 	r = dsi_regulator_init(dsidev);
4980 	if (r)
4981 		return r;
4982 
4983 	mgr = omap_dss_get_overlay_manager(dssdev->dispc_channel);
4984 	if (!mgr)
4985 		return -ENODEV;
4986 
4987 	r = dss_mgr_connect(mgr, dssdev);
4988 	if (r)
4989 		return r;
4990 
4991 	r = omapdss_output_set_device(dssdev, dst);
4992 	if (r) {
4993 		DSSERR("failed to connect output to new device: %s\n",
4994 				dssdev->name);
4995 		dss_mgr_disconnect(mgr, dssdev);
4996 		return r;
4997 	}
4998 
4999 	return 0;
5000 }
5001 
5002 static void dsi_disconnect(struct omap_dss_device *dssdev,
5003 		struct omap_dss_device *dst)
5004 {
5005 	WARN_ON(dst != dssdev->dst);
5006 
5007 	if (dst != dssdev->dst)
5008 		return;
5009 
5010 	omapdss_output_unset_device(dssdev);
5011 
5012 	if (dssdev->manager)
5013 		dss_mgr_disconnect(dssdev->manager, dssdev);
5014 }
5015 
5016 static const struct omapdss_dsi_ops dsi_ops = {
5017 	.connect = dsi_connect,
5018 	.disconnect = dsi_disconnect,
5019 
5020 	.bus_lock = dsi_bus_lock,
5021 	.bus_unlock = dsi_bus_unlock,
5022 
5023 	.enable = dsi_display_enable,
5024 	.disable = dsi_display_disable,
5025 
5026 	.enable_hs = dsi_vc_enable_hs,
5027 
5028 	.configure_pins = dsi_configure_pins,
5029 	.set_config = dsi_set_config,
5030 
5031 	.enable_video_output = dsi_enable_video_output,
5032 	.disable_video_output = dsi_disable_video_output,
5033 
5034 	.update = dsi_update,
5035 
5036 	.enable_te = dsi_enable_te,
5037 
5038 	.request_vc = dsi_request_vc,
5039 	.set_vc_id = dsi_set_vc_id,
5040 	.release_vc = dsi_release_vc,
5041 
5042 	.dcs_write = dsi_vc_dcs_write,
5043 	.dcs_write_nosync = dsi_vc_dcs_write_nosync,
5044 	.dcs_read = dsi_vc_dcs_read,
5045 
5046 	.gen_write = dsi_vc_generic_write,
5047 	.gen_write_nosync = dsi_vc_generic_write_nosync,
5048 	.gen_read = dsi_vc_generic_read,
5049 
5050 	.bta_sync = dsi_vc_send_bta_sync,
5051 
5052 	.set_max_rx_packet_size = dsi_vc_set_max_rx_packet_size,
5053 };
5054 
5055 static void dsi_init_output(struct platform_device *dsidev)
5056 {
5057 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5058 	struct omap_dss_device *out = &dsi->output;
5059 
5060 	out->dev = &dsidev->dev;
5061 	out->id = dsi->module_id == 0 ?
5062 			OMAP_DSS_OUTPUT_DSI1 : OMAP_DSS_OUTPUT_DSI2;
5063 
5064 	out->output_type = OMAP_DISPLAY_TYPE_DSI;
5065 	out->name = dsi->module_id == 0 ? "dsi.0" : "dsi.1";
5066 	out->dispc_channel = dsi_get_channel(dsi->module_id);
5067 	out->ops.dsi = &dsi_ops;
5068 	out->owner = THIS_MODULE;
5069 
5070 	omapdss_register_output(out);
5071 }
5072 
5073 static void dsi_uninit_output(struct platform_device *dsidev)
5074 {
5075 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5076 	struct omap_dss_device *out = &dsi->output;
5077 
5078 	omapdss_unregister_output(out);
5079 }
5080 
5081 static int dsi_probe_of(struct platform_device *pdev)
5082 {
5083 	struct device_node *node = pdev->dev.of_node;
5084 	struct dsi_data *dsi = dsi_get_dsidrv_data(pdev);
5085 	struct property *prop;
5086 	u32 lane_arr[10];
5087 	int len, num_pins;
5088 	int r, i;
5089 	struct device_node *ep;
5090 	struct omap_dsi_pin_config pin_cfg;
5091 
5092 	ep = omapdss_of_get_first_endpoint(node);
5093 	if (!ep)
5094 		return 0;
5095 
5096 	prop = of_find_property(ep, "lanes", &len);
5097 	if (prop == NULL) {
5098 		dev_err(&pdev->dev, "failed to find lane data\n");
5099 		r = -EINVAL;
5100 		goto err;
5101 	}
5102 
5103 	num_pins = len / sizeof(u32);
5104 
5105 	if (num_pins < 4 || num_pins % 2 != 0 ||
5106 		num_pins > dsi->num_lanes_supported * 2) {
5107 		dev_err(&pdev->dev, "bad number of lanes\n");
5108 		r = -EINVAL;
5109 		goto err;
5110 	}
5111 
5112 	r = of_property_read_u32_array(ep, "lanes", lane_arr, num_pins);
5113 	if (r) {
5114 		dev_err(&pdev->dev, "failed to read lane data\n");
5115 		goto err;
5116 	}
5117 
5118 	pin_cfg.num_pins = num_pins;
5119 	for (i = 0; i < num_pins; ++i)
5120 		pin_cfg.pins[i] = (int)lane_arr[i];
5121 
5122 	r = dsi_configure_pins(&dsi->output, &pin_cfg);
5123 	if (r) {
5124 		dev_err(&pdev->dev, "failed to configure pins");
5125 		goto err;
5126 	}
5127 
5128 	of_node_put(ep);
5129 
5130 	return 0;
5131 
5132 err:
5133 	of_node_put(ep);
5134 	return r;
5135 }
5136 
5137 static const struct dss_pll_ops dsi_pll_ops = {
5138 	.enable = dsi_pll_enable,
5139 	.disable = dsi_pll_disable,
5140 	.set_config = dss_pll_write_config_type_a,
5141 };
5142 
5143 static const struct dss_pll_hw dss_omap3_dsi_pll_hw = {
5144 	.n_max = (1 << 7) - 1,
5145 	.m_max = (1 << 11) - 1,
5146 	.mX_max = (1 << 4) - 1,
5147 	.fint_min = 750000,
5148 	.fint_max = 2100000,
5149 	.clkdco_low = 1000000000,
5150 	.clkdco_max = 1800000000,
5151 
5152 	.n_msb = 7,
5153 	.n_lsb = 1,
5154 	.m_msb = 18,
5155 	.m_lsb = 8,
5156 
5157 	.mX_msb[0] = 22,
5158 	.mX_lsb[0] = 19,
5159 	.mX_msb[1] = 26,
5160 	.mX_lsb[1] = 23,
5161 
5162 	.has_stopmode = true,
5163 	.has_freqsel = true,
5164 	.has_selfreqdco = false,
5165 	.has_refsel = false,
5166 };
5167 
5168 static const struct dss_pll_hw dss_omap4_dsi_pll_hw = {
5169 	.n_max = (1 << 8) - 1,
5170 	.m_max = (1 << 12) - 1,
5171 	.mX_max = (1 << 5) - 1,
5172 	.fint_min = 500000,
5173 	.fint_max = 2500000,
5174 	.clkdco_low = 1000000000,
5175 	.clkdco_max = 1800000000,
5176 
5177 	.n_msb = 8,
5178 	.n_lsb = 1,
5179 	.m_msb = 20,
5180 	.m_lsb = 9,
5181 
5182 	.mX_msb[0] = 25,
5183 	.mX_lsb[0] = 21,
5184 	.mX_msb[1] = 30,
5185 	.mX_lsb[1] = 26,
5186 
5187 	.has_stopmode = true,
5188 	.has_freqsel = false,
5189 	.has_selfreqdco = false,
5190 	.has_refsel = false,
5191 };
5192 
5193 static const struct dss_pll_hw dss_omap5_dsi_pll_hw = {
5194 	.n_max = (1 << 8) - 1,
5195 	.m_max = (1 << 12) - 1,
5196 	.mX_max = (1 << 5) - 1,
5197 	.fint_min = 150000,
5198 	.fint_max = 52000000,
5199 	.clkdco_low = 1000000000,
5200 	.clkdco_max = 1800000000,
5201 
5202 	.n_msb = 8,
5203 	.n_lsb = 1,
5204 	.m_msb = 20,
5205 	.m_lsb = 9,
5206 
5207 	.mX_msb[0] = 25,
5208 	.mX_lsb[0] = 21,
5209 	.mX_msb[1] = 30,
5210 	.mX_lsb[1] = 26,
5211 
5212 	.has_stopmode = true,
5213 	.has_freqsel = false,
5214 	.has_selfreqdco = true,
5215 	.has_refsel = true,
5216 };
5217 
5218 static int dsi_init_pll_data(struct platform_device *dsidev)
5219 {
5220 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5221 	struct dss_pll *pll = &dsi->pll;
5222 	struct clk *clk;
5223 	int r;
5224 
5225 	clk = devm_clk_get(&dsidev->dev, "sys_clk");
5226 	if (IS_ERR(clk)) {
5227 		DSSERR("can't get sys_clk\n");
5228 		return PTR_ERR(clk);
5229 	}
5230 
5231 	pll->name = dsi->module_id == 0 ? "dsi0" : "dsi1";
5232 	pll->id = dsi->module_id == 0 ? DSS_PLL_DSI1 : DSS_PLL_DSI2;
5233 	pll->clkin = clk;
5234 	pll->base = dsi->pll_base;
5235 
5236 	switch (omapdss_get_version()) {
5237 	case OMAPDSS_VER_OMAP34xx_ES1:
5238 	case OMAPDSS_VER_OMAP34xx_ES3:
5239 	case OMAPDSS_VER_OMAP3630:
5240 	case OMAPDSS_VER_AM35xx:
5241 		pll->hw = &dss_omap3_dsi_pll_hw;
5242 		break;
5243 
5244 	case OMAPDSS_VER_OMAP4430_ES1:
5245 	case OMAPDSS_VER_OMAP4430_ES2:
5246 	case OMAPDSS_VER_OMAP4:
5247 		pll->hw = &dss_omap4_dsi_pll_hw;
5248 		break;
5249 
5250 	case OMAPDSS_VER_OMAP5:
5251 		pll->hw = &dss_omap5_dsi_pll_hw;
5252 		break;
5253 
5254 	default:
5255 		return -ENODEV;
5256 	}
5257 
5258 	pll->ops = &dsi_pll_ops;
5259 
5260 	r = dss_pll_register(pll);
5261 	if (r)
5262 		return r;
5263 
5264 	return 0;
5265 }
5266 
5267 /* DSI1 HW IP initialisation */
5268 static int dsi_bind(struct device *dev, struct device *master, void *data)
5269 {
5270 	struct platform_device *dsidev = to_platform_device(dev);
5271 	u32 rev;
5272 	int r, i;
5273 	struct dsi_data *dsi;
5274 	struct resource *dsi_mem;
5275 	struct resource *res;
5276 	struct resource temp_res;
5277 
5278 	dsi = devm_kzalloc(&dsidev->dev, sizeof(*dsi), GFP_KERNEL);
5279 	if (!dsi)
5280 		return -ENOMEM;
5281 
5282 	dsi->pdev = dsidev;
5283 	dev_set_drvdata(&dsidev->dev, dsi);
5284 
5285 	spin_lock_init(&dsi->irq_lock);
5286 	spin_lock_init(&dsi->errors_lock);
5287 	dsi->errors = 0;
5288 
5289 #ifdef CONFIG_FB_OMAP2_DSS_COLLECT_IRQ_STATS
5290 	spin_lock_init(&dsi->irq_stats_lock);
5291 	dsi->irq_stats.last_reset = jiffies;
5292 #endif
5293 
5294 	mutex_init(&dsi->lock);
5295 	sema_init(&dsi->bus_lock, 1);
5296 
5297 	INIT_DEFERRABLE_WORK(&dsi->framedone_timeout_work,
5298 			     dsi_framedone_timeout_work_callback);
5299 
5300 #ifdef DSI_CATCH_MISSING_TE
5301 	timer_setup(&dsi->te_timer, dsi_te_timeout, 0);
5302 #endif
5303 
5304 	res = platform_get_resource_byname(dsidev, IORESOURCE_MEM, "proto");
5305 	if (!res) {
5306 		res = platform_get_resource(dsidev, IORESOURCE_MEM, 0);
5307 		if (!res) {
5308 			DSSERR("can't get IORESOURCE_MEM DSI\n");
5309 			return -EINVAL;
5310 		}
5311 
5312 		temp_res.start = res->start;
5313 		temp_res.end = temp_res.start + DSI_PROTO_SZ - 1;
5314 		res = &temp_res;
5315 	}
5316 
5317 	dsi_mem = res;
5318 
5319 	dsi->proto_base = devm_ioremap(&dsidev->dev, res->start,
5320 		resource_size(res));
5321 	if (!dsi->proto_base) {
5322 		DSSERR("can't ioremap DSI protocol engine\n");
5323 		return -ENOMEM;
5324 	}
5325 
5326 	res = platform_get_resource_byname(dsidev, IORESOURCE_MEM, "phy");
5327 	if (!res) {
5328 		res = platform_get_resource(dsidev, IORESOURCE_MEM, 0);
5329 		if (!res) {
5330 			DSSERR("can't get IORESOURCE_MEM DSI\n");
5331 			return -EINVAL;
5332 		}
5333 
5334 		temp_res.start = res->start + DSI_PHY_OFFSET;
5335 		temp_res.end = temp_res.start + DSI_PHY_SZ - 1;
5336 		res = &temp_res;
5337 	}
5338 
5339 	dsi->phy_base = devm_ioremap(&dsidev->dev, res->start,
5340 		resource_size(res));
5341 	if (!dsi->phy_base) {
5342 		DSSERR("can't ioremap DSI PHY\n");
5343 		return -ENOMEM;
5344 	}
5345 
5346 	res = platform_get_resource_byname(dsidev, IORESOURCE_MEM, "pll");
5347 	if (!res) {
5348 		res = platform_get_resource(dsidev, IORESOURCE_MEM, 0);
5349 		if (!res) {
5350 			DSSERR("can't get IORESOURCE_MEM DSI\n");
5351 			return -EINVAL;
5352 		}
5353 
5354 		temp_res.start = res->start + DSI_PLL_OFFSET;
5355 		temp_res.end = temp_res.start + DSI_PLL_SZ - 1;
5356 		res = &temp_res;
5357 	}
5358 
5359 	dsi->pll_base = devm_ioremap(&dsidev->dev, res->start,
5360 		resource_size(res));
5361 	if (!dsi->pll_base) {
5362 		DSSERR("can't ioremap DSI PLL\n");
5363 		return -ENOMEM;
5364 	}
5365 
5366 	dsi->irq = platform_get_irq(dsi->pdev, 0);
5367 	if (dsi->irq < 0) {
5368 		DSSERR("platform_get_irq failed\n");
5369 		return -ENODEV;
5370 	}
5371 
5372 	r = devm_request_irq(&dsidev->dev, dsi->irq, omap_dsi_irq_handler,
5373 			     IRQF_SHARED, dev_name(&dsidev->dev), dsi->pdev);
5374 	if (r < 0) {
5375 		DSSERR("request_irq failed\n");
5376 		return r;
5377 	}
5378 
5379 	if (dsidev->dev.of_node) {
5380 		const struct of_device_id *match;
5381 		const struct dsi_module_id_data *d;
5382 
5383 		match = of_match_node(dsi_of_match, dsidev->dev.of_node);
5384 		if (!match) {
5385 			DSSERR("unsupported DSI module\n");
5386 			return -ENODEV;
5387 		}
5388 
5389 		d = match->data;
5390 
5391 		while (d->address != 0 && d->address != dsi_mem->start)
5392 			d++;
5393 
5394 		if (d->address == 0) {
5395 			DSSERR("unsupported DSI module\n");
5396 			return -ENODEV;
5397 		}
5398 
5399 		dsi->module_id = d->id;
5400 	} else {
5401 		dsi->module_id = dsidev->id;
5402 	}
5403 
5404 	/* DSI VCs initialization */
5405 	for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) {
5406 		dsi->vc[i].source = DSI_VC_SOURCE_L4;
5407 		dsi->vc[i].dssdev = NULL;
5408 		dsi->vc[i].vc_id = 0;
5409 	}
5410 
5411 	r = dsi_get_clocks(dsidev);
5412 	if (r)
5413 		return r;
5414 
5415 	dsi_init_pll_data(dsidev);
5416 
5417 	pm_runtime_enable(&dsidev->dev);
5418 
5419 	r = dsi_runtime_get(dsidev);
5420 	if (r)
5421 		goto err_runtime_get;
5422 
5423 	rev = dsi_read_reg(dsidev, DSI_REVISION);
5424 	dev_dbg(&dsidev->dev, "OMAP DSI rev %d.%d\n",
5425 	       FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
5426 
5427 	/* DSI on OMAP3 doesn't have register DSI_GNQ, set number
5428 	 * of data to 3 by default */
5429 	if (dss_has_feature(FEAT_DSI_GNQ))
5430 		/* NB_DATA_LANES */
5431 		dsi->num_lanes_supported = 1 + REG_GET(dsidev, DSI_GNQ, 11, 9);
5432 	else
5433 		dsi->num_lanes_supported = 3;
5434 
5435 	dsi->line_buffer_size = dsi_get_line_buf_size(dsidev);
5436 
5437 	dsi_init_output(dsidev);
5438 
5439 	if (dsidev->dev.of_node) {
5440 		r = dsi_probe_of(dsidev);
5441 		if (r) {
5442 			DSSERR("Invalid DSI DT data\n");
5443 			goto err_probe_of;
5444 		}
5445 
5446 		r = of_platform_populate(dsidev->dev.of_node, NULL, NULL,
5447 			&dsidev->dev);
5448 		if (r)
5449 			DSSERR("Failed to populate DSI child devices: %d\n", r);
5450 	}
5451 
5452 	dsi_runtime_put(dsidev);
5453 
5454 	if (dsi->module_id == 0)
5455 		dss_debugfs_create_file("dsi1_regs", dsi1_dump_regs);
5456 	else if (dsi->module_id == 1)
5457 		dss_debugfs_create_file("dsi2_regs", dsi2_dump_regs);
5458 
5459 #ifdef CONFIG_FB_OMAP2_DSS_COLLECT_IRQ_STATS
5460 	if (dsi->module_id == 0)
5461 		dss_debugfs_create_file("dsi1_irqs", dsi1_dump_irqs);
5462 	else if (dsi->module_id == 1)
5463 		dss_debugfs_create_file("dsi2_irqs", dsi2_dump_irqs);
5464 #endif
5465 
5466 	return 0;
5467 
5468 err_probe_of:
5469 	dsi_uninit_output(dsidev);
5470 	dsi_runtime_put(dsidev);
5471 
5472 err_runtime_get:
5473 	pm_runtime_disable(&dsidev->dev);
5474 	return r;
5475 }
5476 
5477 static void dsi_unbind(struct device *dev, struct device *master, void *data)
5478 {
5479 	struct platform_device *dsidev = to_platform_device(dev);
5480 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5481 
5482 	of_platform_depopulate(&dsidev->dev);
5483 
5484 	WARN_ON(dsi->scp_clk_refcount > 0);
5485 
5486 	dss_pll_unregister(&dsi->pll);
5487 
5488 	dsi_uninit_output(dsidev);
5489 
5490 	pm_runtime_disable(&dsidev->dev);
5491 
5492 	if (dsi->vdds_dsi_reg != NULL && dsi->vdds_dsi_enabled) {
5493 		regulator_disable(dsi->vdds_dsi_reg);
5494 		dsi->vdds_dsi_enabled = false;
5495 	}
5496 }
5497 
5498 static const struct component_ops dsi_component_ops = {
5499 	.bind	= dsi_bind,
5500 	.unbind	= dsi_unbind,
5501 };
5502 
5503 static int dsi_probe(struct platform_device *pdev)
5504 {
5505 	return component_add(&pdev->dev, &dsi_component_ops);
5506 }
5507 
5508 static int dsi_remove(struct platform_device *pdev)
5509 {
5510 	component_del(&pdev->dev, &dsi_component_ops);
5511 	return 0;
5512 }
5513 
5514 static int dsi_runtime_suspend(struct device *dev)
5515 {
5516 	struct platform_device *pdev = to_platform_device(dev);
5517 	struct dsi_data *dsi = dsi_get_dsidrv_data(pdev);
5518 
5519 	dsi->is_enabled = false;
5520 	/* ensure the irq handler sees the is_enabled value */
5521 	smp_wmb();
5522 	/* wait for current handler to finish before turning the DSI off */
5523 	synchronize_irq(dsi->irq);
5524 
5525 	dispc_runtime_put();
5526 
5527 	return 0;
5528 }
5529 
5530 static int dsi_runtime_resume(struct device *dev)
5531 {
5532 	struct platform_device *pdev = to_platform_device(dev);
5533 	struct dsi_data *dsi = dsi_get_dsidrv_data(pdev);
5534 	int r;
5535 
5536 	r = dispc_runtime_get();
5537 	if (r)
5538 		return r;
5539 
5540 	dsi->is_enabled = true;
5541 	/* ensure the irq handler sees the is_enabled value */
5542 	smp_wmb();
5543 
5544 	return 0;
5545 }
5546 
5547 static const struct dev_pm_ops dsi_pm_ops = {
5548 	.runtime_suspend = dsi_runtime_suspend,
5549 	.runtime_resume = dsi_runtime_resume,
5550 };
5551 
5552 static const struct dsi_module_id_data dsi_of_data_omap3[] = {
5553 	{ .address = 0x4804fc00, .id = 0, },
5554 	{ },
5555 };
5556 
5557 static const struct dsi_module_id_data dsi_of_data_omap4[] = {
5558 	{ .address = 0x58004000, .id = 0, },
5559 	{ .address = 0x58005000, .id = 1, },
5560 	{ },
5561 };
5562 
5563 static const struct dsi_module_id_data dsi_of_data_omap5[] = {
5564 	{ .address = 0x58004000, .id = 0, },
5565 	{ .address = 0x58009000, .id = 1, },
5566 	{ },
5567 };
5568 
5569 static const struct of_device_id dsi_of_match[] = {
5570 	{ .compatible = "ti,omap3-dsi", .data = dsi_of_data_omap3, },
5571 	{ .compatible = "ti,omap4-dsi", .data = dsi_of_data_omap4, },
5572 	{ .compatible = "ti,omap5-dsi", .data = dsi_of_data_omap5, },
5573 	{},
5574 };
5575 
5576 static struct platform_driver omap_dsihw_driver = {
5577 	.probe		= dsi_probe,
5578 	.remove		= dsi_remove,
5579 	.driver         = {
5580 		.name   = "omapdss_dsi",
5581 		.pm	= &dsi_pm_ops,
5582 		.of_match_table = dsi_of_match,
5583 		.suppress_bind_attrs = true,
5584 	},
5585 };
5586 
5587 int __init dsi_init_platform_driver(void)
5588 {
5589 	return platform_driver_register(&omap_dsihw_driver);
5590 }
5591 
5592 void dsi_uninit_platform_driver(void)
5593 {
5594 	platform_driver_unregister(&omap_dsihw_driver);
5595 }
5596