1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * linux/drivers/video/omap2/dss/dispc.c 4 * 5 * Copyright (C) 2009 Nokia Corporation 6 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> 7 * 8 * Some code and ideas taken from drivers/video/omap/ driver 9 * by Imre Deak. 10 */ 11 12 #define DSS_SUBSYS_NAME "DISPC" 13 14 #include <linux/kernel.h> 15 #include <linux/dma-mapping.h> 16 #include <linux/vmalloc.h> 17 #include <linux/export.h> 18 #include <linux/clk.h> 19 #include <linux/io.h> 20 #include <linux/jiffies.h> 21 #include <linux/seq_file.h> 22 #include <linux/delay.h> 23 #include <linux/workqueue.h> 24 #include <linux/hardirq.h> 25 #include <linux/platform_device.h> 26 #include <linux/pm_runtime.h> 27 #include <linux/sizes.h> 28 #include <linux/mfd/syscon.h> 29 #include <linux/regmap.h> 30 #include <linux/of.h> 31 #include <linux/component.h> 32 33 #include <video/omapfb_dss.h> 34 35 #include "dss.h" 36 #include "dss_features.h" 37 #include "dispc.h" 38 39 /* DISPC */ 40 #define DISPC_SZ_REGS SZ_4K 41 42 enum omap_burst_size { 43 BURST_SIZE_X2 = 0, 44 BURST_SIZE_X4 = 1, 45 BURST_SIZE_X8 = 2, 46 }; 47 48 #define REG_GET(idx, start, end) \ 49 FLD_GET(dispc_read_reg(idx), start, end) 50 51 #define REG_FLD_MOD(idx, val, start, end) \ 52 dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end)) 53 54 struct dispc_features { 55 u8 sw_start; 56 u8 fp_start; 57 u8 bp_start; 58 u16 sw_max; 59 u16 vp_max; 60 u16 hp_max; 61 u8 mgr_width_start; 62 u8 mgr_height_start; 63 u16 mgr_width_max; 64 u16 mgr_height_max; 65 unsigned long max_lcd_pclk; 66 unsigned long max_tv_pclk; 67 int (*calc_scaling) (unsigned long pclk, unsigned long lclk, 68 const struct omap_video_timings *mgr_timings, 69 u16 width, u16 height, u16 out_width, u16 out_height, 70 enum omap_color_mode color_mode, bool *five_taps, 71 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y, 72 u16 pos_x, unsigned long *core_clk, bool mem_to_mem); 73 unsigned long (*calc_core_clk) (unsigned long pclk, 74 u16 width, u16 height, u16 out_width, u16 out_height, 75 bool mem_to_mem); 76 u8 num_fifos; 77 78 /* swap GFX & WB fifos */ 79 bool gfx_fifo_workaround:1; 80 81 /* no DISPC_IRQ_FRAMEDONETV on this SoC */ 82 bool no_framedone_tv:1; 83 84 /* revert to the OMAP4 mechanism of DISPC Smart Standby operation */ 85 bool mstandby_workaround:1; 86 87 bool set_max_preload:1; 88 89 /* PIXEL_INC is not added to the last pixel of a line */ 90 bool last_pixel_inc_missing:1; 91 92 /* POL_FREQ has ALIGN bit */ 93 bool supports_sync_align:1; 94 95 bool has_writeback:1; 96 }; 97 98 #define DISPC_MAX_NR_FIFOS 5 99 100 static struct { 101 struct platform_device *pdev; 102 void __iomem *base; 103 104 int irq; 105 irq_handler_t user_handler; 106 void *user_data; 107 108 unsigned long core_clk_rate; 109 unsigned long tv_pclk_rate; 110 111 u32 fifo_size[DISPC_MAX_NR_FIFOS]; 112 /* maps which plane is using a fifo. fifo-id -> plane-id */ 113 int fifo_assignment[DISPC_MAX_NR_FIFOS]; 114 115 bool ctx_valid; 116 u32 ctx[DISPC_SZ_REGS / sizeof(u32)]; 117 118 const struct dispc_features *feat; 119 120 bool is_enabled; 121 122 struct regmap *syscon_pol; 123 u32 syscon_pol_offset; 124 125 /* DISPC_CONTROL & DISPC_CONFIG lock*/ 126 spinlock_t control_lock; 127 } dispc; 128 129 enum omap_color_component { 130 /* used for all color formats for OMAP3 and earlier 131 * and for RGB and Y color component on OMAP4 132 */ 133 DISPC_COLOR_COMPONENT_RGB_Y = 1 << 0, 134 /* used for UV component for 135 * OMAP_DSS_COLOR_YUV2, OMAP_DSS_COLOR_UYVY, OMAP_DSS_COLOR_NV12 136 * color formats on OMAP4 137 */ 138 DISPC_COLOR_COMPONENT_UV = 1 << 1, 139 }; 140 141 enum mgr_reg_fields { 142 DISPC_MGR_FLD_ENABLE, 143 DISPC_MGR_FLD_STNTFT, 144 DISPC_MGR_FLD_GO, 145 DISPC_MGR_FLD_TFTDATALINES, 146 DISPC_MGR_FLD_STALLMODE, 147 DISPC_MGR_FLD_TCKENABLE, 148 DISPC_MGR_FLD_TCKSELECTION, 149 DISPC_MGR_FLD_CPR, 150 DISPC_MGR_FLD_FIFOHANDCHECK, 151 /* used to maintain a count of the above fields */ 152 DISPC_MGR_FLD_NUM, 153 }; 154 155 struct dispc_reg_field { 156 u16 reg; 157 u8 high; 158 u8 low; 159 }; 160 161 static const struct { 162 const char *name; 163 u32 vsync_irq; 164 u32 framedone_irq; 165 u32 sync_lost_irq; 166 struct dispc_reg_field reg_desc[DISPC_MGR_FLD_NUM]; 167 } mgr_desc[] = { 168 [OMAP_DSS_CHANNEL_LCD] = { 169 .name = "LCD", 170 .vsync_irq = DISPC_IRQ_VSYNC, 171 .framedone_irq = DISPC_IRQ_FRAMEDONE, 172 .sync_lost_irq = DISPC_IRQ_SYNC_LOST, 173 .reg_desc = { 174 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 0, 0 }, 175 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL, 3, 3 }, 176 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 5, 5 }, 177 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL, 9, 8 }, 178 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL, 11, 11 }, 179 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG, 10, 10 }, 180 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG, 11, 11 }, 181 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG, 15, 15 }, 182 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG, 16, 16 }, 183 }, 184 }, 185 [OMAP_DSS_CHANNEL_DIGIT] = { 186 .name = "DIGIT", 187 .vsync_irq = DISPC_IRQ_EVSYNC_ODD | DISPC_IRQ_EVSYNC_EVEN, 188 .framedone_irq = DISPC_IRQ_FRAMEDONETV, 189 .sync_lost_irq = DISPC_IRQ_SYNC_LOST_DIGIT, 190 .reg_desc = { 191 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 1, 1 }, 192 [DISPC_MGR_FLD_STNTFT] = { }, 193 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 6, 6 }, 194 [DISPC_MGR_FLD_TFTDATALINES] = { }, 195 [DISPC_MGR_FLD_STALLMODE] = { }, 196 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG, 12, 12 }, 197 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG, 13, 13 }, 198 [DISPC_MGR_FLD_CPR] = { }, 199 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG, 16, 16 }, 200 }, 201 }, 202 [OMAP_DSS_CHANNEL_LCD2] = { 203 .name = "LCD2", 204 .vsync_irq = DISPC_IRQ_VSYNC2, 205 .framedone_irq = DISPC_IRQ_FRAMEDONE2, 206 .sync_lost_irq = DISPC_IRQ_SYNC_LOST2, 207 .reg_desc = { 208 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL2, 0, 0 }, 209 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL2, 3, 3 }, 210 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL2, 5, 5 }, 211 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL2, 9, 8 }, 212 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL2, 11, 11 }, 213 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG2, 10, 10 }, 214 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG2, 11, 11 }, 215 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG2, 15, 15 }, 216 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG2, 16, 16 }, 217 }, 218 }, 219 [OMAP_DSS_CHANNEL_LCD3] = { 220 .name = "LCD3", 221 .vsync_irq = DISPC_IRQ_VSYNC3, 222 .framedone_irq = DISPC_IRQ_FRAMEDONE3, 223 .sync_lost_irq = DISPC_IRQ_SYNC_LOST3, 224 .reg_desc = { 225 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL3, 0, 0 }, 226 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL3, 3, 3 }, 227 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL3, 5, 5 }, 228 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL3, 9, 8 }, 229 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL3, 11, 11 }, 230 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG3, 10, 10 }, 231 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG3, 11, 11 }, 232 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG3, 15, 15 }, 233 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG3, 16, 16 }, 234 }, 235 }, 236 }; 237 238 struct color_conv_coef { 239 int ry, rcr, rcb, gy, gcr, gcb, by, bcr, bcb; 240 int full_range; 241 }; 242 243 static unsigned long dispc_fclk_rate(void); 244 static unsigned long dispc_core_clk_rate(void); 245 static unsigned long dispc_mgr_lclk_rate(enum omap_channel channel); 246 static unsigned long dispc_mgr_pclk_rate(enum omap_channel channel); 247 248 static unsigned long dispc_plane_pclk_rate(enum omap_plane plane); 249 static unsigned long dispc_plane_lclk_rate(enum omap_plane plane); 250 251 static inline void dispc_write_reg(const u16 idx, u32 val) 252 { 253 __raw_writel(val, dispc.base + idx); 254 } 255 256 static inline u32 dispc_read_reg(const u16 idx) 257 { 258 return __raw_readl(dispc.base + idx); 259 } 260 261 static u32 mgr_fld_read(enum omap_channel channel, enum mgr_reg_fields regfld) 262 { 263 const struct dispc_reg_field rfld = mgr_desc[channel].reg_desc[regfld]; 264 return REG_GET(rfld.reg, rfld.high, rfld.low); 265 } 266 267 static void mgr_fld_write(enum omap_channel channel, 268 enum mgr_reg_fields regfld, int val) { 269 const struct dispc_reg_field rfld = mgr_desc[channel].reg_desc[regfld]; 270 const bool need_lock = rfld.reg == DISPC_CONTROL || rfld.reg == DISPC_CONFIG; 271 unsigned long flags; 272 273 if (need_lock) 274 spin_lock_irqsave(&dispc.control_lock, flags); 275 276 REG_FLD_MOD(rfld.reg, val, rfld.high, rfld.low); 277 278 if (need_lock) 279 spin_unlock_irqrestore(&dispc.control_lock, flags); 280 } 281 282 #define SR(reg) \ 283 dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg) 284 #define RR(reg) \ 285 dispc_write_reg(DISPC_##reg, dispc.ctx[DISPC_##reg / sizeof(u32)]) 286 287 static void dispc_save_context(void) 288 { 289 int i, j; 290 291 DSSDBG("dispc_save_context\n"); 292 293 SR(IRQENABLE); 294 SR(CONTROL); 295 SR(CONFIG); 296 SR(LINE_NUMBER); 297 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) || 298 dss_has_feature(FEAT_ALPHA_FREE_ZORDER)) 299 SR(GLOBAL_ALPHA); 300 if (dss_has_feature(FEAT_MGR_LCD2)) { 301 SR(CONTROL2); 302 SR(CONFIG2); 303 } 304 if (dss_has_feature(FEAT_MGR_LCD3)) { 305 SR(CONTROL3); 306 SR(CONFIG3); 307 } 308 309 for (i = 0; i < dss_feat_get_num_mgrs(); i++) { 310 SR(DEFAULT_COLOR(i)); 311 SR(TRANS_COLOR(i)); 312 SR(SIZE_MGR(i)); 313 if (i == OMAP_DSS_CHANNEL_DIGIT) 314 continue; 315 SR(TIMING_H(i)); 316 SR(TIMING_V(i)); 317 SR(POL_FREQ(i)); 318 SR(DIVISORo(i)); 319 320 SR(DATA_CYCLE1(i)); 321 SR(DATA_CYCLE2(i)); 322 SR(DATA_CYCLE3(i)); 323 324 if (dss_has_feature(FEAT_CPR)) { 325 SR(CPR_COEF_R(i)); 326 SR(CPR_COEF_G(i)); 327 SR(CPR_COEF_B(i)); 328 } 329 } 330 331 for (i = 0; i < dss_feat_get_num_ovls(); i++) { 332 SR(OVL_BA0(i)); 333 SR(OVL_BA1(i)); 334 SR(OVL_POSITION(i)); 335 SR(OVL_SIZE(i)); 336 SR(OVL_ATTRIBUTES(i)); 337 SR(OVL_FIFO_THRESHOLD(i)); 338 SR(OVL_ROW_INC(i)); 339 SR(OVL_PIXEL_INC(i)); 340 if (dss_has_feature(FEAT_PRELOAD)) 341 SR(OVL_PRELOAD(i)); 342 if (i == OMAP_DSS_GFX) { 343 SR(OVL_WINDOW_SKIP(i)); 344 SR(OVL_TABLE_BA(i)); 345 continue; 346 } 347 SR(OVL_FIR(i)); 348 SR(OVL_PICTURE_SIZE(i)); 349 SR(OVL_ACCU0(i)); 350 SR(OVL_ACCU1(i)); 351 352 for (j = 0; j < 8; j++) 353 SR(OVL_FIR_COEF_H(i, j)); 354 355 for (j = 0; j < 8; j++) 356 SR(OVL_FIR_COEF_HV(i, j)); 357 358 for (j = 0; j < 5; j++) 359 SR(OVL_CONV_COEF(i, j)); 360 361 if (dss_has_feature(FEAT_FIR_COEF_V)) { 362 for (j = 0; j < 8; j++) 363 SR(OVL_FIR_COEF_V(i, j)); 364 } 365 366 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) { 367 SR(OVL_BA0_UV(i)); 368 SR(OVL_BA1_UV(i)); 369 SR(OVL_FIR2(i)); 370 SR(OVL_ACCU2_0(i)); 371 SR(OVL_ACCU2_1(i)); 372 373 for (j = 0; j < 8; j++) 374 SR(OVL_FIR_COEF_H2(i, j)); 375 376 for (j = 0; j < 8; j++) 377 SR(OVL_FIR_COEF_HV2(i, j)); 378 379 for (j = 0; j < 8; j++) 380 SR(OVL_FIR_COEF_V2(i, j)); 381 } 382 if (dss_has_feature(FEAT_ATTR2)) 383 SR(OVL_ATTRIBUTES2(i)); 384 } 385 386 if (dss_has_feature(FEAT_CORE_CLK_DIV)) 387 SR(DIVISOR); 388 389 dispc.ctx_valid = true; 390 391 DSSDBG("context saved\n"); 392 } 393 394 static void dispc_restore_context(void) 395 { 396 int i, j; 397 398 DSSDBG("dispc_restore_context\n"); 399 400 if (!dispc.ctx_valid) 401 return; 402 403 /*RR(IRQENABLE);*/ 404 /*RR(CONTROL);*/ 405 RR(CONFIG); 406 RR(LINE_NUMBER); 407 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) || 408 dss_has_feature(FEAT_ALPHA_FREE_ZORDER)) 409 RR(GLOBAL_ALPHA); 410 if (dss_has_feature(FEAT_MGR_LCD2)) 411 RR(CONFIG2); 412 if (dss_has_feature(FEAT_MGR_LCD3)) 413 RR(CONFIG3); 414 415 for (i = 0; i < dss_feat_get_num_mgrs(); i++) { 416 RR(DEFAULT_COLOR(i)); 417 RR(TRANS_COLOR(i)); 418 RR(SIZE_MGR(i)); 419 if (i == OMAP_DSS_CHANNEL_DIGIT) 420 continue; 421 RR(TIMING_H(i)); 422 RR(TIMING_V(i)); 423 RR(POL_FREQ(i)); 424 RR(DIVISORo(i)); 425 426 RR(DATA_CYCLE1(i)); 427 RR(DATA_CYCLE2(i)); 428 RR(DATA_CYCLE3(i)); 429 430 if (dss_has_feature(FEAT_CPR)) { 431 RR(CPR_COEF_R(i)); 432 RR(CPR_COEF_G(i)); 433 RR(CPR_COEF_B(i)); 434 } 435 } 436 437 for (i = 0; i < dss_feat_get_num_ovls(); i++) { 438 RR(OVL_BA0(i)); 439 RR(OVL_BA1(i)); 440 RR(OVL_POSITION(i)); 441 RR(OVL_SIZE(i)); 442 RR(OVL_ATTRIBUTES(i)); 443 RR(OVL_FIFO_THRESHOLD(i)); 444 RR(OVL_ROW_INC(i)); 445 RR(OVL_PIXEL_INC(i)); 446 if (dss_has_feature(FEAT_PRELOAD)) 447 RR(OVL_PRELOAD(i)); 448 if (i == OMAP_DSS_GFX) { 449 RR(OVL_WINDOW_SKIP(i)); 450 RR(OVL_TABLE_BA(i)); 451 continue; 452 } 453 RR(OVL_FIR(i)); 454 RR(OVL_PICTURE_SIZE(i)); 455 RR(OVL_ACCU0(i)); 456 RR(OVL_ACCU1(i)); 457 458 for (j = 0; j < 8; j++) 459 RR(OVL_FIR_COEF_H(i, j)); 460 461 for (j = 0; j < 8; j++) 462 RR(OVL_FIR_COEF_HV(i, j)); 463 464 for (j = 0; j < 5; j++) 465 RR(OVL_CONV_COEF(i, j)); 466 467 if (dss_has_feature(FEAT_FIR_COEF_V)) { 468 for (j = 0; j < 8; j++) 469 RR(OVL_FIR_COEF_V(i, j)); 470 } 471 472 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) { 473 RR(OVL_BA0_UV(i)); 474 RR(OVL_BA1_UV(i)); 475 RR(OVL_FIR2(i)); 476 RR(OVL_ACCU2_0(i)); 477 RR(OVL_ACCU2_1(i)); 478 479 for (j = 0; j < 8; j++) 480 RR(OVL_FIR_COEF_H2(i, j)); 481 482 for (j = 0; j < 8; j++) 483 RR(OVL_FIR_COEF_HV2(i, j)); 484 485 for (j = 0; j < 8; j++) 486 RR(OVL_FIR_COEF_V2(i, j)); 487 } 488 if (dss_has_feature(FEAT_ATTR2)) 489 RR(OVL_ATTRIBUTES2(i)); 490 } 491 492 if (dss_has_feature(FEAT_CORE_CLK_DIV)) 493 RR(DIVISOR); 494 495 /* enable last, because LCD & DIGIT enable are here */ 496 RR(CONTROL); 497 if (dss_has_feature(FEAT_MGR_LCD2)) 498 RR(CONTROL2); 499 if (dss_has_feature(FEAT_MGR_LCD3)) 500 RR(CONTROL3); 501 /* clear spurious SYNC_LOST_DIGIT interrupts */ 502 dispc_clear_irqstatus(DISPC_IRQ_SYNC_LOST_DIGIT); 503 504 /* 505 * enable last so IRQs won't trigger before 506 * the context is fully restored 507 */ 508 RR(IRQENABLE); 509 510 DSSDBG("context restored\n"); 511 } 512 513 #undef SR 514 #undef RR 515 516 int dispc_runtime_get(void) 517 { 518 int r; 519 520 DSSDBG("dispc_runtime_get\n"); 521 522 r = pm_runtime_get_sync(&dispc.pdev->dev); 523 WARN_ON(r < 0); 524 return r < 0 ? r : 0; 525 } 526 EXPORT_SYMBOL(dispc_runtime_get); 527 528 void dispc_runtime_put(void) 529 { 530 int r; 531 532 DSSDBG("dispc_runtime_put\n"); 533 534 r = pm_runtime_put_sync(&dispc.pdev->dev); 535 WARN_ON(r < 0 && r != -ENOSYS); 536 } 537 EXPORT_SYMBOL(dispc_runtime_put); 538 539 u32 dispc_mgr_get_vsync_irq(enum omap_channel channel) 540 { 541 return mgr_desc[channel].vsync_irq; 542 } 543 EXPORT_SYMBOL(dispc_mgr_get_vsync_irq); 544 545 u32 dispc_mgr_get_framedone_irq(enum omap_channel channel) 546 { 547 if (channel == OMAP_DSS_CHANNEL_DIGIT && dispc.feat->no_framedone_tv) 548 return 0; 549 550 return mgr_desc[channel].framedone_irq; 551 } 552 EXPORT_SYMBOL(dispc_mgr_get_framedone_irq); 553 554 u32 dispc_mgr_get_sync_lost_irq(enum omap_channel channel) 555 { 556 return mgr_desc[channel].sync_lost_irq; 557 } 558 EXPORT_SYMBOL(dispc_mgr_get_sync_lost_irq); 559 560 bool dispc_mgr_go_busy(enum omap_channel channel) 561 { 562 return mgr_fld_read(channel, DISPC_MGR_FLD_GO) == 1; 563 } 564 EXPORT_SYMBOL(dispc_mgr_go_busy); 565 566 void dispc_mgr_go(enum omap_channel channel) 567 { 568 WARN_ON(!dispc_mgr_is_enabled(channel)); 569 WARN_ON(dispc_mgr_go_busy(channel)); 570 571 DSSDBG("GO %s\n", mgr_desc[channel].name); 572 573 mgr_fld_write(channel, DISPC_MGR_FLD_GO, 1); 574 } 575 EXPORT_SYMBOL(dispc_mgr_go); 576 577 static void dispc_ovl_write_firh_reg(enum omap_plane plane, int reg, u32 value) 578 { 579 dispc_write_reg(DISPC_OVL_FIR_COEF_H(plane, reg), value); 580 } 581 582 static void dispc_ovl_write_firhv_reg(enum omap_plane plane, int reg, u32 value) 583 { 584 dispc_write_reg(DISPC_OVL_FIR_COEF_HV(plane, reg), value); 585 } 586 587 static void dispc_ovl_write_firv_reg(enum omap_plane plane, int reg, u32 value) 588 { 589 dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane, reg), value); 590 } 591 592 static void dispc_ovl_write_firh2_reg(enum omap_plane plane, int reg, u32 value) 593 { 594 BUG_ON(plane == OMAP_DSS_GFX); 595 596 dispc_write_reg(DISPC_OVL_FIR_COEF_H2(plane, reg), value); 597 } 598 599 static void dispc_ovl_write_firhv2_reg(enum omap_plane plane, int reg, 600 u32 value) 601 { 602 BUG_ON(plane == OMAP_DSS_GFX); 603 604 dispc_write_reg(DISPC_OVL_FIR_COEF_HV2(plane, reg), value); 605 } 606 607 static void dispc_ovl_write_firv2_reg(enum omap_plane plane, int reg, u32 value) 608 { 609 BUG_ON(plane == OMAP_DSS_GFX); 610 611 dispc_write_reg(DISPC_OVL_FIR_COEF_V2(plane, reg), value); 612 } 613 614 static void dispc_ovl_set_scale_coef(enum omap_plane plane, int fir_hinc, 615 int fir_vinc, int five_taps, 616 enum omap_color_component color_comp) 617 { 618 const struct dispc_coef *h_coef, *v_coef; 619 int i; 620 621 h_coef = dispc_ovl_get_scale_coef(fir_hinc, true); 622 v_coef = dispc_ovl_get_scale_coef(fir_vinc, five_taps); 623 624 for (i = 0; i < 8; i++) { 625 u32 h, hv; 626 627 h = FLD_VAL(h_coef[i].hc0_vc00, 7, 0) 628 | FLD_VAL(h_coef[i].hc1_vc0, 15, 8) 629 | FLD_VAL(h_coef[i].hc2_vc1, 23, 16) 630 | FLD_VAL(h_coef[i].hc3_vc2, 31, 24); 631 hv = FLD_VAL(h_coef[i].hc4_vc22, 7, 0) 632 | FLD_VAL(v_coef[i].hc1_vc0, 15, 8) 633 | FLD_VAL(v_coef[i].hc2_vc1, 23, 16) 634 | FLD_VAL(v_coef[i].hc3_vc2, 31, 24); 635 636 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) { 637 dispc_ovl_write_firh_reg(plane, i, h); 638 dispc_ovl_write_firhv_reg(plane, i, hv); 639 } else { 640 dispc_ovl_write_firh2_reg(plane, i, h); 641 dispc_ovl_write_firhv2_reg(plane, i, hv); 642 } 643 644 } 645 646 if (five_taps) { 647 for (i = 0; i < 8; i++) { 648 u32 v; 649 v = FLD_VAL(v_coef[i].hc0_vc00, 7, 0) 650 | FLD_VAL(v_coef[i].hc4_vc22, 15, 8); 651 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) 652 dispc_ovl_write_firv_reg(plane, i, v); 653 else 654 dispc_ovl_write_firv2_reg(plane, i, v); 655 } 656 } 657 } 658 659 660 static void dispc_ovl_write_color_conv_coef(enum omap_plane plane, 661 const struct color_conv_coef *ct) 662 { 663 #define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0)) 664 665 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 0), CVAL(ct->rcr, ct->ry)); 666 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 1), CVAL(ct->gy, ct->rcb)); 667 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 2), CVAL(ct->gcb, ct->gcr)); 668 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 3), CVAL(ct->bcr, ct->by)); 669 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 4), CVAL(0, ct->bcb)); 670 671 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), ct->full_range, 11, 11); 672 673 #undef CVAL 674 } 675 676 static void dispc_setup_color_conv_coef(void) 677 { 678 int i; 679 int num_ovl = dss_feat_get_num_ovls(); 680 const struct color_conv_coef ctbl_bt601_5_ovl = { 681 /* YUV -> RGB */ 682 298, 409, 0, 298, -208, -100, 298, 0, 517, 0, 683 }; 684 const struct color_conv_coef ctbl_bt601_5_wb = { 685 /* RGB -> YUV */ 686 66, 129, 25, 112, -94, -18, -38, -74, 112, 0, 687 }; 688 689 for (i = 1; i < num_ovl; i++) 690 dispc_ovl_write_color_conv_coef(i, &ctbl_bt601_5_ovl); 691 692 if (dispc.feat->has_writeback) 693 dispc_ovl_write_color_conv_coef(OMAP_DSS_WB, &ctbl_bt601_5_wb); 694 } 695 696 static void dispc_ovl_set_ba0(enum omap_plane plane, u32 paddr) 697 { 698 dispc_write_reg(DISPC_OVL_BA0(plane), paddr); 699 } 700 701 static void dispc_ovl_set_ba1(enum omap_plane plane, u32 paddr) 702 { 703 dispc_write_reg(DISPC_OVL_BA1(plane), paddr); 704 } 705 706 static void dispc_ovl_set_ba0_uv(enum omap_plane plane, u32 paddr) 707 { 708 dispc_write_reg(DISPC_OVL_BA0_UV(plane), paddr); 709 } 710 711 static void dispc_ovl_set_ba1_uv(enum omap_plane plane, u32 paddr) 712 { 713 dispc_write_reg(DISPC_OVL_BA1_UV(plane), paddr); 714 } 715 716 static void dispc_ovl_set_pos(enum omap_plane plane, 717 enum omap_overlay_caps caps, int x, int y) 718 { 719 u32 val; 720 721 if ((caps & OMAP_DSS_OVL_CAP_POS) == 0) 722 return; 723 724 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0); 725 726 dispc_write_reg(DISPC_OVL_POSITION(plane), val); 727 } 728 729 static void dispc_ovl_set_input_size(enum omap_plane plane, int width, 730 int height) 731 { 732 u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0); 733 734 if (plane == OMAP_DSS_GFX || plane == OMAP_DSS_WB) 735 dispc_write_reg(DISPC_OVL_SIZE(plane), val); 736 else 737 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val); 738 } 739 740 static void dispc_ovl_set_output_size(enum omap_plane plane, int width, 741 int height) 742 { 743 u32 val; 744 745 BUG_ON(plane == OMAP_DSS_GFX); 746 747 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0); 748 749 if (plane == OMAP_DSS_WB) 750 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val); 751 else 752 dispc_write_reg(DISPC_OVL_SIZE(plane), val); 753 } 754 755 static void dispc_ovl_set_zorder(enum omap_plane plane, 756 enum omap_overlay_caps caps, u8 zorder) 757 { 758 if ((caps & OMAP_DSS_OVL_CAP_ZORDER) == 0) 759 return; 760 761 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), zorder, 27, 26); 762 } 763 764 static void dispc_ovl_enable_zorder_planes(void) 765 { 766 int i; 767 768 if (!dss_has_feature(FEAT_ALPHA_FREE_ZORDER)) 769 return; 770 771 for (i = 0; i < dss_feat_get_num_ovls(); i++) 772 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), 1, 25, 25); 773 } 774 775 static void dispc_ovl_set_pre_mult_alpha(enum omap_plane plane, 776 enum omap_overlay_caps caps, bool enable) 777 { 778 if ((caps & OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA) == 0) 779 return; 780 781 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28); 782 } 783 784 static void dispc_ovl_setup_global_alpha(enum omap_plane plane, 785 enum omap_overlay_caps caps, u8 global_alpha) 786 { 787 static const unsigned shifts[] = { 0, 8, 16, 24, }; 788 int shift; 789 790 if ((caps & OMAP_DSS_OVL_CAP_GLOBAL_ALPHA) == 0) 791 return; 792 793 shift = shifts[plane]; 794 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift); 795 } 796 797 static void dispc_ovl_set_pix_inc(enum omap_plane plane, s32 inc) 798 { 799 dispc_write_reg(DISPC_OVL_PIXEL_INC(plane), inc); 800 } 801 802 static void dispc_ovl_set_row_inc(enum omap_plane plane, s32 inc) 803 { 804 dispc_write_reg(DISPC_OVL_ROW_INC(plane), inc); 805 } 806 807 static void dispc_ovl_set_color_mode(enum omap_plane plane, 808 enum omap_color_mode color_mode) 809 { 810 u32 m = 0; 811 if (plane != OMAP_DSS_GFX) { 812 switch (color_mode) { 813 case OMAP_DSS_COLOR_NV12: 814 m = 0x0; break; 815 case OMAP_DSS_COLOR_RGBX16: 816 m = 0x1; break; 817 case OMAP_DSS_COLOR_RGBA16: 818 m = 0x2; break; 819 case OMAP_DSS_COLOR_RGB12U: 820 m = 0x4; break; 821 case OMAP_DSS_COLOR_ARGB16: 822 m = 0x5; break; 823 case OMAP_DSS_COLOR_RGB16: 824 m = 0x6; break; 825 case OMAP_DSS_COLOR_ARGB16_1555: 826 m = 0x7; break; 827 case OMAP_DSS_COLOR_RGB24U: 828 m = 0x8; break; 829 case OMAP_DSS_COLOR_RGB24P: 830 m = 0x9; break; 831 case OMAP_DSS_COLOR_YUV2: 832 m = 0xa; break; 833 case OMAP_DSS_COLOR_UYVY: 834 m = 0xb; break; 835 case OMAP_DSS_COLOR_ARGB32: 836 m = 0xc; break; 837 case OMAP_DSS_COLOR_RGBA32: 838 m = 0xd; break; 839 case OMAP_DSS_COLOR_RGBX32: 840 m = 0xe; break; 841 case OMAP_DSS_COLOR_XRGB16_1555: 842 m = 0xf; break; 843 default: 844 BUG(); return; 845 } 846 } else { 847 switch (color_mode) { 848 case OMAP_DSS_COLOR_CLUT1: 849 m = 0x0; break; 850 case OMAP_DSS_COLOR_CLUT2: 851 m = 0x1; break; 852 case OMAP_DSS_COLOR_CLUT4: 853 m = 0x2; break; 854 case OMAP_DSS_COLOR_CLUT8: 855 m = 0x3; break; 856 case OMAP_DSS_COLOR_RGB12U: 857 m = 0x4; break; 858 case OMAP_DSS_COLOR_ARGB16: 859 m = 0x5; break; 860 case OMAP_DSS_COLOR_RGB16: 861 m = 0x6; break; 862 case OMAP_DSS_COLOR_ARGB16_1555: 863 m = 0x7; break; 864 case OMAP_DSS_COLOR_RGB24U: 865 m = 0x8; break; 866 case OMAP_DSS_COLOR_RGB24P: 867 m = 0x9; break; 868 case OMAP_DSS_COLOR_RGBX16: 869 m = 0xa; break; 870 case OMAP_DSS_COLOR_RGBA16: 871 m = 0xb; break; 872 case OMAP_DSS_COLOR_ARGB32: 873 m = 0xc; break; 874 case OMAP_DSS_COLOR_RGBA32: 875 m = 0xd; break; 876 case OMAP_DSS_COLOR_RGBX32: 877 m = 0xe; break; 878 case OMAP_DSS_COLOR_XRGB16_1555: 879 m = 0xf; break; 880 default: 881 BUG(); return; 882 } 883 } 884 885 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1); 886 } 887 888 static void dispc_ovl_configure_burst_type(enum omap_plane plane, 889 enum omap_dss_rotation_type rotation_type) 890 { 891 if (dss_has_feature(FEAT_BURST_2D) == 0) 892 return; 893 894 if (rotation_type == OMAP_DSS_ROT_TILER) 895 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 1, 29, 29); 896 else 897 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 0, 29, 29); 898 } 899 900 void dispc_ovl_set_channel_out(enum omap_plane plane, enum omap_channel channel) 901 { 902 int shift; 903 u32 val; 904 int chan = 0, chan2 = 0; 905 906 switch (plane) { 907 case OMAP_DSS_GFX: 908 shift = 8; 909 break; 910 case OMAP_DSS_VIDEO1: 911 case OMAP_DSS_VIDEO2: 912 case OMAP_DSS_VIDEO3: 913 shift = 16; 914 break; 915 default: 916 BUG(); 917 return; 918 } 919 920 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane)); 921 if (dss_has_feature(FEAT_MGR_LCD2)) { 922 switch (channel) { 923 case OMAP_DSS_CHANNEL_LCD: 924 chan = 0; 925 chan2 = 0; 926 break; 927 case OMAP_DSS_CHANNEL_DIGIT: 928 chan = 1; 929 chan2 = 0; 930 break; 931 case OMAP_DSS_CHANNEL_LCD2: 932 chan = 0; 933 chan2 = 1; 934 break; 935 case OMAP_DSS_CHANNEL_LCD3: 936 if (dss_has_feature(FEAT_MGR_LCD3)) { 937 chan = 0; 938 chan2 = 2; 939 } else { 940 BUG(); 941 return; 942 } 943 break; 944 case OMAP_DSS_CHANNEL_WB: 945 chan = 0; 946 chan2 = 3; 947 break; 948 default: 949 BUG(); 950 return; 951 } 952 953 val = FLD_MOD(val, chan, shift, shift); 954 val = FLD_MOD(val, chan2, 31, 30); 955 } else { 956 val = FLD_MOD(val, channel, shift, shift); 957 } 958 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val); 959 } 960 EXPORT_SYMBOL(dispc_ovl_set_channel_out); 961 962 static enum omap_channel dispc_ovl_get_channel_out(enum omap_plane plane) 963 { 964 int shift; 965 u32 val; 966 967 switch (plane) { 968 case OMAP_DSS_GFX: 969 shift = 8; 970 break; 971 case OMAP_DSS_VIDEO1: 972 case OMAP_DSS_VIDEO2: 973 case OMAP_DSS_VIDEO3: 974 shift = 16; 975 break; 976 default: 977 BUG(); 978 return 0; 979 } 980 981 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane)); 982 983 if (FLD_GET(val, shift, shift) == 1) 984 return OMAP_DSS_CHANNEL_DIGIT; 985 986 if (!dss_has_feature(FEAT_MGR_LCD2)) 987 return OMAP_DSS_CHANNEL_LCD; 988 989 switch (FLD_GET(val, 31, 30)) { 990 case 0: 991 default: 992 return OMAP_DSS_CHANNEL_LCD; 993 case 1: 994 return OMAP_DSS_CHANNEL_LCD2; 995 case 2: 996 return OMAP_DSS_CHANNEL_LCD3; 997 case 3: 998 return OMAP_DSS_CHANNEL_WB; 999 } 1000 } 1001 1002 static void dispc_ovl_set_burst_size(enum omap_plane plane, 1003 enum omap_burst_size burst_size) 1004 { 1005 static const unsigned shifts[] = { 6, 14, 14, 14, 14, }; 1006 int shift; 1007 1008 shift = shifts[plane]; 1009 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), burst_size, shift + 1, shift); 1010 } 1011 1012 static void dispc_configure_burst_sizes(void) 1013 { 1014 int i; 1015 const int burst_size = BURST_SIZE_X8; 1016 1017 /* Configure burst size always to maximum size */ 1018 for (i = 0; i < dss_feat_get_num_ovls(); ++i) 1019 dispc_ovl_set_burst_size(i, burst_size); 1020 if (dispc.feat->has_writeback) 1021 dispc_ovl_set_burst_size(OMAP_DSS_WB, burst_size); 1022 } 1023 1024 static u32 dispc_ovl_get_burst_size(enum omap_plane plane) 1025 { 1026 unsigned unit = dss_feat_get_burst_size_unit(); 1027 /* burst multiplier is always x8 (see dispc_configure_burst_sizes()) */ 1028 return unit * 8; 1029 } 1030 1031 void dispc_enable_gamma_table(bool enable) 1032 { 1033 /* 1034 * This is partially implemented to support only disabling of 1035 * the gamma table. 1036 */ 1037 if (enable) { 1038 DSSWARN("Gamma table enabling for TV not yet supported"); 1039 return; 1040 } 1041 1042 REG_FLD_MOD(DISPC_CONFIG, enable, 9, 9); 1043 } 1044 1045 static void dispc_mgr_enable_cpr(enum omap_channel channel, bool enable) 1046 { 1047 if (channel == OMAP_DSS_CHANNEL_DIGIT) 1048 return; 1049 1050 mgr_fld_write(channel, DISPC_MGR_FLD_CPR, enable); 1051 } 1052 1053 static void dispc_mgr_set_cpr_coef(enum omap_channel channel, 1054 const struct omap_dss_cpr_coefs *coefs) 1055 { 1056 u32 coef_r, coef_g, coef_b; 1057 1058 if (!dss_mgr_is_lcd(channel)) 1059 return; 1060 1061 coef_r = FLD_VAL(coefs->rr, 31, 22) | FLD_VAL(coefs->rg, 20, 11) | 1062 FLD_VAL(coefs->rb, 9, 0); 1063 coef_g = FLD_VAL(coefs->gr, 31, 22) | FLD_VAL(coefs->gg, 20, 11) | 1064 FLD_VAL(coefs->gb, 9, 0); 1065 coef_b = FLD_VAL(coefs->br, 31, 22) | FLD_VAL(coefs->bg, 20, 11) | 1066 FLD_VAL(coefs->bb, 9, 0); 1067 1068 dispc_write_reg(DISPC_CPR_COEF_R(channel), coef_r); 1069 dispc_write_reg(DISPC_CPR_COEF_G(channel), coef_g); 1070 dispc_write_reg(DISPC_CPR_COEF_B(channel), coef_b); 1071 } 1072 1073 static void dispc_ovl_set_vid_color_conv(enum omap_plane plane, bool enable) 1074 { 1075 u32 val; 1076 1077 BUG_ON(plane == OMAP_DSS_GFX); 1078 1079 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane)); 1080 val = FLD_MOD(val, enable, 9, 9); 1081 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val); 1082 } 1083 1084 static void dispc_ovl_enable_replication(enum omap_plane plane, 1085 enum omap_overlay_caps caps, bool enable) 1086 { 1087 static const unsigned shifts[] = { 5, 10, 10, 10 }; 1088 int shift; 1089 1090 if ((caps & OMAP_DSS_OVL_CAP_REPLICATION) == 0) 1091 return; 1092 1093 shift = shifts[plane]; 1094 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, shift, shift); 1095 } 1096 1097 static void dispc_mgr_set_size(enum omap_channel channel, u16 width, 1098 u16 height) 1099 { 1100 u32 val; 1101 1102 val = FLD_VAL(height - 1, dispc.feat->mgr_height_start, 16) | 1103 FLD_VAL(width - 1, dispc.feat->mgr_width_start, 0); 1104 1105 dispc_write_reg(DISPC_SIZE_MGR(channel), val); 1106 } 1107 1108 static void dispc_init_fifos(void) 1109 { 1110 u32 size; 1111 int fifo; 1112 u8 start, end; 1113 u32 unit; 1114 int i; 1115 1116 unit = dss_feat_get_buffer_size_unit(); 1117 1118 dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end); 1119 1120 for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) { 1121 size = REG_GET(DISPC_OVL_FIFO_SIZE_STATUS(fifo), start, end); 1122 size *= unit; 1123 dispc.fifo_size[fifo] = size; 1124 1125 /* 1126 * By default fifos are mapped directly to overlays, fifo 0 to 1127 * ovl 0, fifo 1 to ovl 1, etc. 1128 */ 1129 dispc.fifo_assignment[fifo] = fifo; 1130 } 1131 1132 /* 1133 * The GFX fifo on OMAP4 is smaller than the other fifos. The small fifo 1134 * causes problems with certain use cases, like using the tiler in 2D 1135 * mode. The below hack swaps the fifos of GFX and WB planes, thus 1136 * giving GFX plane a larger fifo. WB but should work fine with a 1137 * smaller fifo. 1138 */ 1139 if (dispc.feat->gfx_fifo_workaround) { 1140 u32 v; 1141 1142 v = dispc_read_reg(DISPC_GLOBAL_BUFFER); 1143 1144 v = FLD_MOD(v, 4, 2, 0); /* GFX BUF top to WB */ 1145 v = FLD_MOD(v, 4, 5, 3); /* GFX BUF bottom to WB */ 1146 v = FLD_MOD(v, 0, 26, 24); /* WB BUF top to GFX */ 1147 v = FLD_MOD(v, 0, 29, 27); /* WB BUF bottom to GFX */ 1148 1149 dispc_write_reg(DISPC_GLOBAL_BUFFER, v); 1150 1151 dispc.fifo_assignment[OMAP_DSS_GFX] = OMAP_DSS_WB; 1152 dispc.fifo_assignment[OMAP_DSS_WB] = OMAP_DSS_GFX; 1153 } 1154 1155 /* 1156 * Setup default fifo thresholds. 1157 */ 1158 for (i = 0; i < dss_feat_get_num_ovls(); ++i) { 1159 u32 low, high; 1160 const bool use_fifomerge = false; 1161 const bool manual_update = false; 1162 1163 dispc_ovl_compute_fifo_thresholds(i, &low, &high, 1164 use_fifomerge, manual_update); 1165 1166 dispc_ovl_set_fifo_threshold(i, low, high); 1167 } 1168 1169 if (dispc.feat->has_writeback) { 1170 u32 low, high; 1171 const bool use_fifomerge = false; 1172 const bool manual_update = false; 1173 1174 dispc_ovl_compute_fifo_thresholds(OMAP_DSS_WB, &low, &high, 1175 use_fifomerge, manual_update); 1176 1177 dispc_ovl_set_fifo_threshold(OMAP_DSS_WB, low, high); 1178 } 1179 } 1180 1181 static u32 dispc_ovl_get_fifo_size(enum omap_plane plane) 1182 { 1183 int fifo; 1184 u32 size = 0; 1185 1186 for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) { 1187 if (dispc.fifo_assignment[fifo] == plane) 1188 size += dispc.fifo_size[fifo]; 1189 } 1190 1191 return size; 1192 } 1193 1194 void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high) 1195 { 1196 u8 hi_start, hi_end, lo_start, lo_end; 1197 u32 unit; 1198 1199 unit = dss_feat_get_buffer_size_unit(); 1200 1201 WARN_ON(low % unit != 0); 1202 WARN_ON(high % unit != 0); 1203 1204 low /= unit; 1205 high /= unit; 1206 1207 dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end); 1208 dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end); 1209 1210 DSSDBG("fifo(%d) threshold (bytes), old %u/%u, new %u/%u\n", 1211 plane, 1212 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane), 1213 lo_start, lo_end) * unit, 1214 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane), 1215 hi_start, hi_end) * unit, 1216 low * unit, high * unit); 1217 1218 dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD(plane), 1219 FLD_VAL(high, hi_start, hi_end) | 1220 FLD_VAL(low, lo_start, lo_end)); 1221 1222 /* 1223 * configure the preload to the pipeline's high threhold, if HT it's too 1224 * large for the preload field, set the threshold to the maximum value 1225 * that can be held by the preload register 1226 */ 1227 if (dss_has_feature(FEAT_PRELOAD) && dispc.feat->set_max_preload && 1228 plane != OMAP_DSS_WB) 1229 dispc_write_reg(DISPC_OVL_PRELOAD(plane), min(high, 0xfffu)); 1230 } 1231 1232 void dispc_enable_fifomerge(bool enable) 1233 { 1234 if (!dss_has_feature(FEAT_FIFO_MERGE)) { 1235 WARN_ON(enable); 1236 return; 1237 } 1238 1239 DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled"); 1240 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14); 1241 } 1242 1243 void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane, 1244 u32 *fifo_low, u32 *fifo_high, bool use_fifomerge, 1245 bool manual_update) 1246 { 1247 /* 1248 * All sizes are in bytes. Both the buffer and burst are made of 1249 * buffer_units, and the fifo thresholds must be buffer_unit aligned. 1250 */ 1251 1252 unsigned buf_unit = dss_feat_get_buffer_size_unit(); 1253 unsigned ovl_fifo_size, total_fifo_size, burst_size; 1254 int i; 1255 1256 burst_size = dispc_ovl_get_burst_size(plane); 1257 ovl_fifo_size = dispc_ovl_get_fifo_size(plane); 1258 1259 if (use_fifomerge) { 1260 total_fifo_size = 0; 1261 for (i = 0; i < dss_feat_get_num_ovls(); ++i) 1262 total_fifo_size += dispc_ovl_get_fifo_size(i); 1263 } else { 1264 total_fifo_size = ovl_fifo_size; 1265 } 1266 1267 /* 1268 * We use the same low threshold for both fifomerge and non-fifomerge 1269 * cases, but for fifomerge we calculate the high threshold using the 1270 * combined fifo size 1271 */ 1272 1273 if (manual_update && dss_has_feature(FEAT_OMAP3_DSI_FIFO_BUG)) { 1274 *fifo_low = ovl_fifo_size - burst_size * 2; 1275 *fifo_high = total_fifo_size - burst_size; 1276 } else if (plane == OMAP_DSS_WB) { 1277 /* 1278 * Most optimal configuration for writeback is to push out data 1279 * to the interconnect the moment writeback pushes enough pixels 1280 * in the FIFO to form a burst 1281 */ 1282 *fifo_low = 0; 1283 *fifo_high = burst_size; 1284 } else { 1285 *fifo_low = ovl_fifo_size - burst_size; 1286 *fifo_high = total_fifo_size - buf_unit; 1287 } 1288 } 1289 1290 static void dispc_ovl_set_mflag(enum omap_plane plane, bool enable) 1291 { 1292 int bit; 1293 1294 if (plane == OMAP_DSS_GFX) 1295 bit = 14; 1296 else 1297 bit = 23; 1298 1299 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, bit, bit); 1300 } 1301 1302 static void dispc_ovl_set_mflag_threshold(enum omap_plane plane, 1303 int low, int high) 1304 { 1305 dispc_write_reg(DISPC_OVL_MFLAG_THRESHOLD(plane), 1306 FLD_VAL(high, 31, 16) | FLD_VAL(low, 15, 0)); 1307 } 1308 1309 static void dispc_init_mflag(void) 1310 { 1311 int i; 1312 1313 /* 1314 * HACK: NV12 color format and MFLAG seem to have problems working 1315 * together: using two displays, and having an NV12 overlay on one of 1316 * the displays will cause underflows/synclosts when MFLAG_CTRL=2. 1317 * Changing MFLAG thresholds and PRELOAD to certain values seem to 1318 * remove the errors, but there doesn't seem to be a clear logic on 1319 * which values work and which not. 1320 * 1321 * As a work-around, set force MFLAG to always on. 1322 */ 1323 dispc_write_reg(DISPC_GLOBAL_MFLAG_ATTRIBUTE, 1324 (1 << 0) | /* MFLAG_CTRL = force always on */ 1325 (0 << 2)); /* MFLAG_START = disable */ 1326 1327 for (i = 0; i < dss_feat_get_num_ovls(); ++i) { 1328 u32 size = dispc_ovl_get_fifo_size(i); 1329 u32 unit = dss_feat_get_buffer_size_unit(); 1330 u32 low, high; 1331 1332 dispc_ovl_set_mflag(i, true); 1333 1334 /* 1335 * Simulation team suggests below thesholds: 1336 * HT = fifosize * 5 / 8; 1337 * LT = fifosize * 4 / 8; 1338 */ 1339 1340 low = size * 4 / 8 / unit; 1341 high = size * 5 / 8 / unit; 1342 1343 dispc_ovl_set_mflag_threshold(i, low, high); 1344 } 1345 1346 if (dispc.feat->has_writeback) { 1347 u32 size = dispc_ovl_get_fifo_size(OMAP_DSS_WB); 1348 u32 unit = dss_feat_get_buffer_size_unit(); 1349 u32 low, high; 1350 1351 dispc_ovl_set_mflag(OMAP_DSS_WB, true); 1352 1353 /* 1354 * Simulation team suggests below thesholds: 1355 * HT = fifosize * 5 / 8; 1356 * LT = fifosize * 4 / 8; 1357 */ 1358 1359 low = size * 4 / 8 / unit; 1360 high = size * 5 / 8 / unit; 1361 1362 dispc_ovl_set_mflag_threshold(OMAP_DSS_WB, low, high); 1363 } 1364 } 1365 1366 static void dispc_ovl_set_fir(enum omap_plane plane, 1367 int hinc, int vinc, 1368 enum omap_color_component color_comp) 1369 { 1370 u32 val; 1371 1372 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) { 1373 u8 hinc_start, hinc_end, vinc_start, vinc_end; 1374 1375 dss_feat_get_reg_field(FEAT_REG_FIRHINC, 1376 &hinc_start, &hinc_end); 1377 dss_feat_get_reg_field(FEAT_REG_FIRVINC, 1378 &vinc_start, &vinc_end); 1379 val = FLD_VAL(vinc, vinc_start, vinc_end) | 1380 FLD_VAL(hinc, hinc_start, hinc_end); 1381 1382 dispc_write_reg(DISPC_OVL_FIR(plane), val); 1383 } else { 1384 val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0); 1385 dispc_write_reg(DISPC_OVL_FIR2(plane), val); 1386 } 1387 } 1388 1389 static void dispc_ovl_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu) 1390 { 1391 u32 val; 1392 u8 hor_start, hor_end, vert_start, vert_end; 1393 1394 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end); 1395 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end); 1396 1397 val = FLD_VAL(vaccu, vert_start, vert_end) | 1398 FLD_VAL(haccu, hor_start, hor_end); 1399 1400 dispc_write_reg(DISPC_OVL_ACCU0(plane), val); 1401 } 1402 1403 static void dispc_ovl_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu) 1404 { 1405 u32 val; 1406 u8 hor_start, hor_end, vert_start, vert_end; 1407 1408 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end); 1409 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end); 1410 1411 val = FLD_VAL(vaccu, vert_start, vert_end) | 1412 FLD_VAL(haccu, hor_start, hor_end); 1413 1414 dispc_write_reg(DISPC_OVL_ACCU1(plane), val); 1415 } 1416 1417 static void dispc_ovl_set_vid_accu2_0(enum omap_plane plane, int haccu, 1418 int vaccu) 1419 { 1420 u32 val; 1421 1422 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0); 1423 dispc_write_reg(DISPC_OVL_ACCU2_0(plane), val); 1424 } 1425 1426 static void dispc_ovl_set_vid_accu2_1(enum omap_plane plane, int haccu, 1427 int vaccu) 1428 { 1429 u32 val; 1430 1431 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0); 1432 dispc_write_reg(DISPC_OVL_ACCU2_1(plane), val); 1433 } 1434 1435 static void dispc_ovl_set_scale_param(enum omap_plane plane, 1436 u16 orig_width, u16 orig_height, 1437 u16 out_width, u16 out_height, 1438 bool five_taps, u8 rotation, 1439 enum omap_color_component color_comp) 1440 { 1441 int fir_hinc, fir_vinc; 1442 1443 fir_hinc = 1024 * orig_width / out_width; 1444 fir_vinc = 1024 * orig_height / out_height; 1445 1446 dispc_ovl_set_scale_coef(plane, fir_hinc, fir_vinc, five_taps, 1447 color_comp); 1448 dispc_ovl_set_fir(plane, fir_hinc, fir_vinc, color_comp); 1449 } 1450 1451 static void dispc_ovl_set_accu_uv(enum omap_plane plane, 1452 u16 orig_width, u16 orig_height, u16 out_width, u16 out_height, 1453 bool ilace, enum omap_color_mode color_mode, u8 rotation) 1454 { 1455 int h_accu2_0, h_accu2_1; 1456 int v_accu2_0, v_accu2_1; 1457 int chroma_hinc, chroma_vinc; 1458 int idx; 1459 1460 struct accu { 1461 s8 h0_m, h0_n; 1462 s8 h1_m, h1_n; 1463 s8 v0_m, v0_n; 1464 s8 v1_m, v1_n; 1465 }; 1466 1467 const struct accu *accu_table; 1468 const struct accu *accu_val; 1469 1470 static const struct accu accu_nv12[4] = { 1471 { 0, 1, 0, 1 , -1, 2, 0, 1 }, 1472 { 1, 2, -3, 4 , 0, 1, 0, 1 }, 1473 { -1, 1, 0, 1 , -1, 2, 0, 1 }, 1474 { -1, 2, -1, 2 , -1, 1, 0, 1 }, 1475 }; 1476 1477 static const struct accu accu_nv12_ilace[4] = { 1478 { 0, 1, 0, 1 , -3, 4, -1, 4 }, 1479 { -1, 4, -3, 4 , 0, 1, 0, 1 }, 1480 { -1, 1, 0, 1 , -1, 4, -3, 4 }, 1481 { -3, 4, -3, 4 , -1, 1, 0, 1 }, 1482 }; 1483 1484 static const struct accu accu_yuv[4] = { 1485 { 0, 1, 0, 1, 0, 1, 0, 1 }, 1486 { 0, 1, 0, 1, 0, 1, 0, 1 }, 1487 { -1, 1, 0, 1, 0, 1, 0, 1 }, 1488 { 0, 1, 0, 1, -1, 1, 0, 1 }, 1489 }; 1490 1491 switch (rotation) { 1492 case OMAP_DSS_ROT_0: 1493 idx = 0; 1494 break; 1495 case OMAP_DSS_ROT_90: 1496 idx = 1; 1497 break; 1498 case OMAP_DSS_ROT_180: 1499 idx = 2; 1500 break; 1501 case OMAP_DSS_ROT_270: 1502 idx = 3; 1503 break; 1504 default: 1505 BUG(); 1506 return; 1507 } 1508 1509 switch (color_mode) { 1510 case OMAP_DSS_COLOR_NV12: 1511 if (ilace) 1512 accu_table = accu_nv12_ilace; 1513 else 1514 accu_table = accu_nv12; 1515 break; 1516 case OMAP_DSS_COLOR_YUV2: 1517 case OMAP_DSS_COLOR_UYVY: 1518 accu_table = accu_yuv; 1519 break; 1520 default: 1521 BUG(); 1522 return; 1523 } 1524 1525 accu_val = &accu_table[idx]; 1526 1527 chroma_hinc = 1024 * orig_width / out_width; 1528 chroma_vinc = 1024 * orig_height / out_height; 1529 1530 h_accu2_0 = (accu_val->h0_m * chroma_hinc / accu_val->h0_n) % 1024; 1531 h_accu2_1 = (accu_val->h1_m * chroma_hinc / accu_val->h1_n) % 1024; 1532 v_accu2_0 = (accu_val->v0_m * chroma_vinc / accu_val->v0_n) % 1024; 1533 v_accu2_1 = (accu_val->v1_m * chroma_vinc / accu_val->v1_n) % 1024; 1534 1535 dispc_ovl_set_vid_accu2_0(plane, h_accu2_0, v_accu2_0); 1536 dispc_ovl_set_vid_accu2_1(plane, h_accu2_1, v_accu2_1); 1537 } 1538 1539 static void dispc_ovl_set_scaling_common(enum omap_plane plane, 1540 u16 orig_width, u16 orig_height, 1541 u16 out_width, u16 out_height, 1542 bool ilace, bool five_taps, 1543 bool fieldmode, enum omap_color_mode color_mode, 1544 u8 rotation) 1545 { 1546 int accu0 = 0; 1547 int accu1 = 0; 1548 u32 l; 1549 1550 dispc_ovl_set_scale_param(plane, orig_width, orig_height, 1551 out_width, out_height, five_taps, 1552 rotation, DISPC_COLOR_COMPONENT_RGB_Y); 1553 l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane)); 1554 1555 /* RESIZEENABLE and VERTICALTAPS */ 1556 l &= ~((0x3 << 5) | (0x1 << 21)); 1557 l |= (orig_width != out_width) ? (1 << 5) : 0; 1558 l |= (orig_height != out_height) ? (1 << 6) : 0; 1559 l |= five_taps ? (1 << 21) : 0; 1560 1561 /* VRESIZECONF and HRESIZECONF */ 1562 if (dss_has_feature(FEAT_RESIZECONF)) { 1563 l &= ~(0x3 << 7); 1564 l |= (orig_width <= out_width) ? 0 : (1 << 7); 1565 l |= (orig_height <= out_height) ? 0 : (1 << 8); 1566 } 1567 1568 /* LINEBUFFERSPLIT */ 1569 if (dss_has_feature(FEAT_LINEBUFFERSPLIT)) { 1570 l &= ~(0x1 << 22); 1571 l |= five_taps ? (1 << 22) : 0; 1572 } 1573 1574 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l); 1575 1576 /* 1577 * field 0 = even field = bottom field 1578 * field 1 = odd field = top field 1579 */ 1580 if (ilace && !fieldmode) { 1581 accu1 = 0; 1582 accu0 = ((1024 * orig_height / out_height) / 2) & 0x3ff; 1583 if (accu0 >= 1024/2) { 1584 accu1 = 1024/2; 1585 accu0 -= accu1; 1586 } 1587 } 1588 1589 dispc_ovl_set_vid_accu0(plane, 0, accu0); 1590 dispc_ovl_set_vid_accu1(plane, 0, accu1); 1591 } 1592 1593 static void dispc_ovl_set_scaling_uv(enum omap_plane plane, 1594 u16 orig_width, u16 orig_height, 1595 u16 out_width, u16 out_height, 1596 bool ilace, bool five_taps, 1597 bool fieldmode, enum omap_color_mode color_mode, 1598 u8 rotation) 1599 { 1600 int scale_x = out_width != orig_width; 1601 int scale_y = out_height != orig_height; 1602 bool chroma_upscale = plane != OMAP_DSS_WB; 1603 1604 if (!dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) 1605 return; 1606 if ((color_mode != OMAP_DSS_COLOR_YUV2 && 1607 color_mode != OMAP_DSS_COLOR_UYVY && 1608 color_mode != OMAP_DSS_COLOR_NV12)) { 1609 /* reset chroma resampling for RGB formats */ 1610 if (plane != OMAP_DSS_WB) 1611 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 8, 8); 1612 return; 1613 } 1614 1615 dispc_ovl_set_accu_uv(plane, orig_width, orig_height, out_width, 1616 out_height, ilace, color_mode, rotation); 1617 1618 switch (color_mode) { 1619 case OMAP_DSS_COLOR_NV12: 1620 if (chroma_upscale) { 1621 /* UV is subsampled by 2 horizontally and vertically */ 1622 orig_height >>= 1; 1623 orig_width >>= 1; 1624 } else { 1625 /* UV is downsampled by 2 horizontally and vertically */ 1626 orig_height <<= 1; 1627 orig_width <<= 1; 1628 } 1629 1630 break; 1631 case OMAP_DSS_COLOR_YUV2: 1632 case OMAP_DSS_COLOR_UYVY: 1633 /* For YUV422 with 90/270 rotation, we don't upsample chroma */ 1634 if (rotation == OMAP_DSS_ROT_0 || 1635 rotation == OMAP_DSS_ROT_180) { 1636 if (chroma_upscale) 1637 /* UV is subsampled by 2 horizontally */ 1638 orig_width >>= 1; 1639 else 1640 /* UV is downsampled by 2 horizontally */ 1641 orig_width <<= 1; 1642 } 1643 1644 /* must use FIR for YUV422 if rotated */ 1645 if (rotation != OMAP_DSS_ROT_0) 1646 scale_x = scale_y = true; 1647 1648 break; 1649 default: 1650 BUG(); 1651 return; 1652 } 1653 1654 if (out_width != orig_width) 1655 scale_x = true; 1656 if (out_height != orig_height) 1657 scale_y = true; 1658 1659 dispc_ovl_set_scale_param(plane, orig_width, orig_height, 1660 out_width, out_height, five_taps, 1661 rotation, DISPC_COLOR_COMPONENT_UV); 1662 1663 if (plane != OMAP_DSS_WB) 1664 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 1665 (scale_x || scale_y) ? 1 : 0, 8, 8); 1666 1667 /* set H scaling */ 1668 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5); 1669 /* set V scaling */ 1670 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6); 1671 } 1672 1673 static void dispc_ovl_set_scaling(enum omap_plane plane, 1674 u16 orig_width, u16 orig_height, 1675 u16 out_width, u16 out_height, 1676 bool ilace, bool five_taps, 1677 bool fieldmode, enum omap_color_mode color_mode, 1678 u8 rotation) 1679 { 1680 BUG_ON(plane == OMAP_DSS_GFX); 1681 1682 dispc_ovl_set_scaling_common(plane, 1683 orig_width, orig_height, 1684 out_width, out_height, 1685 ilace, five_taps, 1686 fieldmode, color_mode, 1687 rotation); 1688 1689 dispc_ovl_set_scaling_uv(plane, 1690 orig_width, orig_height, 1691 out_width, out_height, 1692 ilace, five_taps, 1693 fieldmode, color_mode, 1694 rotation); 1695 } 1696 1697 static void dispc_ovl_set_rotation_attrs(enum omap_plane plane, u8 rotation, 1698 enum omap_dss_rotation_type rotation_type, 1699 bool mirroring, enum omap_color_mode color_mode) 1700 { 1701 bool row_repeat = false; 1702 int vidrot = 0; 1703 1704 if (color_mode == OMAP_DSS_COLOR_YUV2 || 1705 color_mode == OMAP_DSS_COLOR_UYVY) { 1706 1707 if (mirroring) { 1708 switch (rotation) { 1709 case OMAP_DSS_ROT_0: 1710 vidrot = 2; 1711 break; 1712 case OMAP_DSS_ROT_90: 1713 vidrot = 1; 1714 break; 1715 case OMAP_DSS_ROT_180: 1716 vidrot = 0; 1717 break; 1718 case OMAP_DSS_ROT_270: 1719 vidrot = 3; 1720 break; 1721 } 1722 } else { 1723 switch (rotation) { 1724 case OMAP_DSS_ROT_0: 1725 vidrot = 0; 1726 break; 1727 case OMAP_DSS_ROT_90: 1728 vidrot = 1; 1729 break; 1730 case OMAP_DSS_ROT_180: 1731 vidrot = 2; 1732 break; 1733 case OMAP_DSS_ROT_270: 1734 vidrot = 3; 1735 break; 1736 } 1737 } 1738 1739 if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270) 1740 row_repeat = true; 1741 else 1742 row_repeat = false; 1743 } 1744 1745 /* 1746 * OMAP4/5 Errata i631: 1747 * NV12 in 1D mode must use ROTATION=1. Otherwise DSS will fetch extra 1748 * rows beyond the framebuffer, which may cause OCP error. 1749 */ 1750 if (color_mode == OMAP_DSS_COLOR_NV12 && 1751 rotation_type != OMAP_DSS_ROT_TILER) 1752 vidrot = 1; 1753 1754 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12); 1755 if (dss_has_feature(FEAT_ROWREPEATENABLE)) 1756 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 1757 row_repeat ? 1 : 0, 18, 18); 1758 1759 if (color_mode == OMAP_DSS_COLOR_NV12) { 1760 bool doublestride = (rotation_type == OMAP_DSS_ROT_TILER) && 1761 (rotation == OMAP_DSS_ROT_0 || 1762 rotation == OMAP_DSS_ROT_180); 1763 /* DOUBLESTRIDE */ 1764 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), doublestride, 22, 22); 1765 } 1766 1767 } 1768 1769 static int color_mode_to_bpp(enum omap_color_mode color_mode) 1770 { 1771 switch (color_mode) { 1772 case OMAP_DSS_COLOR_CLUT1: 1773 return 1; 1774 case OMAP_DSS_COLOR_CLUT2: 1775 return 2; 1776 case OMAP_DSS_COLOR_CLUT4: 1777 return 4; 1778 case OMAP_DSS_COLOR_CLUT8: 1779 case OMAP_DSS_COLOR_NV12: 1780 return 8; 1781 case OMAP_DSS_COLOR_RGB12U: 1782 case OMAP_DSS_COLOR_RGB16: 1783 case OMAP_DSS_COLOR_ARGB16: 1784 case OMAP_DSS_COLOR_YUV2: 1785 case OMAP_DSS_COLOR_UYVY: 1786 case OMAP_DSS_COLOR_RGBA16: 1787 case OMAP_DSS_COLOR_RGBX16: 1788 case OMAP_DSS_COLOR_ARGB16_1555: 1789 case OMAP_DSS_COLOR_XRGB16_1555: 1790 return 16; 1791 case OMAP_DSS_COLOR_RGB24P: 1792 return 24; 1793 case OMAP_DSS_COLOR_RGB24U: 1794 case OMAP_DSS_COLOR_ARGB32: 1795 case OMAP_DSS_COLOR_RGBA32: 1796 case OMAP_DSS_COLOR_RGBX32: 1797 return 32; 1798 default: 1799 BUG(); 1800 return 0; 1801 } 1802 } 1803 1804 static s32 pixinc(int pixels, u8 ps) 1805 { 1806 if (pixels == 1) 1807 return 1; 1808 else if (pixels > 1) 1809 return 1 + (pixels - 1) * ps; 1810 else if (pixels < 0) 1811 return 1 - (-pixels + 1) * ps; 1812 else 1813 BUG(); 1814 return 0; 1815 } 1816 1817 static void calc_vrfb_rotation_offset(u8 rotation, bool mirror, 1818 u16 screen_width, 1819 u16 width, u16 height, 1820 enum omap_color_mode color_mode, bool fieldmode, 1821 unsigned int field_offset, 1822 unsigned *offset0, unsigned *offset1, 1823 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim) 1824 { 1825 u8 ps; 1826 1827 /* FIXME CLUT formats */ 1828 switch (color_mode) { 1829 case OMAP_DSS_COLOR_CLUT1: 1830 case OMAP_DSS_COLOR_CLUT2: 1831 case OMAP_DSS_COLOR_CLUT4: 1832 case OMAP_DSS_COLOR_CLUT8: 1833 BUG(); 1834 return; 1835 case OMAP_DSS_COLOR_YUV2: 1836 case OMAP_DSS_COLOR_UYVY: 1837 ps = 4; 1838 break; 1839 default: 1840 ps = color_mode_to_bpp(color_mode) / 8; 1841 break; 1842 } 1843 1844 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width, 1845 width, height); 1846 1847 /* 1848 * field 0 = even field = bottom field 1849 * field 1 = odd field = top field 1850 */ 1851 switch (rotation + mirror * 4) { 1852 case OMAP_DSS_ROT_0: 1853 case OMAP_DSS_ROT_180: 1854 /* 1855 * If the pixel format is YUV or UYVY divide the width 1856 * of the image by 2 for 0 and 180 degree rotation. 1857 */ 1858 if (color_mode == OMAP_DSS_COLOR_YUV2 || 1859 color_mode == OMAP_DSS_COLOR_UYVY) 1860 width = width >> 1; 1861 /* fall through */ 1862 case OMAP_DSS_ROT_90: 1863 case OMAP_DSS_ROT_270: 1864 *offset1 = 0; 1865 if (field_offset) 1866 *offset0 = field_offset * screen_width * ps; 1867 else 1868 *offset0 = 0; 1869 1870 *row_inc = pixinc(1 + 1871 (y_predecim * screen_width - x_predecim * width) + 1872 (fieldmode ? screen_width : 0), ps); 1873 *pix_inc = pixinc(x_predecim, ps); 1874 break; 1875 1876 case OMAP_DSS_ROT_0 + 4: 1877 case OMAP_DSS_ROT_180 + 4: 1878 /* If the pixel format is YUV or UYVY divide the width 1879 * of the image by 2 for 0 degree and 180 degree 1880 */ 1881 if (color_mode == OMAP_DSS_COLOR_YUV2 || 1882 color_mode == OMAP_DSS_COLOR_UYVY) 1883 width = width >> 1; 1884 /* fall through */ 1885 case OMAP_DSS_ROT_90 + 4: 1886 case OMAP_DSS_ROT_270 + 4: 1887 *offset1 = 0; 1888 if (field_offset) 1889 *offset0 = field_offset * screen_width * ps; 1890 else 1891 *offset0 = 0; 1892 *row_inc = pixinc(1 - 1893 (y_predecim * screen_width + x_predecim * width) - 1894 (fieldmode ? screen_width : 0), ps); 1895 *pix_inc = pixinc(x_predecim, ps); 1896 break; 1897 1898 default: 1899 BUG(); 1900 return; 1901 } 1902 } 1903 1904 static void calc_dma_rotation_offset(u8 rotation, bool mirror, 1905 u16 screen_width, 1906 u16 width, u16 height, 1907 enum omap_color_mode color_mode, bool fieldmode, 1908 unsigned int field_offset, 1909 unsigned *offset0, unsigned *offset1, 1910 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim) 1911 { 1912 u8 ps; 1913 u16 fbw, fbh; 1914 1915 /* FIXME CLUT formats */ 1916 switch (color_mode) { 1917 case OMAP_DSS_COLOR_CLUT1: 1918 case OMAP_DSS_COLOR_CLUT2: 1919 case OMAP_DSS_COLOR_CLUT4: 1920 case OMAP_DSS_COLOR_CLUT8: 1921 BUG(); 1922 return; 1923 default: 1924 ps = color_mode_to_bpp(color_mode) / 8; 1925 break; 1926 } 1927 1928 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width, 1929 width, height); 1930 1931 /* width & height are overlay sizes, convert to fb sizes */ 1932 1933 if (rotation == OMAP_DSS_ROT_0 || rotation == OMAP_DSS_ROT_180) { 1934 fbw = width; 1935 fbh = height; 1936 } else { 1937 fbw = height; 1938 fbh = width; 1939 } 1940 1941 /* 1942 * field 0 = even field = bottom field 1943 * field 1 = odd field = top field 1944 */ 1945 switch (rotation + mirror * 4) { 1946 case OMAP_DSS_ROT_0: 1947 *offset1 = 0; 1948 if (field_offset) 1949 *offset0 = *offset1 + field_offset * screen_width * ps; 1950 else 1951 *offset0 = *offset1; 1952 *row_inc = pixinc(1 + 1953 (y_predecim * screen_width - fbw * x_predecim) + 1954 (fieldmode ? screen_width : 0), ps); 1955 if (color_mode == OMAP_DSS_COLOR_YUV2 || 1956 color_mode == OMAP_DSS_COLOR_UYVY) 1957 *pix_inc = pixinc(x_predecim, 2 * ps); 1958 else 1959 *pix_inc = pixinc(x_predecim, ps); 1960 break; 1961 case OMAP_DSS_ROT_90: 1962 *offset1 = screen_width * (fbh - 1) * ps; 1963 if (field_offset) 1964 *offset0 = *offset1 + field_offset * ps; 1965 else 1966 *offset0 = *offset1; 1967 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) + 1968 y_predecim + (fieldmode ? 1 : 0), ps); 1969 *pix_inc = pixinc(-x_predecim * screen_width, ps); 1970 break; 1971 case OMAP_DSS_ROT_180: 1972 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps; 1973 if (field_offset) 1974 *offset0 = *offset1 - field_offset * screen_width * ps; 1975 else 1976 *offset0 = *offset1; 1977 *row_inc = pixinc(-1 - 1978 (y_predecim * screen_width - fbw * x_predecim) - 1979 (fieldmode ? screen_width : 0), ps); 1980 if (color_mode == OMAP_DSS_COLOR_YUV2 || 1981 color_mode == OMAP_DSS_COLOR_UYVY) 1982 *pix_inc = pixinc(-x_predecim, 2 * ps); 1983 else 1984 *pix_inc = pixinc(-x_predecim, ps); 1985 break; 1986 case OMAP_DSS_ROT_270: 1987 *offset1 = (fbw - 1) * ps; 1988 if (field_offset) 1989 *offset0 = *offset1 - field_offset * ps; 1990 else 1991 *offset0 = *offset1; 1992 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) - 1993 y_predecim - (fieldmode ? 1 : 0), ps); 1994 *pix_inc = pixinc(x_predecim * screen_width, ps); 1995 break; 1996 1997 /* mirroring */ 1998 case OMAP_DSS_ROT_0 + 4: 1999 *offset1 = (fbw - 1) * ps; 2000 if (field_offset) 2001 *offset0 = *offset1 + field_offset * screen_width * ps; 2002 else 2003 *offset0 = *offset1; 2004 *row_inc = pixinc(y_predecim * screen_width * 2 - 1 + 2005 (fieldmode ? screen_width : 0), 2006 ps); 2007 if (color_mode == OMAP_DSS_COLOR_YUV2 || 2008 color_mode == OMAP_DSS_COLOR_UYVY) 2009 *pix_inc = pixinc(-x_predecim, 2 * ps); 2010 else 2011 *pix_inc = pixinc(-x_predecim, ps); 2012 break; 2013 2014 case OMAP_DSS_ROT_90 + 4: 2015 *offset1 = 0; 2016 if (field_offset) 2017 *offset0 = *offset1 + field_offset * ps; 2018 else 2019 *offset0 = *offset1; 2020 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) + 2021 y_predecim + (fieldmode ? 1 : 0), 2022 ps); 2023 *pix_inc = pixinc(x_predecim * screen_width, ps); 2024 break; 2025 2026 case OMAP_DSS_ROT_180 + 4: 2027 *offset1 = screen_width * (fbh - 1) * ps; 2028 if (field_offset) 2029 *offset0 = *offset1 - field_offset * screen_width * ps; 2030 else 2031 *offset0 = *offset1; 2032 *row_inc = pixinc(1 - y_predecim * screen_width * 2 - 2033 (fieldmode ? screen_width : 0), 2034 ps); 2035 if (color_mode == OMAP_DSS_COLOR_YUV2 || 2036 color_mode == OMAP_DSS_COLOR_UYVY) 2037 *pix_inc = pixinc(x_predecim, 2 * ps); 2038 else 2039 *pix_inc = pixinc(x_predecim, ps); 2040 break; 2041 2042 case OMAP_DSS_ROT_270 + 4: 2043 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps; 2044 if (field_offset) 2045 *offset0 = *offset1 - field_offset * ps; 2046 else 2047 *offset0 = *offset1; 2048 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) - 2049 y_predecim - (fieldmode ? 1 : 0), 2050 ps); 2051 *pix_inc = pixinc(-x_predecim * screen_width, ps); 2052 break; 2053 2054 default: 2055 BUG(); 2056 return; 2057 } 2058 } 2059 2060 static void calc_tiler_rotation_offset(u16 screen_width, u16 width, 2061 enum omap_color_mode color_mode, bool fieldmode, 2062 unsigned int field_offset, unsigned *offset0, unsigned *offset1, 2063 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim) 2064 { 2065 u8 ps; 2066 2067 switch (color_mode) { 2068 case OMAP_DSS_COLOR_CLUT1: 2069 case OMAP_DSS_COLOR_CLUT2: 2070 case OMAP_DSS_COLOR_CLUT4: 2071 case OMAP_DSS_COLOR_CLUT8: 2072 BUG(); 2073 return; 2074 default: 2075 ps = color_mode_to_bpp(color_mode) / 8; 2076 break; 2077 } 2078 2079 DSSDBG("scrw %d, width %d\n", screen_width, width); 2080 2081 /* 2082 * field 0 = even field = bottom field 2083 * field 1 = odd field = top field 2084 */ 2085 *offset1 = 0; 2086 if (field_offset) 2087 *offset0 = *offset1 + field_offset * screen_width * ps; 2088 else 2089 *offset0 = *offset1; 2090 *row_inc = pixinc(1 + (y_predecim * screen_width - width * x_predecim) + 2091 (fieldmode ? screen_width : 0), ps); 2092 if (color_mode == OMAP_DSS_COLOR_YUV2 || 2093 color_mode == OMAP_DSS_COLOR_UYVY) 2094 *pix_inc = pixinc(x_predecim, 2 * ps); 2095 else 2096 *pix_inc = pixinc(x_predecim, ps); 2097 } 2098 2099 /* 2100 * This function is used to avoid synclosts in OMAP3, because of some 2101 * undocumented horizontal position and timing related limitations. 2102 */ 2103 static int check_horiz_timing_omap3(unsigned long pclk, unsigned long lclk, 2104 const struct omap_video_timings *t, u16 pos_x, 2105 u16 width, u16 height, u16 out_width, u16 out_height, 2106 bool five_taps) 2107 { 2108 const int ds = DIV_ROUND_UP(height, out_height); 2109 unsigned long nonactive; 2110 static const u8 limits[3] = { 8, 10, 20 }; 2111 u64 val, blank; 2112 int i; 2113 2114 nonactive = t->x_res + t->hfp + t->hsw + t->hbp - out_width; 2115 2116 i = 0; 2117 if (out_height < height) 2118 i++; 2119 if (out_width < width) 2120 i++; 2121 blank = div_u64((u64)(t->hbp + t->hsw + t->hfp) * lclk, pclk); 2122 DSSDBG("blanking period + ppl = %llu (limit = %u)\n", blank, limits[i]); 2123 if (blank <= limits[i]) 2124 return -EINVAL; 2125 2126 /* FIXME add checks for 3-tap filter once the limitations are known */ 2127 if (!five_taps) 2128 return 0; 2129 2130 /* 2131 * Pixel data should be prepared before visible display point starts. 2132 * So, atleast DS-2 lines must have already been fetched by DISPC 2133 * during nonactive - pos_x period. 2134 */ 2135 val = div_u64((u64)(nonactive - pos_x) * lclk, pclk); 2136 DSSDBG("(nonactive - pos_x) * pcd = %llu max(0, DS - 2) * width = %d\n", 2137 val, max(0, ds - 2) * width); 2138 if (val < max(0, ds - 2) * width) 2139 return -EINVAL; 2140 2141 /* 2142 * All lines need to be refilled during the nonactive period of which 2143 * only one line can be loaded during the active period. So, atleast 2144 * DS - 1 lines should be loaded during nonactive period. 2145 */ 2146 val = div_u64((u64)nonactive * lclk, pclk); 2147 DSSDBG("nonactive * pcd = %llu, max(0, DS - 1) * width = %d\n", 2148 val, max(0, ds - 1) * width); 2149 if (val < max(0, ds - 1) * width) 2150 return -EINVAL; 2151 2152 return 0; 2153 } 2154 2155 static unsigned long calc_core_clk_five_taps(unsigned long pclk, 2156 const struct omap_video_timings *mgr_timings, u16 width, 2157 u16 height, u16 out_width, u16 out_height, 2158 enum omap_color_mode color_mode) 2159 { 2160 u32 core_clk = 0; 2161 u64 tmp; 2162 2163 if (height <= out_height && width <= out_width) 2164 return (unsigned long) pclk; 2165 2166 if (height > out_height) { 2167 unsigned int ppl = mgr_timings->x_res; 2168 2169 tmp = (u64)pclk * height * out_width; 2170 do_div(tmp, 2 * out_height * ppl); 2171 core_clk = tmp; 2172 2173 if (height > 2 * out_height) { 2174 if (ppl == out_width) 2175 return 0; 2176 2177 tmp = (u64)pclk * (height - 2 * out_height) * out_width; 2178 do_div(tmp, 2 * out_height * (ppl - out_width)); 2179 core_clk = max_t(u32, core_clk, tmp); 2180 } 2181 } 2182 2183 if (width > out_width) { 2184 tmp = (u64)pclk * width; 2185 do_div(tmp, out_width); 2186 core_clk = max_t(u32, core_clk, tmp); 2187 2188 if (color_mode == OMAP_DSS_COLOR_RGB24U) 2189 core_clk <<= 1; 2190 } 2191 2192 return core_clk; 2193 } 2194 2195 static unsigned long calc_core_clk_24xx(unsigned long pclk, u16 width, 2196 u16 height, u16 out_width, u16 out_height, bool mem_to_mem) 2197 { 2198 if (height > out_height && width > out_width) 2199 return pclk * 4; 2200 else 2201 return pclk * 2; 2202 } 2203 2204 static unsigned long calc_core_clk_34xx(unsigned long pclk, u16 width, 2205 u16 height, u16 out_width, u16 out_height, bool mem_to_mem) 2206 { 2207 unsigned int hf, vf; 2208 2209 /* 2210 * FIXME how to determine the 'A' factor 2211 * for the no downscaling case ? 2212 */ 2213 2214 if (width > 3 * out_width) 2215 hf = 4; 2216 else if (width > 2 * out_width) 2217 hf = 3; 2218 else if (width > out_width) 2219 hf = 2; 2220 else 2221 hf = 1; 2222 if (height > out_height) 2223 vf = 2; 2224 else 2225 vf = 1; 2226 2227 return pclk * vf * hf; 2228 } 2229 2230 static unsigned long calc_core_clk_44xx(unsigned long pclk, u16 width, 2231 u16 height, u16 out_width, u16 out_height, bool mem_to_mem) 2232 { 2233 /* 2234 * If the overlay/writeback is in mem to mem mode, there are no 2235 * downscaling limitations with respect to pixel clock, return 1 as 2236 * required core clock to represent that we have sufficient enough 2237 * core clock to do maximum downscaling 2238 */ 2239 if (mem_to_mem) 2240 return 1; 2241 2242 if (width > out_width) 2243 return DIV_ROUND_UP(pclk, out_width) * width; 2244 else 2245 return pclk; 2246 } 2247 2248 static int dispc_ovl_calc_scaling_24xx(unsigned long pclk, unsigned long lclk, 2249 const struct omap_video_timings *mgr_timings, 2250 u16 width, u16 height, u16 out_width, u16 out_height, 2251 enum omap_color_mode color_mode, bool *five_taps, 2252 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y, 2253 u16 pos_x, unsigned long *core_clk, bool mem_to_mem) 2254 { 2255 int error; 2256 u16 in_width, in_height; 2257 int min_factor = min(*decim_x, *decim_y); 2258 const int maxsinglelinewidth = 2259 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH); 2260 2261 *five_taps = false; 2262 2263 do { 2264 in_height = height / *decim_y; 2265 in_width = width / *decim_x; 2266 *core_clk = dispc.feat->calc_core_clk(pclk, in_width, 2267 in_height, out_width, out_height, mem_to_mem); 2268 error = (in_width > maxsinglelinewidth || !*core_clk || 2269 *core_clk > dispc_core_clk_rate()); 2270 if (error) { 2271 if (*decim_x == *decim_y) { 2272 *decim_x = min_factor; 2273 ++*decim_y; 2274 } else { 2275 swap(*decim_x, *decim_y); 2276 if (*decim_x < *decim_y) 2277 ++*decim_x; 2278 } 2279 } 2280 } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error); 2281 2282 if (error) { 2283 DSSERR("failed to find scaling settings\n"); 2284 return -EINVAL; 2285 } 2286 2287 if (in_width > maxsinglelinewidth) { 2288 DSSERR("Cannot scale max input width exceeded"); 2289 return -EINVAL; 2290 } 2291 return 0; 2292 } 2293 2294 static int dispc_ovl_calc_scaling_34xx(unsigned long pclk, unsigned long lclk, 2295 const struct omap_video_timings *mgr_timings, 2296 u16 width, u16 height, u16 out_width, u16 out_height, 2297 enum omap_color_mode color_mode, bool *five_taps, 2298 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y, 2299 u16 pos_x, unsigned long *core_clk, bool mem_to_mem) 2300 { 2301 int error; 2302 u16 in_width, in_height; 2303 const int maxsinglelinewidth = 2304 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH); 2305 2306 do { 2307 in_height = height / *decim_y; 2308 in_width = width / *decim_x; 2309 *five_taps = in_height > out_height; 2310 2311 if (in_width > maxsinglelinewidth) 2312 if (in_height > out_height && 2313 in_height < out_height * 2) 2314 *five_taps = false; 2315 again: 2316 if (*five_taps) 2317 *core_clk = calc_core_clk_five_taps(pclk, mgr_timings, 2318 in_width, in_height, out_width, 2319 out_height, color_mode); 2320 else 2321 *core_clk = dispc.feat->calc_core_clk(pclk, in_width, 2322 in_height, out_width, out_height, 2323 mem_to_mem); 2324 2325 error = check_horiz_timing_omap3(pclk, lclk, mgr_timings, 2326 pos_x, in_width, in_height, out_width, 2327 out_height, *five_taps); 2328 if (error && *five_taps) { 2329 *five_taps = false; 2330 goto again; 2331 } 2332 2333 error = (error || in_width > maxsinglelinewidth * 2 || 2334 (in_width > maxsinglelinewidth && *five_taps) || 2335 !*core_clk || *core_clk > dispc_core_clk_rate()); 2336 2337 if (!error) { 2338 /* verify that we're inside the limits of scaler */ 2339 if (in_width / 4 > out_width) 2340 error = 1; 2341 2342 if (*five_taps) { 2343 if (in_height / 4 > out_height) 2344 error = 1; 2345 } else { 2346 if (in_height / 2 > out_height) 2347 error = 1; 2348 } 2349 } 2350 2351 if (error) 2352 ++*decim_y; 2353 } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error); 2354 2355 if (error) { 2356 DSSERR("failed to find scaling settings\n"); 2357 return -EINVAL; 2358 } 2359 2360 if (check_horiz_timing_omap3(pclk, lclk, mgr_timings, pos_x, in_width, 2361 in_height, out_width, out_height, *five_taps)) { 2362 DSSERR("horizontal timing too tight\n"); 2363 return -EINVAL; 2364 } 2365 2366 if (in_width > (maxsinglelinewidth * 2)) { 2367 DSSERR("Cannot setup scaling"); 2368 DSSERR("width exceeds maximum width possible"); 2369 return -EINVAL; 2370 } 2371 2372 if (in_width > maxsinglelinewidth && *five_taps) { 2373 DSSERR("cannot setup scaling with five taps"); 2374 return -EINVAL; 2375 } 2376 return 0; 2377 } 2378 2379 static int dispc_ovl_calc_scaling_44xx(unsigned long pclk, unsigned long lclk, 2380 const struct omap_video_timings *mgr_timings, 2381 u16 width, u16 height, u16 out_width, u16 out_height, 2382 enum omap_color_mode color_mode, bool *five_taps, 2383 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y, 2384 u16 pos_x, unsigned long *core_clk, bool mem_to_mem) 2385 { 2386 u16 in_width, in_width_max; 2387 int decim_x_min = *decim_x; 2388 u16 in_height = height / *decim_y; 2389 const int maxsinglelinewidth = 2390 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH); 2391 const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE); 2392 2393 if (mem_to_mem) { 2394 in_width_max = out_width * maxdownscale; 2395 } else { 2396 in_width_max = dispc_core_clk_rate() / 2397 DIV_ROUND_UP(pclk, out_width); 2398 } 2399 2400 *decim_x = DIV_ROUND_UP(width, in_width_max); 2401 2402 *decim_x = *decim_x > decim_x_min ? *decim_x : decim_x_min; 2403 if (*decim_x > *x_predecim) 2404 return -EINVAL; 2405 2406 do { 2407 in_width = width / *decim_x; 2408 } while (*decim_x <= *x_predecim && 2409 in_width > maxsinglelinewidth && ++*decim_x); 2410 2411 if (in_width > maxsinglelinewidth) { 2412 DSSERR("Cannot scale width exceeds max line width"); 2413 return -EINVAL; 2414 } 2415 2416 *core_clk = dispc.feat->calc_core_clk(pclk, in_width, in_height, 2417 out_width, out_height, mem_to_mem); 2418 return 0; 2419 } 2420 2421 #define DIV_FRAC(dividend, divisor) \ 2422 ((dividend) * 100 / (divisor) - ((dividend) / (divisor) * 100)) 2423 2424 static int dispc_ovl_calc_scaling(unsigned long pclk, unsigned long lclk, 2425 enum omap_overlay_caps caps, 2426 const struct omap_video_timings *mgr_timings, 2427 u16 width, u16 height, u16 out_width, u16 out_height, 2428 enum omap_color_mode color_mode, bool *five_taps, 2429 int *x_predecim, int *y_predecim, u16 pos_x, 2430 enum omap_dss_rotation_type rotation_type, bool mem_to_mem) 2431 { 2432 const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE); 2433 const int max_decim_limit = 16; 2434 unsigned long core_clk = 0; 2435 int decim_x, decim_y, ret; 2436 2437 if (width == out_width && height == out_height) 2438 return 0; 2439 2440 if (!mem_to_mem && (pclk == 0 || mgr_timings->pixelclock == 0)) { 2441 DSSERR("cannot calculate scaling settings: pclk is zero\n"); 2442 return -EINVAL; 2443 } 2444 2445 if ((caps & OMAP_DSS_OVL_CAP_SCALE) == 0) 2446 return -EINVAL; 2447 2448 if (mem_to_mem) { 2449 *x_predecim = *y_predecim = 1; 2450 } else { 2451 *x_predecim = max_decim_limit; 2452 *y_predecim = (rotation_type == OMAP_DSS_ROT_TILER && 2453 dss_has_feature(FEAT_BURST_2D)) ? 2454 2 : max_decim_limit; 2455 } 2456 2457 if (color_mode == OMAP_DSS_COLOR_CLUT1 || 2458 color_mode == OMAP_DSS_COLOR_CLUT2 || 2459 color_mode == OMAP_DSS_COLOR_CLUT4 || 2460 color_mode == OMAP_DSS_COLOR_CLUT8) { 2461 *x_predecim = 1; 2462 *y_predecim = 1; 2463 *five_taps = false; 2464 return 0; 2465 } 2466 2467 decim_x = DIV_ROUND_UP(DIV_ROUND_UP(width, out_width), maxdownscale); 2468 decim_y = DIV_ROUND_UP(DIV_ROUND_UP(height, out_height), maxdownscale); 2469 2470 if (decim_x > *x_predecim || out_width > width * 8) 2471 return -EINVAL; 2472 2473 if (decim_y > *y_predecim || out_height > height * 8) 2474 return -EINVAL; 2475 2476 ret = dispc.feat->calc_scaling(pclk, lclk, mgr_timings, width, height, 2477 out_width, out_height, color_mode, five_taps, 2478 x_predecim, y_predecim, &decim_x, &decim_y, pos_x, &core_clk, 2479 mem_to_mem); 2480 if (ret) 2481 return ret; 2482 2483 DSSDBG("%dx%d -> %dx%d (%d.%02d x %d.%02d), decim %dx%d %dx%d (%d.%02d x %d.%02d), taps %d, req clk %lu, cur clk %lu\n", 2484 width, height, 2485 out_width, out_height, 2486 out_width / width, DIV_FRAC(out_width, width), 2487 out_height / height, DIV_FRAC(out_height, height), 2488 2489 decim_x, decim_y, 2490 width / decim_x, height / decim_y, 2491 out_width / (width / decim_x), DIV_FRAC(out_width, width / decim_x), 2492 out_height / (height / decim_y), DIV_FRAC(out_height, height / decim_y), 2493 2494 *five_taps ? 5 : 3, 2495 core_clk, dispc_core_clk_rate()); 2496 2497 if (!core_clk || core_clk > dispc_core_clk_rate()) { 2498 DSSERR("failed to set up scaling, " 2499 "required core clk rate = %lu Hz, " 2500 "current core clk rate = %lu Hz\n", 2501 core_clk, dispc_core_clk_rate()); 2502 return -EINVAL; 2503 } 2504 2505 *x_predecim = decim_x; 2506 *y_predecim = decim_y; 2507 return 0; 2508 } 2509 2510 int dispc_ovl_check(enum omap_plane plane, enum omap_channel channel, 2511 const struct omap_overlay_info *oi, 2512 const struct omap_video_timings *timings, 2513 int *x_predecim, int *y_predecim) 2514 { 2515 enum omap_overlay_caps caps = dss_feat_get_overlay_caps(plane); 2516 bool five_taps = true; 2517 bool fieldmode = false; 2518 u16 in_height = oi->height; 2519 u16 in_width = oi->width; 2520 bool ilace = timings->interlace; 2521 u16 out_width, out_height; 2522 int pos_x = oi->pos_x; 2523 unsigned long pclk = dispc_mgr_pclk_rate(channel); 2524 unsigned long lclk = dispc_mgr_lclk_rate(channel); 2525 2526 out_width = oi->out_width == 0 ? oi->width : oi->out_width; 2527 out_height = oi->out_height == 0 ? oi->height : oi->out_height; 2528 2529 if (ilace && oi->height == out_height) 2530 fieldmode = true; 2531 2532 if (ilace) { 2533 if (fieldmode) 2534 in_height /= 2; 2535 out_height /= 2; 2536 2537 DSSDBG("adjusting for ilace: height %d, out_height %d\n", 2538 in_height, out_height); 2539 } 2540 2541 if (!dss_feat_color_mode_supported(plane, oi->color_mode)) 2542 return -EINVAL; 2543 2544 return dispc_ovl_calc_scaling(pclk, lclk, caps, timings, in_width, 2545 in_height, out_width, out_height, oi->color_mode, 2546 &five_taps, x_predecim, y_predecim, pos_x, 2547 oi->rotation_type, false); 2548 } 2549 EXPORT_SYMBOL(dispc_ovl_check); 2550 2551 static int dispc_ovl_setup_common(enum omap_plane plane, 2552 enum omap_overlay_caps caps, u32 paddr, u32 p_uv_addr, 2553 u16 screen_width, int pos_x, int pos_y, u16 width, u16 height, 2554 u16 out_width, u16 out_height, enum omap_color_mode color_mode, 2555 u8 rotation, bool mirror, u8 zorder, u8 pre_mult_alpha, 2556 u8 global_alpha, enum omap_dss_rotation_type rotation_type, 2557 bool replication, const struct omap_video_timings *mgr_timings, 2558 bool mem_to_mem) 2559 { 2560 bool five_taps = true; 2561 bool fieldmode = false; 2562 int r, cconv = 0; 2563 unsigned offset0, offset1; 2564 s32 row_inc; 2565 s32 pix_inc; 2566 u16 frame_width, frame_height; 2567 unsigned int field_offset = 0; 2568 u16 in_height = height; 2569 u16 in_width = width; 2570 int x_predecim = 1, y_predecim = 1; 2571 bool ilace = mgr_timings->interlace; 2572 unsigned long pclk = dispc_plane_pclk_rate(plane); 2573 unsigned long lclk = dispc_plane_lclk_rate(plane); 2574 2575 if (paddr == 0 && rotation_type != OMAP_DSS_ROT_TILER) 2576 return -EINVAL; 2577 2578 switch (color_mode) { 2579 case OMAP_DSS_COLOR_YUV2: 2580 case OMAP_DSS_COLOR_UYVY: 2581 case OMAP_DSS_COLOR_NV12: 2582 if (in_width & 1) { 2583 DSSERR("input width %d is not even for YUV format\n", 2584 in_width); 2585 return -EINVAL; 2586 } 2587 break; 2588 2589 default: 2590 break; 2591 } 2592 2593 out_width = out_width == 0 ? width : out_width; 2594 out_height = out_height == 0 ? height : out_height; 2595 2596 if (ilace && height == out_height) 2597 fieldmode = true; 2598 2599 if (ilace) { 2600 if (fieldmode) 2601 in_height /= 2; 2602 pos_y /= 2; 2603 out_height /= 2; 2604 2605 DSSDBG("adjusting for ilace: height %d, pos_y %d, " 2606 "out_height %d\n", in_height, pos_y, 2607 out_height); 2608 } 2609 2610 if (!dss_feat_color_mode_supported(plane, color_mode)) 2611 return -EINVAL; 2612 2613 r = dispc_ovl_calc_scaling(pclk, lclk, caps, mgr_timings, in_width, 2614 in_height, out_width, out_height, color_mode, 2615 &five_taps, &x_predecim, &y_predecim, pos_x, 2616 rotation_type, mem_to_mem); 2617 if (r) 2618 return r; 2619 2620 in_width = in_width / x_predecim; 2621 in_height = in_height / y_predecim; 2622 2623 if (x_predecim > 1 || y_predecim > 1) 2624 DSSDBG("predecimation %d x %x, new input size %d x %d\n", 2625 x_predecim, y_predecim, in_width, in_height); 2626 2627 switch (color_mode) { 2628 case OMAP_DSS_COLOR_YUV2: 2629 case OMAP_DSS_COLOR_UYVY: 2630 case OMAP_DSS_COLOR_NV12: 2631 if (in_width & 1) { 2632 DSSDBG("predecimated input width is not even for YUV format\n"); 2633 DSSDBG("adjusting input width %d -> %d\n", 2634 in_width, in_width & ~1); 2635 2636 in_width &= ~1; 2637 } 2638 break; 2639 2640 default: 2641 break; 2642 } 2643 2644 if (color_mode == OMAP_DSS_COLOR_YUV2 || 2645 color_mode == OMAP_DSS_COLOR_UYVY || 2646 color_mode == OMAP_DSS_COLOR_NV12) 2647 cconv = 1; 2648 2649 if (ilace && !fieldmode) { 2650 /* 2651 * when downscaling the bottom field may have to start several 2652 * source lines below the top field. Unfortunately ACCUI 2653 * registers will only hold the fractional part of the offset 2654 * so the integer part must be added to the base address of the 2655 * bottom field. 2656 */ 2657 if (!in_height || in_height == out_height) 2658 field_offset = 0; 2659 else 2660 field_offset = in_height / out_height / 2; 2661 } 2662 2663 /* Fields are independent but interleaved in memory. */ 2664 if (fieldmode) 2665 field_offset = 1; 2666 2667 offset0 = 0; 2668 offset1 = 0; 2669 row_inc = 0; 2670 pix_inc = 0; 2671 2672 if (plane == OMAP_DSS_WB) { 2673 frame_width = out_width; 2674 frame_height = out_height; 2675 } else { 2676 frame_width = in_width; 2677 frame_height = height; 2678 } 2679 2680 if (rotation_type == OMAP_DSS_ROT_TILER) 2681 calc_tiler_rotation_offset(screen_width, frame_width, 2682 color_mode, fieldmode, field_offset, 2683 &offset0, &offset1, &row_inc, &pix_inc, 2684 x_predecim, y_predecim); 2685 else if (rotation_type == OMAP_DSS_ROT_DMA) 2686 calc_dma_rotation_offset(rotation, mirror, screen_width, 2687 frame_width, frame_height, 2688 color_mode, fieldmode, field_offset, 2689 &offset0, &offset1, &row_inc, &pix_inc, 2690 x_predecim, y_predecim); 2691 else 2692 calc_vrfb_rotation_offset(rotation, mirror, 2693 screen_width, frame_width, frame_height, 2694 color_mode, fieldmode, field_offset, 2695 &offset0, &offset1, &row_inc, &pix_inc, 2696 x_predecim, y_predecim); 2697 2698 DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n", 2699 offset0, offset1, row_inc, pix_inc); 2700 2701 dispc_ovl_set_color_mode(plane, color_mode); 2702 2703 dispc_ovl_configure_burst_type(plane, rotation_type); 2704 2705 dispc_ovl_set_ba0(plane, paddr + offset0); 2706 dispc_ovl_set_ba1(plane, paddr + offset1); 2707 2708 if (OMAP_DSS_COLOR_NV12 == color_mode) { 2709 dispc_ovl_set_ba0_uv(plane, p_uv_addr + offset0); 2710 dispc_ovl_set_ba1_uv(plane, p_uv_addr + offset1); 2711 } 2712 2713 if (dispc.feat->last_pixel_inc_missing) 2714 row_inc += pix_inc - 1; 2715 2716 dispc_ovl_set_row_inc(plane, row_inc); 2717 dispc_ovl_set_pix_inc(plane, pix_inc); 2718 2719 DSSDBG("%d,%d %dx%d -> %dx%d\n", pos_x, pos_y, in_width, 2720 in_height, out_width, out_height); 2721 2722 dispc_ovl_set_pos(plane, caps, pos_x, pos_y); 2723 2724 dispc_ovl_set_input_size(plane, in_width, in_height); 2725 2726 if (caps & OMAP_DSS_OVL_CAP_SCALE) { 2727 dispc_ovl_set_scaling(plane, in_width, in_height, out_width, 2728 out_height, ilace, five_taps, fieldmode, 2729 color_mode, rotation); 2730 dispc_ovl_set_output_size(plane, out_width, out_height); 2731 dispc_ovl_set_vid_color_conv(plane, cconv); 2732 } 2733 2734 dispc_ovl_set_rotation_attrs(plane, rotation, rotation_type, mirror, 2735 color_mode); 2736 2737 dispc_ovl_set_zorder(plane, caps, zorder); 2738 dispc_ovl_set_pre_mult_alpha(plane, caps, pre_mult_alpha); 2739 dispc_ovl_setup_global_alpha(plane, caps, global_alpha); 2740 2741 dispc_ovl_enable_replication(plane, caps, replication); 2742 2743 return 0; 2744 } 2745 2746 int dispc_ovl_setup(enum omap_plane plane, const struct omap_overlay_info *oi, 2747 bool replication, const struct omap_video_timings *mgr_timings, 2748 bool mem_to_mem) 2749 { 2750 int r; 2751 enum omap_overlay_caps caps = dss_feat_get_overlay_caps(plane); 2752 enum omap_channel channel; 2753 2754 channel = dispc_ovl_get_channel_out(plane); 2755 2756 DSSDBG("dispc_ovl_setup %d, pa %pad, pa_uv %pad, sw %d, %d,%d, %dx%d ->" 2757 " %dx%d, cmode %x, rot %d, mir %d, chan %d repl %d\n", 2758 plane, &oi->paddr, &oi->p_uv_addr, oi->screen_width, oi->pos_x, 2759 oi->pos_y, oi->width, oi->height, oi->out_width, oi->out_height, 2760 oi->color_mode, oi->rotation, oi->mirror, channel, replication); 2761 2762 r = dispc_ovl_setup_common(plane, caps, oi->paddr, oi->p_uv_addr, 2763 oi->screen_width, oi->pos_x, oi->pos_y, oi->width, oi->height, 2764 oi->out_width, oi->out_height, oi->color_mode, oi->rotation, 2765 oi->mirror, oi->zorder, oi->pre_mult_alpha, oi->global_alpha, 2766 oi->rotation_type, replication, mgr_timings, mem_to_mem); 2767 2768 return r; 2769 } 2770 EXPORT_SYMBOL(dispc_ovl_setup); 2771 2772 int dispc_ovl_enable(enum omap_plane plane, bool enable) 2773 { 2774 DSSDBG("dispc_enable_plane %d, %d\n", plane, enable); 2775 2776 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0); 2777 2778 return 0; 2779 } 2780 EXPORT_SYMBOL(dispc_ovl_enable); 2781 2782 bool dispc_ovl_enabled(enum omap_plane plane) 2783 { 2784 return REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0); 2785 } 2786 EXPORT_SYMBOL(dispc_ovl_enabled); 2787 2788 void dispc_mgr_enable(enum omap_channel channel, bool enable) 2789 { 2790 mgr_fld_write(channel, DISPC_MGR_FLD_ENABLE, enable); 2791 /* flush posted write */ 2792 mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE); 2793 } 2794 EXPORT_SYMBOL(dispc_mgr_enable); 2795 2796 bool dispc_mgr_is_enabled(enum omap_channel channel) 2797 { 2798 return !!mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE); 2799 } 2800 EXPORT_SYMBOL(dispc_mgr_is_enabled); 2801 2802 static void dispc_lcd_enable_signal_polarity(bool act_high) 2803 { 2804 if (!dss_has_feature(FEAT_LCDENABLEPOL)) 2805 return; 2806 2807 REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29); 2808 } 2809 2810 void dispc_lcd_enable_signal(bool enable) 2811 { 2812 if (!dss_has_feature(FEAT_LCDENABLESIGNAL)) 2813 return; 2814 2815 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28); 2816 } 2817 2818 void dispc_pck_free_enable(bool enable) 2819 { 2820 if (!dss_has_feature(FEAT_PCKFREEENABLE)) 2821 return; 2822 2823 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27); 2824 } 2825 2826 static void dispc_mgr_enable_fifohandcheck(enum omap_channel channel, bool enable) 2827 { 2828 mgr_fld_write(channel, DISPC_MGR_FLD_FIFOHANDCHECK, enable); 2829 } 2830 2831 2832 static void dispc_mgr_set_lcd_type_tft(enum omap_channel channel) 2833 { 2834 mgr_fld_write(channel, DISPC_MGR_FLD_STNTFT, 1); 2835 } 2836 2837 static void dispc_set_loadmode(enum omap_dss_load_mode mode) 2838 { 2839 REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1); 2840 } 2841 2842 2843 static void dispc_mgr_set_default_color(enum omap_channel channel, u32 color) 2844 { 2845 dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color); 2846 } 2847 2848 static void dispc_mgr_set_trans_key(enum omap_channel ch, 2849 enum omap_dss_trans_key_type type, 2850 u32 trans_key) 2851 { 2852 mgr_fld_write(ch, DISPC_MGR_FLD_TCKSELECTION, type); 2853 2854 dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key); 2855 } 2856 2857 static void dispc_mgr_enable_trans_key(enum omap_channel ch, bool enable) 2858 { 2859 mgr_fld_write(ch, DISPC_MGR_FLD_TCKENABLE, enable); 2860 } 2861 2862 static void dispc_mgr_enable_alpha_fixed_zorder(enum omap_channel ch, 2863 bool enable) 2864 { 2865 if (!dss_has_feature(FEAT_ALPHA_FIXED_ZORDER)) 2866 return; 2867 2868 if (ch == OMAP_DSS_CHANNEL_LCD) 2869 REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18); 2870 else if (ch == OMAP_DSS_CHANNEL_DIGIT) 2871 REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19); 2872 } 2873 2874 void dispc_mgr_setup(enum omap_channel channel, 2875 const struct omap_overlay_manager_info *info) 2876 { 2877 dispc_mgr_set_default_color(channel, info->default_color); 2878 dispc_mgr_set_trans_key(channel, info->trans_key_type, info->trans_key); 2879 dispc_mgr_enable_trans_key(channel, info->trans_enabled); 2880 dispc_mgr_enable_alpha_fixed_zorder(channel, 2881 info->partial_alpha_enabled); 2882 if (dss_has_feature(FEAT_CPR)) { 2883 dispc_mgr_enable_cpr(channel, info->cpr_enable); 2884 dispc_mgr_set_cpr_coef(channel, &info->cpr_coefs); 2885 } 2886 } 2887 EXPORT_SYMBOL(dispc_mgr_setup); 2888 2889 static void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines) 2890 { 2891 int code; 2892 2893 switch (data_lines) { 2894 case 12: 2895 code = 0; 2896 break; 2897 case 16: 2898 code = 1; 2899 break; 2900 case 18: 2901 code = 2; 2902 break; 2903 case 24: 2904 code = 3; 2905 break; 2906 default: 2907 BUG(); 2908 return; 2909 } 2910 2911 mgr_fld_write(channel, DISPC_MGR_FLD_TFTDATALINES, code); 2912 } 2913 2914 static void dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode) 2915 { 2916 u32 l; 2917 int gpout0, gpout1; 2918 2919 switch (mode) { 2920 case DSS_IO_PAD_MODE_RESET: 2921 gpout0 = 0; 2922 gpout1 = 0; 2923 break; 2924 case DSS_IO_PAD_MODE_RFBI: 2925 gpout0 = 1; 2926 gpout1 = 0; 2927 break; 2928 case DSS_IO_PAD_MODE_BYPASS: 2929 gpout0 = 1; 2930 gpout1 = 1; 2931 break; 2932 default: 2933 BUG(); 2934 return; 2935 } 2936 2937 l = dispc_read_reg(DISPC_CONTROL); 2938 l = FLD_MOD(l, gpout0, 15, 15); 2939 l = FLD_MOD(l, gpout1, 16, 16); 2940 dispc_write_reg(DISPC_CONTROL, l); 2941 } 2942 2943 static void dispc_mgr_enable_stallmode(enum omap_channel channel, bool enable) 2944 { 2945 mgr_fld_write(channel, DISPC_MGR_FLD_STALLMODE, enable); 2946 } 2947 2948 void dispc_mgr_set_lcd_config(enum omap_channel channel, 2949 const struct dss_lcd_mgr_config *config) 2950 { 2951 dispc_mgr_set_io_pad_mode(config->io_pad_mode); 2952 2953 dispc_mgr_enable_stallmode(channel, config->stallmode); 2954 dispc_mgr_enable_fifohandcheck(channel, config->fifohandcheck); 2955 2956 dispc_mgr_set_clock_div(channel, &config->clock_info); 2957 2958 dispc_mgr_set_tft_data_lines(channel, config->video_port_width); 2959 2960 dispc_lcd_enable_signal_polarity(config->lcden_sig_polarity); 2961 2962 dispc_mgr_set_lcd_type_tft(channel); 2963 } 2964 EXPORT_SYMBOL(dispc_mgr_set_lcd_config); 2965 2966 static bool _dispc_mgr_size_ok(u16 width, u16 height) 2967 { 2968 return width <= dispc.feat->mgr_width_max && 2969 height <= dispc.feat->mgr_height_max; 2970 } 2971 2972 static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp, 2973 int vsw, int vfp, int vbp) 2974 { 2975 if (hsw < 1 || hsw > dispc.feat->sw_max || 2976 hfp < 1 || hfp > dispc.feat->hp_max || 2977 hbp < 1 || hbp > dispc.feat->hp_max || 2978 vsw < 1 || vsw > dispc.feat->sw_max || 2979 vfp < 0 || vfp > dispc.feat->vp_max || 2980 vbp < 0 || vbp > dispc.feat->vp_max) 2981 return false; 2982 return true; 2983 } 2984 2985 static bool _dispc_mgr_pclk_ok(enum omap_channel channel, 2986 unsigned long pclk) 2987 { 2988 if (dss_mgr_is_lcd(channel)) 2989 return pclk <= dispc.feat->max_lcd_pclk; 2990 else 2991 return pclk <= dispc.feat->max_tv_pclk; 2992 } 2993 2994 bool dispc_mgr_timings_ok(enum omap_channel channel, 2995 const struct omap_video_timings *timings) 2996 { 2997 if (!_dispc_mgr_size_ok(timings->x_res, timings->y_res)) 2998 return false; 2999 3000 if (!_dispc_mgr_pclk_ok(channel, timings->pixelclock)) 3001 return false; 3002 3003 if (dss_mgr_is_lcd(channel)) { 3004 /* TODO: OMAP4+ supports interlace for LCD outputs */ 3005 if (timings->interlace) 3006 return false; 3007 3008 if (!_dispc_lcd_timings_ok(timings->hsw, timings->hfp, 3009 timings->hbp, timings->vsw, timings->vfp, 3010 timings->vbp)) 3011 return false; 3012 } 3013 3014 return true; 3015 } 3016 3017 static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsw, 3018 int hfp, int hbp, int vsw, int vfp, int vbp, 3019 enum omap_dss_signal_level vsync_level, 3020 enum omap_dss_signal_level hsync_level, 3021 enum omap_dss_signal_edge data_pclk_edge, 3022 enum omap_dss_signal_level de_level, 3023 enum omap_dss_signal_edge sync_pclk_edge) 3024 3025 { 3026 u32 timing_h, timing_v, l; 3027 bool onoff, rf, ipc, vs, hs, de; 3028 3029 timing_h = FLD_VAL(hsw-1, dispc.feat->sw_start, 0) | 3030 FLD_VAL(hfp-1, dispc.feat->fp_start, 8) | 3031 FLD_VAL(hbp-1, dispc.feat->bp_start, 20); 3032 timing_v = FLD_VAL(vsw-1, dispc.feat->sw_start, 0) | 3033 FLD_VAL(vfp, dispc.feat->fp_start, 8) | 3034 FLD_VAL(vbp, dispc.feat->bp_start, 20); 3035 3036 dispc_write_reg(DISPC_TIMING_H(channel), timing_h); 3037 dispc_write_reg(DISPC_TIMING_V(channel), timing_v); 3038 3039 switch (vsync_level) { 3040 case OMAPDSS_SIG_ACTIVE_LOW: 3041 vs = true; 3042 break; 3043 case OMAPDSS_SIG_ACTIVE_HIGH: 3044 vs = false; 3045 break; 3046 default: 3047 BUG(); 3048 } 3049 3050 switch (hsync_level) { 3051 case OMAPDSS_SIG_ACTIVE_LOW: 3052 hs = true; 3053 break; 3054 case OMAPDSS_SIG_ACTIVE_HIGH: 3055 hs = false; 3056 break; 3057 default: 3058 BUG(); 3059 } 3060 3061 switch (de_level) { 3062 case OMAPDSS_SIG_ACTIVE_LOW: 3063 de = true; 3064 break; 3065 case OMAPDSS_SIG_ACTIVE_HIGH: 3066 de = false; 3067 break; 3068 default: 3069 BUG(); 3070 } 3071 3072 switch (data_pclk_edge) { 3073 case OMAPDSS_DRIVE_SIG_RISING_EDGE: 3074 ipc = false; 3075 break; 3076 case OMAPDSS_DRIVE_SIG_FALLING_EDGE: 3077 ipc = true; 3078 break; 3079 default: 3080 BUG(); 3081 } 3082 3083 /* always use the 'rf' setting */ 3084 onoff = true; 3085 3086 switch (sync_pclk_edge) { 3087 case OMAPDSS_DRIVE_SIG_FALLING_EDGE: 3088 rf = false; 3089 break; 3090 case OMAPDSS_DRIVE_SIG_RISING_EDGE: 3091 rf = true; 3092 break; 3093 default: 3094 BUG(); 3095 } 3096 3097 l = FLD_VAL(onoff, 17, 17) | 3098 FLD_VAL(rf, 16, 16) | 3099 FLD_VAL(de, 15, 15) | 3100 FLD_VAL(ipc, 14, 14) | 3101 FLD_VAL(hs, 13, 13) | 3102 FLD_VAL(vs, 12, 12); 3103 3104 /* always set ALIGN bit when available */ 3105 if (dispc.feat->supports_sync_align) 3106 l |= (1 << 18); 3107 3108 dispc_write_reg(DISPC_POL_FREQ(channel), l); 3109 3110 if (dispc.syscon_pol) { 3111 const int shifts[] = { 3112 [OMAP_DSS_CHANNEL_LCD] = 0, 3113 [OMAP_DSS_CHANNEL_LCD2] = 1, 3114 [OMAP_DSS_CHANNEL_LCD3] = 2, 3115 }; 3116 3117 u32 mask, val; 3118 3119 mask = (1 << 0) | (1 << 3) | (1 << 6); 3120 val = (rf << 0) | (ipc << 3) | (onoff << 6); 3121 3122 mask <<= 16 + shifts[channel]; 3123 val <<= 16 + shifts[channel]; 3124 3125 regmap_update_bits(dispc.syscon_pol, dispc.syscon_pol_offset, 3126 mask, val); 3127 } 3128 } 3129 3130 /* change name to mode? */ 3131 void dispc_mgr_set_timings(enum omap_channel channel, 3132 const struct omap_video_timings *timings) 3133 { 3134 unsigned xtot, ytot; 3135 unsigned long ht, vt; 3136 struct omap_video_timings t = *timings; 3137 3138 DSSDBG("channel %d xres %u yres %u\n", channel, t.x_res, t.y_res); 3139 3140 if (!dispc_mgr_timings_ok(channel, &t)) { 3141 BUG(); 3142 return; 3143 } 3144 3145 if (dss_mgr_is_lcd(channel)) { 3146 _dispc_mgr_set_lcd_timings(channel, t.hsw, t.hfp, t.hbp, t.vsw, 3147 t.vfp, t.vbp, t.vsync_level, t.hsync_level, 3148 t.data_pclk_edge, t.de_level, t.sync_pclk_edge); 3149 3150 xtot = t.x_res + t.hfp + t.hsw + t.hbp; 3151 ytot = t.y_res + t.vfp + t.vsw + t.vbp; 3152 3153 ht = timings->pixelclock / xtot; 3154 vt = timings->pixelclock / xtot / ytot; 3155 3156 DSSDBG("pck %u\n", timings->pixelclock); 3157 DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n", 3158 t.hsw, t.hfp, t.hbp, t.vsw, t.vfp, t.vbp); 3159 DSSDBG("vsync_level %d hsync_level %d data_pclk_edge %d de_level %d sync_pclk_edge %d\n", 3160 t.vsync_level, t.hsync_level, t.data_pclk_edge, 3161 t.de_level, t.sync_pclk_edge); 3162 3163 DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt); 3164 } else { 3165 if (t.interlace) 3166 t.y_res /= 2; 3167 } 3168 3169 dispc_mgr_set_size(channel, t.x_res, t.y_res); 3170 } 3171 EXPORT_SYMBOL(dispc_mgr_set_timings); 3172 3173 static void dispc_mgr_set_lcd_divisor(enum omap_channel channel, u16 lck_div, 3174 u16 pck_div) 3175 { 3176 BUG_ON(lck_div < 1); 3177 BUG_ON(pck_div < 1); 3178 3179 dispc_write_reg(DISPC_DIVISORo(channel), 3180 FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0)); 3181 3182 if (!dss_has_feature(FEAT_CORE_CLK_DIV) && 3183 channel == OMAP_DSS_CHANNEL_LCD) 3184 dispc.core_clk_rate = dispc_fclk_rate() / lck_div; 3185 } 3186 3187 static void dispc_mgr_get_lcd_divisor(enum omap_channel channel, int *lck_div, 3188 int *pck_div) 3189 { 3190 u32 l; 3191 l = dispc_read_reg(DISPC_DIVISORo(channel)); 3192 *lck_div = FLD_GET(l, 23, 16); 3193 *pck_div = FLD_GET(l, 7, 0); 3194 } 3195 3196 static unsigned long dispc_fclk_rate(void) 3197 { 3198 struct dss_pll *pll; 3199 unsigned long r = 0; 3200 3201 switch (dss_get_dispc_clk_source()) { 3202 case OMAP_DSS_CLK_SRC_FCK: 3203 r = dss_get_dispc_clk_rate(); 3204 break; 3205 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC: 3206 pll = dss_pll_find("dsi0"); 3207 if (!pll) 3208 pll = dss_pll_find("video0"); 3209 3210 r = pll->cinfo.clkout[0]; 3211 break; 3212 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC: 3213 pll = dss_pll_find("dsi1"); 3214 if (!pll) 3215 pll = dss_pll_find("video1"); 3216 3217 r = pll->cinfo.clkout[0]; 3218 break; 3219 default: 3220 BUG(); 3221 return 0; 3222 } 3223 3224 return r; 3225 } 3226 3227 static unsigned long dispc_mgr_lclk_rate(enum omap_channel channel) 3228 { 3229 struct dss_pll *pll; 3230 int lcd; 3231 unsigned long r; 3232 u32 l; 3233 3234 if (dss_mgr_is_lcd(channel)) { 3235 l = dispc_read_reg(DISPC_DIVISORo(channel)); 3236 3237 lcd = FLD_GET(l, 23, 16); 3238 3239 switch (dss_get_lcd_clk_source(channel)) { 3240 case OMAP_DSS_CLK_SRC_FCK: 3241 r = dss_get_dispc_clk_rate(); 3242 break; 3243 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC: 3244 pll = dss_pll_find("dsi0"); 3245 if (!pll) 3246 pll = dss_pll_find("video0"); 3247 3248 r = pll->cinfo.clkout[0]; 3249 break; 3250 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC: 3251 pll = dss_pll_find("dsi1"); 3252 if (!pll) 3253 pll = dss_pll_find("video1"); 3254 3255 r = pll->cinfo.clkout[0]; 3256 break; 3257 default: 3258 BUG(); 3259 return 0; 3260 } 3261 3262 return r / lcd; 3263 } else { 3264 return dispc_fclk_rate(); 3265 } 3266 } 3267 3268 static unsigned long dispc_mgr_pclk_rate(enum omap_channel channel) 3269 { 3270 unsigned long r; 3271 3272 if (dss_mgr_is_lcd(channel)) { 3273 int pcd; 3274 u32 l; 3275 3276 l = dispc_read_reg(DISPC_DIVISORo(channel)); 3277 3278 pcd = FLD_GET(l, 7, 0); 3279 3280 r = dispc_mgr_lclk_rate(channel); 3281 3282 return r / pcd; 3283 } else { 3284 return dispc.tv_pclk_rate; 3285 } 3286 } 3287 3288 void dispc_set_tv_pclk(unsigned long pclk) 3289 { 3290 dispc.tv_pclk_rate = pclk; 3291 } 3292 3293 static unsigned long dispc_core_clk_rate(void) 3294 { 3295 return dispc.core_clk_rate; 3296 } 3297 3298 static unsigned long dispc_plane_pclk_rate(enum omap_plane plane) 3299 { 3300 enum omap_channel channel; 3301 3302 if (plane == OMAP_DSS_WB) 3303 return 0; 3304 3305 channel = dispc_ovl_get_channel_out(plane); 3306 3307 return dispc_mgr_pclk_rate(channel); 3308 } 3309 3310 static unsigned long dispc_plane_lclk_rate(enum omap_plane plane) 3311 { 3312 enum omap_channel channel; 3313 3314 if (plane == OMAP_DSS_WB) 3315 return 0; 3316 3317 channel = dispc_ovl_get_channel_out(plane); 3318 3319 return dispc_mgr_lclk_rate(channel); 3320 } 3321 3322 static void dispc_dump_clocks_channel(struct seq_file *s, enum omap_channel channel) 3323 { 3324 int lcd, pcd; 3325 enum omap_dss_clk_source lcd_clk_src; 3326 3327 seq_printf(s, "- %s -\n", mgr_desc[channel].name); 3328 3329 lcd_clk_src = dss_get_lcd_clk_source(channel); 3330 3331 seq_printf(s, "%s clk source = %s (%s)\n", mgr_desc[channel].name, 3332 dss_get_generic_clk_source_name(lcd_clk_src), 3333 dss_feat_get_clk_source_name(lcd_clk_src)); 3334 3335 dispc_mgr_get_lcd_divisor(channel, &lcd, &pcd); 3336 3337 seq_printf(s, "lck\t\t%-16lulck div\t%u\n", 3338 dispc_mgr_lclk_rate(channel), lcd); 3339 seq_printf(s, "pck\t\t%-16lupck div\t%u\n", 3340 dispc_mgr_pclk_rate(channel), pcd); 3341 } 3342 3343 void dispc_dump_clocks(struct seq_file *s) 3344 { 3345 int lcd; 3346 u32 l; 3347 enum omap_dss_clk_source dispc_clk_src = dss_get_dispc_clk_source(); 3348 3349 if (dispc_runtime_get()) 3350 return; 3351 3352 seq_printf(s, "- DISPC -\n"); 3353 3354 seq_printf(s, "dispc fclk source = %s (%s)\n", 3355 dss_get_generic_clk_source_name(dispc_clk_src), 3356 dss_feat_get_clk_source_name(dispc_clk_src)); 3357 3358 seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate()); 3359 3360 if (dss_has_feature(FEAT_CORE_CLK_DIV)) { 3361 seq_printf(s, "- DISPC-CORE-CLK -\n"); 3362 l = dispc_read_reg(DISPC_DIVISOR); 3363 lcd = FLD_GET(l, 23, 16); 3364 3365 seq_printf(s, "lck\t\t%-16lulck div\t%u\n", 3366 (dispc_fclk_rate()/lcd), lcd); 3367 } 3368 3369 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD); 3370 3371 if (dss_has_feature(FEAT_MGR_LCD2)) 3372 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD2); 3373 if (dss_has_feature(FEAT_MGR_LCD3)) 3374 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD3); 3375 3376 dispc_runtime_put(); 3377 } 3378 3379 static void dispc_dump_regs(struct seq_file *s) 3380 { 3381 int i, j; 3382 const char *mgr_names[] = { 3383 [OMAP_DSS_CHANNEL_LCD] = "LCD", 3384 [OMAP_DSS_CHANNEL_DIGIT] = "TV", 3385 [OMAP_DSS_CHANNEL_LCD2] = "LCD2", 3386 [OMAP_DSS_CHANNEL_LCD3] = "LCD3", 3387 }; 3388 const char *ovl_names[] = { 3389 [OMAP_DSS_GFX] = "GFX", 3390 [OMAP_DSS_VIDEO1] = "VID1", 3391 [OMAP_DSS_VIDEO2] = "VID2", 3392 [OMAP_DSS_VIDEO3] = "VID3", 3393 [OMAP_DSS_WB] = "WB", 3394 }; 3395 const char **p_names; 3396 3397 #define DUMPREG(r) seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(r)) 3398 3399 if (dispc_runtime_get()) 3400 return; 3401 3402 /* DISPC common registers */ 3403 DUMPREG(DISPC_REVISION); 3404 DUMPREG(DISPC_SYSCONFIG); 3405 DUMPREG(DISPC_SYSSTATUS); 3406 DUMPREG(DISPC_IRQSTATUS); 3407 DUMPREG(DISPC_IRQENABLE); 3408 DUMPREG(DISPC_CONTROL); 3409 DUMPREG(DISPC_CONFIG); 3410 DUMPREG(DISPC_CAPABLE); 3411 DUMPREG(DISPC_LINE_STATUS); 3412 DUMPREG(DISPC_LINE_NUMBER); 3413 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) || 3414 dss_has_feature(FEAT_ALPHA_FREE_ZORDER)) 3415 DUMPREG(DISPC_GLOBAL_ALPHA); 3416 if (dss_has_feature(FEAT_MGR_LCD2)) { 3417 DUMPREG(DISPC_CONTROL2); 3418 DUMPREG(DISPC_CONFIG2); 3419 } 3420 if (dss_has_feature(FEAT_MGR_LCD3)) { 3421 DUMPREG(DISPC_CONTROL3); 3422 DUMPREG(DISPC_CONFIG3); 3423 } 3424 if (dss_has_feature(FEAT_MFLAG)) 3425 DUMPREG(DISPC_GLOBAL_MFLAG_ATTRIBUTE); 3426 3427 #undef DUMPREG 3428 3429 #define DISPC_REG(i, name) name(i) 3430 #define DUMPREG(i, r) seq_printf(s, "%s(%s)%*s %08x\n", #r, p_names[i], \ 3431 (int)(48 - strlen(#r) - strlen(p_names[i])), " ", \ 3432 dispc_read_reg(DISPC_REG(i, r))) 3433 3434 p_names = mgr_names; 3435 3436 /* DISPC channel specific registers */ 3437 for (i = 0; i < dss_feat_get_num_mgrs(); i++) { 3438 DUMPREG(i, DISPC_DEFAULT_COLOR); 3439 DUMPREG(i, DISPC_TRANS_COLOR); 3440 DUMPREG(i, DISPC_SIZE_MGR); 3441 3442 if (i == OMAP_DSS_CHANNEL_DIGIT) 3443 continue; 3444 3445 DUMPREG(i, DISPC_TIMING_H); 3446 DUMPREG(i, DISPC_TIMING_V); 3447 DUMPREG(i, DISPC_POL_FREQ); 3448 DUMPREG(i, DISPC_DIVISORo); 3449 3450 DUMPREG(i, DISPC_DATA_CYCLE1); 3451 DUMPREG(i, DISPC_DATA_CYCLE2); 3452 DUMPREG(i, DISPC_DATA_CYCLE3); 3453 3454 if (dss_has_feature(FEAT_CPR)) { 3455 DUMPREG(i, DISPC_CPR_COEF_R); 3456 DUMPREG(i, DISPC_CPR_COEF_G); 3457 DUMPREG(i, DISPC_CPR_COEF_B); 3458 } 3459 } 3460 3461 p_names = ovl_names; 3462 3463 for (i = 0; i < dss_feat_get_num_ovls(); i++) { 3464 DUMPREG(i, DISPC_OVL_BA0); 3465 DUMPREG(i, DISPC_OVL_BA1); 3466 DUMPREG(i, DISPC_OVL_POSITION); 3467 DUMPREG(i, DISPC_OVL_SIZE); 3468 DUMPREG(i, DISPC_OVL_ATTRIBUTES); 3469 DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD); 3470 DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS); 3471 DUMPREG(i, DISPC_OVL_ROW_INC); 3472 DUMPREG(i, DISPC_OVL_PIXEL_INC); 3473 3474 if (dss_has_feature(FEAT_PRELOAD)) 3475 DUMPREG(i, DISPC_OVL_PRELOAD); 3476 if (dss_has_feature(FEAT_MFLAG)) 3477 DUMPREG(i, DISPC_OVL_MFLAG_THRESHOLD); 3478 3479 if (i == OMAP_DSS_GFX) { 3480 DUMPREG(i, DISPC_OVL_WINDOW_SKIP); 3481 DUMPREG(i, DISPC_OVL_TABLE_BA); 3482 continue; 3483 } 3484 3485 DUMPREG(i, DISPC_OVL_FIR); 3486 DUMPREG(i, DISPC_OVL_PICTURE_SIZE); 3487 DUMPREG(i, DISPC_OVL_ACCU0); 3488 DUMPREG(i, DISPC_OVL_ACCU1); 3489 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) { 3490 DUMPREG(i, DISPC_OVL_BA0_UV); 3491 DUMPREG(i, DISPC_OVL_BA1_UV); 3492 DUMPREG(i, DISPC_OVL_FIR2); 3493 DUMPREG(i, DISPC_OVL_ACCU2_0); 3494 DUMPREG(i, DISPC_OVL_ACCU2_1); 3495 } 3496 if (dss_has_feature(FEAT_ATTR2)) 3497 DUMPREG(i, DISPC_OVL_ATTRIBUTES2); 3498 } 3499 3500 if (dispc.feat->has_writeback) { 3501 i = OMAP_DSS_WB; 3502 DUMPREG(i, DISPC_OVL_BA0); 3503 DUMPREG(i, DISPC_OVL_BA1); 3504 DUMPREG(i, DISPC_OVL_SIZE); 3505 DUMPREG(i, DISPC_OVL_ATTRIBUTES); 3506 DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD); 3507 DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS); 3508 DUMPREG(i, DISPC_OVL_ROW_INC); 3509 DUMPREG(i, DISPC_OVL_PIXEL_INC); 3510 3511 if (dss_has_feature(FEAT_MFLAG)) 3512 DUMPREG(i, DISPC_OVL_MFLAG_THRESHOLD); 3513 3514 DUMPREG(i, DISPC_OVL_FIR); 3515 DUMPREG(i, DISPC_OVL_PICTURE_SIZE); 3516 DUMPREG(i, DISPC_OVL_ACCU0); 3517 DUMPREG(i, DISPC_OVL_ACCU1); 3518 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) { 3519 DUMPREG(i, DISPC_OVL_BA0_UV); 3520 DUMPREG(i, DISPC_OVL_BA1_UV); 3521 DUMPREG(i, DISPC_OVL_FIR2); 3522 DUMPREG(i, DISPC_OVL_ACCU2_0); 3523 DUMPREG(i, DISPC_OVL_ACCU2_1); 3524 } 3525 if (dss_has_feature(FEAT_ATTR2)) 3526 DUMPREG(i, DISPC_OVL_ATTRIBUTES2); 3527 } 3528 3529 #undef DISPC_REG 3530 #undef DUMPREG 3531 3532 #define DISPC_REG(plane, name, i) name(plane, i) 3533 #define DUMPREG(plane, name, i) \ 3534 seq_printf(s, "%s_%d(%s)%*s %08x\n", #name, i, p_names[plane], \ 3535 (int)(46 - strlen(#name) - strlen(p_names[plane])), " ", \ 3536 dispc_read_reg(DISPC_REG(plane, name, i))) 3537 3538 /* Video pipeline coefficient registers */ 3539 3540 /* start from OMAP_DSS_VIDEO1 */ 3541 for (i = 1; i < dss_feat_get_num_ovls(); i++) { 3542 for (j = 0; j < 8; j++) 3543 DUMPREG(i, DISPC_OVL_FIR_COEF_H, j); 3544 3545 for (j = 0; j < 8; j++) 3546 DUMPREG(i, DISPC_OVL_FIR_COEF_HV, j); 3547 3548 for (j = 0; j < 5; j++) 3549 DUMPREG(i, DISPC_OVL_CONV_COEF, j); 3550 3551 if (dss_has_feature(FEAT_FIR_COEF_V)) { 3552 for (j = 0; j < 8; j++) 3553 DUMPREG(i, DISPC_OVL_FIR_COEF_V, j); 3554 } 3555 3556 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) { 3557 for (j = 0; j < 8; j++) 3558 DUMPREG(i, DISPC_OVL_FIR_COEF_H2, j); 3559 3560 for (j = 0; j < 8; j++) 3561 DUMPREG(i, DISPC_OVL_FIR_COEF_HV2, j); 3562 3563 for (j = 0; j < 8; j++) 3564 DUMPREG(i, DISPC_OVL_FIR_COEF_V2, j); 3565 } 3566 } 3567 3568 dispc_runtime_put(); 3569 3570 #undef DISPC_REG 3571 #undef DUMPREG 3572 } 3573 3574 /* calculate clock rates using dividers in cinfo */ 3575 int dispc_calc_clock_rates(unsigned long dispc_fclk_rate, 3576 struct dispc_clock_info *cinfo) 3577 { 3578 if (cinfo->lck_div > 255 || cinfo->lck_div == 0) 3579 return -EINVAL; 3580 if (cinfo->pck_div < 1 || cinfo->pck_div > 255) 3581 return -EINVAL; 3582 3583 cinfo->lck = dispc_fclk_rate / cinfo->lck_div; 3584 cinfo->pck = cinfo->lck / cinfo->pck_div; 3585 3586 return 0; 3587 } 3588 3589 bool dispc_div_calc(unsigned long dispc, 3590 unsigned long pck_min, unsigned long pck_max, 3591 dispc_div_calc_func func, void *data) 3592 { 3593 int lckd, lckd_start, lckd_stop; 3594 int pckd, pckd_start, pckd_stop; 3595 unsigned long pck, lck; 3596 unsigned long lck_max; 3597 unsigned long pckd_hw_min, pckd_hw_max; 3598 unsigned min_fck_per_pck; 3599 unsigned long fck; 3600 3601 #ifdef CONFIG_FB_OMAP2_DSS_MIN_FCK_PER_PCK 3602 min_fck_per_pck = CONFIG_FB_OMAP2_DSS_MIN_FCK_PER_PCK; 3603 #else 3604 min_fck_per_pck = 0; 3605 #endif 3606 3607 pckd_hw_min = dss_feat_get_param_min(FEAT_PARAM_DSS_PCD); 3608 pckd_hw_max = dss_feat_get_param_max(FEAT_PARAM_DSS_PCD); 3609 3610 lck_max = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK); 3611 3612 pck_min = pck_min ? pck_min : 1; 3613 pck_max = pck_max ? pck_max : ULONG_MAX; 3614 3615 lckd_start = max(DIV_ROUND_UP(dispc, lck_max), 1ul); 3616 lckd_stop = min(dispc / pck_min, 255ul); 3617 3618 for (lckd = lckd_start; lckd <= lckd_stop; ++lckd) { 3619 lck = dispc / lckd; 3620 3621 pckd_start = max(DIV_ROUND_UP(lck, pck_max), pckd_hw_min); 3622 pckd_stop = min(lck / pck_min, pckd_hw_max); 3623 3624 for (pckd = pckd_start; pckd <= pckd_stop; ++pckd) { 3625 pck = lck / pckd; 3626 3627 /* 3628 * For OMAP2/3 the DISPC fclk is the same as LCD's logic 3629 * clock, which means we're configuring DISPC fclk here 3630 * also. Thus we need to use the calculated lck. For 3631 * OMAP4+ the DISPC fclk is a separate clock. 3632 */ 3633 if (dss_has_feature(FEAT_CORE_CLK_DIV)) 3634 fck = dispc_core_clk_rate(); 3635 else 3636 fck = lck; 3637 3638 if (fck < pck * min_fck_per_pck) 3639 continue; 3640 3641 if (func(lckd, pckd, lck, pck, data)) 3642 return true; 3643 } 3644 } 3645 3646 return false; 3647 } 3648 3649 void dispc_mgr_set_clock_div(enum omap_channel channel, 3650 const struct dispc_clock_info *cinfo) 3651 { 3652 DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div); 3653 DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div); 3654 3655 dispc_mgr_set_lcd_divisor(channel, cinfo->lck_div, cinfo->pck_div); 3656 } 3657 3658 int dispc_mgr_get_clock_div(enum omap_channel channel, 3659 struct dispc_clock_info *cinfo) 3660 { 3661 unsigned long fck; 3662 3663 fck = dispc_fclk_rate(); 3664 3665 cinfo->lck_div = REG_GET(DISPC_DIVISORo(channel), 23, 16); 3666 cinfo->pck_div = REG_GET(DISPC_DIVISORo(channel), 7, 0); 3667 3668 cinfo->lck = fck / cinfo->lck_div; 3669 cinfo->pck = cinfo->lck / cinfo->pck_div; 3670 3671 return 0; 3672 } 3673 3674 u32 dispc_read_irqstatus(void) 3675 { 3676 return dispc_read_reg(DISPC_IRQSTATUS); 3677 } 3678 EXPORT_SYMBOL(dispc_read_irqstatus); 3679 3680 void dispc_clear_irqstatus(u32 mask) 3681 { 3682 dispc_write_reg(DISPC_IRQSTATUS, mask); 3683 } 3684 EXPORT_SYMBOL(dispc_clear_irqstatus); 3685 3686 u32 dispc_read_irqenable(void) 3687 { 3688 return dispc_read_reg(DISPC_IRQENABLE); 3689 } 3690 EXPORT_SYMBOL(dispc_read_irqenable); 3691 3692 void dispc_write_irqenable(u32 mask) 3693 { 3694 u32 old_mask = dispc_read_reg(DISPC_IRQENABLE); 3695 3696 /* clear the irqstatus for newly enabled irqs */ 3697 dispc_clear_irqstatus((mask ^ old_mask) & mask); 3698 3699 dispc_write_reg(DISPC_IRQENABLE, mask); 3700 } 3701 EXPORT_SYMBOL(dispc_write_irqenable); 3702 3703 void dispc_enable_sidle(void) 3704 { 3705 REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3); /* SIDLEMODE: smart idle */ 3706 } 3707 3708 void dispc_disable_sidle(void) 3709 { 3710 REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3); /* SIDLEMODE: no idle */ 3711 } 3712 3713 static void _omap_dispc_initial_config(void) 3714 { 3715 u32 l; 3716 3717 /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */ 3718 if (dss_has_feature(FEAT_CORE_CLK_DIV)) { 3719 l = dispc_read_reg(DISPC_DIVISOR); 3720 /* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */ 3721 l = FLD_MOD(l, 1, 0, 0); 3722 l = FLD_MOD(l, 1, 23, 16); 3723 dispc_write_reg(DISPC_DIVISOR, l); 3724 3725 dispc.core_clk_rate = dispc_fclk_rate(); 3726 } 3727 3728 /* FUNCGATED */ 3729 if (dss_has_feature(FEAT_FUNCGATED)) 3730 REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9); 3731 3732 dispc_setup_color_conv_coef(); 3733 3734 dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY); 3735 3736 dispc_init_fifos(); 3737 3738 dispc_configure_burst_sizes(); 3739 3740 dispc_ovl_enable_zorder_planes(); 3741 3742 if (dispc.feat->mstandby_workaround) 3743 REG_FLD_MOD(DISPC_MSTANDBY_CTRL, 1, 0, 0); 3744 3745 if (dss_has_feature(FEAT_MFLAG)) 3746 dispc_init_mflag(); 3747 } 3748 3749 static const struct dispc_features omap24xx_dispc_feats = { 3750 .sw_start = 5, 3751 .fp_start = 15, 3752 .bp_start = 27, 3753 .sw_max = 64, 3754 .vp_max = 255, 3755 .hp_max = 256, 3756 .mgr_width_start = 10, 3757 .mgr_height_start = 26, 3758 .mgr_width_max = 2048, 3759 .mgr_height_max = 2048, 3760 .max_lcd_pclk = 66500000, 3761 .calc_scaling = dispc_ovl_calc_scaling_24xx, 3762 .calc_core_clk = calc_core_clk_24xx, 3763 .num_fifos = 3, 3764 .no_framedone_tv = true, 3765 .set_max_preload = false, 3766 .last_pixel_inc_missing = true, 3767 }; 3768 3769 static const struct dispc_features omap34xx_rev1_0_dispc_feats = { 3770 .sw_start = 5, 3771 .fp_start = 15, 3772 .bp_start = 27, 3773 .sw_max = 64, 3774 .vp_max = 255, 3775 .hp_max = 256, 3776 .mgr_width_start = 10, 3777 .mgr_height_start = 26, 3778 .mgr_width_max = 2048, 3779 .mgr_height_max = 2048, 3780 .max_lcd_pclk = 173000000, 3781 .max_tv_pclk = 59000000, 3782 .calc_scaling = dispc_ovl_calc_scaling_34xx, 3783 .calc_core_clk = calc_core_clk_34xx, 3784 .num_fifos = 3, 3785 .no_framedone_tv = true, 3786 .set_max_preload = false, 3787 .last_pixel_inc_missing = true, 3788 }; 3789 3790 static const struct dispc_features omap34xx_rev3_0_dispc_feats = { 3791 .sw_start = 7, 3792 .fp_start = 19, 3793 .bp_start = 31, 3794 .sw_max = 256, 3795 .vp_max = 4095, 3796 .hp_max = 4096, 3797 .mgr_width_start = 10, 3798 .mgr_height_start = 26, 3799 .mgr_width_max = 2048, 3800 .mgr_height_max = 2048, 3801 .max_lcd_pclk = 173000000, 3802 .max_tv_pclk = 59000000, 3803 .calc_scaling = dispc_ovl_calc_scaling_34xx, 3804 .calc_core_clk = calc_core_clk_34xx, 3805 .num_fifos = 3, 3806 .no_framedone_tv = true, 3807 .set_max_preload = false, 3808 .last_pixel_inc_missing = true, 3809 }; 3810 3811 static const struct dispc_features omap44xx_dispc_feats = { 3812 .sw_start = 7, 3813 .fp_start = 19, 3814 .bp_start = 31, 3815 .sw_max = 256, 3816 .vp_max = 4095, 3817 .hp_max = 4096, 3818 .mgr_width_start = 10, 3819 .mgr_height_start = 26, 3820 .mgr_width_max = 2048, 3821 .mgr_height_max = 2048, 3822 .max_lcd_pclk = 170000000, 3823 .max_tv_pclk = 185625000, 3824 .calc_scaling = dispc_ovl_calc_scaling_44xx, 3825 .calc_core_clk = calc_core_clk_44xx, 3826 .num_fifos = 5, 3827 .gfx_fifo_workaround = true, 3828 .set_max_preload = true, 3829 .supports_sync_align = true, 3830 .has_writeback = true, 3831 }; 3832 3833 static const struct dispc_features omap54xx_dispc_feats = { 3834 .sw_start = 7, 3835 .fp_start = 19, 3836 .bp_start = 31, 3837 .sw_max = 256, 3838 .vp_max = 4095, 3839 .hp_max = 4096, 3840 .mgr_width_start = 11, 3841 .mgr_height_start = 27, 3842 .mgr_width_max = 4096, 3843 .mgr_height_max = 4096, 3844 .max_lcd_pclk = 170000000, 3845 .max_tv_pclk = 186000000, 3846 .calc_scaling = dispc_ovl_calc_scaling_44xx, 3847 .calc_core_clk = calc_core_clk_44xx, 3848 .num_fifos = 5, 3849 .gfx_fifo_workaround = true, 3850 .mstandby_workaround = true, 3851 .set_max_preload = true, 3852 .supports_sync_align = true, 3853 .has_writeback = true, 3854 }; 3855 3856 static const struct dispc_features *dispc_get_features(void) 3857 { 3858 switch (omapdss_get_version()) { 3859 case OMAPDSS_VER_OMAP24xx: 3860 return &omap24xx_dispc_feats; 3861 3862 case OMAPDSS_VER_OMAP34xx_ES1: 3863 return &omap34xx_rev1_0_dispc_feats; 3864 3865 case OMAPDSS_VER_OMAP34xx_ES3: 3866 case OMAPDSS_VER_OMAP3630: 3867 case OMAPDSS_VER_AM35xx: 3868 case OMAPDSS_VER_AM43xx: 3869 return &omap34xx_rev3_0_dispc_feats; 3870 3871 case OMAPDSS_VER_OMAP4430_ES1: 3872 case OMAPDSS_VER_OMAP4430_ES2: 3873 case OMAPDSS_VER_OMAP4: 3874 return &omap44xx_dispc_feats; 3875 3876 case OMAPDSS_VER_OMAP5: 3877 case OMAPDSS_VER_DRA7xx: 3878 return &omap54xx_dispc_feats; 3879 3880 default: 3881 return NULL; 3882 } 3883 } 3884 3885 static irqreturn_t dispc_irq_handler(int irq, void *arg) 3886 { 3887 if (!dispc.is_enabled) 3888 return IRQ_NONE; 3889 3890 return dispc.user_handler(irq, dispc.user_data); 3891 } 3892 3893 int dispc_request_irq(irq_handler_t handler, void *dev_id) 3894 { 3895 int r; 3896 3897 if (dispc.user_handler != NULL) 3898 return -EBUSY; 3899 3900 dispc.user_handler = handler; 3901 dispc.user_data = dev_id; 3902 3903 /* ensure the dispc_irq_handler sees the values above */ 3904 smp_wmb(); 3905 3906 r = devm_request_irq(&dispc.pdev->dev, dispc.irq, dispc_irq_handler, 3907 IRQF_SHARED, "OMAP DISPC", &dispc); 3908 if (r) { 3909 dispc.user_handler = NULL; 3910 dispc.user_data = NULL; 3911 } 3912 3913 return r; 3914 } 3915 EXPORT_SYMBOL(dispc_request_irq); 3916 3917 void dispc_free_irq(void *dev_id) 3918 { 3919 devm_free_irq(&dispc.pdev->dev, dispc.irq, &dispc); 3920 3921 dispc.user_handler = NULL; 3922 dispc.user_data = NULL; 3923 } 3924 EXPORT_SYMBOL(dispc_free_irq); 3925 3926 /* DISPC HW IP initialisation */ 3927 static int dispc_bind(struct device *dev, struct device *master, void *data) 3928 { 3929 struct platform_device *pdev = to_platform_device(dev); 3930 u32 rev; 3931 int r = 0; 3932 struct resource *dispc_mem; 3933 struct device_node *np = pdev->dev.of_node; 3934 3935 dispc.pdev = pdev; 3936 3937 spin_lock_init(&dispc.control_lock); 3938 3939 dispc.feat = dispc_get_features(); 3940 if (!dispc.feat) 3941 return -ENODEV; 3942 3943 dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0); 3944 if (!dispc_mem) { 3945 DSSERR("can't get IORESOURCE_MEM DISPC\n"); 3946 return -EINVAL; 3947 } 3948 3949 dispc.base = devm_ioremap(&pdev->dev, dispc_mem->start, 3950 resource_size(dispc_mem)); 3951 if (!dispc.base) { 3952 DSSERR("can't ioremap DISPC\n"); 3953 return -ENOMEM; 3954 } 3955 3956 dispc.irq = platform_get_irq(dispc.pdev, 0); 3957 if (dispc.irq < 0) { 3958 DSSERR("platform_get_irq failed\n"); 3959 return -ENODEV; 3960 } 3961 3962 if (np && of_property_read_bool(np, "syscon-pol")) { 3963 dispc.syscon_pol = syscon_regmap_lookup_by_phandle(np, "syscon-pol"); 3964 if (IS_ERR(dispc.syscon_pol)) { 3965 dev_err(&pdev->dev, "failed to get syscon-pol regmap\n"); 3966 return PTR_ERR(dispc.syscon_pol); 3967 } 3968 3969 if (of_property_read_u32_index(np, "syscon-pol", 1, 3970 &dispc.syscon_pol_offset)) { 3971 dev_err(&pdev->dev, "failed to get syscon-pol offset\n"); 3972 return -EINVAL; 3973 } 3974 } 3975 3976 pm_runtime_enable(&pdev->dev); 3977 3978 r = dispc_runtime_get(); 3979 if (r) 3980 goto err_runtime_get; 3981 3982 _omap_dispc_initial_config(); 3983 3984 rev = dispc_read_reg(DISPC_REVISION); 3985 dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n", 3986 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0)); 3987 3988 dispc_runtime_put(); 3989 3990 dss_init_overlay_managers(); 3991 3992 dss_debugfs_create_file("dispc", dispc_dump_regs); 3993 3994 return 0; 3995 3996 err_runtime_get: 3997 pm_runtime_disable(&pdev->dev); 3998 return r; 3999 } 4000 4001 static void dispc_unbind(struct device *dev, struct device *master, 4002 void *data) 4003 { 4004 pm_runtime_disable(dev); 4005 4006 dss_uninit_overlay_managers(); 4007 } 4008 4009 static const struct component_ops dispc_component_ops = { 4010 .bind = dispc_bind, 4011 .unbind = dispc_unbind, 4012 }; 4013 4014 static int dispc_probe(struct platform_device *pdev) 4015 { 4016 return component_add(&pdev->dev, &dispc_component_ops); 4017 } 4018 4019 static int dispc_remove(struct platform_device *pdev) 4020 { 4021 component_del(&pdev->dev, &dispc_component_ops); 4022 return 0; 4023 } 4024 4025 static int dispc_runtime_suspend(struct device *dev) 4026 { 4027 dispc.is_enabled = false; 4028 /* ensure the dispc_irq_handler sees the is_enabled value */ 4029 smp_wmb(); 4030 /* wait for current handler to finish before turning the DISPC off */ 4031 synchronize_irq(dispc.irq); 4032 4033 dispc_save_context(); 4034 4035 return 0; 4036 } 4037 4038 static int dispc_runtime_resume(struct device *dev) 4039 { 4040 /* 4041 * The reset value for load mode is 0 (OMAP_DSS_LOAD_CLUT_AND_FRAME) 4042 * but we always initialize it to 2 (OMAP_DSS_LOAD_FRAME_ONLY) in 4043 * _omap_dispc_initial_config(). We can thus use it to detect if 4044 * we have lost register context. 4045 */ 4046 if (REG_GET(DISPC_CONFIG, 2, 1) != OMAP_DSS_LOAD_FRAME_ONLY) { 4047 _omap_dispc_initial_config(); 4048 4049 dispc_restore_context(); 4050 } 4051 4052 dispc.is_enabled = true; 4053 /* ensure the dispc_irq_handler sees the is_enabled value */ 4054 smp_wmb(); 4055 4056 return 0; 4057 } 4058 4059 static const struct dev_pm_ops dispc_pm_ops = { 4060 .runtime_suspend = dispc_runtime_suspend, 4061 .runtime_resume = dispc_runtime_resume, 4062 }; 4063 4064 static const struct of_device_id dispc_of_match[] = { 4065 { .compatible = "ti,omap2-dispc", }, 4066 { .compatible = "ti,omap3-dispc", }, 4067 { .compatible = "ti,omap4-dispc", }, 4068 { .compatible = "ti,omap5-dispc", }, 4069 { .compatible = "ti,dra7-dispc", }, 4070 {}, 4071 }; 4072 4073 static struct platform_driver omap_dispchw_driver = { 4074 .probe = dispc_probe, 4075 .remove = dispc_remove, 4076 .driver = { 4077 .name = "omapdss_dispc", 4078 .pm = &dispc_pm_ops, 4079 .of_match_table = dispc_of_match, 4080 .suppress_bind_attrs = true, 4081 }, 4082 }; 4083 4084 int __init dispc_init_platform_driver(void) 4085 { 4086 return platform_driver_register(&omap_dispchw_driver); 4087 } 4088 4089 void dispc_uninit_platform_driver(void) 4090 { 4091 platform_driver_unregister(&omap_dispchw_driver); 4092 } 4093