1 /* 2 * linux/drivers/video/nvidia/nvidia.c - nVidia fb driver 3 * 4 * Copyright 2004 Antonino Daplas <adaplas@pol.net> 5 * 6 * This file is subject to the terms and conditions of the GNU General Public 7 * License. See the file COPYING in the main directory of this archive 8 * for more details. 9 * 10 */ 11 12 #include <linux/module.h> 13 #include <linux/kernel.h> 14 #include <linux/errno.h> 15 #include <linux/string.h> 16 #include <linux/mm.h> 17 #include <linux/slab.h> 18 #include <linux/delay.h> 19 #include <linux/fb.h> 20 #include <linux/init.h> 21 #include <linux/pci.h> 22 #include <linux/console.h> 23 #include <linux/backlight.h> 24 #ifdef CONFIG_BOOTX_TEXT 25 #include <asm/btext.h> 26 #endif 27 28 #include "nv_local.h" 29 #include "nv_type.h" 30 #include "nv_proto.h" 31 #include "nv_dma.h" 32 33 #ifdef CONFIG_FB_NVIDIA_DEBUG 34 #define NVTRACE printk 35 #else 36 #define NVTRACE if (0) printk 37 #endif 38 39 #define NVTRACE_ENTER(...) NVTRACE("%s START\n", __func__) 40 #define NVTRACE_LEAVE(...) NVTRACE("%s END\n", __func__) 41 42 #ifdef CONFIG_FB_NVIDIA_DEBUG 43 #define assert(expr) \ 44 if (!(expr)) { \ 45 printk( "Assertion failed! %s,%s,%s,line=%d\n",\ 46 #expr,__FILE__,__func__,__LINE__); \ 47 BUG(); \ 48 } 49 #else 50 #define assert(expr) 51 #endif 52 53 #define PFX "nvidiafb: " 54 55 /* HW cursor parameters */ 56 #define MAX_CURS 32 57 58 static const struct pci_device_id nvidiafb_pci_tbl[] = { 59 {PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 60 PCI_BASE_CLASS_DISPLAY << 16, 0xff0000, 0}, 61 { 0, } 62 }; 63 MODULE_DEVICE_TABLE(pci, nvidiafb_pci_tbl); 64 65 /* command line data, set in nvidiafb_setup() */ 66 static int flatpanel = -1; /* Autodetect later */ 67 static int fpdither = -1; 68 static int forceCRTC = -1; 69 static int hwcur = 0; 70 static int noaccel = 0; 71 static int noscale = 0; 72 static int paneltweak = 0; 73 static int vram = 0; 74 static int bpp = 8; 75 static int reverse_i2c; 76 static bool nomtrr = false; 77 static int backlight = IS_BUILTIN(CONFIG_PMAC_BACKLIGHT); 78 79 static char *mode_option = NULL; 80 81 static struct fb_fix_screeninfo nvidiafb_fix = { 82 .type = FB_TYPE_PACKED_PIXELS, 83 .xpanstep = 8, 84 .ypanstep = 1, 85 }; 86 87 static struct fb_var_screeninfo nvidiafb_default_var = { 88 .xres = 640, 89 .yres = 480, 90 .xres_virtual = 640, 91 .yres_virtual = 480, 92 .bits_per_pixel = 8, 93 .red = {0, 8, 0}, 94 .green = {0, 8, 0}, 95 .blue = {0, 8, 0}, 96 .transp = {0, 0, 0}, 97 .activate = FB_ACTIVATE_NOW, 98 .height = -1, 99 .width = -1, 100 .pixclock = 39721, 101 .left_margin = 40, 102 .right_margin = 24, 103 .upper_margin = 32, 104 .lower_margin = 11, 105 .hsync_len = 96, 106 .vsync_len = 2, 107 .vmode = FB_VMODE_NONINTERLACED 108 }; 109 110 static void nvidiafb_load_cursor_image(struct nvidia_par *par, u8 * data8, 111 u16 bg, u16 fg, u32 w, u32 h) 112 { 113 u32 *data = (u32 *) data8; 114 int i, j, k = 0; 115 u32 b, tmp; 116 117 w = (w + 1) & ~1; 118 119 for (i = 0; i < h; i++) { 120 b = *data++; 121 reverse_order(&b); 122 123 for (j = 0; j < w / 2; j++) { 124 tmp = 0; 125 #if defined (__BIG_ENDIAN) 126 tmp = (b & (1 << 31)) ? fg << 16 : bg << 16; 127 b <<= 1; 128 tmp |= (b & (1 << 31)) ? fg : bg; 129 b <<= 1; 130 #else 131 tmp = (b & 1) ? fg : bg; 132 b >>= 1; 133 tmp |= (b & 1) ? fg << 16 : bg << 16; 134 b >>= 1; 135 #endif 136 NV_WR32(&par->CURSOR[k++], 0, tmp); 137 } 138 k += (MAX_CURS - w) / 2; 139 } 140 } 141 142 static void nvidia_write_clut(struct nvidia_par *par, 143 u8 regnum, u8 red, u8 green, u8 blue) 144 { 145 NVWriteDacMask(par, 0xff); 146 NVWriteDacWriteAddr(par, regnum); 147 NVWriteDacData(par, red); 148 NVWriteDacData(par, green); 149 NVWriteDacData(par, blue); 150 } 151 152 static void nvidia_read_clut(struct nvidia_par *par, 153 u8 regnum, u8 * red, u8 * green, u8 * blue) 154 { 155 NVWriteDacMask(par, 0xff); 156 NVWriteDacReadAddr(par, regnum); 157 *red = NVReadDacData(par); 158 *green = NVReadDacData(par); 159 *blue = NVReadDacData(par); 160 } 161 162 static int nvidia_panel_tweak(struct nvidia_par *par, 163 struct _riva_hw_state *state) 164 { 165 int tweak = 0; 166 167 if (par->paneltweak) { 168 tweak = par->paneltweak; 169 } else { 170 /* Begin flat panel hacks. 171 * This is unfortunate, but some chips need this register 172 * tweaked or else you get artifacts where adjacent pixels are 173 * swapped. There are no hard rules for what to set here so all 174 * we can do is experiment and apply hacks. 175 */ 176 if (((par->Chipset & 0xffff) == 0x0328) && (state->bpp == 32)) { 177 /* At least one NV34 laptop needs this workaround. */ 178 tweak = -1; 179 } 180 181 if ((par->Chipset & 0xfff0) == 0x0310) 182 tweak = 1; 183 /* end flat panel hacks */ 184 } 185 186 return tweak; 187 } 188 189 static void nvidia_screen_off(struct nvidia_par *par, int on) 190 { 191 unsigned char tmp; 192 193 if (on) { 194 /* 195 * Turn off screen and disable sequencer. 196 */ 197 tmp = NVReadSeq(par, 0x01); 198 199 NVWriteSeq(par, 0x00, 0x01); /* Synchronous Reset */ 200 NVWriteSeq(par, 0x01, tmp | 0x20); /* disable the display */ 201 } else { 202 /* 203 * Reenable sequencer, then turn on screen. 204 */ 205 206 tmp = NVReadSeq(par, 0x01); 207 208 NVWriteSeq(par, 0x01, tmp & ~0x20); /* reenable display */ 209 NVWriteSeq(par, 0x00, 0x03); /* End Reset */ 210 } 211 } 212 213 static void nvidia_save_vga(struct nvidia_par *par, 214 struct _riva_hw_state *state) 215 { 216 int i; 217 218 NVTRACE_ENTER(); 219 NVLockUnlock(par, 0); 220 221 NVUnloadStateExt(par, state); 222 223 state->misc_output = NVReadMiscOut(par); 224 225 for (i = 0; i < NUM_CRT_REGS; i++) 226 state->crtc[i] = NVReadCrtc(par, i); 227 228 for (i = 0; i < NUM_ATC_REGS; i++) 229 state->attr[i] = NVReadAttr(par, i); 230 231 for (i = 0; i < NUM_GRC_REGS; i++) 232 state->gra[i] = NVReadGr(par, i); 233 234 for (i = 0; i < NUM_SEQ_REGS; i++) 235 state->seq[i] = NVReadSeq(par, i); 236 NVTRACE_LEAVE(); 237 } 238 239 #undef DUMP_REG 240 241 static void nvidia_write_regs(struct nvidia_par *par, 242 struct _riva_hw_state *state) 243 { 244 int i; 245 246 NVTRACE_ENTER(); 247 248 NVLoadStateExt(par, state); 249 250 NVWriteMiscOut(par, state->misc_output); 251 252 for (i = 1; i < NUM_SEQ_REGS; i++) { 253 #ifdef DUMP_REG 254 printk(" SEQ[%02x] = %08x\n", i, state->seq[i]); 255 #endif 256 NVWriteSeq(par, i, state->seq[i]); 257 } 258 259 /* Ensure CRTC registers 0-7 are unlocked by clearing bit 7 of CRTC[17] */ 260 NVWriteCrtc(par, 0x11, state->crtc[0x11] & ~0x80); 261 262 for (i = 0; i < NUM_CRT_REGS; i++) { 263 switch (i) { 264 case 0x19: 265 case 0x20 ... 0x40: 266 break; 267 default: 268 #ifdef DUMP_REG 269 printk("CRTC[%02x] = %08x\n", i, state->crtc[i]); 270 #endif 271 NVWriteCrtc(par, i, state->crtc[i]); 272 } 273 } 274 275 for (i = 0; i < NUM_GRC_REGS; i++) { 276 #ifdef DUMP_REG 277 printk(" GRA[%02x] = %08x\n", i, state->gra[i]); 278 #endif 279 NVWriteGr(par, i, state->gra[i]); 280 } 281 282 for (i = 0; i < NUM_ATC_REGS; i++) { 283 #ifdef DUMP_REG 284 printk("ATTR[%02x] = %08x\n", i, state->attr[i]); 285 #endif 286 NVWriteAttr(par, i, state->attr[i]); 287 } 288 289 NVTRACE_LEAVE(); 290 } 291 292 static int nvidia_calc_regs(struct fb_info *info) 293 { 294 struct nvidia_par *par = info->par; 295 struct _riva_hw_state *state = &par->ModeReg; 296 int i, depth = fb_get_color_depth(&info->var, &info->fix); 297 int h_display = info->var.xres / 8 - 1; 298 int h_start = (info->var.xres + info->var.right_margin) / 8 - 1; 299 int h_end = (info->var.xres + info->var.right_margin + 300 info->var.hsync_len) / 8 - 1; 301 int h_total = (info->var.xres + info->var.right_margin + 302 info->var.hsync_len + info->var.left_margin) / 8 - 5; 303 int h_blank_s = h_display; 304 int h_blank_e = h_total + 4; 305 int v_display = info->var.yres - 1; 306 int v_start = info->var.yres + info->var.lower_margin - 1; 307 int v_end = (info->var.yres + info->var.lower_margin + 308 info->var.vsync_len) - 1; 309 int v_total = (info->var.yres + info->var.lower_margin + 310 info->var.vsync_len + info->var.upper_margin) - 2; 311 int v_blank_s = v_display; 312 int v_blank_e = v_total + 1; 313 314 /* 315 * Set all CRTC values. 316 */ 317 318 if (info->var.vmode & FB_VMODE_INTERLACED) 319 v_total |= 1; 320 321 if (par->FlatPanel == 1) { 322 v_start = v_total - 3; 323 v_end = v_total - 2; 324 v_blank_s = v_start; 325 h_start = h_total - 5; 326 h_end = h_total - 2; 327 h_blank_e = h_total + 4; 328 } 329 330 state->crtc[0x0] = Set8Bits(h_total); 331 state->crtc[0x1] = Set8Bits(h_display); 332 state->crtc[0x2] = Set8Bits(h_blank_s); 333 state->crtc[0x3] = SetBitField(h_blank_e, 4: 0, 4:0) 334 | SetBit(7); 335 state->crtc[0x4] = Set8Bits(h_start); 336 state->crtc[0x5] = SetBitField(h_blank_e, 5: 5, 7:7) 337 | SetBitField(h_end, 4: 0, 4:0); 338 state->crtc[0x6] = SetBitField(v_total, 7: 0, 7:0); 339 state->crtc[0x7] = SetBitField(v_total, 8: 8, 0:0) 340 | SetBitField(v_display, 8: 8, 1:1) 341 | SetBitField(v_start, 8: 8, 2:2) 342 | SetBitField(v_blank_s, 8: 8, 3:3) 343 | SetBit(4) 344 | SetBitField(v_total, 9: 9, 5:5) 345 | SetBitField(v_display, 9: 9, 6:6) 346 | SetBitField(v_start, 9: 9, 7:7); 347 state->crtc[0x9] = SetBitField(v_blank_s, 9: 9, 5:5) 348 | SetBit(6) 349 | ((info->var.vmode & FB_VMODE_DOUBLE) ? 0x80 : 0x00); 350 state->crtc[0x10] = Set8Bits(v_start); 351 state->crtc[0x11] = SetBitField(v_end, 3: 0, 3:0) | SetBit(5); 352 state->crtc[0x12] = Set8Bits(v_display); 353 state->crtc[0x13] = ((info->var.xres_virtual / 8) * 354 (info->var.bits_per_pixel / 8)); 355 state->crtc[0x15] = Set8Bits(v_blank_s); 356 state->crtc[0x16] = Set8Bits(v_blank_e); 357 358 state->attr[0x10] = 0x01; 359 360 if (par->Television) 361 state->attr[0x11] = 0x00; 362 363 state->screen = SetBitField(h_blank_e, 6: 6, 4:4) 364 | SetBitField(v_blank_s, 10: 10, 3:3) 365 | SetBitField(v_start, 10: 10, 2:2) 366 | SetBitField(v_display, 10: 10, 1:1) 367 | SetBitField(v_total, 10: 10, 0:0); 368 369 state->horiz = SetBitField(h_total, 8: 8, 0:0) 370 | SetBitField(h_display, 8: 8, 1:1) 371 | SetBitField(h_blank_s, 8: 8, 2:2) 372 | SetBitField(h_start, 8: 8, 3:3); 373 374 state->extra = SetBitField(v_total, 11: 11, 0:0) 375 | SetBitField(v_display, 11: 11, 2:2) 376 | SetBitField(v_start, 11: 11, 4:4) 377 | SetBitField(v_blank_s, 11: 11, 6:6); 378 379 if (info->var.vmode & FB_VMODE_INTERLACED) { 380 h_total = (h_total >> 1) & ~1; 381 state->interlace = Set8Bits(h_total); 382 state->horiz |= SetBitField(h_total, 8: 8, 4:4); 383 } else { 384 state->interlace = 0xff; /* interlace off */ 385 } 386 387 /* 388 * Calculate the extended registers. 389 */ 390 391 if (depth < 24) 392 i = depth; 393 else 394 i = 32; 395 396 if (par->Architecture >= NV_ARCH_10) 397 par->CURSOR = (volatile u32 __iomem *)(info->screen_base + 398 par->CursorStart); 399 400 if (info->var.sync & FB_SYNC_HOR_HIGH_ACT) 401 state->misc_output &= ~0x40; 402 else 403 state->misc_output |= 0x40; 404 if (info->var.sync & FB_SYNC_VERT_HIGH_ACT) 405 state->misc_output &= ~0x80; 406 else 407 state->misc_output |= 0x80; 408 409 NVCalcStateExt(par, state, i, info->var.xres_virtual, 410 info->var.xres, info->var.yres_virtual, 411 1000000000 / info->var.pixclock, info->var.vmode); 412 413 state->scale = NV_RD32(par->PRAMDAC, 0x00000848) & 0xfff000ff; 414 if (par->FlatPanel == 1) { 415 state->pixel |= (1 << 7); 416 417 if (!par->fpScaler || (par->fpWidth <= info->var.xres) 418 || (par->fpHeight <= info->var.yres)) { 419 state->scale |= (1 << 8); 420 } 421 422 if (!par->crtcSync_read) { 423 state->crtcSync = NV_RD32(par->PRAMDAC, 0x0828); 424 par->crtcSync_read = 1; 425 } 426 427 par->PanelTweak = nvidia_panel_tweak(par, state); 428 } 429 430 state->vpll = state->pll; 431 state->vpll2 = state->pll; 432 state->vpllB = state->pllB; 433 state->vpll2B = state->pllB; 434 435 VGA_WR08(par->PCIO, 0x03D4, 0x1C); 436 state->fifo = VGA_RD08(par->PCIO, 0x03D5) & ~(1<<5); 437 438 if (par->CRTCnumber) { 439 state->head = NV_RD32(par->PCRTC0, 0x00000860) & ~0x00001000; 440 state->head2 = NV_RD32(par->PCRTC0, 0x00002860) | 0x00001000; 441 state->crtcOwner = 3; 442 state->pllsel |= 0x20000800; 443 state->vpll = NV_RD32(par->PRAMDAC0, 0x00000508); 444 if (par->twoStagePLL) 445 state->vpllB = NV_RD32(par->PRAMDAC0, 0x00000578); 446 } else if (par->twoHeads) { 447 state->head = NV_RD32(par->PCRTC0, 0x00000860) | 0x00001000; 448 state->head2 = NV_RD32(par->PCRTC0, 0x00002860) & ~0x00001000; 449 state->crtcOwner = 0; 450 state->vpll2 = NV_RD32(par->PRAMDAC0, 0x0520); 451 if (par->twoStagePLL) 452 state->vpll2B = NV_RD32(par->PRAMDAC0, 0x057C); 453 } 454 455 state->cursorConfig = 0x00000100; 456 457 if (info->var.vmode & FB_VMODE_DOUBLE) 458 state->cursorConfig |= (1 << 4); 459 460 if (par->alphaCursor) { 461 if ((par->Chipset & 0x0ff0) != 0x0110) 462 state->cursorConfig |= 0x04011000; 463 else 464 state->cursorConfig |= 0x14011000; 465 state->general |= (1 << 29); 466 } else 467 state->cursorConfig |= 0x02000000; 468 469 if (par->twoHeads) { 470 if ((par->Chipset & 0x0ff0) == 0x0110) { 471 state->dither = NV_RD32(par->PRAMDAC, 0x0528) & 472 ~0x00010000; 473 if (par->FPDither) 474 state->dither |= 0x00010000; 475 } else { 476 state->dither = NV_RD32(par->PRAMDAC, 0x083C) & ~1; 477 if (par->FPDither) 478 state->dither |= 1; 479 } 480 } 481 482 state->timingH = 0; 483 state->timingV = 0; 484 state->displayV = info->var.xres; 485 486 return 0; 487 } 488 489 static void nvidia_init_vga(struct fb_info *info) 490 { 491 struct nvidia_par *par = info->par; 492 struct _riva_hw_state *state = &par->ModeReg; 493 int i; 494 495 for (i = 0; i < 0x10; i++) 496 state->attr[i] = i; 497 state->attr[0x10] = 0x41; 498 state->attr[0x11] = 0xff; 499 state->attr[0x12] = 0x0f; 500 state->attr[0x13] = 0x00; 501 state->attr[0x14] = 0x00; 502 503 memset(state->crtc, 0x00, NUM_CRT_REGS); 504 state->crtc[0x0a] = 0x20; 505 state->crtc[0x17] = 0xe3; 506 state->crtc[0x18] = 0xff; 507 state->crtc[0x28] = 0x40; 508 509 memset(state->gra, 0x00, NUM_GRC_REGS); 510 state->gra[0x05] = 0x40; 511 state->gra[0x06] = 0x05; 512 state->gra[0x07] = 0x0f; 513 state->gra[0x08] = 0xff; 514 515 state->seq[0x00] = 0x03; 516 state->seq[0x01] = 0x01; 517 state->seq[0x02] = 0x0f; 518 state->seq[0x03] = 0x00; 519 state->seq[0x04] = 0x0e; 520 521 state->misc_output = 0xeb; 522 } 523 524 static int nvidiafb_cursor(struct fb_info *info, struct fb_cursor *cursor) 525 { 526 struct nvidia_par *par = info->par; 527 u8 data[MAX_CURS * MAX_CURS / 8]; 528 int i, set = cursor->set; 529 u16 fg, bg; 530 531 if (cursor->image.width > MAX_CURS || cursor->image.height > MAX_CURS) 532 return -ENXIO; 533 534 NVShowHideCursor(par, 0); 535 536 if (par->cursor_reset) { 537 set = FB_CUR_SETALL; 538 par->cursor_reset = 0; 539 } 540 541 if (set & FB_CUR_SETSIZE) 542 memset_io(par->CURSOR, 0, MAX_CURS * MAX_CURS * 2); 543 544 if (set & FB_CUR_SETPOS) { 545 u32 xx, yy, temp; 546 547 yy = cursor->image.dy - info->var.yoffset; 548 xx = cursor->image.dx - info->var.xoffset; 549 temp = xx & 0xFFFF; 550 temp |= yy << 16; 551 552 NV_WR32(par->PRAMDAC, 0x0000300, temp); 553 } 554 555 if (set & (FB_CUR_SETSHAPE | FB_CUR_SETCMAP | FB_CUR_SETIMAGE)) { 556 u32 bg_idx = cursor->image.bg_color; 557 u32 fg_idx = cursor->image.fg_color; 558 u32 s_pitch = (cursor->image.width + 7) >> 3; 559 u32 d_pitch = MAX_CURS / 8; 560 u8 *dat = (u8 *) cursor->image.data; 561 u8 *msk = (u8 *) cursor->mask; 562 u8 *src; 563 564 src = kmalloc_array(s_pitch, cursor->image.height, GFP_ATOMIC); 565 566 if (src) { 567 switch (cursor->rop) { 568 case ROP_XOR: 569 for (i = 0; i < s_pitch * cursor->image.height; i++) 570 src[i] = dat[i] ^ msk[i]; 571 break; 572 case ROP_COPY: 573 default: 574 for (i = 0; i < s_pitch * cursor->image.height; i++) 575 src[i] = dat[i] & msk[i]; 576 break; 577 } 578 579 fb_pad_aligned_buffer(data, d_pitch, src, s_pitch, 580 cursor->image.height); 581 582 bg = ((info->cmap.red[bg_idx] & 0xf8) << 7) | 583 ((info->cmap.green[bg_idx] & 0xf8) << 2) | 584 ((info->cmap.blue[bg_idx] & 0xf8) >> 3) | 1 << 15; 585 586 fg = ((info->cmap.red[fg_idx] & 0xf8) << 7) | 587 ((info->cmap.green[fg_idx] & 0xf8) << 2) | 588 ((info->cmap.blue[fg_idx] & 0xf8) >> 3) | 1 << 15; 589 590 NVLockUnlock(par, 0); 591 592 nvidiafb_load_cursor_image(par, data, bg, fg, 593 cursor->image.width, 594 cursor->image.height); 595 kfree(src); 596 } 597 } 598 599 if (cursor->enable) 600 NVShowHideCursor(par, 1); 601 602 return 0; 603 } 604 605 static struct fb_ops nvidia_fb_ops; 606 607 static int nvidiafb_set_par(struct fb_info *info) 608 { 609 struct nvidia_par *par = info->par; 610 611 NVTRACE_ENTER(); 612 613 NVLockUnlock(par, 1); 614 if (!par->FlatPanel || !par->twoHeads) 615 par->FPDither = 0; 616 617 if (par->FPDither < 0) { 618 if ((par->Chipset & 0x0ff0) == 0x0110) 619 par->FPDither = !!(NV_RD32(par->PRAMDAC, 0x0528) 620 & 0x00010000); 621 else 622 par->FPDither = !!(NV_RD32(par->PRAMDAC, 0x083C) & 1); 623 printk(KERN_INFO PFX "Flat panel dithering %s\n", 624 par->FPDither ? "enabled" : "disabled"); 625 } 626 627 info->fix.visual = (info->var.bits_per_pixel == 8) ? 628 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR; 629 630 nvidia_init_vga(info); 631 nvidia_calc_regs(info); 632 633 NVLockUnlock(par, 0); 634 if (par->twoHeads) { 635 VGA_WR08(par->PCIO, 0x03D4, 0x44); 636 VGA_WR08(par->PCIO, 0x03D5, par->ModeReg.crtcOwner); 637 NVLockUnlock(par, 0); 638 } 639 640 nvidia_screen_off(par, 1); 641 642 nvidia_write_regs(par, &par->ModeReg); 643 NVSetStartAddress(par, 0); 644 645 #if defined (__BIG_ENDIAN) 646 /* turn on LFB swapping */ 647 { 648 unsigned char tmp; 649 650 VGA_WR08(par->PCIO, 0x3d4, 0x46); 651 tmp = VGA_RD08(par->PCIO, 0x3d5); 652 tmp |= (1 << 7); 653 VGA_WR08(par->PCIO, 0x3d5, tmp); 654 } 655 #endif 656 657 info->fix.line_length = (info->var.xres_virtual * 658 info->var.bits_per_pixel) >> 3; 659 if (info->var.accel_flags) { 660 nvidia_fb_ops.fb_imageblit = nvidiafb_imageblit; 661 nvidia_fb_ops.fb_fillrect = nvidiafb_fillrect; 662 nvidia_fb_ops.fb_copyarea = nvidiafb_copyarea; 663 nvidia_fb_ops.fb_sync = nvidiafb_sync; 664 info->pixmap.scan_align = 4; 665 info->flags &= ~FBINFO_HWACCEL_DISABLED; 666 info->flags |= FBINFO_READS_FAST; 667 NVResetGraphics(info); 668 } else { 669 nvidia_fb_ops.fb_imageblit = cfb_imageblit; 670 nvidia_fb_ops.fb_fillrect = cfb_fillrect; 671 nvidia_fb_ops.fb_copyarea = cfb_copyarea; 672 nvidia_fb_ops.fb_sync = NULL; 673 info->pixmap.scan_align = 1; 674 info->flags |= FBINFO_HWACCEL_DISABLED; 675 info->flags &= ~FBINFO_READS_FAST; 676 } 677 678 par->cursor_reset = 1; 679 680 nvidia_screen_off(par, 0); 681 682 #ifdef CONFIG_BOOTX_TEXT 683 /* Update debug text engine */ 684 btext_update_display(info->fix.smem_start, 685 info->var.xres, info->var.yres, 686 info->var.bits_per_pixel, info->fix.line_length); 687 #endif 688 689 NVLockUnlock(par, 0); 690 NVTRACE_LEAVE(); 691 return 0; 692 } 693 694 static int nvidiafb_setcolreg(unsigned regno, unsigned red, unsigned green, 695 unsigned blue, unsigned transp, 696 struct fb_info *info) 697 { 698 struct nvidia_par *par = info->par; 699 int i; 700 701 NVTRACE_ENTER(); 702 if (regno >= (1 << info->var.green.length)) 703 return -EINVAL; 704 705 if (info->var.grayscale) { 706 /* gray = 0.30*R + 0.59*G + 0.11*B */ 707 red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8; 708 } 709 710 if (regno < 16 && info->fix.visual == FB_VISUAL_DIRECTCOLOR) { 711 ((u32 *) info->pseudo_palette)[regno] = 712 (regno << info->var.red.offset) | 713 (regno << info->var.green.offset) | 714 (regno << info->var.blue.offset); 715 } 716 717 switch (info->var.bits_per_pixel) { 718 case 8: 719 /* "transparent" stuff is completely ignored. */ 720 nvidia_write_clut(par, regno, red >> 8, green >> 8, blue >> 8); 721 break; 722 case 16: 723 if (info->var.green.length == 5) { 724 for (i = 0; i < 8; i++) { 725 nvidia_write_clut(par, regno * 8 + i, red >> 8, 726 green >> 8, blue >> 8); 727 } 728 } else { 729 u8 r, g, b; 730 731 if (regno < 32) { 732 for (i = 0; i < 8; i++) { 733 nvidia_write_clut(par, regno * 8 + i, 734 red >> 8, green >> 8, 735 blue >> 8); 736 } 737 } 738 739 nvidia_read_clut(par, regno * 4, &r, &g, &b); 740 741 for (i = 0; i < 4; i++) 742 nvidia_write_clut(par, regno * 4 + i, r, 743 green >> 8, b); 744 } 745 break; 746 case 32: 747 nvidia_write_clut(par, regno, red >> 8, green >> 8, blue >> 8); 748 break; 749 default: 750 /* do nothing */ 751 break; 752 } 753 754 NVTRACE_LEAVE(); 755 return 0; 756 } 757 758 static int nvidiafb_check_var(struct fb_var_screeninfo *var, 759 struct fb_info *info) 760 { 761 struct nvidia_par *par = info->par; 762 int memlen, vramlen, mode_valid = 0; 763 int pitch, err = 0; 764 765 NVTRACE_ENTER(); 766 767 var->transp.offset = 0; 768 var->transp.length = 0; 769 770 var->xres &= ~7; 771 772 if (var->bits_per_pixel <= 8) 773 var->bits_per_pixel = 8; 774 else if (var->bits_per_pixel <= 16) 775 var->bits_per_pixel = 16; 776 else 777 var->bits_per_pixel = 32; 778 779 switch (var->bits_per_pixel) { 780 case 8: 781 var->red.offset = 0; 782 var->red.length = 8; 783 var->green.offset = 0; 784 var->green.length = 8; 785 var->blue.offset = 0; 786 var->blue.length = 8; 787 var->transp.offset = 0; 788 var->transp.length = 0; 789 break; 790 case 16: 791 var->green.length = (var->green.length < 6) ? 5 : 6; 792 var->red.length = 5; 793 var->blue.length = 5; 794 var->transp.length = 6 - var->green.length; 795 var->blue.offset = 0; 796 var->green.offset = 5; 797 var->red.offset = 5 + var->green.length; 798 var->transp.offset = (5 + var->red.offset) & 15; 799 break; 800 case 32: /* RGBA 8888 */ 801 var->red.offset = 16; 802 var->red.length = 8; 803 var->green.offset = 8; 804 var->green.length = 8; 805 var->blue.offset = 0; 806 var->blue.length = 8; 807 var->transp.length = 8; 808 var->transp.offset = 24; 809 break; 810 } 811 812 var->red.msb_right = 0; 813 var->green.msb_right = 0; 814 var->blue.msb_right = 0; 815 var->transp.msb_right = 0; 816 817 if (!info->monspecs.hfmax || !info->monspecs.vfmax || 818 !info->monspecs.dclkmax || !fb_validate_mode(var, info)) 819 mode_valid = 1; 820 821 /* calculate modeline if supported by monitor */ 822 if (!mode_valid && info->monspecs.gtf) { 823 if (!fb_get_mode(FB_MAXTIMINGS, 0, var, info)) 824 mode_valid = 1; 825 } 826 827 if (!mode_valid) { 828 const struct fb_videomode *mode; 829 830 mode = fb_find_best_mode(var, &info->modelist); 831 if (mode) { 832 fb_videomode_to_var(var, mode); 833 mode_valid = 1; 834 } 835 } 836 837 if (!mode_valid && info->monspecs.modedb_len) 838 return -EINVAL; 839 840 /* 841 * If we're on a flat panel, check if the mode is outside of the 842 * panel dimensions. If so, cap it and try for the next best mode 843 * before bailing out. 844 */ 845 if (par->fpWidth && par->fpHeight && (par->fpWidth < var->xres || 846 par->fpHeight < var->yres)) { 847 const struct fb_videomode *mode; 848 849 var->xres = par->fpWidth; 850 var->yres = par->fpHeight; 851 852 mode = fb_find_best_mode(var, &info->modelist); 853 if (!mode) { 854 printk(KERN_ERR PFX "mode out of range of flat " 855 "panel dimensions\n"); 856 return -EINVAL; 857 } 858 859 fb_videomode_to_var(var, mode); 860 } 861 862 if (var->yres_virtual < var->yres) 863 var->yres_virtual = var->yres; 864 865 if (var->xres_virtual < var->xres) 866 var->xres_virtual = var->xres; 867 868 var->xres_virtual = (var->xres_virtual + 63) & ~63; 869 870 vramlen = info->screen_size; 871 pitch = ((var->xres_virtual * var->bits_per_pixel) + 7) / 8; 872 memlen = pitch * var->yres_virtual; 873 874 if (memlen > vramlen) { 875 var->yres_virtual = vramlen / pitch; 876 877 if (var->yres_virtual < var->yres) { 878 var->yres_virtual = var->yres; 879 var->xres_virtual = vramlen / var->yres_virtual; 880 var->xres_virtual /= var->bits_per_pixel / 8; 881 var->xres_virtual &= ~63; 882 pitch = (var->xres_virtual * 883 var->bits_per_pixel + 7) / 8; 884 memlen = pitch * var->yres; 885 886 if (var->xres_virtual < var->xres) { 887 printk("nvidiafb: required video memory, " 888 "%d bytes, for %dx%d-%d (virtual) " 889 "is out of range\n", 890 memlen, var->xres_virtual, 891 var->yres_virtual, var->bits_per_pixel); 892 err = -ENOMEM; 893 } 894 } 895 } 896 897 if (var->accel_flags) { 898 if (var->yres_virtual > 0x7fff) 899 var->yres_virtual = 0x7fff; 900 if (var->xres_virtual > 0x7fff) 901 var->xres_virtual = 0x7fff; 902 } 903 904 var->xres_virtual &= ~63; 905 906 NVTRACE_LEAVE(); 907 908 return err; 909 } 910 911 static int nvidiafb_pan_display(struct fb_var_screeninfo *var, 912 struct fb_info *info) 913 { 914 struct nvidia_par *par = info->par; 915 u32 total; 916 917 total = var->yoffset * info->fix.line_length + var->xoffset; 918 919 NVSetStartAddress(par, total); 920 921 return 0; 922 } 923 924 static int nvidiafb_blank(int blank, struct fb_info *info) 925 { 926 struct nvidia_par *par = info->par; 927 unsigned char tmp, vesa; 928 929 tmp = NVReadSeq(par, 0x01) & ~0x20; /* screen on/off */ 930 vesa = NVReadCrtc(par, 0x1a) & ~0xc0; /* sync on/off */ 931 932 NVTRACE_ENTER(); 933 934 if (blank) 935 tmp |= 0x20; 936 937 switch (blank) { 938 case FB_BLANK_UNBLANK: 939 case FB_BLANK_NORMAL: 940 break; 941 case FB_BLANK_VSYNC_SUSPEND: 942 vesa |= 0x80; 943 break; 944 case FB_BLANK_HSYNC_SUSPEND: 945 vesa |= 0x40; 946 break; 947 case FB_BLANK_POWERDOWN: 948 vesa |= 0xc0; 949 break; 950 } 951 952 NVWriteSeq(par, 0x01, tmp); 953 NVWriteCrtc(par, 0x1a, vesa); 954 955 NVTRACE_LEAVE(); 956 957 return 0; 958 } 959 960 /* 961 * Because the VGA registers are not mapped linearly in its MMIO space, 962 * restrict VGA register saving and restore to x86 only, where legacy VGA IO 963 * access is legal. Consequently, we must also check if the device is the 964 * primary display. 965 */ 966 #ifdef CONFIG_X86 967 static void save_vga_x86(struct nvidia_par *par) 968 { 969 struct resource *res= &par->pci_dev->resource[PCI_ROM_RESOURCE]; 970 971 if (res && res->flags & IORESOURCE_ROM_SHADOW) { 972 memset(&par->vgastate, 0, sizeof(par->vgastate)); 973 par->vgastate.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS | 974 VGA_SAVE_CMAP; 975 save_vga(&par->vgastate); 976 } 977 } 978 979 static void restore_vga_x86(struct nvidia_par *par) 980 { 981 struct resource *res= &par->pci_dev->resource[PCI_ROM_RESOURCE]; 982 983 if (res && res->flags & IORESOURCE_ROM_SHADOW) 984 restore_vga(&par->vgastate); 985 } 986 #else 987 #define save_vga_x86(x) do {} while (0) 988 #define restore_vga_x86(x) do {} while (0) 989 #endif /* X86 */ 990 991 static int nvidiafb_open(struct fb_info *info, int user) 992 { 993 struct nvidia_par *par = info->par; 994 995 if (!par->open_count) { 996 save_vga_x86(par); 997 nvidia_save_vga(par, &par->initial_state); 998 } 999 1000 par->open_count++; 1001 return 0; 1002 } 1003 1004 static int nvidiafb_release(struct fb_info *info, int user) 1005 { 1006 struct nvidia_par *par = info->par; 1007 int err = 0; 1008 1009 if (!par->open_count) { 1010 err = -EINVAL; 1011 goto done; 1012 } 1013 1014 if (par->open_count == 1) { 1015 nvidia_write_regs(par, &par->initial_state); 1016 restore_vga_x86(par); 1017 } 1018 1019 par->open_count--; 1020 done: 1021 return err; 1022 } 1023 1024 static struct fb_ops nvidia_fb_ops = { 1025 .owner = THIS_MODULE, 1026 .fb_open = nvidiafb_open, 1027 .fb_release = nvidiafb_release, 1028 .fb_check_var = nvidiafb_check_var, 1029 .fb_set_par = nvidiafb_set_par, 1030 .fb_setcolreg = nvidiafb_setcolreg, 1031 .fb_pan_display = nvidiafb_pan_display, 1032 .fb_blank = nvidiafb_blank, 1033 .fb_fillrect = nvidiafb_fillrect, 1034 .fb_copyarea = nvidiafb_copyarea, 1035 .fb_imageblit = nvidiafb_imageblit, 1036 .fb_cursor = nvidiafb_cursor, 1037 .fb_sync = nvidiafb_sync, 1038 }; 1039 1040 #ifdef CONFIG_PM 1041 static int nvidiafb_suspend(struct pci_dev *dev, pm_message_t mesg) 1042 { 1043 struct fb_info *info = pci_get_drvdata(dev); 1044 struct nvidia_par *par = info->par; 1045 1046 if (mesg.event == PM_EVENT_PRETHAW) 1047 mesg.event = PM_EVENT_FREEZE; 1048 console_lock(); 1049 par->pm_state = mesg.event; 1050 1051 if (mesg.event & PM_EVENT_SLEEP) { 1052 fb_set_suspend(info, 1); 1053 nvidiafb_blank(FB_BLANK_POWERDOWN, info); 1054 nvidia_write_regs(par, &par->SavedReg); 1055 pci_save_state(dev); 1056 pci_disable_device(dev); 1057 pci_set_power_state(dev, pci_choose_state(dev, mesg)); 1058 } 1059 dev->dev.power.power_state = mesg; 1060 1061 console_unlock(); 1062 return 0; 1063 } 1064 1065 static int nvidiafb_resume(struct pci_dev *dev) 1066 { 1067 struct fb_info *info = pci_get_drvdata(dev); 1068 struct nvidia_par *par = info->par; 1069 1070 console_lock(); 1071 pci_set_power_state(dev, PCI_D0); 1072 1073 if (par->pm_state != PM_EVENT_FREEZE) { 1074 pci_restore_state(dev); 1075 1076 if (pci_enable_device(dev)) 1077 goto fail; 1078 1079 pci_set_master(dev); 1080 } 1081 1082 par->pm_state = PM_EVENT_ON; 1083 nvidiafb_set_par(info); 1084 fb_set_suspend (info, 0); 1085 nvidiafb_blank(FB_BLANK_UNBLANK, info); 1086 1087 fail: 1088 console_unlock(); 1089 return 0; 1090 } 1091 #else 1092 #define nvidiafb_suspend NULL 1093 #define nvidiafb_resume NULL 1094 #endif 1095 1096 static int nvidia_set_fbinfo(struct fb_info *info) 1097 { 1098 struct fb_monspecs *specs = &info->monspecs; 1099 struct fb_videomode modedb; 1100 struct nvidia_par *par = info->par; 1101 int lpitch; 1102 1103 NVTRACE_ENTER(); 1104 info->flags = FBINFO_DEFAULT 1105 | FBINFO_HWACCEL_IMAGEBLIT 1106 | FBINFO_HWACCEL_FILLRECT 1107 | FBINFO_HWACCEL_COPYAREA 1108 | FBINFO_HWACCEL_YPAN; 1109 1110 fb_videomode_to_modelist(info->monspecs.modedb, 1111 info->monspecs.modedb_len, &info->modelist); 1112 fb_var_to_videomode(&modedb, &nvidiafb_default_var); 1113 1114 switch (bpp) { 1115 case 0 ... 8: 1116 bpp = 8; 1117 break; 1118 case 9 ... 16: 1119 bpp = 16; 1120 break; 1121 default: 1122 bpp = 32; 1123 break; 1124 } 1125 1126 if (specs->modedb != NULL) { 1127 const struct fb_videomode *mode; 1128 1129 mode = fb_find_best_display(specs, &info->modelist); 1130 fb_videomode_to_var(&nvidiafb_default_var, mode); 1131 nvidiafb_default_var.bits_per_pixel = bpp; 1132 } else if (par->fpWidth && par->fpHeight) { 1133 char buf[16]; 1134 1135 memset(buf, 0, 16); 1136 snprintf(buf, 15, "%dx%dMR", par->fpWidth, par->fpHeight); 1137 fb_find_mode(&nvidiafb_default_var, info, buf, specs->modedb, 1138 specs->modedb_len, &modedb, bpp); 1139 } 1140 1141 if (mode_option) 1142 fb_find_mode(&nvidiafb_default_var, info, mode_option, 1143 specs->modedb, specs->modedb_len, &modedb, bpp); 1144 1145 info->var = nvidiafb_default_var; 1146 info->fix.visual = (info->var.bits_per_pixel == 8) ? 1147 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR; 1148 info->pseudo_palette = par->pseudo_palette; 1149 fb_alloc_cmap(&info->cmap, 256, 0); 1150 fb_destroy_modedb(info->monspecs.modedb); 1151 info->monspecs.modedb = NULL; 1152 1153 /* maximize virtual vertical length */ 1154 lpitch = info->var.xres_virtual * 1155 ((info->var.bits_per_pixel + 7) >> 3); 1156 info->var.yres_virtual = info->screen_size / lpitch; 1157 1158 info->pixmap.scan_align = 4; 1159 info->pixmap.buf_align = 4; 1160 info->pixmap.access_align = 32; 1161 info->pixmap.size = 8 * 1024; 1162 info->pixmap.flags = FB_PIXMAP_SYSTEM; 1163 1164 if (!hwcur) 1165 nvidia_fb_ops.fb_cursor = NULL; 1166 1167 info->var.accel_flags = (!noaccel); 1168 1169 switch (par->Architecture) { 1170 case NV_ARCH_04: 1171 info->fix.accel = FB_ACCEL_NV4; 1172 break; 1173 case NV_ARCH_10: 1174 info->fix.accel = FB_ACCEL_NV_10; 1175 break; 1176 case NV_ARCH_20: 1177 info->fix.accel = FB_ACCEL_NV_20; 1178 break; 1179 case NV_ARCH_30: 1180 info->fix.accel = FB_ACCEL_NV_30; 1181 break; 1182 case NV_ARCH_40: 1183 info->fix.accel = FB_ACCEL_NV_40; 1184 break; 1185 } 1186 1187 NVTRACE_LEAVE(); 1188 1189 return nvidiafb_check_var(&info->var, info); 1190 } 1191 1192 static u32 nvidia_get_chipset(struct fb_info *info) 1193 { 1194 struct nvidia_par *par = info->par; 1195 u32 id = (par->pci_dev->vendor << 16) | par->pci_dev->device; 1196 1197 printk(KERN_INFO PFX "Device ID: %x \n", id); 1198 1199 if ((id & 0xfff0) == 0x00f0 || 1200 (id & 0xfff0) == 0x02e0) { 1201 /* pci-e */ 1202 id = NV_RD32(par->REGS, 0x1800); 1203 1204 if ((id & 0x0000ffff) == 0x000010DE) 1205 id = 0x10DE0000 | (id >> 16); 1206 else if ((id & 0xffff0000) == 0xDE100000) /* wrong endian */ 1207 id = 0x10DE0000 | ((id << 8) & 0x0000ff00) | 1208 ((id >> 8) & 0x000000ff); 1209 printk(KERN_INFO PFX "Subsystem ID: %x \n", id); 1210 } 1211 1212 return id; 1213 } 1214 1215 static u32 nvidia_get_arch(struct fb_info *info) 1216 { 1217 struct nvidia_par *par = info->par; 1218 u32 arch = 0; 1219 1220 switch (par->Chipset & 0x0ff0) { 1221 case 0x0100: /* GeForce 256 */ 1222 case 0x0110: /* GeForce2 MX */ 1223 case 0x0150: /* GeForce2 */ 1224 case 0x0170: /* GeForce4 MX */ 1225 case 0x0180: /* GeForce4 MX (8x AGP) */ 1226 case 0x01A0: /* nForce */ 1227 case 0x01F0: /* nForce2 */ 1228 arch = NV_ARCH_10; 1229 break; 1230 case 0x0200: /* GeForce3 */ 1231 case 0x0250: /* GeForce4 Ti */ 1232 case 0x0280: /* GeForce4 Ti (8x AGP) */ 1233 arch = NV_ARCH_20; 1234 break; 1235 case 0x0300: /* GeForceFX 5800 */ 1236 case 0x0310: /* GeForceFX 5600 */ 1237 case 0x0320: /* GeForceFX 5200 */ 1238 case 0x0330: /* GeForceFX 5900 */ 1239 case 0x0340: /* GeForceFX 5700 */ 1240 arch = NV_ARCH_30; 1241 break; 1242 case 0x0040: /* GeForce 6800 */ 1243 case 0x00C0: /* GeForce 6800 */ 1244 case 0x0120: /* GeForce 6800 */ 1245 case 0x0140: /* GeForce 6600 */ 1246 case 0x0160: /* GeForce 6200 */ 1247 case 0x01D0: /* GeForce 7200, 7300, 7400 */ 1248 case 0x0090: /* GeForce 7800 */ 1249 case 0x0210: /* GeForce 6800 */ 1250 case 0x0220: /* GeForce 6200 */ 1251 case 0x0240: /* GeForce 6100 */ 1252 case 0x0290: /* GeForce 7900 */ 1253 case 0x0390: /* GeForce 7600 */ 1254 case 0x03D0: 1255 arch = NV_ARCH_40; 1256 break; 1257 case 0x0020: /* TNT, TNT2 */ 1258 arch = NV_ARCH_04; 1259 break; 1260 default: /* unknown architecture */ 1261 break; 1262 } 1263 1264 return arch; 1265 } 1266 1267 static int nvidiafb_probe(struct pci_dev *pd, const struct pci_device_id *ent) 1268 { 1269 struct nvidia_par *par; 1270 struct fb_info *info; 1271 unsigned short cmd; 1272 1273 1274 NVTRACE_ENTER(); 1275 assert(pd != NULL); 1276 1277 info = framebuffer_alloc(sizeof(struct nvidia_par), &pd->dev); 1278 1279 if (!info) 1280 goto err_out; 1281 1282 par = info->par; 1283 par->pci_dev = pd; 1284 info->pixmap.addr = kzalloc(8 * 1024, GFP_KERNEL); 1285 1286 if (info->pixmap.addr == NULL) 1287 goto err_out_kfree; 1288 1289 if (pci_enable_device(pd)) { 1290 printk(KERN_ERR PFX "cannot enable PCI device\n"); 1291 goto err_out_enable; 1292 } 1293 1294 if (pci_request_regions(pd, "nvidiafb")) { 1295 printk(KERN_ERR PFX "cannot request PCI regions\n"); 1296 goto err_out_enable; 1297 } 1298 1299 par->FlatPanel = flatpanel; 1300 if (flatpanel == 1) 1301 printk(KERN_INFO PFX "flatpanel support enabled\n"); 1302 par->FPDither = fpdither; 1303 1304 par->CRTCnumber = forceCRTC; 1305 par->FpScale = (!noscale); 1306 par->paneltweak = paneltweak; 1307 par->reverse_i2c = reverse_i2c; 1308 1309 /* enable IO and mem if not already done */ 1310 pci_read_config_word(pd, PCI_COMMAND, &cmd); 1311 cmd |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY); 1312 pci_write_config_word(pd, PCI_COMMAND, cmd); 1313 1314 nvidiafb_fix.mmio_start = pci_resource_start(pd, 0); 1315 nvidiafb_fix.smem_start = pci_resource_start(pd, 1); 1316 nvidiafb_fix.mmio_len = pci_resource_len(pd, 0); 1317 1318 par->REGS = ioremap(nvidiafb_fix.mmio_start, nvidiafb_fix.mmio_len); 1319 1320 if (!par->REGS) { 1321 printk(KERN_ERR PFX "cannot ioremap MMIO base\n"); 1322 goto err_out_free_base0; 1323 } 1324 1325 par->Chipset = nvidia_get_chipset(info); 1326 par->Architecture = nvidia_get_arch(info); 1327 1328 if (par->Architecture == 0) { 1329 printk(KERN_ERR PFX "unknown NV_ARCH\n"); 1330 goto err_out_arch; 1331 } 1332 1333 sprintf(nvidiafb_fix.id, "NV%x", (pd->device & 0x0ff0) >> 4); 1334 1335 if (NVCommonSetup(info)) 1336 goto err_out_arch; 1337 1338 par->FbAddress = nvidiafb_fix.smem_start; 1339 par->FbMapSize = par->RamAmountKBytes * 1024; 1340 if (vram && vram * 1024 * 1024 < par->FbMapSize) 1341 par->FbMapSize = vram * 1024 * 1024; 1342 1343 /* Limit amount of vram to 64 MB */ 1344 if (par->FbMapSize > 64 * 1024 * 1024) 1345 par->FbMapSize = 64 * 1024 * 1024; 1346 1347 if(par->Architecture >= NV_ARCH_40) 1348 par->FbUsableSize = par->FbMapSize - (560 * 1024); 1349 else 1350 par->FbUsableSize = par->FbMapSize - (128 * 1024); 1351 par->ScratchBufferSize = (par->Architecture < NV_ARCH_10) ? 8 * 1024 : 1352 16 * 1024; 1353 par->ScratchBufferStart = par->FbUsableSize - par->ScratchBufferSize; 1354 par->CursorStart = par->FbUsableSize + (32 * 1024); 1355 1356 info->screen_base = ioremap_wc(nvidiafb_fix.smem_start, 1357 par->FbMapSize); 1358 info->screen_size = par->FbUsableSize; 1359 nvidiafb_fix.smem_len = par->RamAmountKBytes * 1024; 1360 1361 if (!info->screen_base) { 1362 printk(KERN_ERR PFX "cannot ioremap FB base\n"); 1363 goto err_out_free_base1; 1364 } 1365 1366 par->FbStart = info->screen_base; 1367 1368 if (!nomtrr) 1369 par->wc_cookie = arch_phys_wc_add(nvidiafb_fix.smem_start, 1370 par->RamAmountKBytes * 1024); 1371 1372 info->fbops = &nvidia_fb_ops; 1373 info->fix = nvidiafb_fix; 1374 1375 if (nvidia_set_fbinfo(info) < 0) { 1376 printk(KERN_ERR PFX "error setting initial video mode\n"); 1377 goto err_out_iounmap_fb; 1378 } 1379 1380 nvidia_save_vga(par, &par->SavedReg); 1381 1382 pci_set_drvdata(pd, info); 1383 1384 if (backlight) 1385 nvidia_bl_init(par); 1386 1387 if (register_framebuffer(info) < 0) { 1388 printk(KERN_ERR PFX "error registering nVidia framebuffer\n"); 1389 goto err_out_iounmap_fb; 1390 } 1391 1392 1393 printk(KERN_INFO PFX 1394 "PCI nVidia %s framebuffer (%dMB @ 0x%lX)\n", 1395 info->fix.id, 1396 par->FbMapSize / (1024 * 1024), info->fix.smem_start); 1397 1398 NVTRACE_LEAVE(); 1399 return 0; 1400 1401 err_out_iounmap_fb: 1402 iounmap(info->screen_base); 1403 err_out_free_base1: 1404 fb_destroy_modedb(info->monspecs.modedb); 1405 nvidia_delete_i2c_busses(par); 1406 err_out_arch: 1407 iounmap(par->REGS); 1408 err_out_free_base0: 1409 pci_release_regions(pd); 1410 err_out_enable: 1411 kfree(info->pixmap.addr); 1412 err_out_kfree: 1413 framebuffer_release(info); 1414 err_out: 1415 return -ENODEV; 1416 } 1417 1418 static void nvidiafb_remove(struct pci_dev *pd) 1419 { 1420 struct fb_info *info = pci_get_drvdata(pd); 1421 struct nvidia_par *par = info->par; 1422 1423 NVTRACE_ENTER(); 1424 1425 unregister_framebuffer(info); 1426 1427 nvidia_bl_exit(par); 1428 arch_phys_wc_del(par->wc_cookie); 1429 iounmap(info->screen_base); 1430 fb_destroy_modedb(info->monspecs.modedb); 1431 nvidia_delete_i2c_busses(par); 1432 iounmap(par->REGS); 1433 pci_release_regions(pd); 1434 kfree(info->pixmap.addr); 1435 framebuffer_release(info); 1436 NVTRACE_LEAVE(); 1437 } 1438 1439 /* ------------------------------------------------------------------------- * 1440 * 1441 * initialization 1442 * 1443 * ------------------------------------------------------------------------- */ 1444 1445 #ifndef MODULE 1446 static int nvidiafb_setup(char *options) 1447 { 1448 char *this_opt; 1449 1450 NVTRACE_ENTER(); 1451 if (!options || !*options) 1452 return 0; 1453 1454 while ((this_opt = strsep(&options, ",")) != NULL) { 1455 if (!strncmp(this_opt, "forceCRTC", 9)) { 1456 char *p; 1457 1458 p = this_opt + 9; 1459 if (!*p || !*(++p)) 1460 continue; 1461 forceCRTC = *p - '0'; 1462 if (forceCRTC < 0 || forceCRTC > 1) 1463 forceCRTC = -1; 1464 } else if (!strncmp(this_opt, "flatpanel", 9)) { 1465 flatpanel = 1; 1466 } else if (!strncmp(this_opt, "hwcur", 5)) { 1467 hwcur = 1; 1468 } else if (!strncmp(this_opt, "noaccel", 6)) { 1469 noaccel = 1; 1470 } else if (!strncmp(this_opt, "noscale", 7)) { 1471 noscale = 1; 1472 } else if (!strncmp(this_opt, "reverse_i2c", 11)) { 1473 reverse_i2c = 1; 1474 } else if (!strncmp(this_opt, "paneltweak:", 11)) { 1475 paneltweak = simple_strtoul(this_opt+11, NULL, 0); 1476 } else if (!strncmp(this_opt, "vram:", 5)) { 1477 vram = simple_strtoul(this_opt+5, NULL, 0); 1478 } else if (!strncmp(this_opt, "backlight:", 10)) { 1479 backlight = simple_strtoul(this_opt+10, NULL, 0); 1480 } else if (!strncmp(this_opt, "nomtrr", 6)) { 1481 nomtrr = true; 1482 } else if (!strncmp(this_opt, "fpdither:", 9)) { 1483 fpdither = simple_strtol(this_opt+9, NULL, 0); 1484 } else if (!strncmp(this_opt, "bpp:", 4)) { 1485 bpp = simple_strtoul(this_opt+4, NULL, 0); 1486 } else 1487 mode_option = this_opt; 1488 } 1489 NVTRACE_LEAVE(); 1490 return 0; 1491 } 1492 #endif /* !MODULE */ 1493 1494 static struct pci_driver nvidiafb_driver = { 1495 .name = "nvidiafb", 1496 .id_table = nvidiafb_pci_tbl, 1497 .probe = nvidiafb_probe, 1498 .suspend = nvidiafb_suspend, 1499 .resume = nvidiafb_resume, 1500 .remove = nvidiafb_remove, 1501 }; 1502 1503 /* ------------------------------------------------------------------------- * 1504 * 1505 * modularization 1506 * 1507 * ------------------------------------------------------------------------- */ 1508 1509 static int nvidiafb_init(void) 1510 { 1511 #ifndef MODULE 1512 char *option = NULL; 1513 1514 if (fb_get_options("nvidiafb", &option)) 1515 return -ENODEV; 1516 nvidiafb_setup(option); 1517 #endif 1518 return pci_register_driver(&nvidiafb_driver); 1519 } 1520 1521 module_init(nvidiafb_init); 1522 1523 static void __exit nvidiafb_exit(void) 1524 { 1525 pci_unregister_driver(&nvidiafb_driver); 1526 } 1527 1528 module_exit(nvidiafb_exit); 1529 1530 module_param(flatpanel, int, 0); 1531 MODULE_PARM_DESC(flatpanel, 1532 "Enables experimental flat panel support for some chipsets. " 1533 "(0=disabled, 1=enabled, -1=autodetect) (default=-1)"); 1534 module_param(fpdither, int, 0); 1535 MODULE_PARM_DESC(fpdither, 1536 "Enables dithering of flat panel for 6 bits panels. " 1537 "(0=disabled, 1=enabled, -1=autodetect) (default=-1)"); 1538 module_param(hwcur, int, 0); 1539 MODULE_PARM_DESC(hwcur, 1540 "Enables hardware cursor implementation. (0 or 1=enabled) " 1541 "(default=0)"); 1542 module_param(noaccel, int, 0); 1543 MODULE_PARM_DESC(noaccel, 1544 "Disables hardware acceleration. (0 or 1=disable) " 1545 "(default=0)"); 1546 module_param(noscale, int, 0); 1547 MODULE_PARM_DESC(noscale, 1548 "Disables screen scaling. (0 or 1=disable) " 1549 "(default=0, do scaling)"); 1550 module_param(paneltweak, int, 0); 1551 MODULE_PARM_DESC(paneltweak, 1552 "Tweak display settings for flatpanels. " 1553 "(default=0, no tweaks)"); 1554 module_param(forceCRTC, int, 0); 1555 MODULE_PARM_DESC(forceCRTC, 1556 "Forces usage of a particular CRTC in case autodetection " 1557 "fails. (0 or 1) (default=autodetect)"); 1558 module_param(vram, int, 0); 1559 MODULE_PARM_DESC(vram, 1560 "amount of framebuffer memory to remap in MiB" 1561 "(default=0 - remap entire memory)"); 1562 module_param(mode_option, charp, 0); 1563 MODULE_PARM_DESC(mode_option, "Specify initial video mode"); 1564 module_param(bpp, int, 0); 1565 MODULE_PARM_DESC(bpp, "pixel width in bits" 1566 "(default=8)"); 1567 module_param(reverse_i2c, int, 0); 1568 MODULE_PARM_DESC(reverse_i2c, "reverse port assignment of the i2c bus"); 1569 module_param(nomtrr, bool, false); 1570 MODULE_PARM_DESC(nomtrr, "Disables MTRR support (0 or 1=disabled) " 1571 "(default=0)"); 1572 1573 MODULE_AUTHOR("Antonino Daplas"); 1574 MODULE_DESCRIPTION("Framebuffer driver for nVidia graphics chipset"); 1575 MODULE_LICENSE("GPL"); 1576