1 /***************************************************************************\ 2 |* *| 3 |* Copyright 2003 NVIDIA, Corporation. All rights reserved. *| 4 |* *| 5 |* NOTICE TO USER: The source code is copyrighted under U.S. and *| 6 |* international laws. Users and possessors of this source code are *| 7 |* hereby granted a nonexclusive, royalty-free copyright license to *| 8 |* use this code in individual and commercial software. *| 9 |* *| 10 |* Any use of this source code must include, in the user documenta- *| 11 |* tion and internal comments to the code, notices to the end user *| 12 |* as follows: *| 13 |* *| 14 |* Copyright 2003 NVIDIA, Corporation. All rights reserved. *| 15 |* *| 16 |* NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY *| 17 |* OF THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" *| 18 |* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *| 19 |* ATION DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, *| 20 |* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *| 21 |* MENT, AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL *| 22 |* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *| 23 |* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *| 24 |* SULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION *| 25 |* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF *| 26 |* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE. *| 27 |* *| 28 |* U.S. Government End Users. This source code is a "commercial *| 29 |* item," as that term is defined at 48 C.F.R. 2.101 (OCT 1995), *| 30 |* consisting of "commercial computer software" and "commercial *| 31 |* computer software documentation," as such terms are used in *| 32 |* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *| 33 |* ment only as a commercial end item. Consistent with 48 C.F.R. *| 34 |* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *| 35 |* all U.S. Government End Users acquire the source code with only *| 36 |* those rights set forth herein. *| 37 |* *| 38 \***************************************************************************/ 39 40 /* 41 * GPL Licensing Note - According to Mark Vojkovich, author of the Xorg/ 42 * XFree86 'nv' driver, this source code is provided under MIT-style licensing 43 * where the source code is provided "as is" without warranty of any kind. 44 * The only usage restriction is for the copyright notices to be retained 45 * whenever code is used. 46 * 47 * Antonino Daplas <adaplas@pol.net> 2005-03-11 48 */ 49 50 #include <video/vga.h> 51 #include <linux/delay.h> 52 #include <linux/pci.h> 53 #include <linux/slab.h> 54 #include "nv_type.h" 55 #include "nv_local.h" 56 #include "nv_proto.h" 57 /* 58 * Override VGA I/O routines. 59 */ 60 void NVWriteCrtc(struct nvidia_par *par, u8 index, u8 value) 61 { 62 VGA_WR08(par->PCIO, par->IOBase + 0x04, index); 63 VGA_WR08(par->PCIO, par->IOBase + 0x05, value); 64 } 65 u8 NVReadCrtc(struct nvidia_par *par, u8 index) 66 { 67 VGA_WR08(par->PCIO, par->IOBase + 0x04, index); 68 return (VGA_RD08(par->PCIO, par->IOBase + 0x05)); 69 } 70 void NVWriteGr(struct nvidia_par *par, u8 index, u8 value) 71 { 72 VGA_WR08(par->PVIO, VGA_GFX_I, index); 73 VGA_WR08(par->PVIO, VGA_GFX_D, value); 74 } 75 u8 NVReadGr(struct nvidia_par *par, u8 index) 76 { 77 VGA_WR08(par->PVIO, VGA_GFX_I, index); 78 return (VGA_RD08(par->PVIO, VGA_GFX_D)); 79 } 80 void NVWriteSeq(struct nvidia_par *par, u8 index, u8 value) 81 { 82 VGA_WR08(par->PVIO, VGA_SEQ_I, index); 83 VGA_WR08(par->PVIO, VGA_SEQ_D, value); 84 } 85 u8 NVReadSeq(struct nvidia_par *par, u8 index) 86 { 87 VGA_WR08(par->PVIO, VGA_SEQ_I, index); 88 return (VGA_RD08(par->PVIO, VGA_SEQ_D)); 89 } 90 void NVWriteAttr(struct nvidia_par *par, u8 index, u8 value) 91 { 92 volatile u8 tmp; 93 94 tmp = VGA_RD08(par->PCIO, par->IOBase + 0x0a); 95 if (par->paletteEnabled) 96 index &= ~0x20; 97 else 98 index |= 0x20; 99 VGA_WR08(par->PCIO, VGA_ATT_IW, index); 100 VGA_WR08(par->PCIO, VGA_ATT_W, value); 101 } 102 u8 NVReadAttr(struct nvidia_par *par, u8 index) 103 { 104 volatile u8 tmp; 105 106 tmp = VGA_RD08(par->PCIO, par->IOBase + 0x0a); 107 if (par->paletteEnabled) 108 index &= ~0x20; 109 else 110 index |= 0x20; 111 VGA_WR08(par->PCIO, VGA_ATT_IW, index); 112 return (VGA_RD08(par->PCIO, VGA_ATT_R)); 113 } 114 void NVWriteMiscOut(struct nvidia_par *par, u8 value) 115 { 116 VGA_WR08(par->PVIO, VGA_MIS_W, value); 117 } 118 u8 NVReadMiscOut(struct nvidia_par *par) 119 { 120 return (VGA_RD08(par->PVIO, VGA_MIS_R)); 121 } 122 #if 0 123 void NVEnablePalette(struct nvidia_par *par) 124 { 125 volatile u8 tmp; 126 127 tmp = VGA_RD08(par->PCIO, par->IOBase + 0x0a); 128 VGA_WR08(par->PCIO, VGA_ATT_IW, 0x00); 129 par->paletteEnabled = 1; 130 } 131 void NVDisablePalette(struct nvidia_par *par) 132 { 133 volatile u8 tmp; 134 135 tmp = VGA_RD08(par->PCIO, par->IOBase + 0x0a); 136 VGA_WR08(par->PCIO, VGA_ATT_IW, 0x20); 137 par->paletteEnabled = 0; 138 } 139 #endif /* 0 */ 140 void NVWriteDacMask(struct nvidia_par *par, u8 value) 141 { 142 VGA_WR08(par->PDIO, VGA_PEL_MSK, value); 143 } 144 #if 0 145 u8 NVReadDacMask(struct nvidia_par *par) 146 { 147 return (VGA_RD08(par->PDIO, VGA_PEL_MSK)); 148 } 149 #endif /* 0 */ 150 void NVWriteDacReadAddr(struct nvidia_par *par, u8 value) 151 { 152 VGA_WR08(par->PDIO, VGA_PEL_IR, value); 153 } 154 void NVWriteDacWriteAddr(struct nvidia_par *par, u8 value) 155 { 156 VGA_WR08(par->PDIO, VGA_PEL_IW, value); 157 } 158 void NVWriteDacData(struct nvidia_par *par, u8 value) 159 { 160 VGA_WR08(par->PDIO, VGA_PEL_D, value); 161 } 162 u8 NVReadDacData(struct nvidia_par *par) 163 { 164 return (VGA_RD08(par->PDIO, VGA_PEL_D)); 165 } 166 167 static int NVIsConnected(struct nvidia_par *par, int output) 168 { 169 volatile u32 __iomem *PRAMDAC = par->PRAMDAC0; 170 u32 reg52C, reg608, dac0_reg608 = 0; 171 int present; 172 173 if (output) { 174 dac0_reg608 = NV_RD32(PRAMDAC, 0x0608); 175 PRAMDAC += 0x800; 176 } 177 178 reg52C = NV_RD32(PRAMDAC, 0x052C); 179 reg608 = NV_RD32(PRAMDAC, 0x0608); 180 181 NV_WR32(PRAMDAC, 0x0608, reg608 & ~0x00010000); 182 183 NV_WR32(PRAMDAC, 0x052C, reg52C & 0x0000FEEE); 184 msleep(1); 185 NV_WR32(PRAMDAC, 0x052C, NV_RD32(PRAMDAC, 0x052C) | 1); 186 187 NV_WR32(par->PRAMDAC0, 0x0610, 0x94050140); 188 NV_WR32(par->PRAMDAC0, 0x0608, NV_RD32(par->PRAMDAC0, 0x0608) | 189 0x00001000); 190 191 msleep(1); 192 193 present = (NV_RD32(PRAMDAC, 0x0608) & (1 << 28)) ? 1 : 0; 194 195 if (present) 196 printk("nvidiafb: CRTC%i analog found\n", output); 197 else 198 printk("nvidiafb: CRTC%i analog not found\n", output); 199 200 if (output) 201 NV_WR32(par->PRAMDAC0, 0x0608, dac0_reg608); 202 203 NV_WR32(PRAMDAC, 0x052C, reg52C); 204 NV_WR32(PRAMDAC, 0x0608, reg608); 205 206 return present; 207 } 208 209 static void NVSelectHeadRegisters(struct nvidia_par *par, int head) 210 { 211 if (head) { 212 par->PCIO = par->PCIO0 + 0x2000; 213 par->PCRTC = par->PCRTC0 + 0x800; 214 par->PRAMDAC = par->PRAMDAC0 + 0x800; 215 par->PDIO = par->PDIO0 + 0x2000; 216 } else { 217 par->PCIO = par->PCIO0; 218 par->PCRTC = par->PCRTC0; 219 par->PRAMDAC = par->PRAMDAC0; 220 par->PDIO = par->PDIO0; 221 } 222 } 223 224 static void nv4GetConfig(struct nvidia_par *par) 225 { 226 if (NV_RD32(par->PFB, 0x0000) & 0x00000100) { 227 par->RamAmountKBytes = 228 ((NV_RD32(par->PFB, 0x0000) >> 12) & 0x0F) * 1024 * 2 + 229 1024 * 2; 230 } else { 231 switch (NV_RD32(par->PFB, 0x0000) & 0x00000003) { 232 case 0: 233 par->RamAmountKBytes = 1024 * 32; 234 break; 235 case 1: 236 par->RamAmountKBytes = 1024 * 4; 237 break; 238 case 2: 239 par->RamAmountKBytes = 1024 * 8; 240 break; 241 case 3: 242 default: 243 par->RamAmountKBytes = 1024 * 16; 244 break; 245 } 246 } 247 par->CrystalFreqKHz = (NV_RD32(par->PEXTDEV, 0x0000) & 0x00000040) ? 248 14318 : 13500; 249 par->CURSOR = &par->PRAMIN[0x1E00]; 250 par->MinVClockFreqKHz = 12000; 251 par->MaxVClockFreqKHz = 350000; 252 } 253 254 static void nv10GetConfig(struct nvidia_par *par) 255 { 256 struct pci_dev *dev; 257 u32 implementation = par->Chipset & 0x0ff0; 258 259 #ifdef __BIG_ENDIAN 260 /* turn on big endian register access */ 261 if (!(NV_RD32(par->PMC, 0x0004) & 0x01000001)) { 262 NV_WR32(par->PMC, 0x0004, 0x01000001); 263 mb(); 264 } 265 #endif 266 267 dev = pci_get_domain_bus_and_slot(pci_domain_nr(par->pci_dev->bus), 268 0, 1); 269 if ((par->Chipset & 0xffff) == 0x01a0) { 270 u32 amt; 271 272 pci_read_config_dword(dev, 0x7c, &amt); 273 par->RamAmountKBytes = (((amt >> 6) & 31) + 1) * 1024; 274 } else if ((par->Chipset & 0xffff) == 0x01f0) { 275 u32 amt; 276 277 pci_read_config_dword(dev, 0x84, &amt); 278 par->RamAmountKBytes = (((amt >> 4) & 127) + 1) * 1024; 279 } else { 280 par->RamAmountKBytes = 281 (NV_RD32(par->PFB, 0x020C) & 0xFFF00000) >> 10; 282 } 283 pci_dev_put(dev); 284 285 par->CrystalFreqKHz = (NV_RD32(par->PEXTDEV, 0x0000) & (1 << 6)) ? 286 14318 : 13500; 287 288 if (par->twoHeads && (implementation != 0x0110)) { 289 if (NV_RD32(par->PEXTDEV, 0x0000) & (1 << 22)) 290 par->CrystalFreqKHz = 27000; 291 } 292 293 par->CURSOR = NULL; /* can't set this here */ 294 par->MinVClockFreqKHz = 12000; 295 par->MaxVClockFreqKHz = par->twoStagePLL ? 400000 : 350000; 296 } 297 298 int NVCommonSetup(struct fb_info *info) 299 { 300 struct nvidia_par *par = info->par; 301 struct fb_var_screeninfo *var; 302 u16 implementation = par->Chipset & 0x0ff0; 303 u8 *edidA = NULL, *edidB = NULL; 304 struct fb_monspecs *monitorA, *monitorB; 305 struct fb_monspecs *monA = NULL, *monB = NULL; 306 int mobile = 0; 307 int tvA = 0; 308 int tvB = 0; 309 int FlatPanel = -1; /* really means the CRTC is slaved */ 310 int Television = 0; 311 int err = 0; 312 313 var = kzalloc(sizeof(struct fb_var_screeninfo), GFP_KERNEL); 314 monitorA = kzalloc(sizeof(struct fb_monspecs), GFP_KERNEL); 315 monitorB = kzalloc(sizeof(struct fb_monspecs), GFP_KERNEL); 316 317 if (!var || !monitorA || !monitorB) { 318 err = -ENOMEM; 319 goto done; 320 } 321 322 par->PRAMIN = par->REGS + (0x00710000 / 4); 323 par->PCRTC0 = par->REGS + (0x00600000 / 4); 324 par->PRAMDAC0 = par->REGS + (0x00680000 / 4); 325 par->PFB = par->REGS + (0x00100000 / 4); 326 par->PFIFO = par->REGS + (0x00002000 / 4); 327 par->PGRAPH = par->REGS + (0x00400000 / 4); 328 par->PEXTDEV = par->REGS + (0x00101000 / 4); 329 par->PTIMER = par->REGS + (0x00009000 / 4); 330 par->PMC = par->REGS + (0x00000000 / 4); 331 par->FIFO = par->REGS + (0x00800000 / 4); 332 333 /* 8 bit registers */ 334 par->PCIO0 = (u8 __iomem *) par->REGS + 0x00601000; 335 par->PDIO0 = (u8 __iomem *) par->REGS + 0x00681000; 336 par->PVIO = (u8 __iomem *) par->REGS + 0x000C0000; 337 338 par->twoHeads = (par->Architecture >= NV_ARCH_10) && 339 (implementation != 0x0100) && 340 (implementation != 0x0150) && 341 (implementation != 0x01A0) && (implementation != 0x0200); 342 343 par->fpScaler = (par->FpScale && par->twoHeads && 344 (implementation != 0x0110)); 345 346 par->twoStagePLL = (implementation == 0x0310) || 347 (implementation == 0x0340) || (par->Architecture >= NV_ARCH_40); 348 349 par->WaitVSyncPossible = (par->Architecture >= NV_ARCH_10) && 350 (implementation != 0x0100); 351 352 par->BlendingPossible = ((par->Chipset & 0xffff) != 0x0020); 353 354 /* look for known laptop chips */ 355 switch (par->Chipset & 0xffff) { 356 case 0x0112: 357 case 0x0174: 358 case 0x0175: 359 case 0x0176: 360 case 0x0177: 361 case 0x0179: 362 case 0x017C: 363 case 0x017D: 364 case 0x0186: 365 case 0x0187: 366 case 0x018D: 367 case 0x01D7: 368 case 0x0228: 369 case 0x0286: 370 case 0x028C: 371 case 0x0316: 372 case 0x0317: 373 case 0x031A: 374 case 0x031B: 375 case 0x031C: 376 case 0x031D: 377 case 0x031E: 378 case 0x031F: 379 case 0x0324: 380 case 0x0325: 381 case 0x0328: 382 case 0x0329: 383 case 0x032C: 384 case 0x032D: 385 case 0x0347: 386 case 0x0348: 387 case 0x0349: 388 case 0x034B: 389 case 0x034C: 390 case 0x0160: 391 case 0x0166: 392 case 0x0169: 393 case 0x016B: 394 case 0x016C: 395 case 0x016D: 396 case 0x00C8: 397 case 0x00CC: 398 case 0x0144: 399 case 0x0146: 400 case 0x0147: 401 case 0x0148: 402 case 0x0098: 403 case 0x0099: 404 mobile = 1; 405 break; 406 default: 407 break; 408 } 409 410 if (par->Architecture == NV_ARCH_04) 411 nv4GetConfig(par); 412 else 413 nv10GetConfig(par); 414 415 NVSelectHeadRegisters(par, 0); 416 417 NVLockUnlock(par, 0); 418 419 par->IOBase = (NVReadMiscOut(par) & 0x01) ? 0x3d0 : 0x3b0; 420 421 par->Television = 0; 422 423 nvidia_create_i2c_busses(par); 424 if (!par->twoHeads) { 425 par->CRTCnumber = 0; 426 if (nvidia_probe_i2c_connector(info, 1, &edidA)) 427 nvidia_probe_of_connector(info, 1, &edidA); 428 if (edidA && !fb_parse_edid(edidA, var)) { 429 printk("nvidiafb: EDID found from BUS1\n"); 430 monA = monitorA; 431 fb_edid_to_monspecs(edidA, monA); 432 FlatPanel = (monA->input & FB_DISP_DDI) ? 1 : 0; 433 434 /* NV4 doesn't support FlatPanels */ 435 if ((par->Chipset & 0x0fff) <= 0x0020) 436 FlatPanel = 0; 437 } else { 438 VGA_WR08(par->PCIO, 0x03D4, 0x28); 439 if (VGA_RD08(par->PCIO, 0x03D5) & 0x80) { 440 VGA_WR08(par->PCIO, 0x03D4, 0x33); 441 if (!(VGA_RD08(par->PCIO, 0x03D5) & 0x01)) 442 Television = 1; 443 FlatPanel = 1; 444 } else { 445 FlatPanel = 0; 446 } 447 printk("nvidiafb: HW is currently programmed for %s\n", 448 FlatPanel ? (Television ? "TV" : "DFP") : 449 "CRT"); 450 } 451 452 if (par->FlatPanel == -1) { 453 par->FlatPanel = FlatPanel; 454 par->Television = Television; 455 } else { 456 printk("nvidiafb: Forcing display type to %s as " 457 "specified\n", par->FlatPanel ? "DFP" : "CRT"); 458 } 459 } else { 460 u8 outputAfromCRTC, outputBfromCRTC; 461 int CRTCnumber = -1; 462 u8 slaved_on_A, slaved_on_B; 463 int analog_on_A, analog_on_B; 464 u32 oldhead; 465 u8 cr44; 466 467 if (implementation != 0x0110) { 468 if (NV_RD32(par->PRAMDAC0, 0x0000052C) & 0x100) 469 outputAfromCRTC = 1; 470 else 471 outputAfromCRTC = 0; 472 if (NV_RD32(par->PRAMDAC0, 0x0000252C) & 0x100) 473 outputBfromCRTC = 1; 474 else 475 outputBfromCRTC = 0; 476 analog_on_A = NVIsConnected(par, 0); 477 analog_on_B = NVIsConnected(par, 1); 478 } else { 479 outputAfromCRTC = 0; 480 outputBfromCRTC = 1; 481 analog_on_A = 0; 482 analog_on_B = 0; 483 } 484 485 VGA_WR08(par->PCIO, 0x03D4, 0x44); 486 cr44 = VGA_RD08(par->PCIO, 0x03D5); 487 488 VGA_WR08(par->PCIO, 0x03D5, 3); 489 NVSelectHeadRegisters(par, 1); 490 NVLockUnlock(par, 0); 491 492 VGA_WR08(par->PCIO, 0x03D4, 0x28); 493 slaved_on_B = VGA_RD08(par->PCIO, 0x03D5) & 0x80; 494 if (slaved_on_B) { 495 VGA_WR08(par->PCIO, 0x03D4, 0x33); 496 tvB = !(VGA_RD08(par->PCIO, 0x03D5) & 0x01); 497 } 498 499 VGA_WR08(par->PCIO, 0x03D4, 0x44); 500 VGA_WR08(par->PCIO, 0x03D5, 0); 501 NVSelectHeadRegisters(par, 0); 502 NVLockUnlock(par, 0); 503 504 VGA_WR08(par->PCIO, 0x03D4, 0x28); 505 slaved_on_A = VGA_RD08(par->PCIO, 0x03D5) & 0x80; 506 if (slaved_on_A) { 507 VGA_WR08(par->PCIO, 0x03D4, 0x33); 508 tvA = !(VGA_RD08(par->PCIO, 0x03D5) & 0x01); 509 } 510 511 oldhead = NV_RD32(par->PCRTC0, 0x00000860); 512 NV_WR32(par->PCRTC0, 0x00000860, oldhead | 0x00000010); 513 514 if (nvidia_probe_i2c_connector(info, 1, &edidA)) 515 nvidia_probe_of_connector(info, 1, &edidA); 516 if (edidA && !fb_parse_edid(edidA, var)) { 517 printk("nvidiafb: EDID found from BUS1\n"); 518 monA = monitorA; 519 fb_edid_to_monspecs(edidA, monA); 520 } 521 522 if (nvidia_probe_i2c_connector(info, 2, &edidB)) 523 nvidia_probe_of_connector(info, 2, &edidB); 524 if (edidB && !fb_parse_edid(edidB, var)) { 525 printk("nvidiafb: EDID found from BUS2\n"); 526 monB = monitorB; 527 fb_edid_to_monspecs(edidB, monB); 528 } 529 530 if (slaved_on_A && !tvA) { 531 CRTCnumber = 0; 532 FlatPanel = 1; 533 printk("nvidiafb: CRTC 0 is currently programmed for " 534 "DFP\n"); 535 } else if (slaved_on_B && !tvB) { 536 CRTCnumber = 1; 537 FlatPanel = 1; 538 printk("nvidiafb: CRTC 1 is currently programmed " 539 "for DFP\n"); 540 } else if (analog_on_A) { 541 CRTCnumber = outputAfromCRTC; 542 FlatPanel = 0; 543 printk("nvidiafb: CRTC %i appears to have a " 544 "CRT attached\n", CRTCnumber); 545 } else if (analog_on_B) { 546 CRTCnumber = outputBfromCRTC; 547 FlatPanel = 0; 548 printk("nvidiafb: CRTC %i appears to have a " 549 "CRT attached\n", CRTCnumber); 550 } else if (slaved_on_A) { 551 CRTCnumber = 0; 552 FlatPanel = 1; 553 Television = 1; 554 printk("nvidiafb: CRTC 0 is currently programmed " 555 "for TV\n"); 556 } else if (slaved_on_B) { 557 CRTCnumber = 1; 558 FlatPanel = 1; 559 Television = 1; 560 printk("nvidiafb: CRTC 1 is currently programmed for " 561 "TV\n"); 562 } else if (monA) { 563 FlatPanel = (monA->input & FB_DISP_DDI) ? 1 : 0; 564 } else if (monB) { 565 FlatPanel = (monB->input & FB_DISP_DDI) ? 1 : 0; 566 } 567 568 if (par->FlatPanel == -1) { 569 if (FlatPanel != -1) { 570 par->FlatPanel = FlatPanel; 571 par->Television = Television; 572 } else { 573 printk("nvidiafb: Unable to detect display " 574 "type...\n"); 575 if (mobile) { 576 printk("...On a laptop, assuming " 577 "DFP\n"); 578 par->FlatPanel = 1; 579 } else { 580 printk("...Using default of CRT\n"); 581 par->FlatPanel = 0; 582 } 583 } 584 } else { 585 printk("nvidiafb: Forcing display type to %s as " 586 "specified\n", par->FlatPanel ? "DFP" : "CRT"); 587 } 588 589 if (par->CRTCnumber == -1) { 590 if (CRTCnumber != -1) 591 par->CRTCnumber = CRTCnumber; 592 else { 593 printk("nvidiafb: Unable to detect which " 594 "CRTCNumber...\n"); 595 if (par->FlatPanel) 596 par->CRTCnumber = 1; 597 else 598 par->CRTCnumber = 0; 599 printk("...Defaulting to CRTCNumber %i\n", 600 par->CRTCnumber); 601 } 602 } else { 603 printk("nvidiafb: Forcing CRTCNumber %i as " 604 "specified\n", par->CRTCnumber); 605 } 606 607 if (monA) { 608 if (((monA->input & FB_DISP_DDI) && 609 par->FlatPanel) || 610 ((!(monA->input & FB_DISP_DDI)) && 611 !par->FlatPanel)) { 612 if (monB) { 613 fb_destroy_modedb(monB->modedb); 614 monB = NULL; 615 } 616 } else { 617 fb_destroy_modedb(monA->modedb); 618 monA = NULL; 619 } 620 } 621 622 if (monB) { 623 if (((monB->input & FB_DISP_DDI) && 624 !par->FlatPanel) || 625 ((!(monB->input & FB_DISP_DDI)) && 626 par->FlatPanel)) { 627 fb_destroy_modedb(monB->modedb); 628 monB = NULL; 629 } else 630 monA = monB; 631 } 632 633 if (implementation == 0x0110) 634 cr44 = par->CRTCnumber * 0x3; 635 636 NV_WR32(par->PCRTC0, 0x00000860, oldhead); 637 638 VGA_WR08(par->PCIO, 0x03D4, 0x44); 639 VGA_WR08(par->PCIO, 0x03D5, cr44); 640 NVSelectHeadRegisters(par, par->CRTCnumber); 641 } 642 643 printk("nvidiafb: Using %s on CRTC %i\n", 644 par->FlatPanel ? (par->Television ? "TV" : "DFP") : "CRT", 645 par->CRTCnumber); 646 647 if (par->FlatPanel && !par->Television) { 648 par->fpWidth = NV_RD32(par->PRAMDAC, 0x0820) + 1; 649 par->fpHeight = NV_RD32(par->PRAMDAC, 0x0800) + 1; 650 par->fpSyncs = NV_RD32(par->PRAMDAC, 0x0848) & 0x30000033; 651 652 printk("nvidiafb: Panel size is %i x %i\n", par->fpWidth, par->fpHeight); 653 } 654 655 if (monA) 656 info->monspecs = *monA; 657 658 if (!par->FlatPanel || !par->twoHeads) 659 par->FPDither = 0; 660 661 par->LVDS = 0; 662 if (par->FlatPanel && par->twoHeads) { 663 NV_WR32(par->PRAMDAC0, 0x08B0, 0x00010004); 664 if (NV_RD32(par->PRAMDAC0, 0x08b4) & 1) 665 par->LVDS = 1; 666 printk("nvidiafb: Panel is %s\n", par->LVDS ? "LVDS" : "TMDS"); 667 } 668 669 kfree(edidA); 670 kfree(edidB); 671 done: 672 kfree(var); 673 kfree(monitorA); 674 kfree(monitorB); 675 return err; 676 } 677