11ccea77eSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later 2f7018c21STomi Valkeinen /* 3f7018c21STomi Valkeinen * linux/drivers/video/mmp/hw/mmp_ctrl.c 4f7018c21STomi Valkeinen * Marvell MMP series Display Controller support 5f7018c21STomi Valkeinen * 6f7018c21STomi Valkeinen * Copyright (C) 2012 Marvell Technology Group Ltd. 7f7018c21STomi Valkeinen * Authors: Guoqing Li <ligq@marvell.com> 8f7018c21STomi Valkeinen * Lisa Du <cldu@marvell.com> 9f7018c21STomi Valkeinen * Zhou Zhu <zzhu3@marvell.com> 10f7018c21STomi Valkeinen */ 11f7018c21STomi Valkeinen #include <linux/module.h> 12f7018c21STomi Valkeinen #include <linux/moduleparam.h> 13f7018c21STomi Valkeinen #include <linux/kernel.h> 14f7018c21STomi Valkeinen #include <linux/errno.h> 15f7018c21STomi Valkeinen #include <linux/string.h> 16f7018c21STomi Valkeinen #include <linux/interrupt.h> 17f7018c21STomi Valkeinen #include <linux/slab.h> 18f7018c21STomi Valkeinen #include <linux/delay.h> 19f7018c21STomi Valkeinen #include <linux/platform_device.h> 20f7018c21STomi Valkeinen #include <linux/dma-mapping.h> 21f7018c21STomi Valkeinen #include <linux/clk.h> 22f7018c21STomi Valkeinen #include <linux/err.h> 23f7018c21STomi Valkeinen #include <linux/vmalloc.h> 24f7018c21STomi Valkeinen #include <linux/uaccess.h> 25f7018c21STomi Valkeinen #include <linux/kthread.h> 26f7018c21STomi Valkeinen #include <linux/io.h> 27f7018c21STomi Valkeinen 28f7018c21STomi Valkeinen #include "mmp_ctrl.h" 29f7018c21STomi Valkeinen 30f7018c21STomi Valkeinen static irqreturn_t ctrl_handle_irq(int irq, void *dev_id) 31f7018c21STomi Valkeinen { 32f7018c21STomi Valkeinen struct mmphw_ctrl *ctrl = (struct mmphw_ctrl *)dev_id; 33f7018c21STomi Valkeinen u32 isr, imask, tmp; 34f7018c21STomi Valkeinen 35f7018c21STomi Valkeinen isr = readl_relaxed(ctrl->reg_base + SPU_IRQ_ISR); 36f7018c21STomi Valkeinen imask = readl_relaxed(ctrl->reg_base + SPU_IRQ_ENA); 37f7018c21STomi Valkeinen 38f7018c21STomi Valkeinen do { 39f7018c21STomi Valkeinen /* clear clock only */ 40f7018c21STomi Valkeinen tmp = readl_relaxed(ctrl->reg_base + SPU_IRQ_ISR); 41f7018c21STomi Valkeinen if (tmp & isr) 42f7018c21STomi Valkeinen writel_relaxed(~isr, ctrl->reg_base + SPU_IRQ_ISR); 43f7018c21STomi Valkeinen } while ((isr = readl_relaxed(ctrl->reg_base + SPU_IRQ_ISR)) & imask); 44f7018c21STomi Valkeinen 45f7018c21STomi Valkeinen return IRQ_HANDLED; 46f7018c21STomi Valkeinen } 47f7018c21STomi Valkeinen 48f7018c21STomi Valkeinen static u32 fmt_to_reg(struct mmp_overlay *overlay, int pix_fmt) 49f7018c21STomi Valkeinen { 50f7018c21STomi Valkeinen u32 rbswap = 0, uvswap = 0, yuvswap = 0, 51f7018c21STomi Valkeinen csc_en = 0, val = 0, 52f7018c21STomi Valkeinen vid = overlay_is_vid(overlay); 53f7018c21STomi Valkeinen 54f7018c21STomi Valkeinen switch (pix_fmt) { 55f7018c21STomi Valkeinen case PIXFMT_RGB565: 56f7018c21STomi Valkeinen case PIXFMT_RGB1555: 57f7018c21STomi Valkeinen case PIXFMT_RGB888PACK: 58f7018c21STomi Valkeinen case PIXFMT_RGB888UNPACK: 59f7018c21STomi Valkeinen case PIXFMT_RGBA888: 60f7018c21STomi Valkeinen rbswap = 1; 61f7018c21STomi Valkeinen break; 62f7018c21STomi Valkeinen case PIXFMT_VYUY: 63f7018c21STomi Valkeinen case PIXFMT_YVU422P: 64f7018c21STomi Valkeinen case PIXFMT_YVU420P: 65f7018c21STomi Valkeinen uvswap = 1; 66f7018c21STomi Valkeinen break; 67f7018c21STomi Valkeinen case PIXFMT_YUYV: 68f7018c21STomi Valkeinen yuvswap = 1; 69f7018c21STomi Valkeinen break; 70f7018c21STomi Valkeinen default: 71f7018c21STomi Valkeinen break; 72f7018c21STomi Valkeinen } 73f7018c21STomi Valkeinen 74f7018c21STomi Valkeinen switch (pix_fmt) { 75f7018c21STomi Valkeinen case PIXFMT_RGB565: 76f7018c21STomi Valkeinen case PIXFMT_BGR565: 77f7018c21STomi Valkeinen break; 78f7018c21STomi Valkeinen case PIXFMT_RGB1555: 79f7018c21STomi Valkeinen case PIXFMT_BGR1555: 80f7018c21STomi Valkeinen val = 0x1; 81f7018c21STomi Valkeinen break; 82f7018c21STomi Valkeinen case PIXFMT_RGB888PACK: 83f7018c21STomi Valkeinen case PIXFMT_BGR888PACK: 84f7018c21STomi Valkeinen val = 0x2; 85f7018c21STomi Valkeinen break; 86f7018c21STomi Valkeinen case PIXFMT_RGB888UNPACK: 87f7018c21STomi Valkeinen case PIXFMT_BGR888UNPACK: 88f7018c21STomi Valkeinen val = 0x3; 89f7018c21STomi Valkeinen break; 90f7018c21STomi Valkeinen case PIXFMT_RGBA888: 91f7018c21STomi Valkeinen case PIXFMT_BGRA888: 92f7018c21STomi Valkeinen val = 0x4; 93f7018c21STomi Valkeinen break; 94f7018c21STomi Valkeinen case PIXFMT_UYVY: 95f7018c21STomi Valkeinen case PIXFMT_VYUY: 96f7018c21STomi Valkeinen case PIXFMT_YUYV: 97f7018c21STomi Valkeinen val = 0x5; 98f7018c21STomi Valkeinen csc_en = 1; 99f7018c21STomi Valkeinen break; 100f7018c21STomi Valkeinen case PIXFMT_YUV422P: 101f7018c21STomi Valkeinen case PIXFMT_YVU422P: 102f7018c21STomi Valkeinen val = 0x6; 103f7018c21STomi Valkeinen csc_en = 1; 104f7018c21STomi Valkeinen break; 105f7018c21STomi Valkeinen case PIXFMT_YUV420P: 106f7018c21STomi Valkeinen case PIXFMT_YVU420P: 107f7018c21STomi Valkeinen val = 0x7; 108f7018c21STomi Valkeinen csc_en = 1; 109f7018c21STomi Valkeinen break; 110f7018c21STomi Valkeinen default: 111f7018c21STomi Valkeinen break; 112f7018c21STomi Valkeinen } 113f7018c21STomi Valkeinen 114f7018c21STomi Valkeinen return (dma_palette(0) | dma_fmt(vid, val) | 115f7018c21STomi Valkeinen dma_swaprb(vid, rbswap) | dma_swapuv(vid, uvswap) | 116f7018c21STomi Valkeinen dma_swapyuv(vid, yuvswap) | dma_csc(vid, csc_en)); 117f7018c21STomi Valkeinen } 118f7018c21STomi Valkeinen 119f7018c21STomi Valkeinen static void dmafetch_set_fmt(struct mmp_overlay *overlay) 120f7018c21STomi Valkeinen { 121f7018c21STomi Valkeinen u32 tmp; 122f7018c21STomi Valkeinen struct mmp_path *path = overlay->path; 123f7018c21STomi Valkeinen tmp = readl_relaxed(ctrl_regs(path) + dma_ctrl(0, path->id)); 124f7018c21STomi Valkeinen tmp &= ~dma_mask(overlay_is_vid(overlay)); 125f7018c21STomi Valkeinen tmp |= fmt_to_reg(overlay, overlay->win.pix_fmt); 126f7018c21STomi Valkeinen writel_relaxed(tmp, ctrl_regs(path) + dma_ctrl(0, path->id)); 127f7018c21STomi Valkeinen } 128f7018c21STomi Valkeinen 129f7018c21STomi Valkeinen static void overlay_set_win(struct mmp_overlay *overlay, struct mmp_win *win) 130f7018c21STomi Valkeinen { 131f7018c21STomi Valkeinen struct lcd_regs *regs = path_regs(overlay->path); 132f7018c21STomi Valkeinen 133f7018c21STomi Valkeinen /* assert win supported */ 134f7018c21STomi Valkeinen memcpy(&overlay->win, win, sizeof(struct mmp_win)); 135f7018c21STomi Valkeinen 136f7018c21STomi Valkeinen mutex_lock(&overlay->access_ok); 137f7018c21STomi Valkeinen 138f7018c21STomi Valkeinen if (overlay_is_vid(overlay)) { 139e41f6b17SBartlomiej Zolnierkiewicz writel_relaxed(win->pitch[0], 140e41f6b17SBartlomiej Zolnierkiewicz (void __iomem *)®s->v_pitch_yc); 141e41f6b17SBartlomiej Zolnierkiewicz writel_relaxed(win->pitch[2] << 16 | win->pitch[1], 142e41f6b17SBartlomiej Zolnierkiewicz (void __iomem *)®s->v_pitch_uv); 143f7018c21STomi Valkeinen 144e41f6b17SBartlomiej Zolnierkiewicz writel_relaxed((win->ysrc << 16) | win->xsrc, 145e41f6b17SBartlomiej Zolnierkiewicz (void __iomem *)®s->v_size); 146e41f6b17SBartlomiej Zolnierkiewicz writel_relaxed((win->ydst << 16) | win->xdst, 147e41f6b17SBartlomiej Zolnierkiewicz (void __iomem *)®s->v_size_z); 148e41f6b17SBartlomiej Zolnierkiewicz writel_relaxed(win->ypos << 16 | win->xpos, 149e41f6b17SBartlomiej Zolnierkiewicz (void __iomem *)®s->v_start); 150f7018c21STomi Valkeinen } else { 151e41f6b17SBartlomiej Zolnierkiewicz writel_relaxed(win->pitch[0], (void __iomem *)®s->g_pitch); 152f7018c21STomi Valkeinen 153e41f6b17SBartlomiej Zolnierkiewicz writel_relaxed((win->ysrc << 16) | win->xsrc, 154e41f6b17SBartlomiej Zolnierkiewicz (void __iomem *)®s->g_size); 155e41f6b17SBartlomiej Zolnierkiewicz writel_relaxed((win->ydst << 16) | win->xdst, 156e41f6b17SBartlomiej Zolnierkiewicz (void __iomem *)®s->g_size_z); 157e41f6b17SBartlomiej Zolnierkiewicz writel_relaxed(win->ypos << 16 | win->xpos, 158e41f6b17SBartlomiej Zolnierkiewicz (void __iomem *)®s->g_start); 159f7018c21STomi Valkeinen } 160f7018c21STomi Valkeinen 161f7018c21STomi Valkeinen dmafetch_set_fmt(overlay); 162f7018c21STomi Valkeinen mutex_unlock(&overlay->access_ok); 163f7018c21STomi Valkeinen } 164f7018c21STomi Valkeinen 165f7018c21STomi Valkeinen static void dmafetch_onoff(struct mmp_overlay *overlay, int on) 166f7018c21STomi Valkeinen { 167f7018c21STomi Valkeinen u32 mask = overlay_is_vid(overlay) ? CFG_DMA_ENA_MASK : 168f7018c21STomi Valkeinen CFG_GRA_ENA_MASK; 169f7018c21STomi Valkeinen u32 enable = overlay_is_vid(overlay) ? CFG_DMA_ENA(1) : CFG_GRA_ENA(1); 170f7018c21STomi Valkeinen u32 tmp; 171f7018c21STomi Valkeinen struct mmp_path *path = overlay->path; 172f7018c21STomi Valkeinen 173f7018c21STomi Valkeinen mutex_lock(&overlay->access_ok); 174f7018c21STomi Valkeinen tmp = readl_relaxed(ctrl_regs(path) + dma_ctrl(0, path->id)); 175f7018c21STomi Valkeinen tmp &= ~mask; 176f7018c21STomi Valkeinen tmp |= (on ? enable : 0); 177f7018c21STomi Valkeinen writel(tmp, ctrl_regs(path) + dma_ctrl(0, path->id)); 178f7018c21STomi Valkeinen mutex_unlock(&overlay->access_ok); 179f7018c21STomi Valkeinen } 180f7018c21STomi Valkeinen 181f7018c21STomi Valkeinen static void path_enabledisable(struct mmp_path *path, int on) 182f7018c21STomi Valkeinen { 183f7018c21STomi Valkeinen u32 tmp; 184f7018c21STomi Valkeinen mutex_lock(&path->access_ok); 185f7018c21STomi Valkeinen tmp = readl_relaxed(ctrl_regs(path) + LCD_SCLK(path)); 186f7018c21STomi Valkeinen if (on) 187f7018c21STomi Valkeinen tmp &= ~SCLK_DISABLE; 188f7018c21STomi Valkeinen else 189f7018c21STomi Valkeinen tmp |= SCLK_DISABLE; 190f7018c21STomi Valkeinen writel_relaxed(tmp, ctrl_regs(path) + LCD_SCLK(path)); 191f7018c21STomi Valkeinen mutex_unlock(&path->access_ok); 192f7018c21STomi Valkeinen } 193f7018c21STomi Valkeinen 194f7018c21STomi Valkeinen static void path_onoff(struct mmp_path *path, int on) 195f7018c21STomi Valkeinen { 196f7018c21STomi Valkeinen if (path->status == on) { 197f7018c21STomi Valkeinen dev_info(path->dev, "path %s is already %s\n", 198f7018c21STomi Valkeinen path->name, stat_name(path->status)); 199f7018c21STomi Valkeinen return; 200f7018c21STomi Valkeinen } 201f7018c21STomi Valkeinen 202f7018c21STomi Valkeinen if (on) { 203f7018c21STomi Valkeinen path_enabledisable(path, 1); 204f7018c21STomi Valkeinen 205f7018c21STomi Valkeinen if (path->panel && path->panel->set_onoff) 206f7018c21STomi Valkeinen path->panel->set_onoff(path->panel, 1); 207f7018c21STomi Valkeinen } else { 208f7018c21STomi Valkeinen if (path->panel && path->panel->set_onoff) 209f7018c21STomi Valkeinen path->panel->set_onoff(path->panel, 0); 210f7018c21STomi Valkeinen 211f7018c21STomi Valkeinen path_enabledisable(path, 0); 212f7018c21STomi Valkeinen } 213f7018c21STomi Valkeinen path->status = on; 214f7018c21STomi Valkeinen } 215f7018c21STomi Valkeinen 216f7018c21STomi Valkeinen static void overlay_set_onoff(struct mmp_overlay *overlay, int on) 217f7018c21STomi Valkeinen { 218f7018c21STomi Valkeinen if (overlay->status == on) { 219f7018c21STomi Valkeinen dev_info(overlay_to_ctrl(overlay)->dev, "overlay %s is already %s\n", 220f7018c21STomi Valkeinen overlay->path->name, stat_name(overlay->status)); 221f7018c21STomi Valkeinen return; 222f7018c21STomi Valkeinen } 223f7018c21STomi Valkeinen overlay->status = on; 224f7018c21STomi Valkeinen dmafetch_onoff(overlay, on); 225f7018c21STomi Valkeinen if (overlay->path->ops.check_status(overlay->path) 226f7018c21STomi Valkeinen != overlay->path->status) 227f7018c21STomi Valkeinen path_onoff(overlay->path, on); 228f7018c21STomi Valkeinen } 229f7018c21STomi Valkeinen 230f7018c21STomi Valkeinen static void overlay_set_fetch(struct mmp_overlay *overlay, int fetch_id) 231f7018c21STomi Valkeinen { 232f7018c21STomi Valkeinen overlay->dmafetch_id = fetch_id; 233f7018c21STomi Valkeinen } 234f7018c21STomi Valkeinen 235f7018c21STomi Valkeinen static int overlay_set_addr(struct mmp_overlay *overlay, struct mmp_addr *addr) 236f7018c21STomi Valkeinen { 237f7018c21STomi Valkeinen struct lcd_regs *regs = path_regs(overlay->path); 238f7018c21STomi Valkeinen 239f7018c21STomi Valkeinen /* FIXME: assert addr supported */ 240f7018c21STomi Valkeinen memcpy(&overlay->addr, addr, sizeof(struct mmp_addr)); 241f7018c21STomi Valkeinen 242f7018c21STomi Valkeinen if (overlay_is_vid(overlay)) { 243e41f6b17SBartlomiej Zolnierkiewicz writel_relaxed(addr->phys[0], (void __iomem *)®s->v_y0); 244e41f6b17SBartlomiej Zolnierkiewicz writel_relaxed(addr->phys[1], (void __iomem *)®s->v_u0); 245e41f6b17SBartlomiej Zolnierkiewicz writel_relaxed(addr->phys[2], (void __iomem *)®s->v_v0); 246f7018c21STomi Valkeinen } else 247e41f6b17SBartlomiej Zolnierkiewicz writel_relaxed(addr->phys[0], (void __iomem *)®s->g_0); 248f7018c21STomi Valkeinen 249f7018c21STomi Valkeinen return overlay->addr.phys[0]; 250f7018c21STomi Valkeinen } 251f7018c21STomi Valkeinen 252f7018c21STomi Valkeinen static void path_set_mode(struct mmp_path *path, struct mmp_mode *mode) 253f7018c21STomi Valkeinen { 254f7018c21STomi Valkeinen struct lcd_regs *regs = path_regs(path); 255f7018c21STomi Valkeinen u32 total_x, total_y, vsync_ctrl, tmp, sclk_src, sclk_div, 256f7018c21STomi Valkeinen link_config = path_to_path_plat(path)->link_config, 257f7018c21STomi Valkeinen dsi_rbswap = path_to_path_plat(path)->link_config; 258f7018c21STomi Valkeinen 259f7018c21STomi Valkeinen /* FIXME: assert videomode supported */ 260f7018c21STomi Valkeinen memcpy(&path->mode, mode, sizeof(struct mmp_mode)); 261f7018c21STomi Valkeinen 262f7018c21STomi Valkeinen mutex_lock(&path->access_ok); 263f7018c21STomi Valkeinen 264f7018c21STomi Valkeinen /* polarity of timing signals */ 265f7018c21STomi Valkeinen tmp = readl_relaxed(ctrl_regs(path) + intf_ctrl(path->id)) & 0x1; 266f7018c21STomi Valkeinen tmp |= mode->vsync_invert ? 0 : 0x8; 267f7018c21STomi Valkeinen tmp |= mode->hsync_invert ? 0 : 0x4; 268f7018c21STomi Valkeinen tmp |= link_config & CFG_DUMBMODE_MASK; 269f7018c21STomi Valkeinen tmp |= CFG_DUMB_ENA(1); 270f7018c21STomi Valkeinen writel_relaxed(tmp, ctrl_regs(path) + intf_ctrl(path->id)); 271f7018c21STomi Valkeinen 272f7018c21STomi Valkeinen /* interface rb_swap setting */ 273f7018c21STomi Valkeinen tmp = readl_relaxed(ctrl_regs(path) + intf_rbswap_ctrl(path->id)) & 274f7018c21STomi Valkeinen (~(CFG_INTFRBSWAP_MASK)); 275f7018c21STomi Valkeinen tmp |= dsi_rbswap & CFG_INTFRBSWAP_MASK; 276f7018c21STomi Valkeinen writel_relaxed(tmp, ctrl_regs(path) + intf_rbswap_ctrl(path->id)); 277f7018c21STomi Valkeinen 278e41f6b17SBartlomiej Zolnierkiewicz writel_relaxed((mode->yres << 16) | mode->xres, 279e41f6b17SBartlomiej Zolnierkiewicz (void __iomem *)®s->screen_active); 280f7018c21STomi Valkeinen writel_relaxed((mode->left_margin << 16) | mode->right_margin, 281e41f6b17SBartlomiej Zolnierkiewicz (void __iomem *)®s->screen_h_porch); 282f7018c21STomi Valkeinen writel_relaxed((mode->upper_margin << 16) | mode->lower_margin, 283e41f6b17SBartlomiej Zolnierkiewicz (void __iomem *)®s->screen_v_porch); 284f7018c21STomi Valkeinen total_x = mode->xres + mode->left_margin + mode->right_margin + 285f7018c21STomi Valkeinen mode->hsync_len; 286f7018c21STomi Valkeinen total_y = mode->yres + mode->upper_margin + mode->lower_margin + 287f7018c21STomi Valkeinen mode->vsync_len; 288e41f6b17SBartlomiej Zolnierkiewicz writel_relaxed((total_y << 16) | total_x, 289e41f6b17SBartlomiej Zolnierkiewicz (void __iomem *)®s->screen_size); 290f7018c21STomi Valkeinen 291f7018c21STomi Valkeinen /* vsync ctrl */ 292f7018c21STomi Valkeinen if (path->output_type == PATH_OUT_DSI) 293f7018c21STomi Valkeinen vsync_ctrl = 0x01330133; 294f7018c21STomi Valkeinen else 295f7018c21STomi Valkeinen vsync_ctrl = ((mode->xres + mode->right_margin) << 16) 296f7018c21STomi Valkeinen | (mode->xres + mode->right_margin); 297e41f6b17SBartlomiej Zolnierkiewicz writel_relaxed(vsync_ctrl, (void __iomem *)®s->vsync_ctrl); 298f7018c21STomi Valkeinen 299f7018c21STomi Valkeinen /* set pixclock div */ 300f7018c21STomi Valkeinen sclk_src = clk_get_rate(path_to_ctrl(path)->clk); 301f7018c21STomi Valkeinen sclk_div = sclk_src / mode->pixclock_freq; 302f7018c21STomi Valkeinen if (sclk_div * mode->pixclock_freq < sclk_src) 303f7018c21STomi Valkeinen sclk_div++; 304f7018c21STomi Valkeinen 305f7018c21STomi Valkeinen dev_info(path->dev, "%s sclk_src %d sclk_div 0x%x pclk %d\n", 306f7018c21STomi Valkeinen __func__, sclk_src, sclk_div, mode->pixclock_freq); 307f7018c21STomi Valkeinen 308f7018c21STomi Valkeinen tmp = readl_relaxed(ctrl_regs(path) + LCD_SCLK(path)); 309f7018c21STomi Valkeinen tmp &= ~CLK_INT_DIV_MASK; 310f7018c21STomi Valkeinen tmp |= sclk_div; 311f7018c21STomi Valkeinen writel_relaxed(tmp, ctrl_regs(path) + LCD_SCLK(path)); 312f7018c21STomi Valkeinen 313f7018c21STomi Valkeinen mutex_unlock(&path->access_ok); 314f7018c21STomi Valkeinen } 315f7018c21STomi Valkeinen 316f7018c21STomi Valkeinen static struct mmp_overlay_ops mmphw_overlay_ops = { 317f7018c21STomi Valkeinen .set_fetch = overlay_set_fetch, 318f7018c21STomi Valkeinen .set_onoff = overlay_set_onoff, 319f7018c21STomi Valkeinen .set_win = overlay_set_win, 320f7018c21STomi Valkeinen .set_addr = overlay_set_addr, 321f7018c21STomi Valkeinen }; 322f7018c21STomi Valkeinen 323f7018c21STomi Valkeinen static void ctrl_set_default(struct mmphw_ctrl *ctrl) 324f7018c21STomi Valkeinen { 325f7018c21STomi Valkeinen u32 tmp, irq_mask; 326f7018c21STomi Valkeinen 327f7018c21STomi Valkeinen /* 328f7018c21STomi Valkeinen * LCD Global control(LCD_TOP_CTRL) should be configed before 329f7018c21STomi Valkeinen * any other LCD registers read/write, or there maybe issues. 330f7018c21STomi Valkeinen */ 331f7018c21STomi Valkeinen tmp = readl_relaxed(ctrl->reg_base + LCD_TOP_CTRL); 332f7018c21STomi Valkeinen tmp |= 0xfff0; 333f7018c21STomi Valkeinen writel_relaxed(tmp, ctrl->reg_base + LCD_TOP_CTRL); 334f7018c21STomi Valkeinen 335f7018c21STomi Valkeinen 336f7018c21STomi Valkeinen /* disable all interrupts */ 337f7018c21STomi Valkeinen irq_mask = path_imasks(0) | err_imask(0) | 338f7018c21STomi Valkeinen path_imasks(1) | err_imask(1); 339f7018c21STomi Valkeinen tmp = readl_relaxed(ctrl->reg_base + SPU_IRQ_ENA); 340f7018c21STomi Valkeinen tmp &= ~irq_mask; 341f7018c21STomi Valkeinen tmp |= irq_mask; 342f7018c21STomi Valkeinen writel_relaxed(tmp, ctrl->reg_base + SPU_IRQ_ENA); 343f7018c21STomi Valkeinen } 344f7018c21STomi Valkeinen 345f7018c21STomi Valkeinen static void path_set_default(struct mmp_path *path) 346f7018c21STomi Valkeinen { 347f7018c21STomi Valkeinen struct lcd_regs *regs = path_regs(path); 348f7018c21STomi Valkeinen u32 dma_ctrl1, mask, tmp, path_config; 349f7018c21STomi Valkeinen 350f7018c21STomi Valkeinen path_config = path_to_path_plat(path)->path_config; 351f7018c21STomi Valkeinen 352f7018c21STomi Valkeinen /* Configure IOPAD: should be parallel only */ 353f7018c21STomi Valkeinen if (PATH_OUT_PARALLEL == path->output_type) { 354f7018c21STomi Valkeinen mask = CFG_IOPADMODE_MASK | CFG_BURST_MASK | CFG_BOUNDARY_MASK; 355f7018c21STomi Valkeinen tmp = readl_relaxed(ctrl_regs(path) + SPU_IOPAD_CONTROL); 356f7018c21STomi Valkeinen tmp &= ~mask; 357f7018c21STomi Valkeinen tmp |= path_config; 358f7018c21STomi Valkeinen writel_relaxed(tmp, ctrl_regs(path) + SPU_IOPAD_CONTROL); 359f7018c21STomi Valkeinen } 360f7018c21STomi Valkeinen 361f7018c21STomi Valkeinen /* Select path clock source */ 362f7018c21STomi Valkeinen tmp = readl_relaxed(ctrl_regs(path) + LCD_SCLK(path)); 363f7018c21STomi Valkeinen tmp &= ~SCLK_SRC_SEL_MASK; 364f7018c21STomi Valkeinen tmp |= path_config; 365f7018c21STomi Valkeinen writel_relaxed(tmp, ctrl_regs(path) + LCD_SCLK(path)); 366f7018c21STomi Valkeinen 367f7018c21STomi Valkeinen /* 368f7018c21STomi Valkeinen * Configure default bits: vsync triggers DMA, 369f7018c21STomi Valkeinen * power save enable, configure alpha registers to 370f7018c21STomi Valkeinen * display 100% graphics, and set pixel command. 371f7018c21STomi Valkeinen */ 372f7018c21STomi Valkeinen dma_ctrl1 = 0x2032ff81; 373f7018c21STomi Valkeinen 374f7018c21STomi Valkeinen dma_ctrl1 |= CFG_VSYNC_INV_MASK; 375f7018c21STomi Valkeinen writel_relaxed(dma_ctrl1, ctrl_regs(path) + dma_ctrl(1, path->id)); 376f7018c21STomi Valkeinen 377f7018c21STomi Valkeinen /* Configure default register values */ 378e41f6b17SBartlomiej Zolnierkiewicz writel_relaxed(0x00000000, (void __iomem *)®s->blank_color); 379e41f6b17SBartlomiej Zolnierkiewicz writel_relaxed(0x00000000, (void __iomem *)®s->g_1); 380e41f6b17SBartlomiej Zolnierkiewicz writel_relaxed(0x00000000, (void __iomem *)®s->g_start); 381f7018c21STomi Valkeinen 382f7018c21STomi Valkeinen /* 383f7018c21STomi Valkeinen * 1.enable multiple burst request in DMA AXI 384f7018c21STomi Valkeinen * bus arbiter for faster read if not tv path; 385f7018c21STomi Valkeinen * 2.enable horizontal smooth filter; 386f7018c21STomi Valkeinen */ 387f7018c21STomi Valkeinen mask = CFG_GRA_HSMOOTH_MASK | CFG_DMA_HSMOOTH_MASK | CFG_ARBFAST_ENA(1); 388f7018c21STomi Valkeinen tmp = readl_relaxed(ctrl_regs(path) + dma_ctrl(0, path->id)); 389f7018c21STomi Valkeinen tmp |= mask; 390f7018c21STomi Valkeinen if (PATH_TV == path->id) 391f7018c21STomi Valkeinen tmp &= ~CFG_ARBFAST_ENA(1); 392f7018c21STomi Valkeinen writel_relaxed(tmp, ctrl_regs(path) + dma_ctrl(0, path->id)); 393f7018c21STomi Valkeinen } 394f7018c21STomi Valkeinen 395f7018c21STomi Valkeinen static int path_init(struct mmphw_path_plat *path_plat, 396f7018c21STomi Valkeinen struct mmp_mach_path_config *config) 397f7018c21STomi Valkeinen { 398f7018c21STomi Valkeinen struct mmphw_ctrl *ctrl = path_plat->ctrl; 399f7018c21STomi Valkeinen struct mmp_path_info *path_info; 400f7018c21STomi Valkeinen struct mmp_path *path = NULL; 401f7018c21STomi Valkeinen 402f7018c21STomi Valkeinen dev_info(ctrl->dev, "%s: %s\n", __func__, config->name); 403f7018c21STomi Valkeinen 404f7018c21STomi Valkeinen /* init driver data */ 405965bef64SMarkus Elfring path_info = kzalloc(sizeof(*path_info), GFP_KERNEL); 406e0e894f5SMarkus Elfring if (!path_info) 407f7018c21STomi Valkeinen return 0; 408e0e894f5SMarkus Elfring 409f7018c21STomi Valkeinen path_info->name = config->name; 410f7018c21STomi Valkeinen path_info->id = path_plat->id; 411f7018c21STomi Valkeinen path_info->dev = ctrl->dev; 412f7018c21STomi Valkeinen path_info->overlay_num = config->overlay_num; 413f7018c21STomi Valkeinen path_info->overlay_ops = &mmphw_overlay_ops; 414f7018c21STomi Valkeinen path_info->set_mode = path_set_mode; 415f7018c21STomi Valkeinen path_info->plat_data = path_plat; 416f7018c21STomi Valkeinen 417f7018c21STomi Valkeinen /* create/register platform device */ 418f7018c21STomi Valkeinen path = mmp_register_path(path_info); 419f7018c21STomi Valkeinen if (!path) { 420f7018c21STomi Valkeinen kfree(path_info); 421f7018c21STomi Valkeinen return 0; 422f7018c21STomi Valkeinen } 423f7018c21STomi Valkeinen path_plat->path = path; 424f7018c21STomi Valkeinen path_plat->path_config = config->path_config; 425f7018c21STomi Valkeinen path_plat->link_config = config->link_config; 426f7018c21STomi Valkeinen path_plat->dsi_rbswap = config->dsi_rbswap; 427f7018c21STomi Valkeinen path_set_default(path); 428f7018c21STomi Valkeinen 429f7018c21STomi Valkeinen kfree(path_info); 430f7018c21STomi Valkeinen return 1; 431f7018c21STomi Valkeinen } 432f7018c21STomi Valkeinen 433f7018c21STomi Valkeinen static void path_deinit(struct mmphw_path_plat *path_plat) 434f7018c21STomi Valkeinen { 435f7018c21STomi Valkeinen if (!path_plat) 436f7018c21STomi Valkeinen return; 437f7018c21STomi Valkeinen 438f7018c21STomi Valkeinen mmp_unregister_path(path_plat->path); 439f7018c21STomi Valkeinen } 440f7018c21STomi Valkeinen 441f7018c21STomi Valkeinen static int mmphw_probe(struct platform_device *pdev) 442f7018c21STomi Valkeinen { 443f7018c21STomi Valkeinen struct mmp_mach_plat_info *mi; 444f7018c21STomi Valkeinen struct resource *res; 445b27b0017SGustavo A. R. Silva int ret, i, irq; 446f7018c21STomi Valkeinen struct mmphw_path_plat *path_plat; 447f7018c21STomi Valkeinen struct mmphw_ctrl *ctrl = NULL; 448f7018c21STomi Valkeinen 449f7018c21STomi Valkeinen /* get resources from platform data */ 450f7018c21STomi Valkeinen res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 451f7018c21STomi Valkeinen if (res == NULL) { 452f7018c21STomi Valkeinen dev_err(&pdev->dev, "%s: no IO memory defined\n", __func__); 453f7018c21STomi Valkeinen ret = -ENOENT; 454f7018c21STomi Valkeinen goto failed; 455f7018c21STomi Valkeinen } 456f7018c21STomi Valkeinen 457f7018c21STomi Valkeinen irq = platform_get_irq(pdev, 0); 458f7018c21STomi Valkeinen if (irq < 0) { 459f7018c21STomi Valkeinen ret = -ENOENT; 460f7018c21STomi Valkeinen goto failed; 461f7018c21STomi Valkeinen } 462f7018c21STomi Valkeinen 463f7018c21STomi Valkeinen /* get configs from platform data */ 464f7018c21STomi Valkeinen mi = pdev->dev.platform_data; 465f7018c21STomi Valkeinen if (mi == NULL || !mi->path_num || !mi->paths) { 466f7018c21STomi Valkeinen dev_err(&pdev->dev, "%s: no platform data defined\n", __func__); 467f7018c21STomi Valkeinen ret = -EINVAL; 468f7018c21STomi Valkeinen goto failed; 469f7018c21STomi Valkeinen } 470f7018c21STomi Valkeinen 471f7018c21STomi Valkeinen /* allocate */ 472b27b0017SGustavo A. R. Silva ctrl = devm_kzalloc(&pdev->dev, 473b27b0017SGustavo A. R. Silva struct_size(ctrl, path_plats, mi->path_num), 474b27b0017SGustavo A. R. Silva GFP_KERNEL); 475f7018c21STomi Valkeinen if (!ctrl) { 476f7018c21STomi Valkeinen ret = -ENOMEM; 477f7018c21STomi Valkeinen goto failed; 478f7018c21STomi Valkeinen } 479f7018c21STomi Valkeinen 480f7018c21STomi Valkeinen ctrl->name = mi->name; 481f7018c21STomi Valkeinen ctrl->path_num = mi->path_num; 482f7018c21STomi Valkeinen ctrl->dev = &pdev->dev; 483f7018c21STomi Valkeinen ctrl->irq = irq; 484f7018c21STomi Valkeinen platform_set_drvdata(pdev, ctrl); 485f7018c21STomi Valkeinen mutex_init(&ctrl->access_ok); 486f7018c21STomi Valkeinen 487f7018c21STomi Valkeinen /* map registers.*/ 488f7018c21STomi Valkeinen if (!devm_request_mem_region(ctrl->dev, res->start, 489f7018c21STomi Valkeinen resource_size(res), ctrl->name)) { 490f7018c21STomi Valkeinen dev_err(ctrl->dev, 491f7018c21STomi Valkeinen "can't request region for resource %pR\n", res); 492f7018c21STomi Valkeinen ret = -EINVAL; 493f7018c21STomi Valkeinen goto failed; 494f7018c21STomi Valkeinen } 495f7018c21STomi Valkeinen 4964bdc0d67SChristoph Hellwig ctrl->reg_base = devm_ioremap(ctrl->dev, 497f7018c21STomi Valkeinen res->start, resource_size(res)); 498f7018c21STomi Valkeinen if (ctrl->reg_base == NULL) { 499c3a2da26SArnd Bergmann dev_err(ctrl->dev, "%s: res %pR map failed\n", __func__, res); 500f7018c21STomi Valkeinen ret = -ENOMEM; 501f7018c21STomi Valkeinen goto failed; 502f7018c21STomi Valkeinen } 503f7018c21STomi Valkeinen 504f7018c21STomi Valkeinen /* request irq */ 505f7018c21STomi Valkeinen ret = devm_request_irq(ctrl->dev, ctrl->irq, ctrl_handle_irq, 506f7018c21STomi Valkeinen IRQF_SHARED, "lcd_controller", ctrl); 507f7018c21STomi Valkeinen if (ret < 0) { 508f7018c21STomi Valkeinen dev_err(ctrl->dev, "%s unable to request IRQ %d\n", 509f7018c21STomi Valkeinen __func__, ctrl->irq); 510f7018c21STomi Valkeinen ret = -ENXIO; 511f7018c21STomi Valkeinen goto failed; 512f7018c21STomi Valkeinen } 513f7018c21STomi Valkeinen 514f7018c21STomi Valkeinen /* get clock */ 515f7018c21STomi Valkeinen ctrl->clk = devm_clk_get(ctrl->dev, mi->clk_name); 516f7018c21STomi Valkeinen if (IS_ERR(ctrl->clk)) { 517*b3a7a9abSChristophe JAILLET ret = PTR_ERR(ctrl->clk); 51881b63420SCai Huoqing dev_err_probe(ctrl->dev, ret, 51981b63420SCai Huoqing "unable to get clk %s\n", mi->clk_name); 520f7018c21STomi Valkeinen goto failed; 521f7018c21STomi Valkeinen } 522f7018c21STomi Valkeinen clk_prepare_enable(ctrl->clk); 523f7018c21STomi Valkeinen 524f7018c21STomi Valkeinen /* init global regs */ 525f7018c21STomi Valkeinen ctrl_set_default(ctrl); 526f7018c21STomi Valkeinen 527f7018c21STomi Valkeinen /* init pathes from machine info and register them */ 528f7018c21STomi Valkeinen for (i = 0; i < ctrl->path_num; i++) { 529f7018c21STomi Valkeinen /* get from config and machine info */ 530f7018c21STomi Valkeinen path_plat = &ctrl->path_plats[i]; 531f7018c21STomi Valkeinen path_plat->id = i; 532f7018c21STomi Valkeinen path_plat->ctrl = ctrl; 533f7018c21STomi Valkeinen 534f7018c21STomi Valkeinen /* path init */ 535f7018c21STomi Valkeinen if (!path_init(path_plat, &mi->paths[i])) { 536f7018c21STomi Valkeinen ret = -EINVAL; 537f7018c21STomi Valkeinen goto failed_path_init; 538f7018c21STomi Valkeinen } 539f7018c21STomi Valkeinen } 540f7018c21STomi Valkeinen 541f7018c21STomi Valkeinen #ifdef CONFIG_MMP_DISP_SPI 542f7018c21STomi Valkeinen ret = lcd_spi_register(ctrl); 543f7018c21STomi Valkeinen if (ret < 0) 544f7018c21STomi Valkeinen goto failed_path_init; 545f7018c21STomi Valkeinen #endif 546f7018c21STomi Valkeinen 547f7018c21STomi Valkeinen dev_info(ctrl->dev, "device init done\n"); 548f7018c21STomi Valkeinen 549f7018c21STomi Valkeinen return 0; 550f7018c21STomi Valkeinen 551f7018c21STomi Valkeinen failed_path_init: 552f7018c21STomi Valkeinen for (i = 0; i < ctrl->path_num; i++) { 553f7018c21STomi Valkeinen path_plat = &ctrl->path_plats[i]; 554f7018c21STomi Valkeinen path_deinit(path_plat); 555f7018c21STomi Valkeinen } 556f7018c21STomi Valkeinen 557f7018c21STomi Valkeinen clk_disable_unprepare(ctrl->clk); 558f7018c21STomi Valkeinen failed: 559f7018c21STomi Valkeinen dev_err(&pdev->dev, "device init failed\n"); 560f7018c21STomi Valkeinen 561f7018c21STomi Valkeinen return ret; 562f7018c21STomi Valkeinen } 563f7018c21STomi Valkeinen 564f7018c21STomi Valkeinen static struct platform_driver mmphw_driver = { 565f7018c21STomi Valkeinen .driver = { 566f7018c21STomi Valkeinen .name = "mmp-disp", 567f7018c21STomi Valkeinen }, 568f7018c21STomi Valkeinen .probe = mmphw_probe, 569f7018c21STomi Valkeinen }; 570f7018c21STomi Valkeinen 571f7018c21STomi Valkeinen static int mmphw_init(void) 572f7018c21STomi Valkeinen { 573f7018c21STomi Valkeinen return platform_driver_register(&mmphw_driver); 574f7018c21STomi Valkeinen } 575f7018c21STomi Valkeinen module_init(mmphw_init); 576f7018c21STomi Valkeinen 577f7018c21STomi Valkeinen MODULE_AUTHOR("Li Guoqing<ligq@marvell.com>"); 578f7018c21STomi Valkeinen MODULE_DESCRIPTION("Framebuffer driver for mmp"); 579f7018c21STomi Valkeinen MODULE_LICENSE("GPL"); 580