1 /* 2 * Copyright (C) 2008 Andres Salomon <dilinger@debian.org> 3 * 4 * Geode GX2 header information 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 */ 11 #ifndef _GXFB_H_ 12 #define _GXFB_H_ 13 14 #include <linux/io.h> 15 16 #define GP_REG_COUNT (0x50 / 4) 17 #define DC_REG_COUNT (0x90 / 4) 18 #define VP_REG_COUNT (0x138 / 8) 19 #define FP_REG_COUNT (0x68 / 8) 20 21 #define DC_PAL_COUNT 0x104 22 23 struct gxfb_par { 24 int enable_crt; 25 void __iomem *dc_regs; 26 void __iomem *vid_regs; 27 void __iomem *gp_regs; 28 #ifdef CONFIG_PM 29 int powered_down; 30 31 /* register state, for power management functionality */ 32 struct { 33 uint64_t padsel; 34 uint64_t dotpll; 35 } msr; 36 37 uint32_t gp[GP_REG_COUNT]; 38 uint32_t dc[DC_REG_COUNT]; 39 uint64_t vp[VP_REG_COUNT]; 40 uint64_t fp[FP_REG_COUNT]; 41 42 uint32_t pal[DC_PAL_COUNT]; 43 #endif 44 }; 45 46 unsigned int gx_frame_buffer_size(void); 47 int gx_line_delta(int xres, int bpp); 48 void gx_set_mode(struct fb_info *info); 49 void gx_set_hw_palette_reg(struct fb_info *info, unsigned regno, 50 unsigned red, unsigned green, unsigned blue); 51 52 void gx_set_dclk_frequency(struct fb_info *info); 53 void gx_configure_display(struct fb_info *info); 54 int gx_blank_display(struct fb_info *info, int blank_mode); 55 56 #ifdef CONFIG_PM 57 int gx_powerdown(struct fb_info *info); 58 int gx_powerup(struct fb_info *info); 59 #endif 60 61 62 /* Graphics Processor registers (table 6-23 from the data book) */ 63 enum gp_registers { 64 GP_DST_OFFSET = 0, 65 GP_SRC_OFFSET, 66 GP_STRIDE, 67 GP_WID_HEIGHT, 68 69 GP_SRC_COLOR_FG, 70 GP_SRC_COLOR_BG, 71 GP_PAT_COLOR_0, 72 GP_PAT_COLOR_1, 73 74 GP_PAT_COLOR_2, 75 GP_PAT_COLOR_3, 76 GP_PAT_COLOR_4, 77 GP_PAT_COLOR_5, 78 79 GP_PAT_DATA_0, 80 GP_PAT_DATA_1, 81 GP_RASTER_MODE, 82 GP_VECTOR_MODE, 83 84 GP_BLT_MODE, 85 GP_BLT_STATUS, 86 GP_HST_SRC, 87 GP_BASE_OFFSET, /* 0x4c */ 88 }; 89 90 #define GP_BLT_STATUS_BLT_PENDING (1 << 2) 91 #define GP_BLT_STATUS_BLT_BUSY (1 << 0) 92 93 94 /* Display Controller registers (table 6-38 from the data book) */ 95 enum dc_registers { 96 DC_UNLOCK = 0, 97 DC_GENERAL_CFG, 98 DC_DISPLAY_CFG, 99 DC_RSVD_0, 100 101 DC_FB_ST_OFFSET, 102 DC_CB_ST_OFFSET, 103 DC_CURS_ST_OFFSET, 104 DC_ICON_ST_OFFSET, 105 106 DC_VID_Y_ST_OFFSET, 107 DC_VID_U_ST_OFFSET, 108 DC_VID_V_ST_OFFSET, 109 DC_RSVD_1, 110 111 DC_LINE_SIZE, 112 DC_GFX_PITCH, 113 DC_VID_YUV_PITCH, 114 DC_RSVD_2, 115 116 DC_H_ACTIVE_TIMING, 117 DC_H_BLANK_TIMING, 118 DC_H_SYNC_TIMING, 119 DC_RSVD_3, 120 121 DC_V_ACTIVE_TIMING, 122 DC_V_BLANK_TIMING, 123 DC_V_SYNC_TIMING, 124 DC_RSVD_4, 125 126 DC_CURSOR_X, 127 DC_CURSOR_Y, 128 DC_ICON_X, 129 DC_LINE_CNT, 130 131 DC_PAL_ADDRESS, 132 DC_PAL_DATA, 133 DC_DFIFO_DIAG, 134 DC_CFIFO_DIAG, 135 136 DC_VID_DS_DELTA, 137 DC_GLIU0_MEM_OFFSET, 138 DC_RSVD_5, 139 DC_DV_ACC, /* 0x8c */ 140 }; 141 142 #define DC_UNLOCK_LOCK 0x00000000 143 #define DC_UNLOCK_UNLOCK 0x00004758 /* magic value */ 144 145 #define DC_GENERAL_CFG_YUVM (1 << 20) 146 #define DC_GENERAL_CFG_VDSE (1 << 19) 147 #define DC_GENERAL_CFG_DFHPEL_SHIFT 12 148 #define DC_GENERAL_CFG_DFHPSL_SHIFT 8 149 #define DC_GENERAL_CFG_DECE (1 << 6) 150 #define DC_GENERAL_CFG_CMPE (1 << 5) 151 #define DC_GENERAL_CFG_VIDE (1 << 3) 152 #define DC_GENERAL_CFG_ICNE (1 << 2) 153 #define DC_GENERAL_CFG_CURE (1 << 1) 154 #define DC_GENERAL_CFG_DFLE (1 << 0) 155 156 #define DC_DISPLAY_CFG_A20M (1 << 31) 157 #define DC_DISPLAY_CFG_A18M (1 << 30) 158 #define DC_DISPLAY_CFG_PALB (1 << 25) 159 #define DC_DISPLAY_CFG_DISP_MODE_24BPP (1 << 9) 160 #define DC_DISPLAY_CFG_DISP_MODE_16BPP (1 << 8) 161 #define DC_DISPLAY_CFG_DISP_MODE_8BPP (0) 162 #define DC_DISPLAY_CFG_VDEN (1 << 4) 163 #define DC_DISPLAY_CFG_GDEN (1 << 3) 164 #define DC_DISPLAY_CFG_TGEN (1 << 0) 165 166 167 /* 168 * Video Processor registers (table 6-54). 169 * There is space for 64 bit values, but we never use more than the 170 * lower 32 bits. The actual register save/restore code only bothers 171 * to restore those 32 bits. 172 */ 173 enum vp_registers { 174 VP_VCFG = 0, 175 VP_DCFG, 176 177 VP_VX, 178 VP_VY, 179 180 VP_VS, 181 VP_VCK, 182 183 VP_VCM, 184 VP_GAR, 185 186 VP_GDR, 187 VP_RSVD_0, 188 189 VP_MISC, 190 VP_CCS, 191 192 VP_RSVD_1, 193 VP_RSVD_2, 194 195 VP_RSVD_3, 196 VP_VDC, 197 198 VP_VCO, 199 VP_CRC, 200 201 VP_CRC32, 202 VP_VDE, 203 204 VP_CCK, 205 VP_CCM, 206 207 VP_CC1, 208 VP_CC2, 209 210 VP_A1X, 211 VP_A1Y, 212 213 VP_A1C, 214 VP_A1T, 215 216 VP_A2X, 217 VP_A2Y, 218 219 VP_A2C, 220 VP_A2T, 221 222 VP_A3X, 223 VP_A3Y, 224 225 VP_A3C, 226 VP_A3T, 227 228 VP_VRR, 229 VP_AWT, 230 231 VP_VTM, /* 0x130 */ 232 }; 233 234 #define VP_VCFG_VID_EN (1 << 0) 235 236 #define VP_DCFG_DAC_VREF (1 << 26) 237 #define VP_DCFG_GV_GAM (1 << 21) 238 #define VP_DCFG_VG_CK (1 << 20) 239 #define VP_DCFG_CRT_SYNC_SKW_DEFAULT (1 << 16) 240 #define VP_DCFG_CRT_SYNC_SKW ((1 << 14) | (1 << 15) | (1 << 16)) 241 #define VP_DCFG_CRT_VSYNC_POL (1 << 9) 242 #define VP_DCFG_CRT_HSYNC_POL (1 << 8) 243 #define VP_DCFG_FP_DATA_EN (1 << 7) /* undocumented */ 244 #define VP_DCFG_FP_PWR_EN (1 << 6) /* undocumented */ 245 #define VP_DCFG_DAC_BL_EN (1 << 3) 246 #define VP_DCFG_VSYNC_EN (1 << 2) 247 #define VP_DCFG_HSYNC_EN (1 << 1) 248 #define VP_DCFG_CRT_EN (1 << 0) 249 250 #define VP_MISC_GAM_EN (1 << 0) 251 #define VP_MISC_DACPWRDN (1 << 10) 252 #define VP_MISC_APWRDN (1 << 11) 253 254 255 /* 256 * Flat Panel registers (table 6-55). 257 * Also 64 bit registers; see above note about 32-bit handling. 258 */ 259 260 /* we're actually in the VP register space, starting at address 0x400 */ 261 #define VP_FP_START 0x400 262 263 enum fp_registers { 264 FP_PT1 = 0, 265 FP_PT2, 266 267 FP_PM, 268 FP_DFC, 269 270 FP_BLFSR, 271 FP_RLFSR, 272 273 FP_FMI, 274 FP_FMD, 275 276 FP_RSVD_0, 277 FP_DCA, 278 279 FP_DMD, 280 FP_CRC, 281 282 FP_FBB, /* 0x460 */ 283 }; 284 285 #define FP_PT1_VSIZE_SHIFT 16 /* undocumented? */ 286 #define FP_PT1_VSIZE_MASK 0x7FF0000 /* undocumented? */ 287 288 #define FP_PT2_HSP (1 << 22) 289 #define FP_PT2_VSP (1 << 23) 290 291 #define FP_PM_P (1 << 24) /* panel power on */ 292 #define FP_PM_PANEL_PWR_UP (1 << 3) /* r/o */ 293 #define FP_PM_PANEL_PWR_DOWN (1 << 2) /* r/o */ 294 #define FP_PM_PANEL_OFF (1 << 1) /* r/o */ 295 #define FP_PM_PANEL_ON (1 << 0) /* r/o */ 296 297 #define FP_DFC_NFI ((1 << 4) | (1 << 5) | (1 << 6)) 298 299 300 /* register access functions */ 301 302 static inline uint32_t read_gp(struct gxfb_par *par, int reg) 303 { 304 return readl(par->gp_regs + 4*reg); 305 } 306 307 static inline void write_gp(struct gxfb_par *par, int reg, uint32_t val) 308 { 309 writel(val, par->gp_regs + 4*reg); 310 } 311 312 static inline uint32_t read_dc(struct gxfb_par *par, int reg) 313 { 314 return readl(par->dc_regs + 4*reg); 315 } 316 317 static inline void write_dc(struct gxfb_par *par, int reg, uint32_t val) 318 { 319 writel(val, par->dc_regs + 4*reg); 320 } 321 322 static inline uint32_t read_vp(struct gxfb_par *par, int reg) 323 { 324 return readl(par->vid_regs + 8*reg); 325 } 326 327 static inline void write_vp(struct gxfb_par *par, int reg, uint32_t val) 328 { 329 writel(val, par->vid_regs + 8*reg); 330 } 331 332 static inline uint32_t read_fp(struct gxfb_par *par, int reg) 333 { 334 return readl(par->vid_regs + 8*reg + VP_FP_START); 335 } 336 337 static inline void write_fp(struct gxfb_par *par, int reg, uint32_t val) 338 { 339 writel(val, par->vid_regs + 8*reg + VP_FP_START); 340 } 341 342 343 /* MSRs are defined in linux/cs5535.h; their bitfields are here */ 344 345 #define MSR_GLCP_SYS_RSTPLL_DOTPOSTDIV3 (1 << 3) 346 #define MSR_GLCP_SYS_RSTPLL_DOTPREMULT2 (1 << 2) 347 #define MSR_GLCP_SYS_RSTPLL_DOTPREDIV2 (1 << 1) 348 349 #define MSR_GLCP_DOTPLL_LOCK (1 << 25) /* r/o */ 350 #define MSR_GLCP_DOTPLL_BYPASS (1 << 15) 351 #define MSR_GLCP_DOTPLL_DOTRESET (1 << 0) 352 353 #define MSR_GX_MSR_PADSEL_MASK 0x3FFFFFFF /* undocumented? */ 354 #define MSR_GX_MSR_PADSEL_TFT 0x1FFFFFFF /* undocumented? */ 355 356 #define MSR_GX_GLD_MSR_CONFIG_FP (1 << 3) 357 358 #endif 359