1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Copyright (C) 2008 Andres Salomon <dilinger@debian.org> 4 * 5 * Geode GX2 header information 6 */ 7 #ifndef _GXFB_H_ 8 #define _GXFB_H_ 9 10 #include <linux/io.h> 11 12 #define GP_REG_COUNT (0x50 / 4) 13 #define DC_REG_COUNT (0x90 / 4) 14 #define VP_REG_COUNT (0x138 / 8) 15 #define FP_REG_COUNT (0x68 / 8) 16 17 #define DC_PAL_COUNT 0x104 18 19 struct gxfb_par { 20 int enable_crt; 21 void __iomem *dc_regs; 22 void __iomem *vid_regs; 23 void __iomem *gp_regs; 24 int powered_down; 25 26 /* register state, for power management functionality */ 27 struct { 28 uint64_t padsel; 29 uint64_t dotpll; 30 } msr; 31 32 uint32_t gp[GP_REG_COUNT]; 33 uint32_t dc[DC_REG_COUNT]; 34 uint64_t vp[VP_REG_COUNT]; 35 uint64_t fp[FP_REG_COUNT]; 36 37 uint32_t pal[DC_PAL_COUNT]; 38 }; 39 40 unsigned int gx_frame_buffer_size(void); 41 int gx_line_delta(int xres, int bpp); 42 void gx_set_mode(struct fb_info *info); 43 void gx_set_hw_palette_reg(struct fb_info *info, unsigned regno, 44 unsigned red, unsigned green, unsigned blue); 45 46 void gx_set_dclk_frequency(struct fb_info *info); 47 void gx_configure_display(struct fb_info *info); 48 int gx_blank_display(struct fb_info *info, int blank_mode); 49 50 int gx_powerdown(struct fb_info *info); 51 int gx_powerup(struct fb_info *info); 52 53 /* Graphics Processor registers (table 6-23 from the data book) */ 54 enum gp_registers { 55 GP_DST_OFFSET = 0, 56 GP_SRC_OFFSET, 57 GP_STRIDE, 58 GP_WID_HEIGHT, 59 60 GP_SRC_COLOR_FG, 61 GP_SRC_COLOR_BG, 62 GP_PAT_COLOR_0, 63 GP_PAT_COLOR_1, 64 65 GP_PAT_COLOR_2, 66 GP_PAT_COLOR_3, 67 GP_PAT_COLOR_4, 68 GP_PAT_COLOR_5, 69 70 GP_PAT_DATA_0, 71 GP_PAT_DATA_1, 72 GP_RASTER_MODE, 73 GP_VECTOR_MODE, 74 75 GP_BLT_MODE, 76 GP_BLT_STATUS, 77 GP_HST_SRC, 78 GP_BASE_OFFSET, /* 0x4c */ 79 }; 80 81 #define GP_BLT_STATUS_BLT_PENDING (1 << 2) 82 #define GP_BLT_STATUS_BLT_BUSY (1 << 0) 83 84 85 /* Display Controller registers (table 6-38 from the data book) */ 86 enum dc_registers { 87 DC_UNLOCK = 0, 88 DC_GENERAL_CFG, 89 DC_DISPLAY_CFG, 90 DC_RSVD_0, 91 92 DC_FB_ST_OFFSET, 93 DC_CB_ST_OFFSET, 94 DC_CURS_ST_OFFSET, 95 DC_ICON_ST_OFFSET, 96 97 DC_VID_Y_ST_OFFSET, 98 DC_VID_U_ST_OFFSET, 99 DC_VID_V_ST_OFFSET, 100 DC_RSVD_1, 101 102 DC_LINE_SIZE, 103 DC_GFX_PITCH, 104 DC_VID_YUV_PITCH, 105 DC_RSVD_2, 106 107 DC_H_ACTIVE_TIMING, 108 DC_H_BLANK_TIMING, 109 DC_H_SYNC_TIMING, 110 DC_RSVD_3, 111 112 DC_V_ACTIVE_TIMING, 113 DC_V_BLANK_TIMING, 114 DC_V_SYNC_TIMING, 115 DC_RSVD_4, 116 117 DC_CURSOR_X, 118 DC_CURSOR_Y, 119 DC_ICON_X, 120 DC_LINE_CNT, 121 122 DC_PAL_ADDRESS, 123 DC_PAL_DATA, 124 DC_DFIFO_DIAG, 125 DC_CFIFO_DIAG, 126 127 DC_VID_DS_DELTA, 128 DC_GLIU0_MEM_OFFSET, 129 DC_RSVD_5, 130 DC_DV_ACC, /* 0x8c */ 131 }; 132 133 #define DC_UNLOCK_LOCK 0x00000000 134 #define DC_UNLOCK_UNLOCK 0x00004758 /* magic value */ 135 136 #define DC_GENERAL_CFG_YUVM (1 << 20) 137 #define DC_GENERAL_CFG_VDSE (1 << 19) 138 #define DC_GENERAL_CFG_DFHPEL_SHIFT 12 139 #define DC_GENERAL_CFG_DFHPSL_SHIFT 8 140 #define DC_GENERAL_CFG_DECE (1 << 6) 141 #define DC_GENERAL_CFG_CMPE (1 << 5) 142 #define DC_GENERAL_CFG_VIDE (1 << 3) 143 #define DC_GENERAL_CFG_ICNE (1 << 2) 144 #define DC_GENERAL_CFG_CURE (1 << 1) 145 #define DC_GENERAL_CFG_DFLE (1 << 0) 146 147 #define DC_DISPLAY_CFG_A20M (1 << 31) 148 #define DC_DISPLAY_CFG_A18M (1 << 30) 149 #define DC_DISPLAY_CFG_PALB (1 << 25) 150 #define DC_DISPLAY_CFG_DISP_MODE_24BPP (1 << 9) 151 #define DC_DISPLAY_CFG_DISP_MODE_16BPP (1 << 8) 152 #define DC_DISPLAY_CFG_DISP_MODE_8BPP (0) 153 #define DC_DISPLAY_CFG_VDEN (1 << 4) 154 #define DC_DISPLAY_CFG_GDEN (1 << 3) 155 #define DC_DISPLAY_CFG_TGEN (1 << 0) 156 157 158 /* 159 * Video Processor registers (table 6-54). 160 * There is space for 64 bit values, but we never use more than the 161 * lower 32 bits. The actual register save/restore code only bothers 162 * to restore those 32 bits. 163 */ 164 enum vp_registers { 165 VP_VCFG = 0, 166 VP_DCFG, 167 168 VP_VX, 169 VP_VY, 170 171 VP_VS, 172 VP_VCK, 173 174 VP_VCM, 175 VP_GAR, 176 177 VP_GDR, 178 VP_RSVD_0, 179 180 VP_MISC, 181 VP_CCS, 182 183 VP_RSVD_1, 184 VP_RSVD_2, 185 186 VP_RSVD_3, 187 VP_VDC, 188 189 VP_VCO, 190 VP_CRC, 191 192 VP_CRC32, 193 VP_VDE, 194 195 VP_CCK, 196 VP_CCM, 197 198 VP_CC1, 199 VP_CC2, 200 201 VP_A1X, 202 VP_A1Y, 203 204 VP_A1C, 205 VP_A1T, 206 207 VP_A2X, 208 VP_A2Y, 209 210 VP_A2C, 211 VP_A2T, 212 213 VP_A3X, 214 VP_A3Y, 215 216 VP_A3C, 217 VP_A3T, 218 219 VP_VRR, 220 VP_AWT, 221 222 VP_VTM, /* 0x130 */ 223 }; 224 225 #define VP_VCFG_VID_EN (1 << 0) 226 227 #define VP_DCFG_DAC_VREF (1 << 26) 228 #define VP_DCFG_GV_GAM (1 << 21) 229 #define VP_DCFG_VG_CK (1 << 20) 230 #define VP_DCFG_CRT_SYNC_SKW_DEFAULT (1 << 16) 231 #define VP_DCFG_CRT_SYNC_SKW ((1 << 14) | (1 << 15) | (1 << 16)) 232 #define VP_DCFG_CRT_VSYNC_POL (1 << 9) 233 #define VP_DCFG_CRT_HSYNC_POL (1 << 8) 234 #define VP_DCFG_FP_DATA_EN (1 << 7) /* undocumented */ 235 #define VP_DCFG_FP_PWR_EN (1 << 6) /* undocumented */ 236 #define VP_DCFG_DAC_BL_EN (1 << 3) 237 #define VP_DCFG_VSYNC_EN (1 << 2) 238 #define VP_DCFG_HSYNC_EN (1 << 1) 239 #define VP_DCFG_CRT_EN (1 << 0) 240 241 #define VP_MISC_GAM_EN (1 << 0) 242 #define VP_MISC_DACPWRDN (1 << 10) 243 #define VP_MISC_APWRDN (1 << 11) 244 245 246 /* 247 * Flat Panel registers (table 6-55). 248 * Also 64 bit registers; see above note about 32-bit handling. 249 */ 250 251 /* we're actually in the VP register space, starting at address 0x400 */ 252 #define VP_FP_START 0x400 253 254 enum fp_registers { 255 FP_PT1 = 0, 256 FP_PT2, 257 258 FP_PM, 259 FP_DFC, 260 261 FP_BLFSR, 262 FP_RLFSR, 263 264 FP_FMI, 265 FP_FMD, 266 267 FP_RSVD_0, 268 FP_DCA, 269 270 FP_DMD, 271 FP_CRC, 272 273 FP_FBB, /* 0x460 */ 274 }; 275 276 #define FP_PT1_VSIZE_SHIFT 16 /* undocumented? */ 277 #define FP_PT1_VSIZE_MASK 0x7FF0000 /* undocumented? */ 278 279 #define FP_PT2_HSP (1 << 22) 280 #define FP_PT2_VSP (1 << 23) 281 282 #define FP_PM_P (1 << 24) /* panel power on */ 283 #define FP_PM_PANEL_PWR_UP (1 << 3) /* r/o */ 284 #define FP_PM_PANEL_PWR_DOWN (1 << 2) /* r/o */ 285 #define FP_PM_PANEL_OFF (1 << 1) /* r/o */ 286 #define FP_PM_PANEL_ON (1 << 0) /* r/o */ 287 288 #define FP_DFC_NFI ((1 << 4) | (1 << 5) | (1 << 6)) 289 290 291 /* register access functions */ 292 293 static inline uint32_t read_gp(struct gxfb_par *par, int reg) 294 { 295 return readl(par->gp_regs + 4*reg); 296 } 297 298 static inline void write_gp(struct gxfb_par *par, int reg, uint32_t val) 299 { 300 writel(val, par->gp_regs + 4*reg); 301 } 302 303 static inline uint32_t read_dc(struct gxfb_par *par, int reg) 304 { 305 return readl(par->dc_regs + 4*reg); 306 } 307 308 static inline void write_dc(struct gxfb_par *par, int reg, uint32_t val) 309 { 310 writel(val, par->dc_regs + 4*reg); 311 } 312 313 static inline uint32_t read_vp(struct gxfb_par *par, int reg) 314 { 315 return readl(par->vid_regs + 8*reg); 316 } 317 318 static inline void write_vp(struct gxfb_par *par, int reg, uint32_t val) 319 { 320 writel(val, par->vid_regs + 8*reg); 321 } 322 323 static inline uint32_t read_fp(struct gxfb_par *par, int reg) 324 { 325 return readl(par->vid_regs + 8*reg + VP_FP_START); 326 } 327 328 static inline void write_fp(struct gxfb_par *par, int reg, uint32_t val) 329 { 330 writel(val, par->vid_regs + 8*reg + VP_FP_START); 331 } 332 333 334 /* MSRs are defined in linux/cs5535.h; their bitfields are here */ 335 336 #define MSR_GLCP_SYS_RSTPLL_DOTPOSTDIV3 (1 << 3) 337 #define MSR_GLCP_SYS_RSTPLL_DOTPREMULT2 (1 << 2) 338 #define MSR_GLCP_SYS_RSTPLL_DOTPREDIV2 (1 << 1) 339 340 #define MSR_GLCP_DOTPLL_LOCK (1 << 25) /* r/o */ 341 #define MSR_GLCP_DOTPLL_BYPASS (1 << 15) 342 #define MSR_GLCP_DOTPLL_DOTRESET (1 << 0) 343 344 #define MSR_GX_MSR_PADSEL_MASK 0x3FFFFFFF /* undocumented? */ 345 #define MSR_GX_MSR_PADSEL_TFT 0x1FFFFFFF /* undocumented? */ 346 347 #define MSR_GX_GLD_MSR_CONFIG_FP (1 << 3) 348 349 #endif 350