1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * Geode GX display controller.
4  *
5  *   Copyright (C) 2005 Arcom Control Systems Ltd.
6  *
7  *   Portions from AMD's original 2.4 driver:
8  *     Copyright (C) 2004 Advanced Micro Devices, Inc.
9  */
10 #include <linux/spinlock.h>
11 #include <linux/fb.h>
12 #include <linux/delay.h>
13 #include <asm/io.h>
14 #include <asm/div64.h>
15 #include <asm/delay.h>
16 #include <linux/cs5535.h>
17 
18 #include "gxfb.h"
19 
20 unsigned int gx_frame_buffer_size(void)
21 {
22 	unsigned int val;
23 
24 	if (!cs5535_has_vsa2()) {
25 		uint32_t hi, lo;
26 
27 		/* The number of pages is (PMAX - PMIN)+1 */
28 		rdmsr(MSR_GLIU_P2D_RO0, lo, hi);
29 
30 		/* PMAX */
31 		val = ((hi & 0xff) << 12) | ((lo & 0xfff00000) >> 20);
32 		/* PMIN */
33 		val -= (lo & 0x000fffff);
34 		val += 1;
35 
36 		/* The page size is 4k */
37 		return (val << 12);
38 	}
39 
40 	/* FB size can be obtained from the VSA II */
41 	/* Virtual register class = 0x02 */
42 	/* VG_MEM_SIZE(512Kb units) = 0x00 */
43 
44 	outw(VSA_VR_UNLOCK, VSA_VRC_INDEX);
45 	outw(VSA_VR_MEM_SIZE, VSA_VRC_INDEX);
46 
47 	val = (unsigned int)(inw(VSA_VRC_DATA)) & 0xFFl;
48 	return (val << 19);
49 }
50 
51 int gx_line_delta(int xres, int bpp)
52 {
53 	/* Must be a multiple of 8 bytes. */
54 	return (xres * (bpp >> 3) + 7) & ~0x7;
55 }
56 
57 void gx_set_mode(struct fb_info *info)
58 {
59 	struct gxfb_par *par = info->par;
60 	u32 gcfg, dcfg;
61 	int hactive, hblankstart, hsyncstart, hsyncend, hblankend, htotal;
62 	int vactive, vblankstart, vsyncstart, vsyncend, vblankend, vtotal;
63 
64 	/* Unlock the display controller registers. */
65 	write_dc(par, DC_UNLOCK, DC_UNLOCK_UNLOCK);
66 
67 	gcfg = read_dc(par, DC_GENERAL_CFG);
68 	dcfg = read_dc(par, DC_DISPLAY_CFG);
69 
70 	/* Disable the timing generator. */
71 	dcfg &= ~DC_DISPLAY_CFG_TGEN;
72 	write_dc(par, DC_DISPLAY_CFG, dcfg);
73 
74 	/* Wait for pending memory requests before disabling the FIFO load. */
75 	udelay(100);
76 
77 	/* Disable FIFO load and compression. */
78 	gcfg &= ~(DC_GENERAL_CFG_DFLE | DC_GENERAL_CFG_CMPE |
79 			DC_GENERAL_CFG_DECE);
80 	write_dc(par, DC_GENERAL_CFG, gcfg);
81 
82 	/* Setup DCLK and its divisor. */
83 	gx_set_dclk_frequency(info);
84 
85 	/*
86 	 * Setup new mode.
87 	 */
88 
89 	/* Clear all unused feature bits. */
90 	gcfg &= DC_GENERAL_CFG_YUVM | DC_GENERAL_CFG_VDSE;
91 	dcfg = 0;
92 
93 	/* Set FIFO priority (default 6/5) and enable. */
94 	/* FIXME: increase fifo priority for 1280x1024 and higher modes? */
95 	gcfg |= (6 << DC_GENERAL_CFG_DFHPEL_SHIFT) |
96 		(5 << DC_GENERAL_CFG_DFHPSL_SHIFT) | DC_GENERAL_CFG_DFLE;
97 
98 	/* Framebuffer start offset. */
99 	write_dc(par, DC_FB_ST_OFFSET, 0);
100 
101 	/* Line delta and line buffer length. */
102 	write_dc(par, DC_GFX_PITCH, info->fix.line_length >> 3);
103 	write_dc(par, DC_LINE_SIZE,
104 		((info->var.xres * info->var.bits_per_pixel/8) >> 3) + 2);
105 
106 
107 	/* Enable graphics and video data and unmask address lines. */
108 	dcfg |= DC_DISPLAY_CFG_GDEN | DC_DISPLAY_CFG_VDEN |
109 		DC_DISPLAY_CFG_A20M | DC_DISPLAY_CFG_A18M;
110 
111 	/* Set pixel format. */
112 	switch (info->var.bits_per_pixel) {
113 	case 8:
114 		dcfg |= DC_DISPLAY_CFG_DISP_MODE_8BPP;
115 		break;
116 	case 16:
117 		dcfg |= DC_DISPLAY_CFG_DISP_MODE_16BPP;
118 		break;
119 	case 32:
120 		dcfg |= DC_DISPLAY_CFG_DISP_MODE_24BPP;
121 		dcfg |= DC_DISPLAY_CFG_PALB;
122 		break;
123 	}
124 
125 	/* Enable timing generator. */
126 	dcfg |= DC_DISPLAY_CFG_TGEN;
127 
128 	/* Horizontal and vertical timings. */
129 	hactive = info->var.xres;
130 	hblankstart = hactive;
131 	hsyncstart = hblankstart + info->var.right_margin;
132 	hsyncend =  hsyncstart + info->var.hsync_len;
133 	hblankend = hsyncend + info->var.left_margin;
134 	htotal = hblankend;
135 
136 	vactive = info->var.yres;
137 	vblankstart = vactive;
138 	vsyncstart = vblankstart + info->var.lower_margin;
139 	vsyncend =  vsyncstart + info->var.vsync_len;
140 	vblankend = vsyncend + info->var.upper_margin;
141 	vtotal = vblankend;
142 
143 	write_dc(par, DC_H_ACTIVE_TIMING, (hactive - 1)    |
144 			((htotal - 1) << 16));
145 	write_dc(par, DC_H_BLANK_TIMING, (hblankstart - 1) |
146 			((hblankend - 1) << 16));
147 	write_dc(par, DC_H_SYNC_TIMING, (hsyncstart - 1)   |
148 			((hsyncend - 1) << 16));
149 
150 	write_dc(par, DC_V_ACTIVE_TIMING, (vactive - 1)    |
151 			((vtotal - 1) << 16));
152 	write_dc(par, DC_V_BLANK_TIMING, (vblankstart - 1) |
153 			((vblankend - 1) << 16));
154 	write_dc(par, DC_V_SYNC_TIMING, (vsyncstart - 1)   |
155 			((vsyncend - 1) << 16));
156 
157 	/* Write final register values. */
158 	write_dc(par, DC_DISPLAY_CFG, dcfg);
159 	write_dc(par, DC_GENERAL_CFG, gcfg);
160 
161 	gx_configure_display(info);
162 
163 	/* Relock display controller registers */
164 	write_dc(par, DC_UNLOCK, DC_UNLOCK_LOCK);
165 }
166 
167 void gx_set_hw_palette_reg(struct fb_info *info, unsigned regno,
168 		unsigned red, unsigned green, unsigned blue)
169 {
170 	struct gxfb_par *par = info->par;
171 	int val;
172 
173 	/* Hardware palette is in RGB 8-8-8 format. */
174 	val  = (red   << 8) & 0xff0000;
175 	val |= (green)      & 0x00ff00;
176 	val |= (blue  >> 8) & 0x0000ff;
177 
178 	write_dc(par, DC_PAL_ADDRESS, regno);
179 	write_dc(par, DC_PAL_DATA, val);
180 }
181