1 /* 2 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. 3 * 4 * Freescale DIU Frame Buffer device driver 5 * 6 * Authors: Hongjun Chen <hong-jun.chen@freescale.com> 7 * Paul Widmer <paul.widmer@freescale.com> 8 * Srikanth Srinivasan <srikanth.srinivasan@freescale.com> 9 * York Sun <yorksun@freescale.com> 10 * 11 * Based on imxfb.c Copyright (C) 2004 S.Hauer, Pengutronix 12 * 13 * This program is free software; you can redistribute it and/or modify it 14 * under the terms of the GNU General Public License as published by the 15 * Free Software Foundation; either version 2 of the License, or (at your 16 * option) any later version. 17 * 18 */ 19 20 #include <linux/module.h> 21 #include <linux/kernel.h> 22 #include <linux/errno.h> 23 #include <linux/string.h> 24 #include <linux/slab.h> 25 #include <linux/fb.h> 26 #include <linux/init.h> 27 #include <linux/dma-mapping.h> 28 #include <linux/platform_device.h> 29 #include <linux/interrupt.h> 30 #include <linux/clk.h> 31 #include <linux/uaccess.h> 32 #include <linux/vmalloc.h> 33 #include <linux/spinlock.h> 34 #include <linux/of_address.h> 35 #include <linux/of_irq.h> 36 37 #include <sysdev/fsl_soc.h> 38 #include <linux/fsl-diu-fb.h> 39 #include "edid.h" 40 41 #define NUM_AOIS 5 /* 1 for plane 0, 2 for planes 1 & 2 each */ 42 43 /* HW cursor parameters */ 44 #define MAX_CURS 32 45 46 /* INT_STATUS/INT_MASK field descriptions */ 47 #define INT_VSYNC 0x01 /* Vsync interrupt */ 48 #define INT_VSYNC_WB 0x02 /* Vsync interrupt for write back operation */ 49 #define INT_UNDRUN 0x04 /* Under run exception interrupt */ 50 #define INT_PARERR 0x08 /* Display parameters error interrupt */ 51 #define INT_LS_BF_VS 0x10 /* Lines before vsync. interrupt */ 52 53 /* 54 * List of supported video modes 55 * 56 * The first entry is the default video mode. The remain entries are in 57 * order if increasing resolution and frequency. The 320x240-60 mode is 58 * the initial AOI for the second and third planes. 59 */ 60 static struct fb_videomode fsl_diu_mode_db[] = { 61 { 62 .refresh = 60, 63 .xres = 1024, 64 .yres = 768, 65 .pixclock = 15385, 66 .left_margin = 160, 67 .right_margin = 24, 68 .upper_margin = 29, 69 .lower_margin = 3, 70 .hsync_len = 136, 71 .vsync_len = 6, 72 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, 73 .vmode = FB_VMODE_NONINTERLACED 74 }, 75 { 76 .refresh = 60, 77 .xres = 320, 78 .yres = 240, 79 .pixclock = 79440, 80 .left_margin = 16, 81 .right_margin = 16, 82 .upper_margin = 16, 83 .lower_margin = 5, 84 .hsync_len = 48, 85 .vsync_len = 1, 86 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, 87 .vmode = FB_VMODE_NONINTERLACED 88 }, 89 { 90 .refresh = 60, 91 .xres = 640, 92 .yres = 480, 93 .pixclock = 39722, 94 .left_margin = 48, 95 .right_margin = 16, 96 .upper_margin = 33, 97 .lower_margin = 10, 98 .hsync_len = 96, 99 .vsync_len = 2, 100 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, 101 .vmode = FB_VMODE_NONINTERLACED 102 }, 103 { 104 .refresh = 72, 105 .xres = 640, 106 .yres = 480, 107 .pixclock = 32052, 108 .left_margin = 128, 109 .right_margin = 24, 110 .upper_margin = 28, 111 .lower_margin = 9, 112 .hsync_len = 40, 113 .vsync_len = 3, 114 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, 115 .vmode = FB_VMODE_NONINTERLACED 116 }, 117 { 118 .refresh = 75, 119 .xres = 640, 120 .yres = 480, 121 .pixclock = 31747, 122 .left_margin = 120, 123 .right_margin = 16, 124 .upper_margin = 16, 125 .lower_margin = 1, 126 .hsync_len = 64, 127 .vsync_len = 3, 128 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, 129 .vmode = FB_VMODE_NONINTERLACED 130 }, 131 { 132 .refresh = 90, 133 .xres = 640, 134 .yres = 480, 135 .pixclock = 25057, 136 .left_margin = 120, 137 .right_margin = 32, 138 .upper_margin = 14, 139 .lower_margin = 25, 140 .hsync_len = 40, 141 .vsync_len = 14, 142 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, 143 .vmode = FB_VMODE_NONINTERLACED 144 }, 145 { 146 .refresh = 100, 147 .xres = 640, 148 .yres = 480, 149 .pixclock = 22272, 150 .left_margin = 48, 151 .right_margin = 32, 152 .upper_margin = 17, 153 .lower_margin = 22, 154 .hsync_len = 128, 155 .vsync_len = 12, 156 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, 157 .vmode = FB_VMODE_NONINTERLACED 158 }, 159 { 160 .refresh = 60, 161 .xres = 800, 162 .yres = 480, 163 .pixclock = 33805, 164 .left_margin = 96, 165 .right_margin = 24, 166 .upper_margin = 10, 167 .lower_margin = 3, 168 .hsync_len = 72, 169 .vsync_len = 7, 170 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, 171 .vmode = FB_VMODE_NONINTERLACED 172 }, 173 { 174 .refresh = 60, 175 .xres = 800, 176 .yres = 600, 177 .pixclock = 25000, 178 .left_margin = 88, 179 .right_margin = 40, 180 .upper_margin = 23, 181 .lower_margin = 1, 182 .hsync_len = 128, 183 .vsync_len = 4, 184 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, 185 .vmode = FB_VMODE_NONINTERLACED 186 }, 187 { 188 .refresh = 60, 189 .xres = 854, 190 .yres = 480, 191 .pixclock = 31518, 192 .left_margin = 104, 193 .right_margin = 16, 194 .upper_margin = 13, 195 .lower_margin = 1, 196 .hsync_len = 88, 197 .vsync_len = 3, 198 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, 199 .vmode = FB_VMODE_NONINTERLACED 200 }, 201 { 202 .refresh = 70, 203 .xres = 1024, 204 .yres = 768, 205 .pixclock = 16886, 206 .left_margin = 3, 207 .right_margin = 3, 208 .upper_margin = 2, 209 .lower_margin = 2, 210 .hsync_len = 40, 211 .vsync_len = 18, 212 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, 213 .vmode = FB_VMODE_NONINTERLACED 214 }, 215 { 216 .refresh = 75, 217 .xres = 1024, 218 .yres = 768, 219 .pixclock = 15009, 220 .left_margin = 3, 221 .right_margin = 3, 222 .upper_margin = 2, 223 .lower_margin = 2, 224 .hsync_len = 80, 225 .vsync_len = 32, 226 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, 227 .vmode = FB_VMODE_NONINTERLACED 228 }, 229 { 230 .refresh = 60, 231 .xres = 1280, 232 .yres = 480, 233 .pixclock = 18939, 234 .left_margin = 353, 235 .right_margin = 47, 236 .upper_margin = 39, 237 .lower_margin = 4, 238 .hsync_len = 8, 239 .vsync_len = 2, 240 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, 241 .vmode = FB_VMODE_NONINTERLACED 242 }, 243 { 244 .refresh = 60, 245 .xres = 1280, 246 .yres = 720, 247 .pixclock = 13426, 248 .left_margin = 192, 249 .right_margin = 64, 250 .upper_margin = 22, 251 .lower_margin = 1, 252 .hsync_len = 136, 253 .vsync_len = 3, 254 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, 255 .vmode = FB_VMODE_NONINTERLACED 256 }, 257 { 258 .refresh = 60, 259 .xres = 1280, 260 .yres = 1024, 261 .pixclock = 9375, 262 .left_margin = 38, 263 .right_margin = 128, 264 .upper_margin = 2, 265 .lower_margin = 7, 266 .hsync_len = 216, 267 .vsync_len = 37, 268 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, 269 .vmode = FB_VMODE_NONINTERLACED 270 }, 271 { 272 .refresh = 70, 273 .xres = 1280, 274 .yres = 1024, 275 .pixclock = 9380, 276 .left_margin = 6, 277 .right_margin = 6, 278 .upper_margin = 4, 279 .lower_margin = 4, 280 .hsync_len = 60, 281 .vsync_len = 94, 282 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, 283 .vmode = FB_VMODE_NONINTERLACED 284 }, 285 { 286 .refresh = 75, 287 .xres = 1280, 288 .yres = 1024, 289 .pixclock = 9380, 290 .left_margin = 6, 291 .right_margin = 6, 292 .upper_margin = 4, 293 .lower_margin = 4, 294 .hsync_len = 60, 295 .vsync_len = 15, 296 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, 297 .vmode = FB_VMODE_NONINTERLACED 298 }, 299 { 300 .refresh = 60, 301 .xres = 1920, 302 .yres = 1080, 303 .pixclock = 5787, 304 .left_margin = 328, 305 .right_margin = 120, 306 .upper_margin = 34, 307 .lower_margin = 1, 308 .hsync_len = 208, 309 .vsync_len = 3, 310 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, 311 .vmode = FB_VMODE_NONINTERLACED 312 }, 313 }; 314 315 static char *fb_mode; 316 static unsigned long default_bpp = 32; 317 static enum fsl_diu_monitor_port monitor_port; 318 static char *monitor_string; 319 320 #if defined(CONFIG_NOT_COHERENT_CACHE) 321 static u8 *coherence_data; 322 static size_t coherence_data_size; 323 static unsigned int d_cache_line_size; 324 #endif 325 326 static DEFINE_SPINLOCK(diu_lock); 327 328 enum mfb_index { 329 PLANE0 = 0, /* Plane 0, only one AOI that fills the screen */ 330 PLANE1_AOI0, /* Plane 1, first AOI */ 331 PLANE1_AOI1, /* Plane 1, second AOI */ 332 PLANE2_AOI0, /* Plane 2, first AOI */ 333 PLANE2_AOI1, /* Plane 2, second AOI */ 334 }; 335 336 struct mfb_info { 337 enum mfb_index index; 338 char *id; 339 int registered; 340 unsigned long pseudo_palette[16]; 341 struct diu_ad *ad; 342 unsigned char g_alpha; 343 unsigned int count; 344 int x_aoi_d; /* aoi display x offset to physical screen */ 345 int y_aoi_d; /* aoi display y offset to physical screen */ 346 struct fsl_diu_data *parent; 347 }; 348 349 /** 350 * struct fsl_diu_data - per-DIU data structure 351 * @dma_addr: DMA address of this structure 352 * @fsl_diu_info: fb_info objects, one per AOI 353 * @dev_attr: sysfs structure 354 * @irq: IRQ 355 * @monitor_port: the monitor port this DIU is connected to 356 * @diu_reg: pointer to the DIU hardware registers 357 * @reg_lock: spinlock for register access 358 * @dummy_aoi: video buffer for the 4x4 32-bit dummy AOI 359 * dummy_ad: DIU Area Descriptor for the dummy AOI 360 * @ad[]: Area Descriptors for each real AOI 361 * @gamma: gamma color table 362 * @cursor: hardware cursor data 363 * @blank_cursor: blank cursor for hiding cursor 364 * @next_cursor: scratch space to build load cursor 365 * @edid_data: EDID information buffer 366 * @has_edid: whether or not the EDID buffer is valid 367 * 368 * This data structure must be allocated with 32-byte alignment, so that the 369 * internal fields can be aligned properly. 370 */ 371 struct fsl_diu_data { 372 dma_addr_t dma_addr; 373 struct fb_info fsl_diu_info[NUM_AOIS]; 374 struct mfb_info mfb[NUM_AOIS]; 375 struct device_attribute dev_attr; 376 unsigned int irq; 377 enum fsl_diu_monitor_port monitor_port; 378 struct diu __iomem *diu_reg; 379 spinlock_t reg_lock; 380 u8 dummy_aoi[4 * 4 * 4]; 381 struct diu_ad dummy_ad __aligned(8); 382 struct diu_ad ad[NUM_AOIS] __aligned(8); 383 u8 gamma[256 * 3] __aligned(32); 384 /* It's easier to parse the cursor data as little-endian */ 385 __le16 cursor[MAX_CURS * MAX_CURS] __aligned(32); 386 /* Blank cursor data -- used to hide the cursor */ 387 __le16 blank_cursor[MAX_CURS * MAX_CURS] __aligned(32); 388 /* Scratch cursor data -- used to build new cursor */ 389 __le16 next_cursor[MAX_CURS * MAX_CURS] __aligned(32); 390 uint8_t edid_data[EDID_LENGTH]; 391 bool has_edid; 392 } __aligned(32); 393 394 /* Determine the DMA address of a member of the fsl_diu_data structure */ 395 #define DMA_ADDR(p, f) ((p)->dma_addr + offsetof(struct fsl_diu_data, f)) 396 397 static const struct mfb_info mfb_template[] = { 398 { 399 .index = PLANE0, 400 .id = "Panel0", 401 .registered = 0, 402 .count = 0, 403 .x_aoi_d = 0, 404 .y_aoi_d = 0, 405 }, 406 { 407 .index = PLANE1_AOI0, 408 .id = "Panel1 AOI0", 409 .registered = 0, 410 .g_alpha = 0xff, 411 .count = 0, 412 .x_aoi_d = 0, 413 .y_aoi_d = 0, 414 }, 415 { 416 .index = PLANE1_AOI1, 417 .id = "Panel1 AOI1", 418 .registered = 0, 419 .g_alpha = 0xff, 420 .count = 0, 421 .x_aoi_d = 0, 422 .y_aoi_d = 480, 423 }, 424 { 425 .index = PLANE2_AOI0, 426 .id = "Panel2 AOI0", 427 .registered = 0, 428 .g_alpha = 0xff, 429 .count = 0, 430 .x_aoi_d = 640, 431 .y_aoi_d = 0, 432 }, 433 { 434 .index = PLANE2_AOI1, 435 .id = "Panel2 AOI1", 436 .registered = 0, 437 .g_alpha = 0xff, 438 .count = 0, 439 .x_aoi_d = 640, 440 .y_aoi_d = 480, 441 }, 442 }; 443 444 #ifdef DEBUG 445 static void __attribute__ ((unused)) fsl_diu_dump(struct diu __iomem *hw) 446 { 447 mb(); 448 pr_debug("DIU: desc=%08x,%08x,%08x, gamma=%08x palette=%08x " 449 "cursor=%08x curs_pos=%08x diu_mode=%08x bgnd=%08x " 450 "disp_size=%08x hsyn_para=%08x vsyn_para=%08x syn_pol=%08x " 451 "thresholds=%08x int_mask=%08x plut=%08x\n", 452 hw->desc[0], hw->desc[1], hw->desc[2], hw->gamma, 453 hw->palette, hw->cursor, hw->curs_pos, hw->diu_mode, 454 hw->bgnd, hw->disp_size, hw->hsyn_para, hw->vsyn_para, 455 hw->syn_pol, hw->thresholds, hw->int_mask, hw->plut); 456 rmb(); 457 } 458 #endif 459 460 /** 461 * fsl_diu_name_to_port - convert a port name to a monitor port enum 462 * 463 * Takes the name of a monitor port ("dvi", "lvds", or "dlvds") and returns 464 * the enum fsl_diu_monitor_port that corresponds to that string. 465 * 466 * For compatibility with older versions, a number ("0", "1", or "2") is also 467 * supported. 468 * 469 * If the string is unknown, DVI is assumed. 470 * 471 * If the particular port is not supported by the platform, another port 472 * (platform-specific) is chosen instead. 473 */ 474 static enum fsl_diu_monitor_port fsl_diu_name_to_port(const char *s) 475 { 476 enum fsl_diu_monitor_port port = FSL_DIU_PORT_DVI; 477 unsigned long val; 478 479 if (s) { 480 if (!kstrtoul(s, 10, &val) && (val <= 2)) 481 port = (enum fsl_diu_monitor_port) val; 482 else if (strncmp(s, "lvds", 4) == 0) 483 port = FSL_DIU_PORT_LVDS; 484 else if (strncmp(s, "dlvds", 5) == 0) 485 port = FSL_DIU_PORT_DLVDS; 486 } 487 488 if (diu_ops.valid_monitor_port) 489 port = diu_ops.valid_monitor_port(port); 490 491 return port; 492 } 493 494 /* 495 * Workaround for failed writing desc register of planes. 496 * Needed with MPC5121 DIU rev 2.0 silicon. 497 */ 498 void wr_reg_wa(u32 *reg, u32 val) 499 { 500 do { 501 out_be32(reg, val); 502 } while (in_be32(reg) != val); 503 } 504 505 static void fsl_diu_enable_panel(struct fb_info *info) 506 { 507 struct mfb_info *pmfbi, *cmfbi, *mfbi = info->par; 508 struct diu_ad *ad = mfbi->ad; 509 struct fsl_diu_data *data = mfbi->parent; 510 struct diu __iomem *hw = data->diu_reg; 511 512 switch (mfbi->index) { 513 case PLANE0: 514 wr_reg_wa(&hw->desc[0], ad->paddr); 515 break; 516 case PLANE1_AOI0: 517 cmfbi = &data->mfb[2]; 518 if (hw->desc[1] != ad->paddr) { /* AOI0 closed */ 519 if (cmfbi->count > 0) /* AOI1 open */ 520 ad->next_ad = 521 cpu_to_le32(cmfbi->ad->paddr); 522 else 523 ad->next_ad = 0; 524 wr_reg_wa(&hw->desc[1], ad->paddr); 525 } 526 break; 527 case PLANE2_AOI0: 528 cmfbi = &data->mfb[4]; 529 if (hw->desc[2] != ad->paddr) { /* AOI0 closed */ 530 if (cmfbi->count > 0) /* AOI1 open */ 531 ad->next_ad = 532 cpu_to_le32(cmfbi->ad->paddr); 533 else 534 ad->next_ad = 0; 535 wr_reg_wa(&hw->desc[2], ad->paddr); 536 } 537 break; 538 case PLANE1_AOI1: 539 pmfbi = &data->mfb[1]; 540 ad->next_ad = 0; 541 if (hw->desc[1] == data->dummy_ad.paddr) 542 wr_reg_wa(&hw->desc[1], ad->paddr); 543 else /* AOI0 open */ 544 pmfbi->ad->next_ad = cpu_to_le32(ad->paddr); 545 break; 546 case PLANE2_AOI1: 547 pmfbi = &data->mfb[3]; 548 ad->next_ad = 0; 549 if (hw->desc[2] == data->dummy_ad.paddr) 550 wr_reg_wa(&hw->desc[2], ad->paddr); 551 else /* AOI0 was open */ 552 pmfbi->ad->next_ad = cpu_to_le32(ad->paddr); 553 break; 554 } 555 } 556 557 static void fsl_diu_disable_panel(struct fb_info *info) 558 { 559 struct mfb_info *pmfbi, *cmfbi, *mfbi = info->par; 560 struct diu_ad *ad = mfbi->ad; 561 struct fsl_diu_data *data = mfbi->parent; 562 struct diu __iomem *hw = data->diu_reg; 563 564 switch (mfbi->index) { 565 case PLANE0: 566 wr_reg_wa(&hw->desc[0], 0); 567 break; 568 case PLANE1_AOI0: 569 cmfbi = &data->mfb[2]; 570 if (cmfbi->count > 0) /* AOI1 is open */ 571 wr_reg_wa(&hw->desc[1], cmfbi->ad->paddr); 572 /* move AOI1 to the first */ 573 else /* AOI1 was closed */ 574 wr_reg_wa(&hw->desc[1], data->dummy_ad.paddr); 575 /* close AOI 0 */ 576 break; 577 case PLANE2_AOI0: 578 cmfbi = &data->mfb[4]; 579 if (cmfbi->count > 0) /* AOI1 is open */ 580 wr_reg_wa(&hw->desc[2], cmfbi->ad->paddr); 581 /* move AOI1 to the first */ 582 else /* AOI1 was closed */ 583 wr_reg_wa(&hw->desc[2], data->dummy_ad.paddr); 584 /* close AOI 0 */ 585 break; 586 case PLANE1_AOI1: 587 pmfbi = &data->mfb[1]; 588 if (hw->desc[1] != ad->paddr) { 589 /* AOI1 is not the first in the chain */ 590 if (pmfbi->count > 0) 591 /* AOI0 is open, must be the first */ 592 pmfbi->ad->next_ad = 0; 593 } else /* AOI1 is the first in the chain */ 594 wr_reg_wa(&hw->desc[1], data->dummy_ad.paddr); 595 /* close AOI 1 */ 596 break; 597 case PLANE2_AOI1: 598 pmfbi = &data->mfb[3]; 599 if (hw->desc[2] != ad->paddr) { 600 /* AOI1 is not the first in the chain */ 601 if (pmfbi->count > 0) 602 /* AOI0 is open, must be the first */ 603 pmfbi->ad->next_ad = 0; 604 } else /* AOI1 is the first in the chain */ 605 wr_reg_wa(&hw->desc[2], data->dummy_ad.paddr); 606 /* close AOI 1 */ 607 break; 608 } 609 } 610 611 static void enable_lcdc(struct fb_info *info) 612 { 613 struct mfb_info *mfbi = info->par; 614 struct fsl_diu_data *data = mfbi->parent; 615 struct diu __iomem *hw = data->diu_reg; 616 617 out_be32(&hw->diu_mode, MFB_MODE1); 618 } 619 620 static void disable_lcdc(struct fb_info *info) 621 { 622 struct mfb_info *mfbi = info->par; 623 struct fsl_diu_data *data = mfbi->parent; 624 struct diu __iomem *hw = data->diu_reg; 625 626 out_be32(&hw->diu_mode, 0); 627 } 628 629 static void adjust_aoi_size_position(struct fb_var_screeninfo *var, 630 struct fb_info *info) 631 { 632 struct mfb_info *lower_aoi_mfbi, *upper_aoi_mfbi, *mfbi = info->par; 633 struct fsl_diu_data *data = mfbi->parent; 634 int available_height, upper_aoi_bottom; 635 enum mfb_index index = mfbi->index; 636 int lower_aoi_is_open, upper_aoi_is_open; 637 __u32 base_plane_width, base_plane_height, upper_aoi_height; 638 639 base_plane_width = data->fsl_diu_info[0].var.xres; 640 base_plane_height = data->fsl_diu_info[0].var.yres; 641 642 if (mfbi->x_aoi_d < 0) 643 mfbi->x_aoi_d = 0; 644 if (mfbi->y_aoi_d < 0) 645 mfbi->y_aoi_d = 0; 646 switch (index) { 647 case PLANE0: 648 if (mfbi->x_aoi_d != 0) 649 mfbi->x_aoi_d = 0; 650 if (mfbi->y_aoi_d != 0) 651 mfbi->y_aoi_d = 0; 652 break; 653 case PLANE1_AOI0: 654 case PLANE2_AOI0: 655 lower_aoi_mfbi = data->fsl_diu_info[index+1].par; 656 lower_aoi_is_open = lower_aoi_mfbi->count > 0 ? 1 : 0; 657 if (var->xres > base_plane_width) 658 var->xres = base_plane_width; 659 if ((mfbi->x_aoi_d + var->xres) > base_plane_width) 660 mfbi->x_aoi_d = base_plane_width - var->xres; 661 662 if (lower_aoi_is_open) 663 available_height = lower_aoi_mfbi->y_aoi_d; 664 else 665 available_height = base_plane_height; 666 if (var->yres > available_height) 667 var->yres = available_height; 668 if ((mfbi->y_aoi_d + var->yres) > available_height) 669 mfbi->y_aoi_d = available_height - var->yres; 670 break; 671 case PLANE1_AOI1: 672 case PLANE2_AOI1: 673 upper_aoi_mfbi = data->fsl_diu_info[index-1].par; 674 upper_aoi_height = data->fsl_diu_info[index-1].var.yres; 675 upper_aoi_bottom = upper_aoi_mfbi->y_aoi_d + upper_aoi_height; 676 upper_aoi_is_open = upper_aoi_mfbi->count > 0 ? 1 : 0; 677 if (var->xres > base_plane_width) 678 var->xres = base_plane_width; 679 if ((mfbi->x_aoi_d + var->xres) > base_plane_width) 680 mfbi->x_aoi_d = base_plane_width - var->xres; 681 if (mfbi->y_aoi_d < 0) 682 mfbi->y_aoi_d = 0; 683 if (upper_aoi_is_open) { 684 if (mfbi->y_aoi_d < upper_aoi_bottom) 685 mfbi->y_aoi_d = upper_aoi_bottom; 686 available_height = base_plane_height 687 - upper_aoi_bottom; 688 } else 689 available_height = base_plane_height; 690 if (var->yres > available_height) 691 var->yres = available_height; 692 if ((mfbi->y_aoi_d + var->yres) > base_plane_height) 693 mfbi->y_aoi_d = base_plane_height - var->yres; 694 break; 695 } 696 } 697 /* 698 * Checks to see if the hardware supports the state requested by var passed 699 * in. This function does not alter the hardware state! If the var passed in 700 * is slightly off by what the hardware can support then we alter the var 701 * PASSED in to what we can do. If the hardware doesn't support mode change 702 * a -EINVAL will be returned by the upper layers. 703 */ 704 static int fsl_diu_check_var(struct fb_var_screeninfo *var, 705 struct fb_info *info) 706 { 707 if (var->xres_virtual < var->xres) 708 var->xres_virtual = var->xres; 709 if (var->yres_virtual < var->yres) 710 var->yres_virtual = var->yres; 711 712 if (var->xoffset + info->var.xres > info->var.xres_virtual) 713 var->xoffset = info->var.xres_virtual - info->var.xres; 714 715 if (var->yoffset + info->var.yres > info->var.yres_virtual) 716 var->yoffset = info->var.yres_virtual - info->var.yres; 717 718 if ((var->bits_per_pixel != 32) && (var->bits_per_pixel != 24) && 719 (var->bits_per_pixel != 16)) 720 var->bits_per_pixel = default_bpp; 721 722 switch (var->bits_per_pixel) { 723 case 16: 724 var->red.length = 5; 725 var->red.offset = 11; 726 var->red.msb_right = 0; 727 728 var->green.length = 6; 729 var->green.offset = 5; 730 var->green.msb_right = 0; 731 732 var->blue.length = 5; 733 var->blue.offset = 0; 734 var->blue.msb_right = 0; 735 736 var->transp.length = 0; 737 var->transp.offset = 0; 738 var->transp.msb_right = 0; 739 break; 740 case 24: 741 var->red.length = 8; 742 var->red.offset = 0; 743 var->red.msb_right = 0; 744 745 var->green.length = 8; 746 var->green.offset = 8; 747 var->green.msb_right = 0; 748 749 var->blue.length = 8; 750 var->blue.offset = 16; 751 var->blue.msb_right = 0; 752 753 var->transp.length = 0; 754 var->transp.offset = 0; 755 var->transp.msb_right = 0; 756 break; 757 case 32: 758 var->red.length = 8; 759 var->red.offset = 16; 760 var->red.msb_right = 0; 761 762 var->green.length = 8; 763 var->green.offset = 8; 764 var->green.msb_right = 0; 765 766 var->blue.length = 8; 767 var->blue.offset = 0; 768 var->blue.msb_right = 0; 769 770 var->transp.length = 8; 771 var->transp.offset = 24; 772 var->transp.msb_right = 0; 773 774 break; 775 } 776 777 var->height = -1; 778 var->width = -1; 779 var->grayscale = 0; 780 781 /* Copy nonstd field to/from sync for fbset usage */ 782 var->sync |= var->nonstd; 783 var->nonstd |= var->sync; 784 785 adjust_aoi_size_position(var, info); 786 return 0; 787 } 788 789 static void set_fix(struct fb_info *info) 790 { 791 struct fb_fix_screeninfo *fix = &info->fix; 792 struct fb_var_screeninfo *var = &info->var; 793 struct mfb_info *mfbi = info->par; 794 795 strncpy(fix->id, mfbi->id, sizeof(fix->id)); 796 fix->line_length = var->xres_virtual * var->bits_per_pixel / 8; 797 fix->type = FB_TYPE_PACKED_PIXELS; 798 fix->accel = FB_ACCEL_NONE; 799 fix->visual = FB_VISUAL_TRUECOLOR; 800 fix->xpanstep = 1; 801 fix->ypanstep = 1; 802 } 803 804 static void update_lcdc(struct fb_info *info) 805 { 806 struct fb_var_screeninfo *var = &info->var; 807 struct mfb_info *mfbi = info->par; 808 struct fsl_diu_data *data = mfbi->parent; 809 struct diu __iomem *hw; 810 int i, j; 811 u8 *gamma_table_base; 812 813 u32 temp; 814 815 hw = data->diu_reg; 816 817 if (diu_ops.set_monitor_port) 818 diu_ops.set_monitor_port(data->monitor_port); 819 gamma_table_base = data->gamma; 820 821 /* Prep for DIU init - gamma table, cursor table */ 822 823 for (i = 0; i <= 2; i++) 824 for (j = 0; j <= 255; j++) 825 *gamma_table_base++ = j; 826 827 if (diu_ops.set_gamma_table) 828 diu_ops.set_gamma_table(data->monitor_port, data->gamma); 829 830 disable_lcdc(info); 831 832 /* Program DIU registers */ 833 834 out_be32(&hw->gamma, DMA_ADDR(data, gamma)); 835 836 out_be32(&hw->bgnd, 0x007F7F7F); /* Set background to grey */ 837 out_be32(&hw->disp_size, (var->yres << 16) | var->xres); 838 839 /* Horizontal and vertical configuration register */ 840 temp = var->left_margin << 22 | /* BP_H */ 841 var->hsync_len << 11 | /* PW_H */ 842 var->right_margin; /* FP_H */ 843 844 out_be32(&hw->hsyn_para, temp); 845 846 temp = var->upper_margin << 22 | /* BP_V */ 847 var->vsync_len << 11 | /* PW_V */ 848 var->lower_margin; /* FP_V */ 849 850 out_be32(&hw->vsyn_para, temp); 851 852 diu_ops.set_pixel_clock(var->pixclock); 853 854 #ifndef CONFIG_PPC_MPC512x 855 /* 856 * The PLUT register is defined differently on the MPC5121 than it 857 * is on other SOCs. Unfortunately, there's no documentation that 858 * explains how it's supposed to be programmed, so for now, we leave 859 * it at the default value on the MPC5121. 860 * 861 * For other SOCs, program it for the highest priority, which will 862 * reduce the chance of underrun. Technically, we should scale the 863 * priority to match the screen resolution, but doing that properly 864 * requires delicate fine-tuning for each use-case. 865 */ 866 out_be32(&hw->plut, 0x01F5F666); 867 #endif 868 869 /* Enable the DIU */ 870 enable_lcdc(info); 871 } 872 873 static int map_video_memory(struct fb_info *info) 874 { 875 u32 smem_len = info->fix.line_length * info->var.yres_virtual; 876 void *p; 877 878 p = alloc_pages_exact(smem_len, GFP_DMA | __GFP_ZERO); 879 if (!p) { 880 dev_err(info->dev, "unable to allocate fb memory\n"); 881 return -ENOMEM; 882 } 883 mutex_lock(&info->mm_lock); 884 info->screen_base = p; 885 info->fix.smem_start = virt_to_phys(info->screen_base); 886 info->fix.smem_len = smem_len; 887 mutex_unlock(&info->mm_lock); 888 info->screen_size = info->fix.smem_len; 889 890 return 0; 891 } 892 893 static void unmap_video_memory(struct fb_info *info) 894 { 895 void *p = info->screen_base; 896 size_t l = info->fix.smem_len; 897 898 mutex_lock(&info->mm_lock); 899 info->screen_base = NULL; 900 info->fix.smem_start = 0; 901 info->fix.smem_len = 0; 902 mutex_unlock(&info->mm_lock); 903 904 if (p) 905 free_pages_exact(p, l); 906 } 907 908 /* 909 * Using the fb_var_screeninfo in fb_info we set the aoi of this 910 * particular framebuffer. It is a light version of fsl_diu_set_par. 911 */ 912 static int fsl_diu_set_aoi(struct fb_info *info) 913 { 914 struct fb_var_screeninfo *var = &info->var; 915 struct mfb_info *mfbi = info->par; 916 struct diu_ad *ad = mfbi->ad; 917 918 /* AOI should not be greater than display size */ 919 ad->offset_xyi = cpu_to_le32((var->yoffset << 16) | var->xoffset); 920 ad->offset_xyd = cpu_to_le32((mfbi->y_aoi_d << 16) | mfbi->x_aoi_d); 921 return 0; 922 } 923 924 /** 925 * fsl_diu_get_pixel_format: return the pixel format for a given color depth 926 * 927 * The pixel format is a 32-bit value that determine which bits in each 928 * pixel are to be used for each color. This is the default function used 929 * if the platform does not define its own version. 930 */ 931 static u32 fsl_diu_get_pixel_format(unsigned int bits_per_pixel) 932 { 933 #define PF_BYTE_F 0x10000000 934 #define PF_ALPHA_C_MASK 0x0E000000 935 #define PF_ALPHA_C_SHIFT 25 936 #define PF_BLUE_C_MASK 0x01800000 937 #define PF_BLUE_C_SHIFT 23 938 #define PF_GREEN_C_MASK 0x00600000 939 #define PF_GREEN_C_SHIFT 21 940 #define PF_RED_C_MASK 0x00180000 941 #define PF_RED_C_SHIFT 19 942 #define PF_PALETTE 0x00040000 943 #define PF_PIXEL_S_MASK 0x00030000 944 #define PF_PIXEL_S_SHIFT 16 945 #define PF_COMP_3_MASK 0x0000F000 946 #define PF_COMP_3_SHIFT 12 947 #define PF_COMP_2_MASK 0x00000F00 948 #define PF_COMP_2_SHIFT 8 949 #define PF_COMP_1_MASK 0x000000F0 950 #define PF_COMP_1_SHIFT 4 951 #define PF_COMP_0_MASK 0x0000000F 952 #define PF_COMP_0_SHIFT 0 953 954 #define MAKE_PF(alpha, red, green, blue, size, c0, c1, c2, c3) \ 955 cpu_to_le32(PF_BYTE_F | (alpha << PF_ALPHA_C_SHIFT) | \ 956 (blue << PF_BLUE_C_SHIFT) | (green << PF_GREEN_C_SHIFT) | \ 957 (red << PF_RED_C_SHIFT) | (c3 << PF_COMP_3_SHIFT) | \ 958 (c2 << PF_COMP_2_SHIFT) | (c1 << PF_COMP_1_SHIFT) | \ 959 (c0 << PF_COMP_0_SHIFT) | (size << PF_PIXEL_S_SHIFT)) 960 961 switch (bits_per_pixel) { 962 case 32: 963 /* 0x88883316 */ 964 return MAKE_PF(3, 2, 1, 0, 3, 8, 8, 8, 8); 965 case 24: 966 /* 0x88082219 */ 967 return MAKE_PF(4, 0, 1, 2, 2, 8, 8, 8, 0); 968 case 16: 969 /* 0x65053118 */ 970 return MAKE_PF(4, 2, 1, 0, 1, 5, 6, 5, 0); 971 default: 972 pr_err("fsl-diu: unsupported color depth %u\n", bits_per_pixel); 973 return 0; 974 } 975 } 976 977 /* 978 * Copies a cursor image from user space to the proper place in driver 979 * memory so that the hardware can display the cursor image. 980 * 981 * Cursor data is represented as a sequence of 'width' bits packed into bytes. 982 * That is, the first 8 bits are in the first byte, the second 8 bits in the 983 * second byte, and so on. Therefore, the each row of the cursor is (width + 984 * 7) / 8 bytes of 'data' 985 * 986 * The DIU only supports cursors up to 32x32 (MAX_CURS). We reject cursors 987 * larger than this, so we already know that 'width' <= 32. Therefore, we can 988 * simplify our code by using a 32-bit big-endian integer ("line") to read in 989 * a single line of pixels, and only look at the top 'width' bits of that 990 * integer. 991 * 992 * This could result in an unaligned 32-bit read. For example, if the cursor 993 * is 24x24, then the first three bytes of 'image' contain the pixel data for 994 * the top line of the cursor. We do a 32-bit read of 'image', but we look 995 * only at the top 24 bits. Then we increment 'image' by 3 bytes. The next 996 * read is unaligned. The only problem is that we might read past the end of 997 * 'image' by 1-3 bytes, but that should not cause any problems. 998 */ 999 static void fsl_diu_load_cursor_image(struct fb_info *info, 1000 const void *image, uint16_t bg, uint16_t fg, 1001 unsigned int width, unsigned int height) 1002 { 1003 struct mfb_info *mfbi = info->par; 1004 struct fsl_diu_data *data = mfbi->parent; 1005 __le16 *cursor = data->cursor; 1006 __le16 _fg = cpu_to_le16(fg); 1007 __le16 _bg = cpu_to_le16(bg); 1008 unsigned int h, w; 1009 1010 for (h = 0; h < height; h++) { 1011 uint32_t mask = 1 << 31; 1012 uint32_t line = be32_to_cpup(image); 1013 1014 for (w = 0; w < width; w++) { 1015 cursor[w] = (line & mask) ? _fg : _bg; 1016 mask >>= 1; 1017 } 1018 1019 cursor += MAX_CURS; 1020 image += DIV_ROUND_UP(width, 8); 1021 } 1022 } 1023 1024 /* 1025 * Set a hardware cursor. The image data for the cursor is passed via the 1026 * fb_cursor object. 1027 */ 1028 static int fsl_diu_cursor(struct fb_info *info, struct fb_cursor *cursor) 1029 { 1030 struct mfb_info *mfbi = info->par; 1031 struct fsl_diu_data *data = mfbi->parent; 1032 struct diu __iomem *hw = data->diu_reg; 1033 1034 if (cursor->image.width > MAX_CURS || cursor->image.height > MAX_CURS) 1035 return -EINVAL; 1036 1037 /* The cursor size has changed */ 1038 if (cursor->set & FB_CUR_SETSIZE) { 1039 /* 1040 * The DIU cursor is a fixed size, so when we get this 1041 * message, instead of resizing the cursor, we just clear 1042 * all the image data, in expectation of new data. However, 1043 * in tests this control does not appear to be normally 1044 * called. 1045 */ 1046 memset(data->cursor, 0, sizeof(data->cursor)); 1047 } 1048 1049 /* The cursor position has changed (cursor->image.dx|dy) */ 1050 if (cursor->set & FB_CUR_SETPOS) { 1051 uint32_t xx, yy; 1052 1053 yy = (cursor->image.dy - info->var.yoffset) & 0x7ff; 1054 xx = (cursor->image.dx - info->var.xoffset) & 0x7ff; 1055 1056 out_be32(&hw->curs_pos, yy << 16 | xx); 1057 } 1058 1059 /* 1060 * FB_CUR_SETIMAGE - the cursor image has changed 1061 * FB_CUR_SETCMAP - the cursor colors has changed 1062 * FB_CUR_SETSHAPE - the cursor bitmask has changed 1063 */ 1064 if (cursor->set & (FB_CUR_SETSHAPE | FB_CUR_SETCMAP | FB_CUR_SETIMAGE)) { 1065 /* 1066 * Determine the size of the cursor image data. Normally, 1067 * it's 8x16. 1068 */ 1069 unsigned int image_size = 1070 DIV_ROUND_UP(cursor->image.width, 8) * 1071 cursor->image.height; 1072 unsigned int image_words = 1073 DIV_ROUND_UP(image_size, sizeof(uint32_t)); 1074 unsigned int bg_idx = cursor->image.bg_color; 1075 unsigned int fg_idx = cursor->image.fg_color; 1076 uint32_t *image, *source, *mask; 1077 uint16_t fg, bg; 1078 unsigned int i; 1079 1080 if (info->state != FBINFO_STATE_RUNNING) 1081 return 0; 1082 1083 bg = ((info->cmap.red[bg_idx] & 0xf8) << 7) | 1084 ((info->cmap.green[bg_idx] & 0xf8) << 2) | 1085 ((info->cmap.blue[bg_idx] & 0xf8) >> 3) | 1086 1 << 15; 1087 1088 fg = ((info->cmap.red[fg_idx] & 0xf8) << 7) | 1089 ((info->cmap.green[fg_idx] & 0xf8) << 2) | 1090 ((info->cmap.blue[fg_idx] & 0xf8) >> 3) | 1091 1 << 15; 1092 1093 /* Use 32-bit operations on the data to improve performance */ 1094 image = (uint32_t *)data->next_cursor; 1095 source = (uint32_t *)cursor->image.data; 1096 mask = (uint32_t *)cursor->mask; 1097 1098 if (cursor->rop == ROP_XOR) 1099 for (i = 0; i < image_words; i++) 1100 image[i] = source[i] ^ mask[i]; 1101 else 1102 for (i = 0; i < image_words; i++) 1103 image[i] = source[i] & mask[i]; 1104 1105 fsl_diu_load_cursor_image(info, image, bg, fg, 1106 cursor->image.width, cursor->image.height); 1107 } 1108 1109 /* 1110 * Show or hide the cursor. The cursor data is always stored in the 1111 * 'cursor' memory block, and the actual cursor position is always in 1112 * the DIU's CURS_POS register. To hide the cursor, we redirect the 1113 * CURSOR register to a blank cursor. The show the cursor, we 1114 * redirect the CURSOR register to the real cursor data. 1115 */ 1116 if (cursor->enable) 1117 out_be32(&hw->cursor, DMA_ADDR(data, cursor)); 1118 else 1119 out_be32(&hw->cursor, DMA_ADDR(data, blank_cursor)); 1120 1121 return 0; 1122 } 1123 1124 /* 1125 * Using the fb_var_screeninfo in fb_info we set the resolution of this 1126 * particular framebuffer. This function alters the fb_fix_screeninfo stored 1127 * in fb_info. It does not alter var in fb_info since we are using that 1128 * data. This means we depend on the data in var inside fb_info to be 1129 * supported by the hardware. fsl_diu_check_var is always called before 1130 * fsl_diu_set_par to ensure this. 1131 */ 1132 static int fsl_diu_set_par(struct fb_info *info) 1133 { 1134 unsigned long len; 1135 struct fb_var_screeninfo *var = &info->var; 1136 struct mfb_info *mfbi = info->par; 1137 struct fsl_diu_data *data = mfbi->parent; 1138 struct diu_ad *ad = mfbi->ad; 1139 struct diu __iomem *hw; 1140 1141 hw = data->diu_reg; 1142 1143 set_fix(info); 1144 1145 len = info->var.yres_virtual * info->fix.line_length; 1146 /* Alloc & dealloc each time resolution/bpp change */ 1147 if (len != info->fix.smem_len) { 1148 if (info->fix.smem_start) 1149 unmap_video_memory(info); 1150 1151 /* Memory allocation for framebuffer */ 1152 if (map_video_memory(info)) { 1153 dev_err(info->dev, "unable to allocate fb memory 1\n"); 1154 return -ENOMEM; 1155 } 1156 } 1157 1158 if (diu_ops.get_pixel_format) 1159 ad->pix_fmt = diu_ops.get_pixel_format(data->monitor_port, 1160 var->bits_per_pixel); 1161 else 1162 ad->pix_fmt = fsl_diu_get_pixel_format(var->bits_per_pixel); 1163 1164 ad->addr = cpu_to_le32(info->fix.smem_start); 1165 ad->src_size_g_alpha = cpu_to_le32((var->yres_virtual << 12) | 1166 var->xres_virtual) | mfbi->g_alpha; 1167 /* AOI should not be greater than display size */ 1168 ad->aoi_size = cpu_to_le32((var->yres << 16) | var->xres); 1169 ad->offset_xyi = cpu_to_le32((var->yoffset << 16) | var->xoffset); 1170 ad->offset_xyd = cpu_to_le32((mfbi->y_aoi_d << 16) | mfbi->x_aoi_d); 1171 1172 /* Disable chroma keying function */ 1173 ad->ckmax_r = 0; 1174 ad->ckmax_g = 0; 1175 ad->ckmax_b = 0; 1176 1177 ad->ckmin_r = 255; 1178 ad->ckmin_g = 255; 1179 ad->ckmin_b = 255; 1180 1181 if (mfbi->index == PLANE0) 1182 update_lcdc(info); 1183 return 0; 1184 } 1185 1186 static inline __u32 CNVT_TOHW(__u32 val, __u32 width) 1187 { 1188 return ((val << width) + 0x7FFF - val) >> 16; 1189 } 1190 1191 /* 1192 * Set a single color register. The values supplied have a 16 bit magnitude 1193 * which needs to be scaled in this function for the hardware. Things to take 1194 * into consideration are how many color registers, if any, are supported with 1195 * the current color visual. With truecolor mode no color palettes are 1196 * supported. Here a pseudo palette is created which we store the value in 1197 * pseudo_palette in struct fb_info. For pseudocolor mode we have a limited 1198 * color palette. 1199 */ 1200 static int fsl_diu_setcolreg(unsigned int regno, unsigned int red, 1201 unsigned int green, unsigned int blue, 1202 unsigned int transp, struct fb_info *info) 1203 { 1204 int ret = 1; 1205 1206 /* 1207 * If greyscale is true, then we convert the RGB value 1208 * to greyscale no matter what visual we are using. 1209 */ 1210 if (info->var.grayscale) 1211 red = green = blue = (19595 * red + 38470 * green + 1212 7471 * blue) >> 16; 1213 switch (info->fix.visual) { 1214 case FB_VISUAL_TRUECOLOR: 1215 /* 1216 * 16-bit True Colour. We encode the RGB value 1217 * according to the RGB bitfield information. 1218 */ 1219 if (regno < 16) { 1220 u32 *pal = info->pseudo_palette; 1221 u32 v; 1222 1223 red = CNVT_TOHW(red, info->var.red.length); 1224 green = CNVT_TOHW(green, info->var.green.length); 1225 blue = CNVT_TOHW(blue, info->var.blue.length); 1226 transp = CNVT_TOHW(transp, info->var.transp.length); 1227 1228 v = (red << info->var.red.offset) | 1229 (green << info->var.green.offset) | 1230 (blue << info->var.blue.offset) | 1231 (transp << info->var.transp.offset); 1232 1233 pal[regno] = v; 1234 ret = 0; 1235 } 1236 break; 1237 } 1238 1239 return ret; 1240 } 1241 1242 /* 1243 * Pan (or wrap, depending on the `vmode' field) the display using the 1244 * 'xoffset' and 'yoffset' fields of the 'var' structure. If the values 1245 * don't fit, return -EINVAL. 1246 */ 1247 static int fsl_diu_pan_display(struct fb_var_screeninfo *var, 1248 struct fb_info *info) 1249 { 1250 if ((info->var.xoffset == var->xoffset) && 1251 (info->var.yoffset == var->yoffset)) 1252 return 0; /* No change, do nothing */ 1253 1254 if (var->xoffset + info->var.xres > info->var.xres_virtual 1255 || var->yoffset + info->var.yres > info->var.yres_virtual) 1256 return -EINVAL; 1257 1258 info->var.xoffset = var->xoffset; 1259 info->var.yoffset = var->yoffset; 1260 1261 if (var->vmode & FB_VMODE_YWRAP) 1262 info->var.vmode |= FB_VMODE_YWRAP; 1263 else 1264 info->var.vmode &= ~FB_VMODE_YWRAP; 1265 1266 fsl_diu_set_aoi(info); 1267 1268 return 0; 1269 } 1270 1271 static int fsl_diu_ioctl(struct fb_info *info, unsigned int cmd, 1272 unsigned long arg) 1273 { 1274 struct mfb_info *mfbi = info->par; 1275 struct diu_ad *ad = mfbi->ad; 1276 struct mfb_chroma_key ck; 1277 unsigned char global_alpha; 1278 struct aoi_display_offset aoi_d; 1279 __u32 pix_fmt; 1280 void __user *buf = (void __user *)arg; 1281 1282 if (!arg) 1283 return -EINVAL; 1284 1285 dev_dbg(info->dev, "ioctl %08x (dir=%s%s type=%u nr=%u size=%u)\n", cmd, 1286 _IOC_DIR(cmd) & _IOC_READ ? "R" : "", 1287 _IOC_DIR(cmd) & _IOC_WRITE ? "W" : "", 1288 _IOC_TYPE(cmd), _IOC_NR(cmd), _IOC_SIZE(cmd)); 1289 1290 switch (cmd) { 1291 case MFB_SET_PIXFMT_OLD: 1292 dev_warn(info->dev, 1293 "MFB_SET_PIXFMT value of 0x%08x is deprecated.\n", 1294 MFB_SET_PIXFMT_OLD); 1295 case MFB_SET_PIXFMT: 1296 if (copy_from_user(&pix_fmt, buf, sizeof(pix_fmt))) 1297 return -EFAULT; 1298 ad->pix_fmt = pix_fmt; 1299 break; 1300 case MFB_GET_PIXFMT_OLD: 1301 dev_warn(info->dev, 1302 "MFB_GET_PIXFMT value of 0x%08x is deprecated.\n", 1303 MFB_GET_PIXFMT_OLD); 1304 case MFB_GET_PIXFMT: 1305 pix_fmt = ad->pix_fmt; 1306 if (copy_to_user(buf, &pix_fmt, sizeof(pix_fmt))) 1307 return -EFAULT; 1308 break; 1309 case MFB_SET_AOID: 1310 if (copy_from_user(&aoi_d, buf, sizeof(aoi_d))) 1311 return -EFAULT; 1312 mfbi->x_aoi_d = aoi_d.x_aoi_d; 1313 mfbi->y_aoi_d = aoi_d.y_aoi_d; 1314 fsl_diu_check_var(&info->var, info); 1315 fsl_diu_set_aoi(info); 1316 break; 1317 case MFB_GET_AOID: 1318 aoi_d.x_aoi_d = mfbi->x_aoi_d; 1319 aoi_d.y_aoi_d = mfbi->y_aoi_d; 1320 if (copy_to_user(buf, &aoi_d, sizeof(aoi_d))) 1321 return -EFAULT; 1322 break; 1323 case MFB_GET_ALPHA: 1324 global_alpha = mfbi->g_alpha; 1325 if (copy_to_user(buf, &global_alpha, sizeof(global_alpha))) 1326 return -EFAULT; 1327 break; 1328 case MFB_SET_ALPHA: 1329 /* set panel information */ 1330 if (copy_from_user(&global_alpha, buf, sizeof(global_alpha))) 1331 return -EFAULT; 1332 ad->src_size_g_alpha = (ad->src_size_g_alpha & (~0xff)) | 1333 (global_alpha & 0xff); 1334 mfbi->g_alpha = global_alpha; 1335 break; 1336 case MFB_SET_CHROMA_KEY: 1337 /* set panel winformation */ 1338 if (copy_from_user(&ck, buf, sizeof(ck))) 1339 return -EFAULT; 1340 1341 if (ck.enable && 1342 (ck.red_max < ck.red_min || 1343 ck.green_max < ck.green_min || 1344 ck.blue_max < ck.blue_min)) 1345 return -EINVAL; 1346 1347 if (!ck.enable) { 1348 ad->ckmax_r = 0; 1349 ad->ckmax_g = 0; 1350 ad->ckmax_b = 0; 1351 ad->ckmin_r = 255; 1352 ad->ckmin_g = 255; 1353 ad->ckmin_b = 255; 1354 } else { 1355 ad->ckmax_r = ck.red_max; 1356 ad->ckmax_g = ck.green_max; 1357 ad->ckmax_b = ck.blue_max; 1358 ad->ckmin_r = ck.red_min; 1359 ad->ckmin_g = ck.green_min; 1360 ad->ckmin_b = ck.blue_min; 1361 } 1362 break; 1363 #ifdef CONFIG_PPC_MPC512x 1364 case MFB_SET_GAMMA: { 1365 struct fsl_diu_data *data = mfbi->parent; 1366 1367 if (copy_from_user(data->gamma, buf, sizeof(data->gamma))) 1368 return -EFAULT; 1369 setbits32(&data->diu_reg->gamma, 0); /* Force table reload */ 1370 break; 1371 } 1372 case MFB_GET_GAMMA: { 1373 struct fsl_diu_data *data = mfbi->parent; 1374 1375 if (copy_to_user(buf, data->gamma, sizeof(data->gamma))) 1376 return -EFAULT; 1377 break; 1378 } 1379 #endif 1380 default: 1381 dev_err(info->dev, "unknown ioctl command (0x%08X)\n", cmd); 1382 return -ENOIOCTLCMD; 1383 } 1384 1385 return 0; 1386 } 1387 1388 static inline void fsl_diu_enable_interrupts(struct fsl_diu_data *data) 1389 { 1390 u32 int_mask = INT_UNDRUN; /* enable underrun detection */ 1391 1392 if (IS_ENABLED(CONFIG_NOT_COHERENT_CACHE)) 1393 int_mask |= INT_VSYNC; /* enable vertical sync */ 1394 1395 clrbits32(&data->diu_reg->int_mask, int_mask); 1396 } 1397 1398 /* turn on fb if count == 1 1399 */ 1400 static int fsl_diu_open(struct fb_info *info, int user) 1401 { 1402 struct mfb_info *mfbi = info->par; 1403 int res = 0; 1404 1405 /* free boot splash memory on first /dev/fb0 open */ 1406 if ((mfbi->index == PLANE0) && diu_ops.release_bootmem) 1407 diu_ops.release_bootmem(); 1408 1409 spin_lock(&diu_lock); 1410 mfbi->count++; 1411 if (mfbi->count == 1) { 1412 fsl_diu_check_var(&info->var, info); 1413 res = fsl_diu_set_par(info); 1414 if (res < 0) 1415 mfbi->count--; 1416 else { 1417 fsl_diu_enable_interrupts(mfbi->parent); 1418 fsl_diu_enable_panel(info); 1419 } 1420 } 1421 1422 spin_unlock(&diu_lock); 1423 return res; 1424 } 1425 1426 /* turn off fb if count == 0 1427 */ 1428 static int fsl_diu_release(struct fb_info *info, int user) 1429 { 1430 struct mfb_info *mfbi = info->par; 1431 int res = 0; 1432 1433 spin_lock(&diu_lock); 1434 mfbi->count--; 1435 if (mfbi->count == 0) { 1436 struct fsl_diu_data *data = mfbi->parent; 1437 bool disable = true; 1438 int i; 1439 1440 /* Disable interrupts only if all AOIs are closed */ 1441 for (i = 0; i < NUM_AOIS; i++) { 1442 struct mfb_info *mi = data->fsl_diu_info[i].par; 1443 1444 if (mi->count) 1445 disable = false; 1446 } 1447 if (disable) 1448 out_be32(&data->diu_reg->int_mask, 0xffffffff); 1449 fsl_diu_disable_panel(info); 1450 } 1451 1452 spin_unlock(&diu_lock); 1453 return res; 1454 } 1455 1456 static struct fb_ops fsl_diu_ops = { 1457 .owner = THIS_MODULE, 1458 .fb_check_var = fsl_diu_check_var, 1459 .fb_set_par = fsl_diu_set_par, 1460 .fb_setcolreg = fsl_diu_setcolreg, 1461 .fb_pan_display = fsl_diu_pan_display, 1462 .fb_fillrect = cfb_fillrect, 1463 .fb_copyarea = cfb_copyarea, 1464 .fb_imageblit = cfb_imageblit, 1465 .fb_ioctl = fsl_diu_ioctl, 1466 .fb_open = fsl_diu_open, 1467 .fb_release = fsl_diu_release, 1468 .fb_cursor = fsl_diu_cursor, 1469 }; 1470 1471 static int install_fb(struct fb_info *info) 1472 { 1473 int rc; 1474 struct mfb_info *mfbi = info->par; 1475 struct fsl_diu_data *data = mfbi->parent; 1476 const char *aoi_mode, *init_aoi_mode = "320x240"; 1477 struct fb_videomode *db = fsl_diu_mode_db; 1478 unsigned int dbsize = ARRAY_SIZE(fsl_diu_mode_db); 1479 int has_default_mode = 1; 1480 1481 info->var.activate = FB_ACTIVATE_NOW; 1482 info->fbops = &fsl_diu_ops; 1483 info->flags = FBINFO_DEFAULT | FBINFO_VIRTFB | FBINFO_PARTIAL_PAN_OK | 1484 FBINFO_READS_FAST; 1485 info->pseudo_palette = mfbi->pseudo_palette; 1486 1487 rc = fb_alloc_cmap(&info->cmap, 16, 0); 1488 if (rc) 1489 return rc; 1490 1491 if (mfbi->index == PLANE0) { 1492 if (data->has_edid) { 1493 /* Now build modedb from EDID */ 1494 fb_edid_to_monspecs(data->edid_data, &info->monspecs); 1495 fb_videomode_to_modelist(info->monspecs.modedb, 1496 info->monspecs.modedb_len, 1497 &info->modelist); 1498 db = info->monspecs.modedb; 1499 dbsize = info->monspecs.modedb_len; 1500 } 1501 aoi_mode = fb_mode; 1502 } else { 1503 aoi_mode = init_aoi_mode; 1504 } 1505 rc = fb_find_mode(&info->var, info, aoi_mode, db, dbsize, NULL, 1506 default_bpp); 1507 if (!rc) { 1508 /* 1509 * For plane 0 we continue and look into 1510 * driver's internal modedb. 1511 */ 1512 if ((mfbi->index == PLANE0) && data->has_edid) 1513 has_default_mode = 0; 1514 else 1515 return -EINVAL; 1516 } 1517 1518 if (!has_default_mode) { 1519 rc = fb_find_mode(&info->var, info, aoi_mode, fsl_diu_mode_db, 1520 ARRAY_SIZE(fsl_diu_mode_db), NULL, default_bpp); 1521 if (rc) 1522 has_default_mode = 1; 1523 } 1524 1525 /* Still not found, use preferred mode from database if any */ 1526 if (!has_default_mode && info->monspecs.modedb) { 1527 struct fb_monspecs *specs = &info->monspecs; 1528 struct fb_videomode *modedb = &specs->modedb[0]; 1529 1530 /* 1531 * Get preferred timing. If not found, 1532 * first mode in database will be used. 1533 */ 1534 if (specs->misc & FB_MISC_1ST_DETAIL) { 1535 int i; 1536 1537 for (i = 0; i < specs->modedb_len; i++) { 1538 if (specs->modedb[i].flag & FB_MODE_IS_FIRST) { 1539 modedb = &specs->modedb[i]; 1540 break; 1541 } 1542 } 1543 } 1544 1545 info->var.bits_per_pixel = default_bpp; 1546 fb_videomode_to_var(&info->var, modedb); 1547 } 1548 1549 if (fsl_diu_check_var(&info->var, info)) { 1550 dev_err(info->dev, "fsl_diu_check_var failed\n"); 1551 unmap_video_memory(info); 1552 fb_dealloc_cmap(&info->cmap); 1553 return -EINVAL; 1554 } 1555 1556 if (register_framebuffer(info) < 0) { 1557 dev_err(info->dev, "register_framebuffer failed\n"); 1558 unmap_video_memory(info); 1559 fb_dealloc_cmap(&info->cmap); 1560 return -EINVAL; 1561 } 1562 1563 mfbi->registered = 1; 1564 dev_info(info->dev, "%s registered successfully\n", mfbi->id); 1565 1566 return 0; 1567 } 1568 1569 static void uninstall_fb(struct fb_info *info) 1570 { 1571 struct mfb_info *mfbi = info->par; 1572 1573 if (!mfbi->registered) 1574 return; 1575 1576 unregister_framebuffer(info); 1577 unmap_video_memory(info); 1578 if (&info->cmap) 1579 fb_dealloc_cmap(&info->cmap); 1580 1581 mfbi->registered = 0; 1582 } 1583 1584 static irqreturn_t fsl_diu_isr(int irq, void *dev_id) 1585 { 1586 struct diu __iomem *hw = dev_id; 1587 uint32_t status = in_be32(&hw->int_status); 1588 1589 if (status) { 1590 /* This is the workaround for underrun */ 1591 if (status & INT_UNDRUN) { 1592 out_be32(&hw->diu_mode, 0); 1593 udelay(1); 1594 out_be32(&hw->diu_mode, 1); 1595 } 1596 #if defined(CONFIG_NOT_COHERENT_CACHE) 1597 else if (status & INT_VSYNC) { 1598 unsigned int i; 1599 1600 for (i = 0; i < coherence_data_size; 1601 i += d_cache_line_size) 1602 __asm__ __volatile__ ( 1603 "dcbz 0, %[input]" 1604 ::[input]"r"(&coherence_data[i])); 1605 } 1606 #endif 1607 return IRQ_HANDLED; 1608 } 1609 return IRQ_NONE; 1610 } 1611 1612 #ifdef CONFIG_PM 1613 /* 1614 * Power management hooks. Note that we won't be called from IRQ context, 1615 * unlike the blank functions above, so we may sleep. 1616 */ 1617 static int fsl_diu_suspend(struct platform_device *ofdev, pm_message_t state) 1618 { 1619 struct fsl_diu_data *data; 1620 1621 data = dev_get_drvdata(&ofdev->dev); 1622 disable_lcdc(data->fsl_diu_info); 1623 1624 return 0; 1625 } 1626 1627 static int fsl_diu_resume(struct platform_device *ofdev) 1628 { 1629 struct fsl_diu_data *data; 1630 unsigned int i; 1631 1632 data = dev_get_drvdata(&ofdev->dev); 1633 1634 fsl_diu_enable_interrupts(data); 1635 update_lcdc(data->fsl_diu_info); 1636 for (i = 0; i < NUM_AOIS; i++) { 1637 if (data->mfb[i].count) 1638 fsl_diu_enable_panel(&data->fsl_diu_info[i]); 1639 } 1640 1641 return 0; 1642 } 1643 1644 #else 1645 #define fsl_diu_suspend NULL 1646 #define fsl_diu_resume NULL 1647 #endif /* CONFIG_PM */ 1648 1649 static ssize_t store_monitor(struct device *device, 1650 struct device_attribute *attr, const char *buf, size_t count) 1651 { 1652 enum fsl_diu_monitor_port old_monitor_port; 1653 struct fsl_diu_data *data = 1654 container_of(attr, struct fsl_diu_data, dev_attr); 1655 1656 old_monitor_port = data->monitor_port; 1657 data->monitor_port = fsl_diu_name_to_port(buf); 1658 1659 if (old_monitor_port != data->monitor_port) { 1660 /* All AOIs need adjust pixel format 1661 * fsl_diu_set_par only change the pixsel format here 1662 * unlikely to fail. */ 1663 unsigned int i; 1664 1665 for (i=0; i < NUM_AOIS; i++) 1666 fsl_diu_set_par(&data->fsl_diu_info[i]); 1667 } 1668 return count; 1669 } 1670 1671 static ssize_t show_monitor(struct device *device, 1672 struct device_attribute *attr, char *buf) 1673 { 1674 struct fsl_diu_data *data = 1675 container_of(attr, struct fsl_diu_data, dev_attr); 1676 1677 switch (data->monitor_port) { 1678 case FSL_DIU_PORT_DVI: 1679 return sprintf(buf, "DVI\n"); 1680 case FSL_DIU_PORT_LVDS: 1681 return sprintf(buf, "Single-link LVDS\n"); 1682 case FSL_DIU_PORT_DLVDS: 1683 return sprintf(buf, "Dual-link LVDS\n"); 1684 } 1685 1686 return 0; 1687 } 1688 1689 static int fsl_diu_probe(struct platform_device *pdev) 1690 { 1691 struct device_node *np = pdev->dev.of_node; 1692 struct mfb_info *mfbi; 1693 struct fsl_diu_data *data; 1694 dma_addr_t dma_addr; /* DMA addr of fsl_diu_data struct */ 1695 const void *prop; 1696 unsigned int i; 1697 int ret; 1698 1699 data = dmam_alloc_coherent(&pdev->dev, sizeof(struct fsl_diu_data), 1700 &dma_addr, GFP_DMA | __GFP_ZERO); 1701 if (!data) 1702 return -ENOMEM; 1703 data->dma_addr = dma_addr; 1704 1705 /* 1706 * dma_alloc_coherent() uses a page allocator, so the address is 1707 * always page-aligned. We need the memory to be 32-byte aligned, 1708 * so that's good. However, if one day the allocator changes, we 1709 * need to catch that. It's not worth the effort to handle unaligned 1710 * alloctions now because it's highly unlikely to ever be a problem. 1711 */ 1712 if ((unsigned long)data & 31) { 1713 dev_err(&pdev->dev, "misaligned allocation"); 1714 ret = -ENOMEM; 1715 goto error; 1716 } 1717 1718 spin_lock_init(&data->reg_lock); 1719 1720 for (i = 0; i < NUM_AOIS; i++) { 1721 struct fb_info *info = &data->fsl_diu_info[i]; 1722 1723 info->device = &pdev->dev; 1724 info->par = &data->mfb[i]; 1725 1726 /* 1727 * We store the physical address of the AD in the reserved 1728 * 'paddr' field of the AD itself. 1729 */ 1730 data->ad[i].paddr = DMA_ADDR(data, ad[i]); 1731 1732 info->fix.smem_start = 0; 1733 1734 /* Initialize the AOI data structure */ 1735 mfbi = info->par; 1736 memcpy(mfbi, &mfb_template[i], sizeof(struct mfb_info)); 1737 mfbi->parent = data; 1738 mfbi->ad = &data->ad[i]; 1739 } 1740 1741 /* Get the EDID data from the device tree, if present */ 1742 prop = of_get_property(np, "edid", &ret); 1743 if (prop && ret == EDID_LENGTH) { 1744 memcpy(data->edid_data, prop, EDID_LENGTH); 1745 data->has_edid = true; 1746 } 1747 1748 data->diu_reg = of_iomap(np, 0); 1749 if (!data->diu_reg) { 1750 dev_err(&pdev->dev, "cannot map DIU registers\n"); 1751 ret = -EFAULT; 1752 goto error; 1753 } 1754 1755 /* Get the IRQ of the DIU */ 1756 data->irq = irq_of_parse_and_map(np, 0); 1757 1758 if (!data->irq) { 1759 dev_err(&pdev->dev, "could not get DIU IRQ\n"); 1760 ret = -EINVAL; 1761 goto error; 1762 } 1763 data->monitor_port = monitor_port; 1764 1765 /* Initialize the dummy Area Descriptor */ 1766 data->dummy_ad.addr = cpu_to_le32(DMA_ADDR(data, dummy_aoi)); 1767 data->dummy_ad.pix_fmt = 0x88882317; 1768 data->dummy_ad.src_size_g_alpha = cpu_to_le32((4 << 12) | 4); 1769 data->dummy_ad.aoi_size = cpu_to_le32((4 << 16) | 2); 1770 data->dummy_ad.offset_xyi = 0; 1771 data->dummy_ad.offset_xyd = 0; 1772 data->dummy_ad.next_ad = 0; 1773 data->dummy_ad.paddr = DMA_ADDR(data, dummy_ad); 1774 1775 /* 1776 * Let DIU continue to display splash screen if it was pre-initialized 1777 * by the bootloader; otherwise, clear the display. 1778 */ 1779 if (in_be32(&data->diu_reg->diu_mode) == MFB_MODE0) 1780 out_be32(&data->diu_reg->desc[0], 0); 1781 1782 out_be32(&data->diu_reg->desc[1], data->dummy_ad.paddr); 1783 out_be32(&data->diu_reg->desc[2], data->dummy_ad.paddr); 1784 1785 /* 1786 * Older versions of U-Boot leave interrupts enabled, so disable 1787 * all of them and clear the status register. 1788 */ 1789 out_be32(&data->diu_reg->int_mask, 0xffffffff); 1790 in_be32(&data->diu_reg->int_status); 1791 1792 ret = request_irq(data->irq, fsl_diu_isr, 0, "fsl-diu-fb", 1793 data->diu_reg); 1794 if (ret) { 1795 dev_err(&pdev->dev, "could not claim irq\n"); 1796 goto error; 1797 } 1798 1799 for (i = 0; i < NUM_AOIS; i++) { 1800 ret = install_fb(&data->fsl_diu_info[i]); 1801 if (ret) { 1802 dev_err(&pdev->dev, "could not register fb %d\n", i); 1803 free_irq(data->irq, data->diu_reg); 1804 goto error; 1805 } 1806 } 1807 1808 sysfs_attr_init(&data->dev_attr.attr); 1809 data->dev_attr.attr.name = "monitor"; 1810 data->dev_attr.attr.mode = S_IRUGO|S_IWUSR; 1811 data->dev_attr.show = show_monitor; 1812 data->dev_attr.store = store_monitor; 1813 ret = device_create_file(&pdev->dev, &data->dev_attr); 1814 if (ret) { 1815 dev_err(&pdev->dev, "could not create sysfs file %s\n", 1816 data->dev_attr.attr.name); 1817 } 1818 1819 dev_set_drvdata(&pdev->dev, data); 1820 return 0; 1821 1822 error: 1823 for (i = 0; i < NUM_AOIS; i++) 1824 uninstall_fb(&data->fsl_diu_info[i]); 1825 1826 iounmap(data->diu_reg); 1827 1828 return ret; 1829 } 1830 1831 static int fsl_diu_remove(struct platform_device *pdev) 1832 { 1833 struct fsl_diu_data *data; 1834 int i; 1835 1836 data = dev_get_drvdata(&pdev->dev); 1837 disable_lcdc(&data->fsl_diu_info[0]); 1838 1839 free_irq(data->irq, data->diu_reg); 1840 1841 for (i = 0; i < NUM_AOIS; i++) 1842 uninstall_fb(&data->fsl_diu_info[i]); 1843 1844 iounmap(data->diu_reg); 1845 1846 return 0; 1847 } 1848 1849 #ifndef MODULE 1850 static int __init fsl_diu_setup(char *options) 1851 { 1852 char *opt; 1853 unsigned long val; 1854 1855 if (!options || !*options) 1856 return 0; 1857 1858 while ((opt = strsep(&options, ",")) != NULL) { 1859 if (!*opt) 1860 continue; 1861 if (!strncmp(opt, "monitor=", 8)) { 1862 monitor_port = fsl_diu_name_to_port(opt + 8); 1863 } else if (!strncmp(opt, "bpp=", 4)) { 1864 if (!kstrtoul(opt + 4, 10, &val)) 1865 default_bpp = val; 1866 } else 1867 fb_mode = opt; 1868 } 1869 1870 return 0; 1871 } 1872 #endif 1873 1874 static const struct of_device_id fsl_diu_match[] = { 1875 #ifdef CONFIG_PPC_MPC512x 1876 { 1877 .compatible = "fsl,mpc5121-diu", 1878 }, 1879 #endif 1880 { 1881 .compatible = "fsl,diu", 1882 }, 1883 {} 1884 }; 1885 MODULE_DEVICE_TABLE(of, fsl_diu_match); 1886 1887 static struct platform_driver fsl_diu_driver = { 1888 .driver = { 1889 .name = "fsl-diu-fb", 1890 .of_match_table = fsl_diu_match, 1891 }, 1892 .probe = fsl_diu_probe, 1893 .remove = fsl_diu_remove, 1894 .suspend = fsl_diu_suspend, 1895 .resume = fsl_diu_resume, 1896 }; 1897 1898 static int __init fsl_diu_init(void) 1899 { 1900 #ifdef CONFIG_NOT_COHERENT_CACHE 1901 struct device_node *np; 1902 const u32 *prop; 1903 #endif 1904 int ret; 1905 #ifndef MODULE 1906 char *option; 1907 1908 /* 1909 * For kernel boot options (in 'video=xxxfb:<options>' format) 1910 */ 1911 if (fb_get_options("fslfb", &option)) 1912 return -ENODEV; 1913 fsl_diu_setup(option); 1914 #else 1915 monitor_port = fsl_diu_name_to_port(monitor_string); 1916 #endif 1917 1918 /* 1919 * Must to verify set_pixel_clock. If not implement on platform, 1920 * then that means that there is no platform support for the DIU. 1921 */ 1922 if (!diu_ops.set_pixel_clock) 1923 return -ENODEV; 1924 1925 pr_info("Freescale Display Interface Unit (DIU) framebuffer driver\n"); 1926 1927 #ifdef CONFIG_NOT_COHERENT_CACHE 1928 np = of_get_cpu_node(0, NULL); 1929 if (!np) { 1930 pr_err("fsl-diu-fb: can't find 'cpu' device node\n"); 1931 return -ENODEV; 1932 } 1933 1934 prop = of_get_property(np, "d-cache-size", NULL); 1935 if (prop == NULL) { 1936 pr_err("fsl-diu-fb: missing 'd-cache-size' property' " 1937 "in 'cpu' node\n"); 1938 of_node_put(np); 1939 return -ENODEV; 1940 } 1941 1942 /* 1943 * Freescale PLRU requires 13/8 times the cache size to do a proper 1944 * displacement flush 1945 */ 1946 coherence_data_size = be32_to_cpup(prop) * 13; 1947 coherence_data_size /= 8; 1948 1949 pr_debug("fsl-diu-fb: coherence data size is %zu bytes\n", 1950 coherence_data_size); 1951 1952 prop = of_get_property(np, "d-cache-line-size", NULL); 1953 if (prop == NULL) { 1954 pr_err("fsl-diu-fb: missing 'd-cache-line-size' property' " 1955 "in 'cpu' node\n"); 1956 of_node_put(np); 1957 return -ENODEV; 1958 } 1959 d_cache_line_size = be32_to_cpup(prop); 1960 1961 pr_debug("fsl-diu-fb: cache lines size is %u bytes\n", 1962 d_cache_line_size); 1963 1964 of_node_put(np); 1965 coherence_data = vmalloc(coherence_data_size); 1966 if (!coherence_data) 1967 return -ENOMEM; 1968 #endif 1969 1970 ret = platform_driver_register(&fsl_diu_driver); 1971 if (ret) { 1972 pr_err("fsl-diu-fb: failed to register platform driver\n"); 1973 #if defined(CONFIG_NOT_COHERENT_CACHE) 1974 vfree(coherence_data); 1975 #endif 1976 } 1977 return ret; 1978 } 1979 1980 static void __exit fsl_diu_exit(void) 1981 { 1982 platform_driver_unregister(&fsl_diu_driver); 1983 #if defined(CONFIG_NOT_COHERENT_CACHE) 1984 vfree(coherence_data); 1985 #endif 1986 } 1987 1988 module_init(fsl_diu_init); 1989 module_exit(fsl_diu_exit); 1990 1991 MODULE_AUTHOR("York Sun <yorksun@freescale.com>"); 1992 MODULE_DESCRIPTION("Freescale DIU framebuffer driver"); 1993 MODULE_LICENSE("GPL"); 1994 1995 module_param_named(mode, fb_mode, charp, 0); 1996 MODULE_PARM_DESC(mode, 1997 "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" "); 1998 module_param_named(bpp, default_bpp, ulong, 0); 1999 MODULE_PARM_DESC(bpp, "Specify bit-per-pixel if not specified in 'mode'"); 2000 module_param_named(monitor, monitor_string, charp, 0); 2001 MODULE_PARM_DESC(monitor, "Specify the monitor port " 2002 "(\"dvi\", \"lvds\", or \"dlvds\") if supported by the platform"); 2003 2004