1 /* 2 * Copyright (C) 2008-2009 MontaVista Software Inc. 3 * Copyright (C) 2008-2009 Texas Instruments Inc 4 * 5 * Based on the LCD driver for TI Avalanche processors written by 6 * Ajay Singh and Shalom Hai. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option)any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 21 */ 22 #include <linux/module.h> 23 #include <linux/kernel.h> 24 #include <linux/fb.h> 25 #include <linux/dma-mapping.h> 26 #include <linux/device.h> 27 #include <linux/platform_device.h> 28 #include <linux/uaccess.h> 29 #include <linux/pm_runtime.h> 30 #include <linux/interrupt.h> 31 #include <linux/wait.h> 32 #include <linux/clk.h> 33 #include <linux/cpufreq.h> 34 #include <linux/console.h> 35 #include <linux/spinlock.h> 36 #include <linux/slab.h> 37 #include <linux/delay.h> 38 #include <linux/lcm.h> 39 #include <video/da8xx-fb.h> 40 #include <asm/div64.h> 41 42 #define DRIVER_NAME "da8xx_lcdc" 43 44 #define LCD_VERSION_1 1 45 #define LCD_VERSION_2 2 46 47 /* LCD Status Register */ 48 #define LCD_END_OF_FRAME1 BIT(9) 49 #define LCD_END_OF_FRAME0 BIT(8) 50 #define LCD_PL_LOAD_DONE BIT(6) 51 #define LCD_FIFO_UNDERFLOW BIT(5) 52 #define LCD_SYNC_LOST BIT(2) 53 #define LCD_FRAME_DONE BIT(0) 54 55 /* LCD DMA Control Register */ 56 #define LCD_DMA_BURST_SIZE(x) ((x) << 4) 57 #define LCD_DMA_BURST_1 0x0 58 #define LCD_DMA_BURST_2 0x1 59 #define LCD_DMA_BURST_4 0x2 60 #define LCD_DMA_BURST_8 0x3 61 #define LCD_DMA_BURST_16 0x4 62 #define LCD_V1_END_OF_FRAME_INT_ENA BIT(2) 63 #define LCD_V2_END_OF_FRAME0_INT_ENA BIT(8) 64 #define LCD_V2_END_OF_FRAME1_INT_ENA BIT(9) 65 #define LCD_DUAL_FRAME_BUFFER_ENABLE BIT(0) 66 67 /* LCD Control Register */ 68 #define LCD_CLK_DIVISOR(x) ((x) << 8) 69 #define LCD_RASTER_MODE 0x01 70 71 /* LCD Raster Control Register */ 72 #define LCD_PALETTE_LOAD_MODE(x) ((x) << 20) 73 #define PALETTE_AND_DATA 0x00 74 #define PALETTE_ONLY 0x01 75 #define DATA_ONLY 0x02 76 77 #define LCD_MONO_8BIT_MODE BIT(9) 78 #define LCD_RASTER_ORDER BIT(8) 79 #define LCD_TFT_MODE BIT(7) 80 #define LCD_V1_UNDERFLOW_INT_ENA BIT(6) 81 #define LCD_V2_UNDERFLOW_INT_ENA BIT(5) 82 #define LCD_V1_PL_INT_ENA BIT(4) 83 #define LCD_V2_PL_INT_ENA BIT(6) 84 #define LCD_MONOCHROME_MODE BIT(1) 85 #define LCD_RASTER_ENABLE BIT(0) 86 #define LCD_TFT_ALT_ENABLE BIT(23) 87 #define LCD_STN_565_ENABLE BIT(24) 88 #define LCD_V2_DMA_CLK_EN BIT(2) 89 #define LCD_V2_LIDD_CLK_EN BIT(1) 90 #define LCD_V2_CORE_CLK_EN BIT(0) 91 #define LCD_V2_LPP_B10 26 92 #define LCD_V2_TFT_24BPP_MODE BIT(25) 93 #define LCD_V2_TFT_24BPP_UNPACK BIT(26) 94 95 /* LCD Raster Timing 2 Register */ 96 #define LCD_AC_BIAS_TRANSITIONS_PER_INT(x) ((x) << 16) 97 #define LCD_AC_BIAS_FREQUENCY(x) ((x) << 8) 98 #define LCD_SYNC_CTRL BIT(25) 99 #define LCD_SYNC_EDGE BIT(24) 100 #define LCD_INVERT_PIXEL_CLOCK BIT(22) 101 #define LCD_INVERT_LINE_CLOCK BIT(21) 102 #define LCD_INVERT_FRAME_CLOCK BIT(20) 103 104 /* LCD Block */ 105 #define LCD_PID_REG 0x0 106 #define LCD_CTRL_REG 0x4 107 #define LCD_STAT_REG 0x8 108 #define LCD_RASTER_CTRL_REG 0x28 109 #define LCD_RASTER_TIMING_0_REG 0x2C 110 #define LCD_RASTER_TIMING_1_REG 0x30 111 #define LCD_RASTER_TIMING_2_REG 0x34 112 #define LCD_DMA_CTRL_REG 0x40 113 #define LCD_DMA_FRM_BUF_BASE_ADDR_0_REG 0x44 114 #define LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG 0x48 115 #define LCD_DMA_FRM_BUF_BASE_ADDR_1_REG 0x4C 116 #define LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG 0x50 117 118 /* Interrupt Registers available only in Version 2 */ 119 #define LCD_RAW_STAT_REG 0x58 120 #define LCD_MASKED_STAT_REG 0x5c 121 #define LCD_INT_ENABLE_SET_REG 0x60 122 #define LCD_INT_ENABLE_CLR_REG 0x64 123 #define LCD_END_OF_INT_IND_REG 0x68 124 125 /* Clock registers available only on Version 2 */ 126 #define LCD_CLK_ENABLE_REG 0x6c 127 #define LCD_CLK_RESET_REG 0x70 128 #define LCD_CLK_MAIN_RESET BIT(3) 129 130 #define LCD_NUM_BUFFERS 2 131 132 #define PALETTE_SIZE 256 133 134 #define CLK_MIN_DIV 2 135 #define CLK_MAX_DIV 255 136 137 static void __iomem *da8xx_fb_reg_base; 138 static unsigned int lcd_revision; 139 static irq_handler_t lcdc_irq_handler; 140 static wait_queue_head_t frame_done_wq; 141 static int frame_done_flag; 142 143 static unsigned int lcdc_read(unsigned int addr) 144 { 145 return (unsigned int)__raw_readl(da8xx_fb_reg_base + (addr)); 146 } 147 148 static void lcdc_write(unsigned int val, unsigned int addr) 149 { 150 __raw_writel(val, da8xx_fb_reg_base + (addr)); 151 } 152 153 struct da8xx_fb_par { 154 struct device *dev; 155 resource_size_t p_palette_base; 156 unsigned char *v_palette_base; 157 dma_addr_t vram_phys; 158 unsigned long vram_size; 159 void *vram_virt; 160 unsigned int dma_start; 161 unsigned int dma_end; 162 struct clk *lcdc_clk; 163 int irq; 164 unsigned int palette_sz; 165 int blank; 166 wait_queue_head_t vsync_wait; 167 int vsync_flag; 168 int vsync_timeout; 169 spinlock_t lock_for_chan_update; 170 171 /* 172 * LCDC has 2 ping pong DMA channels, channel 0 173 * and channel 1. 174 */ 175 unsigned int which_dma_channel_done; 176 #ifdef CONFIG_CPU_FREQ 177 struct notifier_block freq_transition; 178 #endif 179 unsigned int lcdc_clk_rate; 180 void (*panel_power_ctrl)(int); 181 u32 pseudo_palette[16]; 182 struct fb_videomode mode; 183 struct lcd_ctrl_config cfg; 184 }; 185 186 static struct fb_var_screeninfo da8xx_fb_var; 187 188 static struct fb_fix_screeninfo da8xx_fb_fix = { 189 .id = "DA8xx FB Drv", 190 .type = FB_TYPE_PACKED_PIXELS, 191 .type_aux = 0, 192 .visual = FB_VISUAL_PSEUDOCOLOR, 193 .xpanstep = 0, 194 .ypanstep = 1, 195 .ywrapstep = 0, 196 .accel = FB_ACCEL_NONE 197 }; 198 199 static struct fb_videomode known_lcd_panels[] = { 200 /* Sharp LCD035Q3DG01 */ 201 [0] = { 202 .name = "Sharp_LCD035Q3DG01", 203 .xres = 320, 204 .yres = 240, 205 .pixclock = KHZ2PICOS(4607), 206 .left_margin = 6, 207 .right_margin = 8, 208 .upper_margin = 2, 209 .lower_margin = 2, 210 .hsync_len = 0, 211 .vsync_len = 0, 212 .sync = FB_SYNC_CLK_INVERT | 213 FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, 214 }, 215 /* Sharp LK043T1DG01 */ 216 [1] = { 217 .name = "Sharp_LK043T1DG01", 218 .xres = 480, 219 .yres = 272, 220 .pixclock = KHZ2PICOS(7833), 221 .left_margin = 2, 222 .right_margin = 2, 223 .upper_margin = 2, 224 .lower_margin = 2, 225 .hsync_len = 41, 226 .vsync_len = 10, 227 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, 228 .flag = 0, 229 }, 230 [2] = { 231 /* Hitachi SP10Q010 */ 232 .name = "SP10Q010", 233 .xres = 320, 234 .yres = 240, 235 .pixclock = KHZ2PICOS(7833), 236 .left_margin = 10, 237 .right_margin = 10, 238 .upper_margin = 10, 239 .lower_margin = 10, 240 .hsync_len = 10, 241 .vsync_len = 10, 242 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, 243 .flag = 0, 244 }, 245 [3] = { 246 /* Densitron 84-0023-001T */ 247 .name = "Densitron_84-0023-001T", 248 .xres = 320, 249 .yres = 240, 250 .pixclock = KHZ2PICOS(6400), 251 .left_margin = 0, 252 .right_margin = 0, 253 .upper_margin = 0, 254 .lower_margin = 0, 255 .hsync_len = 30, 256 .vsync_len = 3, 257 .sync = 0, 258 }, 259 }; 260 261 static bool da8xx_fb_is_raster_enabled(void) 262 { 263 return !!(lcdc_read(LCD_RASTER_CTRL_REG) & LCD_RASTER_ENABLE); 264 } 265 266 /* Enable the Raster Engine of the LCD Controller */ 267 static void lcd_enable_raster(void) 268 { 269 u32 reg; 270 271 /* Put LCDC in reset for several cycles */ 272 if (lcd_revision == LCD_VERSION_2) 273 /* Write 1 to reset LCDC */ 274 lcdc_write(LCD_CLK_MAIN_RESET, LCD_CLK_RESET_REG); 275 mdelay(1); 276 277 /* Bring LCDC out of reset */ 278 if (lcd_revision == LCD_VERSION_2) 279 lcdc_write(0, LCD_CLK_RESET_REG); 280 mdelay(1); 281 282 /* Above reset sequence doesnot reset register context */ 283 reg = lcdc_read(LCD_RASTER_CTRL_REG); 284 if (!(reg & LCD_RASTER_ENABLE)) 285 lcdc_write(reg | LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG); 286 } 287 288 /* Disable the Raster Engine of the LCD Controller */ 289 static void lcd_disable_raster(enum da8xx_frame_complete wait_for_frame_done) 290 { 291 u32 reg; 292 int ret; 293 294 reg = lcdc_read(LCD_RASTER_CTRL_REG); 295 if (reg & LCD_RASTER_ENABLE) 296 lcdc_write(reg & ~LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG); 297 else 298 /* return if already disabled */ 299 return; 300 301 if ((wait_for_frame_done == DA8XX_FRAME_WAIT) && 302 (lcd_revision == LCD_VERSION_2)) { 303 frame_done_flag = 0; 304 ret = wait_event_interruptible_timeout(frame_done_wq, 305 frame_done_flag != 0, 306 msecs_to_jiffies(50)); 307 if (ret == 0) 308 pr_err("LCD Controller timed out\n"); 309 } 310 } 311 312 static void lcd_blit(int load_mode, struct da8xx_fb_par *par) 313 { 314 u32 start; 315 u32 end; 316 u32 reg_ras; 317 u32 reg_dma; 318 u32 reg_int; 319 320 /* init reg to clear PLM (loading mode) fields */ 321 reg_ras = lcdc_read(LCD_RASTER_CTRL_REG); 322 reg_ras &= ~(3 << 20); 323 324 reg_dma = lcdc_read(LCD_DMA_CTRL_REG); 325 326 if (load_mode == LOAD_DATA) { 327 start = par->dma_start; 328 end = par->dma_end; 329 330 reg_ras |= LCD_PALETTE_LOAD_MODE(DATA_ONLY); 331 if (lcd_revision == LCD_VERSION_1) { 332 reg_dma |= LCD_V1_END_OF_FRAME_INT_ENA; 333 } else { 334 reg_int = lcdc_read(LCD_INT_ENABLE_SET_REG) | 335 LCD_V2_END_OF_FRAME0_INT_ENA | 336 LCD_V2_END_OF_FRAME1_INT_ENA | 337 LCD_FRAME_DONE | LCD_SYNC_LOST; 338 lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG); 339 } 340 reg_dma |= LCD_DUAL_FRAME_BUFFER_ENABLE; 341 342 lcdc_write(start, LCD_DMA_FRM_BUF_BASE_ADDR_0_REG); 343 lcdc_write(end, LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG); 344 lcdc_write(start, LCD_DMA_FRM_BUF_BASE_ADDR_1_REG); 345 lcdc_write(end, LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG); 346 } else if (load_mode == LOAD_PALETTE) { 347 start = par->p_palette_base; 348 end = start + par->palette_sz - 1; 349 350 reg_ras |= LCD_PALETTE_LOAD_MODE(PALETTE_ONLY); 351 352 if (lcd_revision == LCD_VERSION_1) { 353 reg_ras |= LCD_V1_PL_INT_ENA; 354 } else { 355 reg_int = lcdc_read(LCD_INT_ENABLE_SET_REG) | 356 LCD_V2_PL_INT_ENA; 357 lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG); 358 } 359 360 lcdc_write(start, LCD_DMA_FRM_BUF_BASE_ADDR_0_REG); 361 lcdc_write(end, LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG); 362 } 363 364 lcdc_write(reg_dma, LCD_DMA_CTRL_REG); 365 lcdc_write(reg_ras, LCD_RASTER_CTRL_REG); 366 367 /* 368 * The Raster enable bit must be set after all other control fields are 369 * set. 370 */ 371 lcd_enable_raster(); 372 } 373 374 /* Configure the Burst Size and fifo threhold of DMA */ 375 static int lcd_cfg_dma(int burst_size, int fifo_th) 376 { 377 u32 reg; 378 379 reg = lcdc_read(LCD_DMA_CTRL_REG) & 0x00000001; 380 switch (burst_size) { 381 case 1: 382 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_1); 383 break; 384 case 2: 385 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_2); 386 break; 387 case 4: 388 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_4); 389 break; 390 case 8: 391 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_8); 392 break; 393 case 16: 394 default: 395 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_16); 396 break; 397 } 398 399 reg |= (fifo_th << 8); 400 401 lcdc_write(reg, LCD_DMA_CTRL_REG); 402 403 return 0; 404 } 405 406 static void lcd_cfg_ac_bias(int period, int transitions_per_int) 407 { 408 u32 reg; 409 410 /* Set the AC Bias Period and Number of Transisitons per Interrupt */ 411 reg = lcdc_read(LCD_RASTER_TIMING_2_REG) & 0xFFF00000; 412 reg |= LCD_AC_BIAS_FREQUENCY(period) | 413 LCD_AC_BIAS_TRANSITIONS_PER_INT(transitions_per_int); 414 lcdc_write(reg, LCD_RASTER_TIMING_2_REG); 415 } 416 417 static void lcd_cfg_horizontal_sync(int back_porch, int pulse_width, 418 int front_porch) 419 { 420 u32 reg; 421 422 reg = lcdc_read(LCD_RASTER_TIMING_0_REG) & 0xf; 423 reg |= (((back_porch-1) & 0xff) << 24) 424 | (((front_porch-1) & 0xff) << 16) 425 | (((pulse_width-1) & 0x3f) << 10); 426 lcdc_write(reg, LCD_RASTER_TIMING_0_REG); 427 428 /* 429 * LCDC Version 2 adds some extra bits that increase the allowable 430 * size of the horizontal timing registers. 431 * remember that the registers use 0 to represent 1 so all values 432 * that get set into register need to be decremented by 1 433 */ 434 if (lcd_revision == LCD_VERSION_2) { 435 /* Mask off the bits we want to change */ 436 reg = lcdc_read(LCD_RASTER_TIMING_2_REG) & ~0x780000ff; 437 reg |= ((front_porch-1) & 0x300) >> 8; 438 reg |= ((back_porch-1) & 0x300) >> 4; 439 reg |= ((pulse_width-1) & 0x3c0) << 21; 440 lcdc_write(reg, LCD_RASTER_TIMING_2_REG); 441 } 442 } 443 444 static void lcd_cfg_vertical_sync(int back_porch, int pulse_width, 445 int front_porch) 446 { 447 u32 reg; 448 449 reg = lcdc_read(LCD_RASTER_TIMING_1_REG) & 0x3ff; 450 reg |= ((back_porch & 0xff) << 24) 451 | ((front_porch & 0xff) << 16) 452 | (((pulse_width-1) & 0x3f) << 10); 453 lcdc_write(reg, LCD_RASTER_TIMING_1_REG); 454 } 455 456 static int lcd_cfg_display(const struct lcd_ctrl_config *cfg, 457 struct fb_videomode *panel) 458 { 459 u32 reg; 460 u32 reg_int; 461 462 reg = lcdc_read(LCD_RASTER_CTRL_REG) & ~(LCD_TFT_MODE | 463 LCD_MONO_8BIT_MODE | 464 LCD_MONOCHROME_MODE); 465 466 switch (cfg->panel_shade) { 467 case MONOCHROME: 468 reg |= LCD_MONOCHROME_MODE; 469 if (cfg->mono_8bit_mode) 470 reg |= LCD_MONO_8BIT_MODE; 471 break; 472 case COLOR_ACTIVE: 473 reg |= LCD_TFT_MODE; 474 if (cfg->tft_alt_mode) 475 reg |= LCD_TFT_ALT_ENABLE; 476 break; 477 478 case COLOR_PASSIVE: 479 /* AC bias applicable only for Pasive panels */ 480 lcd_cfg_ac_bias(cfg->ac_bias, cfg->ac_bias_intrpt); 481 if (cfg->bpp == 12 && cfg->stn_565_mode) 482 reg |= LCD_STN_565_ENABLE; 483 break; 484 485 default: 486 return -EINVAL; 487 } 488 489 /* enable additional interrupts here */ 490 if (lcd_revision == LCD_VERSION_1) { 491 reg |= LCD_V1_UNDERFLOW_INT_ENA; 492 } else { 493 reg_int = lcdc_read(LCD_INT_ENABLE_SET_REG) | 494 LCD_V2_UNDERFLOW_INT_ENA; 495 lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG); 496 } 497 498 lcdc_write(reg, LCD_RASTER_CTRL_REG); 499 500 reg = lcdc_read(LCD_RASTER_TIMING_2_REG); 501 502 reg |= LCD_SYNC_CTRL; 503 504 if (cfg->sync_edge) 505 reg |= LCD_SYNC_EDGE; 506 else 507 reg &= ~LCD_SYNC_EDGE; 508 509 if ((panel->sync & FB_SYNC_HOR_HIGH_ACT) == 0) 510 reg |= LCD_INVERT_LINE_CLOCK; 511 else 512 reg &= ~LCD_INVERT_LINE_CLOCK; 513 514 if ((panel->sync & FB_SYNC_VERT_HIGH_ACT) == 0) 515 reg |= LCD_INVERT_FRAME_CLOCK; 516 else 517 reg &= ~LCD_INVERT_FRAME_CLOCK; 518 519 lcdc_write(reg, LCD_RASTER_TIMING_2_REG); 520 521 return 0; 522 } 523 524 static int lcd_cfg_frame_buffer(struct da8xx_fb_par *par, u32 width, u32 height, 525 u32 bpp, u32 raster_order) 526 { 527 u32 reg; 528 529 if (bpp > 16 && lcd_revision == LCD_VERSION_1) 530 return -EINVAL; 531 532 /* Set the Panel Width */ 533 /* Pixels per line = (PPL + 1)*16 */ 534 if (lcd_revision == LCD_VERSION_1) { 535 /* 536 * 0x3F in bits 4..9 gives max horizontal resolution = 1024 537 * pixels. 538 */ 539 width &= 0x3f0; 540 } else { 541 /* 542 * 0x7F in bits 4..10 gives max horizontal resolution = 2048 543 * pixels. 544 */ 545 width &= 0x7f0; 546 } 547 548 reg = lcdc_read(LCD_RASTER_TIMING_0_REG); 549 reg &= 0xfffffc00; 550 if (lcd_revision == LCD_VERSION_1) { 551 reg |= ((width >> 4) - 1) << 4; 552 } else { 553 width = (width >> 4) - 1; 554 reg |= ((width & 0x3f) << 4) | ((width & 0x40) >> 3); 555 } 556 lcdc_write(reg, LCD_RASTER_TIMING_0_REG); 557 558 /* Set the Panel Height */ 559 /* Set bits 9:0 of Lines Per Pixel */ 560 reg = lcdc_read(LCD_RASTER_TIMING_1_REG); 561 reg = ((height - 1) & 0x3ff) | (reg & 0xfffffc00); 562 lcdc_write(reg, LCD_RASTER_TIMING_1_REG); 563 564 /* Set bit 10 of Lines Per Pixel */ 565 if (lcd_revision == LCD_VERSION_2) { 566 reg = lcdc_read(LCD_RASTER_TIMING_2_REG); 567 reg |= ((height - 1) & 0x400) << 16; 568 lcdc_write(reg, LCD_RASTER_TIMING_2_REG); 569 } 570 571 /* Set the Raster Order of the Frame Buffer */ 572 reg = lcdc_read(LCD_RASTER_CTRL_REG) & ~(1 << 8); 573 if (raster_order) 574 reg |= LCD_RASTER_ORDER; 575 576 par->palette_sz = 16 * 2; 577 578 switch (bpp) { 579 case 1: 580 case 2: 581 case 4: 582 case 16: 583 break; 584 case 24: 585 reg |= LCD_V2_TFT_24BPP_MODE; 586 break; 587 case 32: 588 reg |= LCD_V2_TFT_24BPP_MODE; 589 reg |= LCD_V2_TFT_24BPP_UNPACK; 590 break; 591 case 8: 592 par->palette_sz = 256 * 2; 593 break; 594 595 default: 596 return -EINVAL; 597 } 598 599 lcdc_write(reg, LCD_RASTER_CTRL_REG); 600 601 return 0; 602 } 603 604 #define CNVT_TOHW(val, width) ((((val) << (width)) + 0x7FFF - (val)) >> 16) 605 static int fb_setcolreg(unsigned regno, unsigned red, unsigned green, 606 unsigned blue, unsigned transp, 607 struct fb_info *info) 608 { 609 struct da8xx_fb_par *par = info->par; 610 unsigned short *palette = (unsigned short *) par->v_palette_base; 611 u_short pal; 612 int update_hw = 0; 613 614 if (regno > 255) 615 return 1; 616 617 if (info->fix.visual == FB_VISUAL_DIRECTCOLOR) 618 return 1; 619 620 if (info->var.bits_per_pixel > 16 && lcd_revision == LCD_VERSION_1) 621 return -EINVAL; 622 623 switch (info->fix.visual) { 624 case FB_VISUAL_TRUECOLOR: 625 red = CNVT_TOHW(red, info->var.red.length); 626 green = CNVT_TOHW(green, info->var.green.length); 627 blue = CNVT_TOHW(blue, info->var.blue.length); 628 break; 629 case FB_VISUAL_PSEUDOCOLOR: 630 switch (info->var.bits_per_pixel) { 631 case 4: 632 if (regno > 15) 633 return -EINVAL; 634 635 if (info->var.grayscale) { 636 pal = regno; 637 } else { 638 red >>= 4; 639 green >>= 8; 640 blue >>= 12; 641 642 pal = red & 0x0f00; 643 pal |= green & 0x00f0; 644 pal |= blue & 0x000f; 645 } 646 if (regno == 0) 647 pal |= 0x2000; 648 palette[regno] = pal; 649 break; 650 651 case 8: 652 red >>= 4; 653 green >>= 8; 654 blue >>= 12; 655 656 pal = (red & 0x0f00); 657 pal |= (green & 0x00f0); 658 pal |= (blue & 0x000f); 659 660 if (palette[regno] != pal) { 661 update_hw = 1; 662 palette[regno] = pal; 663 } 664 break; 665 } 666 break; 667 } 668 669 /* Truecolor has hardware independent palette */ 670 if (info->fix.visual == FB_VISUAL_TRUECOLOR) { 671 u32 v; 672 673 if (regno > 15) 674 return -EINVAL; 675 676 v = (red << info->var.red.offset) | 677 (green << info->var.green.offset) | 678 (blue << info->var.blue.offset); 679 680 ((u32 *) (info->pseudo_palette))[regno] = v; 681 if (palette[0] != 0x4000) { 682 update_hw = 1; 683 palette[0] = 0x4000; 684 } 685 } 686 687 /* Update the palette in the h/w as needed. */ 688 if (update_hw) 689 lcd_blit(LOAD_PALETTE, par); 690 691 return 0; 692 } 693 #undef CNVT_TOHW 694 695 static void da8xx_fb_lcd_reset(void) 696 { 697 /* DMA has to be disabled */ 698 lcdc_write(0, LCD_DMA_CTRL_REG); 699 lcdc_write(0, LCD_RASTER_CTRL_REG); 700 701 if (lcd_revision == LCD_VERSION_2) { 702 lcdc_write(0, LCD_INT_ENABLE_SET_REG); 703 /* Write 1 to reset */ 704 lcdc_write(LCD_CLK_MAIN_RESET, LCD_CLK_RESET_REG); 705 lcdc_write(0, LCD_CLK_RESET_REG); 706 } 707 } 708 709 static int da8xx_fb_config_clk_divider(struct da8xx_fb_par *par, 710 unsigned lcdc_clk_div, 711 unsigned lcdc_clk_rate) 712 { 713 int ret; 714 715 if (par->lcdc_clk_rate != lcdc_clk_rate) { 716 ret = clk_set_rate(par->lcdc_clk, lcdc_clk_rate); 717 if (IS_ERR_VALUE(ret)) { 718 dev_err(par->dev, 719 "unable to set clock rate at %u\n", 720 lcdc_clk_rate); 721 return ret; 722 } 723 par->lcdc_clk_rate = clk_get_rate(par->lcdc_clk); 724 } 725 726 /* Configure the LCD clock divisor. */ 727 lcdc_write(LCD_CLK_DIVISOR(lcdc_clk_div) | 728 (LCD_RASTER_MODE & 0x1), LCD_CTRL_REG); 729 730 if (lcd_revision == LCD_VERSION_2) 731 lcdc_write(LCD_V2_DMA_CLK_EN | LCD_V2_LIDD_CLK_EN | 732 LCD_V2_CORE_CLK_EN, LCD_CLK_ENABLE_REG); 733 734 return 0; 735 } 736 737 static unsigned int da8xx_fb_calc_clk_divider(struct da8xx_fb_par *par, 738 unsigned pixclock, 739 unsigned *lcdc_clk_rate) 740 { 741 unsigned lcdc_clk_div; 742 743 pixclock = PICOS2KHZ(pixclock) * 1000; 744 745 *lcdc_clk_rate = par->lcdc_clk_rate; 746 747 if (pixclock < (*lcdc_clk_rate / CLK_MAX_DIV)) { 748 *lcdc_clk_rate = clk_round_rate(par->lcdc_clk, 749 pixclock * CLK_MAX_DIV); 750 lcdc_clk_div = CLK_MAX_DIV; 751 } else if (pixclock > (*lcdc_clk_rate / CLK_MIN_DIV)) { 752 *lcdc_clk_rate = clk_round_rate(par->lcdc_clk, 753 pixclock * CLK_MIN_DIV); 754 lcdc_clk_div = CLK_MIN_DIV; 755 } else { 756 lcdc_clk_div = *lcdc_clk_rate / pixclock; 757 } 758 759 return lcdc_clk_div; 760 } 761 762 static int da8xx_fb_calc_config_clk_divider(struct da8xx_fb_par *par, 763 struct fb_videomode *mode) 764 { 765 unsigned lcdc_clk_rate; 766 unsigned lcdc_clk_div = da8xx_fb_calc_clk_divider(par, mode->pixclock, 767 &lcdc_clk_rate); 768 769 return da8xx_fb_config_clk_divider(par, lcdc_clk_div, lcdc_clk_rate); 770 } 771 772 static unsigned da8xx_fb_round_clk(struct da8xx_fb_par *par, 773 unsigned pixclock) 774 { 775 unsigned lcdc_clk_div, lcdc_clk_rate; 776 777 lcdc_clk_div = da8xx_fb_calc_clk_divider(par, pixclock, &lcdc_clk_rate); 778 return KHZ2PICOS(lcdc_clk_rate / (1000 * lcdc_clk_div)); 779 } 780 781 static int lcd_init(struct da8xx_fb_par *par, const struct lcd_ctrl_config *cfg, 782 struct fb_videomode *panel) 783 { 784 u32 bpp; 785 int ret = 0; 786 787 ret = da8xx_fb_calc_config_clk_divider(par, panel); 788 if (IS_ERR_VALUE(ret)) { 789 dev_err(par->dev, "unable to configure clock\n"); 790 return ret; 791 } 792 793 if (panel->sync & FB_SYNC_CLK_INVERT) 794 lcdc_write((lcdc_read(LCD_RASTER_TIMING_2_REG) | 795 LCD_INVERT_PIXEL_CLOCK), LCD_RASTER_TIMING_2_REG); 796 else 797 lcdc_write((lcdc_read(LCD_RASTER_TIMING_2_REG) & 798 ~LCD_INVERT_PIXEL_CLOCK), LCD_RASTER_TIMING_2_REG); 799 800 /* Configure the DMA burst size and fifo threshold. */ 801 ret = lcd_cfg_dma(cfg->dma_burst_sz, cfg->fifo_th); 802 if (ret < 0) 803 return ret; 804 805 /* Configure the vertical and horizontal sync properties. */ 806 lcd_cfg_vertical_sync(panel->upper_margin, panel->vsync_len, 807 panel->lower_margin); 808 lcd_cfg_horizontal_sync(panel->left_margin, panel->hsync_len, 809 panel->right_margin); 810 811 /* Configure for disply */ 812 ret = lcd_cfg_display(cfg, panel); 813 if (ret < 0) 814 return ret; 815 816 bpp = cfg->bpp; 817 818 if (bpp == 12) 819 bpp = 16; 820 ret = lcd_cfg_frame_buffer(par, (unsigned int)panel->xres, 821 (unsigned int)panel->yres, bpp, 822 cfg->raster_order); 823 if (ret < 0) 824 return ret; 825 826 /* Configure FDD */ 827 lcdc_write((lcdc_read(LCD_RASTER_CTRL_REG) & 0xfff00fff) | 828 (cfg->fdd << 12), LCD_RASTER_CTRL_REG); 829 830 return 0; 831 } 832 833 /* IRQ handler for version 2 of LCDC */ 834 static irqreturn_t lcdc_irq_handler_rev02(int irq, void *arg) 835 { 836 struct da8xx_fb_par *par = arg; 837 u32 stat = lcdc_read(LCD_MASKED_STAT_REG); 838 839 if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) { 840 lcd_disable_raster(DA8XX_FRAME_NOWAIT); 841 lcdc_write(stat, LCD_MASKED_STAT_REG); 842 lcd_enable_raster(); 843 } else if (stat & LCD_PL_LOAD_DONE) { 844 /* 845 * Must disable raster before changing state of any control bit. 846 * And also must be disabled before clearing the PL loading 847 * interrupt via the following write to the status register. If 848 * this is done after then one gets multiple PL done interrupts. 849 */ 850 lcd_disable_raster(DA8XX_FRAME_NOWAIT); 851 852 lcdc_write(stat, LCD_MASKED_STAT_REG); 853 854 /* Disable PL completion interrupt */ 855 lcdc_write(LCD_V2_PL_INT_ENA, LCD_INT_ENABLE_CLR_REG); 856 857 /* Setup and start data loading mode */ 858 lcd_blit(LOAD_DATA, par); 859 } else { 860 lcdc_write(stat, LCD_MASKED_STAT_REG); 861 862 if (stat & LCD_END_OF_FRAME0) { 863 par->which_dma_channel_done = 0; 864 lcdc_write(par->dma_start, 865 LCD_DMA_FRM_BUF_BASE_ADDR_0_REG); 866 lcdc_write(par->dma_end, 867 LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG); 868 par->vsync_flag = 1; 869 wake_up_interruptible(&par->vsync_wait); 870 } 871 872 if (stat & LCD_END_OF_FRAME1) { 873 par->which_dma_channel_done = 1; 874 lcdc_write(par->dma_start, 875 LCD_DMA_FRM_BUF_BASE_ADDR_1_REG); 876 lcdc_write(par->dma_end, 877 LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG); 878 par->vsync_flag = 1; 879 wake_up_interruptible(&par->vsync_wait); 880 } 881 882 /* Set only when controller is disabled and at the end of 883 * active frame 884 */ 885 if (stat & BIT(0)) { 886 frame_done_flag = 1; 887 wake_up_interruptible(&frame_done_wq); 888 } 889 } 890 891 lcdc_write(0, LCD_END_OF_INT_IND_REG); 892 return IRQ_HANDLED; 893 } 894 895 /* IRQ handler for version 1 LCDC */ 896 static irqreturn_t lcdc_irq_handler_rev01(int irq, void *arg) 897 { 898 struct da8xx_fb_par *par = arg; 899 u32 stat = lcdc_read(LCD_STAT_REG); 900 u32 reg_ras; 901 902 if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) { 903 lcd_disable_raster(DA8XX_FRAME_NOWAIT); 904 lcdc_write(stat, LCD_STAT_REG); 905 lcd_enable_raster(); 906 } else if (stat & LCD_PL_LOAD_DONE) { 907 /* 908 * Must disable raster before changing state of any control bit. 909 * And also must be disabled before clearing the PL loading 910 * interrupt via the following write to the status register. If 911 * this is done after then one gets multiple PL done interrupts. 912 */ 913 lcd_disable_raster(DA8XX_FRAME_NOWAIT); 914 915 lcdc_write(stat, LCD_STAT_REG); 916 917 /* Disable PL completion inerrupt */ 918 reg_ras = lcdc_read(LCD_RASTER_CTRL_REG); 919 reg_ras &= ~LCD_V1_PL_INT_ENA; 920 lcdc_write(reg_ras, LCD_RASTER_CTRL_REG); 921 922 /* Setup and start data loading mode */ 923 lcd_blit(LOAD_DATA, par); 924 } else { 925 lcdc_write(stat, LCD_STAT_REG); 926 927 if (stat & LCD_END_OF_FRAME0) { 928 par->which_dma_channel_done = 0; 929 lcdc_write(par->dma_start, 930 LCD_DMA_FRM_BUF_BASE_ADDR_0_REG); 931 lcdc_write(par->dma_end, 932 LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG); 933 par->vsync_flag = 1; 934 wake_up_interruptible(&par->vsync_wait); 935 } 936 937 if (stat & LCD_END_OF_FRAME1) { 938 par->which_dma_channel_done = 1; 939 lcdc_write(par->dma_start, 940 LCD_DMA_FRM_BUF_BASE_ADDR_1_REG); 941 lcdc_write(par->dma_end, 942 LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG); 943 par->vsync_flag = 1; 944 wake_up_interruptible(&par->vsync_wait); 945 } 946 } 947 948 return IRQ_HANDLED; 949 } 950 951 static int fb_check_var(struct fb_var_screeninfo *var, 952 struct fb_info *info) 953 { 954 int err = 0; 955 struct da8xx_fb_par *par = info->par; 956 int bpp = var->bits_per_pixel >> 3; 957 unsigned long line_size = var->xres_virtual * bpp; 958 959 if (var->bits_per_pixel > 16 && lcd_revision == LCD_VERSION_1) 960 return -EINVAL; 961 962 switch (var->bits_per_pixel) { 963 case 1: 964 case 8: 965 var->red.offset = 0; 966 var->red.length = 8; 967 var->green.offset = 0; 968 var->green.length = 8; 969 var->blue.offset = 0; 970 var->blue.length = 8; 971 var->transp.offset = 0; 972 var->transp.length = 0; 973 var->nonstd = 0; 974 break; 975 case 4: 976 var->red.offset = 0; 977 var->red.length = 4; 978 var->green.offset = 0; 979 var->green.length = 4; 980 var->blue.offset = 0; 981 var->blue.length = 4; 982 var->transp.offset = 0; 983 var->transp.length = 0; 984 var->nonstd = FB_NONSTD_REV_PIX_IN_B; 985 break; 986 case 16: /* RGB 565 */ 987 var->red.offset = 11; 988 var->red.length = 5; 989 var->green.offset = 5; 990 var->green.length = 6; 991 var->blue.offset = 0; 992 var->blue.length = 5; 993 var->transp.offset = 0; 994 var->transp.length = 0; 995 var->nonstd = 0; 996 break; 997 case 24: 998 var->red.offset = 16; 999 var->red.length = 8; 1000 var->green.offset = 8; 1001 var->green.length = 8; 1002 var->blue.offset = 0; 1003 var->blue.length = 8; 1004 var->nonstd = 0; 1005 break; 1006 case 32: 1007 var->transp.offset = 24; 1008 var->transp.length = 8; 1009 var->red.offset = 16; 1010 var->red.length = 8; 1011 var->green.offset = 8; 1012 var->green.length = 8; 1013 var->blue.offset = 0; 1014 var->blue.length = 8; 1015 var->nonstd = 0; 1016 break; 1017 default: 1018 err = -EINVAL; 1019 } 1020 1021 var->red.msb_right = 0; 1022 var->green.msb_right = 0; 1023 var->blue.msb_right = 0; 1024 var->transp.msb_right = 0; 1025 1026 if (line_size * var->yres_virtual > par->vram_size) 1027 var->yres_virtual = par->vram_size / line_size; 1028 1029 if (var->yres > var->yres_virtual) 1030 var->yres = var->yres_virtual; 1031 1032 if (var->xres > var->xres_virtual) 1033 var->xres = var->xres_virtual; 1034 1035 if (var->xres + var->xoffset > var->xres_virtual) 1036 var->xoffset = var->xres_virtual - var->xres; 1037 if (var->yres + var->yoffset > var->yres_virtual) 1038 var->yoffset = var->yres_virtual - var->yres; 1039 1040 var->pixclock = da8xx_fb_round_clk(par, var->pixclock); 1041 1042 return err; 1043 } 1044 1045 #ifdef CONFIG_CPU_FREQ 1046 static int lcd_da8xx_cpufreq_transition(struct notifier_block *nb, 1047 unsigned long val, void *data) 1048 { 1049 struct da8xx_fb_par *par; 1050 1051 par = container_of(nb, struct da8xx_fb_par, freq_transition); 1052 if (val == CPUFREQ_POSTCHANGE) { 1053 if (par->lcdc_clk_rate != clk_get_rate(par->lcdc_clk)) { 1054 par->lcdc_clk_rate = clk_get_rate(par->lcdc_clk); 1055 lcd_disable_raster(DA8XX_FRAME_WAIT); 1056 da8xx_fb_calc_config_clk_divider(par, &par->mode); 1057 if (par->blank == FB_BLANK_UNBLANK) 1058 lcd_enable_raster(); 1059 } 1060 } 1061 1062 return 0; 1063 } 1064 1065 static int lcd_da8xx_cpufreq_register(struct da8xx_fb_par *par) 1066 { 1067 par->freq_transition.notifier_call = lcd_da8xx_cpufreq_transition; 1068 1069 return cpufreq_register_notifier(&par->freq_transition, 1070 CPUFREQ_TRANSITION_NOTIFIER); 1071 } 1072 1073 static void lcd_da8xx_cpufreq_deregister(struct da8xx_fb_par *par) 1074 { 1075 cpufreq_unregister_notifier(&par->freq_transition, 1076 CPUFREQ_TRANSITION_NOTIFIER); 1077 } 1078 #endif 1079 1080 static int fb_remove(struct platform_device *dev) 1081 { 1082 struct fb_info *info = dev_get_drvdata(&dev->dev); 1083 1084 if (info) { 1085 struct da8xx_fb_par *par = info->par; 1086 1087 #ifdef CONFIG_CPU_FREQ 1088 lcd_da8xx_cpufreq_deregister(par); 1089 #endif 1090 if (par->panel_power_ctrl) 1091 par->panel_power_ctrl(0); 1092 1093 lcd_disable_raster(DA8XX_FRAME_WAIT); 1094 lcdc_write(0, LCD_RASTER_CTRL_REG); 1095 1096 /* disable DMA */ 1097 lcdc_write(0, LCD_DMA_CTRL_REG); 1098 1099 unregister_framebuffer(info); 1100 fb_dealloc_cmap(&info->cmap); 1101 dma_free_coherent(NULL, PALETTE_SIZE, par->v_palette_base, 1102 par->p_palette_base); 1103 dma_free_coherent(NULL, par->vram_size, par->vram_virt, 1104 par->vram_phys); 1105 pm_runtime_put_sync(&dev->dev); 1106 pm_runtime_disable(&dev->dev); 1107 framebuffer_release(info); 1108 1109 } 1110 return 0; 1111 } 1112 1113 /* 1114 * Function to wait for vertical sync which for this LCD peripheral 1115 * translates into waiting for the current raster frame to complete. 1116 */ 1117 static int fb_wait_for_vsync(struct fb_info *info) 1118 { 1119 struct da8xx_fb_par *par = info->par; 1120 int ret; 1121 1122 /* 1123 * Set flag to 0 and wait for isr to set to 1. It would seem there is a 1124 * race condition here where the ISR could have occurred just before or 1125 * just after this set. But since we are just coarsely waiting for 1126 * a frame to complete then that's OK. i.e. if the frame completed 1127 * just before this code executed then we have to wait another full 1128 * frame time but there is no way to avoid such a situation. On the 1129 * other hand if the frame completed just after then we don't need 1130 * to wait long at all. Either way we are guaranteed to return to the 1131 * user immediately after a frame completion which is all that is 1132 * required. 1133 */ 1134 par->vsync_flag = 0; 1135 ret = wait_event_interruptible_timeout(par->vsync_wait, 1136 par->vsync_flag != 0, 1137 par->vsync_timeout); 1138 if (ret < 0) 1139 return ret; 1140 if (ret == 0) 1141 return -ETIMEDOUT; 1142 1143 return 0; 1144 } 1145 1146 static int fb_ioctl(struct fb_info *info, unsigned int cmd, 1147 unsigned long arg) 1148 { 1149 struct lcd_sync_arg sync_arg; 1150 1151 switch (cmd) { 1152 case FBIOGET_CONTRAST: 1153 case FBIOPUT_CONTRAST: 1154 case FBIGET_BRIGHTNESS: 1155 case FBIPUT_BRIGHTNESS: 1156 case FBIGET_COLOR: 1157 case FBIPUT_COLOR: 1158 return -ENOTTY; 1159 case FBIPUT_HSYNC: 1160 if (copy_from_user(&sync_arg, (char *)arg, 1161 sizeof(struct lcd_sync_arg))) 1162 return -EFAULT; 1163 lcd_cfg_horizontal_sync(sync_arg.back_porch, 1164 sync_arg.pulse_width, 1165 sync_arg.front_porch); 1166 break; 1167 case FBIPUT_VSYNC: 1168 if (copy_from_user(&sync_arg, (char *)arg, 1169 sizeof(struct lcd_sync_arg))) 1170 return -EFAULT; 1171 lcd_cfg_vertical_sync(sync_arg.back_porch, 1172 sync_arg.pulse_width, 1173 sync_arg.front_porch); 1174 break; 1175 case FBIO_WAITFORVSYNC: 1176 return fb_wait_for_vsync(info); 1177 default: 1178 return -EINVAL; 1179 } 1180 return 0; 1181 } 1182 1183 static int cfb_blank(int blank, struct fb_info *info) 1184 { 1185 struct da8xx_fb_par *par = info->par; 1186 int ret = 0; 1187 1188 if (par->blank == blank) 1189 return 0; 1190 1191 par->blank = blank; 1192 switch (blank) { 1193 case FB_BLANK_UNBLANK: 1194 lcd_enable_raster(); 1195 1196 if (par->panel_power_ctrl) 1197 par->panel_power_ctrl(1); 1198 break; 1199 case FB_BLANK_NORMAL: 1200 case FB_BLANK_VSYNC_SUSPEND: 1201 case FB_BLANK_HSYNC_SUSPEND: 1202 case FB_BLANK_POWERDOWN: 1203 if (par->panel_power_ctrl) 1204 par->panel_power_ctrl(0); 1205 1206 lcd_disable_raster(DA8XX_FRAME_WAIT); 1207 break; 1208 default: 1209 ret = -EINVAL; 1210 } 1211 1212 return ret; 1213 } 1214 1215 /* 1216 * Set new x,y offsets in the virtual display for the visible area and switch 1217 * to the new mode. 1218 */ 1219 static int da8xx_pan_display(struct fb_var_screeninfo *var, 1220 struct fb_info *fbi) 1221 { 1222 int ret = 0; 1223 struct fb_var_screeninfo new_var; 1224 struct da8xx_fb_par *par = fbi->par; 1225 struct fb_fix_screeninfo *fix = &fbi->fix; 1226 unsigned int end; 1227 unsigned int start; 1228 unsigned long irq_flags; 1229 1230 if (var->xoffset != fbi->var.xoffset || 1231 var->yoffset != fbi->var.yoffset) { 1232 memcpy(&new_var, &fbi->var, sizeof(new_var)); 1233 new_var.xoffset = var->xoffset; 1234 new_var.yoffset = var->yoffset; 1235 if (fb_check_var(&new_var, fbi)) 1236 ret = -EINVAL; 1237 else { 1238 memcpy(&fbi->var, &new_var, sizeof(new_var)); 1239 1240 start = fix->smem_start + 1241 new_var.yoffset * fix->line_length + 1242 new_var.xoffset * fbi->var.bits_per_pixel / 8; 1243 end = start + fbi->var.yres * fix->line_length - 1; 1244 par->dma_start = start; 1245 par->dma_end = end; 1246 spin_lock_irqsave(&par->lock_for_chan_update, 1247 irq_flags); 1248 if (par->which_dma_channel_done == 0) { 1249 lcdc_write(par->dma_start, 1250 LCD_DMA_FRM_BUF_BASE_ADDR_0_REG); 1251 lcdc_write(par->dma_end, 1252 LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG); 1253 } else if (par->which_dma_channel_done == 1) { 1254 lcdc_write(par->dma_start, 1255 LCD_DMA_FRM_BUF_BASE_ADDR_1_REG); 1256 lcdc_write(par->dma_end, 1257 LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG); 1258 } 1259 spin_unlock_irqrestore(&par->lock_for_chan_update, 1260 irq_flags); 1261 } 1262 } 1263 1264 return ret; 1265 } 1266 1267 static int da8xxfb_set_par(struct fb_info *info) 1268 { 1269 struct da8xx_fb_par *par = info->par; 1270 int ret; 1271 bool raster = da8xx_fb_is_raster_enabled(); 1272 1273 if (raster) 1274 lcd_disable_raster(DA8XX_FRAME_WAIT); 1275 1276 fb_var_to_videomode(&par->mode, &info->var); 1277 1278 par->cfg.bpp = info->var.bits_per_pixel; 1279 1280 info->fix.visual = (par->cfg.bpp <= 8) ? 1281 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR; 1282 info->fix.line_length = (par->mode.xres * par->cfg.bpp) / 8; 1283 1284 ret = lcd_init(par, &par->cfg, &par->mode); 1285 if (ret < 0) { 1286 dev_err(par->dev, "lcd init failed\n"); 1287 return ret; 1288 } 1289 1290 par->dma_start = info->fix.smem_start + 1291 info->var.yoffset * info->fix.line_length + 1292 info->var.xoffset * info->var.bits_per_pixel / 8; 1293 par->dma_end = par->dma_start + 1294 info->var.yres * info->fix.line_length - 1; 1295 1296 lcdc_write(par->dma_start, LCD_DMA_FRM_BUF_BASE_ADDR_0_REG); 1297 lcdc_write(par->dma_end, LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG); 1298 lcdc_write(par->dma_start, LCD_DMA_FRM_BUF_BASE_ADDR_1_REG); 1299 lcdc_write(par->dma_end, LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG); 1300 1301 if (raster) 1302 lcd_enable_raster(); 1303 1304 return 0; 1305 } 1306 1307 static struct fb_ops da8xx_fb_ops = { 1308 .owner = THIS_MODULE, 1309 .fb_check_var = fb_check_var, 1310 .fb_set_par = da8xxfb_set_par, 1311 .fb_setcolreg = fb_setcolreg, 1312 .fb_pan_display = da8xx_pan_display, 1313 .fb_ioctl = fb_ioctl, 1314 .fb_fillrect = cfb_fillrect, 1315 .fb_copyarea = cfb_copyarea, 1316 .fb_imageblit = cfb_imageblit, 1317 .fb_blank = cfb_blank, 1318 }; 1319 1320 static struct fb_videomode *da8xx_fb_get_videomode(struct platform_device *dev) 1321 { 1322 struct da8xx_lcdc_platform_data *fb_pdata = dev_get_platdata(&dev->dev); 1323 struct fb_videomode *lcdc_info; 1324 int i; 1325 1326 for (i = 0, lcdc_info = known_lcd_panels; 1327 i < ARRAY_SIZE(known_lcd_panels); i++, lcdc_info++) { 1328 if (strcmp(fb_pdata->type, lcdc_info->name) == 0) 1329 break; 1330 } 1331 1332 if (i == ARRAY_SIZE(known_lcd_panels)) { 1333 dev_err(&dev->dev, "no panel found\n"); 1334 return NULL; 1335 } 1336 dev_info(&dev->dev, "found %s panel\n", lcdc_info->name); 1337 1338 return lcdc_info; 1339 } 1340 1341 static int fb_probe(struct platform_device *device) 1342 { 1343 struct da8xx_lcdc_platform_data *fb_pdata = 1344 dev_get_platdata(&device->dev); 1345 static struct resource *lcdc_regs; 1346 struct lcd_ctrl_config *lcd_cfg; 1347 struct fb_videomode *lcdc_info; 1348 struct fb_info *da8xx_fb_info; 1349 struct da8xx_fb_par *par; 1350 struct clk *tmp_lcdc_clk; 1351 int ret; 1352 unsigned long ulcm; 1353 1354 if (fb_pdata == NULL) { 1355 dev_err(&device->dev, "Can not get platform data\n"); 1356 return -ENOENT; 1357 } 1358 1359 lcdc_info = da8xx_fb_get_videomode(device); 1360 if (lcdc_info == NULL) 1361 return -ENODEV; 1362 1363 lcdc_regs = platform_get_resource(device, IORESOURCE_MEM, 0); 1364 da8xx_fb_reg_base = devm_ioremap_resource(&device->dev, lcdc_regs); 1365 if (IS_ERR(da8xx_fb_reg_base)) 1366 return PTR_ERR(da8xx_fb_reg_base); 1367 1368 tmp_lcdc_clk = devm_clk_get(&device->dev, "fck"); 1369 if (IS_ERR(tmp_lcdc_clk)) { 1370 dev_err(&device->dev, "Can not get device clock\n"); 1371 return PTR_ERR(tmp_lcdc_clk); 1372 } 1373 1374 pm_runtime_enable(&device->dev); 1375 pm_runtime_get_sync(&device->dev); 1376 1377 /* Determine LCD IP Version */ 1378 switch (lcdc_read(LCD_PID_REG)) { 1379 case 0x4C100102: 1380 lcd_revision = LCD_VERSION_1; 1381 break; 1382 case 0x4F200800: 1383 case 0x4F201000: 1384 lcd_revision = LCD_VERSION_2; 1385 break; 1386 default: 1387 dev_warn(&device->dev, "Unknown PID Reg value 0x%x, " 1388 "defaulting to LCD revision 1\n", 1389 lcdc_read(LCD_PID_REG)); 1390 lcd_revision = LCD_VERSION_1; 1391 break; 1392 } 1393 1394 lcd_cfg = (struct lcd_ctrl_config *)fb_pdata->controller_data; 1395 1396 if (!lcd_cfg) { 1397 ret = -EINVAL; 1398 goto err_pm_runtime_disable; 1399 } 1400 1401 da8xx_fb_info = framebuffer_alloc(sizeof(struct da8xx_fb_par), 1402 &device->dev); 1403 if (!da8xx_fb_info) { 1404 dev_dbg(&device->dev, "Memory allocation failed for fb_info\n"); 1405 ret = -ENOMEM; 1406 goto err_pm_runtime_disable; 1407 } 1408 1409 par = da8xx_fb_info->par; 1410 par->dev = &device->dev; 1411 par->lcdc_clk = tmp_lcdc_clk; 1412 par->lcdc_clk_rate = clk_get_rate(par->lcdc_clk); 1413 if (fb_pdata->panel_power_ctrl) { 1414 par->panel_power_ctrl = fb_pdata->panel_power_ctrl; 1415 par->panel_power_ctrl(1); 1416 } 1417 1418 fb_videomode_to_var(&da8xx_fb_var, lcdc_info); 1419 par->cfg = *lcd_cfg; 1420 1421 da8xx_fb_lcd_reset(); 1422 1423 /* allocate frame buffer */ 1424 par->vram_size = lcdc_info->xres * lcdc_info->yres * lcd_cfg->bpp; 1425 ulcm = lcm((lcdc_info->xres * lcd_cfg->bpp)/8, PAGE_SIZE); 1426 par->vram_size = roundup(par->vram_size/8, ulcm); 1427 par->vram_size = par->vram_size * LCD_NUM_BUFFERS; 1428 1429 par->vram_virt = dma_alloc_coherent(NULL, 1430 par->vram_size, 1431 (resource_size_t *) &par->vram_phys, 1432 GFP_KERNEL | GFP_DMA); 1433 if (!par->vram_virt) { 1434 dev_err(&device->dev, 1435 "GLCD: kmalloc for frame buffer failed\n"); 1436 ret = -EINVAL; 1437 goto err_release_fb; 1438 } 1439 1440 da8xx_fb_info->screen_base = (char __iomem *) par->vram_virt; 1441 da8xx_fb_fix.smem_start = par->vram_phys; 1442 da8xx_fb_fix.smem_len = par->vram_size; 1443 da8xx_fb_fix.line_length = (lcdc_info->xres * lcd_cfg->bpp) / 8; 1444 1445 par->dma_start = par->vram_phys; 1446 par->dma_end = par->dma_start + lcdc_info->yres * 1447 da8xx_fb_fix.line_length - 1; 1448 1449 /* allocate palette buffer */ 1450 par->v_palette_base = dma_alloc_coherent(NULL, 1451 PALETTE_SIZE, 1452 (resource_size_t *) 1453 &par->p_palette_base, 1454 GFP_KERNEL | GFP_DMA); 1455 if (!par->v_palette_base) { 1456 dev_err(&device->dev, 1457 "GLCD: kmalloc for palette buffer failed\n"); 1458 ret = -EINVAL; 1459 goto err_release_fb_mem; 1460 } 1461 memset(par->v_palette_base, 0, PALETTE_SIZE); 1462 1463 par->irq = platform_get_irq(device, 0); 1464 if (par->irq < 0) { 1465 ret = -ENOENT; 1466 goto err_release_pl_mem; 1467 } 1468 1469 da8xx_fb_var.grayscale = 1470 lcd_cfg->panel_shade == MONOCHROME ? 1 : 0; 1471 da8xx_fb_var.bits_per_pixel = lcd_cfg->bpp; 1472 1473 /* Initialize fbinfo */ 1474 da8xx_fb_info->flags = FBINFO_FLAG_DEFAULT; 1475 da8xx_fb_info->fix = da8xx_fb_fix; 1476 da8xx_fb_info->var = da8xx_fb_var; 1477 da8xx_fb_info->fbops = &da8xx_fb_ops; 1478 da8xx_fb_info->pseudo_palette = par->pseudo_palette; 1479 da8xx_fb_info->fix.visual = (da8xx_fb_info->var.bits_per_pixel <= 8) ? 1480 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR; 1481 1482 ret = fb_alloc_cmap(&da8xx_fb_info->cmap, PALETTE_SIZE, 0); 1483 if (ret) 1484 goto err_release_pl_mem; 1485 da8xx_fb_info->cmap.len = par->palette_sz; 1486 1487 /* initialize var_screeninfo */ 1488 da8xx_fb_var.activate = FB_ACTIVATE_FORCE; 1489 fb_set_var(da8xx_fb_info, &da8xx_fb_var); 1490 1491 dev_set_drvdata(&device->dev, da8xx_fb_info); 1492 1493 /* initialize the vsync wait queue */ 1494 init_waitqueue_head(&par->vsync_wait); 1495 par->vsync_timeout = HZ / 5; 1496 par->which_dma_channel_done = -1; 1497 spin_lock_init(&par->lock_for_chan_update); 1498 1499 /* Register the Frame Buffer */ 1500 if (register_framebuffer(da8xx_fb_info) < 0) { 1501 dev_err(&device->dev, 1502 "GLCD: Frame Buffer Registration Failed!\n"); 1503 ret = -EINVAL; 1504 goto err_dealloc_cmap; 1505 } 1506 1507 #ifdef CONFIG_CPU_FREQ 1508 ret = lcd_da8xx_cpufreq_register(par); 1509 if (ret) { 1510 dev_err(&device->dev, "failed to register cpufreq\n"); 1511 goto err_cpu_freq; 1512 } 1513 #endif 1514 1515 if (lcd_revision == LCD_VERSION_1) 1516 lcdc_irq_handler = lcdc_irq_handler_rev01; 1517 else { 1518 init_waitqueue_head(&frame_done_wq); 1519 lcdc_irq_handler = lcdc_irq_handler_rev02; 1520 } 1521 1522 ret = devm_request_irq(&device->dev, par->irq, lcdc_irq_handler, 0, 1523 DRIVER_NAME, par); 1524 if (ret) 1525 goto irq_freq; 1526 return 0; 1527 1528 irq_freq: 1529 #ifdef CONFIG_CPU_FREQ 1530 lcd_da8xx_cpufreq_deregister(par); 1531 err_cpu_freq: 1532 #endif 1533 unregister_framebuffer(da8xx_fb_info); 1534 1535 err_dealloc_cmap: 1536 fb_dealloc_cmap(&da8xx_fb_info->cmap); 1537 1538 err_release_pl_mem: 1539 dma_free_coherent(NULL, PALETTE_SIZE, par->v_palette_base, 1540 par->p_palette_base); 1541 1542 err_release_fb_mem: 1543 dma_free_coherent(NULL, par->vram_size, par->vram_virt, par->vram_phys); 1544 1545 err_release_fb: 1546 framebuffer_release(da8xx_fb_info); 1547 1548 err_pm_runtime_disable: 1549 pm_runtime_put_sync(&device->dev); 1550 pm_runtime_disable(&device->dev); 1551 1552 return ret; 1553 } 1554 1555 #ifdef CONFIG_PM_SLEEP 1556 static struct lcdc_context { 1557 u32 clk_enable; 1558 u32 ctrl; 1559 u32 dma_ctrl; 1560 u32 raster_timing_0; 1561 u32 raster_timing_1; 1562 u32 raster_timing_2; 1563 u32 int_enable_set; 1564 u32 dma_frm_buf_base_addr_0; 1565 u32 dma_frm_buf_ceiling_addr_0; 1566 u32 dma_frm_buf_base_addr_1; 1567 u32 dma_frm_buf_ceiling_addr_1; 1568 u32 raster_ctrl; 1569 } reg_context; 1570 1571 static void lcd_context_save(void) 1572 { 1573 if (lcd_revision == LCD_VERSION_2) { 1574 reg_context.clk_enable = lcdc_read(LCD_CLK_ENABLE_REG); 1575 reg_context.int_enable_set = lcdc_read(LCD_INT_ENABLE_SET_REG); 1576 } 1577 1578 reg_context.ctrl = lcdc_read(LCD_CTRL_REG); 1579 reg_context.dma_ctrl = lcdc_read(LCD_DMA_CTRL_REG); 1580 reg_context.raster_timing_0 = lcdc_read(LCD_RASTER_TIMING_0_REG); 1581 reg_context.raster_timing_1 = lcdc_read(LCD_RASTER_TIMING_1_REG); 1582 reg_context.raster_timing_2 = lcdc_read(LCD_RASTER_TIMING_2_REG); 1583 reg_context.dma_frm_buf_base_addr_0 = 1584 lcdc_read(LCD_DMA_FRM_BUF_BASE_ADDR_0_REG); 1585 reg_context.dma_frm_buf_ceiling_addr_0 = 1586 lcdc_read(LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG); 1587 reg_context.dma_frm_buf_base_addr_1 = 1588 lcdc_read(LCD_DMA_FRM_BUF_BASE_ADDR_1_REG); 1589 reg_context.dma_frm_buf_ceiling_addr_1 = 1590 lcdc_read(LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG); 1591 reg_context.raster_ctrl = lcdc_read(LCD_RASTER_CTRL_REG); 1592 return; 1593 } 1594 1595 static void lcd_context_restore(void) 1596 { 1597 if (lcd_revision == LCD_VERSION_2) { 1598 lcdc_write(reg_context.clk_enable, LCD_CLK_ENABLE_REG); 1599 lcdc_write(reg_context.int_enable_set, LCD_INT_ENABLE_SET_REG); 1600 } 1601 1602 lcdc_write(reg_context.ctrl, LCD_CTRL_REG); 1603 lcdc_write(reg_context.dma_ctrl, LCD_DMA_CTRL_REG); 1604 lcdc_write(reg_context.raster_timing_0, LCD_RASTER_TIMING_0_REG); 1605 lcdc_write(reg_context.raster_timing_1, LCD_RASTER_TIMING_1_REG); 1606 lcdc_write(reg_context.raster_timing_2, LCD_RASTER_TIMING_2_REG); 1607 lcdc_write(reg_context.dma_frm_buf_base_addr_0, 1608 LCD_DMA_FRM_BUF_BASE_ADDR_0_REG); 1609 lcdc_write(reg_context.dma_frm_buf_ceiling_addr_0, 1610 LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG); 1611 lcdc_write(reg_context.dma_frm_buf_base_addr_1, 1612 LCD_DMA_FRM_BUF_BASE_ADDR_1_REG); 1613 lcdc_write(reg_context.dma_frm_buf_ceiling_addr_1, 1614 LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG); 1615 lcdc_write(reg_context.raster_ctrl, LCD_RASTER_CTRL_REG); 1616 return; 1617 } 1618 1619 static int fb_suspend(struct device *dev) 1620 { 1621 struct fb_info *info = dev_get_drvdata(dev); 1622 struct da8xx_fb_par *par = info->par; 1623 1624 console_lock(); 1625 if (par->panel_power_ctrl) 1626 par->panel_power_ctrl(0); 1627 1628 fb_set_suspend(info, 1); 1629 lcd_disable_raster(DA8XX_FRAME_WAIT); 1630 lcd_context_save(); 1631 pm_runtime_put_sync(dev); 1632 console_unlock(); 1633 1634 return 0; 1635 } 1636 static int fb_resume(struct device *dev) 1637 { 1638 struct fb_info *info = dev_get_drvdata(dev); 1639 struct da8xx_fb_par *par = info->par; 1640 1641 console_lock(); 1642 pm_runtime_get_sync(dev); 1643 lcd_context_restore(); 1644 if (par->blank == FB_BLANK_UNBLANK) { 1645 lcd_enable_raster(); 1646 1647 if (par->panel_power_ctrl) 1648 par->panel_power_ctrl(1); 1649 } 1650 1651 fb_set_suspend(info, 0); 1652 console_unlock(); 1653 1654 return 0; 1655 } 1656 #endif 1657 1658 static SIMPLE_DEV_PM_OPS(fb_pm_ops, fb_suspend, fb_resume); 1659 1660 static struct platform_driver da8xx_fb_driver = { 1661 .probe = fb_probe, 1662 .remove = fb_remove, 1663 .driver = { 1664 .name = DRIVER_NAME, 1665 .owner = THIS_MODULE, 1666 .pm = &fb_pm_ops, 1667 }, 1668 }; 1669 module_platform_driver(da8xx_fb_driver); 1670 1671 MODULE_DESCRIPTION("Framebuffer driver for TI da8xx/omap-l1xx"); 1672 MODULE_AUTHOR("Texas Instruments"); 1673 MODULE_LICENSE("GPL"); 1674