1 /* 2 * linux/drivers/video/cyber2000fb.h 3 * 4 * Copyright (C) 1998-2000 Russell King 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * Integraphics Cyber2000 frame buffer device 11 */ 12 13 /* 14 * Internal CyberPro sizes and offsets. 15 */ 16 #define MMIO_OFFSET 0x00800000 17 #define MMIO_SIZE 0x000c0000 18 19 #define NR_PALETTE 256 20 21 #if defined(DEBUG) && defined(CONFIG_DEBUG_LL) 22 static void debug_printf(char *fmt, ...) 23 { 24 extern void printascii(const char *); 25 char buffer[128]; 26 va_list ap; 27 28 va_start(ap, fmt); 29 vsprintf(buffer, fmt, ap); 30 va_end(ap); 31 32 printascii(buffer); 33 } 34 #else 35 #define debug_printf(x...) do { } while (0) 36 #endif 37 38 #define RAMDAC_RAMPWRDN 0x01 39 #define RAMDAC_DAC8BIT 0x02 40 #define RAMDAC_VREFEN 0x04 41 #define RAMDAC_BYPASS 0x10 42 #define RAMDAC_DACPWRDN 0x40 43 44 #define EXT_CRT_VRTOFL 0x11 45 #define EXT_CRT_VRTOFL_LINECOMP10 0x10 46 #define EXT_CRT_VRTOFL_INTERLACE 0x20 47 48 #define EXT_CRT_IRQ 0x12 49 #define EXT_CRT_IRQ_ENABLE 0x01 50 #define EXT_CRT_IRQ_ACT_HIGH 0x04 51 52 #define EXT_CRT_TEST 0x13 53 54 #define EXT_SYNC_CTL 0x16 55 #define EXT_SYNC_CTL_HS_NORMAL 0x00 56 #define EXT_SYNC_CTL_HS_0 0x01 57 #define EXT_SYNC_CTL_HS_1 0x02 58 #define EXT_SYNC_CTL_HS_HSVS 0x03 59 #define EXT_SYNC_CTL_VS_NORMAL 0x00 60 #define EXT_SYNC_CTL_VS_0 0x04 61 #define EXT_SYNC_CTL_VS_1 0x08 62 #define EXT_SYNC_CTL_VS_COMP 0x0c 63 64 #define EXT_BUS_CTL 0x30 65 #define EXT_BUS_CTL_LIN_1MB 0x00 66 #define EXT_BUS_CTL_LIN_2MB 0x01 67 #define EXT_BUS_CTL_LIN_4MB 0x02 68 #define EXT_BUS_CTL_ZEROWAIT 0x04 69 #define EXT_BUS_CTL_PCIBURST_WRITE 0x20 70 #define EXT_BUS_CTL_PCIBURST_READ 0x80 /* CyberPro 5000 only */ 71 72 #define EXT_SEG_WRITE_PTR 0x31 73 #define EXT_SEG_READ_PTR 0x32 74 #define EXT_BIU_MISC 0x33 75 #define EXT_BIU_MISC_LIN_ENABLE 0x01 76 #define EXT_BIU_MISC_COP_ENABLE 0x04 77 #define EXT_BIU_MISC_COP_BFC 0x08 78 79 #define EXT_FUNC_CTL 0x3c 80 #define EXT_FUNC_CTL_EXTREGENBL 0x80 /* enable access to 0xbcxxx */ 81 82 #define PCI_BM_CTL 0x3e 83 #define PCI_BM_CTL_ENABLE 0x01 /* enable bus-master */ 84 #define PCI_BM_CTL_BURST 0x02 /* enable burst */ 85 #define PCI_BM_CTL_BACK2BACK 0x04 /* enable back to back */ 86 #define PCI_BM_CTL_DUMMY 0x08 /* insert dummy cycle */ 87 88 #define X_V2_VID_MEM_START 0x40 89 #define X_V2_VID_SRC_WIDTH 0x43 90 #define X_V2_X_START 0x45 91 #define X_V2_X_END 0x47 92 #define X_V2_Y_START 0x49 93 #define X_V2_Y_END 0x4b 94 #define X_V2_VID_SRC_WIN_WIDTH 0x4d 95 96 #define Y_V2_DDA_X_INC 0x43 97 #define Y_V2_DDA_Y_INC 0x47 98 #define Y_V2_VID_FIFO_CTL 0x49 99 #define Y_V2_VID_FMT 0x4b 100 #define Y_V2_VID_DISP_CTL1 0x4c 101 #define Y_V2_VID_FIFO_CTL1 0x4d 102 103 #define J_X2_VID_MEM_START 0x40 104 #define J_X2_VID_SRC_WIDTH 0x43 105 #define J_X2_X_START 0x47 106 #define J_X2_X_END 0x49 107 #define J_X2_Y_START 0x4b 108 #define J_X2_Y_END 0x4d 109 #define J_X2_VID_SRC_WIN_WIDTH 0x4f 110 111 #define K_X2_DDA_X_INIT 0x40 112 #define K_X2_DDA_X_INC 0x42 113 #define K_X2_DDA_Y_INIT 0x44 114 #define K_X2_DDA_Y_INC 0x46 115 #define K_X2_VID_FMT 0x48 116 #define K_X2_VID_DISP_CTL1 0x49 117 118 #define K_CAP_X2_CTL1 0x49 119 120 #define CURS_H_START 0x50 121 #define CURS_H_PRESET 0x52 122 #define CURS_V_START 0x53 123 #define CURS_V_PRESET 0x55 124 #define CURS_CTL 0x56 125 126 #define EXT_ATTRIB_CTL 0x57 127 #define EXT_ATTRIB_CTL_EXT 0x01 128 129 #define EXT_OVERSCAN_RED 0x58 130 #define EXT_OVERSCAN_GREEN 0x59 131 #define EXT_OVERSCAN_BLUE 0x5a 132 133 #define CAP_X_START 0x60 134 #define CAP_X_END 0x62 135 #define CAP_Y_START 0x64 136 #define CAP_Y_END 0x66 137 #define CAP_DDA_X_INIT 0x68 138 #define CAP_DDA_X_INC 0x6a 139 #define CAP_DDA_Y_INIT 0x6c 140 #define CAP_DDA_Y_INC 0x6e 141 142 #define EXT_MEM_CTL0 0x70 143 #define EXT_MEM_CTL0_7CLK 0x01 144 #define EXT_MEM_CTL0_RAS_1 0x02 145 #define EXT_MEM_CTL0_RAS2CAS_1 0x04 146 #define EXT_MEM_CTL0_MULTCAS 0x08 147 #define EXT_MEM_CTL0_ASYM 0x10 148 #define EXT_MEM_CTL0_CAS1ON 0x20 149 #define EXT_MEM_CTL0_FIFOFLUSH 0x40 150 #define EXT_MEM_CTL0_SEQRESET 0x80 151 152 #define EXT_MEM_CTL1 0x71 153 #define EXT_MEM_CTL1_PAR 0x00 154 #define EXT_MEM_CTL1_SERPAR 0x01 155 #define EXT_MEM_CTL1_SER 0x03 156 #define EXT_MEM_CTL1_SYNC 0x04 157 #define EXT_MEM_CTL1_VRAM 0x08 158 #define EXT_MEM_CTL1_4K_REFRESH 0x10 159 #define EXT_MEM_CTL1_256Kx4 0x00 160 #define EXT_MEM_CTL1_512Kx8 0x40 161 #define EXT_MEM_CTL1_1Mx16 0x60 162 163 #define EXT_MEM_CTL2 0x72 164 #define MEM_CTL2_SIZE_1MB 0x00 165 #define MEM_CTL2_SIZE_2MB 0x01 166 #define MEM_CTL2_SIZE_4MB 0x02 167 #define MEM_CTL2_SIZE_MASK 0x03 168 #define MEM_CTL2_64BIT 0x04 169 170 #define EXT_HIDDEN_CTL1 0x73 171 172 #define EXT_FIFO_CTL 0x74 173 174 #define EXT_SEQ_MISC 0x77 175 #define EXT_SEQ_MISC_8 0x01 176 #define EXT_SEQ_MISC_16_RGB565 0x02 177 #define EXT_SEQ_MISC_32 0x03 178 #define EXT_SEQ_MISC_24_RGB888 0x04 179 #define EXT_SEQ_MISC_16_RGB555 0x06 180 #define EXT_SEQ_MISC_8_RGB332 0x09 181 #define EXT_SEQ_MISC_16_RGB444 0x0a 182 183 #define EXT_HIDDEN_CTL4 0x7a 184 185 #define CURS_MEM_START 0x7e /* bits 23..12 */ 186 187 #define CAP_PIP_X_START 0x80 188 #define CAP_PIP_X_END 0x82 189 #define CAP_PIP_Y_START 0x84 190 #define CAP_PIP_Y_END 0x86 191 192 #define EXT_CAP_CTL1 0x88 193 194 #define EXT_CAP_CTL2 0x89 195 #define EXT_CAP_CTL2_ODDFRAMEIRQ 0x01 196 #define EXT_CAP_CTL2_ANYFRAMEIRQ 0x02 197 198 #define BM_CTRL0 0x9c 199 #define BM_CTRL1 0x9d 200 201 #define EXT_CAP_MODE1 0xa4 202 #define EXT_CAP_MODE1_8BIT 0x01 /* enable 8bit capture mode */ 203 #define EXT_CAP_MODE1_CCIR656 0x02 /* CCIR656 mode */ 204 #define EXT_CAP_MODE1_IGNOREVGT 0x04 /* ignore VGT */ 205 #define EXT_CAP_MODE1_ALTFIFO 0x10 /* use alternate FIFO for capture */ 206 #define EXT_CAP_MODE1_SWAPUV 0x20 /* swap UV bytes */ 207 #define EXT_CAP_MODE1_MIRRORY 0x40 /* mirror vertically */ 208 #define EXT_CAP_MODE1_MIRRORX 0x80 /* mirror horizontally */ 209 210 #define EXT_CAP_MODE2 0xa5 211 #define EXT_CAP_MODE2_CCIRINVOE 0x01 212 #define EXT_CAP_MODE2_CCIRINVVGT 0x02 213 #define EXT_CAP_MODE2_CCIRINVHGT 0x04 214 #define EXT_CAP_MODE2_CCIRINVDG 0x08 215 #define EXT_CAP_MODE2_DATEND 0x10 216 #define EXT_CAP_MODE2_CCIRDGH 0x20 217 #define EXT_CAP_MODE2_FIXSONY 0x40 218 #define EXT_CAP_MODE2_SYNCFREEZE 0x80 219 220 #define EXT_TV_CTL 0xae 221 222 #define EXT_DCLK_MULT 0xb0 223 #define EXT_DCLK_DIV 0xb1 224 #define EXT_DCLK_DIV_VFSEL 0x20 225 #define EXT_MCLK_MULT 0xb2 226 #define EXT_MCLK_DIV 0xb3 227 228 #define EXT_LATCH1 0xb5 229 #define EXT_LATCH1_VAFC_EN 0x01 /* enable VAFC */ 230 231 #define EXT_FEATURE 0xb7 232 #define EXT_FEATURE_BUS_MASK 0x07 /* host bus mask */ 233 #define EXT_FEATURE_BUS_PCI 0x00 234 #define EXT_FEATURE_BUS_VL_STD 0x04 235 #define EXT_FEATURE_BUS_VL_LINEAR 0x05 236 #define EXT_FEATURE_1682 0x20 /* IGS 1682 compatibility */ 237 238 #define EXT_LATCH2 0xb6 239 #define EXT_LATCH2_I2C_CLKEN 0x10 240 #define EXT_LATCH2_I2C_CLK 0x20 241 #define EXT_LATCH2_I2C_DATEN 0x40 242 #define EXT_LATCH2_I2C_DAT 0x80 243 244 #define EXT_XT_CTL 0xbe 245 #define EXT_XT_CAP16 0x04 246 #define EXT_XT_LINEARFB 0x08 247 #define EXT_XT_PAL 0x10 248 249 #define EXT_MEM_START 0xc0 /* ext start address 21 bits */ 250 #define HOR_PHASE_SHIFT 0xc2 /* high 3 bits */ 251 #define EXT_SRC_WIDTH 0xc3 /* ext offset phase 10 bits */ 252 #define EXT_SRC_HEIGHT 0xc4 /* high 6 bits */ 253 #define EXT_X_START 0xc5 /* ext->screen, 16 bits */ 254 #define EXT_X_END 0xc7 /* ext->screen, 16 bits */ 255 #define EXT_Y_START 0xc9 /* ext->screen, 16 bits */ 256 #define EXT_Y_END 0xcb /* ext->screen, 16 bits */ 257 #define EXT_SRC_WIN_WIDTH 0xcd /* 8 bits */ 258 #define EXT_COLOUR_COMPARE 0xce /* 24 bits */ 259 #define EXT_DDA_X_INIT 0xd1 /* ext->screen 16 bits */ 260 #define EXT_DDA_X_INC 0xd3 /* ext->screen 16 bits */ 261 #define EXT_DDA_Y_INIT 0xd5 /* ext->screen 16 bits */ 262 #define EXT_DDA_Y_INC 0xd7 /* ext->screen 16 bits */ 263 264 #define EXT_VID_FIFO_CTL 0xd9 265 266 #define EXT_VID_FMT 0xdb 267 #define EXT_VID_FMT_YUV422 0x00 /* formats - does this cause conversion? */ 268 #define EXT_VID_FMT_RGB555 0x01 269 #define EXT_VID_FMT_RGB565 0x02 270 #define EXT_VID_FMT_RGB888_24 0x03 271 #define EXT_VID_FMT_RGB888_32 0x04 272 #define EXT_VID_FMT_RGB8 0x05 273 #define EXT_VID_FMT_RGB4444 0x06 274 #define EXT_VID_FMT_RGB8T 0x07 275 #define EXT_VID_FMT_DUP_PIX_ZOON 0x08 /* duplicate pixel zoom */ 276 #define EXT_VID_FMT_MOD_3RD_PIX 0x20 /* modify 3rd duplicated pixel */ 277 #define EXT_VID_FMT_DBL_H_PIX 0x40 /* double horiz pixels */ 278 #define EXT_VID_FMT_YUV128 0x80 /* YUV data offset by 128 */ 279 280 #define EXT_VID_DISP_CTL1 0xdc 281 #define EXT_VID_DISP_CTL1_INTRAM 0x01 /* video pixels go to internal RAM */ 282 #define EXT_VID_DISP_CTL1_IGNORE_CCOMP 0x02 /* ignore colour compare registers */ 283 #define EXT_VID_DISP_CTL1_NOCLIP 0x04 /* do not clip to 16235,16240 */ 284 #define EXT_VID_DISP_CTL1_UV_AVG 0x08 /* U/V data is averaged */ 285 #define EXT_VID_DISP_CTL1_Y128 0x10 /* Y data offset by 128 (if YUV128 set) */ 286 #define EXT_VID_DISP_CTL1_VINTERPOL_OFF 0x20 /* disable vertical interpolation */ 287 #define EXT_VID_DISP_CTL1_FULL_WIN 0x40 /* video out window full */ 288 #define EXT_VID_DISP_CTL1_ENABLE_WINDOW 0x80 /* enable video window */ 289 290 #define EXT_VID_FIFO_CTL1 0xdd 291 #define EXT_VID_FIFO_CTL1_OE_HIGH 0x02 292 #define EXT_VID_FIFO_CTL1_INTERLEAVE 0x04 /* enable interleaved memory read */ 293 294 #define EXT_ROM_UCB4GH 0xe5 295 #define EXT_ROM_UCB4GH_FREEZE 0x02 /* capture frozen */ 296 #define EXT_ROM_UCB4GH_ODDFRAME 0x04 /* 1 = odd frame captured */ 297 #define EXT_ROM_UCB4GH_1HL 0x08 /* first horizonal line after VGT falling edge */ 298 #define EXT_ROM_UCB4GH_ODD 0x10 /* odd frame indicator */ 299 #define EXT_ROM_UCB4GH_INTSTAT 0x20 /* video interrupt */ 300 301 #define VFAC_CTL1 0xe8 302 #define VFAC_CTL1_CAPTURE 0x01 /* capture enable (only when VSYNC high)*/ 303 #define VFAC_CTL1_VFAC_ENABLE 0x02 /* vfac enable */ 304 #define VFAC_CTL1_FREEZE_CAPTURE 0x04 /* freeze capture */ 305 #define VFAC_CTL1_FREEZE_CAPTURE_SYNC 0x08 /* sync freeze capture */ 306 #define VFAC_CTL1_VALIDFRAME_SRC 0x10 /* select valid frame source */ 307 #define VFAC_CTL1_PHILIPS 0x40 /* select Philips mode */ 308 #define VFAC_CTL1_MODVINTERPOLCLK 0x80 /* modify vertical interpolation clocl */ 309 310 #define VFAC_CTL2 0xe9 311 #define VFAC_CTL2_INVERT_VIDDATAVALID 0x01 /* invert video data valid */ 312 #define VFAC_CTL2_INVERT_GRAPHREADY 0x02 /* invert graphic ready output sig */ 313 #define VFAC_CTL2_INVERT_DATACLK 0x04 /* invert data clock signal */ 314 #define VFAC_CTL2_INVERT_HSYNC 0x08 /* invert hsync input */ 315 #define VFAC_CTL2_INVERT_VSYNC 0x10 /* invert vsync input */ 316 #define VFAC_CTL2_INVERT_FRAME 0x20 /* invert frame odd/even input */ 317 #define VFAC_CTL2_INVERT_BLANK 0x40 /* invert blank output */ 318 #define VFAC_CTL2_INVERT_OVSYNC 0x80 /* invert other vsync input */ 319 320 #define VFAC_CTL3 0xea 321 #define VFAC_CTL3_CAP_LARGE_FIFO 0x01 /* large capture fifo */ 322 #define VFAC_CTL3_CAP_INTERLACE 0x02 /* capture odd and even fields */ 323 #define VFAC_CTL3_CAP_HOLD_4NS 0x00 /* hold capture data for 4ns */ 324 #define VFAC_CTL3_CAP_HOLD_2NS 0x04 /* hold capture data for 2ns */ 325 #define VFAC_CTL3_CAP_HOLD_6NS 0x08 /* hold capture data for 6ns */ 326 #define VFAC_CTL3_CAP_HOLD_0NS 0x0c /* hold capture data for 0ns */ 327 #define VFAC_CTL3_CHROMAKEY 0x20 /* capture data will be chromakeyed */ 328 #define VFAC_CTL3_CAP_IRQ 0x40 /* enable capture interrupt */ 329 330 #define CAP_MEM_START 0xeb /* 18 bits */ 331 #define CAP_MAP_WIDTH 0xed /* high 6 bits */ 332 #define CAP_PITCH 0xee /* 8 bits */ 333 334 #define CAP_CTL_MISC 0xef 335 #define CAP_CTL_MISC_HDIV 0x01 336 #define CAP_CTL_MISC_HDIV4 0x02 337 #define CAP_CTL_MISC_ODDEVEN 0x04 338 #define CAP_CTL_MISC_HSYNCDIV2 0x08 339 #define CAP_CTL_MISC_SYNCTZHIGH 0x10 340 #define CAP_CTL_MISC_SYNCTZOR 0x20 341 #define CAP_CTL_MISC_DISPUSED 0x80 342 343 #define REG_BANK 0xfa 344 #define REG_BANK_X 0x00 345 #define REG_BANK_Y 0x01 346 #define REG_BANK_W 0x02 347 #define REG_BANK_T 0x03 348 #define REG_BANK_J 0x04 349 #define REG_BANK_K 0x05 350 351 /* 352 * Bus-master 353 */ 354 #define BM_VID_ADDR_LOW 0xbc040 355 #define BM_VID_ADDR_HIGH 0xbc044 356 #define BM_ADDRESS_LOW 0xbc080 357 #define BM_ADDRESS_HIGH 0xbc084 358 #define BM_LENGTH 0xbc088 359 #define BM_CONTROL 0xbc08c 360 #define BM_CONTROL_ENABLE 0x01 /* enable transfer */ 361 #define BM_CONTROL_IRQEN 0x02 /* enable IRQ at end of transfer */ 362 #define BM_CONTROL_INIT 0x04 /* initialise status & count */ 363 #define BM_COUNT 0xbc090 /* read-only */ 364 365 /* 366 * TV registers 367 */ 368 #define TV_VBLANK_EVEN_START 0xbe43c 369 #define TV_VBLANK_EVEN_END 0xbe440 370 #define TV_VBLANK_ODD_START 0xbe444 371 #define TV_VBLANK_ODD_END 0xbe448 372 #define TV_SYNC_YGAIN 0xbe44c 373 #define TV_UV_GAIN 0xbe450 374 #define TV_PED_UVDET 0xbe454 375 #define TV_UV_BURST_AMP 0xbe458 376 #define TV_HSYNC_START 0xbe45c 377 #define TV_HSYNC_END 0xbe460 378 #define TV_Y_DELAY1 0xbe464 379 #define TV_Y_DELAY2 0xbe468 380 #define TV_UV_DELAY1 0xbe46c 381 #define TV_BURST_START 0xbe470 382 #define TV_BURST_END 0xbe474 383 #define TV_HBLANK_START 0xbe478 384 #define TV_HBLANK_END 0xbe47c 385 #define TV_PED_EVEN_START 0xbe480 386 #define TV_PED_EVEN_END 0xbe484 387 #define TV_PED_ODD_START 0xbe488 388 #define TV_PED_ODD_END 0xbe48c 389 #define TV_VSYNC_EVEN_START 0xbe490 390 #define TV_VSYNC_EVEN_END 0xbe494 391 #define TV_VSYNC_ODD_START 0xbe498 392 #define TV_VSYNC_ODD_END 0xbe49c 393 #define TV_SCFL 0xbe4a0 394 #define TV_SCFH 0xbe4a4 395 #define TV_SCP 0xbe4a8 396 #define TV_DELAYBYPASS 0xbe4b4 397 #define TV_EQL_END 0xbe4bc 398 #define TV_SERR_START 0xbe4c0 399 #define TV_SERR_END 0xbe4c4 400 #define TV_CTL 0xbe4dc /* reflects a previous register- MVFCLR, MVPCLR etc P241*/ 401 #define TV_VSYNC_VGA_HS 0xbe4e8 402 #define TV_FLICK_XMIN 0xbe514 403 #define TV_FLICK_XMAX 0xbe518 404 #define TV_FLICK_YMIN 0xbe51c 405 #define TV_FLICK_YMAX 0xbe520 406 407 /* 408 * Graphics Co-processor 409 */ 410 #define CO_REG_CONTROL 0xbf011 411 #define CO_CTRL_BUSY 0x80 412 #define CO_CTRL_CMDFULL 0x04 413 #define CO_CTRL_FIFOEMPTY 0x02 414 #define CO_CTRL_READY 0x01 415 416 #define CO_REG_SRC_WIDTH 0xbf018 417 #define CO_REG_PIXFMT 0xbf01c 418 #define CO_PIXFMT_32BPP 0x03 419 #define CO_PIXFMT_24BPP 0x02 420 #define CO_PIXFMT_16BPP 0x01 421 #define CO_PIXFMT_8BPP 0x00 422 423 #define CO_REG_FGMIX 0xbf048 424 #define CO_FG_MIX_ZERO 0x00 425 #define CO_FG_MIX_SRC_AND_DST 0x01 426 #define CO_FG_MIX_SRC_AND_NDST 0x02 427 #define CO_FG_MIX_SRC 0x03 428 #define CO_FG_MIX_NSRC_AND_DST 0x04 429 #define CO_FG_MIX_DST 0x05 430 #define CO_FG_MIX_SRC_XOR_DST 0x06 431 #define CO_FG_MIX_SRC_OR_DST 0x07 432 #define CO_FG_MIX_NSRC_AND_NDST 0x08 433 #define CO_FG_MIX_SRC_XOR_NDST 0x09 434 #define CO_FG_MIX_NDST 0x0a 435 #define CO_FG_MIX_SRC_OR_NDST 0x0b 436 #define CO_FG_MIX_NSRC 0x0c 437 #define CO_FG_MIX_NSRC_OR_DST 0x0d 438 #define CO_FG_MIX_NSRC_OR_NDST 0x0e 439 #define CO_FG_MIX_ONES 0x0f 440 441 #define CO_REG_FGCOLOUR 0xbf058 442 #define CO_REG_BGCOLOUR 0xbf05c 443 #define CO_REG_PIXWIDTH 0xbf060 444 #define CO_REG_PIXHEIGHT 0xbf062 445 #define CO_REG_X_PHASE 0xbf078 446 #define CO_REG_CMD_L 0xbf07c 447 #define CO_CMD_L_PATTERN_FGCOL 0x8000 448 #define CO_CMD_L_INC_LEFT 0x0004 449 #define CO_CMD_L_INC_UP 0x0002 450 451 #define CO_REG_CMD_H 0xbf07e 452 #define CO_CMD_H_BGSRCMAP 0x8000 /* otherwise bg colour */ 453 #define CO_CMD_H_FGSRCMAP 0x2000 /* otherwise fg colour */ 454 #define CO_CMD_H_BLITTER 0x0800 455 456 #define CO_REG_SRC1_PTR 0xbf170 457 #define CO_REG_SRC2_PTR 0xbf174 458 #define CO_REG_DEST_PTR 0xbf178 459 #define CO_REG_DEST_WIDTH 0xbf218 460 461 /* 462 * Private structure 463 */ 464 struct cfb_info; 465 466 struct cyberpro_info { 467 struct device *dev; 468 struct i2c_adapter *i2c; 469 unsigned char __iomem *regs; 470 char __iomem *fb; 471 char dev_name[32]; 472 unsigned int fb_size; 473 unsigned int chip_id; 474 unsigned int irq; 475 476 /* 477 * The following is a pointer to be passed into the 478 * functions below. The modules outside the main 479 * cyber2000fb.c driver have no knowledge as to what 480 * is within this structure. 481 */ 482 struct cfb_info *info; 483 }; 484 485 #define ID_IGA_1682 0 486 #define ID_CYBERPRO_2000 1 487 #define ID_CYBERPRO_2010 2 488 #define ID_CYBERPRO_5000 3 489 490 /* 491 * Note! Writing to the Cyber20x0 registers from an interrupt 492 * routine is definitely a bad idea atm. 493 */ 494 int cyber2000fb_attach(struct cyberpro_info *info, int idx); 495 void cyber2000fb_detach(int idx); 496 void cyber2000fb_enable_extregs(struct cfb_info *cfb); 497 void cyber2000fb_disable_extregs(struct cfb_info *cfb); 498