1 /* 2 * linux/drivers/video/cyber2000fb.c 3 * 4 * Copyright (C) 1998-2002 Russell King 5 * 6 * MIPS and 50xx clock support 7 * Copyright (C) 2001 Bradley D. LaRonde <brad@ltc.com> 8 * 9 * 32 bit support, text color and panning fixes for modes != 8 bit 10 * Copyright (C) 2002 Denis Oliver Kropp <dok@directfb.org> 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of the GNU General Public License version 2 as 14 * published by the Free Software Foundation. 15 * 16 * Integraphics CyberPro 2000, 2010 and 5000 frame buffer device 17 * 18 * Based on cyberfb.c. 19 * 20 * Note that we now use the new fbcon fix, var and cmap scheme. We do 21 * still have to check which console is the currently displayed one 22 * however, especially for the colourmap stuff. 23 * 24 * We also use the new hotplug PCI subsystem. I'm not sure if there 25 * are any such cards, but I'm erring on the side of caution. We don't 26 * want to go pop just because someone does have one. 27 * 28 * Note that this doesn't work fully in the case of multiple CyberPro 29 * cards with grabbers. We currently can only attach to the first 30 * CyberPro card found. 31 * 32 * When we're in truecolour mode, we power down the LUT RAM as a power 33 * saving feature. Also, when we enter any of the powersaving modes 34 * (except soft blanking) we power down the RAMDACs. This saves about 35 * 1W, which is roughly 8% of the power consumption of a NetWinder 36 * (which, incidentally, is about the same saving as a 2.5in hard disk 37 * entering standby mode.) 38 */ 39 #include <linux/module.h> 40 #include <linux/kernel.h> 41 #include <linux/errno.h> 42 #include <linux/string.h> 43 #include <linux/mm.h> 44 #include <linux/slab.h> 45 #include <linux/delay.h> 46 #include <linux/fb.h> 47 #include <linux/pci.h> 48 #include <linux/init.h> 49 #include <linux/io.h> 50 #include <linux/i2c.h> 51 #include <linux/i2c-algo-bit.h> 52 53 #include <asm/pgtable.h> 54 55 #ifdef __arm__ 56 #include <asm/mach-types.h> 57 #endif 58 59 #include "cyber2000fb.h" 60 61 struct cfb_info { 62 struct fb_info fb; 63 struct display_switch *dispsw; 64 unsigned char __iomem *region; 65 unsigned char __iomem *regs; 66 u_int id; 67 u_int irq; 68 int func_use_count; 69 u_long ref_ps; 70 71 /* 72 * Clock divisors 73 */ 74 u_int divisors[4]; 75 76 struct { 77 u8 red, green, blue; 78 } palette[NR_PALETTE]; 79 80 u_char mem_ctl1; 81 u_char mem_ctl2; 82 u_char mclk_mult; 83 u_char mclk_div; 84 /* 85 * RAMDAC control register is both of these or'ed together 86 */ 87 u_char ramdac_ctrl; 88 u_char ramdac_powerdown; 89 90 u32 pseudo_palette[16]; 91 92 spinlock_t reg_b0_lock; 93 94 #ifdef CONFIG_FB_CYBER2000_DDC 95 bool ddc_registered; 96 struct i2c_adapter ddc_adapter; 97 struct i2c_algo_bit_data ddc_algo; 98 #endif 99 100 #ifdef CONFIG_FB_CYBER2000_I2C 101 struct i2c_adapter i2c_adapter; 102 struct i2c_algo_bit_data i2c_algo; 103 #endif 104 }; 105 106 static char *default_font = "Acorn8x8"; 107 module_param(default_font, charp, 0); 108 MODULE_PARM_DESC(default_font, "Default font name"); 109 110 /* 111 * Our access methods. 112 */ 113 #define cyber2000fb_writel(val, reg, cfb) writel(val, (cfb)->regs + (reg)) 114 #define cyber2000fb_writew(val, reg, cfb) writew(val, (cfb)->regs + (reg)) 115 #define cyber2000fb_writeb(val, reg, cfb) writeb(val, (cfb)->regs + (reg)) 116 117 #define cyber2000fb_readb(reg, cfb) readb((cfb)->regs + (reg)) 118 119 static inline void 120 cyber2000_crtcw(unsigned int reg, unsigned int val, struct cfb_info *cfb) 121 { 122 cyber2000fb_writew((reg & 255) | val << 8, 0x3d4, cfb); 123 } 124 125 static inline void 126 cyber2000_grphw(unsigned int reg, unsigned int val, struct cfb_info *cfb) 127 { 128 cyber2000fb_writew((reg & 255) | val << 8, 0x3ce, cfb); 129 } 130 131 static inline unsigned int 132 cyber2000_grphr(unsigned int reg, struct cfb_info *cfb) 133 { 134 cyber2000fb_writeb(reg, 0x3ce, cfb); 135 return cyber2000fb_readb(0x3cf, cfb); 136 } 137 138 static inline void 139 cyber2000_attrw(unsigned int reg, unsigned int val, struct cfb_info *cfb) 140 { 141 cyber2000fb_readb(0x3da, cfb); 142 cyber2000fb_writeb(reg, 0x3c0, cfb); 143 cyber2000fb_readb(0x3c1, cfb); 144 cyber2000fb_writeb(val, 0x3c0, cfb); 145 } 146 147 static inline void 148 cyber2000_seqw(unsigned int reg, unsigned int val, struct cfb_info *cfb) 149 { 150 cyber2000fb_writew((reg & 255) | val << 8, 0x3c4, cfb); 151 } 152 153 /* -------------------- Hardware specific routines ------------------------- */ 154 155 /* 156 * Hardware Cyber2000 Acceleration 157 */ 158 static void 159 cyber2000fb_fillrect(struct fb_info *info, const struct fb_fillrect *rect) 160 { 161 struct cfb_info *cfb = container_of(info, struct cfb_info, fb); 162 unsigned long dst, col; 163 164 if (!(cfb->fb.var.accel_flags & FB_ACCELF_TEXT)) { 165 cfb_fillrect(info, rect); 166 return; 167 } 168 169 cyber2000fb_writeb(0, CO_REG_CONTROL, cfb); 170 cyber2000fb_writew(rect->width - 1, CO_REG_PIXWIDTH, cfb); 171 cyber2000fb_writew(rect->height - 1, CO_REG_PIXHEIGHT, cfb); 172 173 col = rect->color; 174 if (cfb->fb.var.bits_per_pixel > 8) 175 col = ((u32 *)cfb->fb.pseudo_palette)[col]; 176 cyber2000fb_writel(col, CO_REG_FGCOLOUR, cfb); 177 178 dst = rect->dx + rect->dy * cfb->fb.var.xres_virtual; 179 if (cfb->fb.var.bits_per_pixel == 24) { 180 cyber2000fb_writeb(dst, CO_REG_X_PHASE, cfb); 181 dst *= 3; 182 } 183 184 cyber2000fb_writel(dst, CO_REG_DEST_PTR, cfb); 185 cyber2000fb_writeb(CO_FG_MIX_SRC, CO_REG_FGMIX, cfb); 186 cyber2000fb_writew(CO_CMD_L_PATTERN_FGCOL, CO_REG_CMD_L, cfb); 187 cyber2000fb_writew(CO_CMD_H_BLITTER, CO_REG_CMD_H, cfb); 188 } 189 190 static void 191 cyber2000fb_copyarea(struct fb_info *info, const struct fb_copyarea *region) 192 { 193 struct cfb_info *cfb = container_of(info, struct cfb_info, fb); 194 unsigned int cmd = CO_CMD_L_PATTERN_FGCOL; 195 unsigned long src, dst; 196 197 if (!(cfb->fb.var.accel_flags & FB_ACCELF_TEXT)) { 198 cfb_copyarea(info, region); 199 return; 200 } 201 202 cyber2000fb_writeb(0, CO_REG_CONTROL, cfb); 203 cyber2000fb_writew(region->width - 1, CO_REG_PIXWIDTH, cfb); 204 cyber2000fb_writew(region->height - 1, CO_REG_PIXHEIGHT, cfb); 205 206 src = region->sx + region->sy * cfb->fb.var.xres_virtual; 207 dst = region->dx + region->dy * cfb->fb.var.xres_virtual; 208 209 if (region->sx < region->dx) { 210 src += region->width - 1; 211 dst += region->width - 1; 212 cmd |= CO_CMD_L_INC_LEFT; 213 } 214 215 if (region->sy < region->dy) { 216 src += (region->height - 1) * cfb->fb.var.xres_virtual; 217 dst += (region->height - 1) * cfb->fb.var.xres_virtual; 218 cmd |= CO_CMD_L_INC_UP; 219 } 220 221 if (cfb->fb.var.bits_per_pixel == 24) { 222 cyber2000fb_writeb(dst, CO_REG_X_PHASE, cfb); 223 src *= 3; 224 dst *= 3; 225 } 226 cyber2000fb_writel(src, CO_REG_SRC1_PTR, cfb); 227 cyber2000fb_writel(dst, CO_REG_DEST_PTR, cfb); 228 cyber2000fb_writew(CO_FG_MIX_SRC, CO_REG_FGMIX, cfb); 229 cyber2000fb_writew(cmd, CO_REG_CMD_L, cfb); 230 cyber2000fb_writew(CO_CMD_H_FGSRCMAP | CO_CMD_H_BLITTER, 231 CO_REG_CMD_H, cfb); 232 } 233 234 static void 235 cyber2000fb_imageblit(struct fb_info *info, const struct fb_image *image) 236 { 237 cfb_imageblit(info, image); 238 return; 239 } 240 241 static int cyber2000fb_sync(struct fb_info *info) 242 { 243 struct cfb_info *cfb = container_of(info, struct cfb_info, fb); 244 int count = 100000; 245 246 if (!(cfb->fb.var.accel_flags & FB_ACCELF_TEXT)) 247 return 0; 248 249 while (cyber2000fb_readb(CO_REG_CONTROL, cfb) & CO_CTRL_BUSY) { 250 if (!count--) { 251 debug_printf("accel_wait timed out\n"); 252 cyber2000fb_writeb(0, CO_REG_CONTROL, cfb); 253 break; 254 } 255 udelay(1); 256 } 257 return 0; 258 } 259 260 /* 261 * =========================================================================== 262 */ 263 264 static inline u32 convert_bitfield(u_int val, struct fb_bitfield *bf) 265 { 266 u_int mask = (1 << bf->length) - 1; 267 268 return (val >> (16 - bf->length) & mask) << bf->offset; 269 } 270 271 /* 272 * Set a single color register. Return != 0 for invalid regno. 273 */ 274 static int 275 cyber2000fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, 276 u_int transp, struct fb_info *info) 277 { 278 struct cfb_info *cfb = container_of(info, struct cfb_info, fb); 279 struct fb_var_screeninfo *var = &cfb->fb.var; 280 u32 pseudo_val; 281 int ret = 1; 282 283 switch (cfb->fb.fix.visual) { 284 default: 285 return 1; 286 287 /* 288 * Pseudocolour: 289 * 8 8 290 * pixel --/--+--/--> red lut --> red dac 291 * | 8 292 * +--/--> green lut --> green dac 293 * | 8 294 * +--/--> blue lut --> blue dac 295 */ 296 case FB_VISUAL_PSEUDOCOLOR: 297 if (regno >= NR_PALETTE) 298 return 1; 299 300 red >>= 8; 301 green >>= 8; 302 blue >>= 8; 303 304 cfb->palette[regno].red = red; 305 cfb->palette[regno].green = green; 306 cfb->palette[regno].blue = blue; 307 308 cyber2000fb_writeb(regno, 0x3c8, cfb); 309 cyber2000fb_writeb(red, 0x3c9, cfb); 310 cyber2000fb_writeb(green, 0x3c9, cfb); 311 cyber2000fb_writeb(blue, 0x3c9, cfb); 312 return 0; 313 314 /* 315 * Direct colour: 316 * n rl 317 * pixel --/--+--/--> red lut --> red dac 318 * | gl 319 * +--/--> green lut --> green dac 320 * | bl 321 * +--/--> blue lut --> blue dac 322 * n = bpp, rl = red length, gl = green length, bl = blue length 323 */ 324 case FB_VISUAL_DIRECTCOLOR: 325 red >>= 8; 326 green >>= 8; 327 blue >>= 8; 328 329 if (var->green.length == 6 && regno < 64) { 330 cfb->palette[regno << 2].green = green; 331 332 /* 333 * The 6 bits of the green component are applied 334 * to the high 6 bits of the LUT. 335 */ 336 cyber2000fb_writeb(regno << 2, 0x3c8, cfb); 337 cyber2000fb_writeb(cfb->palette[regno >> 1].red, 338 0x3c9, cfb); 339 cyber2000fb_writeb(green, 0x3c9, cfb); 340 cyber2000fb_writeb(cfb->palette[regno >> 1].blue, 341 0x3c9, cfb); 342 343 green = cfb->palette[regno << 3].green; 344 345 ret = 0; 346 } 347 348 if (var->green.length >= 5 && regno < 32) { 349 cfb->palette[regno << 3].red = red; 350 cfb->palette[regno << 3].green = green; 351 cfb->palette[regno << 3].blue = blue; 352 353 /* 354 * The 5 bits of each colour component are 355 * applied to the high 5 bits of the LUT. 356 */ 357 cyber2000fb_writeb(regno << 3, 0x3c8, cfb); 358 cyber2000fb_writeb(red, 0x3c9, cfb); 359 cyber2000fb_writeb(green, 0x3c9, cfb); 360 cyber2000fb_writeb(blue, 0x3c9, cfb); 361 ret = 0; 362 } 363 364 if (var->green.length == 4 && regno < 16) { 365 cfb->palette[regno << 4].red = red; 366 cfb->palette[regno << 4].green = green; 367 cfb->palette[regno << 4].blue = blue; 368 369 /* 370 * The 5 bits of each colour component are 371 * applied to the high 5 bits of the LUT. 372 */ 373 cyber2000fb_writeb(regno << 4, 0x3c8, cfb); 374 cyber2000fb_writeb(red, 0x3c9, cfb); 375 cyber2000fb_writeb(green, 0x3c9, cfb); 376 cyber2000fb_writeb(blue, 0x3c9, cfb); 377 ret = 0; 378 } 379 380 /* 381 * Since this is only used for the first 16 colours, we 382 * don't have to care about overflowing for regno >= 32 383 */ 384 pseudo_val = regno << var->red.offset | 385 regno << var->green.offset | 386 regno << var->blue.offset; 387 break; 388 389 /* 390 * True colour: 391 * n rl 392 * pixel --/--+--/--> red dac 393 * | gl 394 * +--/--> green dac 395 * | bl 396 * +--/--> blue dac 397 * n = bpp, rl = red length, gl = green length, bl = blue length 398 */ 399 case FB_VISUAL_TRUECOLOR: 400 pseudo_val = convert_bitfield(transp ^ 0xffff, &var->transp); 401 pseudo_val |= convert_bitfield(red, &var->red); 402 pseudo_val |= convert_bitfield(green, &var->green); 403 pseudo_val |= convert_bitfield(blue, &var->blue); 404 ret = 0; 405 break; 406 } 407 408 /* 409 * Now set our pseudo palette for the CFB16/24/32 drivers. 410 */ 411 if (regno < 16) 412 ((u32 *)cfb->fb.pseudo_palette)[regno] = pseudo_val; 413 414 return ret; 415 } 416 417 struct par_info { 418 /* 419 * Hardware 420 */ 421 u_char clock_mult; 422 u_char clock_div; 423 u_char extseqmisc; 424 u_char co_pixfmt; 425 u_char crtc_ofl; 426 u_char crtc[19]; 427 u_int width; 428 u_int pitch; 429 u_int fetch; 430 431 /* 432 * Other 433 */ 434 u_char ramdac; 435 }; 436 437 static const u_char crtc_idx[] = { 438 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 439 0x08, 0x09, 440 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18 441 }; 442 443 static void cyber2000fb_write_ramdac_ctrl(struct cfb_info *cfb) 444 { 445 unsigned int i; 446 unsigned int val = cfb->ramdac_ctrl | cfb->ramdac_powerdown; 447 448 cyber2000fb_writeb(0x56, 0x3ce, cfb); 449 i = cyber2000fb_readb(0x3cf, cfb); 450 cyber2000fb_writeb(i | 4, 0x3cf, cfb); 451 cyber2000fb_writeb(val, 0x3c6, cfb); 452 cyber2000fb_writeb(i, 0x3cf, cfb); 453 /* prevent card lock-up observed on x86 with CyberPro 2000 */ 454 cyber2000fb_readb(0x3cf, cfb); 455 } 456 457 static void cyber2000fb_set_timing(struct cfb_info *cfb, struct par_info *hw) 458 { 459 u_int i; 460 461 /* 462 * Blank palette 463 */ 464 for (i = 0; i < NR_PALETTE; i++) { 465 cyber2000fb_writeb(i, 0x3c8, cfb); 466 cyber2000fb_writeb(0, 0x3c9, cfb); 467 cyber2000fb_writeb(0, 0x3c9, cfb); 468 cyber2000fb_writeb(0, 0x3c9, cfb); 469 } 470 471 cyber2000fb_writeb(0xef, 0x3c2, cfb); 472 cyber2000_crtcw(0x11, 0x0b, cfb); 473 cyber2000_attrw(0x11, 0x00, cfb); 474 475 cyber2000_seqw(0x00, 0x01, cfb); 476 cyber2000_seqw(0x01, 0x01, cfb); 477 cyber2000_seqw(0x02, 0x0f, cfb); 478 cyber2000_seqw(0x03, 0x00, cfb); 479 cyber2000_seqw(0x04, 0x0e, cfb); 480 cyber2000_seqw(0x00, 0x03, cfb); 481 482 for (i = 0; i < sizeof(crtc_idx); i++) 483 cyber2000_crtcw(crtc_idx[i], hw->crtc[i], cfb); 484 485 for (i = 0x0a; i < 0x10; i++) 486 cyber2000_crtcw(i, 0, cfb); 487 488 cyber2000_grphw(EXT_CRT_VRTOFL, hw->crtc_ofl, cfb); 489 cyber2000_grphw(0x00, 0x00, cfb); 490 cyber2000_grphw(0x01, 0x00, cfb); 491 cyber2000_grphw(0x02, 0x00, cfb); 492 cyber2000_grphw(0x03, 0x00, cfb); 493 cyber2000_grphw(0x04, 0x00, cfb); 494 cyber2000_grphw(0x05, 0x60, cfb); 495 cyber2000_grphw(0x06, 0x05, cfb); 496 cyber2000_grphw(0x07, 0x0f, cfb); 497 cyber2000_grphw(0x08, 0xff, cfb); 498 499 /* Attribute controller registers */ 500 for (i = 0; i < 16; i++) 501 cyber2000_attrw(i, i, cfb); 502 503 cyber2000_attrw(0x10, 0x01, cfb); 504 cyber2000_attrw(0x11, 0x00, cfb); 505 cyber2000_attrw(0x12, 0x0f, cfb); 506 cyber2000_attrw(0x13, 0x00, cfb); 507 cyber2000_attrw(0x14, 0x00, cfb); 508 509 /* PLL registers */ 510 spin_lock(&cfb->reg_b0_lock); 511 cyber2000_grphw(EXT_DCLK_MULT, hw->clock_mult, cfb); 512 cyber2000_grphw(EXT_DCLK_DIV, hw->clock_div, cfb); 513 cyber2000_grphw(EXT_MCLK_MULT, cfb->mclk_mult, cfb); 514 cyber2000_grphw(EXT_MCLK_DIV, cfb->mclk_div, cfb); 515 cyber2000_grphw(0x90, 0x01, cfb); 516 cyber2000_grphw(0xb9, 0x80, cfb); 517 cyber2000_grphw(0xb9, 0x00, cfb); 518 spin_unlock(&cfb->reg_b0_lock); 519 520 cfb->ramdac_ctrl = hw->ramdac; 521 cyber2000fb_write_ramdac_ctrl(cfb); 522 523 cyber2000fb_writeb(0x20, 0x3c0, cfb); 524 cyber2000fb_writeb(0xff, 0x3c6, cfb); 525 526 cyber2000_grphw(0x14, hw->fetch, cfb); 527 cyber2000_grphw(0x15, ((hw->fetch >> 8) & 0x03) | 528 ((hw->pitch >> 4) & 0x30), cfb); 529 cyber2000_grphw(EXT_SEQ_MISC, hw->extseqmisc, cfb); 530 531 /* 532 * Set up accelerator registers 533 */ 534 cyber2000fb_writew(hw->width, CO_REG_SRC_WIDTH, cfb); 535 cyber2000fb_writew(hw->width, CO_REG_DEST_WIDTH, cfb); 536 cyber2000fb_writeb(hw->co_pixfmt, CO_REG_PIXFMT, cfb); 537 } 538 539 static inline int 540 cyber2000fb_update_start(struct cfb_info *cfb, struct fb_var_screeninfo *var) 541 { 542 u_int base = var->yoffset * var->xres_virtual + var->xoffset; 543 544 base *= var->bits_per_pixel; 545 546 /* 547 * Convert to bytes and shift two extra bits because DAC 548 * can only start on 4 byte aligned data. 549 */ 550 base >>= 5; 551 552 if (base >= 1 << 20) 553 return -EINVAL; 554 555 cyber2000_grphw(0x10, base >> 16 | 0x10, cfb); 556 cyber2000_crtcw(0x0c, base >> 8, cfb); 557 cyber2000_crtcw(0x0d, base, cfb); 558 559 return 0; 560 } 561 562 static int 563 cyber2000fb_decode_crtc(struct par_info *hw, struct cfb_info *cfb, 564 struct fb_var_screeninfo *var) 565 { 566 u_int Htotal, Hblankend, Hsyncend; 567 u_int Vtotal, Vdispend, Vblankstart, Vblankend, Vsyncstart, Vsyncend; 568 #define ENCODE_BIT(v, b1, m, b2) ((((v) >> (b1)) & (m)) << (b2)) 569 570 hw->crtc[13] = hw->pitch; 571 hw->crtc[17] = 0xe3; 572 hw->crtc[14] = 0; 573 hw->crtc[8] = 0; 574 575 Htotal = var->xres + var->right_margin + 576 var->hsync_len + var->left_margin; 577 578 if (Htotal > 2080) 579 return -EINVAL; 580 581 hw->crtc[0] = (Htotal >> 3) - 5; 582 hw->crtc[1] = (var->xres >> 3) - 1; 583 hw->crtc[2] = var->xres >> 3; 584 hw->crtc[4] = (var->xres + var->right_margin) >> 3; 585 586 Hblankend = (Htotal - 4 * 8) >> 3; 587 588 hw->crtc[3] = ENCODE_BIT(Hblankend, 0, 0x1f, 0) | 589 ENCODE_BIT(1, 0, 0x01, 7); 590 591 Hsyncend = (var->xres + var->right_margin + var->hsync_len) >> 3; 592 593 hw->crtc[5] = ENCODE_BIT(Hsyncend, 0, 0x1f, 0) | 594 ENCODE_BIT(Hblankend, 5, 0x01, 7); 595 596 Vdispend = var->yres - 1; 597 Vsyncstart = var->yres + var->lower_margin; 598 Vsyncend = var->yres + var->lower_margin + var->vsync_len; 599 Vtotal = var->yres + var->lower_margin + var->vsync_len + 600 var->upper_margin - 2; 601 602 if (Vtotal > 2047) 603 return -EINVAL; 604 605 Vblankstart = var->yres + 6; 606 Vblankend = Vtotal - 10; 607 608 hw->crtc[6] = Vtotal; 609 hw->crtc[7] = ENCODE_BIT(Vtotal, 8, 0x01, 0) | 610 ENCODE_BIT(Vdispend, 8, 0x01, 1) | 611 ENCODE_BIT(Vsyncstart, 8, 0x01, 2) | 612 ENCODE_BIT(Vblankstart, 8, 0x01, 3) | 613 ENCODE_BIT(1, 0, 0x01, 4) | 614 ENCODE_BIT(Vtotal, 9, 0x01, 5) | 615 ENCODE_BIT(Vdispend, 9, 0x01, 6) | 616 ENCODE_BIT(Vsyncstart, 9, 0x01, 7); 617 hw->crtc[9] = ENCODE_BIT(0, 0, 0x1f, 0) | 618 ENCODE_BIT(Vblankstart, 9, 0x01, 5) | 619 ENCODE_BIT(1, 0, 0x01, 6); 620 hw->crtc[10] = Vsyncstart; 621 hw->crtc[11] = ENCODE_BIT(Vsyncend, 0, 0x0f, 0) | 622 ENCODE_BIT(1, 0, 0x01, 7); 623 hw->crtc[12] = Vdispend; 624 hw->crtc[15] = Vblankstart; 625 hw->crtc[16] = Vblankend; 626 hw->crtc[18] = 0xff; 627 628 /* 629 * overflow - graphics reg 0x11 630 * 0=VTOTAL:10 1=VDEND:10 2=VRSTART:10 3=VBSTART:10 631 * 4=LINECOMP:10 5-IVIDEO 6=FIXCNT 632 */ 633 hw->crtc_ofl = 634 ENCODE_BIT(Vtotal, 10, 0x01, 0) | 635 ENCODE_BIT(Vdispend, 10, 0x01, 1) | 636 ENCODE_BIT(Vsyncstart, 10, 0x01, 2) | 637 ENCODE_BIT(Vblankstart, 10, 0x01, 3) | 638 EXT_CRT_VRTOFL_LINECOMP10; 639 640 /* woody: set the interlaced bit... */ 641 /* FIXME: what about doublescan? */ 642 if ((var->vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) 643 hw->crtc_ofl |= EXT_CRT_VRTOFL_INTERLACE; 644 645 return 0; 646 } 647 648 /* 649 * The following was discovered by a good monitor, bit twiddling, theorising 650 * and but mostly luck. Strangely, it looks like everyone elses' PLL! 651 * 652 * Clock registers: 653 * fclock = fpll / div2 654 * fpll = fref * mult / div1 655 * where: 656 * fref = 14.318MHz (69842ps) 657 * mult = reg0xb0.7:0 658 * div1 = (reg0xb1.5:0 + 1) 659 * div2 = 2^(reg0xb1.7:6) 660 * fpll should be between 115 and 260 MHz 661 * (8696ps and 3846ps) 662 */ 663 static int 664 cyber2000fb_decode_clock(struct par_info *hw, struct cfb_info *cfb, 665 struct fb_var_screeninfo *var) 666 { 667 u_long pll_ps = var->pixclock; 668 const u_long ref_ps = cfb->ref_ps; 669 u_int div2, t_div1, best_div1, best_mult; 670 int best_diff; 671 int vco; 672 673 /* 674 * Step 1: 675 * find div2 such that 115MHz < fpll < 260MHz 676 * and 0 <= div2 < 4 677 */ 678 for (div2 = 0; div2 < 4; div2++) { 679 u_long new_pll; 680 681 new_pll = pll_ps / cfb->divisors[div2]; 682 if (8696 > new_pll && new_pll > 3846) { 683 pll_ps = new_pll; 684 break; 685 } 686 } 687 688 if (div2 == 4) 689 return -EINVAL; 690 691 /* 692 * Step 2: 693 * Given pll_ps and ref_ps, find: 694 * pll_ps * 0.995 < pll_ps_calc < pll_ps * 1.005 695 * where { 1 < best_div1 < 32, 1 < best_mult < 256 } 696 * pll_ps_calc = best_div1 / (ref_ps * best_mult) 697 */ 698 best_diff = 0x7fffffff; 699 best_mult = 2; 700 best_div1 = 32; 701 for (t_div1 = 2; t_div1 < 32; t_div1 += 1) { 702 u_int rr, t_mult, t_pll_ps; 703 int diff; 704 705 /* 706 * Find the multiplier for this divisor 707 */ 708 rr = ref_ps * t_div1; 709 t_mult = (rr + pll_ps / 2) / pll_ps; 710 711 /* 712 * Is the multiplier within the correct range? 713 */ 714 if (t_mult > 256 || t_mult < 2) 715 continue; 716 717 /* 718 * Calculate the actual clock period from this multiplier 719 * and divisor, and estimate the error. 720 */ 721 t_pll_ps = (rr + t_mult / 2) / t_mult; 722 diff = pll_ps - t_pll_ps; 723 if (diff < 0) 724 diff = -diff; 725 726 if (diff < best_diff) { 727 best_diff = diff; 728 best_mult = t_mult; 729 best_div1 = t_div1; 730 } 731 732 /* 733 * If we hit an exact value, there is no point in continuing. 734 */ 735 if (diff == 0) 736 break; 737 } 738 739 /* 740 * Step 3: 741 * combine values 742 */ 743 hw->clock_mult = best_mult - 1; 744 hw->clock_div = div2 << 6 | (best_div1 - 1); 745 746 vco = ref_ps * best_div1 / best_mult; 747 if ((ref_ps == 40690) && (vco < 5556)) 748 /* Set VFSEL when VCO > 180MHz (5.556 ps). */ 749 hw->clock_div |= EXT_DCLK_DIV_VFSEL; 750 751 return 0; 752 } 753 754 /* 755 * Set the User Defined Part of the Display 756 */ 757 static int 758 cyber2000fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) 759 { 760 struct cfb_info *cfb = container_of(info, struct cfb_info, fb); 761 struct par_info hw; 762 unsigned int mem; 763 int err; 764 765 var->transp.msb_right = 0; 766 var->red.msb_right = 0; 767 var->green.msb_right = 0; 768 var->blue.msb_right = 0; 769 var->transp.offset = 0; 770 var->transp.length = 0; 771 772 switch (var->bits_per_pixel) { 773 case 8: /* PSEUDOCOLOUR, 256 */ 774 var->red.offset = 0; 775 var->red.length = 8; 776 var->green.offset = 0; 777 var->green.length = 8; 778 var->blue.offset = 0; 779 var->blue.length = 8; 780 break; 781 782 case 16:/* DIRECTCOLOUR, 64k or 32k */ 783 switch (var->green.length) { 784 case 6: /* RGB565, 64k */ 785 var->red.offset = 11; 786 var->red.length = 5; 787 var->green.offset = 5; 788 var->green.length = 6; 789 var->blue.offset = 0; 790 var->blue.length = 5; 791 break; 792 793 default: 794 case 5: /* RGB555, 32k */ 795 var->red.offset = 10; 796 var->red.length = 5; 797 var->green.offset = 5; 798 var->green.length = 5; 799 var->blue.offset = 0; 800 var->blue.length = 5; 801 break; 802 803 case 4: /* RGB444, 4k + transparency? */ 804 var->transp.offset = 12; 805 var->transp.length = 4; 806 var->red.offset = 8; 807 var->red.length = 4; 808 var->green.offset = 4; 809 var->green.length = 4; 810 var->blue.offset = 0; 811 var->blue.length = 4; 812 break; 813 } 814 break; 815 816 case 24:/* TRUECOLOUR, 16m */ 817 var->red.offset = 16; 818 var->red.length = 8; 819 var->green.offset = 8; 820 var->green.length = 8; 821 var->blue.offset = 0; 822 var->blue.length = 8; 823 break; 824 825 case 32:/* TRUECOLOUR, 16m */ 826 var->transp.offset = 24; 827 var->transp.length = 8; 828 var->red.offset = 16; 829 var->red.length = 8; 830 var->green.offset = 8; 831 var->green.length = 8; 832 var->blue.offset = 0; 833 var->blue.length = 8; 834 break; 835 836 default: 837 return -EINVAL; 838 } 839 840 mem = var->xres_virtual * var->yres_virtual * (var->bits_per_pixel / 8); 841 if (mem > cfb->fb.fix.smem_len) 842 var->yres_virtual = cfb->fb.fix.smem_len * 8 / 843 (var->bits_per_pixel * var->xres_virtual); 844 845 if (var->yres > var->yres_virtual) 846 var->yres = var->yres_virtual; 847 if (var->xres > var->xres_virtual) 848 var->xres = var->xres_virtual; 849 850 err = cyber2000fb_decode_clock(&hw, cfb, var); 851 if (err) 852 return err; 853 854 err = cyber2000fb_decode_crtc(&hw, cfb, var); 855 if (err) 856 return err; 857 858 return 0; 859 } 860 861 static int cyber2000fb_set_par(struct fb_info *info) 862 { 863 struct cfb_info *cfb = container_of(info, struct cfb_info, fb); 864 struct fb_var_screeninfo *var = &cfb->fb.var; 865 struct par_info hw; 866 unsigned int mem; 867 868 hw.width = var->xres_virtual; 869 hw.ramdac = RAMDAC_VREFEN | RAMDAC_DAC8BIT; 870 871 switch (var->bits_per_pixel) { 872 case 8: 873 hw.co_pixfmt = CO_PIXFMT_8BPP; 874 hw.pitch = hw.width >> 3; 875 hw.extseqmisc = EXT_SEQ_MISC_8; 876 break; 877 878 case 16: 879 hw.co_pixfmt = CO_PIXFMT_16BPP; 880 hw.pitch = hw.width >> 2; 881 882 switch (var->green.length) { 883 case 6: /* RGB565, 64k */ 884 hw.extseqmisc = EXT_SEQ_MISC_16_RGB565; 885 break; 886 case 5: /* RGB555, 32k */ 887 hw.extseqmisc = EXT_SEQ_MISC_16_RGB555; 888 break; 889 case 4: /* RGB444, 4k + transparency? */ 890 hw.extseqmisc = EXT_SEQ_MISC_16_RGB444; 891 break; 892 default: 893 BUG(); 894 } 895 break; 896 897 case 24:/* TRUECOLOUR, 16m */ 898 hw.co_pixfmt = CO_PIXFMT_24BPP; 899 hw.width *= 3; 900 hw.pitch = hw.width >> 3; 901 hw.ramdac |= (RAMDAC_BYPASS | RAMDAC_RAMPWRDN); 902 hw.extseqmisc = EXT_SEQ_MISC_24_RGB888; 903 break; 904 905 case 32:/* TRUECOLOUR, 16m */ 906 hw.co_pixfmt = CO_PIXFMT_32BPP; 907 hw.pitch = hw.width >> 1; 908 hw.ramdac |= (RAMDAC_BYPASS | RAMDAC_RAMPWRDN); 909 hw.extseqmisc = EXT_SEQ_MISC_32; 910 break; 911 912 default: 913 BUG(); 914 } 915 916 /* 917 * Sigh, this is absolutely disgusting, but caused by 918 * the way the fbcon developers want to separate out 919 * the "checking" and the "setting" of the video mode. 920 * 921 * If the mode is not suitable for the hardware here, 922 * we can't prevent it being set by returning an error. 923 * 924 * In theory, since NetWinders contain just one VGA card, 925 * we should never end up hitting this problem. 926 */ 927 BUG_ON(cyber2000fb_decode_clock(&hw, cfb, var) != 0); 928 BUG_ON(cyber2000fb_decode_crtc(&hw, cfb, var) != 0); 929 930 hw.width -= 1; 931 hw.fetch = hw.pitch; 932 if (!(cfb->mem_ctl2 & MEM_CTL2_64BIT)) 933 hw.fetch <<= 1; 934 hw.fetch += 1; 935 936 cfb->fb.fix.line_length = var->xres_virtual * var->bits_per_pixel / 8; 937 938 /* 939 * Same here - if the size of the video mode exceeds the 940 * available RAM, we can't prevent this mode being set. 941 * 942 * In theory, since NetWinders contain just one VGA card, 943 * we should never end up hitting this problem. 944 */ 945 mem = cfb->fb.fix.line_length * var->yres_virtual; 946 BUG_ON(mem > cfb->fb.fix.smem_len); 947 948 /* 949 * 8bpp displays are always pseudo colour. 16bpp and above 950 * are direct colour or true colour, depending on whether 951 * the RAMDAC palettes are bypassed. (Direct colour has 952 * palettes, true colour does not.) 953 */ 954 if (var->bits_per_pixel == 8) 955 cfb->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR; 956 else if (hw.ramdac & RAMDAC_BYPASS) 957 cfb->fb.fix.visual = FB_VISUAL_TRUECOLOR; 958 else 959 cfb->fb.fix.visual = FB_VISUAL_DIRECTCOLOR; 960 961 cyber2000fb_set_timing(cfb, &hw); 962 cyber2000fb_update_start(cfb, var); 963 964 return 0; 965 } 966 967 /* 968 * Pan or Wrap the Display 969 */ 970 static int 971 cyber2000fb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info) 972 { 973 struct cfb_info *cfb = container_of(info, struct cfb_info, fb); 974 975 if (cyber2000fb_update_start(cfb, var)) 976 return -EINVAL; 977 978 cfb->fb.var.xoffset = var->xoffset; 979 cfb->fb.var.yoffset = var->yoffset; 980 981 if (var->vmode & FB_VMODE_YWRAP) { 982 cfb->fb.var.vmode |= FB_VMODE_YWRAP; 983 } else { 984 cfb->fb.var.vmode &= ~FB_VMODE_YWRAP; 985 } 986 987 return 0; 988 } 989 990 /* 991 * (Un)Blank the display. 992 * 993 * Blank the screen if blank_mode != 0, else unblank. If 994 * blank == NULL then the caller blanks by setting the CLUT 995 * (Color Look Up Table) to all black. Return 0 if blanking 996 * succeeded, != 0 if un-/blanking failed due to e.g. a 997 * video mode which doesn't support it. Implements VESA 998 * suspend and powerdown modes on hardware that supports 999 * disabling hsync/vsync: 1000 * blank_mode == 2: suspend vsync 1001 * blank_mode == 3: suspend hsync 1002 * blank_mode == 4: powerdown 1003 * 1004 * wms...Enable VESA DMPS compatible powerdown mode 1005 * run "setterm -powersave powerdown" to take advantage 1006 */ 1007 static int cyber2000fb_blank(int blank, struct fb_info *info) 1008 { 1009 struct cfb_info *cfb = container_of(info, struct cfb_info, fb); 1010 unsigned int sync = 0; 1011 int i; 1012 1013 switch (blank) { 1014 case FB_BLANK_POWERDOWN: /* powerdown - both sync lines down */ 1015 sync = EXT_SYNC_CTL_VS_0 | EXT_SYNC_CTL_HS_0; 1016 break; 1017 case FB_BLANK_HSYNC_SUSPEND: /* hsync off */ 1018 sync = EXT_SYNC_CTL_VS_NORMAL | EXT_SYNC_CTL_HS_0; 1019 break; 1020 case FB_BLANK_VSYNC_SUSPEND: /* vsync off */ 1021 sync = EXT_SYNC_CTL_VS_0 | EXT_SYNC_CTL_HS_NORMAL; 1022 break; 1023 case FB_BLANK_NORMAL: /* soft blank */ 1024 default: /* unblank */ 1025 break; 1026 } 1027 1028 cyber2000_grphw(EXT_SYNC_CTL, sync, cfb); 1029 1030 if (blank <= 1) { 1031 /* turn on ramdacs */ 1032 cfb->ramdac_powerdown &= ~(RAMDAC_DACPWRDN | RAMDAC_BYPASS | 1033 RAMDAC_RAMPWRDN); 1034 cyber2000fb_write_ramdac_ctrl(cfb); 1035 } 1036 1037 /* 1038 * Soft blank/unblank the display. 1039 */ 1040 if (blank) { /* soft blank */ 1041 for (i = 0; i < NR_PALETTE; i++) { 1042 cyber2000fb_writeb(i, 0x3c8, cfb); 1043 cyber2000fb_writeb(0, 0x3c9, cfb); 1044 cyber2000fb_writeb(0, 0x3c9, cfb); 1045 cyber2000fb_writeb(0, 0x3c9, cfb); 1046 } 1047 } else { /* unblank */ 1048 for (i = 0; i < NR_PALETTE; i++) { 1049 cyber2000fb_writeb(i, 0x3c8, cfb); 1050 cyber2000fb_writeb(cfb->palette[i].red, 0x3c9, cfb); 1051 cyber2000fb_writeb(cfb->palette[i].green, 0x3c9, cfb); 1052 cyber2000fb_writeb(cfb->palette[i].blue, 0x3c9, cfb); 1053 } 1054 } 1055 1056 if (blank >= 2) { 1057 /* turn off ramdacs */ 1058 cfb->ramdac_powerdown |= RAMDAC_DACPWRDN | RAMDAC_BYPASS | 1059 RAMDAC_RAMPWRDN; 1060 cyber2000fb_write_ramdac_ctrl(cfb); 1061 } 1062 1063 return 0; 1064 } 1065 1066 static struct fb_ops cyber2000fb_ops = { 1067 .owner = THIS_MODULE, 1068 .fb_check_var = cyber2000fb_check_var, 1069 .fb_set_par = cyber2000fb_set_par, 1070 .fb_setcolreg = cyber2000fb_setcolreg, 1071 .fb_blank = cyber2000fb_blank, 1072 .fb_pan_display = cyber2000fb_pan_display, 1073 .fb_fillrect = cyber2000fb_fillrect, 1074 .fb_copyarea = cyber2000fb_copyarea, 1075 .fb_imageblit = cyber2000fb_imageblit, 1076 .fb_sync = cyber2000fb_sync, 1077 }; 1078 1079 /* 1080 * This is the only "static" reference to the internal data structures 1081 * of this driver. It is here solely at the moment to support the other 1082 * CyberPro modules external to this driver. 1083 */ 1084 static struct cfb_info *int_cfb_info; 1085 1086 /* 1087 * Enable access to the extended registers 1088 */ 1089 void cyber2000fb_enable_extregs(struct cfb_info *cfb) 1090 { 1091 cfb->func_use_count += 1; 1092 1093 if (cfb->func_use_count == 1) { 1094 int old; 1095 1096 old = cyber2000_grphr(EXT_FUNC_CTL, cfb); 1097 old |= EXT_FUNC_CTL_EXTREGENBL; 1098 cyber2000_grphw(EXT_FUNC_CTL, old, cfb); 1099 } 1100 } 1101 EXPORT_SYMBOL(cyber2000fb_enable_extregs); 1102 1103 /* 1104 * Disable access to the extended registers 1105 */ 1106 void cyber2000fb_disable_extregs(struct cfb_info *cfb) 1107 { 1108 if (cfb->func_use_count == 1) { 1109 int old; 1110 1111 old = cyber2000_grphr(EXT_FUNC_CTL, cfb); 1112 old &= ~EXT_FUNC_CTL_EXTREGENBL; 1113 cyber2000_grphw(EXT_FUNC_CTL, old, cfb); 1114 } 1115 1116 if (cfb->func_use_count == 0) 1117 printk(KERN_ERR "disable_extregs: count = 0\n"); 1118 else 1119 cfb->func_use_count -= 1; 1120 } 1121 EXPORT_SYMBOL(cyber2000fb_disable_extregs); 1122 1123 /* 1124 * Attach a capture/tv driver to the core CyberX0X0 driver. 1125 */ 1126 int cyber2000fb_attach(struct cyberpro_info *info, int idx) 1127 { 1128 if (int_cfb_info != NULL) { 1129 info->dev = int_cfb_info->fb.device; 1130 #ifdef CONFIG_FB_CYBER2000_I2C 1131 info->i2c = &int_cfb_info->i2c_adapter; 1132 #else 1133 info->i2c = NULL; 1134 #endif 1135 info->regs = int_cfb_info->regs; 1136 info->irq = int_cfb_info->irq; 1137 info->fb = int_cfb_info->fb.screen_base; 1138 info->fb_size = int_cfb_info->fb.fix.smem_len; 1139 info->info = int_cfb_info; 1140 1141 strlcpy(info->dev_name, int_cfb_info->fb.fix.id, 1142 sizeof(info->dev_name)); 1143 } 1144 1145 return int_cfb_info != NULL; 1146 } 1147 EXPORT_SYMBOL(cyber2000fb_attach); 1148 1149 /* 1150 * Detach a capture/tv driver from the core CyberX0X0 driver. 1151 */ 1152 void cyber2000fb_detach(int idx) 1153 { 1154 } 1155 EXPORT_SYMBOL(cyber2000fb_detach); 1156 1157 #ifdef CONFIG_FB_CYBER2000_DDC 1158 1159 #define DDC_REG 0xb0 1160 #define DDC_SCL_OUT (1 << 0) 1161 #define DDC_SDA_OUT (1 << 4) 1162 #define DDC_SCL_IN (1 << 2) 1163 #define DDC_SDA_IN (1 << 6) 1164 1165 static void cyber2000fb_enable_ddc(struct cfb_info *cfb) 1166 { 1167 spin_lock(&cfb->reg_b0_lock); 1168 cyber2000fb_writew(0x1bf, 0x3ce, cfb); 1169 } 1170 1171 static void cyber2000fb_disable_ddc(struct cfb_info *cfb) 1172 { 1173 cyber2000fb_writew(0x0bf, 0x3ce, cfb); 1174 spin_unlock(&cfb->reg_b0_lock); 1175 } 1176 1177 1178 static void cyber2000fb_ddc_setscl(void *data, int val) 1179 { 1180 struct cfb_info *cfb = data; 1181 unsigned char reg; 1182 1183 cyber2000fb_enable_ddc(cfb); 1184 reg = cyber2000_grphr(DDC_REG, cfb); 1185 if (!val) /* bit is inverted */ 1186 reg |= DDC_SCL_OUT; 1187 else 1188 reg &= ~DDC_SCL_OUT; 1189 cyber2000_grphw(DDC_REG, reg, cfb); 1190 cyber2000fb_disable_ddc(cfb); 1191 } 1192 1193 static void cyber2000fb_ddc_setsda(void *data, int val) 1194 { 1195 struct cfb_info *cfb = data; 1196 unsigned char reg; 1197 1198 cyber2000fb_enable_ddc(cfb); 1199 reg = cyber2000_grphr(DDC_REG, cfb); 1200 if (!val) /* bit is inverted */ 1201 reg |= DDC_SDA_OUT; 1202 else 1203 reg &= ~DDC_SDA_OUT; 1204 cyber2000_grphw(DDC_REG, reg, cfb); 1205 cyber2000fb_disable_ddc(cfb); 1206 } 1207 1208 static int cyber2000fb_ddc_getscl(void *data) 1209 { 1210 struct cfb_info *cfb = data; 1211 int retval; 1212 1213 cyber2000fb_enable_ddc(cfb); 1214 retval = !!(cyber2000_grphr(DDC_REG, cfb) & DDC_SCL_IN); 1215 cyber2000fb_disable_ddc(cfb); 1216 1217 return retval; 1218 } 1219 1220 static int cyber2000fb_ddc_getsda(void *data) 1221 { 1222 struct cfb_info *cfb = data; 1223 int retval; 1224 1225 cyber2000fb_enable_ddc(cfb); 1226 retval = !!(cyber2000_grphr(DDC_REG, cfb) & DDC_SDA_IN); 1227 cyber2000fb_disable_ddc(cfb); 1228 1229 return retval; 1230 } 1231 1232 static int cyber2000fb_setup_ddc_bus(struct cfb_info *cfb) 1233 { 1234 strlcpy(cfb->ddc_adapter.name, cfb->fb.fix.id, 1235 sizeof(cfb->ddc_adapter.name)); 1236 cfb->ddc_adapter.owner = THIS_MODULE; 1237 cfb->ddc_adapter.class = I2C_CLASS_DDC; 1238 cfb->ddc_adapter.algo_data = &cfb->ddc_algo; 1239 cfb->ddc_adapter.dev.parent = cfb->fb.device; 1240 cfb->ddc_algo.setsda = cyber2000fb_ddc_setsda; 1241 cfb->ddc_algo.setscl = cyber2000fb_ddc_setscl; 1242 cfb->ddc_algo.getsda = cyber2000fb_ddc_getsda; 1243 cfb->ddc_algo.getscl = cyber2000fb_ddc_getscl; 1244 cfb->ddc_algo.udelay = 10; 1245 cfb->ddc_algo.timeout = 20; 1246 cfb->ddc_algo.data = cfb; 1247 1248 i2c_set_adapdata(&cfb->ddc_adapter, cfb); 1249 1250 return i2c_bit_add_bus(&cfb->ddc_adapter); 1251 } 1252 #endif /* CONFIG_FB_CYBER2000_DDC */ 1253 1254 #ifdef CONFIG_FB_CYBER2000_I2C 1255 static void cyber2000fb_i2c_setsda(void *data, int state) 1256 { 1257 struct cfb_info *cfb = data; 1258 unsigned int latch2; 1259 1260 spin_lock(&cfb->reg_b0_lock); 1261 latch2 = cyber2000_grphr(EXT_LATCH2, cfb); 1262 latch2 &= EXT_LATCH2_I2C_CLKEN; 1263 if (state) 1264 latch2 |= EXT_LATCH2_I2C_DATEN; 1265 cyber2000_grphw(EXT_LATCH2, latch2, cfb); 1266 spin_unlock(&cfb->reg_b0_lock); 1267 } 1268 1269 static void cyber2000fb_i2c_setscl(void *data, int state) 1270 { 1271 struct cfb_info *cfb = data; 1272 unsigned int latch2; 1273 1274 spin_lock(&cfb->reg_b0_lock); 1275 latch2 = cyber2000_grphr(EXT_LATCH2, cfb); 1276 latch2 &= EXT_LATCH2_I2C_DATEN; 1277 if (state) 1278 latch2 |= EXT_LATCH2_I2C_CLKEN; 1279 cyber2000_grphw(EXT_LATCH2, latch2, cfb); 1280 spin_unlock(&cfb->reg_b0_lock); 1281 } 1282 1283 static int cyber2000fb_i2c_getsda(void *data) 1284 { 1285 struct cfb_info *cfb = data; 1286 int ret; 1287 1288 spin_lock(&cfb->reg_b0_lock); 1289 ret = !!(cyber2000_grphr(EXT_LATCH2, cfb) & EXT_LATCH2_I2C_DAT); 1290 spin_unlock(&cfb->reg_b0_lock); 1291 1292 return ret; 1293 } 1294 1295 static int cyber2000fb_i2c_getscl(void *data) 1296 { 1297 struct cfb_info *cfb = data; 1298 int ret; 1299 1300 spin_lock(&cfb->reg_b0_lock); 1301 ret = !!(cyber2000_grphr(EXT_LATCH2, cfb) & EXT_LATCH2_I2C_CLK); 1302 spin_unlock(&cfb->reg_b0_lock); 1303 1304 return ret; 1305 } 1306 1307 static int cyber2000fb_i2c_register(struct cfb_info *cfb) 1308 { 1309 strlcpy(cfb->i2c_adapter.name, cfb->fb.fix.id, 1310 sizeof(cfb->i2c_adapter.name)); 1311 cfb->i2c_adapter.owner = THIS_MODULE; 1312 cfb->i2c_adapter.algo_data = &cfb->i2c_algo; 1313 cfb->i2c_adapter.dev.parent = cfb->fb.device; 1314 cfb->i2c_algo.setsda = cyber2000fb_i2c_setsda; 1315 cfb->i2c_algo.setscl = cyber2000fb_i2c_setscl; 1316 cfb->i2c_algo.getsda = cyber2000fb_i2c_getsda; 1317 cfb->i2c_algo.getscl = cyber2000fb_i2c_getscl; 1318 cfb->i2c_algo.udelay = 5; 1319 cfb->i2c_algo.timeout = msecs_to_jiffies(100); 1320 cfb->i2c_algo.data = cfb; 1321 1322 return i2c_bit_add_bus(&cfb->i2c_adapter); 1323 } 1324 1325 static void cyber2000fb_i2c_unregister(struct cfb_info *cfb) 1326 { 1327 i2c_del_adapter(&cfb->i2c_adapter); 1328 } 1329 #else 1330 #define cyber2000fb_i2c_register(cfb) (0) 1331 #define cyber2000fb_i2c_unregister(cfb) do { } while (0) 1332 #endif 1333 1334 /* 1335 * These parameters give 1336 * 640x480, hsync 31.5kHz, vsync 60Hz 1337 */ 1338 static const struct fb_videomode cyber2000fb_default_mode = { 1339 .refresh = 60, 1340 .xres = 640, 1341 .yres = 480, 1342 .pixclock = 39722, 1343 .left_margin = 56, 1344 .right_margin = 16, 1345 .upper_margin = 34, 1346 .lower_margin = 9, 1347 .hsync_len = 88, 1348 .vsync_len = 2, 1349 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, 1350 .vmode = FB_VMODE_NONINTERLACED 1351 }; 1352 1353 static char igs_regs[] = { 1354 EXT_CRT_IRQ, 0, 1355 EXT_CRT_TEST, 0, 1356 EXT_SYNC_CTL, 0, 1357 EXT_SEG_WRITE_PTR, 0, 1358 EXT_SEG_READ_PTR, 0, 1359 EXT_BIU_MISC, EXT_BIU_MISC_LIN_ENABLE | 1360 EXT_BIU_MISC_COP_ENABLE | 1361 EXT_BIU_MISC_COP_BFC, 1362 EXT_FUNC_CTL, 0, 1363 CURS_H_START, 0, 1364 CURS_H_START + 1, 0, 1365 CURS_H_PRESET, 0, 1366 CURS_V_START, 0, 1367 CURS_V_START + 1, 0, 1368 CURS_V_PRESET, 0, 1369 CURS_CTL, 0, 1370 EXT_ATTRIB_CTL, EXT_ATTRIB_CTL_EXT, 1371 EXT_OVERSCAN_RED, 0, 1372 EXT_OVERSCAN_GREEN, 0, 1373 EXT_OVERSCAN_BLUE, 0, 1374 1375 /* some of these are questionable when we have a BIOS */ 1376 EXT_MEM_CTL0, EXT_MEM_CTL0_7CLK | 1377 EXT_MEM_CTL0_RAS_1 | 1378 EXT_MEM_CTL0_MULTCAS, 1379 EXT_HIDDEN_CTL1, 0x30, 1380 EXT_FIFO_CTL, 0x0b, 1381 EXT_FIFO_CTL + 1, 0x17, 1382 0x76, 0x00, 1383 EXT_HIDDEN_CTL4, 0xc8 1384 }; 1385 1386 /* 1387 * Initialise the CyberPro hardware. On the CyberPro5XXXX, 1388 * ensure that we're using the correct PLL (5XXX's may be 1389 * programmed to use an additional set of PLLs.) 1390 */ 1391 static void cyberpro_init_hw(struct cfb_info *cfb) 1392 { 1393 int i; 1394 1395 for (i = 0; i < sizeof(igs_regs); i += 2) 1396 cyber2000_grphw(igs_regs[i], igs_regs[i + 1], cfb); 1397 1398 if (cfb->id == ID_CYBERPRO_5000) { 1399 unsigned char val; 1400 cyber2000fb_writeb(0xba, 0x3ce, cfb); 1401 val = cyber2000fb_readb(0x3cf, cfb) & 0x80; 1402 cyber2000fb_writeb(val, 0x3cf, cfb); 1403 } 1404 } 1405 1406 static struct cfb_info *cyberpro_alloc_fb_info(unsigned int id, char *name) 1407 { 1408 struct cfb_info *cfb; 1409 1410 cfb = kzalloc(sizeof(struct cfb_info), GFP_KERNEL); 1411 if (!cfb) 1412 return NULL; 1413 1414 1415 cfb->id = id; 1416 1417 if (id == ID_CYBERPRO_5000) 1418 cfb->ref_ps = 40690; /* 24.576 MHz */ 1419 else 1420 cfb->ref_ps = 69842; /* 14.31818 MHz (69841?) */ 1421 1422 cfb->divisors[0] = 1; 1423 cfb->divisors[1] = 2; 1424 cfb->divisors[2] = 4; 1425 1426 if (id == ID_CYBERPRO_2000) 1427 cfb->divisors[3] = 8; 1428 else 1429 cfb->divisors[3] = 6; 1430 1431 strcpy(cfb->fb.fix.id, name); 1432 1433 cfb->fb.fix.type = FB_TYPE_PACKED_PIXELS; 1434 cfb->fb.fix.type_aux = 0; 1435 cfb->fb.fix.xpanstep = 0; 1436 cfb->fb.fix.ypanstep = 1; 1437 cfb->fb.fix.ywrapstep = 0; 1438 1439 switch (id) { 1440 case ID_IGA_1682: 1441 cfb->fb.fix.accel = 0; 1442 break; 1443 1444 case ID_CYBERPRO_2000: 1445 cfb->fb.fix.accel = FB_ACCEL_IGS_CYBER2000; 1446 break; 1447 1448 case ID_CYBERPRO_2010: 1449 cfb->fb.fix.accel = FB_ACCEL_IGS_CYBER2010; 1450 break; 1451 1452 case ID_CYBERPRO_5000: 1453 cfb->fb.fix.accel = FB_ACCEL_IGS_CYBER5000; 1454 break; 1455 } 1456 1457 cfb->fb.var.nonstd = 0; 1458 cfb->fb.var.activate = FB_ACTIVATE_NOW; 1459 cfb->fb.var.height = -1; 1460 cfb->fb.var.width = -1; 1461 cfb->fb.var.accel_flags = FB_ACCELF_TEXT; 1462 1463 cfb->fb.fbops = &cyber2000fb_ops; 1464 cfb->fb.flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN; 1465 cfb->fb.pseudo_palette = cfb->pseudo_palette; 1466 1467 spin_lock_init(&cfb->reg_b0_lock); 1468 1469 fb_alloc_cmap(&cfb->fb.cmap, NR_PALETTE, 0); 1470 1471 return cfb; 1472 } 1473 1474 static void cyberpro_free_fb_info(struct cfb_info *cfb) 1475 { 1476 if (cfb) { 1477 /* 1478 * Free the colourmap 1479 */ 1480 fb_alloc_cmap(&cfb->fb.cmap, 0, 0); 1481 1482 kfree(cfb); 1483 } 1484 } 1485 1486 /* 1487 * Parse Cyber2000fb options. Usage: 1488 * video=cyber2000:font:fontname 1489 */ 1490 #ifndef MODULE 1491 static int cyber2000fb_setup(char *options) 1492 { 1493 char *opt; 1494 1495 if (!options || !*options) 1496 return 0; 1497 1498 while ((opt = strsep(&options, ",")) != NULL) { 1499 if (!*opt) 1500 continue; 1501 1502 if (strncmp(opt, "font:", 5) == 0) { 1503 static char default_font_storage[40]; 1504 1505 strlcpy(default_font_storage, opt + 5, 1506 sizeof(default_font_storage)); 1507 default_font = default_font_storage; 1508 continue; 1509 } 1510 1511 printk(KERN_ERR "CyberPro20x0: unknown parameter: %s\n", opt); 1512 } 1513 return 0; 1514 } 1515 #endif /* MODULE */ 1516 1517 /* 1518 * The CyberPro chips can be placed on many different bus types. 1519 * This probe function is common to all bus types. The bus-specific 1520 * probe function is expected to have: 1521 * - enabled access to the linear memory region 1522 * - memory mapped access to the registers 1523 * - initialised mem_ctl1 and mem_ctl2 appropriately. 1524 */ 1525 static int cyberpro_common_probe(struct cfb_info *cfb) 1526 { 1527 u_long smem_size; 1528 u_int h_sync, v_sync; 1529 int err; 1530 1531 cyberpro_init_hw(cfb); 1532 1533 /* 1534 * Get the video RAM size and width from the VGA register. 1535 * This should have been already initialised by the BIOS, 1536 * but if it's garbage, claim default 1MB VRAM (woody) 1537 */ 1538 cfb->mem_ctl1 = cyber2000_grphr(EXT_MEM_CTL1, cfb); 1539 cfb->mem_ctl2 = cyber2000_grphr(EXT_MEM_CTL2, cfb); 1540 1541 /* 1542 * Determine the size of the memory. 1543 */ 1544 switch (cfb->mem_ctl2 & MEM_CTL2_SIZE_MASK) { 1545 case MEM_CTL2_SIZE_4MB: 1546 smem_size = 0x00400000; 1547 break; 1548 case MEM_CTL2_SIZE_2MB: 1549 smem_size = 0x00200000; 1550 break; 1551 case MEM_CTL2_SIZE_1MB: 1552 smem_size = 0x00100000; 1553 break; 1554 default: 1555 smem_size = 0x00100000; 1556 break; 1557 } 1558 1559 cfb->fb.fix.smem_len = smem_size; 1560 cfb->fb.fix.mmio_len = MMIO_SIZE; 1561 cfb->fb.screen_base = cfb->region; 1562 1563 #ifdef CONFIG_FB_CYBER2000_DDC 1564 if (cyber2000fb_setup_ddc_bus(cfb) == 0) 1565 cfb->ddc_registered = true; 1566 #endif 1567 1568 err = -EINVAL; 1569 if (!fb_find_mode(&cfb->fb.var, &cfb->fb, NULL, NULL, 0, 1570 &cyber2000fb_default_mode, 8)) { 1571 printk(KERN_ERR "%s: no valid mode found\n", cfb->fb.fix.id); 1572 goto failed; 1573 } 1574 1575 cfb->fb.var.yres_virtual = cfb->fb.fix.smem_len * 8 / 1576 (cfb->fb.var.bits_per_pixel * cfb->fb.var.xres_virtual); 1577 1578 if (cfb->fb.var.yres_virtual < cfb->fb.var.yres) 1579 cfb->fb.var.yres_virtual = cfb->fb.var.yres; 1580 1581 /* fb_set_var(&cfb->fb.var, -1, &cfb->fb); */ 1582 1583 /* 1584 * Calculate the hsync and vsync frequencies. Note that 1585 * we split the 1e12 constant up so that we can preserve 1586 * the precision and fit the results into 32-bit registers. 1587 * (1953125000 * 512 = 1e12) 1588 */ 1589 h_sync = 1953125000 / cfb->fb.var.pixclock; 1590 h_sync = h_sync * 512 / (cfb->fb.var.xres + cfb->fb.var.left_margin + 1591 cfb->fb.var.right_margin + cfb->fb.var.hsync_len); 1592 v_sync = h_sync / (cfb->fb.var.yres + cfb->fb.var.upper_margin + 1593 cfb->fb.var.lower_margin + cfb->fb.var.vsync_len); 1594 1595 printk(KERN_INFO "%s: %dKiB VRAM, using %dx%d, %d.%03dkHz, %dHz\n", 1596 cfb->fb.fix.id, cfb->fb.fix.smem_len >> 10, 1597 cfb->fb.var.xres, cfb->fb.var.yres, 1598 h_sync / 1000, h_sync % 1000, v_sync); 1599 1600 err = cyber2000fb_i2c_register(cfb); 1601 if (err) 1602 goto failed; 1603 1604 err = register_framebuffer(&cfb->fb); 1605 if (err) 1606 cyber2000fb_i2c_unregister(cfb); 1607 1608 failed: 1609 #ifdef CONFIG_FB_CYBER2000_DDC 1610 if (err && cfb->ddc_registered) 1611 i2c_del_adapter(&cfb->ddc_adapter); 1612 #endif 1613 return err; 1614 } 1615 1616 static void cyberpro_common_remove(struct cfb_info *cfb) 1617 { 1618 unregister_framebuffer(&cfb->fb); 1619 #ifdef CONFIG_FB_CYBER2000_DDC 1620 if (cfb->ddc_registered) 1621 i2c_del_adapter(&cfb->ddc_adapter); 1622 #endif 1623 cyber2000fb_i2c_unregister(cfb); 1624 } 1625 1626 static void cyberpro_common_resume(struct cfb_info *cfb) 1627 { 1628 cyberpro_init_hw(cfb); 1629 1630 /* 1631 * Reprogram the MEM_CTL1 and MEM_CTL2 registers 1632 */ 1633 cyber2000_grphw(EXT_MEM_CTL1, cfb->mem_ctl1, cfb); 1634 cyber2000_grphw(EXT_MEM_CTL2, cfb->mem_ctl2, cfb); 1635 1636 /* 1637 * Restore the old video mode and the palette. 1638 * We also need to tell fbcon to redraw the console. 1639 */ 1640 cyber2000fb_set_par(&cfb->fb); 1641 } 1642 1643 /* 1644 * PCI specific support. 1645 */ 1646 #ifdef CONFIG_PCI 1647 /* 1648 * We need to wake up the CyberPro, and make sure its in linear memory 1649 * mode. Unfortunately, this is specific to the platform and card that 1650 * we are running on. 1651 * 1652 * On x86 and ARM, should we be initialising the CyberPro first via the 1653 * IO registers, and then the MMIO registers to catch all cases? Can we 1654 * end up in the situation where the chip is in MMIO mode, but not awake 1655 * on an x86 system? 1656 */ 1657 static int cyberpro_pci_enable_mmio(struct cfb_info *cfb) 1658 { 1659 unsigned char val; 1660 1661 #if defined(__sparc_v9__) 1662 #error "You lose, consult DaveM." 1663 #elif defined(__sparc__) 1664 /* 1665 * SPARC does not have an "outb" instruction, so we generate 1666 * I/O cycles storing into a reserved memory space at 1667 * physical address 0x3000000 1668 */ 1669 unsigned char __iomem *iop; 1670 1671 iop = ioremap(0x3000000, 0x5000); 1672 if (iop == NULL) { 1673 printk(KERN_ERR "iga5000: cannot map I/O\n"); 1674 return -ENOMEM; 1675 } 1676 1677 writeb(0x18, iop + 0x46e8); 1678 writeb(0x01, iop + 0x102); 1679 writeb(0x08, iop + 0x46e8); 1680 writeb(EXT_BIU_MISC, iop + 0x3ce); 1681 writeb(EXT_BIU_MISC_LIN_ENABLE, iop + 0x3cf); 1682 1683 iounmap(iop); 1684 #else 1685 /* 1686 * Most other machine types are "normal", so 1687 * we use the standard IO-based wakeup. 1688 */ 1689 outb(0x18, 0x46e8); 1690 outb(0x01, 0x102); 1691 outb(0x08, 0x46e8); 1692 outb(EXT_BIU_MISC, 0x3ce); 1693 outb(EXT_BIU_MISC_LIN_ENABLE, 0x3cf); 1694 #endif 1695 1696 /* 1697 * Allow the CyberPro to accept PCI burst accesses 1698 */ 1699 if (cfb->id == ID_CYBERPRO_2010) { 1700 printk(KERN_INFO "%s: NOT enabling PCI bursts\n", 1701 cfb->fb.fix.id); 1702 } else { 1703 val = cyber2000_grphr(EXT_BUS_CTL, cfb); 1704 if (!(val & EXT_BUS_CTL_PCIBURST_WRITE)) { 1705 printk(KERN_INFO "%s: enabling PCI bursts\n", 1706 cfb->fb.fix.id); 1707 1708 val |= EXT_BUS_CTL_PCIBURST_WRITE; 1709 1710 if (cfb->id == ID_CYBERPRO_5000) 1711 val |= EXT_BUS_CTL_PCIBURST_READ; 1712 1713 cyber2000_grphw(EXT_BUS_CTL, val, cfb); 1714 } 1715 } 1716 1717 return 0; 1718 } 1719 1720 static int cyberpro_pci_probe(struct pci_dev *dev, 1721 const struct pci_device_id *id) 1722 { 1723 struct cfb_info *cfb; 1724 char name[16]; 1725 int err; 1726 1727 sprintf(name, "CyberPro%4X", id->device); 1728 1729 err = pci_enable_device(dev); 1730 if (err) 1731 return err; 1732 1733 err = -ENOMEM; 1734 cfb = cyberpro_alloc_fb_info(id->driver_data, name); 1735 if (!cfb) 1736 goto failed_release; 1737 1738 err = pci_request_regions(dev, cfb->fb.fix.id); 1739 if (err) 1740 goto failed_regions; 1741 1742 cfb->irq = dev->irq; 1743 cfb->region = pci_ioremap_bar(dev, 0); 1744 if (!cfb->region) { 1745 err = -ENOMEM; 1746 goto failed_ioremap; 1747 } 1748 1749 cfb->regs = cfb->region + MMIO_OFFSET; 1750 cfb->fb.device = &dev->dev; 1751 cfb->fb.fix.mmio_start = pci_resource_start(dev, 0) + MMIO_OFFSET; 1752 cfb->fb.fix.smem_start = pci_resource_start(dev, 0); 1753 1754 /* 1755 * Bring up the hardware. This is expected to enable access 1756 * to the linear memory region, and allow access to the memory 1757 * mapped registers. Also, mem_ctl1 and mem_ctl2 must be 1758 * initialised. 1759 */ 1760 err = cyberpro_pci_enable_mmio(cfb); 1761 if (err) 1762 goto failed; 1763 1764 /* 1765 * Use MCLK from BIOS. FIXME: what about hotplug? 1766 */ 1767 cfb->mclk_mult = cyber2000_grphr(EXT_MCLK_MULT, cfb); 1768 cfb->mclk_div = cyber2000_grphr(EXT_MCLK_DIV, cfb); 1769 1770 #ifdef __arm__ 1771 /* 1772 * MCLK on the NetWinder and the Shark is fixed at 75MHz 1773 */ 1774 if (machine_is_netwinder()) { 1775 cfb->mclk_mult = 0xdb; 1776 cfb->mclk_div = 0x54; 1777 } 1778 #endif 1779 1780 err = cyberpro_common_probe(cfb); 1781 if (err) 1782 goto failed; 1783 1784 /* 1785 * Our driver data 1786 */ 1787 pci_set_drvdata(dev, cfb); 1788 if (int_cfb_info == NULL) 1789 int_cfb_info = cfb; 1790 1791 return 0; 1792 1793 failed: 1794 iounmap(cfb->region); 1795 failed_ioremap: 1796 pci_release_regions(dev); 1797 failed_regions: 1798 cyberpro_free_fb_info(cfb); 1799 failed_release: 1800 return err; 1801 } 1802 1803 static void cyberpro_pci_remove(struct pci_dev *dev) 1804 { 1805 struct cfb_info *cfb = pci_get_drvdata(dev); 1806 1807 if (cfb) { 1808 cyberpro_common_remove(cfb); 1809 iounmap(cfb->region); 1810 cyberpro_free_fb_info(cfb); 1811 1812 if (cfb == int_cfb_info) 1813 int_cfb_info = NULL; 1814 1815 pci_release_regions(dev); 1816 } 1817 } 1818 1819 static int cyberpro_pci_suspend(struct pci_dev *dev, pm_message_t state) 1820 { 1821 return 0; 1822 } 1823 1824 /* 1825 * Re-initialise the CyberPro hardware 1826 */ 1827 static int cyberpro_pci_resume(struct pci_dev *dev) 1828 { 1829 struct cfb_info *cfb = pci_get_drvdata(dev); 1830 1831 if (cfb) { 1832 cyberpro_pci_enable_mmio(cfb); 1833 cyberpro_common_resume(cfb); 1834 } 1835 1836 return 0; 1837 } 1838 1839 static struct pci_device_id cyberpro_pci_table[] = { 1840 /* Not yet 1841 * { PCI_VENDOR_ID_INTERG, PCI_DEVICE_ID_INTERG_1682, 1842 * PCI_ANY_ID, PCI_ANY_ID, 0, 0, ID_IGA_1682 }, 1843 */ 1844 { PCI_VENDOR_ID_INTERG, PCI_DEVICE_ID_INTERG_2000, 1845 PCI_ANY_ID, PCI_ANY_ID, 0, 0, ID_CYBERPRO_2000 }, 1846 { PCI_VENDOR_ID_INTERG, PCI_DEVICE_ID_INTERG_2010, 1847 PCI_ANY_ID, PCI_ANY_ID, 0, 0, ID_CYBERPRO_2010 }, 1848 { PCI_VENDOR_ID_INTERG, PCI_DEVICE_ID_INTERG_5000, 1849 PCI_ANY_ID, PCI_ANY_ID, 0, 0, ID_CYBERPRO_5000 }, 1850 { 0, } 1851 }; 1852 1853 MODULE_DEVICE_TABLE(pci, cyberpro_pci_table); 1854 1855 static struct pci_driver cyberpro_driver = { 1856 .name = "CyberPro", 1857 .probe = cyberpro_pci_probe, 1858 .remove = cyberpro_pci_remove, 1859 .suspend = cyberpro_pci_suspend, 1860 .resume = cyberpro_pci_resume, 1861 .id_table = cyberpro_pci_table 1862 }; 1863 #endif 1864 1865 /* 1866 * I don't think we can use the "module_init" stuff here because 1867 * the fbcon stuff may not be initialised yet. Hence the #ifdef 1868 * around module_init. 1869 * 1870 * Tony: "module_init" is now required 1871 */ 1872 static int __init cyber2000fb_init(void) 1873 { 1874 int ret = -1, err; 1875 1876 #ifndef MODULE 1877 char *option = NULL; 1878 1879 if (fb_get_options("cyber2000fb", &option)) 1880 return -ENODEV; 1881 cyber2000fb_setup(option); 1882 #endif 1883 1884 err = pci_register_driver(&cyberpro_driver); 1885 if (!err) 1886 ret = 0; 1887 1888 return ret ? err : 0; 1889 } 1890 module_init(cyber2000fb_init); 1891 1892 static void __exit cyberpro_exit(void) 1893 { 1894 pci_unregister_driver(&cyberpro_driver); 1895 } 1896 module_exit(cyberpro_exit); 1897 1898 MODULE_AUTHOR("Russell King"); 1899 MODULE_DESCRIPTION("CyberPro 2000, 2010 and 5000 framebuffer driver"); 1900 MODULE_LICENSE("GPL"); 1901