1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * linux/drivers/video/cyber2000fb.c 4 * 5 * Copyright (C) 1998-2002 Russell King 6 * 7 * MIPS and 50xx clock support 8 * Copyright (C) 2001 Bradley D. LaRonde <brad@ltc.com> 9 * 10 * 32 bit support, text color and panning fixes for modes != 8 bit 11 * Copyright (C) 2002 Denis Oliver Kropp <dok@directfb.org> 12 * 13 * Integraphics CyberPro 2000, 2010 and 5000 frame buffer device 14 * 15 * Based on cyberfb.c. 16 * 17 * Note that we now use the new fbcon fix, var and cmap scheme. We do 18 * still have to check which console is the currently displayed one 19 * however, especially for the colourmap stuff. 20 * 21 * We also use the new hotplug PCI subsystem. I'm not sure if there 22 * are any such cards, but I'm erring on the side of caution. We don't 23 * want to go pop just because someone does have one. 24 * 25 * Note that this doesn't work fully in the case of multiple CyberPro 26 * cards with grabbers. We currently can only attach to the first 27 * CyberPro card found. 28 * 29 * When we're in truecolour mode, we power down the LUT RAM as a power 30 * saving feature. Also, when we enter any of the powersaving modes 31 * (except soft blanking) we power down the RAMDACs. This saves about 32 * 1W, which is roughly 8% of the power consumption of a NetWinder 33 * (which, incidentally, is about the same saving as a 2.5in hard disk 34 * entering standby mode.) 35 */ 36 #include <linux/module.h> 37 #include <linux/kernel.h> 38 #include <linux/errno.h> 39 #include <linux/string.h> 40 #include <linux/mm.h> 41 #include <linux/slab.h> 42 #include <linux/delay.h> 43 #include <linux/fb.h> 44 #include <linux/pci.h> 45 #include <linux/init.h> 46 #include <linux/io.h> 47 #include <linux/i2c.h> 48 #include <linux/i2c-algo-bit.h> 49 50 #include <asm/pgtable.h> 51 52 #ifdef __arm__ 53 #include <asm/mach-types.h> 54 #endif 55 56 #include "cyber2000fb.h" 57 58 struct cfb_info { 59 struct fb_info fb; 60 struct display_switch *dispsw; 61 struct display *display; 62 unsigned char __iomem *region; 63 unsigned char __iomem *regs; 64 u_int id; 65 u_int irq; 66 int func_use_count; 67 u_long ref_ps; 68 69 /* 70 * Clock divisors 71 */ 72 u_int divisors[4]; 73 74 struct { 75 u8 red, green, blue; 76 } palette[NR_PALETTE]; 77 78 u_char mem_ctl1; 79 u_char mem_ctl2; 80 u_char mclk_mult; 81 u_char mclk_div; 82 /* 83 * RAMDAC control register is both of these or'ed together 84 */ 85 u_char ramdac_ctrl; 86 u_char ramdac_powerdown; 87 88 u32 pseudo_palette[16]; 89 90 spinlock_t reg_b0_lock; 91 92 #ifdef CONFIG_FB_CYBER2000_DDC 93 bool ddc_registered; 94 struct i2c_adapter ddc_adapter; 95 struct i2c_algo_bit_data ddc_algo; 96 #endif 97 98 #ifdef CONFIG_FB_CYBER2000_I2C 99 struct i2c_adapter i2c_adapter; 100 struct i2c_algo_bit_data i2c_algo; 101 #endif 102 }; 103 104 static char *default_font = "Acorn8x8"; 105 module_param(default_font, charp, 0); 106 MODULE_PARM_DESC(default_font, "Default font name"); 107 108 /* 109 * Our access methods. 110 */ 111 #define cyber2000fb_writel(val, reg, cfb) writel(val, (cfb)->regs + (reg)) 112 #define cyber2000fb_writew(val, reg, cfb) writew(val, (cfb)->regs + (reg)) 113 #define cyber2000fb_writeb(val, reg, cfb) writeb(val, (cfb)->regs + (reg)) 114 115 #define cyber2000fb_readb(reg, cfb) readb((cfb)->regs + (reg)) 116 117 static inline void 118 cyber2000_crtcw(unsigned int reg, unsigned int val, struct cfb_info *cfb) 119 { 120 cyber2000fb_writew((reg & 255) | val << 8, 0x3d4, cfb); 121 } 122 123 static inline void 124 cyber2000_grphw(unsigned int reg, unsigned int val, struct cfb_info *cfb) 125 { 126 cyber2000fb_writew((reg & 255) | val << 8, 0x3ce, cfb); 127 } 128 129 static inline unsigned int 130 cyber2000_grphr(unsigned int reg, struct cfb_info *cfb) 131 { 132 cyber2000fb_writeb(reg, 0x3ce, cfb); 133 return cyber2000fb_readb(0x3cf, cfb); 134 } 135 136 static inline void 137 cyber2000_attrw(unsigned int reg, unsigned int val, struct cfb_info *cfb) 138 { 139 cyber2000fb_readb(0x3da, cfb); 140 cyber2000fb_writeb(reg, 0x3c0, cfb); 141 cyber2000fb_readb(0x3c1, cfb); 142 cyber2000fb_writeb(val, 0x3c0, cfb); 143 } 144 145 static inline void 146 cyber2000_seqw(unsigned int reg, unsigned int val, struct cfb_info *cfb) 147 { 148 cyber2000fb_writew((reg & 255) | val << 8, 0x3c4, cfb); 149 } 150 151 /* -------------------- Hardware specific routines ------------------------- */ 152 153 /* 154 * Hardware Cyber2000 Acceleration 155 */ 156 static void 157 cyber2000fb_fillrect(struct fb_info *info, const struct fb_fillrect *rect) 158 { 159 struct cfb_info *cfb = container_of(info, struct cfb_info, fb); 160 unsigned long dst, col; 161 162 if (!(cfb->fb.var.accel_flags & FB_ACCELF_TEXT)) { 163 cfb_fillrect(info, rect); 164 return; 165 } 166 167 cyber2000fb_writeb(0, CO_REG_CONTROL, cfb); 168 cyber2000fb_writew(rect->width - 1, CO_REG_PIXWIDTH, cfb); 169 cyber2000fb_writew(rect->height - 1, CO_REG_PIXHEIGHT, cfb); 170 171 col = rect->color; 172 if (cfb->fb.var.bits_per_pixel > 8) 173 col = ((u32 *)cfb->fb.pseudo_palette)[col]; 174 cyber2000fb_writel(col, CO_REG_FGCOLOUR, cfb); 175 176 dst = rect->dx + rect->dy * cfb->fb.var.xres_virtual; 177 if (cfb->fb.var.bits_per_pixel == 24) { 178 cyber2000fb_writeb(dst, CO_REG_X_PHASE, cfb); 179 dst *= 3; 180 } 181 182 cyber2000fb_writel(dst, CO_REG_DEST_PTR, cfb); 183 cyber2000fb_writeb(CO_FG_MIX_SRC, CO_REG_FGMIX, cfb); 184 cyber2000fb_writew(CO_CMD_L_PATTERN_FGCOL, CO_REG_CMD_L, cfb); 185 cyber2000fb_writew(CO_CMD_H_BLITTER, CO_REG_CMD_H, cfb); 186 } 187 188 static void 189 cyber2000fb_copyarea(struct fb_info *info, const struct fb_copyarea *region) 190 { 191 struct cfb_info *cfb = container_of(info, struct cfb_info, fb); 192 unsigned int cmd = CO_CMD_L_PATTERN_FGCOL; 193 unsigned long src, dst; 194 195 if (!(cfb->fb.var.accel_flags & FB_ACCELF_TEXT)) { 196 cfb_copyarea(info, region); 197 return; 198 } 199 200 cyber2000fb_writeb(0, CO_REG_CONTROL, cfb); 201 cyber2000fb_writew(region->width - 1, CO_REG_PIXWIDTH, cfb); 202 cyber2000fb_writew(region->height - 1, CO_REG_PIXHEIGHT, cfb); 203 204 src = region->sx + region->sy * cfb->fb.var.xres_virtual; 205 dst = region->dx + region->dy * cfb->fb.var.xres_virtual; 206 207 if (region->sx < region->dx) { 208 src += region->width - 1; 209 dst += region->width - 1; 210 cmd |= CO_CMD_L_INC_LEFT; 211 } 212 213 if (region->sy < region->dy) { 214 src += (region->height - 1) * cfb->fb.var.xres_virtual; 215 dst += (region->height - 1) * cfb->fb.var.xres_virtual; 216 cmd |= CO_CMD_L_INC_UP; 217 } 218 219 if (cfb->fb.var.bits_per_pixel == 24) { 220 cyber2000fb_writeb(dst, CO_REG_X_PHASE, cfb); 221 src *= 3; 222 dst *= 3; 223 } 224 cyber2000fb_writel(src, CO_REG_SRC1_PTR, cfb); 225 cyber2000fb_writel(dst, CO_REG_DEST_PTR, cfb); 226 cyber2000fb_writew(CO_FG_MIX_SRC, CO_REG_FGMIX, cfb); 227 cyber2000fb_writew(cmd, CO_REG_CMD_L, cfb); 228 cyber2000fb_writew(CO_CMD_H_FGSRCMAP | CO_CMD_H_BLITTER, 229 CO_REG_CMD_H, cfb); 230 } 231 232 static void 233 cyber2000fb_imageblit(struct fb_info *info, const struct fb_image *image) 234 { 235 cfb_imageblit(info, image); 236 return; 237 } 238 239 static int cyber2000fb_sync(struct fb_info *info) 240 { 241 struct cfb_info *cfb = container_of(info, struct cfb_info, fb); 242 int count = 100000; 243 244 if (!(cfb->fb.var.accel_flags & FB_ACCELF_TEXT)) 245 return 0; 246 247 while (cyber2000fb_readb(CO_REG_CONTROL, cfb) & CO_CTRL_BUSY) { 248 if (!count--) { 249 debug_printf("accel_wait timed out\n"); 250 cyber2000fb_writeb(0, CO_REG_CONTROL, cfb); 251 break; 252 } 253 udelay(1); 254 } 255 return 0; 256 } 257 258 /* 259 * =========================================================================== 260 */ 261 262 static inline u32 convert_bitfield(u_int val, struct fb_bitfield *bf) 263 { 264 u_int mask = (1 << bf->length) - 1; 265 266 return (val >> (16 - bf->length) & mask) << bf->offset; 267 } 268 269 /* 270 * Set a single color register. Return != 0 for invalid regno. 271 */ 272 static int 273 cyber2000fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, 274 u_int transp, struct fb_info *info) 275 { 276 struct cfb_info *cfb = container_of(info, struct cfb_info, fb); 277 struct fb_var_screeninfo *var = &cfb->fb.var; 278 u32 pseudo_val; 279 int ret = 1; 280 281 switch (cfb->fb.fix.visual) { 282 default: 283 return 1; 284 285 /* 286 * Pseudocolour: 287 * 8 8 288 * pixel --/--+--/--> red lut --> red dac 289 * | 8 290 * +--/--> green lut --> green dac 291 * | 8 292 * +--/--> blue lut --> blue dac 293 */ 294 case FB_VISUAL_PSEUDOCOLOR: 295 if (regno >= NR_PALETTE) 296 return 1; 297 298 red >>= 8; 299 green >>= 8; 300 blue >>= 8; 301 302 cfb->palette[regno].red = red; 303 cfb->palette[regno].green = green; 304 cfb->palette[regno].blue = blue; 305 306 cyber2000fb_writeb(regno, 0x3c8, cfb); 307 cyber2000fb_writeb(red, 0x3c9, cfb); 308 cyber2000fb_writeb(green, 0x3c9, cfb); 309 cyber2000fb_writeb(blue, 0x3c9, cfb); 310 return 0; 311 312 /* 313 * Direct colour: 314 * n rl 315 * pixel --/--+--/--> red lut --> red dac 316 * | gl 317 * +--/--> green lut --> green dac 318 * | bl 319 * +--/--> blue lut --> blue dac 320 * n = bpp, rl = red length, gl = green length, bl = blue length 321 */ 322 case FB_VISUAL_DIRECTCOLOR: 323 red >>= 8; 324 green >>= 8; 325 blue >>= 8; 326 327 if (var->green.length == 6 && regno < 64) { 328 cfb->palette[regno << 2].green = green; 329 330 /* 331 * The 6 bits of the green component are applied 332 * to the high 6 bits of the LUT. 333 */ 334 cyber2000fb_writeb(regno << 2, 0x3c8, cfb); 335 cyber2000fb_writeb(cfb->palette[regno >> 1].red, 336 0x3c9, cfb); 337 cyber2000fb_writeb(green, 0x3c9, cfb); 338 cyber2000fb_writeb(cfb->palette[regno >> 1].blue, 339 0x3c9, cfb); 340 341 green = cfb->palette[regno << 3].green; 342 343 ret = 0; 344 } 345 346 if (var->green.length >= 5 && regno < 32) { 347 cfb->palette[regno << 3].red = red; 348 cfb->palette[regno << 3].green = green; 349 cfb->palette[regno << 3].blue = blue; 350 351 /* 352 * The 5 bits of each colour component are 353 * applied to the high 5 bits of the LUT. 354 */ 355 cyber2000fb_writeb(regno << 3, 0x3c8, cfb); 356 cyber2000fb_writeb(red, 0x3c9, cfb); 357 cyber2000fb_writeb(green, 0x3c9, cfb); 358 cyber2000fb_writeb(blue, 0x3c9, cfb); 359 ret = 0; 360 } 361 362 if (var->green.length == 4 && regno < 16) { 363 cfb->palette[regno << 4].red = red; 364 cfb->palette[regno << 4].green = green; 365 cfb->palette[regno << 4].blue = blue; 366 367 /* 368 * The 5 bits of each colour component are 369 * applied to the high 5 bits of the LUT. 370 */ 371 cyber2000fb_writeb(regno << 4, 0x3c8, cfb); 372 cyber2000fb_writeb(red, 0x3c9, cfb); 373 cyber2000fb_writeb(green, 0x3c9, cfb); 374 cyber2000fb_writeb(blue, 0x3c9, cfb); 375 ret = 0; 376 } 377 378 /* 379 * Since this is only used for the first 16 colours, we 380 * don't have to care about overflowing for regno >= 32 381 */ 382 pseudo_val = regno << var->red.offset | 383 regno << var->green.offset | 384 regno << var->blue.offset; 385 break; 386 387 /* 388 * True colour: 389 * n rl 390 * pixel --/--+--/--> red dac 391 * | gl 392 * +--/--> green dac 393 * | bl 394 * +--/--> blue dac 395 * n = bpp, rl = red length, gl = green length, bl = blue length 396 */ 397 case FB_VISUAL_TRUECOLOR: 398 pseudo_val = convert_bitfield(transp ^ 0xffff, &var->transp); 399 pseudo_val |= convert_bitfield(red, &var->red); 400 pseudo_val |= convert_bitfield(green, &var->green); 401 pseudo_val |= convert_bitfield(blue, &var->blue); 402 ret = 0; 403 break; 404 } 405 406 /* 407 * Now set our pseudo palette for the CFB16/24/32 drivers. 408 */ 409 if (regno < 16) 410 ((u32 *)cfb->fb.pseudo_palette)[regno] = pseudo_val; 411 412 return ret; 413 } 414 415 struct par_info { 416 /* 417 * Hardware 418 */ 419 u_char clock_mult; 420 u_char clock_div; 421 u_char extseqmisc; 422 u_char co_pixfmt; 423 u_char crtc_ofl; 424 u_char crtc[19]; 425 u_int width; 426 u_int pitch; 427 u_int fetch; 428 429 /* 430 * Other 431 */ 432 u_char ramdac; 433 }; 434 435 static const u_char crtc_idx[] = { 436 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 437 0x08, 0x09, 438 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18 439 }; 440 441 static void cyber2000fb_write_ramdac_ctrl(struct cfb_info *cfb) 442 { 443 unsigned int i; 444 unsigned int val = cfb->ramdac_ctrl | cfb->ramdac_powerdown; 445 446 cyber2000fb_writeb(0x56, 0x3ce, cfb); 447 i = cyber2000fb_readb(0x3cf, cfb); 448 cyber2000fb_writeb(i | 4, 0x3cf, cfb); 449 cyber2000fb_writeb(val, 0x3c6, cfb); 450 cyber2000fb_writeb(i, 0x3cf, cfb); 451 /* prevent card lock-up observed on x86 with CyberPro 2000 */ 452 cyber2000fb_readb(0x3cf, cfb); 453 } 454 455 static void cyber2000fb_set_timing(struct cfb_info *cfb, struct par_info *hw) 456 { 457 u_int i; 458 459 /* 460 * Blank palette 461 */ 462 for (i = 0; i < NR_PALETTE; i++) { 463 cyber2000fb_writeb(i, 0x3c8, cfb); 464 cyber2000fb_writeb(0, 0x3c9, cfb); 465 cyber2000fb_writeb(0, 0x3c9, cfb); 466 cyber2000fb_writeb(0, 0x3c9, cfb); 467 } 468 469 cyber2000fb_writeb(0xef, 0x3c2, cfb); 470 cyber2000_crtcw(0x11, 0x0b, cfb); 471 cyber2000_attrw(0x11, 0x00, cfb); 472 473 cyber2000_seqw(0x00, 0x01, cfb); 474 cyber2000_seqw(0x01, 0x01, cfb); 475 cyber2000_seqw(0x02, 0x0f, cfb); 476 cyber2000_seqw(0x03, 0x00, cfb); 477 cyber2000_seqw(0x04, 0x0e, cfb); 478 cyber2000_seqw(0x00, 0x03, cfb); 479 480 for (i = 0; i < sizeof(crtc_idx); i++) 481 cyber2000_crtcw(crtc_idx[i], hw->crtc[i], cfb); 482 483 for (i = 0x0a; i < 0x10; i++) 484 cyber2000_crtcw(i, 0, cfb); 485 486 cyber2000_grphw(EXT_CRT_VRTOFL, hw->crtc_ofl, cfb); 487 cyber2000_grphw(0x00, 0x00, cfb); 488 cyber2000_grphw(0x01, 0x00, cfb); 489 cyber2000_grphw(0x02, 0x00, cfb); 490 cyber2000_grphw(0x03, 0x00, cfb); 491 cyber2000_grphw(0x04, 0x00, cfb); 492 cyber2000_grphw(0x05, 0x60, cfb); 493 cyber2000_grphw(0x06, 0x05, cfb); 494 cyber2000_grphw(0x07, 0x0f, cfb); 495 cyber2000_grphw(0x08, 0xff, cfb); 496 497 /* Attribute controller registers */ 498 for (i = 0; i < 16; i++) 499 cyber2000_attrw(i, i, cfb); 500 501 cyber2000_attrw(0x10, 0x01, cfb); 502 cyber2000_attrw(0x11, 0x00, cfb); 503 cyber2000_attrw(0x12, 0x0f, cfb); 504 cyber2000_attrw(0x13, 0x00, cfb); 505 cyber2000_attrw(0x14, 0x00, cfb); 506 507 /* PLL registers */ 508 spin_lock(&cfb->reg_b0_lock); 509 cyber2000_grphw(EXT_DCLK_MULT, hw->clock_mult, cfb); 510 cyber2000_grphw(EXT_DCLK_DIV, hw->clock_div, cfb); 511 cyber2000_grphw(EXT_MCLK_MULT, cfb->mclk_mult, cfb); 512 cyber2000_grphw(EXT_MCLK_DIV, cfb->mclk_div, cfb); 513 cyber2000_grphw(0x90, 0x01, cfb); 514 cyber2000_grphw(0xb9, 0x80, cfb); 515 cyber2000_grphw(0xb9, 0x00, cfb); 516 spin_unlock(&cfb->reg_b0_lock); 517 518 cfb->ramdac_ctrl = hw->ramdac; 519 cyber2000fb_write_ramdac_ctrl(cfb); 520 521 cyber2000fb_writeb(0x20, 0x3c0, cfb); 522 cyber2000fb_writeb(0xff, 0x3c6, cfb); 523 524 cyber2000_grphw(0x14, hw->fetch, cfb); 525 cyber2000_grphw(0x15, ((hw->fetch >> 8) & 0x03) | 526 ((hw->pitch >> 4) & 0x30), cfb); 527 cyber2000_grphw(EXT_SEQ_MISC, hw->extseqmisc, cfb); 528 529 /* 530 * Set up accelerator registers 531 */ 532 cyber2000fb_writew(hw->width, CO_REG_SRC_WIDTH, cfb); 533 cyber2000fb_writew(hw->width, CO_REG_DEST_WIDTH, cfb); 534 cyber2000fb_writeb(hw->co_pixfmt, CO_REG_PIXFMT, cfb); 535 } 536 537 static inline int 538 cyber2000fb_update_start(struct cfb_info *cfb, struct fb_var_screeninfo *var) 539 { 540 u_int base = var->yoffset * var->xres_virtual + var->xoffset; 541 542 base *= var->bits_per_pixel; 543 544 /* 545 * Convert to bytes and shift two extra bits because DAC 546 * can only start on 4 byte aligned data. 547 */ 548 base >>= 5; 549 550 if (base >= 1 << 20) 551 return -EINVAL; 552 553 cyber2000_grphw(0x10, base >> 16 | 0x10, cfb); 554 cyber2000_crtcw(0x0c, base >> 8, cfb); 555 cyber2000_crtcw(0x0d, base, cfb); 556 557 return 0; 558 } 559 560 static int 561 cyber2000fb_decode_crtc(struct par_info *hw, struct cfb_info *cfb, 562 struct fb_var_screeninfo *var) 563 { 564 u_int Htotal, Hblankend, Hsyncend; 565 u_int Vtotal, Vdispend, Vblankstart, Vblankend, Vsyncstart, Vsyncend; 566 #define ENCODE_BIT(v, b1, m, b2) ((((v) >> (b1)) & (m)) << (b2)) 567 568 hw->crtc[13] = hw->pitch; 569 hw->crtc[17] = 0xe3; 570 hw->crtc[14] = 0; 571 hw->crtc[8] = 0; 572 573 Htotal = var->xres + var->right_margin + 574 var->hsync_len + var->left_margin; 575 576 if (Htotal > 2080) 577 return -EINVAL; 578 579 hw->crtc[0] = (Htotal >> 3) - 5; 580 hw->crtc[1] = (var->xres >> 3) - 1; 581 hw->crtc[2] = var->xres >> 3; 582 hw->crtc[4] = (var->xres + var->right_margin) >> 3; 583 584 Hblankend = (Htotal - 4 * 8) >> 3; 585 586 hw->crtc[3] = ENCODE_BIT(Hblankend, 0, 0x1f, 0) | 587 ENCODE_BIT(1, 0, 0x01, 7); 588 589 Hsyncend = (var->xres + var->right_margin + var->hsync_len) >> 3; 590 591 hw->crtc[5] = ENCODE_BIT(Hsyncend, 0, 0x1f, 0) | 592 ENCODE_BIT(Hblankend, 5, 0x01, 7); 593 594 Vdispend = var->yres - 1; 595 Vsyncstart = var->yres + var->lower_margin; 596 Vsyncend = var->yres + var->lower_margin + var->vsync_len; 597 Vtotal = var->yres + var->lower_margin + var->vsync_len + 598 var->upper_margin - 2; 599 600 if (Vtotal > 2047) 601 return -EINVAL; 602 603 Vblankstart = var->yres + 6; 604 Vblankend = Vtotal - 10; 605 606 hw->crtc[6] = Vtotal; 607 hw->crtc[7] = ENCODE_BIT(Vtotal, 8, 0x01, 0) | 608 ENCODE_BIT(Vdispend, 8, 0x01, 1) | 609 ENCODE_BIT(Vsyncstart, 8, 0x01, 2) | 610 ENCODE_BIT(Vblankstart, 8, 0x01, 3) | 611 ENCODE_BIT(1, 0, 0x01, 4) | 612 ENCODE_BIT(Vtotal, 9, 0x01, 5) | 613 ENCODE_BIT(Vdispend, 9, 0x01, 6) | 614 ENCODE_BIT(Vsyncstart, 9, 0x01, 7); 615 hw->crtc[9] = ENCODE_BIT(0, 0, 0x1f, 0) | 616 ENCODE_BIT(Vblankstart, 9, 0x01, 5) | 617 ENCODE_BIT(1, 0, 0x01, 6); 618 hw->crtc[10] = Vsyncstart; 619 hw->crtc[11] = ENCODE_BIT(Vsyncend, 0, 0x0f, 0) | 620 ENCODE_BIT(1, 0, 0x01, 7); 621 hw->crtc[12] = Vdispend; 622 hw->crtc[15] = Vblankstart; 623 hw->crtc[16] = Vblankend; 624 hw->crtc[18] = 0xff; 625 626 /* 627 * overflow - graphics reg 0x11 628 * 0=VTOTAL:10 1=VDEND:10 2=VRSTART:10 3=VBSTART:10 629 * 4=LINECOMP:10 5-IVIDEO 6=FIXCNT 630 */ 631 hw->crtc_ofl = 632 ENCODE_BIT(Vtotal, 10, 0x01, 0) | 633 ENCODE_BIT(Vdispend, 10, 0x01, 1) | 634 ENCODE_BIT(Vsyncstart, 10, 0x01, 2) | 635 ENCODE_BIT(Vblankstart, 10, 0x01, 3) | 636 EXT_CRT_VRTOFL_LINECOMP10; 637 638 /* woody: set the interlaced bit... */ 639 /* FIXME: what about doublescan? */ 640 if ((var->vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) 641 hw->crtc_ofl |= EXT_CRT_VRTOFL_INTERLACE; 642 643 return 0; 644 } 645 646 /* 647 * The following was discovered by a good monitor, bit twiddling, theorising 648 * and but mostly luck. Strangely, it looks like everyone elses' PLL! 649 * 650 * Clock registers: 651 * fclock = fpll / div2 652 * fpll = fref * mult / div1 653 * where: 654 * fref = 14.318MHz (69842ps) 655 * mult = reg0xb0.7:0 656 * div1 = (reg0xb1.5:0 + 1) 657 * div2 = 2^(reg0xb1.7:6) 658 * fpll should be between 115 and 260 MHz 659 * (8696ps and 3846ps) 660 */ 661 static int 662 cyber2000fb_decode_clock(struct par_info *hw, struct cfb_info *cfb, 663 struct fb_var_screeninfo *var) 664 { 665 u_long pll_ps = var->pixclock; 666 const u_long ref_ps = cfb->ref_ps; 667 u_int div2, t_div1, best_div1, best_mult; 668 int best_diff; 669 int vco; 670 671 /* 672 * Step 1: 673 * find div2 such that 115MHz < fpll < 260MHz 674 * and 0 <= div2 < 4 675 */ 676 for (div2 = 0; div2 < 4; div2++) { 677 u_long new_pll; 678 679 new_pll = pll_ps / cfb->divisors[div2]; 680 if (8696 > new_pll && new_pll > 3846) { 681 pll_ps = new_pll; 682 break; 683 } 684 } 685 686 if (div2 == 4) 687 return -EINVAL; 688 689 /* 690 * Step 2: 691 * Given pll_ps and ref_ps, find: 692 * pll_ps * 0.995 < pll_ps_calc < pll_ps * 1.005 693 * where { 1 < best_div1 < 32, 1 < best_mult < 256 } 694 * pll_ps_calc = best_div1 / (ref_ps * best_mult) 695 */ 696 best_diff = 0x7fffffff; 697 best_mult = 2; 698 best_div1 = 32; 699 for (t_div1 = 2; t_div1 < 32; t_div1 += 1) { 700 u_int rr, t_mult, t_pll_ps; 701 int diff; 702 703 /* 704 * Find the multiplier for this divisor 705 */ 706 rr = ref_ps * t_div1; 707 t_mult = (rr + pll_ps / 2) / pll_ps; 708 709 /* 710 * Is the multiplier within the correct range? 711 */ 712 if (t_mult > 256 || t_mult < 2) 713 continue; 714 715 /* 716 * Calculate the actual clock period from this multiplier 717 * and divisor, and estimate the error. 718 */ 719 t_pll_ps = (rr + t_mult / 2) / t_mult; 720 diff = pll_ps - t_pll_ps; 721 if (diff < 0) 722 diff = -diff; 723 724 if (diff < best_diff) { 725 best_diff = diff; 726 best_mult = t_mult; 727 best_div1 = t_div1; 728 } 729 730 /* 731 * If we hit an exact value, there is no point in continuing. 732 */ 733 if (diff == 0) 734 break; 735 } 736 737 /* 738 * Step 3: 739 * combine values 740 */ 741 hw->clock_mult = best_mult - 1; 742 hw->clock_div = div2 << 6 | (best_div1 - 1); 743 744 vco = ref_ps * best_div1 / best_mult; 745 if ((ref_ps == 40690) && (vco < 5556)) 746 /* Set VFSEL when VCO > 180MHz (5.556 ps). */ 747 hw->clock_div |= EXT_DCLK_DIV_VFSEL; 748 749 return 0; 750 } 751 752 /* 753 * Set the User Defined Part of the Display 754 */ 755 static int 756 cyber2000fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) 757 { 758 struct cfb_info *cfb = container_of(info, struct cfb_info, fb); 759 struct par_info hw; 760 unsigned int mem; 761 int err; 762 763 var->transp.msb_right = 0; 764 var->red.msb_right = 0; 765 var->green.msb_right = 0; 766 var->blue.msb_right = 0; 767 var->transp.offset = 0; 768 var->transp.length = 0; 769 770 switch (var->bits_per_pixel) { 771 case 8: /* PSEUDOCOLOUR, 256 */ 772 var->red.offset = 0; 773 var->red.length = 8; 774 var->green.offset = 0; 775 var->green.length = 8; 776 var->blue.offset = 0; 777 var->blue.length = 8; 778 break; 779 780 case 16:/* DIRECTCOLOUR, 64k or 32k */ 781 switch (var->green.length) { 782 case 6: /* RGB565, 64k */ 783 var->red.offset = 11; 784 var->red.length = 5; 785 var->green.offset = 5; 786 var->green.length = 6; 787 var->blue.offset = 0; 788 var->blue.length = 5; 789 break; 790 791 default: 792 case 5: /* RGB555, 32k */ 793 var->red.offset = 10; 794 var->red.length = 5; 795 var->green.offset = 5; 796 var->green.length = 5; 797 var->blue.offset = 0; 798 var->blue.length = 5; 799 break; 800 801 case 4: /* RGB444, 4k + transparency? */ 802 var->transp.offset = 12; 803 var->transp.length = 4; 804 var->red.offset = 8; 805 var->red.length = 4; 806 var->green.offset = 4; 807 var->green.length = 4; 808 var->blue.offset = 0; 809 var->blue.length = 4; 810 break; 811 } 812 break; 813 814 case 24:/* TRUECOLOUR, 16m */ 815 var->red.offset = 16; 816 var->red.length = 8; 817 var->green.offset = 8; 818 var->green.length = 8; 819 var->blue.offset = 0; 820 var->blue.length = 8; 821 break; 822 823 case 32:/* TRUECOLOUR, 16m */ 824 var->transp.offset = 24; 825 var->transp.length = 8; 826 var->red.offset = 16; 827 var->red.length = 8; 828 var->green.offset = 8; 829 var->green.length = 8; 830 var->blue.offset = 0; 831 var->blue.length = 8; 832 break; 833 834 default: 835 return -EINVAL; 836 } 837 838 mem = var->xres_virtual * var->yres_virtual * (var->bits_per_pixel / 8); 839 if (mem > cfb->fb.fix.smem_len) 840 var->yres_virtual = cfb->fb.fix.smem_len * 8 / 841 (var->bits_per_pixel * var->xres_virtual); 842 843 if (var->yres > var->yres_virtual) 844 var->yres = var->yres_virtual; 845 if (var->xres > var->xres_virtual) 846 var->xres = var->xres_virtual; 847 848 err = cyber2000fb_decode_clock(&hw, cfb, var); 849 if (err) 850 return err; 851 852 err = cyber2000fb_decode_crtc(&hw, cfb, var); 853 if (err) 854 return err; 855 856 return 0; 857 } 858 859 static int cyber2000fb_set_par(struct fb_info *info) 860 { 861 struct cfb_info *cfb = container_of(info, struct cfb_info, fb); 862 struct fb_var_screeninfo *var = &cfb->fb.var; 863 struct par_info hw; 864 unsigned int mem; 865 866 hw.width = var->xres_virtual; 867 hw.ramdac = RAMDAC_VREFEN | RAMDAC_DAC8BIT; 868 869 switch (var->bits_per_pixel) { 870 case 8: 871 hw.co_pixfmt = CO_PIXFMT_8BPP; 872 hw.pitch = hw.width >> 3; 873 hw.extseqmisc = EXT_SEQ_MISC_8; 874 break; 875 876 case 16: 877 hw.co_pixfmt = CO_PIXFMT_16BPP; 878 hw.pitch = hw.width >> 2; 879 880 switch (var->green.length) { 881 case 6: /* RGB565, 64k */ 882 hw.extseqmisc = EXT_SEQ_MISC_16_RGB565; 883 break; 884 case 5: /* RGB555, 32k */ 885 hw.extseqmisc = EXT_SEQ_MISC_16_RGB555; 886 break; 887 case 4: /* RGB444, 4k + transparency? */ 888 hw.extseqmisc = EXT_SEQ_MISC_16_RGB444; 889 break; 890 default: 891 BUG(); 892 } 893 break; 894 895 case 24:/* TRUECOLOUR, 16m */ 896 hw.co_pixfmt = CO_PIXFMT_24BPP; 897 hw.width *= 3; 898 hw.pitch = hw.width >> 3; 899 hw.ramdac |= (RAMDAC_BYPASS | RAMDAC_RAMPWRDN); 900 hw.extseqmisc = EXT_SEQ_MISC_24_RGB888; 901 break; 902 903 case 32:/* TRUECOLOUR, 16m */ 904 hw.co_pixfmt = CO_PIXFMT_32BPP; 905 hw.pitch = hw.width >> 1; 906 hw.ramdac |= (RAMDAC_BYPASS | RAMDAC_RAMPWRDN); 907 hw.extseqmisc = EXT_SEQ_MISC_32; 908 break; 909 910 default: 911 BUG(); 912 } 913 914 /* 915 * Sigh, this is absolutely disgusting, but caused by 916 * the way the fbcon developers want to separate out 917 * the "checking" and the "setting" of the video mode. 918 * 919 * If the mode is not suitable for the hardware here, 920 * we can't prevent it being set by returning an error. 921 * 922 * In theory, since NetWinders contain just one VGA card, 923 * we should never end up hitting this problem. 924 */ 925 BUG_ON(cyber2000fb_decode_clock(&hw, cfb, var) != 0); 926 BUG_ON(cyber2000fb_decode_crtc(&hw, cfb, var) != 0); 927 928 hw.width -= 1; 929 hw.fetch = hw.pitch; 930 if (!(cfb->mem_ctl2 & MEM_CTL2_64BIT)) 931 hw.fetch <<= 1; 932 hw.fetch += 1; 933 934 cfb->fb.fix.line_length = var->xres_virtual * var->bits_per_pixel / 8; 935 936 /* 937 * Same here - if the size of the video mode exceeds the 938 * available RAM, we can't prevent this mode being set. 939 * 940 * In theory, since NetWinders contain just one VGA card, 941 * we should never end up hitting this problem. 942 */ 943 mem = cfb->fb.fix.line_length * var->yres_virtual; 944 BUG_ON(mem > cfb->fb.fix.smem_len); 945 946 /* 947 * 8bpp displays are always pseudo colour. 16bpp and above 948 * are direct colour or true colour, depending on whether 949 * the RAMDAC palettes are bypassed. (Direct colour has 950 * palettes, true colour does not.) 951 */ 952 if (var->bits_per_pixel == 8) 953 cfb->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR; 954 else if (hw.ramdac & RAMDAC_BYPASS) 955 cfb->fb.fix.visual = FB_VISUAL_TRUECOLOR; 956 else 957 cfb->fb.fix.visual = FB_VISUAL_DIRECTCOLOR; 958 959 cyber2000fb_set_timing(cfb, &hw); 960 cyber2000fb_update_start(cfb, var); 961 962 return 0; 963 } 964 965 /* 966 * Pan or Wrap the Display 967 */ 968 static int 969 cyber2000fb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info) 970 { 971 struct cfb_info *cfb = container_of(info, struct cfb_info, fb); 972 973 if (cyber2000fb_update_start(cfb, var)) 974 return -EINVAL; 975 976 cfb->fb.var.xoffset = var->xoffset; 977 cfb->fb.var.yoffset = var->yoffset; 978 979 if (var->vmode & FB_VMODE_YWRAP) { 980 cfb->fb.var.vmode |= FB_VMODE_YWRAP; 981 } else { 982 cfb->fb.var.vmode &= ~FB_VMODE_YWRAP; 983 } 984 985 return 0; 986 } 987 988 /* 989 * (Un)Blank the display. 990 * 991 * Blank the screen if blank_mode != 0, else unblank. If 992 * blank == NULL then the caller blanks by setting the CLUT 993 * (Color Look Up Table) to all black. Return 0 if blanking 994 * succeeded, != 0 if un-/blanking failed due to e.g. a 995 * video mode which doesn't support it. Implements VESA 996 * suspend and powerdown modes on hardware that supports 997 * disabling hsync/vsync: 998 * blank_mode == 2: suspend vsync 999 * blank_mode == 3: suspend hsync 1000 * blank_mode == 4: powerdown 1001 * 1002 * wms...Enable VESA DMPS compatible powerdown mode 1003 * run "setterm -powersave powerdown" to take advantage 1004 */ 1005 static int cyber2000fb_blank(int blank, struct fb_info *info) 1006 { 1007 struct cfb_info *cfb = container_of(info, struct cfb_info, fb); 1008 unsigned int sync = 0; 1009 int i; 1010 1011 switch (blank) { 1012 case FB_BLANK_POWERDOWN: /* powerdown - both sync lines down */ 1013 sync = EXT_SYNC_CTL_VS_0 | EXT_SYNC_CTL_HS_0; 1014 break; 1015 case FB_BLANK_HSYNC_SUSPEND: /* hsync off */ 1016 sync = EXT_SYNC_CTL_VS_NORMAL | EXT_SYNC_CTL_HS_0; 1017 break; 1018 case FB_BLANK_VSYNC_SUSPEND: /* vsync off */ 1019 sync = EXT_SYNC_CTL_VS_0 | EXT_SYNC_CTL_HS_NORMAL; 1020 break; 1021 case FB_BLANK_NORMAL: /* soft blank */ 1022 default: /* unblank */ 1023 break; 1024 } 1025 1026 cyber2000_grphw(EXT_SYNC_CTL, sync, cfb); 1027 1028 if (blank <= 1) { 1029 /* turn on ramdacs */ 1030 cfb->ramdac_powerdown &= ~(RAMDAC_DACPWRDN | RAMDAC_BYPASS | 1031 RAMDAC_RAMPWRDN); 1032 cyber2000fb_write_ramdac_ctrl(cfb); 1033 } 1034 1035 /* 1036 * Soft blank/unblank the display. 1037 */ 1038 if (blank) { /* soft blank */ 1039 for (i = 0; i < NR_PALETTE; i++) { 1040 cyber2000fb_writeb(i, 0x3c8, cfb); 1041 cyber2000fb_writeb(0, 0x3c9, cfb); 1042 cyber2000fb_writeb(0, 0x3c9, cfb); 1043 cyber2000fb_writeb(0, 0x3c9, cfb); 1044 } 1045 } else { /* unblank */ 1046 for (i = 0; i < NR_PALETTE; i++) { 1047 cyber2000fb_writeb(i, 0x3c8, cfb); 1048 cyber2000fb_writeb(cfb->palette[i].red, 0x3c9, cfb); 1049 cyber2000fb_writeb(cfb->palette[i].green, 0x3c9, cfb); 1050 cyber2000fb_writeb(cfb->palette[i].blue, 0x3c9, cfb); 1051 } 1052 } 1053 1054 if (blank >= 2) { 1055 /* turn off ramdacs */ 1056 cfb->ramdac_powerdown |= RAMDAC_DACPWRDN | RAMDAC_BYPASS | 1057 RAMDAC_RAMPWRDN; 1058 cyber2000fb_write_ramdac_ctrl(cfb); 1059 } 1060 1061 return 0; 1062 } 1063 1064 static struct fb_ops cyber2000fb_ops = { 1065 .owner = THIS_MODULE, 1066 .fb_check_var = cyber2000fb_check_var, 1067 .fb_set_par = cyber2000fb_set_par, 1068 .fb_setcolreg = cyber2000fb_setcolreg, 1069 .fb_blank = cyber2000fb_blank, 1070 .fb_pan_display = cyber2000fb_pan_display, 1071 .fb_fillrect = cyber2000fb_fillrect, 1072 .fb_copyarea = cyber2000fb_copyarea, 1073 .fb_imageblit = cyber2000fb_imageblit, 1074 .fb_sync = cyber2000fb_sync, 1075 }; 1076 1077 /* 1078 * This is the only "static" reference to the internal data structures 1079 * of this driver. It is here solely at the moment to support the other 1080 * CyberPro modules external to this driver. 1081 */ 1082 static struct cfb_info *int_cfb_info; 1083 1084 /* 1085 * Enable access to the extended registers 1086 */ 1087 void cyber2000fb_enable_extregs(struct cfb_info *cfb) 1088 { 1089 cfb->func_use_count += 1; 1090 1091 if (cfb->func_use_count == 1) { 1092 int old; 1093 1094 old = cyber2000_grphr(EXT_FUNC_CTL, cfb); 1095 old |= EXT_FUNC_CTL_EXTREGENBL; 1096 cyber2000_grphw(EXT_FUNC_CTL, old, cfb); 1097 } 1098 } 1099 EXPORT_SYMBOL(cyber2000fb_enable_extregs); 1100 1101 /* 1102 * Disable access to the extended registers 1103 */ 1104 void cyber2000fb_disable_extregs(struct cfb_info *cfb) 1105 { 1106 if (cfb->func_use_count == 1) { 1107 int old; 1108 1109 old = cyber2000_grphr(EXT_FUNC_CTL, cfb); 1110 old &= ~EXT_FUNC_CTL_EXTREGENBL; 1111 cyber2000_grphw(EXT_FUNC_CTL, old, cfb); 1112 } 1113 1114 if (cfb->func_use_count == 0) 1115 printk(KERN_ERR "disable_extregs: count = 0\n"); 1116 else 1117 cfb->func_use_count -= 1; 1118 } 1119 EXPORT_SYMBOL(cyber2000fb_disable_extregs); 1120 1121 /* 1122 * Attach a capture/tv driver to the core CyberX0X0 driver. 1123 */ 1124 int cyber2000fb_attach(struct cyberpro_info *info, int idx) 1125 { 1126 if (int_cfb_info != NULL) { 1127 info->dev = int_cfb_info->fb.device; 1128 #ifdef CONFIG_FB_CYBER2000_I2C 1129 info->i2c = &int_cfb_info->i2c_adapter; 1130 #else 1131 info->i2c = NULL; 1132 #endif 1133 info->regs = int_cfb_info->regs; 1134 info->irq = int_cfb_info->irq; 1135 info->fb = int_cfb_info->fb.screen_base; 1136 info->fb_size = int_cfb_info->fb.fix.smem_len; 1137 info->info = int_cfb_info; 1138 1139 strlcpy(info->dev_name, int_cfb_info->fb.fix.id, 1140 sizeof(info->dev_name)); 1141 } 1142 1143 return int_cfb_info != NULL; 1144 } 1145 EXPORT_SYMBOL(cyber2000fb_attach); 1146 1147 /* 1148 * Detach a capture/tv driver from the core CyberX0X0 driver. 1149 */ 1150 void cyber2000fb_detach(int idx) 1151 { 1152 } 1153 EXPORT_SYMBOL(cyber2000fb_detach); 1154 1155 #ifdef CONFIG_FB_CYBER2000_DDC 1156 1157 #define DDC_REG 0xb0 1158 #define DDC_SCL_OUT (1 << 0) 1159 #define DDC_SDA_OUT (1 << 4) 1160 #define DDC_SCL_IN (1 << 2) 1161 #define DDC_SDA_IN (1 << 6) 1162 1163 static void cyber2000fb_enable_ddc(struct cfb_info *cfb) 1164 { 1165 spin_lock(&cfb->reg_b0_lock); 1166 cyber2000fb_writew(0x1bf, 0x3ce, cfb); 1167 } 1168 1169 static void cyber2000fb_disable_ddc(struct cfb_info *cfb) 1170 { 1171 cyber2000fb_writew(0x0bf, 0x3ce, cfb); 1172 spin_unlock(&cfb->reg_b0_lock); 1173 } 1174 1175 1176 static void cyber2000fb_ddc_setscl(void *data, int val) 1177 { 1178 struct cfb_info *cfb = data; 1179 unsigned char reg; 1180 1181 cyber2000fb_enable_ddc(cfb); 1182 reg = cyber2000_grphr(DDC_REG, cfb); 1183 if (!val) /* bit is inverted */ 1184 reg |= DDC_SCL_OUT; 1185 else 1186 reg &= ~DDC_SCL_OUT; 1187 cyber2000_grphw(DDC_REG, reg, cfb); 1188 cyber2000fb_disable_ddc(cfb); 1189 } 1190 1191 static void cyber2000fb_ddc_setsda(void *data, int val) 1192 { 1193 struct cfb_info *cfb = data; 1194 unsigned char reg; 1195 1196 cyber2000fb_enable_ddc(cfb); 1197 reg = cyber2000_grphr(DDC_REG, cfb); 1198 if (!val) /* bit is inverted */ 1199 reg |= DDC_SDA_OUT; 1200 else 1201 reg &= ~DDC_SDA_OUT; 1202 cyber2000_grphw(DDC_REG, reg, cfb); 1203 cyber2000fb_disable_ddc(cfb); 1204 } 1205 1206 static int cyber2000fb_ddc_getscl(void *data) 1207 { 1208 struct cfb_info *cfb = data; 1209 int retval; 1210 1211 cyber2000fb_enable_ddc(cfb); 1212 retval = !!(cyber2000_grphr(DDC_REG, cfb) & DDC_SCL_IN); 1213 cyber2000fb_disable_ddc(cfb); 1214 1215 return retval; 1216 } 1217 1218 static int cyber2000fb_ddc_getsda(void *data) 1219 { 1220 struct cfb_info *cfb = data; 1221 int retval; 1222 1223 cyber2000fb_enable_ddc(cfb); 1224 retval = !!(cyber2000_grphr(DDC_REG, cfb) & DDC_SDA_IN); 1225 cyber2000fb_disable_ddc(cfb); 1226 1227 return retval; 1228 } 1229 1230 static int cyber2000fb_setup_ddc_bus(struct cfb_info *cfb) 1231 { 1232 strlcpy(cfb->ddc_adapter.name, cfb->fb.fix.id, 1233 sizeof(cfb->ddc_adapter.name)); 1234 cfb->ddc_adapter.owner = THIS_MODULE; 1235 cfb->ddc_adapter.class = I2C_CLASS_DDC; 1236 cfb->ddc_adapter.algo_data = &cfb->ddc_algo; 1237 cfb->ddc_adapter.dev.parent = cfb->fb.device; 1238 cfb->ddc_algo.setsda = cyber2000fb_ddc_setsda; 1239 cfb->ddc_algo.setscl = cyber2000fb_ddc_setscl; 1240 cfb->ddc_algo.getsda = cyber2000fb_ddc_getsda; 1241 cfb->ddc_algo.getscl = cyber2000fb_ddc_getscl; 1242 cfb->ddc_algo.udelay = 10; 1243 cfb->ddc_algo.timeout = 20; 1244 cfb->ddc_algo.data = cfb; 1245 1246 i2c_set_adapdata(&cfb->ddc_adapter, cfb); 1247 1248 return i2c_bit_add_bus(&cfb->ddc_adapter); 1249 } 1250 #endif /* CONFIG_FB_CYBER2000_DDC */ 1251 1252 #ifdef CONFIG_FB_CYBER2000_I2C 1253 static void cyber2000fb_i2c_setsda(void *data, int state) 1254 { 1255 struct cfb_info *cfb = data; 1256 unsigned int latch2; 1257 1258 spin_lock(&cfb->reg_b0_lock); 1259 latch2 = cyber2000_grphr(EXT_LATCH2, cfb); 1260 latch2 &= EXT_LATCH2_I2C_CLKEN; 1261 if (state) 1262 latch2 |= EXT_LATCH2_I2C_DATEN; 1263 cyber2000_grphw(EXT_LATCH2, latch2, cfb); 1264 spin_unlock(&cfb->reg_b0_lock); 1265 } 1266 1267 static void cyber2000fb_i2c_setscl(void *data, int state) 1268 { 1269 struct cfb_info *cfb = data; 1270 unsigned int latch2; 1271 1272 spin_lock(&cfb->reg_b0_lock); 1273 latch2 = cyber2000_grphr(EXT_LATCH2, cfb); 1274 latch2 &= EXT_LATCH2_I2C_DATEN; 1275 if (state) 1276 latch2 |= EXT_LATCH2_I2C_CLKEN; 1277 cyber2000_grphw(EXT_LATCH2, latch2, cfb); 1278 spin_unlock(&cfb->reg_b0_lock); 1279 } 1280 1281 static int cyber2000fb_i2c_getsda(void *data) 1282 { 1283 struct cfb_info *cfb = data; 1284 int ret; 1285 1286 spin_lock(&cfb->reg_b0_lock); 1287 ret = !!(cyber2000_grphr(EXT_LATCH2, cfb) & EXT_LATCH2_I2C_DAT); 1288 spin_unlock(&cfb->reg_b0_lock); 1289 1290 return ret; 1291 } 1292 1293 static int cyber2000fb_i2c_getscl(void *data) 1294 { 1295 struct cfb_info *cfb = data; 1296 int ret; 1297 1298 spin_lock(&cfb->reg_b0_lock); 1299 ret = !!(cyber2000_grphr(EXT_LATCH2, cfb) & EXT_LATCH2_I2C_CLK); 1300 spin_unlock(&cfb->reg_b0_lock); 1301 1302 return ret; 1303 } 1304 1305 static int cyber2000fb_i2c_register(struct cfb_info *cfb) 1306 { 1307 strlcpy(cfb->i2c_adapter.name, cfb->fb.fix.id, 1308 sizeof(cfb->i2c_adapter.name)); 1309 cfb->i2c_adapter.owner = THIS_MODULE; 1310 cfb->i2c_adapter.algo_data = &cfb->i2c_algo; 1311 cfb->i2c_adapter.dev.parent = cfb->fb.device; 1312 cfb->i2c_algo.setsda = cyber2000fb_i2c_setsda; 1313 cfb->i2c_algo.setscl = cyber2000fb_i2c_setscl; 1314 cfb->i2c_algo.getsda = cyber2000fb_i2c_getsda; 1315 cfb->i2c_algo.getscl = cyber2000fb_i2c_getscl; 1316 cfb->i2c_algo.udelay = 5; 1317 cfb->i2c_algo.timeout = msecs_to_jiffies(100); 1318 cfb->i2c_algo.data = cfb; 1319 1320 return i2c_bit_add_bus(&cfb->i2c_adapter); 1321 } 1322 1323 static void cyber2000fb_i2c_unregister(struct cfb_info *cfb) 1324 { 1325 i2c_del_adapter(&cfb->i2c_adapter); 1326 } 1327 #else 1328 #define cyber2000fb_i2c_register(cfb) (0) 1329 #define cyber2000fb_i2c_unregister(cfb) do { } while (0) 1330 #endif 1331 1332 /* 1333 * These parameters give 1334 * 640x480, hsync 31.5kHz, vsync 60Hz 1335 */ 1336 static const struct fb_videomode cyber2000fb_default_mode = { 1337 .refresh = 60, 1338 .xres = 640, 1339 .yres = 480, 1340 .pixclock = 39722, 1341 .left_margin = 56, 1342 .right_margin = 16, 1343 .upper_margin = 34, 1344 .lower_margin = 9, 1345 .hsync_len = 88, 1346 .vsync_len = 2, 1347 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, 1348 .vmode = FB_VMODE_NONINTERLACED 1349 }; 1350 1351 static char igs_regs[] = { 1352 EXT_CRT_IRQ, 0, 1353 EXT_CRT_TEST, 0, 1354 EXT_SYNC_CTL, 0, 1355 EXT_SEG_WRITE_PTR, 0, 1356 EXT_SEG_READ_PTR, 0, 1357 EXT_BIU_MISC, EXT_BIU_MISC_LIN_ENABLE | 1358 EXT_BIU_MISC_COP_ENABLE | 1359 EXT_BIU_MISC_COP_BFC, 1360 EXT_FUNC_CTL, 0, 1361 CURS_H_START, 0, 1362 CURS_H_START + 1, 0, 1363 CURS_H_PRESET, 0, 1364 CURS_V_START, 0, 1365 CURS_V_START + 1, 0, 1366 CURS_V_PRESET, 0, 1367 CURS_CTL, 0, 1368 EXT_ATTRIB_CTL, EXT_ATTRIB_CTL_EXT, 1369 EXT_OVERSCAN_RED, 0, 1370 EXT_OVERSCAN_GREEN, 0, 1371 EXT_OVERSCAN_BLUE, 0, 1372 1373 /* some of these are questionable when we have a BIOS */ 1374 EXT_MEM_CTL0, EXT_MEM_CTL0_7CLK | 1375 EXT_MEM_CTL0_RAS_1 | 1376 EXT_MEM_CTL0_MULTCAS, 1377 EXT_HIDDEN_CTL1, 0x30, 1378 EXT_FIFO_CTL, 0x0b, 1379 EXT_FIFO_CTL + 1, 0x17, 1380 0x76, 0x00, 1381 EXT_HIDDEN_CTL4, 0xc8 1382 }; 1383 1384 /* 1385 * Initialise the CyberPro hardware. On the CyberPro5XXXX, 1386 * ensure that we're using the correct PLL (5XXX's may be 1387 * programmed to use an additional set of PLLs.) 1388 */ 1389 static void cyberpro_init_hw(struct cfb_info *cfb) 1390 { 1391 int i; 1392 1393 for (i = 0; i < sizeof(igs_regs); i += 2) 1394 cyber2000_grphw(igs_regs[i], igs_regs[i + 1], cfb); 1395 1396 if (cfb->id == ID_CYBERPRO_5000) { 1397 unsigned char val; 1398 cyber2000fb_writeb(0xba, 0x3ce, cfb); 1399 val = cyber2000fb_readb(0x3cf, cfb) & 0x80; 1400 cyber2000fb_writeb(val, 0x3cf, cfb); 1401 } 1402 } 1403 1404 static struct cfb_info *cyberpro_alloc_fb_info(unsigned int id, char *name) 1405 { 1406 struct cfb_info *cfb; 1407 1408 cfb = kzalloc(sizeof(struct cfb_info), GFP_KERNEL); 1409 if (!cfb) 1410 return NULL; 1411 1412 1413 cfb->id = id; 1414 1415 if (id == ID_CYBERPRO_5000) 1416 cfb->ref_ps = 40690; /* 24.576 MHz */ 1417 else 1418 cfb->ref_ps = 69842; /* 14.31818 MHz (69841?) */ 1419 1420 cfb->divisors[0] = 1; 1421 cfb->divisors[1] = 2; 1422 cfb->divisors[2] = 4; 1423 1424 if (id == ID_CYBERPRO_2000) 1425 cfb->divisors[3] = 8; 1426 else 1427 cfb->divisors[3] = 6; 1428 1429 strcpy(cfb->fb.fix.id, name); 1430 1431 cfb->fb.fix.type = FB_TYPE_PACKED_PIXELS; 1432 cfb->fb.fix.type_aux = 0; 1433 cfb->fb.fix.xpanstep = 0; 1434 cfb->fb.fix.ypanstep = 1; 1435 cfb->fb.fix.ywrapstep = 0; 1436 1437 switch (id) { 1438 case ID_IGA_1682: 1439 cfb->fb.fix.accel = 0; 1440 break; 1441 1442 case ID_CYBERPRO_2000: 1443 cfb->fb.fix.accel = FB_ACCEL_IGS_CYBER2000; 1444 break; 1445 1446 case ID_CYBERPRO_2010: 1447 cfb->fb.fix.accel = FB_ACCEL_IGS_CYBER2010; 1448 break; 1449 1450 case ID_CYBERPRO_5000: 1451 cfb->fb.fix.accel = FB_ACCEL_IGS_CYBER5000; 1452 break; 1453 } 1454 1455 cfb->fb.var.nonstd = 0; 1456 cfb->fb.var.activate = FB_ACTIVATE_NOW; 1457 cfb->fb.var.height = -1; 1458 cfb->fb.var.width = -1; 1459 cfb->fb.var.accel_flags = FB_ACCELF_TEXT; 1460 1461 cfb->fb.fbops = &cyber2000fb_ops; 1462 cfb->fb.flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN; 1463 cfb->fb.pseudo_palette = cfb->pseudo_palette; 1464 1465 spin_lock_init(&cfb->reg_b0_lock); 1466 1467 fb_alloc_cmap(&cfb->fb.cmap, NR_PALETTE, 0); 1468 1469 return cfb; 1470 } 1471 1472 static void cyberpro_free_fb_info(struct cfb_info *cfb) 1473 { 1474 if (cfb) { 1475 /* 1476 * Free the colourmap 1477 */ 1478 fb_alloc_cmap(&cfb->fb.cmap, 0, 0); 1479 1480 kfree(cfb); 1481 } 1482 } 1483 1484 /* 1485 * Parse Cyber2000fb options. Usage: 1486 * video=cyber2000:font:fontname 1487 */ 1488 #ifndef MODULE 1489 static int cyber2000fb_setup(char *options) 1490 { 1491 char *opt; 1492 1493 if (!options || !*options) 1494 return 0; 1495 1496 while ((opt = strsep(&options, ",")) != NULL) { 1497 if (!*opt) 1498 continue; 1499 1500 if (strncmp(opt, "font:", 5) == 0) { 1501 static char default_font_storage[40]; 1502 1503 strlcpy(default_font_storage, opt + 5, 1504 sizeof(default_font_storage)); 1505 default_font = default_font_storage; 1506 continue; 1507 } 1508 1509 printk(KERN_ERR "CyberPro20x0: unknown parameter: %s\n", opt); 1510 } 1511 return 0; 1512 } 1513 #endif /* MODULE */ 1514 1515 /* 1516 * The CyberPro chips can be placed on many different bus types. 1517 * This probe function is common to all bus types. The bus-specific 1518 * probe function is expected to have: 1519 * - enabled access to the linear memory region 1520 * - memory mapped access to the registers 1521 * - initialised mem_ctl1 and mem_ctl2 appropriately. 1522 */ 1523 static int cyberpro_common_probe(struct cfb_info *cfb) 1524 { 1525 u_long smem_size; 1526 u_int h_sync, v_sync; 1527 int err; 1528 1529 cyberpro_init_hw(cfb); 1530 1531 /* 1532 * Get the video RAM size and width from the VGA register. 1533 * This should have been already initialised by the BIOS, 1534 * but if it's garbage, claim default 1MB VRAM (woody) 1535 */ 1536 cfb->mem_ctl1 = cyber2000_grphr(EXT_MEM_CTL1, cfb); 1537 cfb->mem_ctl2 = cyber2000_grphr(EXT_MEM_CTL2, cfb); 1538 1539 /* 1540 * Determine the size of the memory. 1541 */ 1542 switch (cfb->mem_ctl2 & MEM_CTL2_SIZE_MASK) { 1543 case MEM_CTL2_SIZE_4MB: 1544 smem_size = 0x00400000; 1545 break; 1546 case MEM_CTL2_SIZE_2MB: 1547 smem_size = 0x00200000; 1548 break; 1549 case MEM_CTL2_SIZE_1MB: 1550 smem_size = 0x00100000; 1551 break; 1552 default: 1553 smem_size = 0x00100000; 1554 break; 1555 } 1556 1557 cfb->fb.fix.smem_len = smem_size; 1558 cfb->fb.fix.mmio_len = MMIO_SIZE; 1559 cfb->fb.screen_base = cfb->region; 1560 1561 #ifdef CONFIG_FB_CYBER2000_DDC 1562 if (cyber2000fb_setup_ddc_bus(cfb) == 0) 1563 cfb->ddc_registered = true; 1564 #endif 1565 1566 err = -EINVAL; 1567 if (!fb_find_mode(&cfb->fb.var, &cfb->fb, NULL, NULL, 0, 1568 &cyber2000fb_default_mode, 8)) { 1569 printk(KERN_ERR "%s: no valid mode found\n", cfb->fb.fix.id); 1570 goto failed; 1571 } 1572 1573 cfb->fb.var.yres_virtual = cfb->fb.fix.smem_len * 8 / 1574 (cfb->fb.var.bits_per_pixel * cfb->fb.var.xres_virtual); 1575 1576 if (cfb->fb.var.yres_virtual < cfb->fb.var.yres) 1577 cfb->fb.var.yres_virtual = cfb->fb.var.yres; 1578 1579 /* fb_set_var(&cfb->fb.var, -1, &cfb->fb); */ 1580 1581 /* 1582 * Calculate the hsync and vsync frequencies. Note that 1583 * we split the 1e12 constant up so that we can preserve 1584 * the precision and fit the results into 32-bit registers. 1585 * (1953125000 * 512 = 1e12) 1586 */ 1587 h_sync = 1953125000 / cfb->fb.var.pixclock; 1588 h_sync = h_sync * 512 / (cfb->fb.var.xres + cfb->fb.var.left_margin + 1589 cfb->fb.var.right_margin + cfb->fb.var.hsync_len); 1590 v_sync = h_sync / (cfb->fb.var.yres + cfb->fb.var.upper_margin + 1591 cfb->fb.var.lower_margin + cfb->fb.var.vsync_len); 1592 1593 printk(KERN_INFO "%s: %dKiB VRAM, using %dx%d, %d.%03dkHz, %dHz\n", 1594 cfb->fb.fix.id, cfb->fb.fix.smem_len >> 10, 1595 cfb->fb.var.xres, cfb->fb.var.yres, 1596 h_sync / 1000, h_sync % 1000, v_sync); 1597 1598 err = cyber2000fb_i2c_register(cfb); 1599 if (err) 1600 goto failed; 1601 1602 err = register_framebuffer(&cfb->fb); 1603 if (err) 1604 cyber2000fb_i2c_unregister(cfb); 1605 1606 failed: 1607 #ifdef CONFIG_FB_CYBER2000_DDC 1608 if (err && cfb->ddc_registered) 1609 i2c_del_adapter(&cfb->ddc_adapter); 1610 #endif 1611 return err; 1612 } 1613 1614 static void cyberpro_common_remove(struct cfb_info *cfb) 1615 { 1616 unregister_framebuffer(&cfb->fb); 1617 #ifdef CONFIG_FB_CYBER2000_DDC 1618 if (cfb->ddc_registered) 1619 i2c_del_adapter(&cfb->ddc_adapter); 1620 #endif 1621 cyber2000fb_i2c_unregister(cfb); 1622 } 1623 1624 static void cyberpro_common_resume(struct cfb_info *cfb) 1625 { 1626 cyberpro_init_hw(cfb); 1627 1628 /* 1629 * Reprogram the MEM_CTL1 and MEM_CTL2 registers 1630 */ 1631 cyber2000_grphw(EXT_MEM_CTL1, cfb->mem_ctl1, cfb); 1632 cyber2000_grphw(EXT_MEM_CTL2, cfb->mem_ctl2, cfb); 1633 1634 /* 1635 * Restore the old video mode and the palette. 1636 * We also need to tell fbcon to redraw the console. 1637 */ 1638 cyber2000fb_set_par(&cfb->fb); 1639 } 1640 1641 /* 1642 * PCI specific support. 1643 */ 1644 #ifdef CONFIG_PCI 1645 /* 1646 * We need to wake up the CyberPro, and make sure its in linear memory 1647 * mode. Unfortunately, this is specific to the platform and card that 1648 * we are running on. 1649 * 1650 * On x86 and ARM, should we be initialising the CyberPro first via the 1651 * IO registers, and then the MMIO registers to catch all cases? Can we 1652 * end up in the situation where the chip is in MMIO mode, but not awake 1653 * on an x86 system? 1654 */ 1655 static int cyberpro_pci_enable_mmio(struct cfb_info *cfb) 1656 { 1657 unsigned char val; 1658 1659 #if defined(__sparc_v9__) 1660 #error "You lose, consult DaveM." 1661 #elif defined(__sparc__) 1662 /* 1663 * SPARC does not have an "outb" instruction, so we generate 1664 * I/O cycles storing into a reserved memory space at 1665 * physical address 0x3000000 1666 */ 1667 unsigned char __iomem *iop; 1668 1669 iop = ioremap(0x3000000, 0x5000); 1670 if (iop == NULL) { 1671 printk(KERN_ERR "iga5000: cannot map I/O\n"); 1672 return -ENOMEM; 1673 } 1674 1675 writeb(0x18, iop + 0x46e8); 1676 writeb(0x01, iop + 0x102); 1677 writeb(0x08, iop + 0x46e8); 1678 writeb(EXT_BIU_MISC, iop + 0x3ce); 1679 writeb(EXT_BIU_MISC_LIN_ENABLE, iop + 0x3cf); 1680 1681 iounmap(iop); 1682 #else 1683 /* 1684 * Most other machine types are "normal", so 1685 * we use the standard IO-based wakeup. 1686 */ 1687 outb(0x18, 0x46e8); 1688 outb(0x01, 0x102); 1689 outb(0x08, 0x46e8); 1690 outb(EXT_BIU_MISC, 0x3ce); 1691 outb(EXT_BIU_MISC_LIN_ENABLE, 0x3cf); 1692 #endif 1693 1694 /* 1695 * Allow the CyberPro to accept PCI burst accesses 1696 */ 1697 if (cfb->id == ID_CYBERPRO_2010) { 1698 printk(KERN_INFO "%s: NOT enabling PCI bursts\n", 1699 cfb->fb.fix.id); 1700 } else { 1701 val = cyber2000_grphr(EXT_BUS_CTL, cfb); 1702 if (!(val & EXT_BUS_CTL_PCIBURST_WRITE)) { 1703 printk(KERN_INFO "%s: enabling PCI bursts\n", 1704 cfb->fb.fix.id); 1705 1706 val |= EXT_BUS_CTL_PCIBURST_WRITE; 1707 1708 if (cfb->id == ID_CYBERPRO_5000) 1709 val |= EXT_BUS_CTL_PCIBURST_READ; 1710 1711 cyber2000_grphw(EXT_BUS_CTL, val, cfb); 1712 } 1713 } 1714 1715 return 0; 1716 } 1717 1718 static int cyberpro_pci_probe(struct pci_dev *dev, 1719 const struct pci_device_id *id) 1720 { 1721 struct cfb_info *cfb; 1722 char name[16]; 1723 int err; 1724 1725 sprintf(name, "CyberPro%4X", id->device); 1726 1727 err = pci_enable_device(dev); 1728 if (err) 1729 return err; 1730 1731 err = -ENOMEM; 1732 cfb = cyberpro_alloc_fb_info(id->driver_data, name); 1733 if (!cfb) 1734 goto failed_release; 1735 1736 err = pci_request_regions(dev, cfb->fb.fix.id); 1737 if (err) 1738 goto failed_regions; 1739 1740 cfb->irq = dev->irq; 1741 cfb->region = pci_ioremap_bar(dev, 0); 1742 if (!cfb->region) { 1743 err = -ENOMEM; 1744 goto failed_ioremap; 1745 } 1746 1747 cfb->regs = cfb->region + MMIO_OFFSET; 1748 cfb->fb.device = &dev->dev; 1749 cfb->fb.fix.mmio_start = pci_resource_start(dev, 0) + MMIO_OFFSET; 1750 cfb->fb.fix.smem_start = pci_resource_start(dev, 0); 1751 1752 /* 1753 * Bring up the hardware. This is expected to enable access 1754 * to the linear memory region, and allow access to the memory 1755 * mapped registers. Also, mem_ctl1 and mem_ctl2 must be 1756 * initialised. 1757 */ 1758 err = cyberpro_pci_enable_mmio(cfb); 1759 if (err) 1760 goto failed; 1761 1762 /* 1763 * Use MCLK from BIOS. FIXME: what about hotplug? 1764 */ 1765 cfb->mclk_mult = cyber2000_grphr(EXT_MCLK_MULT, cfb); 1766 cfb->mclk_div = cyber2000_grphr(EXT_MCLK_DIV, cfb); 1767 1768 #ifdef __arm__ 1769 /* 1770 * MCLK on the NetWinder and the Shark is fixed at 75MHz 1771 */ 1772 if (machine_is_netwinder()) { 1773 cfb->mclk_mult = 0xdb; 1774 cfb->mclk_div = 0x54; 1775 } 1776 #endif 1777 1778 err = cyberpro_common_probe(cfb); 1779 if (err) 1780 goto failed; 1781 1782 /* 1783 * Our driver data 1784 */ 1785 pci_set_drvdata(dev, cfb); 1786 if (int_cfb_info == NULL) 1787 int_cfb_info = cfb; 1788 1789 return 0; 1790 1791 failed: 1792 iounmap(cfb->region); 1793 failed_ioremap: 1794 pci_release_regions(dev); 1795 failed_regions: 1796 cyberpro_free_fb_info(cfb); 1797 failed_release: 1798 return err; 1799 } 1800 1801 static void cyberpro_pci_remove(struct pci_dev *dev) 1802 { 1803 struct cfb_info *cfb = pci_get_drvdata(dev); 1804 1805 if (cfb) { 1806 cyberpro_common_remove(cfb); 1807 iounmap(cfb->region); 1808 cyberpro_free_fb_info(cfb); 1809 1810 if (cfb == int_cfb_info) 1811 int_cfb_info = NULL; 1812 1813 pci_release_regions(dev); 1814 } 1815 } 1816 1817 static int cyberpro_pci_suspend(struct pci_dev *dev, pm_message_t state) 1818 { 1819 return 0; 1820 } 1821 1822 /* 1823 * Re-initialise the CyberPro hardware 1824 */ 1825 static int cyberpro_pci_resume(struct pci_dev *dev) 1826 { 1827 struct cfb_info *cfb = pci_get_drvdata(dev); 1828 1829 if (cfb) { 1830 cyberpro_pci_enable_mmio(cfb); 1831 cyberpro_common_resume(cfb); 1832 } 1833 1834 return 0; 1835 } 1836 1837 static struct pci_device_id cyberpro_pci_table[] = { 1838 /* Not yet 1839 * { PCI_VENDOR_ID_INTERG, PCI_DEVICE_ID_INTERG_1682, 1840 * PCI_ANY_ID, PCI_ANY_ID, 0, 0, ID_IGA_1682 }, 1841 */ 1842 { PCI_VENDOR_ID_INTERG, PCI_DEVICE_ID_INTERG_2000, 1843 PCI_ANY_ID, PCI_ANY_ID, 0, 0, ID_CYBERPRO_2000 }, 1844 { PCI_VENDOR_ID_INTERG, PCI_DEVICE_ID_INTERG_2010, 1845 PCI_ANY_ID, PCI_ANY_ID, 0, 0, ID_CYBERPRO_2010 }, 1846 { PCI_VENDOR_ID_INTERG, PCI_DEVICE_ID_INTERG_5000, 1847 PCI_ANY_ID, PCI_ANY_ID, 0, 0, ID_CYBERPRO_5000 }, 1848 { 0, } 1849 }; 1850 1851 MODULE_DEVICE_TABLE(pci, cyberpro_pci_table); 1852 1853 static struct pci_driver cyberpro_driver = { 1854 .name = "CyberPro", 1855 .probe = cyberpro_pci_probe, 1856 .remove = cyberpro_pci_remove, 1857 .suspend = cyberpro_pci_suspend, 1858 .resume = cyberpro_pci_resume, 1859 .id_table = cyberpro_pci_table 1860 }; 1861 #endif 1862 1863 /* 1864 * I don't think we can use the "module_init" stuff here because 1865 * the fbcon stuff may not be initialised yet. Hence the #ifdef 1866 * around module_init. 1867 * 1868 * Tony: "module_init" is now required 1869 */ 1870 static int __init cyber2000fb_init(void) 1871 { 1872 int ret = -1, err; 1873 1874 #ifndef MODULE 1875 char *option = NULL; 1876 1877 if (fb_get_options("cyber2000fb", &option)) 1878 return -ENODEV; 1879 cyber2000fb_setup(option); 1880 #endif 1881 1882 err = pci_register_driver(&cyberpro_driver); 1883 if (!err) 1884 ret = 0; 1885 1886 return ret ? err : 0; 1887 } 1888 module_init(cyber2000fb_init); 1889 1890 static void __exit cyberpro_exit(void) 1891 { 1892 pci_unregister_driver(&cyberpro_driver); 1893 } 1894 module_exit(cyberpro_exit); 1895 1896 MODULE_AUTHOR("Russell King"); 1897 MODULE_DESCRIPTION("CyberPro 2000, 2010 and 5000 framebuffer driver"); 1898 MODULE_LICENSE("GPL"); 1899