1 /* 2 * controlfb.c -- frame buffer device for the PowerMac 'control' display 3 * 4 * Created 12 July 1998 by Dan Jacobowitz <dan@debian.org> 5 * Copyright (C) 1998 Dan Jacobowitz 6 * Copyright (C) 2001 Takashi Oe 7 * 8 * Mmap code by Michel Lanners <mlan@cpu.lu> 9 * 10 * Frame buffer structure from: 11 * drivers/video/chipsfb.c -- frame buffer device for 12 * Chips & Technologies 65550 chip. 13 * 14 * Copyright (C) 1998 Paul Mackerras 15 * 16 * This file is derived from the Powermac "chips" driver: 17 * Copyright (C) 1997 Fabio Riccardi. 18 * And from the frame buffer device for Open Firmware-initialized devices: 19 * Copyright (C) 1997 Geert Uytterhoeven. 20 * 21 * Hardware information from: 22 * control.c: Console support for PowerMac "control" display adaptor. 23 * Copyright (C) 1996 Paul Mackerras 24 * 25 * Updated to 2.5 framebuffer API by Ben Herrenschmidt 26 * <benh@kernel.crashing.org>, Paul Mackerras <paulus@samba.org>, 27 * and James Simmons <jsimmons@infradead.org>. 28 * 29 * This file is subject to the terms and conditions of the GNU General Public 30 * License. See the file COPYING in the main directory of this archive for 31 * more details. 32 */ 33 34 #include <linux/kernel.h> 35 #include <linux/errno.h> 36 #include <linux/string.h> 37 #include <linux/mm.h> 38 #include <linux/slab.h> 39 #include <linux/vmalloc.h> 40 #include <linux/delay.h> 41 #include <linux/interrupt.h> 42 #include <linux/of.h> 43 #include <linux/of_address.h> 44 #include <linux/fb.h> 45 #include <linux/init.h> 46 #include <linux/pci.h> 47 #include <linux/nvram.h> 48 #include <linux/adb.h> 49 #include <linux/cuda.h> 50 #ifdef CONFIG_PPC_PMAC 51 #include <asm/prom.h> 52 #include <asm/btext.h> 53 #endif 54 55 #include "macmodes.h" 56 #include "controlfb.h" 57 58 #if !defined(CONFIG_PPC_PMAC) || !defined(CONFIG_PPC32) 59 #define invalid_vram_cache(addr) 60 #undef in_8 61 #undef out_8 62 #undef in_le32 63 #undef out_le32 64 #define in_8(addr) 0 65 #define out_8(addr, val) 66 #define in_le32(addr) 0 67 #define out_le32(addr, val) 68 #define pgprot_cached_wthru(prot) (prot) 69 #else 70 static void invalid_vram_cache(void __force *addr) 71 { 72 eieio(); 73 dcbf(addr); 74 mb(); 75 eieio(); 76 dcbf(addr); 77 mb(); 78 } 79 #endif 80 81 struct fb_par_control { 82 int vmode, cmode; 83 int xres, yres; 84 int vxres, vyres; 85 int xoffset, yoffset; 86 int pitch; 87 struct control_regvals regvals; 88 unsigned long sync; 89 unsigned char ctrl; 90 }; 91 92 #define DIRTY(z) ((x)->z != (y)->z) 93 #define DIRTY_CMAP(z) (memcmp(&((x)->z), &((y)->z), sizeof((y)->z))) 94 static inline int PAR_EQUAL(struct fb_par_control *x, struct fb_par_control *y) 95 { 96 int i, results; 97 98 results = 1; 99 for (i = 0; i < 3; i++) 100 results &= !DIRTY(regvals.clock_params[i]); 101 if (!results) 102 return 0; 103 for (i = 0; i < 16; i++) 104 results &= !DIRTY(regvals.regs[i]); 105 if (!results) 106 return 0; 107 return (!DIRTY(cmode) && !DIRTY(xres) && !DIRTY(yres) 108 && !DIRTY(vxres) && !DIRTY(vyres)); 109 } 110 static inline int VAR_MATCH(struct fb_var_screeninfo *x, struct fb_var_screeninfo *y) 111 { 112 return (!DIRTY(bits_per_pixel) && !DIRTY(xres) 113 && !DIRTY(yres) && !DIRTY(xres_virtual) 114 && !DIRTY(yres_virtual) 115 && !DIRTY_CMAP(red) && !DIRTY_CMAP(green) && !DIRTY_CMAP(blue)); 116 } 117 118 struct fb_info_control { 119 struct fb_info info; 120 struct fb_par_control par; 121 u32 pseudo_palette[16]; 122 123 struct cmap_regs __iomem *cmap_regs; 124 unsigned long cmap_regs_phys; 125 126 struct control_regs __iomem *control_regs; 127 unsigned long control_regs_phys; 128 unsigned long control_regs_size; 129 130 __u8 __iomem *frame_buffer; 131 unsigned long frame_buffer_phys; 132 unsigned long fb_orig_base; 133 unsigned long fb_orig_size; 134 135 int control_use_bank2; 136 unsigned long total_vram; 137 unsigned char vram_attr; 138 }; 139 140 /* control register access macro */ 141 #define CNTRL_REG(INFO,REG) (&(((INFO)->control_regs->REG).r)) 142 143 144 /************************** Internal variables *******************************/ 145 146 static struct fb_info_control *control_fb; 147 148 static int default_vmode __initdata = VMODE_NVRAM; 149 static int default_cmode __initdata = CMODE_NVRAM; 150 151 152 static int controlfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, 153 u_int transp, struct fb_info *info) 154 { 155 struct fb_info_control *p = 156 container_of(info, struct fb_info_control, info); 157 __u8 r, g, b; 158 159 if (regno > 255) 160 return 1; 161 162 r = red >> 8; 163 g = green >> 8; 164 b = blue >> 8; 165 166 out_8(&p->cmap_regs->addr, regno); /* tell clut what addr to fill */ 167 out_8(&p->cmap_regs->lut, r); /* send one color channel at */ 168 out_8(&p->cmap_regs->lut, g); /* a time... */ 169 out_8(&p->cmap_regs->lut, b); 170 171 if (regno < 16) { 172 int i; 173 switch (p->par.cmode) { 174 case CMODE_16: 175 p->pseudo_palette[regno] = 176 (regno << 10) | (regno << 5) | regno; 177 break; 178 case CMODE_32: 179 i = (regno << 8) | regno; 180 p->pseudo_palette[regno] = (i << 16) | i; 181 break; 182 } 183 } 184 185 return 0; 186 } 187 188 189 /******************** End of controlfb_ops implementation ******************/ 190 191 192 193 static void set_control_clock(unsigned char *params) 194 { 195 #ifdef CONFIG_ADB_CUDA 196 struct adb_request req; 197 int i; 198 199 for (i = 0; i < 3; ++i) { 200 cuda_request(&req, NULL, 5, CUDA_PACKET, CUDA_GET_SET_IIC, 201 0x50, i + 1, params[i]); 202 while (!req.complete) 203 cuda_poll(); 204 } 205 #endif 206 } 207 208 /* 209 * Set screen start address according to var offset values 210 */ 211 static inline void set_screen_start(int xoffset, int yoffset, 212 struct fb_info_control *p) 213 { 214 struct fb_par_control *par = &p->par; 215 216 par->xoffset = xoffset; 217 par->yoffset = yoffset; 218 out_le32(CNTRL_REG(p,start_addr), 219 par->yoffset * par->pitch + (par->xoffset << par->cmode)); 220 } 221 222 #define RADACAL_WRITE(a,d) \ 223 out_8(&p->cmap_regs->addr, (a)); \ 224 out_8(&p->cmap_regs->dat, (d)) 225 226 /* Now how about actually saying, Make it so! */ 227 /* Some things in here probably don't need to be done each time. */ 228 static void control_set_hardware(struct fb_info_control *p, struct fb_par_control *par) 229 { 230 struct control_regvals *r; 231 volatile struct preg __iomem *rp; 232 int i, cmode; 233 234 if (PAR_EQUAL(&p->par, par)) { 235 /* 236 * check if only xoffset or yoffset differs. 237 * this prevents flickers in typical VT switch case. 238 */ 239 if (p->par.xoffset != par->xoffset || 240 p->par.yoffset != par->yoffset) 241 set_screen_start(par->xoffset, par->yoffset, p); 242 243 return; 244 } 245 246 p->par = *par; 247 cmode = p->par.cmode; 248 r = &par->regvals; 249 250 /* Turn off display */ 251 out_le32(CNTRL_REG(p,ctrl), 0x400 | par->ctrl); 252 253 set_control_clock(r->clock_params); 254 255 RADACAL_WRITE(0x20, r->radacal_ctrl); 256 RADACAL_WRITE(0x21, p->control_use_bank2 ? 0 : 1); 257 RADACAL_WRITE(0x10, 0); 258 RADACAL_WRITE(0x11, 0); 259 260 rp = &p->control_regs->vswin; 261 for (i = 0; i < 16; ++i, ++rp) 262 out_le32(&rp->r, r->regs[i]); 263 264 out_le32(CNTRL_REG(p,pitch), par->pitch); 265 out_le32(CNTRL_REG(p,mode), r->mode); 266 out_le32(CNTRL_REG(p,vram_attr), p->vram_attr); 267 out_le32(CNTRL_REG(p,start_addr), par->yoffset * par->pitch 268 + (par->xoffset << cmode)); 269 out_le32(CNTRL_REG(p,rfrcnt), 0x1e5); 270 out_le32(CNTRL_REG(p,intr_ena), 0); 271 272 /* Turn on display */ 273 out_le32(CNTRL_REG(p,ctrl), par->ctrl); 274 275 #ifdef CONFIG_BOOTX_TEXT 276 btext_update_display(p->frame_buffer_phys + CTRLFB_OFF, 277 p->par.xres, p->par.yres, 278 (cmode == CMODE_32? 32: cmode == CMODE_16? 16: 8), 279 p->par.pitch); 280 #endif /* CONFIG_BOOTX_TEXT */ 281 } 282 283 /* Work out which banks of VRAM we have installed. */ 284 /* danj: I guess the card just ignores writes to nonexistant VRAM... */ 285 286 static void __init find_vram_size(struct fb_info_control *p) 287 { 288 int bank1, bank2; 289 290 /* 291 * Set VRAM in 2MB (bank 1) mode 292 * VRAM Bank 2 will be accessible through offset 0x600000 if present 293 * and VRAM Bank 1 will not respond at that offset even if present 294 */ 295 out_le32(CNTRL_REG(p,vram_attr), 0x31); 296 297 out_8(&p->frame_buffer[0x600000], 0xb3); 298 out_8(&p->frame_buffer[0x600001], 0x71); 299 invalid_vram_cache(&p->frame_buffer[0x600000]); 300 301 bank2 = (in_8(&p->frame_buffer[0x600000]) == 0xb3) 302 && (in_8(&p->frame_buffer[0x600001]) == 0x71); 303 304 /* 305 * Set VRAM in 2MB (bank 2) mode 306 * VRAM Bank 1 will be accessible through offset 0x000000 if present 307 * and VRAM Bank 2 will not respond at that offset even if present 308 */ 309 out_le32(CNTRL_REG(p,vram_attr), 0x39); 310 311 out_8(&p->frame_buffer[0], 0x5a); 312 out_8(&p->frame_buffer[1], 0xc7); 313 invalid_vram_cache(&p->frame_buffer[0]); 314 315 bank1 = (in_8(&p->frame_buffer[0]) == 0x5a) 316 && (in_8(&p->frame_buffer[1]) == 0xc7); 317 318 if (bank2) { 319 if (!bank1) { 320 /* 321 * vram bank 2 only 322 */ 323 p->control_use_bank2 = 1; 324 p->vram_attr = 0x39; 325 p->frame_buffer += 0x600000; 326 p->frame_buffer_phys += 0x600000; 327 } else { 328 /* 329 * 4 MB vram 330 */ 331 p->vram_attr = 0x51; 332 } 333 } else { 334 /* 335 * vram bank 1 only 336 */ 337 p->vram_attr = 0x31; 338 } 339 340 p->total_vram = (bank1 + bank2) * 0x200000; 341 342 printk(KERN_INFO "controlfb: VRAM Total = %dMB " 343 "(%dMB @ bank 1, %dMB @ bank 2)\n", 344 (bank1 + bank2) << 1, bank1 << 1, bank2 << 1); 345 } 346 347 /* 348 * Get the monitor sense value. 349 * Note that this can be called before calibrate_delay, 350 * so we can't use udelay. 351 */ 352 static int read_control_sense(struct fb_info_control *p) 353 { 354 int sense; 355 356 out_le32(CNTRL_REG(p,mon_sense), 7); /* drive all lines high */ 357 __delay(200); 358 out_le32(CNTRL_REG(p,mon_sense), 077); /* turn off drivers */ 359 __delay(2000); 360 sense = (in_le32(CNTRL_REG(p,mon_sense)) & 0x1c0) << 2; 361 362 /* drive each sense line low in turn and collect the other 2 */ 363 out_le32(CNTRL_REG(p,mon_sense), 033); /* drive A low */ 364 __delay(2000); 365 sense |= (in_le32(CNTRL_REG(p,mon_sense)) & 0xc0) >> 2; 366 out_le32(CNTRL_REG(p,mon_sense), 055); /* drive B low */ 367 __delay(2000); 368 sense |= ((in_le32(CNTRL_REG(p,mon_sense)) & 0x100) >> 5) 369 | ((in_le32(CNTRL_REG(p,mon_sense)) & 0x40) >> 4); 370 out_le32(CNTRL_REG(p,mon_sense), 066); /* drive C low */ 371 __delay(2000); 372 sense |= (in_le32(CNTRL_REG(p,mon_sense)) & 0x180) >> 7; 373 374 out_le32(CNTRL_REG(p,mon_sense), 077); /* turn off drivers */ 375 376 return sense; 377 } 378 379 /********************** Various translation functions **********************/ 380 381 #define CONTROL_PIXCLOCK_BASE 256016 382 #define CONTROL_PIXCLOCK_MIN 5000 /* ~ 200 MHz dot clock */ 383 384 /* 385 * calculate the clock paramaters to be sent to CUDA according to given 386 * pixclock in pico second. 387 */ 388 static int calc_clock_params(unsigned long clk, unsigned char *param) 389 { 390 unsigned long p0, p1, p2, k, l, m, n, min; 391 392 if (clk > (CONTROL_PIXCLOCK_BASE << 3)) 393 return 1; 394 395 p2 = ((clk << 4) < CONTROL_PIXCLOCK_BASE)? 3: 2; 396 l = clk << p2; 397 p0 = 0; 398 p1 = 0; 399 for (k = 1, min = l; k < 32; k++) { 400 unsigned long rem; 401 402 m = CONTROL_PIXCLOCK_BASE * k; 403 n = m / l; 404 rem = m % l; 405 if (n && (n < 128) && rem < min) { 406 p0 = k; 407 p1 = n; 408 min = rem; 409 } 410 } 411 if (!p0 || !p1) 412 return 1; 413 414 param[0] = p0; 415 param[1] = p1; 416 param[2] = p2; 417 418 return 0; 419 } 420 421 422 /* 423 * This routine takes a user-supplied var, and picks the best vmode/cmode 424 * from it. 425 */ 426 427 static int control_var_to_par(struct fb_var_screeninfo *var, 428 struct fb_par_control *par, const struct fb_info *fb_info) 429 { 430 int cmode, piped_diff, hstep; 431 unsigned hperiod, hssync, hsblank, hesync, heblank, piped, heq, hlfln, 432 hserr, vperiod, vssync, vesync, veblank, vsblank, vswin, vewin; 433 unsigned long pixclock; 434 struct fb_info_control *p = 435 container_of(fb_info, struct fb_info_control, info); 436 struct control_regvals *r = &par->regvals; 437 438 switch (var->bits_per_pixel) { 439 case 8: 440 par->cmode = CMODE_8; 441 if (p->total_vram > 0x200000) { 442 r->mode = 3; 443 r->radacal_ctrl = 0x20; 444 piped_diff = 13; 445 } else { 446 r->mode = 2; 447 r->radacal_ctrl = 0x10; 448 piped_diff = 9; 449 } 450 break; 451 case 15: 452 case 16: 453 par->cmode = CMODE_16; 454 if (p->total_vram > 0x200000) { 455 r->mode = 2; 456 r->radacal_ctrl = 0x24; 457 piped_diff = 5; 458 } else { 459 r->mode = 1; 460 r->radacal_ctrl = 0x14; 461 piped_diff = 3; 462 } 463 break; 464 case 32: 465 par->cmode = CMODE_32; 466 if (p->total_vram > 0x200000) { 467 r->mode = 1; 468 r->radacal_ctrl = 0x28; 469 } else { 470 r->mode = 0; 471 r->radacal_ctrl = 0x18; 472 } 473 piped_diff = 1; 474 break; 475 default: 476 return -EINVAL; 477 } 478 479 /* 480 * adjust xres and vxres so that the corresponding memory widths are 481 * 32-byte aligned 482 */ 483 hstep = 31 >> par->cmode; 484 par->xres = (var->xres + hstep) & ~hstep; 485 par->vxres = (var->xres_virtual + hstep) & ~hstep; 486 par->xoffset = (var->xoffset + hstep) & ~hstep; 487 if (par->vxres < par->xres) 488 par->vxres = par->xres; 489 par->pitch = par->vxres << par->cmode; 490 491 par->yres = var->yres; 492 par->vyres = var->yres_virtual; 493 par->yoffset = var->yoffset; 494 if (par->vyres < par->yres) 495 par->vyres = par->yres; 496 497 par->sync = var->sync; 498 499 if (par->pitch * par->vyres + CTRLFB_OFF > p->total_vram) 500 return -EINVAL; 501 502 if (par->xoffset + par->xres > par->vxres) 503 par->xoffset = par->vxres - par->xres; 504 if (par->yoffset + par->yres > par->vyres) 505 par->yoffset = par->vyres - par->yres; 506 507 pixclock = (var->pixclock < CONTROL_PIXCLOCK_MIN)? CONTROL_PIXCLOCK_MIN: 508 var->pixclock; 509 if (calc_clock_params(pixclock, r->clock_params)) 510 return -EINVAL; 511 512 hperiod = ((var->left_margin + par->xres + var->right_margin 513 + var->hsync_len) >> 1) - 2; 514 hssync = hperiod + 1; 515 hsblank = hssync - (var->right_margin >> 1); 516 hesync = (var->hsync_len >> 1) - 1; 517 heblank = (var->left_margin >> 1) + hesync; 518 piped = heblank - piped_diff; 519 heq = var->hsync_len >> 2; 520 hlfln = (hperiod+2) >> 1; 521 hserr = hssync-hesync; 522 vperiod = (var->vsync_len + var->lower_margin + par->yres 523 + var->upper_margin) << 1; 524 vssync = vperiod - 2; 525 vesync = (var->vsync_len << 1) - vperiod + vssync; 526 veblank = (var->upper_margin << 1) + vesync; 527 vsblank = vssync - (var->lower_margin << 1); 528 vswin = (vsblank+vssync) >> 1; 529 vewin = (vesync+veblank) >> 1; 530 531 r->regs[0] = vswin; 532 r->regs[1] = vsblank; 533 r->regs[2] = veblank; 534 r->regs[3] = vewin; 535 r->regs[4] = vesync; 536 r->regs[5] = vssync; 537 r->regs[6] = vperiod; 538 r->regs[7] = piped; 539 r->regs[8] = hperiod; 540 r->regs[9] = hsblank; 541 r->regs[10] = heblank; 542 r->regs[11] = hesync; 543 r->regs[12] = hssync; 544 r->regs[13] = heq; 545 r->regs[14] = hlfln; 546 r->regs[15] = hserr; 547 548 if (par->xres >= 1280 && par->cmode >= CMODE_16) 549 par->ctrl = 0x7f; 550 else 551 par->ctrl = 0x3b; 552 553 if (mac_var_to_vmode(var, &par->vmode, &cmode)) 554 par->vmode = 0; 555 556 return 0; 557 } 558 559 560 /* 561 * Convert hardware data in par to an fb_var_screeninfo 562 */ 563 564 static void control_par_to_var(struct fb_par_control *par, struct fb_var_screeninfo *var) 565 { 566 struct control_regints *rv; 567 568 rv = (struct control_regints *) par->regvals.regs; 569 570 memset(var, 0, sizeof(*var)); 571 var->xres = par->xres; 572 var->yres = par->yres; 573 var->xres_virtual = par->vxres; 574 var->yres_virtual = par->vyres; 575 var->xoffset = par->xoffset; 576 var->yoffset = par->yoffset; 577 578 switch(par->cmode) { 579 default: 580 case CMODE_8: 581 var->bits_per_pixel = 8; 582 var->red.length = 8; 583 var->green.length = 8; 584 var->blue.length = 8; 585 break; 586 case CMODE_16: /* RGB 555 */ 587 var->bits_per_pixel = 16; 588 var->red.offset = 10; 589 var->red.length = 5; 590 var->green.offset = 5; 591 var->green.length = 5; 592 var->blue.length = 5; 593 break; 594 case CMODE_32: /* RGB 888 */ 595 var->bits_per_pixel = 32; 596 var->red.offset = 16; 597 var->red.length = 8; 598 var->green.offset = 8; 599 var->green.length = 8; 600 var->blue.length = 8; 601 var->transp.offset = 24; 602 var->transp.length = 8; 603 break; 604 } 605 var->height = -1; 606 var->width = -1; 607 var->vmode = FB_VMODE_NONINTERLACED; 608 609 var->left_margin = (rv->heblank - rv->hesync) << 1; 610 var->right_margin = (rv->hssync - rv->hsblank) << 1; 611 var->hsync_len = (rv->hperiod + 2 - rv->hssync + rv->hesync) << 1; 612 613 var->upper_margin = (rv->veblank - rv->vesync) >> 1; 614 var->lower_margin = (rv->vssync - rv->vsblank) >> 1; 615 var->vsync_len = (rv->vperiod - rv->vssync + rv->vesync) >> 1; 616 617 var->sync = par->sync; 618 619 /* 620 * 10^12 * clock_params[0] / (3906400 * clock_params[1] 621 * * 2^clock_params[2]) 622 * (10^12 * clock_params[0] / (3906400 * clock_params[1])) 623 * >> clock_params[2] 624 */ 625 /* (255990.17 * clock_params[0] / clock_params[1]) >> clock_params[2] */ 626 var->pixclock = CONTROL_PIXCLOCK_BASE * par->regvals.clock_params[0]; 627 var->pixclock /= par->regvals.clock_params[1]; 628 var->pixclock >>= par->regvals.clock_params[2]; 629 } 630 631 /******************** The functions for controlfb_ops ********************/ 632 633 /* 634 * Checks a var structure 635 */ 636 static int controlfb_check_var (struct fb_var_screeninfo *var, struct fb_info *info) 637 { 638 struct fb_par_control par; 639 int err; 640 641 err = control_var_to_par(var, &par, info); 642 if (err) 643 return err; 644 control_par_to_var(&par, var); 645 646 return 0; 647 } 648 649 /* 650 * Applies current var to display 651 */ 652 static int controlfb_set_par (struct fb_info *info) 653 { 654 struct fb_info_control *p = 655 container_of(info, struct fb_info_control, info); 656 struct fb_par_control par; 657 int err; 658 659 if((err = control_var_to_par(&info->var, &par, info))) { 660 printk (KERN_ERR "controlfb_set_par: error calling" 661 " control_var_to_par: %d.\n", err); 662 return err; 663 } 664 665 control_set_hardware(p, &par); 666 667 info->fix.visual = (p->par.cmode == CMODE_8) ? 668 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR; 669 info->fix.line_length = p->par.pitch; 670 info->fix.xpanstep = 32 >> p->par.cmode; 671 info->fix.ypanstep = 1; 672 673 return 0; 674 } 675 676 static int controlfb_pan_display(struct fb_var_screeninfo *var, 677 struct fb_info *info) 678 { 679 unsigned int xoffset, hstep; 680 struct fb_info_control *p = 681 container_of(info, struct fb_info_control, info); 682 struct fb_par_control *par = &p->par; 683 684 /* 685 * make sure start addr will be 32-byte aligned 686 */ 687 hstep = 0x1f >> par->cmode; 688 xoffset = (var->xoffset + hstep) & ~hstep; 689 690 if (xoffset+par->xres > par->vxres || 691 var->yoffset+par->yres > par->vyres) 692 return -EINVAL; 693 694 set_screen_start(xoffset, var->yoffset, p); 695 696 return 0; 697 } 698 699 static int controlfb_blank(int blank_mode, struct fb_info *info) 700 { 701 struct fb_info_control __maybe_unused *p = 702 container_of(info, struct fb_info_control, info); 703 unsigned ctrl; 704 705 ctrl = in_le32(CNTRL_REG(p, ctrl)); 706 if (blank_mode > 0) 707 switch (blank_mode) { 708 case FB_BLANK_VSYNC_SUSPEND: 709 ctrl &= ~3; 710 break; 711 case FB_BLANK_HSYNC_SUSPEND: 712 ctrl &= ~0x30; 713 break; 714 case FB_BLANK_POWERDOWN: 715 ctrl &= ~0x33; 716 /* fall through */ 717 case FB_BLANK_NORMAL: 718 ctrl |= 0x400; 719 break; 720 default: 721 break; 722 } 723 else { 724 ctrl &= ~0x400; 725 ctrl |= 0x33; 726 } 727 out_le32(CNTRL_REG(p,ctrl), ctrl); 728 729 return 0; 730 } 731 732 /* 733 * Private mmap since we want to have a different caching on the framebuffer 734 * for controlfb. 735 * Note there's no locking in here; it's done in fb_mmap() in fbmem.c. 736 */ 737 static int controlfb_mmap(struct fb_info *info, 738 struct vm_area_struct *vma) 739 { 740 unsigned long mmio_pgoff; 741 unsigned long start; 742 u32 len; 743 744 start = info->fix.smem_start; 745 len = info->fix.smem_len; 746 mmio_pgoff = PAGE_ALIGN((start & ~PAGE_MASK) + len) >> PAGE_SHIFT; 747 if (vma->vm_pgoff >= mmio_pgoff) { 748 if (info->var.accel_flags) 749 return -EINVAL; 750 vma->vm_pgoff -= mmio_pgoff; 751 start = info->fix.mmio_start; 752 len = info->fix.mmio_len; 753 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); 754 } else { 755 /* framebuffer */ 756 vma->vm_page_prot = pgprot_cached_wthru(vma->vm_page_prot); 757 } 758 759 return vm_iomap_memory(vma, start, len); 760 } 761 762 static const struct fb_ops controlfb_ops = { 763 .owner = THIS_MODULE, 764 .fb_check_var = controlfb_check_var, 765 .fb_set_par = controlfb_set_par, 766 .fb_setcolreg = controlfb_setcolreg, 767 .fb_pan_display = controlfb_pan_display, 768 .fb_blank = controlfb_blank, 769 .fb_mmap = controlfb_mmap, 770 .fb_fillrect = cfb_fillrect, 771 .fb_copyarea = cfb_copyarea, 772 .fb_imageblit = cfb_imageblit, 773 }; 774 775 /* 776 * Set misc info vars for this driver 777 */ 778 static void __init control_init_info(struct fb_info *info, struct fb_info_control *p) 779 { 780 /* Fill fb_info */ 781 info->par = &p->par; 782 info->fbops = &controlfb_ops; 783 info->pseudo_palette = p->pseudo_palette; 784 info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN; 785 info->screen_base = p->frame_buffer + CTRLFB_OFF; 786 787 fb_alloc_cmap(&info->cmap, 256, 0); 788 789 /* Fill fix common fields */ 790 strcpy(info->fix.id, "control"); 791 info->fix.mmio_start = p->control_regs_phys; 792 info->fix.mmio_len = sizeof(struct control_regs); 793 info->fix.type = FB_TYPE_PACKED_PIXELS; 794 info->fix.smem_start = p->frame_buffer_phys + CTRLFB_OFF; 795 info->fix.smem_len = p->total_vram - CTRLFB_OFF; 796 info->fix.ywrapstep = 0; 797 info->fix.type_aux = 0; 798 info->fix.accel = FB_ACCEL_NONE; 799 } 800 801 /* 802 * Parse user specified options (`video=controlfb:') 803 */ 804 static void __init control_setup(char *options) 805 { 806 char *this_opt; 807 808 if (!options || !*options) 809 return; 810 811 while ((this_opt = strsep(&options, ",")) != NULL) { 812 if (!strncmp(this_opt, "vmode:", 6)) { 813 int vmode = simple_strtoul(this_opt+6, NULL, 0); 814 if (vmode > 0 && vmode <= VMODE_MAX && 815 control_mac_modes[vmode - 1].m[1] >= 0) 816 default_vmode = vmode; 817 } else if (!strncmp(this_opt, "cmode:", 6)) { 818 int depth = simple_strtoul(this_opt+6, NULL, 0); 819 switch (depth) { 820 case CMODE_8: 821 case CMODE_16: 822 case CMODE_32: 823 default_cmode = depth; 824 break; 825 case 8: 826 default_cmode = CMODE_8; 827 break; 828 case 15: 829 case 16: 830 default_cmode = CMODE_16; 831 break; 832 case 24: 833 case 32: 834 default_cmode = CMODE_32; 835 break; 836 } 837 } 838 } 839 } 840 841 /* 842 * finish off the driver initialization and register 843 */ 844 static int __init init_control(struct fb_info_control *p) 845 { 846 int full, sense, vmode, cmode, vyres; 847 struct fb_var_screeninfo var; 848 int rc; 849 850 printk(KERN_INFO "controlfb: "); 851 852 full = p->total_vram == 0x400000; 853 854 /* Try to pick a video mode out of NVRAM if we have one. */ 855 cmode = default_cmode; 856 if (IS_REACHABLE(CONFIG_NVRAM) && cmode == CMODE_NVRAM) 857 cmode = nvram_read_byte(NV_CMODE); 858 if (cmode < CMODE_8 || cmode > CMODE_32) 859 cmode = CMODE_8; 860 861 vmode = default_vmode; 862 if (IS_REACHABLE(CONFIG_NVRAM) && vmode == VMODE_NVRAM) 863 vmode = nvram_read_byte(NV_VMODE); 864 if (vmode < 1 || vmode > VMODE_MAX || 865 control_mac_modes[vmode - 1].m[full] < cmode) { 866 sense = read_control_sense(p); 867 printk(KERN_CONT "Monitor sense value = 0x%x, ", sense); 868 vmode = mac_map_monitor_sense(sense); 869 if (control_mac_modes[vmode - 1].m[full] < 0) 870 vmode = VMODE_640_480_60; 871 cmode = min(cmode, control_mac_modes[vmode - 1].m[full]); 872 } 873 874 /* Initialize info structure */ 875 control_init_info(&p->info, p); 876 877 /* Setup default var */ 878 if (mac_vmode_to_var(vmode, cmode, &var) < 0) { 879 /* This shouldn't happen! */ 880 printk("mac_vmode_to_var(%d, %d,) failed\n", vmode, cmode); 881 try_again: 882 vmode = VMODE_640_480_60; 883 cmode = CMODE_8; 884 if (mac_vmode_to_var(vmode, cmode, &var) < 0) { 885 printk(KERN_ERR "controlfb: mac_vmode_to_var() failed\n"); 886 return -ENXIO; 887 } 888 printk(KERN_INFO "controlfb: "); 889 } 890 printk("using video mode %d and color mode %d.\n", vmode, cmode); 891 892 vyres = (p->total_vram - CTRLFB_OFF) / (var.xres << cmode); 893 if (vyres > var.yres) 894 var.yres_virtual = vyres; 895 896 /* Apply default var */ 897 var.activate = FB_ACTIVATE_NOW; 898 rc = fb_set_var(&p->info, &var); 899 if (rc && (vmode != VMODE_640_480_60 || cmode != CMODE_8)) 900 goto try_again; 901 902 /* Register with fbdev layer */ 903 if (register_framebuffer(&p->info) < 0) 904 return -ENXIO; 905 906 fb_info(&p->info, "control display adapter\n"); 907 908 return 0; 909 } 910 911 static void control_cleanup(void) 912 { 913 struct fb_info_control *p = control_fb; 914 915 if (!p) 916 return; 917 918 if (p->cmap_regs) 919 iounmap(p->cmap_regs); 920 if (p->control_regs) 921 iounmap(p->control_regs); 922 if (p->frame_buffer) { 923 if (p->control_use_bank2) 924 p->frame_buffer -= 0x600000; 925 iounmap(p->frame_buffer); 926 } 927 if (p->cmap_regs_phys) 928 release_mem_region(p->cmap_regs_phys, 0x1000); 929 if (p->control_regs_phys) 930 release_mem_region(p->control_regs_phys, p->control_regs_size); 931 if (p->fb_orig_base) 932 release_mem_region(p->fb_orig_base, p->fb_orig_size); 933 kfree(p); 934 } 935 936 /* 937 * find "control" and initialize 938 */ 939 static int __init control_of_init(struct device_node *dp) 940 { 941 struct fb_info_control *p; 942 struct resource fb_res, reg_res; 943 944 if (control_fb) { 945 printk(KERN_ERR "controlfb: only one control is supported\n"); 946 return -ENXIO; 947 } 948 949 if (of_pci_address_to_resource(dp, 2, &fb_res) || 950 of_pci_address_to_resource(dp, 1, ®_res)) { 951 printk(KERN_ERR "can't get 2 addresses for control\n"); 952 return -ENXIO; 953 } 954 p = kzalloc(sizeof(*p), GFP_KERNEL); 955 if (!p) 956 return -ENOMEM; 957 control_fb = p; /* save it for cleanups */ 958 959 /* Map in frame buffer and registers */ 960 p->fb_orig_base = fb_res.start; 961 p->fb_orig_size = resource_size(&fb_res); 962 /* use the big-endian aperture (??) */ 963 p->frame_buffer_phys = fb_res.start + 0x800000; 964 p->control_regs_phys = reg_res.start; 965 p->control_regs_size = resource_size(®_res); 966 967 if (!p->fb_orig_base || 968 !request_mem_region(p->fb_orig_base,p->fb_orig_size,"controlfb")) { 969 p->fb_orig_base = 0; 970 goto error_out; 971 } 972 /* map at most 8MB for the frame buffer */ 973 p->frame_buffer = ioremap_wt(p->frame_buffer_phys, 0x800000); 974 975 if (!p->control_regs_phys || 976 !request_mem_region(p->control_regs_phys, p->control_regs_size, 977 "controlfb regs")) { 978 p->control_regs_phys = 0; 979 goto error_out; 980 } 981 p->control_regs = ioremap(p->control_regs_phys, p->control_regs_size); 982 983 p->cmap_regs_phys = 0xf301b000; /* XXX not in prom? */ 984 if (!request_mem_region(p->cmap_regs_phys, 0x1000, "controlfb cmap")) { 985 p->cmap_regs_phys = 0; 986 goto error_out; 987 } 988 p->cmap_regs = ioremap(p->cmap_regs_phys, 0x1000); 989 990 if (!p->cmap_regs || !p->control_regs || !p->frame_buffer) 991 goto error_out; 992 993 find_vram_size(p); 994 if (!p->total_vram) 995 goto error_out; 996 997 if (init_control(p) < 0) 998 goto error_out; 999 1000 return 0; 1001 1002 error_out: 1003 control_cleanup(); 1004 return -ENXIO; 1005 } 1006 1007 static int __init control_init(void) 1008 { 1009 struct device_node *dp; 1010 char *option = NULL; 1011 int ret = -ENXIO; 1012 1013 if (fb_get_options("controlfb", &option)) 1014 return -ENODEV; 1015 control_setup(option); 1016 1017 dp = of_find_node_by_name(NULL, "control"); 1018 if (dp && !control_of_init(dp)) 1019 ret = 0; 1020 of_node_put(dp); 1021 1022 return ret; 1023 } 1024 1025 device_initcall(control_init); 1026