1 /* 2 * drivers/video/chipsfb.c -- frame buffer device for 3 * Chips & Technologies 65550 chip. 4 * 5 * Copyright (C) 1998-2002 Paul Mackerras 6 * 7 * This file is derived from the Powermac "chips" driver: 8 * Copyright (C) 1997 Fabio Riccardi. 9 * And from the frame buffer device for Open Firmware-initialized devices: 10 * Copyright (C) 1997 Geert Uytterhoeven. 11 * 12 * This file is subject to the terms and conditions of the GNU General Public 13 * License. See the file COPYING in the main directory of this archive for 14 * more details. 15 */ 16 17 #include <linux/aperture.h> 18 #include <linux/module.h> 19 #include <linux/kernel.h> 20 #include <linux/errno.h> 21 #include <linux/string.h> 22 #include <linux/mm.h> 23 #include <linux/vmalloc.h> 24 #include <linux/delay.h> 25 #include <linux/interrupt.h> 26 #include <linux/fb.h> 27 #include <linux/pm.h> 28 #include <linux/init.h> 29 #include <linux/pci.h> 30 #include <linux/console.h> 31 32 #ifdef CONFIG_PMAC_BACKLIGHT 33 #include <asm/backlight.h> 34 #endif 35 36 /* 37 * Since we access the display with inb/outb to fixed port numbers, 38 * we can only handle one 6555x chip. -- paulus 39 */ 40 #define write_ind(num, val, ap, dp) do { \ 41 outb((num), (ap)); outb((val), (dp)); \ 42 } while (0) 43 #define read_ind(num, var, ap, dp) do { \ 44 outb((num), (ap)); var = inb((dp)); \ 45 } while (0) 46 47 /* extension registers */ 48 #define write_xr(num, val) write_ind(num, val, 0x3d6, 0x3d7) 49 #define read_xr(num, var) read_ind(num, var, 0x3d6, 0x3d7) 50 /* flat panel registers */ 51 #define write_fr(num, val) write_ind(num, val, 0x3d0, 0x3d1) 52 #define read_fr(num, var) read_ind(num, var, 0x3d0, 0x3d1) 53 /* CRTC registers */ 54 #define write_cr(num, val) write_ind(num, val, 0x3d4, 0x3d5) 55 #define read_cr(num, var) read_ind(num, var, 0x3d4, 0x3d5) 56 /* graphics registers */ 57 #define write_gr(num, val) write_ind(num, val, 0x3ce, 0x3cf) 58 #define read_gr(num, var) read_ind(num, var, 0x3ce, 0x3cf) 59 /* sequencer registers */ 60 #define write_sr(num, val) write_ind(num, val, 0x3c4, 0x3c5) 61 #define read_sr(num, var) read_ind(num, var, 0x3c4, 0x3c5) 62 /* attribute registers - slightly strange */ 63 #define write_ar(num, val) do { \ 64 inb(0x3da); write_ind(num, val, 0x3c0, 0x3c0); \ 65 } while (0) 66 #define read_ar(num, var) do { \ 67 inb(0x3da); read_ind(num, var, 0x3c0, 0x3c1); \ 68 } while (0) 69 70 /* 71 * Exported functions 72 */ 73 int chips_init(void); 74 75 static int chipsfb_pci_init(struct pci_dev *dp, const struct pci_device_id *); 76 static int chipsfb_check_var(struct fb_var_screeninfo *var, 77 struct fb_info *info); 78 static int chipsfb_set_par(struct fb_info *info); 79 static int chipsfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, 80 u_int transp, struct fb_info *info); 81 static int chipsfb_blank(int blank, struct fb_info *info); 82 83 static const struct fb_ops chipsfb_ops = { 84 .owner = THIS_MODULE, 85 .fb_check_var = chipsfb_check_var, 86 .fb_set_par = chipsfb_set_par, 87 .fb_setcolreg = chipsfb_setcolreg, 88 .fb_blank = chipsfb_blank, 89 .fb_fillrect = cfb_fillrect, 90 .fb_copyarea = cfb_copyarea, 91 .fb_imageblit = cfb_imageblit, 92 }; 93 94 static int chipsfb_check_var(struct fb_var_screeninfo *var, 95 struct fb_info *info) 96 { 97 if (var->xres > 800 || var->yres > 600 98 || var->xres_virtual > 800 || var->yres_virtual > 600 99 || (var->bits_per_pixel != 8 && var->bits_per_pixel != 16) 100 || var->nonstd 101 || (var->vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED) 102 return -EINVAL; 103 104 var->xres = var->xres_virtual = 800; 105 var->yres = var->yres_virtual = 600; 106 107 return 0; 108 } 109 110 static int chipsfb_set_par(struct fb_info *info) 111 { 112 if (info->var.bits_per_pixel == 16) { 113 write_cr(0x13, 200); // Set line length (doublewords) 114 write_xr(0x81, 0x14); // 15 bit (555) color mode 115 write_xr(0x82, 0x00); // Disable palettes 116 write_xr(0x20, 0x10); // 16 bit blitter mode 117 118 info->fix.line_length = 800*2; 119 info->fix.visual = FB_VISUAL_TRUECOLOR; 120 121 info->var.red.offset = 10; 122 info->var.green.offset = 5; 123 info->var.blue.offset = 0; 124 info->var.red.length = info->var.green.length = 125 info->var.blue.length = 5; 126 127 } else { 128 /* p->var.bits_per_pixel == 8 */ 129 write_cr(0x13, 100); // Set line length (doublewords) 130 write_xr(0x81, 0x12); // 8 bit color mode 131 write_xr(0x82, 0x08); // Graphics gamma enable 132 write_xr(0x20, 0x00); // 8 bit blitter mode 133 134 info->fix.line_length = 800; 135 info->fix.visual = FB_VISUAL_PSEUDOCOLOR; 136 137 info->var.red.offset = info->var.green.offset = 138 info->var.blue.offset = 0; 139 info->var.red.length = info->var.green.length = 140 info->var.blue.length = 8; 141 142 } 143 return 0; 144 } 145 146 static int chipsfb_blank(int blank, struct fb_info *info) 147 { 148 return 1; /* get fb_blank to set the colormap to all black */ 149 } 150 151 static int chipsfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, 152 u_int transp, struct fb_info *info) 153 { 154 if (regno > 255) 155 return 1; 156 red >>= 8; 157 green >>= 8; 158 blue >>= 8; 159 outb(regno, 0x3c8); 160 udelay(1); 161 outb(red, 0x3c9); 162 outb(green, 0x3c9); 163 outb(blue, 0x3c9); 164 165 return 0; 166 } 167 168 struct chips_init_reg { 169 unsigned char addr; 170 unsigned char data; 171 }; 172 173 static struct chips_init_reg chips_init_sr[] = { 174 { 0x00, 0x03 }, 175 { 0x01, 0x01 }, 176 { 0x02, 0x0f }, 177 { 0x04, 0x0e } 178 }; 179 180 static struct chips_init_reg chips_init_gr[] = { 181 { 0x05, 0x00 }, 182 { 0x06, 0x0d }, 183 { 0x08, 0xff } 184 }; 185 186 static struct chips_init_reg chips_init_ar[] = { 187 { 0x10, 0x01 }, 188 { 0x12, 0x0f }, 189 { 0x13, 0x00 } 190 }; 191 192 static struct chips_init_reg chips_init_cr[] = { 193 { 0x00, 0x7f }, 194 { 0x01, 0x63 }, 195 { 0x02, 0x63 }, 196 { 0x03, 0x83 }, 197 { 0x04, 0x66 }, 198 { 0x05, 0x10 }, 199 { 0x06, 0x72 }, 200 { 0x07, 0x3e }, 201 { 0x08, 0x00 }, 202 { 0x09, 0x40 }, 203 { 0x0c, 0x00 }, 204 { 0x0d, 0x00 }, 205 { 0x10, 0x59 }, 206 { 0x11, 0x0d }, 207 { 0x12, 0x57 }, 208 { 0x13, 0x64 }, 209 { 0x14, 0x00 }, 210 { 0x15, 0x57 }, 211 { 0x16, 0x73 }, 212 { 0x17, 0xe3 }, 213 { 0x18, 0xff }, 214 { 0x30, 0x02 }, 215 { 0x31, 0x02 }, 216 { 0x32, 0x02 }, 217 { 0x33, 0x02 }, 218 { 0x40, 0x00 }, 219 { 0x41, 0x00 }, 220 { 0x40, 0x80 } 221 }; 222 223 static struct chips_init_reg chips_init_fr[] = { 224 { 0x01, 0x02 }, 225 { 0x03, 0x08 }, 226 { 0x04, 0x81 }, 227 { 0x05, 0x21 }, 228 { 0x08, 0x0c }, 229 { 0x0a, 0x74 }, 230 { 0x0b, 0x11 }, 231 { 0x10, 0x0c }, 232 { 0x11, 0xe0 }, 233 /* { 0x12, 0x40 }, -- 3400 needs 40, 2400 needs 48, no way to tell */ 234 { 0x20, 0x63 }, 235 { 0x21, 0x68 }, 236 { 0x22, 0x19 }, 237 { 0x23, 0x7f }, 238 { 0x24, 0x68 }, 239 { 0x26, 0x00 }, 240 { 0x27, 0x0f }, 241 { 0x30, 0x57 }, 242 { 0x31, 0x58 }, 243 { 0x32, 0x0d }, 244 { 0x33, 0x72 }, 245 { 0x34, 0x02 }, 246 { 0x35, 0x22 }, 247 { 0x36, 0x02 }, 248 { 0x37, 0x00 } 249 }; 250 251 static struct chips_init_reg chips_init_xr[] = { 252 { 0xce, 0x00 }, /* set default memory clock */ 253 { 0xcc, 0x43 }, /* memory clock ratio */ 254 { 0xcd, 0x18 }, 255 { 0xce, 0xa1 }, 256 { 0xc8, 0x84 }, 257 { 0xc9, 0x0a }, 258 { 0xca, 0x00 }, 259 { 0xcb, 0x20 }, 260 { 0xcf, 0x06 }, 261 { 0xd0, 0x0e }, 262 { 0x09, 0x01 }, 263 { 0x0a, 0x02 }, 264 { 0x0b, 0x01 }, 265 { 0x20, 0x00 }, 266 { 0x40, 0x03 }, 267 { 0x41, 0x01 }, 268 { 0x42, 0x00 }, 269 { 0x80, 0x82 }, 270 { 0x81, 0x12 }, 271 { 0x82, 0x08 }, 272 { 0xa0, 0x00 }, 273 { 0xa8, 0x00 } 274 }; 275 276 static void chips_hw_init(void) 277 { 278 int i; 279 280 for (i = 0; i < ARRAY_SIZE(chips_init_xr); ++i) 281 write_xr(chips_init_xr[i].addr, chips_init_xr[i].data); 282 outb(0x29, 0x3c2); /* set misc output reg */ 283 for (i = 0; i < ARRAY_SIZE(chips_init_sr); ++i) 284 write_sr(chips_init_sr[i].addr, chips_init_sr[i].data); 285 for (i = 0; i < ARRAY_SIZE(chips_init_gr); ++i) 286 write_gr(chips_init_gr[i].addr, chips_init_gr[i].data); 287 for (i = 0; i < ARRAY_SIZE(chips_init_ar); ++i) 288 write_ar(chips_init_ar[i].addr, chips_init_ar[i].data); 289 for (i = 0; i < ARRAY_SIZE(chips_init_cr); ++i) 290 write_cr(chips_init_cr[i].addr, chips_init_cr[i].data); 291 for (i = 0; i < ARRAY_SIZE(chips_init_fr); ++i) 292 write_fr(chips_init_fr[i].addr, chips_init_fr[i].data); 293 } 294 295 static const struct fb_fix_screeninfo chipsfb_fix = { 296 .id = "C&T 65550", 297 .type = FB_TYPE_PACKED_PIXELS, 298 .visual = FB_VISUAL_PSEUDOCOLOR, 299 .accel = FB_ACCEL_NONE, 300 .line_length = 800, 301 302 // FIXME: Assumes 1MB frame buffer, but 65550 supports 1MB or 2MB. 303 // * "3500" PowerBook G3 (the original PB G3) has 2MB. 304 // * 2400 has 1MB composed of 2 Mitsubishi M5M4V4265CTP DRAM chips. 305 // Motherboard actually supports 2MB -- there are two blank locations 306 // for a second pair of DRAMs. (Thanks, Apple!) 307 // * 3400 has 1MB (I think). Don't know if it's expandable. 308 // -- Tim Seufert 309 .smem_len = 0x100000, /* 1MB */ 310 }; 311 312 static const struct fb_var_screeninfo chipsfb_var = { 313 .xres = 800, 314 .yres = 600, 315 .xres_virtual = 800, 316 .yres_virtual = 600, 317 .bits_per_pixel = 8, 318 .red = { .length = 8 }, 319 .green = { .length = 8 }, 320 .blue = { .length = 8 }, 321 .height = -1, 322 .width = -1, 323 .vmode = FB_VMODE_NONINTERLACED, 324 .pixclock = 10000, 325 .left_margin = 16, 326 .right_margin = 16, 327 .upper_margin = 16, 328 .lower_margin = 16, 329 .hsync_len = 8, 330 .vsync_len = 8, 331 }; 332 333 static void init_chips(struct fb_info *p, unsigned long addr) 334 { 335 fb_memset(p->screen_base, 0, 0x100000); 336 337 p->fix = chipsfb_fix; 338 p->fix.smem_start = addr; 339 340 p->var = chipsfb_var; 341 342 p->fbops = &chipsfb_ops; 343 p->flags = FBINFO_DEFAULT; 344 345 fb_alloc_cmap(&p->cmap, 256, 0); 346 347 chips_hw_init(); 348 } 349 350 static int chipsfb_pci_init(struct pci_dev *dp, const struct pci_device_id *ent) 351 { 352 struct fb_info *p; 353 unsigned long addr; 354 unsigned short cmd; 355 int rc; 356 357 rc = aperture_remove_conflicting_pci_devices(dp, "chipsfb"); 358 if (rc) 359 return rc; 360 361 if (pci_enable_device(dp) < 0) { 362 dev_err(&dp->dev, "Cannot enable PCI device\n"); 363 goto err_out; 364 } 365 366 if ((dp->resource[0].flags & IORESOURCE_MEM) == 0) 367 goto err_disable; 368 addr = pci_resource_start(dp, 0); 369 if (addr == 0) 370 goto err_disable; 371 372 p = framebuffer_alloc(0, &dp->dev); 373 if (p == NULL) { 374 rc = -ENOMEM; 375 goto err_disable; 376 } 377 378 if (pci_request_region(dp, 0, "chipsfb") != 0) { 379 dev_err(&dp->dev, "Cannot request framebuffer\n"); 380 rc = -EBUSY; 381 goto err_release_fb; 382 } 383 384 #ifdef __BIG_ENDIAN 385 addr += 0x800000; // Use big-endian aperture 386 #endif 387 388 /* we should use pci_enable_device here, but, 389 the device doesn't declare its I/O ports in its BARs 390 so pci_enable_device won't turn on I/O responses */ 391 pci_read_config_word(dp, PCI_COMMAND, &cmd); 392 cmd |= 3; /* enable memory and IO space */ 393 pci_write_config_word(dp, PCI_COMMAND, cmd); 394 395 #ifdef CONFIG_PMAC_BACKLIGHT 396 /* turn on the backlight */ 397 mutex_lock(&pmac_backlight_mutex); 398 if (pmac_backlight) { 399 pmac_backlight->props.power = FB_BLANK_UNBLANK; 400 backlight_update_status(pmac_backlight); 401 } 402 mutex_unlock(&pmac_backlight_mutex); 403 #endif /* CONFIG_PMAC_BACKLIGHT */ 404 405 #ifdef CONFIG_PPC 406 p->screen_base = ioremap_wc(addr, 0x200000); 407 #else 408 p->screen_base = ioremap(addr, 0x200000); 409 #endif 410 if (p->screen_base == NULL) { 411 dev_err(&dp->dev, "Cannot map framebuffer\n"); 412 rc = -ENOMEM; 413 goto err_release_pci; 414 } 415 416 pci_set_drvdata(dp, p); 417 418 init_chips(p, addr); 419 420 if (register_framebuffer(p) < 0) { 421 dev_err(&dp->dev,"C&T 65550 framebuffer failed to register\n"); 422 goto err_unmap; 423 } 424 425 dev_info(&dp->dev,"fb%d: Chips 65550 frame buffer" 426 " (%dK RAM detected)\n", 427 p->node, p->fix.smem_len / 1024); 428 429 return 0; 430 431 err_unmap: 432 iounmap(p->screen_base); 433 err_release_pci: 434 pci_release_region(dp, 0); 435 err_release_fb: 436 framebuffer_release(p); 437 err_disable: 438 pci_disable_device(dp); 439 err_out: 440 return rc; 441 } 442 443 static void chipsfb_remove(struct pci_dev *dp) 444 { 445 struct fb_info *p = pci_get_drvdata(dp); 446 447 if (p->screen_base == NULL) 448 return; 449 unregister_framebuffer(p); 450 iounmap(p->screen_base); 451 p->screen_base = NULL; 452 pci_release_region(dp, 0); 453 } 454 455 #ifdef CONFIG_PM 456 static int chipsfb_pci_suspend(struct pci_dev *pdev, pm_message_t state) 457 { 458 struct fb_info *p = pci_get_drvdata(pdev); 459 460 if (state.event == pdev->dev.power.power_state.event) 461 return 0; 462 if (!(state.event & PM_EVENT_SLEEP)) 463 goto done; 464 465 console_lock(); 466 chipsfb_blank(1, p); 467 fb_set_suspend(p, 1); 468 console_unlock(); 469 done: 470 pdev->dev.power.power_state = state; 471 return 0; 472 } 473 474 static int chipsfb_pci_resume(struct pci_dev *pdev) 475 { 476 struct fb_info *p = pci_get_drvdata(pdev); 477 478 console_lock(); 479 fb_set_suspend(p, 0); 480 chipsfb_blank(0, p); 481 console_unlock(); 482 483 pdev->dev.power.power_state = PMSG_ON; 484 return 0; 485 } 486 #endif /* CONFIG_PM */ 487 488 489 static struct pci_device_id chipsfb_pci_tbl[] = { 490 { PCI_VENDOR_ID_CT, PCI_DEVICE_ID_CT_65550, PCI_ANY_ID, PCI_ANY_ID }, 491 { 0 } 492 }; 493 494 MODULE_DEVICE_TABLE(pci, chipsfb_pci_tbl); 495 496 static struct pci_driver chipsfb_driver = { 497 .name = "chipsfb", 498 .id_table = chipsfb_pci_tbl, 499 .probe = chipsfb_pci_init, 500 .remove = chipsfb_remove, 501 #ifdef CONFIG_PM 502 .suspend = chipsfb_pci_suspend, 503 .resume = chipsfb_pci_resume, 504 #endif 505 }; 506 507 int __init chips_init(void) 508 { 509 if (fb_get_options("chipsfb", NULL)) 510 return -ENODEV; 511 512 return pci_register_driver(&chipsfb_driver); 513 } 514 515 module_init(chips_init); 516 517 static void __exit chipsfb_exit(void) 518 { 519 pci_unregister_driver(&chipsfb_driver); 520 } 521 522 MODULE_LICENSE("GPL"); 523