1 // SPDX-License-Identifier: GPL-2.0-only 2 /* cg6.c: CGSIX (GX, GXplus, TGX) frame buffer driver 3 * 4 * Copyright (C) 2003, 2006 David S. Miller (davem@davemloft.net) 5 * Copyright (C) 1996,1998 Jakub Jelinek (jj@ultra.linux.cz) 6 * Copyright (C) 1996 Miguel de Icaza (miguel@nuclecu.unam.mx) 7 * Copyright (C) 1996 Eddie C. Dost (ecd@skynet.be) 8 * 9 * Driver layout based loosely on tgafb.c, see that file for credits. 10 */ 11 12 #include <linux/module.h> 13 #include <linux/kernel.h> 14 #include <linux/errno.h> 15 #include <linux/string.h> 16 #include <linux/delay.h> 17 #include <linux/init.h> 18 #include <linux/fb.h> 19 #include <linux/mm.h> 20 #include <linux/of.h> 21 #include <linux/platform_device.h> 22 23 #include <asm/io.h> 24 #include <asm/fbio.h> 25 26 #include "sbuslib.h" 27 28 /* 29 * Local functions. 30 */ 31 32 static int cg6_setcolreg(unsigned, unsigned, unsigned, unsigned, 33 unsigned, struct fb_info *); 34 static int cg6_blank(int, struct fb_info *); 35 36 static void cg6_imageblit(struct fb_info *, const struct fb_image *); 37 static void cg6_fillrect(struct fb_info *, const struct fb_fillrect *); 38 static void cg6_copyarea(struct fb_info *info, const struct fb_copyarea *area); 39 static int cg6_sync(struct fb_info *); 40 static int cg6_mmap(struct fb_info *, struct vm_area_struct *); 41 static int cg6_ioctl(struct fb_info *, unsigned int, unsigned long); 42 static int cg6_pan_display(struct fb_var_screeninfo *, struct fb_info *); 43 44 /* 45 * Frame buffer operations 46 */ 47 48 static const struct fb_ops cg6_ops = { 49 .owner = THIS_MODULE, 50 .fb_setcolreg = cg6_setcolreg, 51 .fb_blank = cg6_blank, 52 .fb_pan_display = cg6_pan_display, 53 .fb_fillrect = cg6_fillrect, 54 .fb_copyarea = cg6_copyarea, 55 .fb_imageblit = cg6_imageblit, 56 .fb_sync = cg6_sync, 57 .fb_mmap = cg6_mmap, 58 .fb_ioctl = cg6_ioctl, 59 #ifdef CONFIG_COMPAT 60 .fb_compat_ioctl = sbusfb_compat_ioctl, 61 #endif 62 }; 63 64 /* Offset of interesting structures in the OBIO space */ 65 /* 66 * Brooktree is the video dac and is funny to program on the cg6. 67 * (it's even funnier on the cg3) 68 * The FBC could be the frame buffer control 69 * The FHC could is the frame buffer hardware control. 70 */ 71 #define CG6_ROM_OFFSET 0x0UL 72 #define CG6_BROOKTREE_OFFSET 0x200000UL 73 #define CG6_DHC_OFFSET 0x240000UL 74 #define CG6_ALT_OFFSET 0x280000UL 75 #define CG6_FHC_OFFSET 0x300000UL 76 #define CG6_THC_OFFSET 0x301000UL 77 #define CG6_FBC_OFFSET 0x700000UL 78 #define CG6_TEC_OFFSET 0x701000UL 79 #define CG6_RAM_OFFSET 0x800000UL 80 81 /* FHC definitions */ 82 #define CG6_FHC_FBID_SHIFT 24 83 #define CG6_FHC_FBID_MASK 255 84 #define CG6_FHC_REV_SHIFT 20 85 #define CG6_FHC_REV_MASK 15 86 #define CG6_FHC_FROP_DISABLE (1 << 19) 87 #define CG6_FHC_ROW_DISABLE (1 << 18) 88 #define CG6_FHC_SRC_DISABLE (1 << 17) 89 #define CG6_FHC_DST_DISABLE (1 << 16) 90 #define CG6_FHC_RESET (1 << 15) 91 #define CG6_FHC_LITTLE_ENDIAN (1 << 13) 92 #define CG6_FHC_RES_MASK (3 << 11) 93 #define CG6_FHC_1024 (0 << 11) 94 #define CG6_FHC_1152 (1 << 11) 95 #define CG6_FHC_1280 (2 << 11) 96 #define CG6_FHC_1600 (3 << 11) 97 #define CG6_FHC_CPU_MASK (3 << 9) 98 #define CG6_FHC_CPU_SPARC (0 << 9) 99 #define CG6_FHC_CPU_68020 (1 << 9) 100 #define CG6_FHC_CPU_386 (2 << 9) 101 #define CG6_FHC_TEST (1 << 8) 102 #define CG6_FHC_TEST_X_SHIFT 4 103 #define CG6_FHC_TEST_X_MASK 15 104 #define CG6_FHC_TEST_Y_SHIFT 0 105 #define CG6_FHC_TEST_Y_MASK 15 106 107 /* FBC mode definitions */ 108 #define CG6_FBC_BLIT_IGNORE 0x00000000 109 #define CG6_FBC_BLIT_NOSRC 0x00100000 110 #define CG6_FBC_BLIT_SRC 0x00200000 111 #define CG6_FBC_BLIT_ILLEGAL 0x00300000 112 #define CG6_FBC_BLIT_MASK 0x00300000 113 114 #define CG6_FBC_VBLANK 0x00080000 115 116 #define CG6_FBC_MODE_IGNORE 0x00000000 117 #define CG6_FBC_MODE_COLOR8 0x00020000 118 #define CG6_FBC_MODE_COLOR1 0x00040000 119 #define CG6_FBC_MODE_HRMONO 0x00060000 120 #define CG6_FBC_MODE_MASK 0x00060000 121 122 #define CG6_FBC_DRAW_IGNORE 0x00000000 123 #define CG6_FBC_DRAW_RENDER 0x00008000 124 #define CG6_FBC_DRAW_PICK 0x00010000 125 #define CG6_FBC_DRAW_ILLEGAL 0x00018000 126 #define CG6_FBC_DRAW_MASK 0x00018000 127 128 #define CG6_FBC_BWRITE0_IGNORE 0x00000000 129 #define CG6_FBC_BWRITE0_ENABLE 0x00002000 130 #define CG6_FBC_BWRITE0_DISABLE 0x00004000 131 #define CG6_FBC_BWRITE0_ILLEGAL 0x00006000 132 #define CG6_FBC_BWRITE0_MASK 0x00006000 133 134 #define CG6_FBC_BWRITE1_IGNORE 0x00000000 135 #define CG6_FBC_BWRITE1_ENABLE 0x00000800 136 #define CG6_FBC_BWRITE1_DISABLE 0x00001000 137 #define CG6_FBC_BWRITE1_ILLEGAL 0x00001800 138 #define CG6_FBC_BWRITE1_MASK 0x00001800 139 140 #define CG6_FBC_BREAD_IGNORE 0x00000000 141 #define CG6_FBC_BREAD_0 0x00000200 142 #define CG6_FBC_BREAD_1 0x00000400 143 #define CG6_FBC_BREAD_ILLEGAL 0x00000600 144 #define CG6_FBC_BREAD_MASK 0x00000600 145 146 #define CG6_FBC_BDISP_IGNORE 0x00000000 147 #define CG6_FBC_BDISP_0 0x00000080 148 #define CG6_FBC_BDISP_1 0x00000100 149 #define CG6_FBC_BDISP_ILLEGAL 0x00000180 150 #define CG6_FBC_BDISP_MASK 0x00000180 151 152 #define CG6_FBC_INDEX_MOD 0x00000040 153 #define CG6_FBC_INDEX_MASK 0x00000030 154 155 /* THC definitions */ 156 #define CG6_THC_MISC_REV_SHIFT 16 157 #define CG6_THC_MISC_REV_MASK 15 158 #define CG6_THC_MISC_RESET (1 << 12) 159 #define CG6_THC_MISC_VIDEO (1 << 10) 160 #define CG6_THC_MISC_SYNC (1 << 9) 161 #define CG6_THC_MISC_VSYNC (1 << 8) 162 #define CG6_THC_MISC_SYNC_ENAB (1 << 7) 163 #define CG6_THC_MISC_CURS_RES (1 << 6) 164 #define CG6_THC_MISC_INT_ENAB (1 << 5) 165 #define CG6_THC_MISC_INT (1 << 4) 166 #define CG6_THC_MISC_INIT 0x9f 167 #define CG6_THC_CURSOFF ((65536-32) | ((65536-32) << 16)) 168 169 /* The contents are unknown */ 170 struct cg6_tec { 171 int tec_matrix; 172 int tec_clip; 173 int tec_vdc; 174 }; 175 176 struct cg6_thc { 177 u32 thc_pad0[512]; 178 u32 thc_hs; /* hsync timing */ 179 u32 thc_hsdvs; 180 u32 thc_hd; 181 u32 thc_vs; /* vsync timing */ 182 u32 thc_vd; 183 u32 thc_refresh; 184 u32 thc_misc; 185 u32 thc_pad1[56]; 186 u32 thc_cursxy; /* cursor x,y position (16 bits each) */ 187 u32 thc_cursmask[32]; /* cursor mask bits */ 188 u32 thc_cursbits[32]; /* what to show where mask enabled */ 189 }; 190 191 struct cg6_fbc { 192 u32 xxx0[1]; 193 u32 mode; 194 u32 clip; 195 u32 xxx1[1]; 196 u32 s; 197 u32 draw; 198 u32 blit; 199 u32 font; 200 u32 xxx2[24]; 201 u32 x0, y0, z0, color0; 202 u32 x1, y1, z1, color1; 203 u32 x2, y2, z2, color2; 204 u32 x3, y3, z3, color3; 205 u32 offx, offy; 206 u32 xxx3[2]; 207 u32 incx, incy; 208 u32 xxx4[2]; 209 u32 clipminx, clipminy; 210 u32 xxx5[2]; 211 u32 clipmaxx, clipmaxy; 212 u32 xxx6[2]; 213 u32 fg; 214 u32 bg; 215 u32 alu; 216 u32 pm; 217 u32 pixelm; 218 u32 xxx7[2]; 219 u32 patalign; 220 u32 pattern[8]; 221 u32 xxx8[432]; 222 u32 apointx, apointy, apointz; 223 u32 xxx9[1]; 224 u32 rpointx, rpointy, rpointz; 225 u32 xxx10[5]; 226 u32 pointr, pointg, pointb, pointa; 227 u32 alinex, aliney, alinez; 228 u32 xxx11[1]; 229 u32 rlinex, rliney, rlinez; 230 u32 xxx12[5]; 231 u32 liner, lineg, lineb, linea; 232 u32 atrix, atriy, atriz; 233 u32 xxx13[1]; 234 u32 rtrix, rtriy, rtriz; 235 u32 xxx14[5]; 236 u32 trir, trig, trib, tria; 237 u32 aquadx, aquady, aquadz; 238 u32 xxx15[1]; 239 u32 rquadx, rquady, rquadz; 240 u32 xxx16[5]; 241 u32 quadr, quadg, quadb, quada; 242 u32 arectx, arecty, arectz; 243 u32 xxx17[1]; 244 u32 rrectx, rrecty, rrectz; 245 u32 xxx18[5]; 246 u32 rectr, rectg, rectb, recta; 247 }; 248 249 struct bt_regs { 250 u32 addr; 251 u32 color_map; 252 u32 control; 253 u32 cursor; 254 }; 255 256 struct cg6_par { 257 spinlock_t lock; 258 struct bt_regs __iomem *bt; 259 struct cg6_fbc __iomem *fbc; 260 struct cg6_thc __iomem *thc; 261 struct cg6_tec __iomem *tec; 262 u32 __iomem *fhc; 263 264 u32 flags; 265 #define CG6_FLAG_BLANKED 0x00000001 266 267 unsigned long which_io; 268 }; 269 270 static int cg6_sync(struct fb_info *info) 271 { 272 struct cg6_par *par = (struct cg6_par *)info->par; 273 struct cg6_fbc __iomem *fbc = par->fbc; 274 int limit = 10000; 275 276 do { 277 if (!(sbus_readl(&fbc->s) & 0x10000000)) 278 break; 279 udelay(10); 280 } while (--limit > 0); 281 282 return 0; 283 } 284 285 static void cg6_switch_from_graph(struct cg6_par *par) 286 { 287 struct cg6_thc __iomem *thc = par->thc; 288 unsigned long flags; 289 290 spin_lock_irqsave(&par->lock, flags); 291 292 /* Hide the cursor. */ 293 sbus_writel(CG6_THC_CURSOFF, &thc->thc_cursxy); 294 295 spin_unlock_irqrestore(&par->lock, flags); 296 } 297 298 static int cg6_pan_display(struct fb_var_screeninfo *var, struct fb_info *info) 299 { 300 struct cg6_par *par = (struct cg6_par *)info->par; 301 302 /* We just use this to catch switches out of 303 * graphics mode. 304 */ 305 cg6_switch_from_graph(par); 306 307 if (var->xoffset || var->yoffset || var->vmode) 308 return -EINVAL; 309 return 0; 310 } 311 312 /** 313 * cg6_fillrect - Draws a rectangle on the screen. 314 * 315 * @info: frame buffer structure that represents a single frame buffer 316 * @rect: structure defining the rectagle and operation. 317 */ 318 static void cg6_fillrect(struct fb_info *info, const struct fb_fillrect *rect) 319 { 320 struct cg6_par *par = (struct cg6_par *)info->par; 321 struct cg6_fbc __iomem *fbc = par->fbc; 322 unsigned long flags; 323 s32 val; 324 325 /* CG6 doesn't handle ROP_XOR */ 326 327 spin_lock_irqsave(&par->lock, flags); 328 329 cg6_sync(info); 330 331 sbus_writel(rect->color, &fbc->fg); 332 sbus_writel(~(u32)0, &fbc->pixelm); 333 sbus_writel(0xea80ff00, &fbc->alu); 334 sbus_writel(0, &fbc->s); 335 sbus_writel(0, &fbc->clip); 336 sbus_writel(~(u32)0, &fbc->pm); 337 sbus_writel(rect->dy, &fbc->arecty); 338 sbus_writel(rect->dx, &fbc->arectx); 339 sbus_writel(rect->dy + rect->height, &fbc->arecty); 340 sbus_writel(rect->dx + rect->width, &fbc->arectx); 341 do { 342 val = sbus_readl(&fbc->draw); 343 } while (val < 0 && (val & 0x20000000)); 344 spin_unlock_irqrestore(&par->lock, flags); 345 } 346 347 /** 348 * cg6_copyarea - Copies one area of the screen to another area. 349 * 350 * @info: frame buffer structure that represents a single frame buffer 351 * @area: Structure providing the data to copy the framebuffer contents 352 * from one region to another. 353 * 354 * This drawing operation copies a rectangular area from one area of the 355 * screen to another area. 356 */ 357 static void cg6_copyarea(struct fb_info *info, const struct fb_copyarea *area) 358 { 359 struct cg6_par *par = (struct cg6_par *)info->par; 360 struct cg6_fbc __iomem *fbc = par->fbc; 361 unsigned long flags; 362 int i; 363 364 spin_lock_irqsave(&par->lock, flags); 365 366 cg6_sync(info); 367 368 sbus_writel(0xff, &fbc->fg); 369 sbus_writel(0x00, &fbc->bg); 370 sbus_writel(~0, &fbc->pixelm); 371 sbus_writel(0xe880cccc, &fbc->alu); 372 sbus_writel(0, &fbc->s); 373 sbus_writel(0, &fbc->clip); 374 375 sbus_writel(area->sy, &fbc->y0); 376 sbus_writel(area->sx, &fbc->x0); 377 sbus_writel(area->sy + area->height - 1, &fbc->y1); 378 sbus_writel(area->sx + area->width - 1, &fbc->x1); 379 sbus_writel(area->dy, &fbc->y2); 380 sbus_writel(area->dx, &fbc->x2); 381 sbus_writel(area->dy + area->height - 1, &fbc->y3); 382 sbus_writel(area->dx + area->width - 1, &fbc->x3); 383 do { 384 i = sbus_readl(&fbc->blit); 385 } while (i < 0 && (i & 0x20000000)); 386 spin_unlock_irqrestore(&par->lock, flags); 387 } 388 389 /** 390 * cg6_imageblit - Copies a image from system memory to the screen. 391 * 392 * @info: frame buffer structure that represents a single frame buffer 393 * @image: structure defining the image. 394 */ 395 static void cg6_imageblit(struct fb_info *info, const struct fb_image *image) 396 { 397 struct cg6_par *par = (struct cg6_par *)info->par; 398 struct cg6_fbc __iomem *fbc = par->fbc; 399 const u8 *data = image->data; 400 unsigned long flags; 401 u32 x, y; 402 int i, width; 403 404 if (image->depth > 1) { 405 cfb_imageblit(info, image); 406 return; 407 } 408 409 spin_lock_irqsave(&par->lock, flags); 410 411 cg6_sync(info); 412 413 sbus_writel(image->fg_color, &fbc->fg); 414 sbus_writel(image->bg_color, &fbc->bg); 415 sbus_writel(0x140000, &fbc->mode); 416 sbus_writel(0xe880fc30, &fbc->alu); 417 sbus_writel(~(u32)0, &fbc->pixelm); 418 sbus_writel(0, &fbc->s); 419 sbus_writel(0, &fbc->clip); 420 sbus_writel(0xff, &fbc->pm); 421 sbus_writel(32, &fbc->incx); 422 sbus_writel(0, &fbc->incy); 423 424 x = image->dx; 425 y = image->dy; 426 for (i = 0; i < image->height; i++) { 427 width = image->width; 428 429 while (width >= 32) { 430 u32 val; 431 432 sbus_writel(y, &fbc->y0); 433 sbus_writel(x, &fbc->x0); 434 sbus_writel(x + 32 - 1, &fbc->x1); 435 436 val = ((u32)data[0] << 24) | 437 ((u32)data[1] << 16) | 438 ((u32)data[2] << 8) | 439 ((u32)data[3] << 0); 440 sbus_writel(val, &fbc->font); 441 442 data += 4; 443 x += 32; 444 width -= 32; 445 } 446 if (width) { 447 u32 val; 448 449 sbus_writel(y, &fbc->y0); 450 sbus_writel(x, &fbc->x0); 451 sbus_writel(x + width - 1, &fbc->x1); 452 if (width <= 8) { 453 val = (u32) data[0] << 24; 454 data += 1; 455 } else if (width <= 16) { 456 val = ((u32) data[0] << 24) | 457 ((u32) data[1] << 16); 458 data += 2; 459 } else { 460 val = ((u32) data[0] << 24) | 461 ((u32) data[1] << 16) | 462 ((u32) data[2] << 8); 463 data += 3; 464 } 465 sbus_writel(val, &fbc->font); 466 } 467 468 y += 1; 469 x = image->dx; 470 } 471 472 spin_unlock_irqrestore(&par->lock, flags); 473 } 474 475 /** 476 * cg6_setcolreg - Sets a color register. 477 * 478 * @regno: boolean, 0 copy local, 1 get_user() function 479 * @red: frame buffer colormap structure 480 * @green: The green value which can be up to 16 bits wide 481 * @blue: The blue value which can be up to 16 bits wide. 482 * @transp: If supported the alpha value which can be up to 16 bits wide. 483 * @info: frame buffer info structure 484 */ 485 static int cg6_setcolreg(unsigned regno, 486 unsigned red, unsigned green, unsigned blue, 487 unsigned transp, struct fb_info *info) 488 { 489 struct cg6_par *par = (struct cg6_par *)info->par; 490 struct bt_regs __iomem *bt = par->bt; 491 unsigned long flags; 492 493 if (regno >= 256) 494 return 1; 495 496 red >>= 8; 497 green >>= 8; 498 blue >>= 8; 499 500 spin_lock_irqsave(&par->lock, flags); 501 502 sbus_writel((u32)regno << 24, &bt->addr); 503 sbus_writel((u32)red << 24, &bt->color_map); 504 sbus_writel((u32)green << 24, &bt->color_map); 505 sbus_writel((u32)blue << 24, &bt->color_map); 506 507 spin_unlock_irqrestore(&par->lock, flags); 508 509 return 0; 510 } 511 512 /** 513 * cg6_blank - Blanks the display. 514 * 515 * @blank: the blank mode we want. 516 * @info: frame buffer structure that represents a single frame buffer 517 */ 518 static int cg6_blank(int blank, struct fb_info *info) 519 { 520 struct cg6_par *par = (struct cg6_par *)info->par; 521 struct cg6_thc __iomem *thc = par->thc; 522 unsigned long flags; 523 u32 val; 524 525 spin_lock_irqsave(&par->lock, flags); 526 val = sbus_readl(&thc->thc_misc); 527 528 switch (blank) { 529 case FB_BLANK_UNBLANK: /* Unblanking */ 530 val |= CG6_THC_MISC_VIDEO; 531 par->flags &= ~CG6_FLAG_BLANKED; 532 break; 533 534 case FB_BLANK_NORMAL: /* Normal blanking */ 535 case FB_BLANK_VSYNC_SUSPEND: /* VESA blank (vsync off) */ 536 case FB_BLANK_HSYNC_SUSPEND: /* VESA blank (hsync off) */ 537 case FB_BLANK_POWERDOWN: /* Poweroff */ 538 val &= ~CG6_THC_MISC_VIDEO; 539 par->flags |= CG6_FLAG_BLANKED; 540 break; 541 } 542 543 sbus_writel(val, &thc->thc_misc); 544 spin_unlock_irqrestore(&par->lock, flags); 545 546 return 0; 547 } 548 549 static struct sbus_mmap_map cg6_mmap_map[] = { 550 { 551 .voff = CG6_FBC, 552 .poff = CG6_FBC_OFFSET, 553 .size = PAGE_SIZE 554 }, 555 { 556 .voff = CG6_TEC, 557 .poff = CG6_TEC_OFFSET, 558 .size = PAGE_SIZE 559 }, 560 { 561 .voff = CG6_BTREGS, 562 .poff = CG6_BROOKTREE_OFFSET, 563 .size = PAGE_SIZE 564 }, 565 { 566 .voff = CG6_FHC, 567 .poff = CG6_FHC_OFFSET, 568 .size = PAGE_SIZE 569 }, 570 { 571 .voff = CG6_THC, 572 .poff = CG6_THC_OFFSET, 573 .size = PAGE_SIZE 574 }, 575 { 576 .voff = CG6_ROM, 577 .poff = CG6_ROM_OFFSET, 578 .size = 0x10000 579 }, 580 { 581 .voff = CG6_RAM, 582 .poff = CG6_RAM_OFFSET, 583 .size = SBUS_MMAP_FBSIZE(1) 584 }, 585 { 586 .voff = CG6_DHC, 587 .poff = CG6_DHC_OFFSET, 588 .size = 0x40000 589 }, 590 { .size = 0 } 591 }; 592 593 static int cg6_mmap(struct fb_info *info, struct vm_area_struct *vma) 594 { 595 struct cg6_par *par = (struct cg6_par *)info->par; 596 597 return sbusfb_mmap_helper(cg6_mmap_map, 598 info->fix.smem_start, info->fix.smem_len, 599 par->which_io, vma); 600 } 601 602 static int cg6_ioctl(struct fb_info *info, unsigned int cmd, unsigned long arg) 603 { 604 return sbusfb_ioctl_helper(cmd, arg, info, 605 FBTYPE_SUNFAST_COLOR, 8, info->fix.smem_len); 606 } 607 608 /* 609 * Initialisation 610 */ 611 612 static void cg6_init_fix(struct fb_info *info, int linebytes) 613 { 614 struct cg6_par *par = (struct cg6_par *)info->par; 615 const char *cg6_cpu_name, *cg6_card_name; 616 u32 conf; 617 618 conf = sbus_readl(par->fhc); 619 switch (conf & CG6_FHC_CPU_MASK) { 620 case CG6_FHC_CPU_SPARC: 621 cg6_cpu_name = "sparc"; 622 break; 623 case CG6_FHC_CPU_68020: 624 cg6_cpu_name = "68020"; 625 break; 626 default: 627 cg6_cpu_name = "i386"; 628 break; 629 } 630 if (((conf >> CG6_FHC_REV_SHIFT) & CG6_FHC_REV_MASK) >= 11) { 631 if (info->fix.smem_len <= 0x100000) 632 cg6_card_name = "TGX"; 633 else 634 cg6_card_name = "TGX+"; 635 } else { 636 if (info->fix.smem_len <= 0x100000) 637 cg6_card_name = "GX"; 638 else 639 cg6_card_name = "GX+"; 640 } 641 642 sprintf(info->fix.id, "%s %s", cg6_card_name, cg6_cpu_name); 643 info->fix.id[sizeof(info->fix.id) - 1] = 0; 644 645 info->fix.type = FB_TYPE_PACKED_PIXELS; 646 info->fix.visual = FB_VISUAL_PSEUDOCOLOR; 647 648 info->fix.line_length = linebytes; 649 650 info->fix.accel = FB_ACCEL_SUN_CGSIX; 651 } 652 653 /* Initialize Brooktree DAC */ 654 static void cg6_bt_init(struct cg6_par *par) 655 { 656 struct bt_regs __iomem *bt = par->bt; 657 658 sbus_writel(0x04 << 24, &bt->addr); /* color planes */ 659 sbus_writel(0xff << 24, &bt->control); 660 sbus_writel(0x05 << 24, &bt->addr); 661 sbus_writel(0x00 << 24, &bt->control); 662 sbus_writel(0x06 << 24, &bt->addr); /* overlay plane */ 663 sbus_writel(0x73 << 24, &bt->control); 664 sbus_writel(0x07 << 24, &bt->addr); 665 sbus_writel(0x00 << 24, &bt->control); 666 } 667 668 static void cg6_chip_init(struct fb_info *info) 669 { 670 struct cg6_par *par = (struct cg6_par *)info->par; 671 struct cg6_tec __iomem *tec = par->tec; 672 struct cg6_fbc __iomem *fbc = par->fbc; 673 struct cg6_thc __iomem *thc = par->thc; 674 u32 rev, conf, mode; 675 int i; 676 677 /* Hide the cursor. */ 678 sbus_writel(CG6_THC_CURSOFF, &thc->thc_cursxy); 679 680 /* Turn off stuff in the Transform Engine. */ 681 sbus_writel(0, &tec->tec_matrix); 682 sbus_writel(0, &tec->tec_clip); 683 sbus_writel(0, &tec->tec_vdc); 684 685 /* Take care of bugs in old revisions. */ 686 rev = (sbus_readl(par->fhc) >> CG6_FHC_REV_SHIFT) & CG6_FHC_REV_MASK; 687 if (rev < 5) { 688 conf = (sbus_readl(par->fhc) & CG6_FHC_RES_MASK) | 689 CG6_FHC_CPU_68020 | CG6_FHC_TEST | 690 (11 << CG6_FHC_TEST_X_SHIFT) | 691 (11 << CG6_FHC_TEST_Y_SHIFT); 692 if (rev < 2) 693 conf |= CG6_FHC_DST_DISABLE; 694 sbus_writel(conf, par->fhc); 695 } 696 697 /* Set things in the FBC. Bad things appear to happen if we do 698 * back to back store/loads on the mode register, so copy it 699 * out instead. */ 700 mode = sbus_readl(&fbc->mode); 701 do { 702 i = sbus_readl(&fbc->s); 703 } while (i & 0x10000000); 704 mode &= ~(CG6_FBC_BLIT_MASK | CG6_FBC_MODE_MASK | 705 CG6_FBC_DRAW_MASK | CG6_FBC_BWRITE0_MASK | 706 CG6_FBC_BWRITE1_MASK | CG6_FBC_BREAD_MASK | 707 CG6_FBC_BDISP_MASK); 708 mode |= (CG6_FBC_BLIT_SRC | CG6_FBC_MODE_COLOR8 | 709 CG6_FBC_DRAW_RENDER | CG6_FBC_BWRITE0_ENABLE | 710 CG6_FBC_BWRITE1_DISABLE | CG6_FBC_BREAD_0 | 711 CG6_FBC_BDISP_0); 712 sbus_writel(mode, &fbc->mode); 713 714 sbus_writel(0, &fbc->clip); 715 sbus_writel(0, &fbc->offx); 716 sbus_writel(0, &fbc->offy); 717 sbus_writel(0, &fbc->clipminx); 718 sbus_writel(0, &fbc->clipminy); 719 sbus_writel(info->var.xres - 1, &fbc->clipmaxx); 720 sbus_writel(info->var.yres - 1, &fbc->clipmaxy); 721 } 722 723 static void cg6_unmap_regs(struct platform_device *op, struct fb_info *info, 724 struct cg6_par *par) 725 { 726 if (par->fbc) 727 of_iounmap(&op->resource[0], par->fbc, 4096); 728 if (par->tec) 729 of_iounmap(&op->resource[0], par->tec, sizeof(struct cg6_tec)); 730 if (par->thc) 731 of_iounmap(&op->resource[0], par->thc, sizeof(struct cg6_thc)); 732 if (par->bt) 733 of_iounmap(&op->resource[0], par->bt, sizeof(struct bt_regs)); 734 if (par->fhc) 735 of_iounmap(&op->resource[0], par->fhc, sizeof(u32)); 736 737 if (info->screen_base) 738 of_iounmap(&op->resource[0], info->screen_base, 739 info->fix.smem_len); 740 } 741 742 static int cg6_probe(struct platform_device *op) 743 { 744 struct device_node *dp = op->dev.of_node; 745 struct fb_info *info; 746 struct cg6_par *par; 747 int linebytes, err; 748 int dblbuf; 749 750 info = framebuffer_alloc(sizeof(struct cg6_par), &op->dev); 751 752 err = -ENOMEM; 753 if (!info) 754 goto out_err; 755 par = info->par; 756 757 spin_lock_init(&par->lock); 758 759 info->fix.smem_start = op->resource[0].start; 760 par->which_io = op->resource[0].flags & IORESOURCE_BITS; 761 762 sbusfb_fill_var(&info->var, dp, 8); 763 info->var.red.length = 8; 764 info->var.green.length = 8; 765 info->var.blue.length = 8; 766 767 linebytes = of_getintprop_default(dp, "linebytes", 768 info->var.xres); 769 info->fix.smem_len = PAGE_ALIGN(linebytes * info->var.yres); 770 771 dblbuf = of_getintprop_default(dp, "dblbuf", 0); 772 if (dblbuf) 773 info->fix.smem_len *= 4; 774 775 par->fbc = of_ioremap(&op->resource[0], CG6_FBC_OFFSET, 776 4096, "cgsix fbc"); 777 par->tec = of_ioremap(&op->resource[0], CG6_TEC_OFFSET, 778 sizeof(struct cg6_tec), "cgsix tec"); 779 par->thc = of_ioremap(&op->resource[0], CG6_THC_OFFSET, 780 sizeof(struct cg6_thc), "cgsix thc"); 781 par->bt = of_ioremap(&op->resource[0], CG6_BROOKTREE_OFFSET, 782 sizeof(struct bt_regs), "cgsix dac"); 783 par->fhc = of_ioremap(&op->resource[0], CG6_FHC_OFFSET, 784 sizeof(u32), "cgsix fhc"); 785 786 info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_IMAGEBLIT | 787 FBINFO_HWACCEL_COPYAREA | FBINFO_HWACCEL_FILLRECT | 788 FBINFO_READS_FAST; 789 info->fbops = &cg6_ops; 790 791 info->screen_base = of_ioremap(&op->resource[0], CG6_RAM_OFFSET, 792 info->fix.smem_len, "cgsix ram"); 793 if (!par->fbc || !par->tec || !par->thc || 794 !par->bt || !par->fhc || !info->screen_base) 795 goto out_unmap_regs; 796 797 info->var.accel_flags = FB_ACCELF_TEXT; 798 799 cg6_bt_init(par); 800 cg6_chip_init(info); 801 cg6_blank(FB_BLANK_UNBLANK, info); 802 803 if (fb_alloc_cmap(&info->cmap, 256, 0)) 804 goto out_unmap_regs; 805 806 fb_set_cmap(&info->cmap, info); 807 cg6_init_fix(info, linebytes); 808 809 err = register_framebuffer(info); 810 if (err < 0) 811 goto out_dealloc_cmap; 812 813 dev_set_drvdata(&op->dev, info); 814 815 printk(KERN_INFO "%pOF: CGsix [%s] at %lx:%lx\n", 816 dp, info->fix.id, 817 par->which_io, info->fix.smem_start); 818 819 return 0; 820 821 out_dealloc_cmap: 822 fb_dealloc_cmap(&info->cmap); 823 824 out_unmap_regs: 825 cg6_unmap_regs(op, info, par); 826 framebuffer_release(info); 827 828 out_err: 829 return err; 830 } 831 832 static void cg6_remove(struct platform_device *op) 833 { 834 struct fb_info *info = dev_get_drvdata(&op->dev); 835 struct cg6_par *par = info->par; 836 837 unregister_framebuffer(info); 838 fb_dealloc_cmap(&info->cmap); 839 840 cg6_unmap_regs(op, info, par); 841 842 framebuffer_release(info); 843 } 844 845 static const struct of_device_id cg6_match[] = { 846 { 847 .name = "cgsix", 848 }, 849 { 850 .name = "cgthree+", 851 }, 852 {}, 853 }; 854 MODULE_DEVICE_TABLE(of, cg6_match); 855 856 static struct platform_driver cg6_driver = { 857 .driver = { 858 .name = "cg6", 859 .of_match_table = cg6_match, 860 }, 861 .probe = cg6_probe, 862 .remove_new = cg6_remove, 863 }; 864 865 static int __init cg6_init(void) 866 { 867 if (fb_get_options("cg6fb", NULL)) 868 return -ENODEV; 869 870 return platform_driver_register(&cg6_driver); 871 } 872 873 static void __exit cg6_exit(void) 874 { 875 platform_driver_unregister(&cg6_driver); 876 } 877 878 module_init(cg6_init); 879 module_exit(cg6_exit); 880 881 MODULE_DESCRIPTION("framebuffer driver for CGsix chipsets"); 882 MODULE_AUTHOR("David S. Miller <davem@davemloft.net>"); 883 MODULE_VERSION("2.0"); 884 MODULE_LICENSE("GPL"); 885