xref: /openbmc/linux/drivers/video/fbdev/cg3.c (revision 3ddc8b84) 
1 // SPDX-License-Identifier: GPL-2.0-only
2 /* cg3.c: CGTHREE frame buffer driver
3  *
4  * Copyright (C) 2003, 2006 David S. Miller (davem@davemloft.net)
5  * Copyright (C) 1996,1998 Jakub Jelinek (jj@ultra.linux.cz)
6  * Copyright (C) 1996 Miguel de Icaza (miguel@nuclecu.unam.mx)
7  * Copyright (C) 1997 Eddie C. Dost (ecd@skynet.be)
8  *
9  * Driver layout based loosely on tgafb.c, see that file for credits.
10  */
11 
12 #include <linux/module.h>
13 #include <linux/kernel.h>
14 #include <linux/errno.h>
15 #include <linux/string.h>
16 #include <linux/delay.h>
17 #include <linux/init.h>
18 #include <linux/fb.h>
19 #include <linux/mm.h>
20 #include <linux/of.h>
21 #include <linux/platform_device.h>
22 
23 #include <asm/io.h>
24 #include <asm/fbio.h>
25 
26 #include "sbuslib.h"
27 
28 /*
29  * Local functions.
30  */
31 
32 static int cg3_setcolreg(unsigned, unsigned, unsigned, unsigned,
33 			 unsigned, struct fb_info *);
34 static int cg3_blank(int, struct fb_info *);
35 
36 static int cg3_mmap(struct fb_info *, struct vm_area_struct *);
37 static int cg3_ioctl(struct fb_info *, unsigned int, unsigned long);
38 
39 /*
40  *  Frame buffer operations
41  */
42 
43 static const struct fb_ops cg3_ops = {
44 	.owner			= THIS_MODULE,
45 	.fb_setcolreg		= cg3_setcolreg,
46 	.fb_blank		= cg3_blank,
47 	.fb_fillrect		= cfb_fillrect,
48 	.fb_copyarea		= cfb_copyarea,
49 	.fb_imageblit		= cfb_imageblit,
50 	.fb_mmap		= cg3_mmap,
51 	.fb_ioctl		= cg3_ioctl,
52 #ifdef CONFIG_COMPAT
53 	.fb_compat_ioctl	= sbusfb_compat_ioctl,
54 #endif
55 };
56 
57 
58 /* Control Register Constants */
59 #define CG3_CR_ENABLE_INTS      0x80
60 #define CG3_CR_ENABLE_VIDEO     0x40
61 #define CG3_CR_ENABLE_TIMING    0x20
62 #define CG3_CR_ENABLE_CURCMP    0x10
63 #define CG3_CR_XTAL_MASK        0x0c
64 #define CG3_CR_DIVISOR_MASK     0x03
65 
66 /* Status Register Constants */
67 #define CG3_SR_PENDING_INT      0x80
68 #define CG3_SR_RES_MASK         0x70
69 #define CG3_SR_1152_900_76_A    0x40
70 #define CG3_SR_1152_900_76_B    0x60
71 #define CG3_SR_ID_MASK          0x0f
72 #define CG3_SR_ID_COLOR         0x01
73 #define CG3_SR_ID_MONO          0x02
74 #define CG3_SR_ID_MONO_ECL      0x03
75 
76 enum cg3_type {
77 	CG3_AT_66HZ = 0,
78 	CG3_AT_76HZ,
79 	CG3_RDI
80 };
81 
82 struct bt_regs {
83 	u32 addr;
84 	u32 color_map;
85 	u32 control;
86 	u32 cursor;
87 };
88 
89 struct cg3_regs {
90 	struct bt_regs	cmap;
91 	u8	control;
92 	u8	status;
93 	u8	cursor_start;
94 	u8	cursor_end;
95 	u8	h_blank_start;
96 	u8	h_blank_end;
97 	u8	h_sync_start;
98 	u8	h_sync_end;
99 	u8	comp_sync_end;
100 	u8	v_blank_start_high;
101 	u8	v_blank_start_low;
102 	u8	v_blank_end;
103 	u8	v_sync_start;
104 	u8	v_sync_end;
105 	u8	xfer_holdoff_start;
106 	u8	xfer_holdoff_end;
107 };
108 
109 /* Offset of interesting structures in the OBIO space */
110 #define CG3_REGS_OFFSET	     0x400000UL
111 #define CG3_RAM_OFFSET	     0x800000UL
112 
113 struct cg3_par {
114 	spinlock_t		lock;
115 	struct cg3_regs		__iomem *regs;
116 	u32			sw_cmap[((256 * 3) + 3) / 4];
117 
118 	u32			flags;
119 #define CG3_FLAG_BLANKED	0x00000001
120 #define CG3_FLAG_RDI		0x00000002
121 
122 	unsigned long		which_io;
123 };
124 
125 /**
126  *      cg3_setcolreg - Optional function. Sets a color register.
127  *      @regno: boolean, 0 copy local, 1 get_user() function
128  *      @red: frame buffer colormap structure
129  *      @green: The green value which can be up to 16 bits wide
130  *      @blue:  The blue value which can be up to 16 bits wide.
131  *      @transp: If supported the alpha value which can be up to 16 bits wide.
132  *      @info: frame buffer info structure
133  *
134  * The cg3 palette is loaded with 4 color values at each time
135  * so you end up with: (rgb)(r), (gb)(rg), (b)(rgb), and so on.
136  * We keep a sw copy of the hw cmap to assist us in this esoteric
137  * loading procedure.
138  */
139 static int cg3_setcolreg(unsigned regno,
140 			 unsigned red, unsigned green, unsigned blue,
141 			 unsigned transp, struct fb_info *info)
142 {
143 	struct cg3_par *par = (struct cg3_par *) info->par;
144 	struct bt_regs __iomem *bt = &par->regs->cmap;
145 	unsigned long flags;
146 	u32 *p32;
147 	u8 *p8;
148 	int count;
149 
150 	if (regno >= 256)
151 		return 1;
152 
153 	red >>= 8;
154 	green >>= 8;
155 	blue >>= 8;
156 
157 	spin_lock_irqsave(&par->lock, flags);
158 
159 	p8 = (u8 *)par->sw_cmap + (regno * 3);
160 	p8[0] = red;
161 	p8[1] = green;
162 	p8[2] = blue;
163 
164 #define D4M3(x) ((((x)>>2)<<1) + ((x)>>2))      /* (x/4)*3 */
165 #define D4M4(x) ((x)&~0x3)                      /* (x/4)*4 */
166 
167 	count = 3;
168 	p32 = &par->sw_cmap[D4M3(regno)];
169 	sbus_writel(D4M4(regno), &bt->addr);
170 	while (count--)
171 		sbus_writel(*p32++, &bt->color_map);
172 
173 #undef D4M3
174 #undef D4M4
175 
176 	spin_unlock_irqrestore(&par->lock, flags);
177 
178 	return 0;
179 }
180 
181 /**
182  *      cg3_blank - Optional function.  Blanks the display.
183  *      @blank: the blank mode we want.
184  *      @info: frame buffer structure that represents a single frame buffer
185  */
186 static int cg3_blank(int blank, struct fb_info *info)
187 {
188 	struct cg3_par *par = (struct cg3_par *) info->par;
189 	struct cg3_regs __iomem *regs = par->regs;
190 	unsigned long flags;
191 	u8 val;
192 
193 	spin_lock_irqsave(&par->lock, flags);
194 
195 	switch (blank) {
196 	case FB_BLANK_UNBLANK: /* Unblanking */
197 		val = sbus_readb(&regs->control);
198 		val |= CG3_CR_ENABLE_VIDEO;
199 		sbus_writeb(val, &regs->control);
200 		par->flags &= ~CG3_FLAG_BLANKED;
201 		break;
202 
203 	case FB_BLANK_NORMAL: /* Normal blanking */
204 	case FB_BLANK_VSYNC_SUSPEND: /* VESA blank (vsync off) */
205 	case FB_BLANK_HSYNC_SUSPEND: /* VESA blank (hsync off) */
206 	case FB_BLANK_POWERDOWN: /* Poweroff */
207 		val = sbus_readb(&regs->control);
208 		val &= ~CG3_CR_ENABLE_VIDEO;
209 		sbus_writeb(val, &regs->control);
210 		par->flags |= CG3_FLAG_BLANKED;
211 		break;
212 	}
213 
214 	spin_unlock_irqrestore(&par->lock, flags);
215 
216 	return 0;
217 }
218 
219 static struct sbus_mmap_map cg3_mmap_map[] = {
220 	{
221 		.voff	= CG3_MMAP_OFFSET,
222 		.poff	= CG3_RAM_OFFSET,
223 		.size	= SBUS_MMAP_FBSIZE(1)
224 	},
225 	{ .size = 0 }
226 };
227 
228 static int cg3_mmap(struct fb_info *info, struct vm_area_struct *vma)
229 {
230 	struct cg3_par *par = (struct cg3_par *)info->par;
231 
232 	return sbusfb_mmap_helper(cg3_mmap_map,
233 				  info->fix.smem_start, info->fix.smem_len,
234 				  par->which_io,
235 				  vma);
236 }
237 
238 static int cg3_ioctl(struct fb_info *info, unsigned int cmd, unsigned long arg)
239 {
240 	return sbusfb_ioctl_helper(cmd, arg, info,
241 				   FBTYPE_SUN3COLOR, 8, info->fix.smem_len);
242 }
243 
244 /*
245  *  Initialisation
246  */
247 
248 static void cg3_init_fix(struct fb_info *info, int linebytes,
249 			 struct device_node *dp)
250 {
251 	snprintf(info->fix.id, sizeof(info->fix.id), "%pOFn", dp);
252 
253 	info->fix.type = FB_TYPE_PACKED_PIXELS;
254 	info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
255 
256 	info->fix.line_length = linebytes;
257 
258 	info->fix.accel = FB_ACCEL_SUN_CGTHREE;
259 }
260 
261 static void cg3_rdi_maybe_fixup_var(struct fb_var_screeninfo *var,
262 				    struct device_node *dp)
263 {
264 	const char *params;
265 	char *p;
266 	int ww, hh;
267 
268 	params = of_get_property(dp, "params", NULL);
269 	if (params) {
270 		ww = simple_strtoul(params, &p, 10);
271 		if (ww && *p == 'x') {
272 			hh = simple_strtoul(p + 1, &p, 10);
273 			if (hh && *p == '-') {
274 				if (var->xres != ww ||
275 				    var->yres != hh) {
276 					var->xres = var->xres_virtual = ww;
277 					var->yres = var->yres_virtual = hh;
278 				}
279 			}
280 		}
281 	}
282 }
283 
284 static u8 cg3regvals_66hz[] = {	/* 1152 x 900, 66 Hz */
285 	0x14, 0xbb,	0x15, 0x2b,	0x16, 0x04,	0x17, 0x14,
286 	0x18, 0xae,	0x19, 0x03,	0x1a, 0xa8,	0x1b, 0x24,
287 	0x1c, 0x01,	0x1d, 0x05,	0x1e, 0xff,	0x1f, 0x01,
288 	0x10, 0x20,	0
289 };
290 
291 static u8 cg3regvals_76hz[] = {	/* 1152 x 900, 76 Hz */
292 	0x14, 0xb7,	0x15, 0x27,	0x16, 0x03,	0x17, 0x0f,
293 	0x18, 0xae,	0x19, 0x03,	0x1a, 0xae,	0x1b, 0x2a,
294 	0x1c, 0x01,	0x1d, 0x09,	0x1e, 0xff,	0x1f, 0x01,
295 	0x10, 0x24,	0
296 };
297 
298 static u8 cg3regvals_rdi[] = {	/* 640 x 480, cgRDI */
299 	0x14, 0x70,	0x15, 0x20,	0x16, 0x08,	0x17, 0x10,
300 	0x18, 0x06,	0x19, 0x02,	0x1a, 0x31,	0x1b, 0x51,
301 	0x1c, 0x06,	0x1d, 0x0c,	0x1e, 0xff,	0x1f, 0x01,
302 	0x10, 0x22,	0
303 };
304 
305 static u8 *cg3_regvals[] = {
306 	cg3regvals_66hz, cg3regvals_76hz, cg3regvals_rdi
307 };
308 
309 static u_char cg3_dacvals[] = {
310 	4, 0xff,	5, 0x00,	6, 0x70,	7, 0x00,	0
311 };
312 
313 static int cg3_do_default_mode(struct cg3_par *par)
314 {
315 	enum cg3_type type;
316 	u8 *p;
317 
318 	if (par->flags & CG3_FLAG_RDI)
319 		type = CG3_RDI;
320 	else {
321 		u8 status = sbus_readb(&par->regs->status), mon;
322 		if ((status & CG3_SR_ID_MASK) == CG3_SR_ID_COLOR) {
323 			mon = status & CG3_SR_RES_MASK;
324 			if (mon == CG3_SR_1152_900_76_A ||
325 			    mon == CG3_SR_1152_900_76_B)
326 				type = CG3_AT_76HZ;
327 			else
328 				type = CG3_AT_66HZ;
329 		} else {
330 			printk(KERN_ERR "cgthree: can't handle SR %02x\n",
331 			       status);
332 			return -EINVAL;
333 		}
334 	}
335 
336 	for (p = cg3_regvals[type]; *p; p += 2) {
337 		u8 __iomem *regp = &((u8 __iomem *)par->regs)[p[0]];
338 		sbus_writeb(p[1], regp);
339 	}
340 	for (p = cg3_dacvals; *p; p += 2) {
341 		u8 __iomem *regp;
342 
343 		regp = (u8 __iomem *)&par->regs->cmap.addr;
344 		sbus_writeb(p[0], regp);
345 		regp = (u8 __iomem *)&par->regs->cmap.control;
346 		sbus_writeb(p[1], regp);
347 	}
348 	return 0;
349 }
350 
351 static int cg3_probe(struct platform_device *op)
352 {
353 	struct device_node *dp = op->dev.of_node;
354 	struct fb_info *info;
355 	struct cg3_par *par;
356 	int linebytes, err;
357 
358 	info = framebuffer_alloc(sizeof(struct cg3_par), &op->dev);
359 
360 	err = -ENOMEM;
361 	if (!info)
362 		goto out_err;
363 	par = info->par;
364 
365 	spin_lock_init(&par->lock);
366 
367 	info->fix.smem_start = op->resource[0].start;
368 	par->which_io = op->resource[0].flags & IORESOURCE_BITS;
369 
370 	sbusfb_fill_var(&info->var, dp, 8);
371 	info->var.red.length = 8;
372 	info->var.green.length = 8;
373 	info->var.blue.length = 8;
374 	if (of_node_name_eq(dp, "cgRDI"))
375 		par->flags |= CG3_FLAG_RDI;
376 	if (par->flags & CG3_FLAG_RDI)
377 		cg3_rdi_maybe_fixup_var(&info->var, dp);
378 
379 	linebytes = of_getintprop_default(dp, "linebytes",
380 					  info->var.xres);
381 	info->fix.smem_len = PAGE_ALIGN(linebytes * info->var.yres);
382 
383 	par->regs = of_ioremap(&op->resource[0], CG3_REGS_OFFSET,
384 			       sizeof(struct cg3_regs), "cg3 regs");
385 	if (!par->regs)
386 		goto out_release_fb;
387 
388 	info->fbops = &cg3_ops;
389 	info->screen_base = of_ioremap(&op->resource[0], CG3_RAM_OFFSET,
390 				       info->fix.smem_len, "cg3 ram");
391 	if (!info->screen_base)
392 		goto out_unmap_regs;
393 
394 	cg3_blank(FB_BLANK_UNBLANK, info);
395 
396 	if (!of_property_present(dp, "width")) {
397 		err = cg3_do_default_mode(par);
398 		if (err)
399 			goto out_unmap_screen;
400 	}
401 
402 	err = fb_alloc_cmap(&info->cmap, 256, 0);
403 	if (err)
404 		goto out_unmap_screen;
405 
406 	fb_set_cmap(&info->cmap, info);
407 
408 	cg3_init_fix(info, linebytes, dp);
409 
410 	err = register_framebuffer(info);
411 	if (err < 0)
412 		goto out_dealloc_cmap;
413 
414 	dev_set_drvdata(&op->dev, info);
415 
416 	printk(KERN_INFO "%pOF: cg3 at %lx:%lx\n",
417 	       dp, par->which_io, info->fix.smem_start);
418 
419 	return 0;
420 
421 out_dealloc_cmap:
422 	fb_dealloc_cmap(&info->cmap);
423 
424 out_unmap_screen:
425 	of_iounmap(&op->resource[0], info->screen_base, info->fix.smem_len);
426 
427 out_unmap_regs:
428 	of_iounmap(&op->resource[0], par->regs, sizeof(struct cg3_regs));
429 
430 out_release_fb:
431 	framebuffer_release(info);
432 
433 out_err:
434 	return err;
435 }
436 
437 static void cg3_remove(struct platform_device *op)
438 {
439 	struct fb_info *info = dev_get_drvdata(&op->dev);
440 	struct cg3_par *par = info->par;
441 
442 	unregister_framebuffer(info);
443 	fb_dealloc_cmap(&info->cmap);
444 
445 	of_iounmap(&op->resource[0], par->regs, sizeof(struct cg3_regs));
446 	of_iounmap(&op->resource[0], info->screen_base, info->fix.smem_len);
447 
448 	framebuffer_release(info);
449 }
450 
451 static const struct of_device_id cg3_match[] = {
452 	{
453 		.name = "cgthree",
454 	},
455 	{
456 		.name = "cgRDI",
457 	},
458 	{},
459 };
460 MODULE_DEVICE_TABLE(of, cg3_match);
461 
462 static struct platform_driver cg3_driver = {
463 	.driver = {
464 		.name = "cg3",
465 		.of_match_table = cg3_match,
466 	},
467 	.probe		= cg3_probe,
468 	.remove_new	= cg3_remove,
469 };
470 
471 static int __init cg3_init(void)
472 {
473 	if (fb_get_options("cg3fb", NULL))
474 		return -ENODEV;
475 
476 	return platform_driver_register(&cg3_driver);
477 }
478 
479 static void __exit cg3_exit(void)
480 {
481 	platform_driver_unregister(&cg3_driver);
482 }
483 
484 module_init(cg3_init);
485 module_exit(cg3_exit);
486 
487 MODULE_DESCRIPTION("framebuffer driver for CGthree chipsets");
488 MODULE_AUTHOR("David S. Miller <davem@davemloft.net>");
489 MODULE_VERSION("2.0");
490 MODULE_LICENSE("GPL");
491