1 // SPDX-License-Identifier: GPL-2.0-only 2 /* cg14.c: CGFOURTEEN frame buffer driver 3 * 4 * Copyright (C) 2003, 2006 David S. Miller (davem@davemloft.net) 5 * Copyright (C) 1996,1998 Jakub Jelinek (jj@ultra.linux.cz) 6 * Copyright (C) 1995 Miguel de Icaza (miguel@nuclecu.unam.mx) 7 * 8 * Driver layout based loosely on tgafb.c, see that file for credits. 9 */ 10 11 #include <linux/module.h> 12 #include <linux/kernel.h> 13 #include <linux/errno.h> 14 #include <linux/string.h> 15 #include <linux/delay.h> 16 #include <linux/init.h> 17 #include <linux/fb.h> 18 #include <linux/mm.h> 19 #include <linux/uaccess.h> 20 #include <linux/of.h> 21 #include <linux/platform_device.h> 22 23 #include <asm/io.h> 24 #include <asm/fbio.h> 25 26 #include "sbuslib.h" 27 28 /* 29 * Local functions. 30 */ 31 32 static int cg14_setcolreg(unsigned, unsigned, unsigned, unsigned, 33 unsigned, struct fb_info *); 34 35 static int cg14_mmap(struct fb_info *, struct vm_area_struct *); 36 static int cg14_ioctl(struct fb_info *, unsigned int, unsigned long); 37 static int cg14_pan_display(struct fb_var_screeninfo *, struct fb_info *); 38 39 /* 40 * Frame buffer operations 41 */ 42 43 static const struct fb_ops cg14_ops = { 44 .owner = THIS_MODULE, 45 .fb_setcolreg = cg14_setcolreg, 46 .fb_pan_display = cg14_pan_display, 47 .fb_fillrect = cfb_fillrect, 48 .fb_copyarea = cfb_copyarea, 49 .fb_imageblit = cfb_imageblit, 50 .fb_mmap = cg14_mmap, 51 .fb_ioctl = cg14_ioctl, 52 #ifdef CONFIG_COMPAT 53 .fb_compat_ioctl = sbusfb_compat_ioctl, 54 #endif 55 }; 56 57 #define CG14_MCR_INTENABLE_SHIFT 7 58 #define CG14_MCR_INTENABLE_MASK 0x80 59 #define CG14_MCR_VIDENABLE_SHIFT 6 60 #define CG14_MCR_VIDENABLE_MASK 0x40 61 #define CG14_MCR_PIXMODE_SHIFT 4 62 #define CG14_MCR_PIXMODE_MASK 0x30 63 #define CG14_MCR_TMR_SHIFT 2 64 #define CG14_MCR_TMR_MASK 0x0c 65 #define CG14_MCR_TMENABLE_SHIFT 1 66 #define CG14_MCR_TMENABLE_MASK 0x02 67 #define CG14_MCR_RESET_SHIFT 0 68 #define CG14_MCR_RESET_MASK 0x01 69 #define CG14_REV_REVISION_SHIFT 4 70 #define CG14_REV_REVISION_MASK 0xf0 71 #define CG14_REV_IMPL_SHIFT 0 72 #define CG14_REV_IMPL_MASK 0x0f 73 #define CG14_VBR_FRAMEBASE_SHIFT 12 74 #define CG14_VBR_FRAMEBASE_MASK 0x00fff000 75 #define CG14_VMCR1_SETUP_SHIFT 0 76 #define CG14_VMCR1_SETUP_MASK 0x000001ff 77 #define CG14_VMCR1_VCONFIG_SHIFT 9 78 #define CG14_VMCR1_VCONFIG_MASK 0x00000e00 79 #define CG14_VMCR2_REFRESH_SHIFT 0 80 #define CG14_VMCR2_REFRESH_MASK 0x00000001 81 #define CG14_VMCR2_TESTROWCNT_SHIFT 1 82 #define CG14_VMCR2_TESTROWCNT_MASK 0x00000002 83 #define CG14_VMCR2_FBCONFIG_SHIFT 2 84 #define CG14_VMCR2_FBCONFIG_MASK 0x0000000c 85 #define CG14_VCR_REFRESHREQ_SHIFT 0 86 #define CG14_VCR_REFRESHREQ_MASK 0x000003ff 87 #define CG14_VCR1_REFRESHENA_SHIFT 10 88 #define CG14_VCR1_REFRESHENA_MASK 0x00000400 89 #define CG14_VCA_CAD_SHIFT 0 90 #define CG14_VCA_CAD_MASK 0x000003ff 91 #define CG14_VCA_VERS_SHIFT 10 92 #define CG14_VCA_VERS_MASK 0x00000c00 93 #define CG14_VCA_RAMSPEED_SHIFT 12 94 #define CG14_VCA_RAMSPEED_MASK 0x00001000 95 #define CG14_VCA_8MB_SHIFT 13 96 #define CG14_VCA_8MB_MASK 0x00002000 97 98 #define CG14_MCR_PIXMODE_8 0 99 #define CG14_MCR_PIXMODE_16 2 100 #define CG14_MCR_PIXMODE_32 3 101 102 struct cg14_regs{ 103 u8 mcr; /* Master Control Reg */ 104 u8 ppr; /* Packed Pixel Reg */ 105 u8 tms[2]; /* Test Mode Status Regs */ 106 u8 msr; /* Master Status Reg */ 107 u8 fsr; /* Fault Status Reg */ 108 u8 rev; /* Revision & Impl */ 109 u8 ccr; /* Clock Control Reg */ 110 u32 tmr; /* Test Mode Read Back */ 111 u8 mod; /* Monitor Operation Data Reg */ 112 u8 acr; /* Aux Control */ 113 u8 xxx0[6]; 114 u16 hct; /* Hor Counter */ 115 u16 vct; /* Vert Counter */ 116 u16 hbs; /* Hor Blank Start */ 117 u16 hbc; /* Hor Blank Clear */ 118 u16 hss; /* Hor Sync Start */ 119 u16 hsc; /* Hor Sync Clear */ 120 u16 csc; /* Composite Sync Clear */ 121 u16 vbs; /* Vert Blank Start */ 122 u16 vbc; /* Vert Blank Clear */ 123 u16 vss; /* Vert Sync Start */ 124 u16 vsc; /* Vert Sync Clear */ 125 u16 xcs; 126 u16 xcc; 127 u16 fsa; /* Fault Status Address */ 128 u16 adr; /* Address Registers */ 129 u8 xxx1[0xce]; 130 u8 pcg[0x100]; /* Pixel Clock Generator */ 131 u32 vbr; /* Frame Base Row */ 132 u32 vmcr; /* VBC Master Control */ 133 u32 vcr; /* VBC refresh */ 134 u32 vca; /* VBC Config */ 135 }; 136 137 #define CG14_CCR_ENABLE 0x04 138 #define CG14_CCR_SELECT 0x02 /* HW/Full screen */ 139 140 struct cg14_cursor { 141 u32 cpl0[32]; /* Enable plane 0 */ 142 u32 cpl1[32]; /* Color selection plane */ 143 u8 ccr; /* Cursor Control Reg */ 144 u8 xxx0[3]; 145 u16 cursx; /* Cursor x,y position */ 146 u16 cursy; /* Cursor x,y position */ 147 u32 color0; 148 u32 color1; 149 u32 xxx1[0x1bc]; 150 u32 cpl0i[32]; /* Enable plane 0 autoinc */ 151 u32 cpl1i[32]; /* Color selection autoinc */ 152 }; 153 154 struct cg14_dac { 155 u8 addr; /* Address Register */ 156 u8 xxx0[255]; 157 u8 glut; /* Gamma table */ 158 u8 xxx1[255]; 159 u8 select; /* Register Select */ 160 u8 xxx2[255]; 161 u8 mode; /* Mode Register */ 162 }; 163 164 struct cg14_xlut{ 165 u8 x_xlut [256]; 166 u8 x_xlutd [256]; 167 u8 xxx0[0x600]; 168 u8 x_xlut_inc [256]; 169 u8 x_xlutd_inc [256]; 170 }; 171 172 /* Color look up table (clut) */ 173 /* Each one of these arrays hold the color lookup table (for 256 174 * colors) for each MDI page (I assume then there should be 4 MDI 175 * pages, I still wonder what they are. I have seen NeXTStep split 176 * the screen in four parts, while operating in 24 bits mode. Each 177 * integer holds 4 values: alpha value (transparency channel, thanks 178 * go to John Stone (johns@umr.edu) from OpenBSD), red, green and blue 179 * 180 * I currently use the clut instead of the Xlut 181 */ 182 struct cg14_clut { 183 u32 c_clut [256]; 184 u32 c_clutd [256]; /* i wonder what the 'd' is for */ 185 u32 c_clut_inc [256]; 186 u32 c_clutd_inc [256]; 187 }; 188 189 #define CG14_MMAP_ENTRIES 16 190 191 struct cg14_par { 192 spinlock_t lock; 193 struct cg14_regs __iomem *regs; 194 struct cg14_clut __iomem *clut; 195 struct cg14_cursor __iomem *cursor; 196 197 u32 flags; 198 #define CG14_FLAG_BLANKED 0x00000001 199 200 unsigned long iospace; 201 202 struct sbus_mmap_map mmap_map[CG14_MMAP_ENTRIES]; 203 204 int mode; 205 int ramsize; 206 }; 207 208 static void __cg14_reset(struct cg14_par *par) 209 { 210 struct cg14_regs __iomem *regs = par->regs; 211 u8 val; 212 213 val = sbus_readb(®s->mcr); 214 val &= ~(CG14_MCR_PIXMODE_MASK); 215 sbus_writeb(val, ®s->mcr); 216 } 217 218 static int cg14_pan_display(struct fb_var_screeninfo *var, struct fb_info *info) 219 { 220 struct cg14_par *par = (struct cg14_par *) info->par; 221 unsigned long flags; 222 223 /* We just use this to catch switches out of 224 * graphics mode. 225 */ 226 spin_lock_irqsave(&par->lock, flags); 227 __cg14_reset(par); 228 spin_unlock_irqrestore(&par->lock, flags); 229 230 if (var->xoffset || var->yoffset || var->vmode) 231 return -EINVAL; 232 return 0; 233 } 234 235 /** 236 * cg14_setcolreg - Optional function. Sets a color register. 237 * @regno: boolean, 0 copy local, 1 get_user() function 238 * @red: frame buffer colormap structure 239 * @green: The green value which can be up to 16 bits wide 240 * @blue: The blue value which can be up to 16 bits wide. 241 * @transp: If supported the alpha value which can be up to 16 bits wide. 242 * @info: frame buffer info structure 243 */ 244 static int cg14_setcolreg(unsigned regno, 245 unsigned red, unsigned green, unsigned blue, 246 unsigned transp, struct fb_info *info) 247 { 248 struct cg14_par *par = (struct cg14_par *) info->par; 249 struct cg14_clut __iomem *clut = par->clut; 250 unsigned long flags; 251 u32 val; 252 253 if (regno >= 256) 254 return 1; 255 256 red >>= 8; 257 green >>= 8; 258 blue >>= 8; 259 val = (red | (green << 8) | (blue << 16)); 260 261 spin_lock_irqsave(&par->lock, flags); 262 sbus_writel(val, &clut->c_clut[regno]); 263 spin_unlock_irqrestore(&par->lock, flags); 264 265 return 0; 266 } 267 268 static int cg14_mmap(struct fb_info *info, struct vm_area_struct *vma) 269 { 270 struct cg14_par *par = (struct cg14_par *) info->par; 271 272 return sbusfb_mmap_helper(par->mmap_map, 273 info->fix.smem_start, info->fix.smem_len, 274 par->iospace, vma); 275 } 276 277 static int cg14_ioctl(struct fb_info *info, unsigned int cmd, unsigned long arg) 278 { 279 struct cg14_par *par = (struct cg14_par *) info->par; 280 struct cg14_regs __iomem *regs = par->regs; 281 struct mdi_cfginfo kmdi, __user *mdii; 282 unsigned long flags; 283 int cur_mode, mode, ret = 0; 284 285 switch (cmd) { 286 case MDI_RESET: 287 spin_lock_irqsave(&par->lock, flags); 288 __cg14_reset(par); 289 spin_unlock_irqrestore(&par->lock, flags); 290 break; 291 292 case MDI_GET_CFGINFO: 293 memset(&kmdi, 0, sizeof(kmdi)); 294 295 spin_lock_irqsave(&par->lock, flags); 296 kmdi.mdi_type = FBTYPE_MDICOLOR; 297 kmdi.mdi_height = info->var.yres; 298 kmdi.mdi_width = info->var.xres; 299 kmdi.mdi_mode = par->mode; 300 kmdi.mdi_pixfreq = 72; /* FIXME */ 301 kmdi.mdi_size = par->ramsize; 302 spin_unlock_irqrestore(&par->lock, flags); 303 304 mdii = (struct mdi_cfginfo __user *) arg; 305 if (copy_to_user(mdii, &kmdi, sizeof(kmdi))) 306 ret = -EFAULT; 307 break; 308 309 case MDI_SET_PIXELMODE: 310 if (get_user(mode, (int __user *) arg)) { 311 ret = -EFAULT; 312 break; 313 } 314 315 spin_lock_irqsave(&par->lock, flags); 316 cur_mode = sbus_readb(®s->mcr); 317 cur_mode &= ~CG14_MCR_PIXMODE_MASK; 318 switch(mode) { 319 case MDI_32_PIX: 320 cur_mode |= (CG14_MCR_PIXMODE_32 << 321 CG14_MCR_PIXMODE_SHIFT); 322 break; 323 324 case MDI_16_PIX: 325 cur_mode |= (CG14_MCR_PIXMODE_16 << 326 CG14_MCR_PIXMODE_SHIFT); 327 break; 328 329 case MDI_8_PIX: 330 break; 331 332 default: 333 ret = -ENOSYS; 334 break; 335 } 336 if (!ret) { 337 sbus_writeb(cur_mode, ®s->mcr); 338 par->mode = mode; 339 } 340 spin_unlock_irqrestore(&par->lock, flags); 341 break; 342 343 default: 344 ret = sbusfb_ioctl_helper(cmd, arg, info, 345 FBTYPE_MDICOLOR, 8, 346 info->fix.smem_len); 347 break; 348 } 349 350 return ret; 351 } 352 353 /* 354 * Initialisation 355 */ 356 357 static void cg14_init_fix(struct fb_info *info, int linebytes, 358 struct device_node *dp) 359 { 360 snprintf(info->fix.id, sizeof(info->fix.id), "%pOFn", dp); 361 362 info->fix.type = FB_TYPE_PACKED_PIXELS; 363 info->fix.visual = FB_VISUAL_PSEUDOCOLOR; 364 365 info->fix.line_length = linebytes; 366 367 info->fix.accel = FB_ACCEL_SUN_CG14; 368 } 369 370 static struct sbus_mmap_map __cg14_mmap_map[CG14_MMAP_ENTRIES] = { 371 { 372 .voff = CG14_REGS, 373 .poff = 0x80000000, 374 .size = 0x1000 375 }, 376 { 377 .voff = CG14_XLUT, 378 .poff = 0x80003000, 379 .size = 0x1000 380 }, 381 { 382 .voff = CG14_CLUT1, 383 .poff = 0x80004000, 384 .size = 0x1000 385 }, 386 { 387 .voff = CG14_CLUT2, 388 .poff = 0x80005000, 389 .size = 0x1000 390 }, 391 { 392 .voff = CG14_CLUT3, 393 .poff = 0x80006000, 394 .size = 0x1000 395 }, 396 { 397 .voff = CG3_MMAP_OFFSET - 0x7000, 398 .poff = 0x80000000, 399 .size = 0x7000 400 }, 401 { 402 .voff = CG3_MMAP_OFFSET, 403 .poff = 0x00000000, 404 .size = SBUS_MMAP_FBSIZE(1) 405 }, 406 { 407 .voff = MDI_CURSOR_MAP, 408 .poff = 0x80001000, 409 .size = 0x1000 410 }, 411 { 412 .voff = MDI_CHUNKY_BGR_MAP, 413 .poff = 0x01000000, 414 .size = 0x400000 415 }, 416 { 417 .voff = MDI_PLANAR_X16_MAP, 418 .poff = 0x02000000, 419 .size = 0x200000 420 }, 421 { 422 .voff = MDI_PLANAR_C16_MAP, 423 .poff = 0x02800000, 424 .size = 0x200000 425 }, 426 { 427 .voff = MDI_PLANAR_X32_MAP, 428 .poff = 0x03000000, 429 .size = 0x100000 430 }, 431 { 432 .voff = MDI_PLANAR_B32_MAP, 433 .poff = 0x03400000, 434 .size = 0x100000 435 }, 436 { 437 .voff = MDI_PLANAR_G32_MAP, 438 .poff = 0x03800000, 439 .size = 0x100000 440 }, 441 { 442 .voff = MDI_PLANAR_R32_MAP, 443 .poff = 0x03c00000, 444 .size = 0x100000 445 }, 446 { .size = 0 } 447 }; 448 449 static void cg14_unmap_regs(struct platform_device *op, struct fb_info *info, 450 struct cg14_par *par) 451 { 452 if (par->regs) 453 of_iounmap(&op->resource[0], 454 par->regs, sizeof(struct cg14_regs)); 455 if (par->clut) 456 of_iounmap(&op->resource[0], 457 par->clut, sizeof(struct cg14_clut)); 458 if (par->cursor) 459 of_iounmap(&op->resource[0], 460 par->cursor, sizeof(struct cg14_cursor)); 461 if (info->screen_base) 462 of_iounmap(&op->resource[1], 463 info->screen_base, info->fix.smem_len); 464 } 465 466 static int cg14_probe(struct platform_device *op) 467 { 468 struct device_node *dp = op->dev.of_node; 469 struct fb_info *info; 470 struct cg14_par *par; 471 int is_8mb, linebytes, i, err; 472 473 info = framebuffer_alloc(sizeof(struct cg14_par), &op->dev); 474 475 err = -ENOMEM; 476 if (!info) 477 goto out_err; 478 par = info->par; 479 480 spin_lock_init(&par->lock); 481 482 sbusfb_fill_var(&info->var, dp, 8); 483 info->var.red.length = 8; 484 info->var.green.length = 8; 485 info->var.blue.length = 8; 486 487 linebytes = of_getintprop_default(dp, "linebytes", 488 info->var.xres); 489 info->fix.smem_len = PAGE_ALIGN(linebytes * info->var.yres); 490 491 if (of_node_name_eq(dp->parent, "sbus") || 492 of_node_name_eq(dp->parent, "sbi")) { 493 info->fix.smem_start = op->resource[0].start; 494 par->iospace = op->resource[0].flags & IORESOURCE_BITS; 495 } else { 496 info->fix.smem_start = op->resource[1].start; 497 par->iospace = op->resource[0].flags & IORESOURCE_BITS; 498 } 499 500 par->regs = of_ioremap(&op->resource[0], 0, 501 sizeof(struct cg14_regs), "cg14 regs"); 502 par->clut = of_ioremap(&op->resource[0], CG14_CLUT1, 503 sizeof(struct cg14_clut), "cg14 clut"); 504 par->cursor = of_ioremap(&op->resource[0], CG14_CURSORREGS, 505 sizeof(struct cg14_cursor), "cg14 cursor"); 506 507 info->screen_base = of_ioremap(&op->resource[1], 0, 508 info->fix.smem_len, "cg14 ram"); 509 510 if (!par->regs || !par->clut || !par->cursor || !info->screen_base) 511 goto out_unmap_regs; 512 513 is_8mb = (resource_size(&op->resource[1]) == (8 * 1024 * 1024)); 514 515 BUILD_BUG_ON(sizeof(par->mmap_map) != sizeof(__cg14_mmap_map)); 516 517 memcpy(&par->mmap_map, &__cg14_mmap_map, sizeof(par->mmap_map)); 518 519 for (i = 0; i < CG14_MMAP_ENTRIES; i++) { 520 struct sbus_mmap_map *map = &par->mmap_map[i]; 521 522 if (!map->size) 523 break; 524 if (map->poff & 0x80000000) 525 map->poff = (map->poff & 0x7fffffff) + 526 (op->resource[0].start - 527 op->resource[1].start); 528 if (is_8mb && 529 map->size >= 0x100000 && 530 map->size <= 0x400000) 531 map->size *= 2; 532 } 533 534 par->mode = MDI_8_PIX; 535 par->ramsize = (is_8mb ? 0x800000 : 0x400000); 536 537 info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN; 538 info->fbops = &cg14_ops; 539 540 __cg14_reset(par); 541 542 if (fb_alloc_cmap(&info->cmap, 256, 0)) 543 goto out_unmap_regs; 544 545 fb_set_cmap(&info->cmap, info); 546 547 cg14_init_fix(info, linebytes, dp); 548 549 err = register_framebuffer(info); 550 if (err < 0) 551 goto out_dealloc_cmap; 552 553 dev_set_drvdata(&op->dev, info); 554 555 printk(KERN_INFO "%pOF: cgfourteen at %lx:%lx, %dMB\n", 556 dp, 557 par->iospace, info->fix.smem_start, 558 par->ramsize >> 20); 559 560 return 0; 561 562 out_dealloc_cmap: 563 fb_dealloc_cmap(&info->cmap); 564 565 out_unmap_regs: 566 cg14_unmap_regs(op, info, par); 567 framebuffer_release(info); 568 569 out_err: 570 return err; 571 } 572 573 static void cg14_remove(struct platform_device *op) 574 { 575 struct fb_info *info = dev_get_drvdata(&op->dev); 576 struct cg14_par *par = info->par; 577 578 unregister_framebuffer(info); 579 fb_dealloc_cmap(&info->cmap); 580 581 cg14_unmap_regs(op, info, par); 582 583 framebuffer_release(info); 584 } 585 586 static const struct of_device_id cg14_match[] = { 587 { 588 .name = "cgfourteen", 589 }, 590 {}, 591 }; 592 MODULE_DEVICE_TABLE(of, cg14_match); 593 594 static struct platform_driver cg14_driver = { 595 .driver = { 596 .name = "cg14", 597 .of_match_table = cg14_match, 598 }, 599 .probe = cg14_probe, 600 .remove_new = cg14_remove, 601 }; 602 603 static int __init cg14_init(void) 604 { 605 if (fb_get_options("cg14fb", NULL)) 606 return -ENODEV; 607 608 return platform_driver_register(&cg14_driver); 609 } 610 611 static void __exit cg14_exit(void) 612 { 613 platform_driver_unregister(&cg14_driver); 614 } 615 616 module_init(cg14_init); 617 module_exit(cg14_exit); 618 619 MODULE_DESCRIPTION("framebuffer driver for CGfourteen chipsets"); 620 MODULE_AUTHOR("David S. Miller <davem@davemloft.net>"); 621 MODULE_VERSION("2.0"); 622 MODULE_LICENSE("GPL"); 623