1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  *	drivers/video/aty/radeon_pm.c
4  *
5  *	Copyright 2003,2004 Ben. Herrenschmidt <benh@kernel.crashing.org>
6  *	Copyright 2004 Paul Mackerras <paulus@samba.org>
7  *
8  *	This is the power management code for ATI radeon chipsets. It contains
9  *	some dynamic clock PM enable/disable code similar to what X.org does,
10  *	some D2-state (APM-style) sleep/wakeup code for use on some PowerMacs,
11  *	and the necessary bits to re-initialize from scratch a few chips found
12  *	on PowerMacs as well. The later could be extended to more platforms
13  *	provided the memory controller configuration code be made more generic,
14  *	and you can get the proper mode register commands for your RAMs.
15  *	Those things may be found in the BIOS image...
16  */
17 
18 #include "radeonfb.h"
19 
20 #include <linux/console.h>
21 #include <linux/agp_backend.h>
22 
23 #ifdef CONFIG_PPC_PMAC
24 #include <asm/machdep.h>
25 #include <asm/prom.h>
26 #include <asm/pmac_feature.h>
27 #endif
28 
29 #include "ati_ids.h"
30 
31 /*
32  * Workarounds for bugs in PC laptops:
33  * - enable D2 sleep in some IBM Thinkpads
34  * - special case for Samsung P35
35  *
36  * Whitelist by subsystem vendor/device because
37  * its the subsystem vendor's fault!
38  */
39 
40 #if defined(CONFIG_PM) && defined(CONFIG_X86)
41 static void radeon_reinitialize_M10(struct radeonfb_info *rinfo);
42 
43 struct radeon_device_id {
44         const char *ident;                     /* (arbitrary) Name */
45         const unsigned short subsystem_vendor; /* Subsystem Vendor ID */
46         const unsigned short subsystem_device; /* Subsystem Device ID */
47 	const enum radeon_pm_mode pm_mode_modifier; /* modify pm_mode */
48 	const reinit_function_ptr new_reinit_func;   /* changed reinit_func */
49 };
50 
51 #define BUGFIX(model, sv, sd, pm, fn) { \
52 	.ident = model, \
53 	.subsystem_vendor = sv, \
54 	.subsystem_device = sd, \
55 	.pm_mode_modifier = pm, \
56 	.new_reinit_func  = fn  \
57 }
58 
59 static struct radeon_device_id radeon_workaround_list[] = {
60 	BUGFIX("IBM Thinkpad R32",
61 	       PCI_VENDOR_ID_IBM, 0x1905,
62 	       radeon_pm_d2, NULL),
63 	BUGFIX("IBM Thinkpad R40",
64 	       PCI_VENDOR_ID_IBM, 0x0526,
65 	       radeon_pm_d2, NULL),
66 	BUGFIX("IBM Thinkpad R40",
67 	       PCI_VENDOR_ID_IBM, 0x0527,
68 	       radeon_pm_d2, NULL),
69 	BUGFIX("IBM Thinkpad R50/R51/T40/T41",
70 	       PCI_VENDOR_ID_IBM, 0x0531,
71 	       radeon_pm_d2, NULL),
72 	BUGFIX("IBM Thinkpad R51/T40/T41/T42",
73 	       PCI_VENDOR_ID_IBM, 0x0530,
74 	       radeon_pm_d2, NULL),
75 	BUGFIX("IBM Thinkpad T30",
76 	       PCI_VENDOR_ID_IBM, 0x0517,
77 	       radeon_pm_d2, NULL),
78 	BUGFIX("IBM Thinkpad T40p",
79 	       PCI_VENDOR_ID_IBM, 0x054d,
80 	       radeon_pm_d2, NULL),
81 	BUGFIX("IBM Thinkpad T42",
82 	       PCI_VENDOR_ID_IBM, 0x0550,
83 	       radeon_pm_d2, NULL),
84 	BUGFIX("IBM Thinkpad X31/X32",
85 	       PCI_VENDOR_ID_IBM, 0x052f,
86 	       radeon_pm_d2, NULL),
87 	BUGFIX("Samsung P35",
88 	       PCI_VENDOR_ID_SAMSUNG, 0xc00c,
89 	       radeon_pm_off, radeon_reinitialize_M10),
90 	BUGFIX("Acer Aspire 2010",
91 	       PCI_VENDOR_ID_AI, 0x0061,
92 	       radeon_pm_off, radeon_reinitialize_M10),
93 	BUGFIX("Acer Travelmate 290D/292LMi",
94 	       PCI_VENDOR_ID_AI, 0x005a,
95 	       radeon_pm_off, radeon_reinitialize_M10),
96 	{ .ident = NULL }
97 };
98 
99 static int radeon_apply_workarounds(struct radeonfb_info *rinfo)
100 {
101 	struct radeon_device_id *id;
102 
103 	for (id = radeon_workaround_list; id->ident != NULL; id++ )
104 		if ((id->subsystem_vendor == rinfo->pdev->subsystem_vendor ) &&
105 		    (id->subsystem_device == rinfo->pdev->subsystem_device )) {
106 
107 			/* we found a device that requires workaround */
108 			printk(KERN_DEBUG "radeonfb: %s detected"
109 			       ", enabling workaround\n", id->ident);
110 
111 			rinfo->pm_mode |= id->pm_mode_modifier;
112 
113 			if (id->new_reinit_func != NULL)
114 				rinfo->reinit_func = id->new_reinit_func;
115 
116 			return 1;
117 		}
118 	return 0;  /* not found */
119 }
120 
121 #else  /* defined(CONFIG_PM) && defined(CONFIG_X86) */
122 static inline int radeon_apply_workarounds(struct radeonfb_info *rinfo)
123 {
124         return 0;
125 }
126 #endif /* defined(CONFIG_PM) && defined(CONFIG_X86) */
127 
128 
129 
130 static void radeon_pm_disable_dynamic_mode(struct radeonfb_info *rinfo)
131 {
132 	u32 tmp;
133 
134 	/* RV100 */
135 	if ((rinfo->family == CHIP_FAMILY_RV100) && (!rinfo->is_mobility)) {
136 		if (rinfo->has_CRTC2) {
137 			tmp = INPLL(pllSCLK_CNTL);
138 			tmp &= ~SCLK_CNTL__DYN_STOP_LAT_MASK;
139 			tmp |= SCLK_CNTL__CP_MAX_DYN_STOP_LAT | SCLK_CNTL__FORCEON_MASK;
140 			OUTPLL(pllSCLK_CNTL, tmp);
141 		}
142 		tmp = INPLL(pllMCLK_CNTL);
143 		tmp |= (MCLK_CNTL__FORCE_MCLKA |
144 		        MCLK_CNTL__FORCE_MCLKB |
145 		        MCLK_CNTL__FORCE_YCLKA |
146 		        MCLK_CNTL__FORCE_YCLKB |
147 			MCLK_CNTL__FORCE_AIC |
148 			MCLK_CNTL__FORCE_MC);
149                 OUTPLL(pllMCLK_CNTL, tmp);
150 		return;
151 	}
152 	/* R100 */
153 	if (!rinfo->has_CRTC2) {
154                 tmp = INPLL(pllSCLK_CNTL);
155                 tmp |= (SCLK_CNTL__FORCE_CP	| SCLK_CNTL__FORCE_HDP	|
156 			SCLK_CNTL__FORCE_DISP1	| SCLK_CNTL__FORCE_TOP	|
157                         SCLK_CNTL__FORCE_E2	| SCLK_CNTL__FORCE_SE 	|
158 			SCLK_CNTL__FORCE_IDCT	| SCLK_CNTL__FORCE_VIP	|
159 			SCLK_CNTL__FORCE_RE	| SCLK_CNTL__FORCE_PB 	|
160 			SCLK_CNTL__FORCE_TAM	| SCLK_CNTL__FORCE_TDM	|
161                         SCLK_CNTL__FORCE_RB);
162                 OUTPLL(pllSCLK_CNTL, tmp);
163 		return;
164 	}
165 	/* RV350 (M10/M11) */
166 	if (rinfo->family == CHIP_FAMILY_RV350) {
167                 /* for RV350/M10/M11, no delays are required. */
168                 tmp = INPLL(pllSCLK_CNTL2);
169                 tmp |= (SCLK_CNTL2__R300_FORCE_TCL |
170                         SCLK_CNTL2__R300_FORCE_GA  |
171 			SCLK_CNTL2__R300_FORCE_CBA);
172                 OUTPLL(pllSCLK_CNTL2, tmp);
173 
174                 tmp = INPLL(pllSCLK_CNTL);
175                 tmp |= (SCLK_CNTL__FORCE_DISP2		| SCLK_CNTL__FORCE_CP		|
176                         SCLK_CNTL__FORCE_HDP		| SCLK_CNTL__FORCE_DISP1	|
177                         SCLK_CNTL__FORCE_TOP		| SCLK_CNTL__FORCE_E2		|
178                         SCLK_CNTL__R300_FORCE_VAP	| SCLK_CNTL__FORCE_IDCT    	|
179 			SCLK_CNTL__FORCE_VIP		| SCLK_CNTL__R300_FORCE_SR	|
180 			SCLK_CNTL__R300_FORCE_PX	| SCLK_CNTL__R300_FORCE_TX	|
181 			SCLK_CNTL__R300_FORCE_US	| SCLK_CNTL__FORCE_TV_SCLK	|
182                         SCLK_CNTL__R300_FORCE_SU	| SCLK_CNTL__FORCE_OV0);
183                 OUTPLL(pllSCLK_CNTL, tmp);
184 
185                 tmp = INPLL(pllSCLK_MORE_CNTL);
186 		tmp |= (SCLK_MORE_CNTL__FORCE_DISPREGS	| SCLK_MORE_CNTL__FORCE_MC_GUI	|
187 			SCLK_MORE_CNTL__FORCE_MC_HOST);
188                 OUTPLL(pllSCLK_MORE_CNTL, tmp);
189 
190 		tmp = INPLL(pllMCLK_CNTL);
191 		tmp |= (MCLK_CNTL__FORCE_MCLKA |
192 		        MCLK_CNTL__FORCE_MCLKB |
193 		        MCLK_CNTL__FORCE_YCLKA |
194 		        MCLK_CNTL__FORCE_YCLKB |
195 			MCLK_CNTL__FORCE_MC);
196                 OUTPLL(pllMCLK_CNTL, tmp);
197 
198                 tmp = INPLL(pllVCLK_ECP_CNTL);
199                 tmp &= ~(VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb  |
200                          VCLK_ECP_CNTL__PIXCLK_DAC_ALWAYS_ONb |
201 			 VCLK_ECP_CNTL__R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF);
202                 OUTPLL(pllVCLK_ECP_CNTL, tmp);
203 
204                 tmp = INPLL(pllPIXCLKS_CNTL);
205                 tmp &= ~(PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb		|
206 			 PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb		|
207 			 PIXCLKS_CNTL__DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb	|
208 			 PIXCLKS_CNTL__R300_DVOCLK_ALWAYS_ONb		|
209 			 PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb		|
210 			 PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb		|
211 			 PIXCLKS_CNTL__R300_PIXCLK_DVO_ALWAYS_ONb	|
212 			 PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb		|
213 			 PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb		|
214 			 PIXCLKS_CNTL__R300_PIXCLK_TRANS_ALWAYS_ONb	|
215 			 PIXCLKS_CNTL__R300_PIXCLK_TVO_ALWAYS_ONb	|
216 			 PIXCLKS_CNTL__R300_P2G2CLK_ALWAYS_ONb		|
217 			 PIXCLKS_CNTL__R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF);
218                 OUTPLL(pllPIXCLKS_CNTL, tmp);
219 
220 		return;
221 	}
222 
223 	/* Default */
224 
225 	/* Force Core Clocks */
226 	tmp = INPLL(pllSCLK_CNTL);
227 	tmp |= (SCLK_CNTL__FORCE_CP | SCLK_CNTL__FORCE_E2);
228 
229 	/* XFree doesn't do that case, but we had this code from Apple and it
230 	 * seem necessary for proper suspend/resume operations
231 	 */
232 	if (rinfo->is_mobility) {
233 		tmp |= 	SCLK_CNTL__FORCE_HDP|
234 			SCLK_CNTL__FORCE_DISP1|
235 			SCLK_CNTL__FORCE_DISP2|
236 			SCLK_CNTL__FORCE_TOP|
237 			SCLK_CNTL__FORCE_SE|
238 			SCLK_CNTL__FORCE_IDCT|
239 			SCLK_CNTL__FORCE_VIP|
240 			SCLK_CNTL__FORCE_PB|
241 			SCLK_CNTL__FORCE_RE|
242 			SCLK_CNTL__FORCE_TAM|
243 			SCLK_CNTL__FORCE_TDM|
244 			SCLK_CNTL__FORCE_RB|
245 			SCLK_CNTL__FORCE_TV_SCLK|
246 			SCLK_CNTL__FORCE_SUBPIC|
247 			SCLK_CNTL__FORCE_OV0;
248 	}
249 	else if (rinfo->family == CHIP_FAMILY_R300 ||
250 		   rinfo->family == CHIP_FAMILY_R350) {
251 		tmp |=  SCLK_CNTL__FORCE_HDP   |
252 			SCLK_CNTL__FORCE_DISP1 |
253 			SCLK_CNTL__FORCE_DISP2 |
254 			SCLK_CNTL__FORCE_TOP   |
255 			SCLK_CNTL__FORCE_IDCT  |
256 			SCLK_CNTL__FORCE_VIP;
257 	}
258     	OUTPLL(pllSCLK_CNTL, tmp);
259 	radeon_msleep(16);
260 
261 	if (rinfo->family == CHIP_FAMILY_R300 || rinfo->family == CHIP_FAMILY_R350) {
262 		tmp = INPLL(pllSCLK_CNTL2);
263 		tmp |=  SCLK_CNTL2__R300_FORCE_TCL |
264 			SCLK_CNTL2__R300_FORCE_GA  |
265 			SCLK_CNTL2__R300_FORCE_CBA;
266 		OUTPLL(pllSCLK_CNTL2, tmp);
267 		radeon_msleep(16);
268 	}
269 
270 	tmp = INPLL(pllCLK_PIN_CNTL);
271 	tmp &= ~CLK_PIN_CNTL__SCLK_DYN_START_CNTL;
272 	OUTPLL(pllCLK_PIN_CNTL, tmp);
273 	radeon_msleep(15);
274 
275 	if (rinfo->is_IGP) {
276 		/* Weird  ... X is _un_ forcing clocks here, I think it's
277 		 * doing backward. Imitate it for now...
278 		 */
279 		tmp = INPLL(pllMCLK_CNTL);
280 		tmp &= ~(MCLK_CNTL__FORCE_MCLKA |
281 			 MCLK_CNTL__FORCE_YCLKA);
282 		OUTPLL(pllMCLK_CNTL, tmp);
283 		radeon_msleep(16);
284 	}
285 	/* Hrm... same shit, X doesn't do that but I have to */
286 	else if (rinfo->is_mobility) {
287 		tmp = INPLL(pllMCLK_CNTL);
288 		tmp |= (MCLK_CNTL__FORCE_MCLKA |
289 			MCLK_CNTL__FORCE_MCLKB |
290 			MCLK_CNTL__FORCE_YCLKA |
291 			MCLK_CNTL__FORCE_YCLKB);
292 		OUTPLL(pllMCLK_CNTL, tmp);
293 		radeon_msleep(16);
294 
295 		tmp = INPLL(pllMCLK_MISC);
296 		tmp &= 	~(MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT|
297 			  MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT|
298 			  MCLK_MISC__MC_MCLK_DYN_ENABLE|
299 			  MCLK_MISC__IO_MCLK_DYN_ENABLE);
300 		OUTPLL(pllMCLK_MISC, tmp);
301 		radeon_msleep(15);
302 	}
303 
304 	if (rinfo->is_mobility) {
305 		tmp = INPLL(pllSCLK_MORE_CNTL);
306 		tmp |= 	SCLK_MORE_CNTL__FORCE_DISPREGS|
307 			SCLK_MORE_CNTL__FORCE_MC_GUI|
308 			SCLK_MORE_CNTL__FORCE_MC_HOST;
309 		OUTPLL(pllSCLK_MORE_CNTL, tmp);
310 		radeon_msleep(16);
311 	}
312 
313 	tmp = INPLL(pllPIXCLKS_CNTL);
314 	tmp &= ~(PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb |
315 		 PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb|
316 		 PIXCLKS_CNTL__PIXCLK_DIG_TMDS_ALWAYS_ONb |
317 		 PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb|
318 		 PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb|
319 		 PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb|
320 		 PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb);
321  	OUTPLL(pllPIXCLKS_CNTL, tmp);
322 	radeon_msleep(16);
323 
324 	tmp = INPLL( pllVCLK_ECP_CNTL);
325 	tmp &= ~(VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb |
326 		 VCLK_ECP_CNTL__PIXCLK_DAC_ALWAYS_ONb);
327 	OUTPLL( pllVCLK_ECP_CNTL, tmp);
328 	radeon_msleep(16);
329 }
330 
331 static void radeon_pm_enable_dynamic_mode(struct radeonfb_info *rinfo)
332 {
333 	u32 tmp;
334 
335 	/* R100 */
336 	if (!rinfo->has_CRTC2) {
337                 tmp = INPLL(pllSCLK_CNTL);
338 
339 		if ((INREG(CNFG_CNTL) & CFG_ATI_REV_ID_MASK) > CFG_ATI_REV_A13)
340                     tmp &= ~(SCLK_CNTL__FORCE_CP	| SCLK_CNTL__FORCE_RB);
341                 tmp &= ~(SCLK_CNTL__FORCE_HDP		| SCLK_CNTL__FORCE_DISP1 |
342 			 SCLK_CNTL__FORCE_TOP		| SCLK_CNTL__FORCE_SE   |
343 			 SCLK_CNTL__FORCE_IDCT		| SCLK_CNTL__FORCE_RE   |
344 			 SCLK_CNTL__FORCE_PB		| SCLK_CNTL__FORCE_TAM  |
345 			 SCLK_CNTL__FORCE_TDM);
346                 OUTPLL(pllSCLK_CNTL, tmp);
347 		return;
348 	}
349 
350 	/* M10/M11 */
351 	if (rinfo->family == CHIP_FAMILY_RV350) {
352 		tmp = INPLL(pllSCLK_CNTL2);
353 		tmp &= ~(SCLK_CNTL2__R300_FORCE_TCL |
354 			 SCLK_CNTL2__R300_FORCE_GA  |
355 			 SCLK_CNTL2__R300_FORCE_CBA);
356 		tmp |=  (SCLK_CNTL2__R300_TCL_MAX_DYN_STOP_LAT |
357 			 SCLK_CNTL2__R300_GA_MAX_DYN_STOP_LAT  |
358 			 SCLK_CNTL2__R300_CBA_MAX_DYN_STOP_LAT);
359 		OUTPLL(pllSCLK_CNTL2, tmp);
360 
361 		tmp = INPLL(pllSCLK_CNTL);
362 		tmp &= ~(SCLK_CNTL__FORCE_DISP2 | SCLK_CNTL__FORCE_CP      |
363 			 SCLK_CNTL__FORCE_HDP   | SCLK_CNTL__FORCE_DISP1   |
364 			 SCLK_CNTL__FORCE_TOP   | SCLK_CNTL__FORCE_E2      |
365 			 SCLK_CNTL__R300_FORCE_VAP | SCLK_CNTL__FORCE_IDCT |
366 			 SCLK_CNTL__FORCE_VIP   | SCLK_CNTL__R300_FORCE_SR |
367 			 SCLK_CNTL__R300_FORCE_PX | SCLK_CNTL__R300_FORCE_TX |
368 			 SCLK_CNTL__R300_FORCE_US | SCLK_CNTL__FORCE_TV_SCLK |
369 			 SCLK_CNTL__R300_FORCE_SU | SCLK_CNTL__FORCE_OV0);
370 		tmp |= SCLK_CNTL__DYN_STOP_LAT_MASK;
371 		OUTPLL(pllSCLK_CNTL, tmp);
372 
373 		tmp = INPLL(pllSCLK_MORE_CNTL);
374 		tmp &= ~SCLK_MORE_CNTL__FORCEON;
375 		tmp |=  SCLK_MORE_CNTL__DISPREGS_MAX_DYN_STOP_LAT |
376 			SCLK_MORE_CNTL__MC_GUI_MAX_DYN_STOP_LAT |
377 			SCLK_MORE_CNTL__MC_HOST_MAX_DYN_STOP_LAT;
378 		OUTPLL(pllSCLK_MORE_CNTL, tmp);
379 
380 		tmp = INPLL(pllVCLK_ECP_CNTL);
381 		tmp |= (VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb |
382 			VCLK_ECP_CNTL__PIXCLK_DAC_ALWAYS_ONb);
383 		OUTPLL(pllVCLK_ECP_CNTL, tmp);
384 
385 		tmp = INPLL(pllPIXCLKS_CNTL);
386 		tmp |= (PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb         |
387 			PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb     |
388 			PIXCLKS_CNTL__DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb |
389 			PIXCLKS_CNTL__R300_DVOCLK_ALWAYS_ONb            |
390 			PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb    |
391 			PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb       |
392 			PIXCLKS_CNTL__R300_PIXCLK_DVO_ALWAYS_ONb        |
393 			PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb     |
394 			PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb     |
395 			PIXCLKS_CNTL__R300_PIXCLK_TRANS_ALWAYS_ONb      |
396 			PIXCLKS_CNTL__R300_PIXCLK_TVO_ALWAYS_ONb        |
397 			PIXCLKS_CNTL__R300_P2G2CLK_ALWAYS_ONb           |
398 			PIXCLKS_CNTL__R300_P2G2CLK_DAC_ALWAYS_ONb);
399 		OUTPLL(pllPIXCLKS_CNTL, tmp);
400 
401 		tmp = INPLL(pllMCLK_MISC);
402 		tmp |= (MCLK_MISC__MC_MCLK_DYN_ENABLE |
403 			MCLK_MISC__IO_MCLK_DYN_ENABLE);
404 		OUTPLL(pllMCLK_MISC, tmp);
405 
406 		tmp = INPLL(pllMCLK_CNTL);
407 		tmp |= (MCLK_CNTL__FORCE_MCLKA | MCLK_CNTL__FORCE_MCLKB);
408 		tmp &= ~(MCLK_CNTL__FORCE_YCLKA  |
409 			 MCLK_CNTL__FORCE_YCLKB  |
410 			 MCLK_CNTL__FORCE_MC);
411 
412 		/* Some releases of vbios have set DISABLE_MC_MCLKA
413 		 * and DISABLE_MC_MCLKB bits in the vbios table.  Setting these
414 		 * bits will cause H/W hang when reading video memory with dynamic
415 		 * clocking enabled.
416 		 */
417 		if ((tmp & MCLK_CNTL__R300_DISABLE_MC_MCLKA) &&
418 		    (tmp & MCLK_CNTL__R300_DISABLE_MC_MCLKB)) {
419 			/* If both bits are set, then check the active channels */
420 			tmp = INPLL(pllMCLK_CNTL);
421 			if (rinfo->vram_width == 64) {
422 			    if (INREG(MEM_CNTL) & R300_MEM_USE_CD_CH_ONLY)
423 				tmp &= ~MCLK_CNTL__R300_DISABLE_MC_MCLKB;
424 			    else
425 				tmp &= ~MCLK_CNTL__R300_DISABLE_MC_MCLKA;
426 			} else {
427 			    tmp &= ~(MCLK_CNTL__R300_DISABLE_MC_MCLKA |
428 				     MCLK_CNTL__R300_DISABLE_MC_MCLKB);
429 			}
430 		}
431 		OUTPLL(pllMCLK_CNTL, tmp);
432 		return;
433 	}
434 
435 	/* R300 */
436 	if (rinfo->family == CHIP_FAMILY_R300 || rinfo->family == CHIP_FAMILY_R350) {
437 		tmp = INPLL(pllSCLK_CNTL);
438 		tmp &= ~(SCLK_CNTL__R300_FORCE_VAP);
439 		tmp |= SCLK_CNTL__FORCE_CP;
440 		OUTPLL(pllSCLK_CNTL, tmp);
441 		radeon_msleep(15);
442 
443 		tmp = INPLL(pllSCLK_CNTL2);
444 		tmp &= ~(SCLK_CNTL2__R300_FORCE_TCL |
445 			 SCLK_CNTL2__R300_FORCE_GA  |
446 			 SCLK_CNTL2__R300_FORCE_CBA);
447 		OUTPLL(pllSCLK_CNTL2, tmp);
448 	}
449 
450 	/* Others */
451 
452 	tmp = INPLL( pllCLK_PWRMGT_CNTL);
453 	tmp &= ~(CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT_MASK|
454 		 CLK_PWRMGT_CNTL__DISP_DYN_STOP_LAT_MASK|
455 		 CLK_PWRMGT_CNTL__DYN_STOP_MODE_MASK);
456 	tmp |= CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE_MASK |
457 	       (0x01 << CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT__SHIFT);
458 	OUTPLL( pllCLK_PWRMGT_CNTL, tmp);
459 	radeon_msleep(15);
460 
461 	tmp = INPLL(pllCLK_PIN_CNTL);
462 	tmp |= CLK_PIN_CNTL__SCLK_DYN_START_CNTL;
463 	OUTPLL(pllCLK_PIN_CNTL, tmp);
464 	radeon_msleep(15);
465 
466 	/* When DRI is enabled, setting DYN_STOP_LAT to zero can cause some R200
467 	 * to lockup randomly, leave them as set by BIOS.
468 	 */
469 	tmp = INPLL(pllSCLK_CNTL);
470 	tmp &= ~SCLK_CNTL__FORCEON_MASK;
471 
472 	/*RAGE_6::A11 A12 A12N1 A13, RV250::A11 A12, R300*/
473 	if ((rinfo->family == CHIP_FAMILY_RV250 &&
474 	     ((INREG(CNFG_CNTL) & CFG_ATI_REV_ID_MASK) < CFG_ATI_REV_A13)) ||
475 	    ((rinfo->family == CHIP_FAMILY_RV100) &&
476 	     ((INREG(CNFG_CNTL) & CFG_ATI_REV_ID_MASK) <= CFG_ATI_REV_A13))) {
477 		tmp |= SCLK_CNTL__FORCE_CP;
478 		tmp |= SCLK_CNTL__FORCE_VIP;
479 	}
480 	OUTPLL(pllSCLK_CNTL, tmp);
481 	radeon_msleep(15);
482 
483 	if ((rinfo->family == CHIP_FAMILY_RV200) ||
484 	    (rinfo->family == CHIP_FAMILY_RV250) ||
485 	    (rinfo->family == CHIP_FAMILY_RV280)) {
486 		tmp = INPLL(pllSCLK_MORE_CNTL);
487 		tmp &= ~SCLK_MORE_CNTL__FORCEON;
488 
489 		/* RV200::A11 A12 RV250::A11 A12 */
490 		if (((rinfo->family == CHIP_FAMILY_RV200) ||
491 		     (rinfo->family == CHIP_FAMILY_RV250)) &&
492 		    ((INREG(CNFG_CNTL) & CFG_ATI_REV_ID_MASK) < CFG_ATI_REV_A13))
493 			tmp |= SCLK_MORE_CNTL__FORCEON;
494 
495 		OUTPLL(pllSCLK_MORE_CNTL, tmp);
496 		radeon_msleep(15);
497 	}
498 
499 
500 	/* RV200::A11 A12, RV250::A11 A12 */
501 	if (((rinfo->family == CHIP_FAMILY_RV200) ||
502 	     (rinfo->family == CHIP_FAMILY_RV250)) &&
503 	    ((INREG(CNFG_CNTL) & CFG_ATI_REV_ID_MASK) < CFG_ATI_REV_A13)) {
504 		tmp = INPLL(pllPLL_PWRMGT_CNTL);
505 		tmp |= PLL_PWRMGT_CNTL__TCL_BYPASS_DISABLE;
506 		OUTPLL(pllPLL_PWRMGT_CNTL, tmp);
507 		radeon_msleep(15);
508 	}
509 
510 	tmp = INPLL(pllPIXCLKS_CNTL);
511 	tmp |=  PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb |
512 		PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb|
513 		PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb|
514 		PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb|
515 		PIXCLKS_CNTL__PIXCLK_DIG_TMDS_ALWAYS_ONb|
516 		PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb|
517 		PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb;
518 	OUTPLL(pllPIXCLKS_CNTL, tmp);
519 	radeon_msleep(15);
520 
521 	tmp = INPLL(pllVCLK_ECP_CNTL);
522 	tmp |=  VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb |
523 		VCLK_ECP_CNTL__PIXCLK_DAC_ALWAYS_ONb;
524 	OUTPLL(pllVCLK_ECP_CNTL, tmp);
525 
526 	/* X doesn't do that ... hrm, we do on mobility && Macs */
527 #ifdef CONFIG_PPC
528 	if (rinfo->is_mobility) {
529 		tmp  = INPLL(pllMCLK_CNTL);
530 		tmp &= ~(MCLK_CNTL__FORCE_MCLKA |
531 			 MCLK_CNTL__FORCE_MCLKB |
532 			 MCLK_CNTL__FORCE_YCLKA |
533 			 MCLK_CNTL__FORCE_YCLKB);
534 		OUTPLL(pllMCLK_CNTL, tmp);
535 		radeon_msleep(15);
536 
537 		tmp = INPLL(pllMCLK_MISC);
538 		tmp |= 	MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT|
539 			MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT|
540 			MCLK_MISC__MC_MCLK_DYN_ENABLE|
541 			MCLK_MISC__IO_MCLK_DYN_ENABLE;
542 		OUTPLL(pllMCLK_MISC, tmp);
543 		radeon_msleep(15);
544 	}
545 #endif /* CONFIG_PPC */
546 }
547 
548 #ifdef CONFIG_PM
549 
550 static void OUTMC( struct radeonfb_info *rinfo, u8 indx, u32 value)
551 {
552 	OUTREG( MC_IND_INDEX, indx | MC_IND_INDEX__MC_IND_WR_EN);
553 	OUTREG( MC_IND_DATA, value);
554 }
555 
556 static u32 INMC(struct radeonfb_info *rinfo, u8 indx)
557 {
558 	OUTREG( MC_IND_INDEX, indx);
559 	return INREG( MC_IND_DATA);
560 }
561 
562 static void radeon_pm_save_regs(struct radeonfb_info *rinfo, int saving_for_d3)
563 {
564 	rinfo->save_regs[0] = INPLL(PLL_PWRMGT_CNTL);
565 	rinfo->save_regs[1] = INPLL(CLK_PWRMGT_CNTL);
566 	rinfo->save_regs[2] = INPLL(MCLK_CNTL);
567 	rinfo->save_regs[3] = INPLL(SCLK_CNTL);
568 	rinfo->save_regs[4] = INPLL(CLK_PIN_CNTL);
569 	rinfo->save_regs[5] = INPLL(VCLK_ECP_CNTL);
570 	rinfo->save_regs[6] = INPLL(PIXCLKS_CNTL);
571 	rinfo->save_regs[7] = INPLL(MCLK_MISC);
572 	rinfo->save_regs[8] = INPLL(P2PLL_CNTL);
573 
574 	rinfo->save_regs[9] = INREG(DISP_MISC_CNTL);
575 	rinfo->save_regs[10] = INREG(DISP_PWR_MAN);
576 	rinfo->save_regs[11] = INREG(LVDS_GEN_CNTL);
577 	rinfo->save_regs[13] = INREG(TV_DAC_CNTL);
578 	rinfo->save_regs[14] = INREG(BUS_CNTL1);
579 	rinfo->save_regs[15] = INREG(CRTC_OFFSET_CNTL);
580 	rinfo->save_regs[16] = INREG(AGP_CNTL);
581 	rinfo->save_regs[17] = (INREG(CRTC_GEN_CNTL) & 0xfdffffff) | 0x04000000;
582 	rinfo->save_regs[18] = (INREG(CRTC2_GEN_CNTL) & 0xfdffffff) | 0x04000000;
583 	rinfo->save_regs[19] = INREG(GPIOPAD_A);
584 	rinfo->save_regs[20] = INREG(GPIOPAD_EN);
585 	rinfo->save_regs[21] = INREG(GPIOPAD_MASK);
586 	rinfo->save_regs[22] = INREG(ZV_LCDPAD_A);
587 	rinfo->save_regs[23] = INREG(ZV_LCDPAD_EN);
588 	rinfo->save_regs[24] = INREG(ZV_LCDPAD_MASK);
589 	rinfo->save_regs[25] = INREG(GPIO_VGA_DDC);
590 	rinfo->save_regs[26] = INREG(GPIO_DVI_DDC);
591 	rinfo->save_regs[27] = INREG(GPIO_MONID);
592 	rinfo->save_regs[28] = INREG(GPIO_CRT2_DDC);
593 
594 	rinfo->save_regs[29] = INREG(SURFACE_CNTL);
595 	rinfo->save_regs[30] = INREG(MC_FB_LOCATION);
596 	rinfo->save_regs[31] = INREG(DISPLAY_BASE_ADDR);
597 	rinfo->save_regs[32] = INREG(MC_AGP_LOCATION);
598 	rinfo->save_regs[33] = INREG(CRTC2_DISPLAY_BASE_ADDR);
599 
600 	rinfo->save_regs[34] = INPLL(SCLK_MORE_CNTL);
601 	rinfo->save_regs[35] = INREG(MEM_SDRAM_MODE_REG);
602 	rinfo->save_regs[36] = INREG(BUS_CNTL);
603 	rinfo->save_regs[39] = INREG(RBBM_CNTL);
604 	rinfo->save_regs[40] = INREG(DAC_CNTL);
605 	rinfo->save_regs[41] = INREG(HOST_PATH_CNTL);
606 	rinfo->save_regs[37] = INREG(MPP_TB_CONFIG);
607 	rinfo->save_regs[38] = INREG(FCP_CNTL);
608 
609 	if (rinfo->is_mobility) {
610 		rinfo->save_regs[12] = INREG(LVDS_PLL_CNTL);
611 		rinfo->save_regs[43] = INPLL(pllSSPLL_CNTL);
612 		rinfo->save_regs[44] = INPLL(pllSSPLL_REF_DIV);
613 		rinfo->save_regs[45] = INPLL(pllSSPLL_DIV_0);
614 		rinfo->save_regs[90] = INPLL(pllSS_INT_CNTL);
615 		rinfo->save_regs[91] = INPLL(pllSS_TST_CNTL);
616 		rinfo->save_regs[81] = INREG(LVDS_GEN_CNTL);
617 	}
618 
619 	if (rinfo->family >= CHIP_FAMILY_RV200) {
620 		rinfo->save_regs[42] = INREG(MEM_REFRESH_CNTL);
621 		rinfo->save_regs[46] = INREG(MC_CNTL);
622 		rinfo->save_regs[47] = INREG(MC_INIT_GFX_LAT_TIMER);
623 		rinfo->save_regs[48] = INREG(MC_INIT_MISC_LAT_TIMER);
624 		rinfo->save_regs[49] = INREG(MC_TIMING_CNTL);
625 		rinfo->save_regs[50] = INREG(MC_READ_CNTL_AB);
626 		rinfo->save_regs[51] = INREG(MC_IOPAD_CNTL);
627 		rinfo->save_regs[52] = INREG(MC_CHIP_IO_OE_CNTL_AB);
628 		rinfo->save_regs[53] = INREG(MC_DEBUG);
629 	}
630 	rinfo->save_regs[54] = INREG(PAMAC0_DLY_CNTL);
631 	rinfo->save_regs[55] = INREG(PAMAC1_DLY_CNTL);
632 	rinfo->save_regs[56] = INREG(PAD_CTLR_MISC);
633 	rinfo->save_regs[57] = INREG(FW_CNTL);
634 
635 	if (rinfo->family >= CHIP_FAMILY_R300) {
636 		rinfo->save_regs[58] = INMC(rinfo, ixR300_MC_MC_INIT_WR_LAT_TIMER);
637 		rinfo->save_regs[59] = INMC(rinfo, ixR300_MC_IMP_CNTL);
638 		rinfo->save_regs[60] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_C0);
639 		rinfo->save_regs[61] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_C1);
640 		rinfo->save_regs[62] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_D0);
641 		rinfo->save_regs[63] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_D1);
642 		rinfo->save_regs[64] = INMC(rinfo, ixR300_MC_BIST_CNTL_3);
643 		rinfo->save_regs[65] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_A0);
644 		rinfo->save_regs[66] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_A1);
645 		rinfo->save_regs[67] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_B0);
646 		rinfo->save_regs[68] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_B1);
647 		rinfo->save_regs[69] = INMC(rinfo, ixR300_MC_DEBUG_CNTL);
648 		rinfo->save_regs[70] = INMC(rinfo, ixR300_MC_DLL_CNTL);
649 		rinfo->save_regs[71] = INMC(rinfo, ixR300_MC_IMP_CNTL_0);
650 		rinfo->save_regs[72] = INMC(rinfo, ixR300_MC_ELPIDA_CNTL);
651 		rinfo->save_regs[96] = INMC(rinfo, ixR300_MC_READ_CNTL_CD);
652 	} else {
653 		rinfo->save_regs[59] = INMC(rinfo, ixMC_IMP_CNTL);
654 		rinfo->save_regs[65] = INMC(rinfo, ixMC_CHP_IO_CNTL_A0);
655 		rinfo->save_regs[66] = INMC(rinfo, ixMC_CHP_IO_CNTL_A1);
656 		rinfo->save_regs[67] = INMC(rinfo, ixMC_CHP_IO_CNTL_B0);
657 		rinfo->save_regs[68] = INMC(rinfo, ixMC_CHP_IO_CNTL_B1);
658 		rinfo->save_regs[71] = INMC(rinfo, ixMC_IMP_CNTL_0);
659 	}
660 
661 	rinfo->save_regs[73] = INPLL(pllMPLL_CNTL);
662 	rinfo->save_regs[74] = INPLL(pllSPLL_CNTL);
663 	rinfo->save_regs[75] = INPLL(pllMPLL_AUX_CNTL);
664 	rinfo->save_regs[76] = INPLL(pllSPLL_AUX_CNTL);
665 	rinfo->save_regs[77] = INPLL(pllM_SPLL_REF_FB_DIV);
666 	rinfo->save_regs[78] = INPLL(pllAGP_PLL_CNTL);
667 	rinfo->save_regs[79] = INREG(PAMAC2_DLY_CNTL);
668 
669 	rinfo->save_regs[80] = INREG(OV0_BASE_ADDR);
670 	rinfo->save_regs[82] = INREG(FP_GEN_CNTL);
671 	rinfo->save_regs[83] = INREG(FP2_GEN_CNTL);
672 	rinfo->save_regs[84] = INREG(TMDS_CNTL);
673 	rinfo->save_regs[85] = INREG(TMDS_TRANSMITTER_CNTL);
674 	rinfo->save_regs[86] = INREG(DISP_OUTPUT_CNTL);
675 	rinfo->save_regs[87] = INREG(DISP_HW_DEBUG);
676 	rinfo->save_regs[88] = INREG(TV_MASTER_CNTL);
677 	rinfo->save_regs[89] = INPLL(pllP2PLL_REF_DIV);
678 	rinfo->save_regs[92] = INPLL(pllPPLL_DIV_0);
679 	rinfo->save_regs[93] = INPLL(pllPPLL_CNTL);
680 	rinfo->save_regs[94] = INREG(GRPH_BUFFER_CNTL);
681 	rinfo->save_regs[95] = INREG(GRPH2_BUFFER_CNTL);
682 	rinfo->save_regs[96] = INREG(HDP_DEBUG);
683 	rinfo->save_regs[97] = INPLL(pllMDLL_CKO);
684 	rinfo->save_regs[98] = INPLL(pllMDLL_RDCKA);
685 	rinfo->save_regs[99] = INPLL(pllMDLL_RDCKB);
686 }
687 
688 static void radeon_pm_restore_regs(struct radeonfb_info *rinfo)
689 {
690 	OUTPLL(P2PLL_CNTL, rinfo->save_regs[8] & 0xFFFFFFFE); /* First */
691 
692 	OUTPLL(PLL_PWRMGT_CNTL, rinfo->save_regs[0]);
693 	OUTPLL(CLK_PWRMGT_CNTL, rinfo->save_regs[1]);
694 	OUTPLL(MCLK_CNTL, rinfo->save_regs[2]);
695 	OUTPLL(SCLK_CNTL, rinfo->save_regs[3]);
696 	OUTPLL(CLK_PIN_CNTL, rinfo->save_regs[4]);
697 	OUTPLL(VCLK_ECP_CNTL, rinfo->save_regs[5]);
698 	OUTPLL(PIXCLKS_CNTL, rinfo->save_regs[6]);
699 	OUTPLL(MCLK_MISC, rinfo->save_regs[7]);
700 	if (rinfo->family == CHIP_FAMILY_RV350)
701 		OUTPLL(SCLK_MORE_CNTL, rinfo->save_regs[34]);
702 
703 	OUTREG(SURFACE_CNTL, rinfo->save_regs[29]);
704 	OUTREG(MC_FB_LOCATION, rinfo->save_regs[30]);
705 	OUTREG(DISPLAY_BASE_ADDR, rinfo->save_regs[31]);
706 	OUTREG(MC_AGP_LOCATION, rinfo->save_regs[32]);
707 	OUTREG(CRTC2_DISPLAY_BASE_ADDR, rinfo->save_regs[33]);
708 	OUTREG(CNFG_MEMSIZE, rinfo->video_ram);
709 
710 	OUTREG(DISP_MISC_CNTL, rinfo->save_regs[9]);
711 	OUTREG(DISP_PWR_MAN, rinfo->save_regs[10]);
712 	OUTREG(LVDS_GEN_CNTL, rinfo->save_regs[11]);
713 	OUTREG(LVDS_PLL_CNTL,rinfo->save_regs[12]);
714 	OUTREG(TV_DAC_CNTL, rinfo->save_regs[13]);
715 	OUTREG(BUS_CNTL1, rinfo->save_regs[14]);
716 	OUTREG(CRTC_OFFSET_CNTL, rinfo->save_regs[15]);
717 	OUTREG(AGP_CNTL, rinfo->save_regs[16]);
718 	OUTREG(CRTC_GEN_CNTL, rinfo->save_regs[17]);
719 	OUTREG(CRTC2_GEN_CNTL, rinfo->save_regs[18]);
720 	OUTPLL(P2PLL_CNTL, rinfo->save_regs[8]);
721 
722 	OUTREG(GPIOPAD_A, rinfo->save_regs[19]);
723 	OUTREG(GPIOPAD_EN, rinfo->save_regs[20]);
724 	OUTREG(GPIOPAD_MASK, rinfo->save_regs[21]);
725 	OUTREG(ZV_LCDPAD_A, rinfo->save_regs[22]);
726 	OUTREG(ZV_LCDPAD_EN, rinfo->save_regs[23]);
727 	OUTREG(ZV_LCDPAD_MASK, rinfo->save_regs[24]);
728 	OUTREG(GPIO_VGA_DDC, rinfo->save_regs[25]);
729 	OUTREG(GPIO_DVI_DDC, rinfo->save_regs[26]);
730 	OUTREG(GPIO_MONID, rinfo->save_regs[27]);
731 	OUTREG(GPIO_CRT2_DDC, rinfo->save_regs[28]);
732 }
733 
734 static void radeon_pm_disable_iopad(struct radeonfb_info *rinfo)
735 {
736 	OUTREG(GPIOPAD_MASK, 0x0001ffff);
737 	OUTREG(GPIOPAD_EN, 0x00000400);
738 	OUTREG(GPIOPAD_A, 0x00000000);
739         OUTREG(ZV_LCDPAD_MASK, 0x00000000);
740         OUTREG(ZV_LCDPAD_EN, 0x00000000);
741       	OUTREG(ZV_LCDPAD_A, 0x00000000);
742 	OUTREG(GPIO_VGA_DDC, 0x00030000);
743 	OUTREG(GPIO_DVI_DDC, 0x00000000);
744 	OUTREG(GPIO_MONID, 0x00030000);
745 	OUTREG(GPIO_CRT2_DDC, 0x00000000);
746 }
747 
748 static void radeon_pm_program_v2clk(struct radeonfb_info *rinfo)
749 {
750 	/* Set v2clk to 65MHz */
751 	if (rinfo->family <= CHIP_FAMILY_RV280) {
752 		OUTPLL(pllPIXCLKS_CNTL,
753 			 __INPLL(rinfo, pllPIXCLKS_CNTL)
754 			 & ~PIXCLKS_CNTL__PIX2CLK_SRC_SEL_MASK);
755 
756 		OUTPLL(pllP2PLL_REF_DIV, 0x0000000c);
757 		OUTPLL(pllP2PLL_CNTL, 0x0000bf00);
758 	} else {
759 		OUTPLL(pllP2PLL_REF_DIV, 0x0000000c);
760 		INPLL(pllP2PLL_REF_DIV);
761 		OUTPLL(pllP2PLL_CNTL, 0x0000a700);
762 	}
763 
764 	OUTPLL(pllP2PLL_DIV_0, 0x00020074 | P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_W);
765 
766 	OUTPLL(pllP2PLL_CNTL, INPLL(pllP2PLL_CNTL) & ~P2PLL_CNTL__P2PLL_SLEEP);
767 	mdelay(1);
768 
769 	OUTPLL(pllP2PLL_CNTL, INPLL(pllP2PLL_CNTL) & ~P2PLL_CNTL__P2PLL_RESET);
770 	mdelay( 1);
771 
772   	OUTPLL(pllPIXCLKS_CNTL,
773   		(INPLL(pllPIXCLKS_CNTL) & ~PIXCLKS_CNTL__PIX2CLK_SRC_SEL_MASK)
774   		| (0x03 << PIXCLKS_CNTL__PIX2CLK_SRC_SEL__SHIFT));
775 	mdelay( 1);
776 }
777 
778 static void radeon_pm_low_current(struct radeonfb_info *rinfo)
779 {
780 	u32 reg;
781 
782 	reg  = INREG(BUS_CNTL1);
783 	if (rinfo->family <= CHIP_FAMILY_RV280) {
784 		reg &= ~BUS_CNTL1_MOBILE_PLATFORM_SEL_MASK;
785 		reg |= BUS_CNTL1_AGPCLK_VALID | (1<<BUS_CNTL1_MOBILE_PLATFORM_SEL_SHIFT);
786 	} else {
787 		reg |= 0x4080;
788 	}
789 	OUTREG(BUS_CNTL1, reg);
790 
791 	reg  = INPLL(PLL_PWRMGT_CNTL);
792 	reg |= PLL_PWRMGT_CNTL_SPLL_TURNOFF | PLL_PWRMGT_CNTL_PPLL_TURNOFF |
793 		PLL_PWRMGT_CNTL_P2PLL_TURNOFF | PLL_PWRMGT_CNTL_TVPLL_TURNOFF;
794 	reg &= ~PLL_PWRMGT_CNTL_SU_MCLK_USE_BCLK;
795 	reg &= ~PLL_PWRMGT_CNTL_MOBILE_SU;
796 	OUTPLL(PLL_PWRMGT_CNTL, reg);
797 
798 	reg  = INREG(TV_DAC_CNTL);
799 	reg &= ~(TV_DAC_CNTL_BGADJ_MASK |TV_DAC_CNTL_DACADJ_MASK);
800 	reg |=TV_DAC_CNTL_BGSLEEP | TV_DAC_CNTL_RDACPD | TV_DAC_CNTL_GDACPD |
801 		TV_DAC_CNTL_BDACPD |
802 		(8<<TV_DAC_CNTL_BGADJ__SHIFT) | (8<<TV_DAC_CNTL_DACADJ__SHIFT);
803 	OUTREG(TV_DAC_CNTL, reg);
804 
805 	reg  = INREG(TMDS_TRANSMITTER_CNTL);
806 	reg &= ~(TMDS_PLL_EN | TMDS_PLLRST);
807 	OUTREG(TMDS_TRANSMITTER_CNTL, reg);
808 
809 	reg = INREG(DAC_CNTL);
810 	reg &= ~DAC_CMP_EN;
811 	OUTREG(DAC_CNTL, reg);
812 
813 	reg = INREG(DAC_CNTL2);
814 	reg &= ~DAC2_CMP_EN;
815 	OUTREG(DAC_CNTL2, reg);
816 
817 	reg  = INREG(TV_DAC_CNTL);
818 	reg &= ~TV_DAC_CNTL_DETECT;
819 	OUTREG(TV_DAC_CNTL, reg);
820 }
821 
822 static void radeon_pm_setup_for_suspend(struct radeonfb_info *rinfo)
823 {
824 
825 	u32 sclk_cntl, mclk_cntl, sclk_more_cntl;
826 
827 	u32 pll_pwrmgt_cntl;
828 	u32 clk_pwrmgt_cntl;
829 	u32 clk_pin_cntl;
830 	u32 vclk_ecp_cntl;
831 	u32 pixclks_cntl;
832 	u32 disp_mis_cntl;
833 	u32 disp_pwr_man;
834 	u32 tmp;
835 
836 	/* Force Core Clocks */
837 	sclk_cntl = INPLL( pllSCLK_CNTL);
838 	sclk_cntl |= 	SCLK_CNTL__IDCT_MAX_DYN_STOP_LAT|
839 			SCLK_CNTL__VIP_MAX_DYN_STOP_LAT|
840 			SCLK_CNTL__RE_MAX_DYN_STOP_LAT|
841 			SCLK_CNTL__PB_MAX_DYN_STOP_LAT|
842 			SCLK_CNTL__TAM_MAX_DYN_STOP_LAT|
843 			SCLK_CNTL__TDM_MAX_DYN_STOP_LAT|
844 			SCLK_CNTL__RB_MAX_DYN_STOP_LAT|
845 
846 			SCLK_CNTL__FORCE_DISP2|
847 			SCLK_CNTL__FORCE_CP|
848 			SCLK_CNTL__FORCE_HDP|
849 			SCLK_CNTL__FORCE_DISP1|
850 			SCLK_CNTL__FORCE_TOP|
851 			SCLK_CNTL__FORCE_E2|
852 			SCLK_CNTL__FORCE_SE|
853 			SCLK_CNTL__FORCE_IDCT|
854 			SCLK_CNTL__FORCE_VIP|
855 
856 			SCLK_CNTL__FORCE_PB|
857 			SCLK_CNTL__FORCE_TAM|
858 			SCLK_CNTL__FORCE_TDM|
859 			SCLK_CNTL__FORCE_RB|
860 			SCLK_CNTL__FORCE_TV_SCLK|
861 			SCLK_CNTL__FORCE_SUBPIC|
862 			SCLK_CNTL__FORCE_OV0;
863 	if (rinfo->family <= CHIP_FAMILY_RV280)
864 		sclk_cntl |= SCLK_CNTL__FORCE_RE;
865 	else
866 		sclk_cntl |= SCLK_CNTL__SE_MAX_DYN_STOP_LAT |
867 			SCLK_CNTL__E2_MAX_DYN_STOP_LAT |
868 			SCLK_CNTL__TV_MAX_DYN_STOP_LAT |
869 			SCLK_CNTL__HDP_MAX_DYN_STOP_LAT |
870 			SCLK_CNTL__CP_MAX_DYN_STOP_LAT;
871 
872 	OUTPLL( pllSCLK_CNTL, sclk_cntl);
873 
874 	sclk_more_cntl = INPLL(pllSCLK_MORE_CNTL);
875 	sclk_more_cntl |= 	SCLK_MORE_CNTL__FORCE_DISPREGS |
876 				SCLK_MORE_CNTL__FORCE_MC_GUI |
877 				SCLK_MORE_CNTL__FORCE_MC_HOST;
878 
879 	OUTPLL(pllSCLK_MORE_CNTL, sclk_more_cntl);
880 
881 
882 	mclk_cntl = INPLL( pllMCLK_CNTL);
883 	mclk_cntl &= ~(	MCLK_CNTL__FORCE_MCLKA |
884 			MCLK_CNTL__FORCE_MCLKB |
885 			MCLK_CNTL__FORCE_YCLKA |
886 			MCLK_CNTL__FORCE_YCLKB |
887 			MCLK_CNTL__FORCE_MC
888 		      );
889     	OUTPLL( pllMCLK_CNTL, mclk_cntl);
890 
891 	/* Force Display clocks	*/
892 	vclk_ecp_cntl = INPLL( pllVCLK_ECP_CNTL);
893 	vclk_ecp_cntl &= ~(VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb
894 			   | VCLK_ECP_CNTL__PIXCLK_DAC_ALWAYS_ONb);
895 	vclk_ecp_cntl |= VCLK_ECP_CNTL__ECP_FORCE_ON;
896 	OUTPLL( pllVCLK_ECP_CNTL, vclk_ecp_cntl);
897 
898 
899 	pixclks_cntl = INPLL( pllPIXCLKS_CNTL);
900 	pixclks_cntl &= ~(	PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb |
901 				PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb|
902 				PIXCLKS_CNTL__PIXCLK_DIG_TMDS_ALWAYS_ONb |
903 				PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb|
904 				PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb|
905 				PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb|
906 				PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb);
907 
908  	OUTPLL( pllPIXCLKS_CNTL, pixclks_cntl);
909 
910 	/* Switch off LVDS interface */
911 	OUTREG(LVDS_GEN_CNTL, INREG(LVDS_GEN_CNTL) &
912 	       ~(LVDS_BLON | LVDS_EN | LVDS_ON | LVDS_DIGON));
913 
914 	/* Enable System power management */
915 	pll_pwrmgt_cntl = INPLL( pllPLL_PWRMGT_CNTL);
916 
917 	pll_pwrmgt_cntl |= 	PLL_PWRMGT_CNTL__SPLL_TURNOFF |
918 				PLL_PWRMGT_CNTL__MPLL_TURNOFF|
919 				PLL_PWRMGT_CNTL__PPLL_TURNOFF|
920 				PLL_PWRMGT_CNTL__P2PLL_TURNOFF|
921 				PLL_PWRMGT_CNTL__TVPLL_TURNOFF;
922 
923 	OUTPLL( pllPLL_PWRMGT_CNTL, pll_pwrmgt_cntl);
924 
925 	clk_pwrmgt_cntl	 = INPLL( pllCLK_PWRMGT_CNTL);
926 
927 	clk_pwrmgt_cntl &= ~(	CLK_PWRMGT_CNTL__MPLL_PWRMGT_OFF|
928 				CLK_PWRMGT_CNTL__SPLL_PWRMGT_OFF|
929 				CLK_PWRMGT_CNTL__PPLL_PWRMGT_OFF|
930 				CLK_PWRMGT_CNTL__P2PLL_PWRMGT_OFF|
931 				CLK_PWRMGT_CNTL__MCLK_TURNOFF|
932 				CLK_PWRMGT_CNTL__SCLK_TURNOFF|
933 				CLK_PWRMGT_CNTL__PCLK_TURNOFF|
934 				CLK_PWRMGT_CNTL__P2CLK_TURNOFF|
935 				CLK_PWRMGT_CNTL__TVPLL_PWRMGT_OFF|
936 				CLK_PWRMGT_CNTL__GLOBAL_PMAN_EN|
937 				CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE|
938 				CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT_MASK|
939 				CLK_PWRMGT_CNTL__CG_NO1_DEBUG_MASK
940 			);
941 
942 	clk_pwrmgt_cntl |= CLK_PWRMGT_CNTL__GLOBAL_PMAN_EN
943 		| CLK_PWRMGT_CNTL__DISP_PM;
944 
945 	OUTPLL( pllCLK_PWRMGT_CNTL, clk_pwrmgt_cntl);
946 
947 	clk_pin_cntl = INPLL( pllCLK_PIN_CNTL);
948 
949 	clk_pin_cntl &= ~CLK_PIN_CNTL__ACCESS_REGS_IN_SUSPEND;
950 
951 	/* because both INPLL and OUTPLL take the same lock, that's why. */
952 	tmp = INPLL( pllMCLK_MISC) | MCLK_MISC__EN_MCLK_TRISTATE_IN_SUSPEND;
953 	OUTPLL( pllMCLK_MISC, tmp);
954 
955 	/* BUS_CNTL1__MOBILE_PLATORM_SEL setting is northbridge chipset
956 	 * and radeon chip dependent. Thus we only enable it on Mac for
957 	 * now (until we get more info on how to compute the correct
958 	 * value for various X86 bridges).
959 	 */
960 #ifdef CONFIG_PPC_PMAC
961 	if (machine_is(powermac)) {
962 		/* AGP PLL control */
963 		if (rinfo->family <= CHIP_FAMILY_RV280) {
964 			OUTREG(BUS_CNTL1, INREG(BUS_CNTL1) |  BUS_CNTL1__AGPCLK_VALID);
965 			OUTREG(BUS_CNTL1,
966 			       (INREG(BUS_CNTL1) & ~BUS_CNTL1__MOBILE_PLATFORM_SEL_MASK)
967 			       | (2<<BUS_CNTL1__MOBILE_PLATFORM_SEL__SHIFT));	// 440BX
968 		} else {
969 			OUTREG(BUS_CNTL1, INREG(BUS_CNTL1));
970 			OUTREG(BUS_CNTL1, (INREG(BUS_CNTL1) & ~0x4000) | 0x8000);
971 		}
972 	}
973 #endif
974 
975 	OUTREG(CRTC_OFFSET_CNTL, (INREG(CRTC_OFFSET_CNTL)
976 				  & ~CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_OUT_EN));
977 
978 	clk_pin_cntl &= ~CLK_PIN_CNTL__CG_CLK_TO_OUTPIN;
979 	clk_pin_cntl |= CLK_PIN_CNTL__XTALIN_ALWAYS_ONb;
980 	OUTPLL( pllCLK_PIN_CNTL, clk_pin_cntl);
981 
982 	/* Solano2M */
983 	OUTREG(AGP_CNTL,
984 		(INREG(AGP_CNTL) & ~(AGP_CNTL__MAX_IDLE_CLK_MASK))
985 		| (0x20<<AGP_CNTL__MAX_IDLE_CLK__SHIFT));
986 
987 	/* ACPI mode */
988 	/* because both INPLL and OUTPLL take the same lock, that's why. */
989 	tmp = INPLL( pllPLL_PWRMGT_CNTL) & ~PLL_PWRMGT_CNTL__PM_MODE_SEL;
990 	OUTPLL( pllPLL_PWRMGT_CNTL, tmp);
991 
992 
993 	disp_mis_cntl = INREG(DISP_MISC_CNTL);
994 
995 	disp_mis_cntl &= ~(	DISP_MISC_CNTL__SOFT_RESET_GRPH_PP |
996 				DISP_MISC_CNTL__SOFT_RESET_SUBPIC_PP |
997 				DISP_MISC_CNTL__SOFT_RESET_OV0_PP |
998 				DISP_MISC_CNTL__SOFT_RESET_GRPH_SCLK|
999 				DISP_MISC_CNTL__SOFT_RESET_SUBPIC_SCLK|
1000 				DISP_MISC_CNTL__SOFT_RESET_OV0_SCLK|
1001 				DISP_MISC_CNTL__SOFT_RESET_GRPH2_PP|
1002 				DISP_MISC_CNTL__SOFT_RESET_GRPH2_SCLK|
1003 				DISP_MISC_CNTL__SOFT_RESET_LVDS|
1004 				DISP_MISC_CNTL__SOFT_RESET_TMDS|
1005 				DISP_MISC_CNTL__SOFT_RESET_DIG_TMDS|
1006 				DISP_MISC_CNTL__SOFT_RESET_TV);
1007 
1008 	OUTREG(DISP_MISC_CNTL, disp_mis_cntl);
1009 
1010 	disp_pwr_man = INREG(DISP_PWR_MAN);
1011 
1012 	disp_pwr_man &= ~(	DISP_PWR_MAN__DISP_PWR_MAN_D3_CRTC_EN	|
1013 				DISP_PWR_MAN__DISP2_PWR_MAN_D3_CRTC2_EN |
1014 				DISP_PWR_MAN__DISP_PWR_MAN_DPMS_MASK|
1015 				DISP_PWR_MAN__DISP_D3_RST|
1016 				DISP_PWR_MAN__DISP_D3_REG_RST
1017 				);
1018 
1019 	disp_pwr_man |= DISP_PWR_MAN__DISP_D3_GRPH_RST|
1020 					DISP_PWR_MAN__DISP_D3_SUBPIC_RST|
1021 					DISP_PWR_MAN__DISP_D3_OV0_RST|
1022 					DISP_PWR_MAN__DISP_D1D2_GRPH_RST|
1023 					DISP_PWR_MAN__DISP_D1D2_SUBPIC_RST|
1024 					DISP_PWR_MAN__DISP_D1D2_OV0_RST|
1025 					DISP_PWR_MAN__DIG_TMDS_ENABLE_RST|
1026 					DISP_PWR_MAN__TV_ENABLE_RST|
1027 //					DISP_PWR_MAN__AUTO_PWRUP_EN|
1028 					0;
1029 
1030 	OUTREG(DISP_PWR_MAN, disp_pwr_man);
1031 
1032 	clk_pwrmgt_cntl = INPLL( pllCLK_PWRMGT_CNTL);
1033 	pll_pwrmgt_cntl = INPLL( pllPLL_PWRMGT_CNTL) ;
1034 	clk_pin_cntl 	= INPLL( pllCLK_PIN_CNTL);
1035 	disp_pwr_man	= INREG(DISP_PWR_MAN);
1036 
1037 
1038 	/* D2 */
1039 	clk_pwrmgt_cntl |= CLK_PWRMGT_CNTL__DISP_PM;
1040 	pll_pwrmgt_cntl |= PLL_PWRMGT_CNTL__MOBILE_SU | PLL_PWRMGT_CNTL__SU_SCLK_USE_BCLK;
1041 	clk_pin_cntl	|= CLK_PIN_CNTL__XTALIN_ALWAYS_ONb;
1042 	disp_pwr_man 	&= ~(DISP_PWR_MAN__DISP_PWR_MAN_D3_CRTC_EN_MASK
1043 			     | DISP_PWR_MAN__DISP2_PWR_MAN_D3_CRTC2_EN_MASK);
1044 
1045 	OUTPLL( pllCLK_PWRMGT_CNTL, clk_pwrmgt_cntl);
1046 	OUTPLL( pllPLL_PWRMGT_CNTL, pll_pwrmgt_cntl);
1047 	OUTPLL( pllCLK_PIN_CNTL, clk_pin_cntl);
1048 	OUTREG(DISP_PWR_MAN, disp_pwr_man);
1049 
1050 	/* disable display request & disable display */
1051 	OUTREG( CRTC_GEN_CNTL, (INREG( CRTC_GEN_CNTL) & ~CRTC_GEN_CNTL__CRTC_EN)
1052 		| CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B);
1053 	OUTREG( CRTC2_GEN_CNTL, (INREG( CRTC2_GEN_CNTL) & ~CRTC2_GEN_CNTL__CRTC2_EN)
1054 		| CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B);
1055 
1056 	mdelay(17);
1057 
1058 }
1059 
1060 static void radeon_pm_yclk_mclk_sync(struct radeonfb_info *rinfo)
1061 {
1062 	u32 mc_chp_io_cntl_a1, mc_chp_io_cntl_b1;
1063 
1064 	mc_chp_io_cntl_a1 = INMC( rinfo, ixMC_CHP_IO_CNTL_A1)
1065 		& ~MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA_MASK;
1066 	mc_chp_io_cntl_b1 = INMC( rinfo, ixMC_CHP_IO_CNTL_B1)
1067 		& ~MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB_MASK;
1068 
1069 	OUTMC( rinfo, ixMC_CHP_IO_CNTL_A1, mc_chp_io_cntl_a1
1070 	       | (1<<MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA__SHIFT));
1071 	OUTMC( rinfo, ixMC_CHP_IO_CNTL_B1, mc_chp_io_cntl_b1
1072 	       | (1<<MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB__SHIFT));
1073 
1074 	OUTMC( rinfo, ixMC_CHP_IO_CNTL_A1, mc_chp_io_cntl_a1);
1075 	OUTMC( rinfo, ixMC_CHP_IO_CNTL_B1, mc_chp_io_cntl_b1);
1076 
1077 	mdelay( 1);
1078 }
1079 
1080 static void radeon_pm_yclk_mclk_sync_m10(struct radeonfb_info *rinfo)
1081 {
1082 	u32 mc_chp_io_cntl_a1, mc_chp_io_cntl_b1;
1083 
1084 	mc_chp_io_cntl_a1 = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_A1)
1085 		& ~MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA_MASK;
1086 	mc_chp_io_cntl_b1 = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_B1)
1087 		& ~MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB_MASK;
1088 
1089 	OUTMC( rinfo, ixR300_MC_CHP_IO_CNTL_A1,
1090 	       mc_chp_io_cntl_a1 | (1<<MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA__SHIFT));
1091 	OUTMC( rinfo, ixR300_MC_CHP_IO_CNTL_B1,
1092 	       mc_chp_io_cntl_b1 | (1<<MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB__SHIFT));
1093 
1094 	OUTMC( rinfo, ixR300_MC_CHP_IO_CNTL_A1, mc_chp_io_cntl_a1);
1095 	OUTMC( rinfo, ixR300_MC_CHP_IO_CNTL_B1, mc_chp_io_cntl_b1);
1096 
1097 	mdelay( 1);
1098 }
1099 
1100 static void radeon_pm_program_mode_reg(struct radeonfb_info *rinfo, u16 value,
1101 				       u8 delay_required)
1102 {
1103 	u32 mem_sdram_mode;
1104 
1105 	mem_sdram_mode  = INREG( MEM_SDRAM_MODE_REG);
1106 
1107 	mem_sdram_mode &= ~MEM_SDRAM_MODE_REG__MEM_MODE_REG_MASK;
1108 	mem_sdram_mode |= (value<<MEM_SDRAM_MODE_REG__MEM_MODE_REG__SHIFT)
1109 		| MEM_SDRAM_MODE_REG__MEM_CFG_TYPE;
1110 	OUTREG( MEM_SDRAM_MODE_REG, mem_sdram_mode);
1111 	if (delay_required >= 2)
1112 		mdelay(1);
1113 
1114 	mem_sdram_mode |=  MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET;
1115 	OUTREG( MEM_SDRAM_MODE_REG, mem_sdram_mode);
1116 	if (delay_required >= 2)
1117 		mdelay(1);
1118 
1119 	mem_sdram_mode &= ~MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET;
1120 	OUTREG( MEM_SDRAM_MODE_REG, mem_sdram_mode);
1121 	if (delay_required >= 2)
1122 		mdelay(1);
1123 
1124 	if (delay_required) {
1125 		do {
1126 			if (delay_required >= 2)
1127 				mdelay(1);
1128 		} while ((INREG(MC_STATUS)
1129 			  & (MC_STATUS__MEM_PWRUP_COMPL_A |
1130 			     MC_STATUS__MEM_PWRUP_COMPL_B)) == 0);
1131 	}
1132 }
1133 
1134 static void radeon_pm_m10_program_mode_wait(struct radeonfb_info *rinfo)
1135 {
1136 	int cnt;
1137 
1138 	for (cnt = 0; cnt < 100; ++cnt) {
1139 		mdelay(1);
1140 		if (INREG(MC_STATUS) & (MC_STATUS__MEM_PWRUP_COMPL_A
1141 					| MC_STATUS__MEM_PWRUP_COMPL_B))
1142 			break;
1143 	}
1144 }
1145 
1146 
1147 static void radeon_pm_enable_dll(struct radeonfb_info *rinfo)
1148 {
1149 #define DLL_RESET_DELAY 	5
1150 #define DLL_SLEEP_DELAY		1
1151 
1152 	u32 cko = INPLL(pllMDLL_CKO)   | MDLL_CKO__MCKOA_SLEEP
1153 		| MDLL_CKO__MCKOA_RESET;
1154 	u32 cka = INPLL(pllMDLL_RDCKA) | MDLL_RDCKA__MRDCKA0_SLEEP
1155 		| MDLL_RDCKA__MRDCKA1_SLEEP | MDLL_RDCKA__MRDCKA0_RESET
1156 		| MDLL_RDCKA__MRDCKA1_RESET;
1157 	u32 ckb = INPLL(pllMDLL_RDCKB) | MDLL_RDCKB__MRDCKB0_SLEEP
1158 		| MDLL_RDCKB__MRDCKB1_SLEEP | MDLL_RDCKB__MRDCKB0_RESET
1159 		| MDLL_RDCKB__MRDCKB1_RESET;
1160 
1161 	/* Setting up the DLL range for write */
1162 	OUTPLL(pllMDLL_CKO,   	cko);
1163 	OUTPLL(pllMDLL_RDCKA,  	cka);
1164 	OUTPLL(pllMDLL_RDCKB,	ckb);
1165 
1166 	mdelay(DLL_RESET_DELAY*2);
1167 
1168 	cko &= ~(MDLL_CKO__MCKOA_SLEEP | MDLL_CKO__MCKOB_SLEEP);
1169 	OUTPLL(pllMDLL_CKO, cko);
1170 	mdelay(DLL_SLEEP_DELAY);
1171 	cko &= ~(MDLL_CKO__MCKOA_RESET | MDLL_CKO__MCKOB_RESET);
1172 	OUTPLL(pllMDLL_CKO, cko);
1173 	mdelay(DLL_RESET_DELAY);
1174 
1175 	cka &= ~(MDLL_RDCKA__MRDCKA0_SLEEP | MDLL_RDCKA__MRDCKA1_SLEEP);
1176 	OUTPLL(pllMDLL_RDCKA, cka);
1177 	mdelay(DLL_SLEEP_DELAY);
1178 	cka &= ~(MDLL_RDCKA__MRDCKA0_RESET | MDLL_RDCKA__MRDCKA1_RESET);
1179 	OUTPLL(pllMDLL_RDCKA, cka);
1180 	mdelay(DLL_RESET_DELAY);
1181 
1182 	ckb &= ~(MDLL_RDCKB__MRDCKB0_SLEEP | MDLL_RDCKB__MRDCKB1_SLEEP);
1183 	OUTPLL(pllMDLL_RDCKB, ckb);
1184 	mdelay(DLL_SLEEP_DELAY);
1185 	ckb &= ~(MDLL_RDCKB__MRDCKB0_RESET | MDLL_RDCKB__MRDCKB1_RESET);
1186 	OUTPLL(pllMDLL_RDCKB, ckb);
1187 	mdelay(DLL_RESET_DELAY);
1188 
1189 
1190 #undef DLL_RESET_DELAY
1191 #undef DLL_SLEEP_DELAY
1192 }
1193 
1194 static void radeon_pm_enable_dll_m10(struct radeonfb_info *rinfo)
1195 {
1196 	u32 dll_value;
1197 	u32 dll_sleep_mask = 0;
1198 	u32 dll_reset_mask = 0;
1199 	u32 mc;
1200 
1201 #define DLL_RESET_DELAY 	5
1202 #define DLL_SLEEP_DELAY		1
1203 
1204 	OUTMC(rinfo, ixR300_MC_DLL_CNTL, rinfo->save_regs[70]);
1205 	mc = INREG(MC_CNTL);
1206 	/* Check which channels are enabled */
1207 	switch (mc & 0x3) {
1208 	case 1:
1209 		if (mc & 0x4)
1210 			break;
1211 		/* fall through */
1212 	case 2:
1213 		dll_sleep_mask |= MDLL_R300_RDCK__MRDCKB_SLEEP;
1214 		dll_reset_mask |= MDLL_R300_RDCK__MRDCKB_RESET;
1215 		/* fall through */
1216 	case 0:
1217 		dll_sleep_mask |= MDLL_R300_RDCK__MRDCKA_SLEEP;
1218 		dll_reset_mask |= MDLL_R300_RDCK__MRDCKA_RESET;
1219 	}
1220 	switch (mc & 0x3) {
1221 	case 1:
1222 		if (!(mc & 0x4))
1223 			break;
1224 		/* fall through */
1225 	case 2:
1226 		dll_sleep_mask |= MDLL_R300_RDCK__MRDCKD_SLEEP;
1227 		dll_reset_mask |= MDLL_R300_RDCK__MRDCKD_RESET;
1228 		dll_sleep_mask |= MDLL_R300_RDCK__MRDCKC_SLEEP;
1229 		dll_reset_mask |= MDLL_R300_RDCK__MRDCKC_RESET;
1230 	}
1231 
1232 	dll_value = INPLL(pllMDLL_RDCKA);
1233 
1234 	/* Power Up */
1235 	dll_value &= ~(dll_sleep_mask);
1236 	OUTPLL(pllMDLL_RDCKA, dll_value);
1237 	mdelay( DLL_SLEEP_DELAY);
1238 
1239 	dll_value &= ~(dll_reset_mask);
1240 	OUTPLL(pllMDLL_RDCKA, dll_value);
1241 	mdelay( DLL_RESET_DELAY);
1242 
1243 #undef DLL_RESET_DELAY
1244 #undef DLL_SLEEP_DELAY
1245 }
1246 
1247 
1248 static void radeon_pm_full_reset_sdram(struct radeonfb_info *rinfo)
1249 {
1250 	u32 crtcGenCntl, crtcGenCntl2, memRefreshCntl, crtc_more_cntl,
1251 		fp_gen_cntl, fp2_gen_cntl;
1252 
1253 	crtcGenCntl  = INREG( CRTC_GEN_CNTL);
1254 	crtcGenCntl2 = INREG( CRTC2_GEN_CNTL);
1255 
1256 	crtc_more_cntl 	= INREG( CRTC_MORE_CNTL);
1257 	fp_gen_cntl 	= INREG( FP_GEN_CNTL);
1258 	fp2_gen_cntl 	= INREG( FP2_GEN_CNTL);
1259 
1260 
1261 	OUTREG( CRTC_MORE_CNTL, 0);
1262 	OUTREG( FP_GEN_CNTL, 0);
1263 	OUTREG( FP2_GEN_CNTL,0);
1264 
1265 	OUTREG( CRTC_GEN_CNTL,  (crtcGenCntl | CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B) );
1266 	OUTREG( CRTC2_GEN_CNTL, (crtcGenCntl2 | CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B) );
1267 
1268 	/* This is the code for the Aluminium PowerBooks M10 / iBooks M11 */
1269 	if (rinfo->family == CHIP_FAMILY_RV350) {
1270 		u32 sdram_mode_reg = rinfo->save_regs[35];
1271 		static const u32 default_mrtable[] =
1272 			{ 0x21320032,
1273 			  0x21321000, 0xa1321000, 0x21321000, 0xffffffff,
1274 			  0x21320032, 0xa1320032, 0x21320032, 0xffffffff,
1275 			  0x21321002, 0xa1321002, 0x21321002, 0xffffffff,
1276 			  0x21320132, 0xa1320132, 0x21320132, 0xffffffff,
1277 			  0x21320032, 0xa1320032, 0x21320032, 0xffffffff,
1278 			  0x31320032 };
1279 
1280 		const u32 *mrtable = default_mrtable;
1281 		int i, mrtable_size = ARRAY_SIZE(default_mrtable);
1282 
1283 		mdelay(30);
1284 
1285 		/* Disable refresh */
1286 		memRefreshCntl 	= INREG( MEM_REFRESH_CNTL)
1287 			& ~MEM_REFRESH_CNTL__MEM_REFRESH_DIS;
1288 		OUTREG( MEM_REFRESH_CNTL, memRefreshCntl
1289 			| MEM_REFRESH_CNTL__MEM_REFRESH_DIS);
1290 
1291 		/* Configure and enable M & SPLLs */
1292        		radeon_pm_enable_dll_m10(rinfo);
1293 		radeon_pm_yclk_mclk_sync_m10(rinfo);
1294 
1295 #ifdef CONFIG_PPC
1296 		if (rinfo->of_node != NULL) {
1297 			int size;
1298 
1299 			mrtable = of_get_property(rinfo->of_node, "ATY,MRT", &size);
1300 			if (mrtable)
1301 				mrtable_size = size >> 2;
1302 			else
1303 				mrtable = default_mrtable;
1304 		}
1305 #endif /* CONFIG_PPC */
1306 
1307 		/* Program the SDRAM */
1308 		sdram_mode_reg = mrtable[0];
1309 		OUTREG(MEM_SDRAM_MODE_REG, sdram_mode_reg);
1310 		for (i = 0; i < mrtable_size; i++) {
1311 			if (mrtable[i] == 0xffffffffu)
1312 				radeon_pm_m10_program_mode_wait(rinfo);
1313 			else {
1314 				sdram_mode_reg &= ~(MEM_SDRAM_MODE_REG__MEM_MODE_REG_MASK
1315 						    | MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE
1316 						    | MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET);
1317 				sdram_mode_reg |= mrtable[i];
1318 
1319 				OUTREG(MEM_SDRAM_MODE_REG, sdram_mode_reg);
1320 				mdelay(1);
1321 			}
1322 		}
1323 
1324 		/* Restore memory refresh */
1325 		OUTREG(MEM_REFRESH_CNTL, memRefreshCntl);
1326 		mdelay(30);
1327 
1328 	}
1329 	/* Here come the desktop RV200 "QW" card */
1330 	else if (!rinfo->is_mobility && rinfo->family == CHIP_FAMILY_RV200) {
1331 		/* Disable refresh */
1332 		memRefreshCntl 	= INREG( MEM_REFRESH_CNTL)
1333 			& ~MEM_REFRESH_CNTL__MEM_REFRESH_DIS;
1334 		OUTREG(MEM_REFRESH_CNTL, memRefreshCntl
1335 		       | MEM_REFRESH_CNTL__MEM_REFRESH_DIS);
1336 		mdelay(30);
1337 
1338 		/* Reset memory */
1339 		OUTREG(MEM_SDRAM_MODE_REG,
1340 		       INREG( MEM_SDRAM_MODE_REG) & ~MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE);
1341 
1342 		radeon_pm_program_mode_reg(rinfo, 0x2002, 2);
1343 		radeon_pm_program_mode_reg(rinfo, 0x0132, 2);
1344 		radeon_pm_program_mode_reg(rinfo, 0x0032, 2);
1345 
1346 		OUTREG(MEM_SDRAM_MODE_REG,
1347 		       INREG(MEM_SDRAM_MODE_REG) | MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE);
1348 
1349 		OUTREG( MEM_REFRESH_CNTL, 	memRefreshCntl);
1350 
1351 	}
1352 	/* The M6 */
1353 	else if (rinfo->is_mobility && rinfo->family == CHIP_FAMILY_RV100) {
1354 		/* Disable refresh */
1355 		memRefreshCntl = INREG(EXT_MEM_CNTL) & ~(1 << 20);
1356 		OUTREG( EXT_MEM_CNTL, memRefreshCntl | (1 << 20));
1357 
1358 		/* Reset memory */
1359 		OUTREG( MEM_SDRAM_MODE_REG,
1360 			INREG( MEM_SDRAM_MODE_REG)
1361 			& ~MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE);
1362 
1363 		/* DLL */
1364 		radeon_pm_enable_dll(rinfo);
1365 
1366 		/* MLCK / YCLK sync */
1367 		radeon_pm_yclk_mclk_sync(rinfo);
1368 
1369 		/* Program Mode Register */
1370 		radeon_pm_program_mode_reg(rinfo, 0x2000, 1);
1371 		radeon_pm_program_mode_reg(rinfo, 0x2001, 1);
1372 		radeon_pm_program_mode_reg(rinfo, 0x2002, 1);
1373 		radeon_pm_program_mode_reg(rinfo, 0x0132, 1);
1374 		radeon_pm_program_mode_reg(rinfo, 0x0032, 1);
1375 
1376 		/* Complete & re-enable refresh */
1377 		OUTREG( MEM_SDRAM_MODE_REG,
1378 			INREG( MEM_SDRAM_MODE_REG) | MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE);
1379 
1380 		OUTREG(EXT_MEM_CNTL, memRefreshCntl);
1381 	}
1382 	/* And finally, the M7..M9 models, including M9+ (RV280) */
1383 	else if (rinfo->is_mobility) {
1384 
1385 		/* Disable refresh */
1386 		memRefreshCntl 	= INREG( MEM_REFRESH_CNTL)
1387 			& ~MEM_REFRESH_CNTL__MEM_REFRESH_DIS;
1388 		OUTREG( MEM_REFRESH_CNTL, memRefreshCntl
1389 			| MEM_REFRESH_CNTL__MEM_REFRESH_DIS);
1390 
1391 		/* Reset memory */
1392 		OUTREG( MEM_SDRAM_MODE_REG,
1393 			INREG( MEM_SDRAM_MODE_REG)
1394 			& ~MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE);
1395 
1396 		/* DLL */
1397 		radeon_pm_enable_dll(rinfo);
1398 
1399 		/* MLCK / YCLK sync */
1400 		radeon_pm_yclk_mclk_sync(rinfo);
1401 
1402 		/* M6, M7 and M9 so far ... */
1403 		if (rinfo->family <= CHIP_FAMILY_RV250) {
1404 			radeon_pm_program_mode_reg(rinfo, 0x2000, 1);
1405 			radeon_pm_program_mode_reg(rinfo, 0x2001, 1);
1406 			radeon_pm_program_mode_reg(rinfo, 0x2002, 1);
1407 			radeon_pm_program_mode_reg(rinfo, 0x0132, 1);
1408 			radeon_pm_program_mode_reg(rinfo, 0x0032, 1);
1409 		}
1410 		/* M9+ (iBook G4) */
1411 		else if (rinfo->family == CHIP_FAMILY_RV280) {
1412 			radeon_pm_program_mode_reg(rinfo, 0x2000, 1);
1413 			radeon_pm_program_mode_reg(rinfo, 0x0132, 1);
1414 			radeon_pm_program_mode_reg(rinfo, 0x0032, 1);
1415 		}
1416 
1417 		/* Complete & re-enable refresh */
1418 		OUTREG( MEM_SDRAM_MODE_REG,
1419 			INREG( MEM_SDRAM_MODE_REG) | MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE);
1420 
1421 		OUTREG( MEM_REFRESH_CNTL, 	memRefreshCntl);
1422 	}
1423 
1424 	OUTREG( CRTC_GEN_CNTL, 		crtcGenCntl);
1425 	OUTREG( CRTC2_GEN_CNTL, 	crtcGenCntl2);
1426 	OUTREG( FP_GEN_CNTL, 		fp_gen_cntl);
1427 	OUTREG( FP2_GEN_CNTL, 		fp2_gen_cntl);
1428 
1429 	OUTREG( CRTC_MORE_CNTL, 	crtc_more_cntl);
1430 
1431 	mdelay( 15);
1432 }
1433 
1434 #if defined(CONFIG_PM)
1435 #if defined(CONFIG_X86) || defined(CONFIG_PPC_PMAC)
1436 static void radeon_pm_reset_pad_ctlr_strength(struct radeonfb_info *rinfo)
1437 {
1438 	u32 tmp, tmp2;
1439 	int i,j;
1440 
1441 	/* Reset the PAD_CTLR_STRENGTH & wait for it to be stable */
1442 	INREG(PAD_CTLR_STRENGTH);
1443 	OUTREG(PAD_CTLR_STRENGTH, INREG(PAD_CTLR_STRENGTH) & ~PAD_MANUAL_OVERRIDE);
1444 	tmp = INREG(PAD_CTLR_STRENGTH);
1445 	for (i = j = 0; i < 65; ++i) {
1446 		mdelay(1);
1447 		tmp2 = INREG(PAD_CTLR_STRENGTH);
1448 		if (tmp != tmp2) {
1449 			tmp = tmp2;
1450 			i = 0;
1451 			j++;
1452 			if (j > 10) {
1453 				printk(KERN_WARNING "radeon: PAD_CTLR_STRENGTH doesn't "
1454 				       "stabilize !\n");
1455 				break;
1456 			}
1457 		}
1458 	}
1459 }
1460 
1461 static void radeon_pm_all_ppls_off(struct radeonfb_info *rinfo)
1462 {
1463 	u32 tmp;
1464 
1465 	tmp = INPLL(pllPPLL_CNTL);
1466 	OUTPLL(pllPPLL_CNTL, tmp | 0x3);
1467 	tmp = INPLL(pllP2PLL_CNTL);
1468 	OUTPLL(pllP2PLL_CNTL, tmp | 0x3);
1469 	tmp = INPLL(pllSPLL_CNTL);
1470 	OUTPLL(pllSPLL_CNTL, tmp | 0x3);
1471 	tmp = INPLL(pllMPLL_CNTL);
1472 	OUTPLL(pllMPLL_CNTL, tmp | 0x3);
1473 }
1474 
1475 static void radeon_pm_start_mclk_sclk(struct radeonfb_info *rinfo)
1476 {
1477 	u32 tmp;
1478 
1479 	/* Switch SPLL to PCI source */
1480 	tmp = INPLL(pllSCLK_CNTL);
1481 	OUTPLL(pllSCLK_CNTL, tmp & ~SCLK_CNTL__SCLK_SRC_SEL_MASK);
1482 
1483 	/* Reconfigure SPLL charge pump, VCO gain, duty cycle */
1484 	tmp = INPLL(pllSPLL_CNTL);
1485 	OUTREG8(CLOCK_CNTL_INDEX, pllSPLL_CNTL + PLL_WR_EN);
1486 	radeon_pll_errata_after_index(rinfo);
1487 	OUTREG8(CLOCK_CNTL_DATA + 1, (tmp >> 8) & 0xff);
1488 	radeon_pll_errata_after_data(rinfo);
1489 
1490 	/* Set SPLL feedback divider */
1491 	tmp = INPLL(pllM_SPLL_REF_FB_DIV);
1492 	tmp = (tmp & 0xff00fffful) | (rinfo->save_regs[77] & 0x00ff0000ul);
1493 	OUTPLL(pllM_SPLL_REF_FB_DIV, tmp);
1494 
1495 	/* Power up SPLL */
1496 	tmp = INPLL(pllSPLL_CNTL);
1497 	OUTPLL(pllSPLL_CNTL, tmp & ~1);
1498 	(void)INPLL(pllSPLL_CNTL);
1499 
1500 	mdelay(10);
1501 
1502 	/* Release SPLL reset */
1503 	tmp = INPLL(pllSPLL_CNTL);
1504 	OUTPLL(pllSPLL_CNTL, tmp & ~0x2);
1505 	(void)INPLL(pllSPLL_CNTL);
1506 
1507 	mdelay(10);
1508 
1509 	/* Select SCLK source  */
1510 	tmp = INPLL(pllSCLK_CNTL);
1511 	tmp &= ~SCLK_CNTL__SCLK_SRC_SEL_MASK;
1512 	tmp |= rinfo->save_regs[3] & SCLK_CNTL__SCLK_SRC_SEL_MASK;
1513 	OUTPLL(pllSCLK_CNTL, tmp);
1514 	(void)INPLL(pllSCLK_CNTL);
1515 
1516 	mdelay(10);
1517 
1518 	/* Reconfigure MPLL charge pump, VCO gain, duty cycle */
1519 	tmp = INPLL(pllMPLL_CNTL);
1520 	OUTREG8(CLOCK_CNTL_INDEX, pllMPLL_CNTL + PLL_WR_EN);
1521 	radeon_pll_errata_after_index(rinfo);
1522 	OUTREG8(CLOCK_CNTL_DATA + 1, (tmp >> 8) & 0xff);
1523 	radeon_pll_errata_after_data(rinfo);
1524 
1525 	/* Set MPLL feedback divider */
1526 	tmp = INPLL(pllM_SPLL_REF_FB_DIV);
1527 	tmp = (tmp & 0xffff00fful) | (rinfo->save_regs[77] & 0x0000ff00ul);
1528 
1529 	OUTPLL(pllM_SPLL_REF_FB_DIV, tmp);
1530 	/* Power up MPLL */
1531 	tmp = INPLL(pllMPLL_CNTL);
1532 	OUTPLL(pllMPLL_CNTL, tmp & ~0x2);
1533 	(void)INPLL(pllMPLL_CNTL);
1534 
1535 	mdelay(10);
1536 
1537 	/* Un-reset MPLL */
1538 	tmp = INPLL(pllMPLL_CNTL);
1539 	OUTPLL(pllMPLL_CNTL, tmp & ~0x1);
1540 	(void)INPLL(pllMPLL_CNTL);
1541 
1542 	mdelay(10);
1543 
1544 	/* Select source for MCLK */
1545 	tmp = INPLL(pllMCLK_CNTL);
1546 	tmp |= rinfo->save_regs[2] & 0xffff;
1547 	OUTPLL(pllMCLK_CNTL, tmp);
1548 	(void)INPLL(pllMCLK_CNTL);
1549 
1550 	mdelay(10);
1551 }
1552 
1553 static void radeon_pm_m10_disable_spread_spectrum(struct radeonfb_info *rinfo)
1554 {
1555 	u32 r2ec;
1556 
1557 	/* GACK ! I though we didn't have a DDA on Radeon's anymore
1558 	 * here we rewrite with the same value, ... I suppose we clear
1559 	 * some bits that are already clear ? Or maybe this 0x2ec
1560 	 * register is something new ?
1561 	 */
1562 	mdelay(20);
1563 	r2ec = INREG(VGA_DDA_ON_OFF);
1564 	OUTREG(VGA_DDA_ON_OFF, r2ec);
1565 	mdelay(1);
1566 
1567 	/* Spread spectrum PLLL off */
1568 	OUTPLL(pllSSPLL_CNTL, 0xbf03);
1569 
1570 	/* Spread spectrum disabled */
1571 	OUTPLL(pllSS_INT_CNTL, rinfo->save_regs[90] & ~3);
1572 
1573 	/* The trace shows read & rewrite of LVDS_PLL_CNTL here with same
1574 	 * value, not sure what for...
1575 	 */
1576 
1577 	r2ec |= 0x3f0;
1578 	OUTREG(VGA_DDA_ON_OFF, r2ec);
1579 	mdelay(1);
1580 }
1581 
1582 static void radeon_pm_m10_enable_lvds_spread_spectrum(struct radeonfb_info *rinfo)
1583 {
1584 	u32 r2ec, tmp;
1585 
1586 	/* GACK (bis) ! I though we didn't have a DDA on Radeon's anymore
1587 	 * here we rewrite with the same value, ... I suppose we clear/set
1588 	 * some bits that are already clear/set ?
1589 	 */
1590 	r2ec = INREG(VGA_DDA_ON_OFF);
1591 	OUTREG(VGA_DDA_ON_OFF, r2ec);
1592 	mdelay(1);
1593 
1594 	/* Enable spread spectrum */
1595 	OUTPLL(pllSSPLL_CNTL, rinfo->save_regs[43] | 3);
1596 	mdelay(3);
1597 
1598 	OUTPLL(pllSSPLL_REF_DIV, rinfo->save_regs[44]);
1599 	OUTPLL(pllSSPLL_DIV_0, rinfo->save_regs[45]);
1600 	tmp = INPLL(pllSSPLL_CNTL);
1601 	OUTPLL(pllSSPLL_CNTL, tmp & ~0x2);
1602 	mdelay(6);
1603 	tmp = INPLL(pllSSPLL_CNTL);
1604 	OUTPLL(pllSSPLL_CNTL, tmp & ~0x1);
1605 	mdelay(5);
1606 
1607        	OUTPLL(pllSS_INT_CNTL, rinfo->save_regs[90]);
1608 
1609 	r2ec |= 8;
1610 	OUTREG(VGA_DDA_ON_OFF, r2ec);
1611 	mdelay(20);
1612 
1613 	/* Enable LVDS interface */
1614 	tmp = INREG(LVDS_GEN_CNTL);
1615 	OUTREG(LVDS_GEN_CNTL, tmp | LVDS_EN);
1616 
1617 	/* Enable LVDS_PLL */
1618 	tmp = INREG(LVDS_PLL_CNTL);
1619 	tmp &= ~0x30000;
1620 	tmp |= 0x10000;
1621 	OUTREG(LVDS_PLL_CNTL, tmp);
1622 
1623 	OUTPLL(pllSCLK_MORE_CNTL, rinfo->save_regs[34]);
1624 	OUTPLL(pllSS_TST_CNTL, rinfo->save_regs[91]);
1625 
1626 	/* The trace reads that one here, waiting for something to settle down ? */
1627 	INREG(RBBM_STATUS);
1628 
1629 	/* Ugh ? SS_TST_DEC is supposed to be a read register in the
1630 	 * R300 register spec at least...
1631 	 */
1632 	tmp = INPLL(pllSS_TST_CNTL);
1633 	tmp |= 0x00400000;
1634 	OUTPLL(pllSS_TST_CNTL, tmp);
1635 }
1636 
1637 static void radeon_pm_restore_pixel_pll(struct radeonfb_info *rinfo)
1638 {
1639 	u32 tmp;
1640 
1641 	OUTREG8(CLOCK_CNTL_INDEX, pllHTOTAL_CNTL + PLL_WR_EN);
1642 	radeon_pll_errata_after_index(rinfo);
1643 	OUTREG8(CLOCK_CNTL_DATA, 0);
1644 	radeon_pll_errata_after_data(rinfo);
1645 
1646 	tmp = INPLL(pllVCLK_ECP_CNTL);
1647 	OUTPLL(pllVCLK_ECP_CNTL, tmp | 0x80);
1648 	mdelay(5);
1649 
1650 	tmp = INPLL(pllPPLL_REF_DIV);
1651 	tmp = (tmp & ~PPLL_REF_DIV_MASK) | rinfo->pll.ref_div;
1652 	OUTPLL(pllPPLL_REF_DIV, tmp);
1653 	INPLL(pllPPLL_REF_DIV);
1654 
1655 	/* Reconfigure SPLL charge pump, VCO gain, duty cycle,
1656 	 * probably useless since we already did it ...
1657 	 */
1658 	tmp = INPLL(pllPPLL_CNTL);
1659 	OUTREG8(CLOCK_CNTL_INDEX, pllSPLL_CNTL + PLL_WR_EN);
1660 	radeon_pll_errata_after_index(rinfo);
1661 	OUTREG8(CLOCK_CNTL_DATA + 1, (tmp >> 8) & 0xff);
1662 	radeon_pll_errata_after_data(rinfo);
1663 
1664 	/* Restore our "reference" PPLL divider set by firmware
1665 	 * according to proper spread spectrum calculations
1666 	 */
1667 	OUTPLL(pllPPLL_DIV_0, rinfo->save_regs[92]);
1668 
1669 	tmp = INPLL(pllPPLL_CNTL);
1670 	OUTPLL(pllPPLL_CNTL, tmp & ~0x2);
1671 	mdelay(5);
1672 
1673 	tmp = INPLL(pllPPLL_CNTL);
1674 	OUTPLL(pllPPLL_CNTL, tmp & ~0x1);
1675 	mdelay(5);
1676 
1677 	tmp = INPLL(pllVCLK_ECP_CNTL);
1678 	OUTPLL(pllVCLK_ECP_CNTL, tmp | 3);
1679 	mdelay(5);
1680 
1681 	tmp = INPLL(pllVCLK_ECP_CNTL);
1682 	OUTPLL(pllVCLK_ECP_CNTL, tmp | 3);
1683 	mdelay(5);
1684 
1685 	/* Switch pixel clock to firmware default div 0 */
1686 	OUTREG8(CLOCK_CNTL_INDEX+1, 0);
1687 	radeon_pll_errata_after_index(rinfo);
1688 	radeon_pll_errata_after_data(rinfo);
1689 }
1690 
1691 static void radeon_pm_m10_reconfigure_mc(struct radeonfb_info *rinfo)
1692 {
1693 	OUTREG(MC_CNTL, rinfo->save_regs[46]);
1694 	OUTREG(MC_INIT_GFX_LAT_TIMER, rinfo->save_regs[47]);
1695 	OUTREG(MC_INIT_MISC_LAT_TIMER, rinfo->save_regs[48]);
1696 	OUTREG(MEM_SDRAM_MODE_REG,
1697 	       rinfo->save_regs[35] & ~MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE);
1698 	OUTREG(MC_TIMING_CNTL, rinfo->save_regs[49]);
1699 	OUTREG(MEM_REFRESH_CNTL, rinfo->save_regs[42]);
1700 	OUTREG(MC_READ_CNTL_AB, rinfo->save_regs[50]);
1701 	OUTREG(MC_CHIP_IO_OE_CNTL_AB, rinfo->save_regs[52]);
1702 	OUTREG(MC_IOPAD_CNTL, rinfo->save_regs[51]);
1703 	OUTREG(MC_DEBUG, rinfo->save_regs[53]);
1704 
1705 	OUTMC(rinfo, ixR300_MC_MC_INIT_WR_LAT_TIMER, rinfo->save_regs[58]);
1706 	OUTMC(rinfo, ixR300_MC_IMP_CNTL, rinfo->save_regs[59]);
1707 	OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_C0, rinfo->save_regs[60]);
1708 	OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_C1, rinfo->save_regs[61]);
1709 	OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_D0, rinfo->save_regs[62]);
1710 	OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_D1, rinfo->save_regs[63]);
1711 	OUTMC(rinfo, ixR300_MC_BIST_CNTL_3, rinfo->save_regs[64]);
1712 	OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_A0, rinfo->save_regs[65]);
1713 	OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_A1, rinfo->save_regs[66]);
1714 	OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_B0, rinfo->save_regs[67]);
1715 	OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_B1, rinfo->save_regs[68]);
1716 	OUTMC(rinfo, ixR300_MC_DEBUG_CNTL, rinfo->save_regs[69]);
1717 	OUTMC(rinfo, ixR300_MC_DLL_CNTL, rinfo->save_regs[70]);
1718 	OUTMC(rinfo, ixR300_MC_IMP_CNTL_0, rinfo->save_regs[71]);
1719 	OUTMC(rinfo, ixR300_MC_ELPIDA_CNTL, rinfo->save_regs[72]);
1720 	OUTMC(rinfo, ixR300_MC_READ_CNTL_CD, rinfo->save_regs[96]);
1721 	OUTREG(MC_IND_INDEX, 0);
1722 }
1723 
1724 static void radeon_reinitialize_M10(struct radeonfb_info *rinfo)
1725 {
1726 	u32 tmp, i;
1727 
1728 	/* Restore a bunch of registers first */
1729 	OUTREG(MC_AGP_LOCATION, rinfo->save_regs[32]);
1730 	OUTREG(DISPLAY_BASE_ADDR, rinfo->save_regs[31]);
1731 	OUTREG(CRTC2_DISPLAY_BASE_ADDR, rinfo->save_regs[33]);
1732 	OUTREG(MC_FB_LOCATION, rinfo->save_regs[30]);
1733 	OUTREG(OV0_BASE_ADDR, rinfo->save_regs[80]);
1734 	OUTREG(CNFG_MEMSIZE, rinfo->video_ram);
1735 	OUTREG(BUS_CNTL, rinfo->save_regs[36]);
1736 	OUTREG(BUS_CNTL1, rinfo->save_regs[14]);
1737 	OUTREG(MPP_TB_CONFIG, rinfo->save_regs[37]);
1738 	OUTREG(FCP_CNTL, rinfo->save_regs[38]);
1739 	OUTREG(RBBM_CNTL, rinfo->save_regs[39]);
1740 	OUTREG(DAC_CNTL, rinfo->save_regs[40]);
1741 	OUTREG(DAC_MACRO_CNTL, (INREG(DAC_MACRO_CNTL) & ~0x6) | 8);
1742 	OUTREG(DAC_MACRO_CNTL, (INREG(DAC_MACRO_CNTL) & ~0x6) | 8);
1743 
1744 	/* Hrm... */
1745 	OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) | DAC2_EXPAND_MODE);
1746 
1747 	/* Reset the PAD CTLR */
1748 	radeon_pm_reset_pad_ctlr_strength(rinfo);
1749 
1750 	/* Some PLLs are Read & written identically in the trace here...
1751 	 * I suppose it's actually to switch them all off & reset,
1752 	 * let's assume off is what we want. I'm just doing that for all major PLLs now.
1753 	 */
1754 	radeon_pm_all_ppls_off(rinfo);
1755 
1756 	/* Clear tiling, reset swappers */
1757 	INREG(SURFACE_CNTL);
1758 	OUTREG(SURFACE_CNTL, 0);
1759 
1760 	/* Some black magic with TV_DAC_CNTL, we should restore those from backups
1761 	 * rather than hard coding...
1762 	 */
1763 	tmp = INREG(TV_DAC_CNTL) & ~TV_DAC_CNTL_BGADJ_MASK;
1764 	tmp |= 8 << TV_DAC_CNTL_BGADJ__SHIFT;
1765 	OUTREG(TV_DAC_CNTL, tmp);
1766 
1767 	tmp = INREG(TV_DAC_CNTL) & ~TV_DAC_CNTL_DACADJ_MASK;
1768 	tmp |= 7 << TV_DAC_CNTL_DACADJ__SHIFT;
1769 	OUTREG(TV_DAC_CNTL, tmp);
1770 
1771 	/* More registers restored */
1772 	OUTREG(AGP_CNTL, rinfo->save_regs[16]);
1773 	OUTREG(HOST_PATH_CNTL, rinfo->save_regs[41]);
1774 	OUTREG(DISP_MISC_CNTL, rinfo->save_regs[9]);
1775 
1776 	/* Hrmmm ... What is that ? */
1777 	tmp = rinfo->save_regs[1]
1778 		& ~(CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT_MASK |
1779 		    CLK_PWRMGT_CNTL__MC_BUSY);
1780 	OUTPLL(pllCLK_PWRMGT_CNTL, tmp);
1781 
1782 	OUTREG(PAD_CTLR_MISC, rinfo->save_regs[56]);
1783 	OUTREG(FW_CNTL, rinfo->save_regs[57]);
1784 	OUTREG(HDP_DEBUG, rinfo->save_regs[96]);
1785 	OUTREG(PAMAC0_DLY_CNTL, rinfo->save_regs[54]);
1786 	OUTREG(PAMAC1_DLY_CNTL, rinfo->save_regs[55]);
1787 	OUTREG(PAMAC2_DLY_CNTL, rinfo->save_regs[79]);
1788 
1789 	/* Restore Memory Controller configuration */
1790 	radeon_pm_m10_reconfigure_mc(rinfo);
1791 
1792 	/* Make sure CRTC's dont touch memory */
1793 	OUTREG(CRTC_GEN_CNTL, INREG(CRTC_GEN_CNTL)
1794 	       | CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B);
1795 	OUTREG(CRTC2_GEN_CNTL, INREG(CRTC2_GEN_CNTL)
1796 	       | CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B);
1797 	mdelay(30);
1798 
1799 	/* Disable SDRAM refresh */
1800 	OUTREG(MEM_REFRESH_CNTL, INREG(MEM_REFRESH_CNTL)
1801 	       | MEM_REFRESH_CNTL__MEM_REFRESH_DIS);
1802 
1803 	/* Restore XTALIN routing (CLK_PIN_CNTL) */
1804 	OUTPLL(pllCLK_PIN_CNTL, rinfo->save_regs[4]);
1805 
1806 	/* Switch MCLK, YCLK and SCLK PLLs to PCI source & force them ON */
1807 	tmp = rinfo->save_regs[2] & 0xff000000;
1808 	tmp |=	MCLK_CNTL__FORCE_MCLKA |
1809 		MCLK_CNTL__FORCE_MCLKB |
1810 		MCLK_CNTL__FORCE_YCLKA |
1811 		MCLK_CNTL__FORCE_YCLKB |
1812 		MCLK_CNTL__FORCE_MC;
1813 	OUTPLL(pllMCLK_CNTL, tmp);
1814 
1815 	/* Force all clocks on in SCLK */
1816 	tmp = INPLL(pllSCLK_CNTL);
1817 	tmp |=	SCLK_CNTL__FORCE_DISP2|
1818 		SCLK_CNTL__FORCE_CP|
1819 		SCLK_CNTL__FORCE_HDP|
1820 		SCLK_CNTL__FORCE_DISP1|
1821 		SCLK_CNTL__FORCE_TOP|
1822 		SCLK_CNTL__FORCE_E2|
1823 		SCLK_CNTL__FORCE_SE|
1824 		SCLK_CNTL__FORCE_IDCT|
1825 		SCLK_CNTL__FORCE_VIP|
1826 		SCLK_CNTL__FORCE_PB|
1827 		SCLK_CNTL__FORCE_TAM|
1828 		SCLK_CNTL__FORCE_TDM|
1829 		SCLK_CNTL__FORCE_RB|
1830 		SCLK_CNTL__FORCE_TV_SCLK|
1831 		SCLK_CNTL__FORCE_SUBPIC|
1832 		SCLK_CNTL__FORCE_OV0;
1833 	tmp |=	SCLK_CNTL__CP_MAX_DYN_STOP_LAT  |
1834 		SCLK_CNTL__HDP_MAX_DYN_STOP_LAT |
1835 		SCLK_CNTL__TV_MAX_DYN_STOP_LAT  |
1836 		SCLK_CNTL__E2_MAX_DYN_STOP_LAT  |
1837 		SCLK_CNTL__SE_MAX_DYN_STOP_LAT  |
1838 		SCLK_CNTL__IDCT_MAX_DYN_STOP_LAT|
1839 		SCLK_CNTL__VIP_MAX_DYN_STOP_LAT |
1840 		SCLK_CNTL__RE_MAX_DYN_STOP_LAT  |
1841 		SCLK_CNTL__PB_MAX_DYN_STOP_LAT  |
1842 		SCLK_CNTL__TAM_MAX_DYN_STOP_LAT |
1843 		SCLK_CNTL__TDM_MAX_DYN_STOP_LAT |
1844 		SCLK_CNTL__RB_MAX_DYN_STOP_LAT;
1845 	OUTPLL(pllSCLK_CNTL, tmp);
1846 
1847 	OUTPLL(pllVCLK_ECP_CNTL, 0);
1848 	OUTPLL(pllPIXCLKS_CNTL, 0);
1849 	OUTPLL(pllMCLK_MISC,
1850 	       MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT |
1851 	       MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT);
1852 
1853 	mdelay(5);
1854 
1855 	/* Restore the M_SPLL_REF_FB_DIV, MPLL_AUX_CNTL and SPLL_AUX_CNTL values */
1856 	OUTPLL(pllM_SPLL_REF_FB_DIV, rinfo->save_regs[77]);
1857 	OUTPLL(pllMPLL_AUX_CNTL, rinfo->save_regs[75]);
1858 	OUTPLL(pllSPLL_AUX_CNTL, rinfo->save_regs[76]);
1859 
1860 	/* Now restore the major PLLs settings, keeping them off & reset though */
1861 	OUTPLL(pllPPLL_CNTL, rinfo->save_regs[93] | 0x3);
1862 	OUTPLL(pllP2PLL_CNTL, rinfo->save_regs[8] | 0x3);
1863 	OUTPLL(pllMPLL_CNTL, rinfo->save_regs[73] | 0x03);
1864 	OUTPLL(pllSPLL_CNTL, rinfo->save_regs[74] | 0x03);
1865 
1866 	/* Restore MC DLL state and switch it off/reset too  */
1867 	OUTMC(rinfo, ixR300_MC_DLL_CNTL, rinfo->save_regs[70]);
1868 
1869 	/* Switch MDLL off & reset */
1870 	OUTPLL(pllMDLL_RDCKA, rinfo->save_regs[98] | 0xff);
1871 	mdelay(5);
1872 
1873 	/* Setup some black magic bits in PLL_PWRMGT_CNTL. Hrm... we saved
1874 	 * 0xa1100007... and MacOS writes 0xa1000007 ..
1875 	 */
1876 	OUTPLL(pllPLL_PWRMGT_CNTL, rinfo->save_regs[0]);
1877 
1878 	/* Restore more stuffs */
1879 	OUTPLL(pllHTOTAL_CNTL, 0);
1880 	OUTPLL(pllHTOTAL2_CNTL, 0);
1881 
1882 	/* More PLL initial configuration */
1883 	tmp = INPLL(pllSCLK_CNTL2); /* What for ? */
1884 	OUTPLL(pllSCLK_CNTL2, tmp);
1885 
1886 	tmp = INPLL(pllSCLK_MORE_CNTL);
1887 	tmp |= 	SCLK_MORE_CNTL__FORCE_DISPREGS |	/* a guess */
1888 		SCLK_MORE_CNTL__FORCE_MC_GUI |
1889 		SCLK_MORE_CNTL__FORCE_MC_HOST;
1890 	OUTPLL(pllSCLK_MORE_CNTL, tmp);
1891 
1892 	/* Now we actually start MCLK and SCLK */
1893 	radeon_pm_start_mclk_sclk(rinfo);
1894 
1895 	/* Full reset sdrams, this also re-inits the MDLL */
1896 	radeon_pm_full_reset_sdram(rinfo);
1897 
1898 	/* Fill palettes */
1899 	OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) | 0x20);
1900 	for (i=0; i<256; i++)
1901 		OUTREG(PALETTE_30_DATA, 0x15555555);
1902 	OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) & ~20);
1903 	udelay(20);
1904 	for (i=0; i<256; i++)
1905 		OUTREG(PALETTE_30_DATA, 0x15555555);
1906 
1907 	OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) & ~0x20);
1908 	mdelay(3);
1909 
1910 	/* Restore TMDS */
1911 	OUTREG(FP_GEN_CNTL, rinfo->save_regs[82]);
1912 	OUTREG(FP2_GEN_CNTL, rinfo->save_regs[83]);
1913 
1914 	/* Set LVDS registers but keep interface & pll down */
1915 	OUTREG(LVDS_GEN_CNTL, rinfo->save_regs[11] &
1916 	       ~(LVDS_EN | LVDS_ON | LVDS_DIGON | LVDS_BLON | LVDS_BL_MOD_EN));
1917 	OUTREG(LVDS_PLL_CNTL, (rinfo->save_regs[12] & ~0xf0000) | 0x20000);
1918 
1919 	OUTREG(DISP_OUTPUT_CNTL, rinfo->save_regs[86]);
1920 
1921 	/* Restore GPIOPAD state */
1922 	OUTREG(GPIOPAD_A, rinfo->save_regs[19]);
1923 	OUTREG(GPIOPAD_EN, rinfo->save_regs[20]);
1924 	OUTREG(GPIOPAD_MASK, rinfo->save_regs[21]);
1925 
1926 	/* write some stuff to the framebuffer... */
1927 	for (i = 0; i < 0x8000; ++i)
1928 		writeb(0, rinfo->fb_base + i);
1929 
1930 	mdelay(40);
1931 	OUTREG(LVDS_GEN_CNTL, INREG(LVDS_GEN_CNTL) | LVDS_DIGON | LVDS_ON);
1932 	mdelay(40);
1933 
1934 	/* Restore a few more things */
1935 	OUTREG(GRPH_BUFFER_CNTL, rinfo->save_regs[94]);
1936 	OUTREG(GRPH2_BUFFER_CNTL, rinfo->save_regs[95]);
1937 
1938 	/* Take care of spread spectrum & PPLLs now */
1939 	radeon_pm_m10_disable_spread_spectrum(rinfo);
1940 	radeon_pm_restore_pixel_pll(rinfo);
1941 
1942 	/* GRRRR... I can't figure out the proper LVDS power sequence, and the
1943 	 * code I have for blank/unblank doesn't quite work on some laptop models
1944 	 * it seems ... Hrm. What I have here works most of the time ...
1945 	 */
1946 	radeon_pm_m10_enable_lvds_spread_spectrum(rinfo);
1947 }
1948 #endif
1949 
1950 #ifdef CONFIG_PPC
1951 #ifdef CONFIG_PPC_PMAC
1952 static void radeon_pm_m9p_reconfigure_mc(struct radeonfb_info *rinfo)
1953 {
1954 	OUTREG(MC_CNTL, rinfo->save_regs[46]);
1955 	OUTREG(MC_INIT_GFX_LAT_TIMER, rinfo->save_regs[47]);
1956 	OUTREG(MC_INIT_MISC_LAT_TIMER, rinfo->save_regs[48]);
1957 	OUTREG(MEM_SDRAM_MODE_REG,
1958 	       rinfo->save_regs[35] & ~MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE);
1959 	OUTREG(MC_TIMING_CNTL, rinfo->save_regs[49]);
1960 	OUTREG(MC_READ_CNTL_AB, rinfo->save_regs[50]);
1961 	OUTREG(MEM_REFRESH_CNTL, rinfo->save_regs[42]);
1962 	OUTREG(MC_IOPAD_CNTL, rinfo->save_regs[51]);
1963 	OUTREG(MC_DEBUG, rinfo->save_regs[53]);
1964 	OUTREG(MC_CHIP_IO_OE_CNTL_AB, rinfo->save_regs[52]);
1965 
1966 	OUTMC(rinfo, ixMC_IMP_CNTL, rinfo->save_regs[59] /*0x00f460d6*/);
1967 	OUTMC(rinfo, ixMC_CHP_IO_CNTL_A0, rinfo->save_regs[65] /*0xfecfa666*/);
1968 	OUTMC(rinfo, ixMC_CHP_IO_CNTL_A1, rinfo->save_regs[66] /*0x141555ff*/);
1969 	OUTMC(rinfo, ixMC_CHP_IO_CNTL_B0, rinfo->save_regs[67] /*0xfecfa666*/);
1970 	OUTMC(rinfo, ixMC_CHP_IO_CNTL_B1, rinfo->save_regs[68] /*0x141555ff*/);
1971 	OUTMC(rinfo, ixMC_IMP_CNTL_0, rinfo->save_regs[71] /*0x00009249*/);
1972 	OUTREG(MC_IND_INDEX, 0);
1973 	OUTREG(CNFG_MEMSIZE, rinfo->video_ram);
1974 
1975 	mdelay(20);
1976 }
1977 
1978 static void radeon_reinitialize_M9P(struct radeonfb_info *rinfo)
1979 {
1980 	u32 tmp, i;
1981 
1982 	/* Restore a bunch of registers first */
1983 	OUTREG(SURFACE_CNTL, rinfo->save_regs[29]);
1984 	OUTREG(MC_AGP_LOCATION, rinfo->save_regs[32]);
1985 	OUTREG(DISPLAY_BASE_ADDR, rinfo->save_regs[31]);
1986 	OUTREG(CRTC2_DISPLAY_BASE_ADDR, rinfo->save_regs[33]);
1987 	OUTREG(MC_FB_LOCATION, rinfo->save_regs[30]);
1988 	OUTREG(OV0_BASE_ADDR, rinfo->save_regs[80]);
1989 	OUTREG(BUS_CNTL, rinfo->save_regs[36]);
1990 	OUTREG(BUS_CNTL1, rinfo->save_regs[14]);
1991 	OUTREG(MPP_TB_CONFIG, rinfo->save_regs[37]);
1992 	OUTREG(FCP_CNTL, rinfo->save_regs[38]);
1993 	OUTREG(RBBM_CNTL, rinfo->save_regs[39]);
1994 
1995 	OUTREG(DAC_CNTL, rinfo->save_regs[40]);
1996 	OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) | DAC2_EXPAND_MODE);
1997 
1998 	/* Reset the PAD CTLR */
1999 	radeon_pm_reset_pad_ctlr_strength(rinfo);
2000 
2001 	/* Some PLLs are Read & written identically in the trace here...
2002 	 * I suppose it's actually to switch them all off & reset,
2003 	 * let's assume off is what we want. I'm just doing that for all major PLLs now.
2004 	 */
2005 	radeon_pm_all_ppls_off(rinfo);
2006 
2007 	/* Clear tiling, reset swappers */
2008 	INREG(SURFACE_CNTL);
2009 	OUTREG(SURFACE_CNTL, 0);
2010 
2011 	/* Some black magic with TV_DAC_CNTL, we should restore those from backups
2012 	 * rather than hard coding...
2013 	 */
2014 	tmp = INREG(TV_DAC_CNTL) & ~TV_DAC_CNTL_BGADJ_MASK;
2015 	tmp |= 6 << TV_DAC_CNTL_BGADJ__SHIFT;
2016 	OUTREG(TV_DAC_CNTL, tmp);
2017 
2018 	tmp = INREG(TV_DAC_CNTL) & ~TV_DAC_CNTL_DACADJ_MASK;
2019 	tmp |= 6 << TV_DAC_CNTL_DACADJ__SHIFT;
2020 	OUTREG(TV_DAC_CNTL, tmp);
2021 
2022 	OUTPLL(pllAGP_PLL_CNTL, rinfo->save_regs[78]);
2023 
2024 	OUTREG(PAMAC0_DLY_CNTL, rinfo->save_regs[54]);
2025 	OUTREG(PAMAC1_DLY_CNTL, rinfo->save_regs[55]);
2026 	OUTREG(PAMAC2_DLY_CNTL, rinfo->save_regs[79]);
2027 
2028 	OUTREG(AGP_CNTL, rinfo->save_regs[16]);
2029 	OUTREG(HOST_PATH_CNTL, rinfo->save_regs[41]); /* MacOS sets that to 0 !!! */
2030 	OUTREG(DISP_MISC_CNTL, rinfo->save_regs[9]);
2031 
2032 	tmp  = rinfo->save_regs[1]
2033 		& ~(CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT_MASK |
2034 		    CLK_PWRMGT_CNTL__MC_BUSY);
2035 	OUTPLL(pllCLK_PWRMGT_CNTL, tmp);
2036 
2037 	OUTREG(FW_CNTL, rinfo->save_regs[57]);
2038 
2039 	/* Disable SDRAM refresh */
2040 	OUTREG(MEM_REFRESH_CNTL, INREG(MEM_REFRESH_CNTL)
2041 	       | MEM_REFRESH_CNTL__MEM_REFRESH_DIS);
2042 
2043 	/* Restore XTALIN routing (CLK_PIN_CNTL) */
2044        	OUTPLL(pllCLK_PIN_CNTL, rinfo->save_regs[4]);
2045 
2046 	/* Force MCLK to be PCI sourced and forced ON */
2047 	tmp = rinfo->save_regs[2] & 0xff000000;
2048 	tmp |=	MCLK_CNTL__FORCE_MCLKA |
2049 		MCLK_CNTL__FORCE_MCLKB |
2050 		MCLK_CNTL__FORCE_YCLKA |
2051 		MCLK_CNTL__FORCE_YCLKB |
2052 		MCLK_CNTL__FORCE_MC    |
2053 		MCLK_CNTL__FORCE_AIC;
2054 	OUTPLL(pllMCLK_CNTL, tmp);
2055 
2056 	/* Force SCLK to be PCI sourced with a bunch forced */
2057 	tmp =	0 |
2058 		SCLK_CNTL__FORCE_DISP2|
2059 		SCLK_CNTL__FORCE_CP|
2060 		SCLK_CNTL__FORCE_HDP|
2061 		SCLK_CNTL__FORCE_DISP1|
2062 		SCLK_CNTL__FORCE_TOP|
2063 		SCLK_CNTL__FORCE_E2|
2064 		SCLK_CNTL__FORCE_SE|
2065 		SCLK_CNTL__FORCE_IDCT|
2066 		SCLK_CNTL__FORCE_VIP|
2067 		SCLK_CNTL__FORCE_RE|
2068 		SCLK_CNTL__FORCE_PB|
2069 		SCLK_CNTL__FORCE_TAM|
2070 		SCLK_CNTL__FORCE_TDM|
2071 		SCLK_CNTL__FORCE_RB;
2072 	OUTPLL(pllSCLK_CNTL, tmp);
2073 
2074 	/* Clear VCLK_ECP_CNTL & PIXCLKS_CNTL  */
2075 	OUTPLL(pllVCLK_ECP_CNTL, 0);
2076 	OUTPLL(pllPIXCLKS_CNTL, 0);
2077 
2078 	/* Setup MCLK_MISC, non dynamic mode */
2079 	OUTPLL(pllMCLK_MISC,
2080 	       MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT |
2081 	       MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT);
2082 
2083 	mdelay(5);
2084 
2085 	/* Set back the default clock dividers */
2086 	OUTPLL(pllM_SPLL_REF_FB_DIV, rinfo->save_regs[77]);
2087 	OUTPLL(pllMPLL_AUX_CNTL, rinfo->save_regs[75]);
2088 	OUTPLL(pllSPLL_AUX_CNTL, rinfo->save_regs[76]);
2089 
2090 	/* PPLL and P2PLL default values & off */
2091 	OUTPLL(pllPPLL_CNTL, rinfo->save_regs[93] | 0x3);
2092 	OUTPLL(pllP2PLL_CNTL, rinfo->save_regs[8] | 0x3);
2093 
2094 	/* S and M PLLs are reset & off, configure them */
2095 	OUTPLL(pllMPLL_CNTL, rinfo->save_regs[73] | 0x03);
2096 	OUTPLL(pllSPLL_CNTL, rinfo->save_regs[74] | 0x03);
2097 
2098 	/* Default values for MDLL ... fixme */
2099 	OUTPLL(pllMDLL_CKO, 0x9c009c);
2100 	OUTPLL(pllMDLL_RDCKA, 0x08830883);
2101 	OUTPLL(pllMDLL_RDCKB, 0x08830883);
2102 	mdelay(5);
2103 
2104 	/* Restore PLL_PWRMGT_CNTL */ // XXXX
2105 	tmp = rinfo->save_regs[0];
2106 	tmp &= ~PLL_PWRMGT_CNTL_SU_SCLK_USE_BCLK;
2107 	tmp |= PLL_PWRMGT_CNTL_SU_MCLK_USE_BCLK;
2108 	OUTPLL(PLL_PWRMGT_CNTL,  tmp);
2109 
2110 	/* Clear HTOTAL_CNTL & HTOTAL2_CNTL */
2111 	OUTPLL(pllHTOTAL_CNTL, 0);
2112 	OUTPLL(pllHTOTAL2_CNTL, 0);
2113 
2114 	/* All outputs off */
2115 	OUTREG(CRTC_GEN_CNTL, 0x04000000);
2116 	OUTREG(CRTC2_GEN_CNTL, 0x04000000);
2117 	OUTREG(FP_GEN_CNTL, 0x00004008);
2118 	OUTREG(FP2_GEN_CNTL, 0x00000008);
2119 	OUTREG(LVDS_GEN_CNTL, 0x08000008);
2120 
2121 	/* Restore Memory Controller configuration */
2122 	radeon_pm_m9p_reconfigure_mc(rinfo);
2123 
2124 	/* Now we actually start MCLK and SCLK */
2125 	radeon_pm_start_mclk_sclk(rinfo);
2126 
2127 	/* Full reset sdrams, this also re-inits the MDLL */
2128 	radeon_pm_full_reset_sdram(rinfo);
2129 
2130 	/* Fill palettes */
2131 	OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) | 0x20);
2132 	for (i=0; i<256; i++)
2133 		OUTREG(PALETTE_30_DATA, 0x15555555);
2134 	OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) & ~20);
2135 	udelay(20);
2136 	for (i=0; i<256; i++)
2137 		OUTREG(PALETTE_30_DATA, 0x15555555);
2138 
2139 	OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) & ~0x20);
2140 	mdelay(3);
2141 
2142 	/* Restore TV stuff, make sure TV DAC is down */
2143 	OUTREG(TV_MASTER_CNTL, rinfo->save_regs[88]);
2144 	OUTREG(TV_DAC_CNTL, rinfo->save_regs[13] | 0x07000000);
2145 
2146 	/* Restore GPIOS. MacOS does some magic here with one of the GPIO bits,
2147 	 * possibly related to the weird PLL related workarounds and to the
2148 	 * fact that CLK_PIN_CNTL is tweaked in ways I don't fully understand,
2149 	 * but we keep things the simple way here
2150 	 */
2151 	OUTREG(GPIOPAD_A, rinfo->save_regs[19]);
2152 	OUTREG(GPIOPAD_EN, rinfo->save_regs[20]);
2153 	OUTREG(GPIOPAD_MASK, rinfo->save_regs[21]);
2154 
2155 	/* Now do things with SCLK_MORE_CNTL. Force bits are already set, copy
2156 	 * high bits from backup
2157 	 */
2158 	tmp = INPLL(pllSCLK_MORE_CNTL) & 0x0000ffff;
2159 	tmp |= rinfo->save_regs[34] & 0xffff0000;
2160 	tmp |= SCLK_MORE_CNTL__FORCE_DISPREGS;
2161 	OUTPLL(pllSCLK_MORE_CNTL, tmp);
2162 
2163 	tmp = INPLL(pllSCLK_MORE_CNTL) & 0x0000ffff;
2164 	tmp |= rinfo->save_regs[34] & 0xffff0000;
2165 	tmp |= SCLK_MORE_CNTL__FORCE_DISPREGS;
2166 	OUTPLL(pllSCLK_MORE_CNTL, tmp);
2167 
2168 	OUTREG(LVDS_GEN_CNTL, rinfo->save_regs[11] &
2169 	       ~(LVDS_EN | LVDS_ON | LVDS_DIGON | LVDS_BLON | LVDS_BL_MOD_EN));
2170 	OUTREG(LVDS_GEN_CNTL, INREG(LVDS_GEN_CNTL) | LVDS_BLON);
2171 	OUTREG(LVDS_PLL_CNTL, (rinfo->save_regs[12] & ~0xf0000) | 0x20000);
2172 	mdelay(20);
2173 
2174 	/* write some stuff to the framebuffer... */
2175 	for (i = 0; i < 0x8000; ++i)
2176 		writeb(0, rinfo->fb_base + i);
2177 
2178 	OUTREG(0x2ec, 0x6332a020);
2179 	OUTPLL(pllSSPLL_REF_DIV, rinfo->save_regs[44] /*0x3f */);
2180 	OUTPLL(pllSSPLL_DIV_0, rinfo->save_regs[45] /*0x000081bb */);
2181 	tmp = INPLL(pllSSPLL_CNTL);
2182 	tmp &= ~2;
2183 	OUTPLL(pllSSPLL_CNTL, tmp);
2184 	mdelay(6);
2185 	tmp &= ~1;
2186 	OUTPLL(pllSSPLL_CNTL, tmp);
2187 	mdelay(5);
2188 	tmp |= 3;
2189 	OUTPLL(pllSSPLL_CNTL, tmp);
2190 	mdelay(5);
2191 
2192 	OUTPLL(pllSS_INT_CNTL, rinfo->save_regs[90] & ~3);/*0x0020300c*/
2193 	OUTREG(0x2ec, 0x6332a3f0);
2194 	mdelay(17);
2195 
2196 	OUTPLL(pllPPLL_REF_DIV, rinfo->pll.ref_div);
2197 	OUTPLL(pllPPLL_DIV_0, rinfo->save_regs[92]);
2198 
2199 	mdelay(40);
2200 	OUTREG(LVDS_GEN_CNTL, INREG(LVDS_GEN_CNTL) | LVDS_DIGON | LVDS_ON);
2201 	mdelay(40);
2202 
2203 	/* Restore a few more things */
2204 	OUTREG(GRPH_BUFFER_CNTL, rinfo->save_regs[94]);
2205 	OUTREG(GRPH2_BUFFER_CNTL, rinfo->save_regs[95]);
2206 
2207 	/* Restore PPLL, spread spectrum & LVDS */
2208 	radeon_pm_m10_disable_spread_spectrum(rinfo);
2209 	radeon_pm_restore_pixel_pll(rinfo);
2210 	radeon_pm_m10_enable_lvds_spread_spectrum(rinfo);
2211 }
2212 #endif
2213 #endif
2214 
2215 #if 0 /* Not ready yet */
2216 static void radeon_reinitialize_QW(struct radeonfb_info *rinfo)
2217 {
2218 	int i;
2219 	u32 tmp, tmp2;
2220 	u32 cko, cka, ckb;
2221 	u32 cgc, cec, c2gc;
2222 
2223 	OUTREG(MC_AGP_LOCATION, rinfo->save_regs[32]);
2224 	OUTREG(DISPLAY_BASE_ADDR, rinfo->save_regs[31]);
2225 	OUTREG(CRTC2_DISPLAY_BASE_ADDR, rinfo->save_regs[33]);
2226 	OUTREG(MC_FB_LOCATION, rinfo->save_regs[30]);
2227 	OUTREG(BUS_CNTL, rinfo->save_regs[36]);
2228 	OUTREG(RBBM_CNTL, rinfo->save_regs[39]);
2229 
2230 	INREG(PAD_CTLR_STRENGTH);
2231 	OUTREG(PAD_CTLR_STRENGTH, INREG(PAD_CTLR_STRENGTH) & ~0x10000);
2232 	for (i = 0; i < 65; ++i) {
2233 		mdelay(1);
2234 		INREG(PAD_CTLR_STRENGTH);
2235 	}
2236 
2237 	OUTREG(DISP_TEST_DEBUG_CNTL, INREG(DISP_TEST_DEBUG_CNTL) | 0x10000000);
2238 	OUTREG(OV0_FLAG_CNTRL, INREG(OV0_FLAG_CNTRL) | 0x100);
2239 	OUTREG(CRTC_GEN_CNTL, INREG(CRTC_GEN_CNTL));
2240 	OUTREG(DAC_CNTL, 0xff00410a);
2241 	OUTREG(CRTC2_GEN_CNTL, INREG(CRTC2_GEN_CNTL));
2242 	OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) | 0x4000);
2243 
2244 	OUTREG(SURFACE_CNTL, rinfo->save_regs[29]);
2245 	OUTREG(AGP_CNTL, rinfo->save_regs[16]);
2246 	OUTREG(HOST_PATH_CNTL, rinfo->save_regs[41]);
2247 	OUTREG(DISP_MISC_CNTL, rinfo->save_regs[9]);
2248 
2249 	OUTMC(rinfo, ixMC_CHP_IO_CNTL_A0, 0xf7bb4433);
2250 	OUTREG(MC_IND_INDEX, 0);
2251 	OUTMC(rinfo, ixMC_CHP_IO_CNTL_B0, 0xf7bb4433);
2252 	OUTREG(MC_IND_INDEX, 0);
2253 
2254 	OUTREG(CRTC_MORE_CNTL, INREG(CRTC_MORE_CNTL));
2255 
2256 	tmp = INPLL(pllVCLK_ECP_CNTL);
2257 	OUTPLL(pllVCLK_ECP_CNTL, tmp);
2258 	tmp = INPLL(pllPIXCLKS_CNTL);
2259 	OUTPLL(pllPIXCLKS_CNTL, tmp);
2260 
2261 	OUTPLL(MCLK_CNTL, 0xaa3f0000);
2262 	OUTPLL(SCLK_CNTL, 0xffff0000);
2263 	OUTPLL(pllMPLL_AUX_CNTL, 6);
2264 	OUTPLL(pllSPLL_AUX_CNTL, 1);
2265 	OUTPLL(MDLL_CKO, 0x9f009f);
2266 	OUTPLL(MDLL_RDCKA, 0x830083);
2267 	OUTPLL(pllMDLL_RDCKB, 0x830083);
2268 	OUTPLL(PPLL_CNTL, 0xa433);
2269 	OUTPLL(P2PLL_CNTL, 0xa433);
2270 	OUTPLL(MPLL_CNTL, 0x0400a403);
2271 	OUTPLL(SPLL_CNTL, 0x0400a433);
2272 
2273 	tmp = INPLL(M_SPLL_REF_FB_DIV);
2274 	OUTPLL(M_SPLL_REF_FB_DIV, tmp);
2275 	tmp = INPLL(M_SPLL_REF_FB_DIV);
2276 	OUTPLL(M_SPLL_REF_FB_DIV, tmp | 0xc);
2277 	INPLL(M_SPLL_REF_FB_DIV);
2278 
2279 	tmp = INPLL(MPLL_CNTL);
2280 	OUTREG8(CLOCK_CNTL_INDEX, MPLL_CNTL + PLL_WR_EN);
2281 	radeon_pll_errata_after_index(rinfo);
2282 	OUTREG8(CLOCK_CNTL_DATA + 1, (tmp >> 8) & 0xff);
2283 	radeon_pll_errata_after_data(rinfo);
2284 
2285 	tmp = INPLL(M_SPLL_REF_FB_DIV);
2286 	OUTPLL(M_SPLL_REF_FB_DIV, tmp | 0x5900);
2287 
2288 	tmp = INPLL(MPLL_CNTL);
2289 	OUTPLL(MPLL_CNTL, tmp & ~0x2);
2290 	mdelay(1);
2291 	tmp = INPLL(MPLL_CNTL);
2292 	OUTPLL(MPLL_CNTL, tmp & ~0x1);
2293 	mdelay(10);
2294 
2295 	OUTPLL(MCLK_CNTL, 0xaa3f1212);
2296 	mdelay(1);
2297 
2298 	INPLL(M_SPLL_REF_FB_DIV);
2299 	INPLL(MCLK_CNTL);
2300 	INPLL(M_SPLL_REF_FB_DIV);
2301 
2302 	tmp = INPLL(SPLL_CNTL);
2303 	OUTREG8(CLOCK_CNTL_INDEX, SPLL_CNTL + PLL_WR_EN);
2304 	radeon_pll_errata_after_index(rinfo);
2305 	OUTREG8(CLOCK_CNTL_DATA + 1, (tmp >> 8) & 0xff);
2306 	radeon_pll_errata_after_data(rinfo);
2307 
2308 	tmp = INPLL(M_SPLL_REF_FB_DIV);
2309 	OUTPLL(M_SPLL_REF_FB_DIV, tmp | 0x780000);
2310 
2311 	tmp = INPLL(SPLL_CNTL);
2312 	OUTPLL(SPLL_CNTL, tmp & ~0x1);
2313 	mdelay(1);
2314 	tmp = INPLL(SPLL_CNTL);
2315 	OUTPLL(SPLL_CNTL, tmp & ~0x2);
2316 	mdelay(10);
2317 
2318 	tmp = INPLL(SCLK_CNTL);
2319 	OUTPLL(SCLK_CNTL, tmp | 2);
2320 	mdelay(1);
2321 
2322 	cko = INPLL(pllMDLL_CKO);
2323 	cka = INPLL(pllMDLL_RDCKA);
2324 	ckb = INPLL(pllMDLL_RDCKB);
2325 
2326 	cko &= ~(MDLL_CKO__MCKOA_SLEEP | MDLL_CKO__MCKOB_SLEEP);
2327 	OUTPLL(pllMDLL_CKO, cko);
2328 	mdelay(1);
2329 	cko &= ~(MDLL_CKO__MCKOA_RESET | MDLL_CKO__MCKOB_RESET);
2330 	OUTPLL(pllMDLL_CKO, cko);
2331 	mdelay(5);
2332 
2333 	cka &= ~(MDLL_RDCKA__MRDCKA0_SLEEP | MDLL_RDCKA__MRDCKA1_SLEEP);
2334 	OUTPLL(pllMDLL_RDCKA, cka);
2335 	mdelay(1);
2336 	cka &= ~(MDLL_RDCKA__MRDCKA0_RESET | MDLL_RDCKA__MRDCKA1_RESET);
2337 	OUTPLL(pllMDLL_RDCKA, cka);
2338 	mdelay(5);
2339 
2340 	ckb &= ~(MDLL_RDCKB__MRDCKB0_SLEEP | MDLL_RDCKB__MRDCKB1_SLEEP);
2341 	OUTPLL(pllMDLL_RDCKB, ckb);
2342 	mdelay(1);
2343 	ckb &= ~(MDLL_RDCKB__MRDCKB0_RESET | MDLL_RDCKB__MRDCKB1_RESET);
2344 	OUTPLL(pllMDLL_RDCKB, ckb);
2345 	mdelay(5);
2346 
2347 	OUTMC(rinfo, ixMC_CHP_IO_CNTL_A1, 0x151550ff);
2348 	OUTREG(MC_IND_INDEX, 0);
2349 	OUTMC(rinfo, ixMC_CHP_IO_CNTL_B1, 0x151550ff);
2350 	OUTREG(MC_IND_INDEX, 0);
2351 	mdelay(1);
2352 	OUTMC(rinfo, ixMC_CHP_IO_CNTL_A1, 0x141550ff);
2353 	OUTREG(MC_IND_INDEX, 0);
2354 	OUTMC(rinfo, ixMC_CHP_IO_CNTL_B1, 0x141550ff);
2355 	OUTREG(MC_IND_INDEX, 0);
2356 	mdelay(1);
2357 
2358 	OUTPLL(pllHTOTAL_CNTL, 0);
2359 	OUTPLL(pllHTOTAL2_CNTL, 0);
2360 
2361 	OUTREG(MEM_CNTL, 0x29002901);
2362 	OUTREG(MEM_SDRAM_MODE_REG, 0x45320032);	/* XXX use save_regs[35]? */
2363 	OUTREG(EXT_MEM_CNTL, 0x1a394333);
2364 	OUTREG(MEM_IO_CNTL_A1, 0x0aac0aac);
2365 	OUTREG(MEM_INIT_LATENCY_TIMER, 0x34444444);
2366 	OUTREG(MEM_REFRESH_CNTL, 0x1f1f7218);	/* XXX or save_regs[42]? */
2367 	OUTREG(MC_DEBUG, 0);
2368 	OUTREG(MEM_IO_OE_CNTL, 0x04300430);
2369 
2370 	OUTMC(rinfo, ixMC_IMP_CNTL, 0x00f460d6);
2371 	OUTREG(MC_IND_INDEX, 0);
2372 	OUTMC(rinfo, ixMC_IMP_CNTL_0, 0x00009249);
2373 	OUTREG(MC_IND_INDEX, 0);
2374 
2375 	OUTREG(CNFG_MEMSIZE, rinfo->video_ram);
2376 
2377 	radeon_pm_full_reset_sdram(rinfo);
2378 
2379 	INREG(FP_GEN_CNTL);
2380 	OUTREG(TMDS_CNTL, 0x01000000);	/* XXX ? */
2381 	tmp = INREG(FP_GEN_CNTL);
2382 	tmp |= FP_CRTC_DONT_SHADOW_HEND | FP_CRTC_DONT_SHADOW_VPAR | 0x200;
2383 	OUTREG(FP_GEN_CNTL, tmp);
2384 
2385 	tmp = INREG(DISP_OUTPUT_CNTL);
2386 	tmp &= ~0x400;
2387 	OUTREG(DISP_OUTPUT_CNTL, tmp);
2388 
2389 	OUTPLL(CLK_PIN_CNTL, rinfo->save_regs[4]);
2390 	OUTPLL(CLK_PWRMGT_CNTL, rinfo->save_regs[1]);
2391 	OUTPLL(PLL_PWRMGT_CNTL, rinfo->save_regs[0]);
2392 
2393 	tmp = INPLL(MCLK_MISC);
2394 	tmp |= MCLK_MISC__MC_MCLK_DYN_ENABLE | MCLK_MISC__IO_MCLK_DYN_ENABLE;
2395 	OUTPLL(MCLK_MISC, tmp);
2396 
2397 	tmp = INPLL(SCLK_CNTL);
2398 	OUTPLL(SCLK_CNTL, tmp);
2399 
2400 	OUTREG(CRTC_MORE_CNTL, 0);
2401 	OUTREG8(CRTC_GEN_CNTL+1, 6);
2402 	OUTREG8(CRTC_GEN_CNTL+3, 1);
2403 	OUTREG(CRTC_PITCH, 32);
2404 
2405 	tmp = INPLL(VCLK_ECP_CNTL);
2406 	OUTPLL(VCLK_ECP_CNTL, tmp);
2407 
2408 	tmp = INPLL(PPLL_CNTL);
2409 	OUTPLL(PPLL_CNTL, tmp);
2410 
2411 	/* palette stuff and BIOS_1_SCRATCH... */
2412 
2413 	tmp = INREG(FP_GEN_CNTL);
2414 	tmp2 = INREG(TMDS_TRANSMITTER_CNTL);
2415 	tmp |= 2;
2416 	OUTREG(FP_GEN_CNTL, tmp);
2417 	mdelay(5);
2418 	OUTREG(FP_GEN_CNTL, tmp);
2419 	mdelay(5);
2420 	OUTREG(TMDS_TRANSMITTER_CNTL, tmp2);
2421 	OUTREG(CRTC_MORE_CNTL, 0);
2422 	mdelay(20);
2423 
2424 	tmp = INREG(CRTC_MORE_CNTL);
2425 	OUTREG(CRTC_MORE_CNTL, tmp);
2426 
2427 	cgc = INREG(CRTC_GEN_CNTL);
2428 	cec = INREG(CRTC_EXT_CNTL);
2429 	c2gc = INREG(CRTC2_GEN_CNTL);
2430 
2431 	OUTREG(CRTC_H_SYNC_STRT_WID, 0x008e0580);
2432 	OUTREG(CRTC_H_TOTAL_DISP, 0x009f00d2);
2433 	OUTREG8(CLOCK_CNTL_INDEX, HTOTAL_CNTL + PLL_WR_EN);
2434 	radeon_pll_errata_after_index(rinfo);
2435 	OUTREG8(CLOCK_CNTL_DATA, 0);
2436 	radeon_pll_errata_after_data(rinfo);
2437 	OUTREG(CRTC_V_SYNC_STRT_WID, 0x00830403);
2438 	OUTREG(CRTC_V_TOTAL_DISP, 0x03ff0429);
2439 	OUTREG(FP_CRTC_H_TOTAL_DISP, 0x009f0033);
2440 	OUTREG(FP_H_SYNC_STRT_WID, 0x008e0080);
2441 	OUTREG(CRT_CRTC_H_SYNC_STRT_WID, 0x008e0080);
2442 	OUTREG(FP_CRTC_V_TOTAL_DISP, 0x03ff002a);
2443 	OUTREG(FP_V_SYNC_STRT_WID, 0x00830004);
2444 	OUTREG(CRT_CRTC_V_SYNC_STRT_WID, 0x00830004);
2445 	OUTREG(FP_HORZ_VERT_ACTIVE, 0x009f03ff);
2446 	OUTREG(FP_HORZ_STRETCH, 0);
2447 	OUTREG(FP_VERT_STRETCH, 0);
2448 	OUTREG(OVR_CLR, 0);
2449 	OUTREG(OVR_WID_LEFT_RIGHT, 0);
2450 	OUTREG(OVR_WID_TOP_BOTTOM, 0);
2451 
2452 	tmp = INPLL(PPLL_REF_DIV);
2453 	tmp = (tmp & ~PPLL_REF_DIV_MASK) | rinfo->pll.ref_div;
2454 	OUTPLL(PPLL_REF_DIV, tmp);
2455 	INPLL(PPLL_REF_DIV);
2456 
2457 	OUTREG8(CLOCK_CNTL_INDEX, PPLL_CNTL + PLL_WR_EN);
2458 	radeon_pll_errata_after_index(rinfo);
2459 	OUTREG8(CLOCK_CNTL_DATA + 1, 0xbc);
2460 	radeon_pll_errata_after_data(rinfo);
2461 
2462 	tmp = INREG(CLOCK_CNTL_INDEX);
2463 	radeon_pll_errata_after_index(rinfo);
2464 	OUTREG(CLOCK_CNTL_INDEX, tmp & 0xff);
2465 	radeon_pll_errata_after_index(rinfo);
2466 	radeon_pll_errata_after_data(rinfo);
2467 
2468 	OUTPLL(PPLL_DIV_0, 0x48090);
2469 
2470 	tmp = INPLL(PPLL_CNTL);
2471 	OUTPLL(PPLL_CNTL, tmp & ~0x2);
2472 	mdelay(1);
2473 	tmp = INPLL(PPLL_CNTL);
2474 	OUTPLL(PPLL_CNTL, tmp & ~0x1);
2475 	mdelay(10);
2476 
2477 	tmp = INPLL(VCLK_ECP_CNTL);
2478 	OUTPLL(VCLK_ECP_CNTL, tmp | 3);
2479 	mdelay(1);
2480 
2481 	tmp = INPLL(VCLK_ECP_CNTL);
2482 	OUTPLL(VCLK_ECP_CNTL, tmp);
2483 
2484 	c2gc |= CRTC2_DISP_REQ_EN_B;
2485 	OUTREG(CRTC2_GEN_CNTL, c2gc);
2486 	cgc |= CRTC_EN;
2487 	OUTREG(CRTC_GEN_CNTL, cgc);
2488 	OUTREG(CRTC_EXT_CNTL, cec);
2489 	OUTREG(CRTC_PITCH, 0xa0);
2490 	OUTREG(CRTC_OFFSET, 0);
2491 	OUTREG(CRTC_OFFSET_CNTL, 0);
2492 
2493 	OUTREG(GRPH_BUFFER_CNTL, 0x20117c7c);
2494 	OUTREG(GRPH2_BUFFER_CNTL, 0x00205c5c);
2495 
2496 	tmp2 = INREG(FP_GEN_CNTL);
2497 	tmp = INREG(TMDS_TRANSMITTER_CNTL);
2498 	OUTREG(0x2a8, 0x0000061b);
2499 	tmp |= TMDS_PLL_EN;
2500 	OUTREG(TMDS_TRANSMITTER_CNTL, tmp);
2501 	mdelay(1);
2502 	tmp &= ~TMDS_PLLRST;
2503 	OUTREG(TMDS_TRANSMITTER_CNTL, tmp);
2504 	tmp2 &= ~2;
2505 	tmp2 |= FP_TMDS_EN;
2506 	OUTREG(FP_GEN_CNTL, tmp2);
2507 	mdelay(5);
2508 	tmp2 |= FP_FPON;
2509 	OUTREG(FP_GEN_CNTL, tmp2);
2510 
2511 	OUTREG(CUR_HORZ_VERT_OFF, CUR_LOCK | 1);
2512 	cgc = INREG(CRTC_GEN_CNTL);
2513 	OUTREG(CUR_HORZ_VERT_POSN, 0xbfff0fff);
2514 	cgc |= 0x10000;
2515 	OUTREG(CUR_OFFSET, 0);
2516 }
2517 #endif /* 0 */
2518 
2519 #endif /* CONFIG_PPC */
2520 
2521 static void radeonfb_whack_power_state(struct radeonfb_info *rinfo, pci_power_t state)
2522 {
2523 	u16 pwr_cmd;
2524 
2525 	for (;;) {
2526 		pci_read_config_word(rinfo->pdev,
2527 				     rinfo->pdev->pm_cap + PCI_PM_CTRL,
2528 				     &pwr_cmd);
2529 		if (pwr_cmd & state)
2530 			break;
2531 		pwr_cmd = (pwr_cmd & ~PCI_PM_CTRL_STATE_MASK) | state;
2532 		pci_write_config_word(rinfo->pdev,
2533 				      rinfo->pdev->pm_cap + PCI_PM_CTRL,
2534 				      pwr_cmd);
2535 		msleep(500);
2536 	}
2537 	rinfo->pdev->current_state = state;
2538 }
2539 
2540 static void radeon_set_suspend(struct radeonfb_info *rinfo, int suspend)
2541 {
2542 	u32 tmp;
2543 
2544 	if (!rinfo->pdev->pm_cap)
2545 		return;
2546 
2547 	/* Set the chip into appropriate suspend mode (we use D2,
2548 	 * D3 would require a compete re-initialization of the chip,
2549 	 * including PCI config registers, clocks, AGP conf, ...)
2550 	 */
2551 	if (suspend) {
2552 		printk(KERN_DEBUG "radeonfb (%s): switching to D2 state...\n",
2553 		       pci_name(rinfo->pdev));
2554 
2555 		/* Disable dynamic power management of clocks for the
2556 		 * duration of the suspend/resume process
2557 		 */
2558 		radeon_pm_disable_dynamic_mode(rinfo);
2559 
2560 		/* Save some registers */
2561 		radeon_pm_save_regs(rinfo, 0);
2562 
2563 		/* Prepare mobility chips for suspend.
2564 		 */
2565 		if (rinfo->is_mobility) {
2566 			/* Program V2CLK */
2567 			radeon_pm_program_v2clk(rinfo);
2568 
2569 			/* Disable IO PADs */
2570 			radeon_pm_disable_iopad(rinfo);
2571 
2572 			/* Set low current */
2573 			radeon_pm_low_current(rinfo);
2574 
2575 			/* Prepare chip for power management */
2576 			radeon_pm_setup_for_suspend(rinfo);
2577 
2578 			if (rinfo->family <= CHIP_FAMILY_RV280) {
2579 				/* Reset the MDLL */
2580 				/* because both INPLL and OUTPLL take the same
2581 				 * lock, that's why. */
2582 				tmp = INPLL( pllMDLL_CKO) | MDLL_CKO__MCKOA_RESET
2583 					| MDLL_CKO__MCKOB_RESET;
2584 				OUTPLL( pllMDLL_CKO, tmp );
2585 			}
2586 		}
2587 
2588 		/* Switch PCI power management to D2. */
2589 		pci_disable_device(rinfo->pdev);
2590 		pci_save_state(rinfo->pdev);
2591 		/* The chip seems to need us to whack the PM register
2592 		 * repeatedly until it sticks. We do that -prior- to
2593 		 * calling pci_set_power_state()
2594 		 */
2595 		radeonfb_whack_power_state(rinfo, PCI_D2);
2596 		__pci_complete_power_transition(rinfo->pdev, PCI_D2);
2597 	} else {
2598 		printk(KERN_DEBUG "radeonfb (%s): switching to D0 state...\n",
2599 		       pci_name(rinfo->pdev));
2600 
2601 		if (rinfo->family <= CHIP_FAMILY_RV250) {
2602 			/* Reset the SDRAM controller  */
2603 			radeon_pm_full_reset_sdram(rinfo);
2604 
2605 			/* Restore some registers */
2606 			radeon_pm_restore_regs(rinfo);
2607 		} else {
2608 			/* Restore registers first */
2609 			radeon_pm_restore_regs(rinfo);
2610 			/* init sdram controller */
2611 			radeon_pm_full_reset_sdram(rinfo);
2612 		}
2613 	}
2614 }
2615 
2616 int radeonfb_pci_suspend(struct pci_dev *pdev, pm_message_t mesg)
2617 {
2618         struct fb_info *info = pci_get_drvdata(pdev);
2619         struct radeonfb_info *rinfo = info->par;
2620 
2621 	if (mesg.event == pdev->dev.power.power_state.event)
2622 		return 0;
2623 
2624 	printk(KERN_DEBUG "radeonfb (%s): suspending for event: %d...\n",
2625 	       pci_name(pdev), mesg.event);
2626 
2627 	/* For suspend-to-disk, we cheat here. We don't suspend anything and
2628 	 * let fbcon continue drawing until we are all set. That shouldn't
2629 	 * really cause any problem at this point, provided that the wakeup
2630 	 * code knows that any state in memory may not match the HW
2631 	 */
2632 	switch (mesg.event) {
2633 	case PM_EVENT_FREEZE:		/* about to take snapshot */
2634 	case PM_EVENT_PRETHAW:		/* before restoring snapshot */
2635 		goto done;
2636 	}
2637 
2638 	console_lock();
2639 
2640 	fb_set_suspend(info, 1);
2641 
2642 	if (!(info->flags & FBINFO_HWACCEL_DISABLED)) {
2643 		/* Make sure engine is reset */
2644 		radeon_engine_idle();
2645 		radeonfb_engine_reset(rinfo);
2646 		radeon_engine_idle();
2647 	}
2648 
2649 	/* Blank display and LCD */
2650 	radeon_screen_blank(rinfo, FB_BLANK_POWERDOWN, 1);
2651 
2652 	/* Sleep */
2653 	rinfo->asleep = 1;
2654 	rinfo->lock_blank = 1;
2655 	del_timer_sync(&rinfo->lvds_timer);
2656 
2657 #ifdef CONFIG_PPC_PMAC
2658 	/* On powermac, we have hooks to properly suspend/resume AGP now,
2659 	 * use them here. We'll ultimately need some generic support here,
2660 	 * but the generic code isn't quite ready for that yet
2661 	 */
2662 	pmac_suspend_agp_for_card(pdev);
2663 #endif /* CONFIG_PPC_PMAC */
2664 
2665 	/* It's unclear whether or when the generic code will do that, so let's
2666 	 * do it ourselves. We save state before we do any power management
2667 	 */
2668 	pci_save_state(pdev);
2669 
2670 	/* If we support wakeup from poweroff, we save all regs we can including cfg
2671 	 * space
2672 	 */
2673 	if (rinfo->pm_mode & radeon_pm_off) {
2674 		/* Always disable dynamic clocks or weird things are happening when
2675 		 * the chip goes off (basically the panel doesn't shut down properly
2676 		 * and we crash on wakeup),
2677 		 * also, we want the saved regs context to have no dynamic clocks in
2678 		 * it, we'll restore the dynamic clocks state on wakeup
2679 		 */
2680 		radeon_pm_disable_dynamic_mode(rinfo);
2681 		msleep(50);
2682 		radeon_pm_save_regs(rinfo, 1);
2683 
2684 		if (rinfo->is_mobility && !(rinfo->pm_mode & radeon_pm_d2)) {
2685 			/* Switch off LVDS interface */
2686 			usleep_range(1000, 2000);
2687 			OUTREG(LVDS_GEN_CNTL, INREG(LVDS_GEN_CNTL) & ~(LVDS_BL_MOD_EN));
2688 			usleep_range(1000, 2000);
2689 			OUTREG(LVDS_GEN_CNTL, INREG(LVDS_GEN_CNTL) & ~(LVDS_EN | LVDS_ON));
2690 			OUTREG(LVDS_PLL_CNTL, (INREG(LVDS_PLL_CNTL) & ~30000) | 0x20000);
2691 			msleep(20);
2692 			OUTREG(LVDS_GEN_CNTL, INREG(LVDS_GEN_CNTL) & ~(LVDS_DIGON));
2693 		}
2694 		pci_disable_device(pdev);
2695 	}
2696 	/* If we support D2, we go to it (should be fixed later with a flag forcing
2697 	 * D3 only for some laptops)
2698 	 */
2699 	if (rinfo->pm_mode & radeon_pm_d2)
2700 		radeon_set_suspend(rinfo, 1);
2701 
2702 	console_unlock();
2703 
2704  done:
2705 	pdev->dev.power.power_state = mesg;
2706 
2707 	return 0;
2708 }
2709 
2710 static int radeon_check_power_loss(struct radeonfb_info *rinfo)
2711 {
2712 	return rinfo->save_regs[4] != INPLL(CLK_PIN_CNTL) ||
2713 	       rinfo->save_regs[2] != INPLL(MCLK_CNTL) ||
2714 	       rinfo->save_regs[3] != INPLL(SCLK_CNTL);
2715 }
2716 
2717 int radeonfb_pci_resume(struct pci_dev *pdev)
2718 {
2719         struct fb_info *info = pci_get_drvdata(pdev);
2720         struct radeonfb_info *rinfo = info->par;
2721 	int rc = 0;
2722 
2723 	if (pdev->dev.power.power_state.event == PM_EVENT_ON)
2724 		return 0;
2725 
2726 	if (rinfo->no_schedule) {
2727 		if (!console_trylock())
2728 			return 0;
2729 	} else
2730 		console_lock();
2731 
2732 	printk(KERN_DEBUG "radeonfb (%s): resuming from state: %d...\n",
2733 	       pci_name(pdev), pdev->dev.power.power_state.event);
2734 
2735 	/* PCI state will have been restored by the core, so
2736 	 * we should be in D0 now with our config space fully
2737 	 * restored
2738 	 */
2739 	if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
2740 		/* Wakeup chip */
2741 		if ((rinfo->pm_mode & radeon_pm_off) && radeon_check_power_loss(rinfo)) {
2742 			if (rinfo->reinit_func != NULL)
2743 				rinfo->reinit_func(rinfo);
2744 			else {
2745 				printk(KERN_ERR "radeonfb (%s): can't resume radeon from"
2746 				       " D3 cold, need softboot !", pci_name(pdev));
2747 				rc = -EIO;
2748 				goto bail;
2749 			}
2750 		}
2751 		/* If we support D2, try to resume... we should check what was our
2752 		 * state though... (were we really in D2 state ?). Right now, this code
2753 		 * is only enable on Macs so it's fine.
2754 		 */
2755 		else if (rinfo->pm_mode & radeon_pm_d2)
2756 			radeon_set_suspend(rinfo, 0);
2757 
2758 		rinfo->asleep = 0;
2759 	} else
2760 		radeon_engine_idle();
2761 
2762 	/* Restore display & engine */
2763 	radeon_write_mode (rinfo, &rinfo->state, 1);
2764 	if (!(info->flags & FBINFO_HWACCEL_DISABLED))
2765 		radeonfb_engine_init (rinfo);
2766 
2767 	fb_pan_display(info, &info->var);
2768 	fb_set_cmap(&info->cmap, info);
2769 
2770 	/* Refresh */
2771 	fb_set_suspend(info, 0);
2772 
2773 	/* Unblank */
2774 	rinfo->lock_blank = 0;
2775 	radeon_screen_blank(rinfo, FB_BLANK_UNBLANK, 1);
2776 
2777 #ifdef CONFIG_PPC_PMAC
2778 	/* On powermac, we have hooks to properly suspend/resume AGP now,
2779 	 * use them here. We'll ultimately need some generic support here,
2780 	 * but the generic code isn't quite ready for that yet
2781 	 */
2782 	pmac_resume_agp_for_card(pdev);
2783 #endif /* CONFIG_PPC_PMAC */
2784 
2785 
2786 	/* Check status of dynclk */
2787 	if (rinfo->dynclk == 1)
2788 		radeon_pm_enable_dynamic_mode(rinfo);
2789 	else if (rinfo->dynclk == 0)
2790 		radeon_pm_disable_dynamic_mode(rinfo);
2791 
2792 	pdev->dev.power.power_state = PMSG_ON;
2793 
2794  bail:
2795 	console_unlock();
2796 
2797 	return rc;
2798 }
2799 
2800 #ifdef CONFIG_PPC__disabled
2801 static void radeonfb_early_resume(void *data)
2802 {
2803         struct radeonfb_info *rinfo = data;
2804 
2805 	rinfo->no_schedule = 1;
2806 	pci_restore_state(rinfo->pdev);
2807 	radeonfb_pci_resume(rinfo->pdev);
2808 	rinfo->no_schedule = 0;
2809 }
2810 #endif /* CONFIG_PPC */
2811 
2812 #endif /* CONFIG_PM */
2813 
2814 void radeonfb_pm_init(struct radeonfb_info *rinfo, int dynclk, int ignore_devlist, int force_sleep)
2815 {
2816 	/* Enable/Disable dynamic clocks: TODO add sysfs access */
2817 	if (rinfo->family == CHIP_FAMILY_RS480)
2818 		rinfo->dynclk = -1;
2819 	else
2820 		rinfo->dynclk = dynclk;
2821 
2822 	if (rinfo->dynclk == 1) {
2823 		radeon_pm_enable_dynamic_mode(rinfo);
2824 		printk("radeonfb: Dynamic Clock Power Management enabled\n");
2825 	} else if (rinfo->dynclk == 0) {
2826 		radeon_pm_disable_dynamic_mode(rinfo);
2827 		printk("radeonfb: Dynamic Clock Power Management disabled\n");
2828 	}
2829 
2830 #if defined(CONFIG_PM)
2831 #if defined(CONFIG_PPC_PMAC)
2832 	/* Check if we can power manage on suspend/resume. We can do
2833 	 * D2 on M6, M7 and M9, and we can resume from D3 cold a few other
2834 	 * "Mac" cards, but that's all. We need more infos about what the
2835 	 * BIOS does tho. Right now, all this PM stuff is pmac-only for that
2836 	 * reason. --BenH
2837 	 */
2838 	if (machine_is(powermac) && rinfo->of_node) {
2839 		if (rinfo->is_mobility && rinfo->pdev->pm_cap &&
2840 		    rinfo->family <= CHIP_FAMILY_RV250)
2841 			rinfo->pm_mode |= radeon_pm_d2;
2842 
2843 		/* We can restart Jasper (M10 chip in albooks), BlueStone (7500 chip
2844 		 * in some desktop G4s), Via (M9+ chip on iBook G4) and
2845 		 * Snowy (M11 chip on iBook G4 manufactured after July 2005)
2846 		 */
2847 		if (of_node_name_eq(rinfo->of_node, "ATY,JasperParent") ||
2848 		    of_node_name_eq(rinfo->of_node, "ATY,SnowyParent")) {
2849 			rinfo->reinit_func = radeon_reinitialize_M10;
2850 			rinfo->pm_mode |= radeon_pm_off;
2851 		}
2852 #if 0 /* Not ready yet */
2853 		if (!strcmp(rinfo->of_node->name, "ATY,BlueStoneParent")) {
2854 			rinfo->reinit_func = radeon_reinitialize_QW;
2855 			rinfo->pm_mode |= radeon_pm_off;
2856 		}
2857 #endif
2858 		if (of_node_name_eq(rinfo->of_node, "ATY,ViaParent")) {
2859 			rinfo->reinit_func = radeon_reinitialize_M9P;
2860 			rinfo->pm_mode |= radeon_pm_off;
2861 		}
2862 
2863 		/* If any of the above is set, we assume the machine can sleep/resume.
2864 		 * It's a bit of a "shortcut" but will work fine. Ideally, we need infos
2865 		 * from the platform about what happens to the chip...
2866 		 * Now we tell the platform about our capability
2867 		 */
2868 		if (rinfo->pm_mode != radeon_pm_none) {
2869 			pmac_call_feature(PMAC_FTR_DEVICE_CAN_WAKE, rinfo->of_node, 0, 1);
2870 #if 0 /* Disable the early video resume hack for now as it's causing problems, among
2871        * others we now rely on the PCI core restoring the config space for us, which
2872        * isn't the case with that hack, and that code path causes various things to
2873        * be called with interrupts off while they shouldn't. I'm leaving the code in
2874        * as it can be useful for debugging purposes
2875        */
2876 			pmac_set_early_video_resume(radeonfb_early_resume, rinfo);
2877 #endif
2878 		}
2879 
2880 #if 0
2881 		/* Power down TV DAC, that saves a significant amount of power,
2882 		 * we'll have something better once we actually have some TVOut
2883 		 * support
2884 		 */
2885 		OUTREG(TV_DAC_CNTL, INREG(TV_DAC_CNTL) | 0x07000000);
2886 #endif
2887 	}
2888 #endif /* defined(CONFIG_PPC_PMAC) */
2889 #endif /* defined(CONFIG_PM) */
2890 
2891 	if (ignore_devlist)
2892 		printk(KERN_DEBUG
2893 		       "radeonfb: skipping test for device workarounds\n");
2894 	else
2895 		radeon_apply_workarounds(rinfo);
2896 
2897 	if (force_sleep) {
2898 		printk(KERN_DEBUG
2899 		       "radeonfb: forcefully enabling D2 sleep mode\n");
2900 		rinfo->pm_mode |= radeon_pm_d2;
2901 	}
2902 }
2903 
2904 void radeonfb_pm_exit(struct radeonfb_info *rinfo)
2905 {
2906 #if defined(CONFIG_PM) && defined(CONFIG_PPC_PMAC)
2907 	if (rinfo->pm_mode != radeon_pm_none)
2908 		pmac_set_early_video_resume(NULL, NULL);
2909 #endif
2910 }
2911